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Kamil Koniecznyherbertx
Kamil Konieczny
authored and
herbertx
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crypto: s5p-sss - Change spaces to tabs
Change #define lines to use tabs consistently. Acked-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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‎drivers/crypto/s5p-sss.c

Lines changed: 95 additions & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -30,121 +30,121 @@
3030
#include <crypto/algapi.h>
3131
#include <crypto/scatterwalk.h>
3232

33-
#define _SBF(s, v) ((v) << (s))
33+
#define _SBF(s, v) ((v) << (s))
3434

3535
/* Feed control registers */
36-
#define SSS_REG_FCINTSTAT 0x0000
37-
#define SSS_FCINTSTAT_BRDMAINT BIT(3)
38-
#define SSS_FCINTSTAT_BTDMAINT BIT(2)
39-
#define SSS_FCINTSTAT_HRDMAINT BIT(1)
40-
#define SSS_FCINTSTAT_PKDMAINT BIT(0)
41-
42-
#define SSS_REG_FCINTENSET 0x0004
43-
#define SSS_FCINTENSET_BRDMAINTENSET BIT(3)
44-
#define SSS_FCINTENSET_BTDMAINTENSET BIT(2)
45-
#define SSS_FCINTENSET_HRDMAINTENSET BIT(1)
46-
#define SSS_FCINTENSET_PKDMAINTENSET BIT(0)
47-
48-
#define SSS_REG_FCINTENCLR 0x0008
49-
#define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3)
50-
#define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2)
51-
#define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1)
52-
#define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0)
53-
54-
#define SSS_REG_FCINTPEND 0x000C
55-
#define SSS_FCINTPEND_BRDMAINTP BIT(3)
56-
#define SSS_FCINTPEND_BTDMAINTP BIT(2)
57-
#define SSS_FCINTPEND_HRDMAINTP BIT(1)
58-
#define SSS_FCINTPEND_PKDMAINTP BIT(0)
59-
60-
#define SSS_REG_FCFIFOSTAT 0x0010
61-
#define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7)
62-
#define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6)
63-
#define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5)
64-
#define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4)
65-
#define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3)
66-
#define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2)
67-
#define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1)
68-
#define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0)
69-
70-
#define SSS_REG_FCFIFOCTRL 0x0014
71-
#define SSS_FCFIFOCTRL_DESSEL BIT(2)
72-
#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)
73-
#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)
74-
#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)
75-
76-
#define SSS_REG_FCBRDMAS 0x0020
77-
#define SSS_REG_FCBRDMAL 0x0024
78-
#define SSS_REG_FCBRDMAC 0x0028
79-
#define SSS_FCBRDMAC_BYTESWAP BIT(1)
80-
#define SSS_FCBRDMAC_FLUSH BIT(0)
81-
82-
#define SSS_REG_FCBTDMAS 0x0030
83-
#define SSS_REG_FCBTDMAL 0x0034
84-
#define SSS_REG_FCBTDMAC 0x0038
85-
#define SSS_FCBTDMAC_BYTESWAP BIT(1)
86-
#define SSS_FCBTDMAC_FLUSH BIT(0)
87-
88-
#define SSS_REG_FCHRDMAS 0x0040
89-
#define SSS_REG_FCHRDMAL 0x0044
90-
#define SSS_REG_FCHRDMAC 0x0048
91-
#define SSS_FCHRDMAC_BYTESWAP BIT(1)
92-
#define SSS_FCHRDMAC_FLUSH BIT(0)
93-
94-
#define SSS_REG_FCPKDMAS 0x0050
95-
#define SSS_REG_FCPKDMAL 0x0054
96-
#define SSS_REG_FCPKDMAC 0x0058
97-
#define SSS_FCPKDMAC_BYTESWAP BIT(3)
98-
#define SSS_FCPKDMAC_DESCEND BIT(2)
99-
#define SSS_FCPKDMAC_TRANSMIT BIT(1)
100-
#define SSS_FCPKDMAC_FLUSH BIT(0)
101-
102-
#define SSS_REG_FCPKDMAO 0x005C
36+
#define SSS_REG_FCINTSTAT 0x0000
37+
#define SSS_FCINTSTAT_BRDMAINT BIT(3)
38+
#define SSS_FCINTSTAT_BTDMAINT BIT(2)
39+
#define SSS_FCINTSTAT_HRDMAINT BIT(1)
40+
#define SSS_FCINTSTAT_PKDMAINT BIT(0)
41+
42+
#define SSS_REG_FCINTENSET 0x0004
43+
#define SSS_FCINTENSET_BRDMAINTENSET BIT(3)
44+
#define SSS_FCINTENSET_BTDMAINTENSET BIT(2)
45+
#define SSS_FCINTENSET_HRDMAINTENSET BIT(1)
46+
#define SSS_FCINTENSET_PKDMAINTENSET BIT(0)
47+
48+
#define SSS_REG_FCINTENCLR 0x0008
49+
#define SSS_FCINTENCLR_BRDMAINTENCLR BIT(3)
50+
#define SSS_FCINTENCLR_BTDMAINTENCLR BIT(2)
51+
#define SSS_FCINTENCLR_HRDMAINTENCLR BIT(1)
52+
#define SSS_FCINTENCLR_PKDMAINTENCLR BIT(0)
53+
54+
#define SSS_REG_FCINTPEND 0x000C
55+
#define SSS_FCINTPEND_BRDMAINTP BIT(3)
56+
#define SSS_FCINTPEND_BTDMAINTP BIT(2)
57+
#define SSS_FCINTPEND_HRDMAINTP BIT(1)
58+
#define SSS_FCINTPEND_PKDMAINTP BIT(0)
59+
60+
#define SSS_REG_FCFIFOSTAT 0x0010
61+
#define SSS_FCFIFOSTAT_BRFIFOFUL BIT(7)
62+
#define SSS_FCFIFOSTAT_BRFIFOEMP BIT(6)
63+
#define SSS_FCFIFOSTAT_BTFIFOFUL BIT(5)
64+
#define SSS_FCFIFOSTAT_BTFIFOEMP BIT(4)
65+
#define SSS_FCFIFOSTAT_HRFIFOFUL BIT(3)
66+
#define SSS_FCFIFOSTAT_HRFIFOEMP BIT(2)
67+
#define SSS_FCFIFOSTAT_PKFIFOFUL BIT(1)
68+
#define SSS_FCFIFOSTAT_PKFIFOEMP BIT(0)
69+
70+
#define SSS_REG_FCFIFOCTRL 0x0014
71+
#define SSS_FCFIFOCTRL_DESSEL BIT(2)
72+
#define SSS_HASHIN_INDEPENDENT _SBF(0, 0x00)
73+
#define SSS_HASHIN_CIPHER_INPUT _SBF(0, 0x01)
74+
#define SSS_HASHIN_CIPHER_OUTPUT _SBF(0, 0x02)
75+
76+
#define SSS_REG_FCBRDMAS 0x0020
77+
#define SSS_REG_FCBRDMAL 0x0024
78+
#define SSS_REG_FCBRDMAC 0x0028
79+
#define SSS_FCBRDMAC_BYTESWAP BIT(1)
80+
#define SSS_FCBRDMAC_FLUSH BIT(0)
81+
82+
#define SSS_REG_FCBTDMAS 0x0030
83+
#define SSS_REG_FCBTDMAL 0x0034
84+
#define SSS_REG_FCBTDMAC 0x0038
85+
#define SSS_FCBTDMAC_BYTESWAP BIT(1)
86+
#define SSS_FCBTDMAC_FLUSH BIT(0)
87+
88+
#define SSS_REG_FCHRDMAS 0x0040
89+
#define SSS_REG_FCHRDMAL 0x0044
90+
#define SSS_REG_FCHRDMAC 0x0048
91+
#define SSS_FCHRDMAC_BYTESWAP BIT(1)
92+
#define SSS_FCHRDMAC_FLUSH BIT(0)
93+
94+
#define SSS_REG_FCPKDMAS 0x0050
95+
#define SSS_REG_FCPKDMAL 0x0054
96+
#define SSS_REG_FCPKDMAC 0x0058
97+
#define SSS_FCPKDMAC_BYTESWAP BIT(3)
98+
#define SSS_FCPKDMAC_DESCEND BIT(2)
99+
#define SSS_FCPKDMAC_TRANSMIT BIT(1)
100+
#define SSS_FCPKDMAC_FLUSH BIT(0)
101+
102+
#define SSS_REG_FCPKDMAO 0x005C
103103

104104
/* AES registers */
105105
#define SSS_REG_AES_CONTROL 0x00
106-
#define SSS_AES_BYTESWAP_DI BIT(11)
107-
#define SSS_AES_BYTESWAP_DO BIT(10)
108-
#define SSS_AES_BYTESWAP_IV BIT(9)
109-
#define SSS_AES_BYTESWAP_CNT BIT(8)
110-
#define SSS_AES_BYTESWAP_KEY BIT(7)
111-
#define SSS_AES_KEY_CHANGE_MODE BIT(6)
112-
#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)
113-
#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)
114-
#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)
115-
#define SSS_AES_FIFO_MODE BIT(3)
116-
#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)
117-
#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)
118-
#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
119-
#define SSS_AES_MODE_DECRYPT BIT(0)
106+
#define SSS_AES_BYTESWAP_DI BIT(11)
107+
#define SSS_AES_BYTESWAP_DO BIT(10)
108+
#define SSS_AES_BYTESWAP_IV BIT(9)
109+
#define SSS_AES_BYTESWAP_CNT BIT(8)
110+
#define SSS_AES_BYTESWAP_KEY BIT(7)
111+
#define SSS_AES_KEY_CHANGE_MODE BIT(6)
112+
#define SSS_AES_KEY_SIZE_128 _SBF(4, 0x00)
113+
#define SSS_AES_KEY_SIZE_192 _SBF(4, 0x01)
114+
#define SSS_AES_KEY_SIZE_256 _SBF(4, 0x02)
115+
#define SSS_AES_FIFO_MODE BIT(3)
116+
#define SSS_AES_CHAIN_MODE_ECB _SBF(1, 0x00)
117+
#define SSS_AES_CHAIN_MODE_CBC _SBF(1, 0x01)
118+
#define SSS_AES_CHAIN_MODE_CTR _SBF(1, 0x02)
119+
#define SSS_AES_MODE_DECRYPT BIT(0)
120120

121121
#define SSS_REG_AES_STATUS 0x04
122-
#define SSS_AES_BUSY BIT(2)
123-
#define SSS_AES_INPUT_READY BIT(1)
124-
#define SSS_AES_OUTPUT_READY BIT(0)
122+
#define SSS_AES_BUSY BIT(2)
123+
#define SSS_AES_INPUT_READY BIT(1)
124+
#define SSS_AES_OUTPUT_READY BIT(0)
125125

126126
#define SSS_REG_AES_IN_DATA(s) (0x10 + (s << 2))
127127
#define SSS_REG_AES_OUT_DATA(s) (0x20 + (s << 2))
128128
#define SSS_REG_AES_IV_DATA(s) (0x30 + (s << 2))
129129
#define SSS_REG_AES_CNT_DATA(s) (0x40 + (s << 2))
130130
#define SSS_REG_AES_KEY_DATA(s) (0x80 + (s << 2))
131131

132-
#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
133-
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
134-
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
132+
#define SSS_REG(dev, reg) ((dev)->ioaddr + (SSS_REG_##reg))
133+
#define SSS_READ(dev, reg) __raw_readl(SSS_REG(dev, reg))
134+
#define SSS_WRITE(dev, reg, val) __raw_writel((val), SSS_REG(dev, reg))
135135

136-
#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
136+
#define SSS_AES_REG(dev, reg) ((dev)->aes_ioaddr + SSS_REG_##reg)
137137
#define SSS_AES_WRITE(dev, reg, val) __raw_writel((val), \
138138
SSS_AES_REG(dev, reg))
139139

140140
/* HW engine modes */
141-
#define FLAGS_AES_DECRYPT BIT(0)
142-
#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
143-
#define FLAGS_AES_CBC _SBF(1, 0x01)
144-
#define FLAGS_AES_CTR _SBF(1, 0x02)
141+
#define FLAGS_AES_DECRYPT BIT(0)
142+
#define FLAGS_AES_MODE_MASK _SBF(1, 0x03)
143+
#define FLAGS_AES_CBC _SBF(1, 0x01)
144+
#define FLAGS_AES_CTR _SBF(1, 0x02)
145145

146-
#define AES_KEY_LEN 16
147-
#define CRYPTO_QUEUE_LEN 1
146+
#define AES_KEY_LEN 16
147+
#define CRYPTO_QUEUE_LEN 1
148148

149149
/**
150150
* struct samsung_aes_variant - platform specific SSS driver data

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