clk: ingenic: Fix recalc_rate for clocks with fixed divider

pcercuei · amalon · commit e6cfa64375d3 · 2018-01-18T22:04:56.000Z
Previously, the clocks with a fixed divider would report their rate as being the same as the one of their parent, independently of the divider in use. This commit fixes this behaviour. This went unnoticed as neither the jz4740 nor the jz4780 CGU code have clocks with fixed dividers yet. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Maarten ter Huurne <maarten@treewalker.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18477/ Signed-off-by: James Hogan <jhogan@kernel.org>
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
@@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 		div *= clk_info->div.div;
 
 		rate /= div;
+	} else if (clk_info->type & CGU_CLK_FIXDIV) {
+		rate /= clk_info->fixdiv.div;
 	}
 
 	return rate;

Original file line number	Diff line number	Diff line change
`@@ -328,6 +328,8 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)`
`328`	`328`	`div *= clk_info->div.div;`
`329`	`329`
`330`	`330`	`rate /= div;`
	`331`	`+ } else if (clk_info->type & CGU_CLK_FIXDIV) {`
	`332`	`+ rate /= clk_info->fixdiv.div;`
`331`	`333`	`}`
`332`	`334`
`333`	`335`	`return rate;`