Skip to content

Commit e6e1869

Browse files
mmindmmind
committed
ARM: dts: rockchip: add rk3066/rk3188 power-domains
Add the power-domain nodes to both rk3066 and rk3188 including their clocks and qos connections. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
1 parent 3e712a0 commit e6e1869

File tree

2 files changed

+103
-0
lines changed

2 files changed

+103
-0
lines changed

‎arch/arm/boot/dts/rk3066a.dtsi

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include <dt-bindings/gpio/gpio.h>
88
#include <dt-bindings/pinctrl/rockchip.h>
99
#include <dt-bindings/clock/rk3066a-cru.h>
10+
#include <dt-bindings/power/rk3066-power.h>
1011
#include "rk3xxx.dtsi"
1112

1213
/ {
@@ -595,6 +596,7 @@
595596
"ppmmu2",
596597
"pp3",
597598
"ppmmu3";
599+
power-domains = <&power RK3066_PD_GPU>;
598600
};
599601

600602
&i2c0 {
@@ -643,6 +645,56 @@
643645
dma-names = "rx-tx";
644646
};
645647

648+
&pmu {
649+
power: power-controller {
650+
compatible = "rockchip,rk3066-power-controller";
651+
#power-domain-cells = <1>;
652+
#address-cells = <1>;
653+
#size-cells = <0>;
654+
655+
pd_vio@RK3066_PD_VIO {
656+
reg = <RK3066_PD_VIO>;
657+
clocks = <&cru ACLK_LCDC0>,
658+
<&cru ACLK_LCDC1>,
659+
<&cru DCLK_LCDC0>,
660+
<&cru DCLK_LCDC1>,
661+
<&cru HCLK_LCDC0>,
662+
<&cru HCLK_LCDC1>,
663+
<&cru SCLK_CIF1>,
664+
<&cru ACLK_CIF1>,
665+
<&cru HCLK_CIF1>,
666+
<&cru SCLK_CIF0>,
667+
<&cru ACLK_CIF0>,
668+
<&cru HCLK_CIF0>,
669+
<&cru ACLK_IPP>,
670+
<&cru HCLK_IPP>,
671+
<&cru ACLK_RGA>,
672+
<&cru HCLK_RGA>;
673+
pm_qos = <&qos_lcdc0>,
674+
<&qos_lcdc1>,
675+
<&qos_cif0>,
676+
<&qos_cif1>,
677+
<&qos_ipp>,
678+
<&qos_rga>;
679+
};
680+
681+
pd_video@RK3066_PD_VIDEO {
682+
reg = <RK3066_PD_VIDEO>;
683+
clocks = <&cru ACLK_VDPU>,
684+
<&cru ACLK_VEPU>,
685+
<&cru HCLK_VDPU>,
686+
<&cru HCLK_VEPU>;
687+
pm_qos = <&qos_vpu>;
688+
};
689+
690+
pd_gpu@RK3066_PD_GPU {
691+
reg = <RK3066_PD_GPU>;
692+
clocks = <&cru ACLK_GPU>;
693+
pm_qos = <&qos_gpu>;
694+
};
695+
};
696+
};
697+
646698
&pwm0 {
647699
pinctrl-names = "default";
648700
pinctrl-0 = <&pwm0_out>;

‎arch/arm/boot/dts/rk3188.dtsi

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
#include <dt-bindings/gpio/gpio.h>
88
#include <dt-bindings/pinctrl/rockchip.h>
99
#include <dt-bindings/clock/rk3188-cru.h>
10+
#include <dt-bindings/power/rk3188-power.h>
1011
#include "rk3xxx.dtsi"
1112

1213
/ {
@@ -80,6 +81,7 @@
8081
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
8182
clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
8283
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
84+
power-domains = <&power RK3188_PD_VIO>;
8385
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
8486
reset-names = "axi", "ahb", "dclk";
8587
status = "disabled";
@@ -96,6 +98,7 @@
9698
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
9799
clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
98100
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
101+
power-domains = <&power RK3188_PD_VIO>;
99102
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
100103
reset-names = "axi", "ahb", "dclk";
101104
status = "disabled";
@@ -620,6 +623,7 @@
620623
"ppmmu2",
621624
"pp3",
622625
"ppmmu3";
626+
power-domains = <&power RK3188_PD_GPU>;
623627
};
624628

625629
&i2c0 {
@@ -652,6 +656,53 @@
652656
pinctrl-0 = <&i2c4_xfer>;
653657
};
654658

659+
&pmu {
660+
power: power-controller {
661+
compatible = "rockchip,rk3188-power-controller";
662+
#power-domain-cells = <1>;
663+
#address-cells = <1>;
664+
#size-cells = <0>;
665+
666+
pd_vio@RK3188_PD_VIO {
667+
reg = <RK3188_PD_VIO>;
668+
clocks = <&cru ACLK_LCDC0>,
669+
<&cru ACLK_LCDC1>,
670+
<&cru DCLK_LCDC0>,
671+
<&cru DCLK_LCDC1>,
672+
<&cru HCLK_LCDC0>,
673+
<&cru HCLK_LCDC1>,
674+
<&cru SCLK_CIF0>,
675+
<&cru ACLK_CIF0>,
676+
<&cru HCLK_CIF0>,
677+
<&cru ACLK_IPP>,
678+
<&cru HCLK_IPP>,
679+
<&cru ACLK_RGA>,
680+
<&cru HCLK_RGA>;
681+
pm_qos = <&qos_lcdc0>,
682+
<&qos_lcdc1>,
683+
<&qos_cif0>,
684+
<&qos_cif1>,
685+
<&qos_ipp>,
686+
<&qos_rga>;
687+
};
688+
689+
pd_video@RK3188_PD_VIDEO {
690+
reg = <RK3188_PD_VIDEO>;
691+
clocks = <&cru ACLK_VDPU>,
692+
<&cru ACLK_VEPU>,
693+
<&cru HCLK_VDPU>,
694+
<&cru HCLK_VEPU>;
695+
pm_qos = <&qos_vpu>;
696+
};
697+
698+
pd_gpu@RK3188_PD_GPU {
699+
reg = <RK3188_PD_GPU>;
700+
clocks = <&cru ACLK_GPU>;
701+
pm_qos = <&qos_gpu>;
702+
};
703+
};
704+
};
705+
655706
&pwm0 {
656707
pinctrl-names = "default";
657708
pinctrl-0 = <&pwm0_out>;

0 commit comments

Comments
 (0)