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191 | 191 |
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192 | 192 | #include "ns2-clock.dtsi"
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193 | 193 |
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| 194 | + pdc0: iproc-pdc0@612c0000 { |
| 195 | + compatible = "brcm,iproc-pdc-mbox"; |
| 196 | + reg = <0x612c0000 0x445>; /* PDC FS0 regs */ |
| 197 | + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
| 198 | + #mbox-cells = <1>; |
| 199 | + brcm,rx-status-len = <32>; |
| 200 | + brcm,use-bcm-hdr; |
| 201 | + }; |
| 202 | + |
| 203 | + pdc1: iproc-pdc1@612e0000 { |
| 204 | + compatible = "brcm,iproc-pdc-mbox"; |
| 205 | + reg = <0x612e0000 0x445>; /* PDC FS1 regs */ |
| 206 | + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
| 207 | + #mbox-cells = <1>; |
| 208 | + brcm,rx-status-len = <32>; |
| 209 | + brcm,use-bcm-hdr; |
| 210 | + }; |
| 211 | + |
| 212 | + pdc2: iproc-pdc2@61300000 { |
| 213 | + compatible = "brcm,iproc-pdc-mbox"; |
| 214 | + reg = <0x61300000 0x445>; /* PDC FS2 regs */ |
| 215 | + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; |
| 216 | + #mbox-cells = <1>; |
| 217 | + brcm,rx-status-len = <32>; |
| 218 | + brcm,use-bcm-hdr; |
| 219 | + }; |
| 220 | + |
| 221 | + pdc3: iproc-pdc3@61320000 { |
| 222 | + compatible = "brcm,iproc-pdc-mbox"; |
| 223 | + reg = <0x61320000 0x445>; /* PDC FS3 regs */ |
| 224 | + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; |
| 225 | + #mbox-cells = <1>; |
| 226 | + brcm,rx-status-len = <32>; |
| 227 | + brcm,use-bcm-hdr; |
| 228 | + }; |
| 229 | + |
194 | 230 | dma0: dma@61360000 {
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195 | 231 | compatible = "arm,pl330", "arm,primecell";
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196 | 232 | reg = <0x61360000 0x1000>;
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