Skip to content

Commit e7aa6d8

Browse files
niejlinusw
niej
authored and
linusw
committed
gpio: zx: Add ZTE zx296702 GPIO support
Add ZTE zx296702 GPIO controller support Signed-off-by: Jun Nie <jun.nie@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
1 parent 24f743a commit e7aa6d8

File tree

3 files changed

+331
-0
lines changed

3 files changed

+331
-0
lines changed

‎drivers/gpio/Kconfig

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1003,6 +1003,12 @@ config GPIO_MC33880
10031003
SPI driver for Freescale MC33880 high-side/low-side switch.
10041004
This provides GPIO interface supporting inputs and outputs.
10051005

1006+
config GPIO_ZX
1007+
bool "ZTE ZX GPIO support"
1008+
select GPIOLIB_IRQCHIP
1009+
help
1010+
Say yes here to support the GPIO device on ZTE ZX SoCs.
1011+
10061012
endmenu
10071013

10081014
menu "USB GPIO expanders"

‎drivers/gpio/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -116,3 +116,4 @@ obj-$(CONFIG_GPIO_XLP) += gpio-xlp.o
116116
obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
117117
obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
118118
obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
119+
obj-$(CONFIG_GPIO_ZX) += gpio-zx.o

‎drivers/gpio/gpio-zx.c

Lines changed: 324 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,324 @@
1+
/*
2+
* Copyright (C) 2015 Linaro Ltd.
3+
*
4+
* This program is free software; you can redistribute it and/or modify
5+
* it under the terms of the GNU General Public License version 2 as
6+
* published by the Free Software Foundation.
7+
*/
8+
#include <linux/bitops.h>
9+
#include <linux/device.h>
10+
#include <linux/errno.h>
11+
#include <linux/gpio/driver.h>
12+
#include <linux/irqchip/chained_irq.h>
13+
#include <linux/module.h>
14+
#include <linux/of.h>
15+
#include <linux/pinctrl/consumer.h>
16+
#include <linux/platform_device.h>
17+
#include <linux/pm.h>
18+
#include <linux/slab.h>
19+
#include <linux/spinlock.h>
20+
21+
#define ZX_GPIO_DIR 0x00
22+
#define ZX_GPIO_IVE 0x04
23+
#define ZX_GPIO_IV 0x08
24+
#define ZX_GPIO_IEP 0x0C
25+
#define ZX_GPIO_IEN 0x10
26+
#define ZX_GPIO_DI 0x14
27+
#define ZX_GPIO_DO1 0x18
28+
#define ZX_GPIO_DO0 0x1C
29+
#define ZX_GPIO_DO 0x20
30+
31+
#define ZX_GPIO_IM 0x28
32+
#define ZX_GPIO_IE 0x2C
33+
34+
#define ZX_GPIO_MIS 0x30
35+
#define ZX_GPIO_IC 0x34
36+
37+
#define ZX_GPIO_NR 16
38+
39+
struct zx_gpio {
40+
spinlock_t lock;
41+
42+
void __iomem *base;
43+
struct gpio_chip gc;
44+
bool uses_pinctrl;
45+
};
46+
47+
static inline struct zx_gpio *to_zx(struct gpio_chip *gc)
48+
{
49+
return container_of(gc, struct zx_gpio, gc);
50+
}
51+
52+
static int zx_gpio_request(struct gpio_chip *gc, unsigned offset)
53+
{
54+
struct zx_gpio *chip = to_zx(gc);
55+
int gpio = gc->base + offset;
56+
57+
if (chip->uses_pinctrl)
58+
return pinctrl_request_gpio(gpio);
59+
return 0;
60+
}
61+
62+
static void zx_gpio_free(struct gpio_chip *gc, unsigned offset)
63+
{
64+
struct zx_gpio *chip = to_zx(gc);
65+
int gpio = gc->base + offset;
66+
67+
if (chip->uses_pinctrl)
68+
pinctrl_free_gpio(gpio);
69+
}
70+
71+
static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
72+
{
73+
struct zx_gpio *chip = to_zx(gc);
74+
unsigned long flags;
75+
u16 gpiodir;
76+
77+
if (offset >= gc->ngpio)
78+
return -EINVAL;
79+
80+
spin_lock_irqsave(&chip->lock, flags);
81+
gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
82+
gpiodir &= ~BIT(offset);
83+
writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
84+
spin_unlock_irqrestore(&chip->lock, flags);
85+
86+
return 0;
87+
}
88+
89+
static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
90+
int value)
91+
{
92+
struct zx_gpio *chip = to_zx(gc);
93+
unsigned long flags;
94+
u16 gpiodir;
95+
96+
if (offset >= gc->ngpio)
97+
return -EINVAL;
98+
99+
spin_lock_irqsave(&chip->lock, flags);
100+
gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
101+
gpiodir |= BIT(offset);
102+
writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
103+
104+
if (value)
105+
writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
106+
else
107+
writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
108+
spin_unlock_irqrestore(&chip->lock, flags);
109+
110+
return 0;
111+
}
112+
113+
static int zx_get_value(struct gpio_chip *gc, unsigned offset)
114+
{
115+
struct zx_gpio *chip = to_zx(gc);
116+
117+
return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
118+
}
119+
120+
static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
121+
{
122+
struct zx_gpio *chip = to_zx(gc);
123+
124+
if (value)
125+
writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
126+
else
127+
writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
128+
}
129+
130+
static int zx_irq_type(struct irq_data *d, unsigned trigger)
131+
{
132+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133+
struct zx_gpio *chip = to_zx(gc);
134+
int offset = irqd_to_hwirq(d);
135+
unsigned long flags;
136+
u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
137+
u16 bit = BIT(offset);
138+
139+
if (offset < 0 || offset >= ZX_GPIO_NR)
140+
return -EINVAL;
141+
142+
spin_lock_irqsave(&chip->lock, flags);
143+
144+
gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
145+
gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
146+
gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
147+
gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
148+
149+
if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
150+
gpiois |= bit;
151+
if (trigger & IRQ_TYPE_LEVEL_HIGH)
152+
gpioiev |= bit;
153+
else
154+
gpioiev &= ~bit;
155+
} else
156+
gpiois &= ~bit;
157+
158+
if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
159+
gpioi_epos |= bit;
160+
gpioi_eneg |= bit;
161+
} else {
162+
if (trigger & IRQ_TYPE_EDGE_RISING) {
163+
gpioi_epos |= bit;
164+
gpioi_eneg &= ~bit;
165+
} else if (trigger & IRQ_TYPE_EDGE_FALLING) {
166+
gpioi_eneg |= bit;
167+
gpioi_epos &= ~bit;
168+
}
169+
}
170+
171+
writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
172+
writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
173+
writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
174+
writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
175+
spin_unlock_irqrestore(&chip->lock, flags);
176+
177+
return 0;
178+
}
179+
180+
static void zx_irq_handler(unsigned irq, struct irq_desc *desc)
181+
{
182+
unsigned long pending;
183+
int offset;
184+
struct gpio_chip *gc = irq_desc_get_handler_data(desc);
185+
struct zx_gpio *chip = to_zx(gc);
186+
struct irq_chip *irqchip = irq_desc_get_chip(desc);
187+
188+
chained_irq_enter(irqchip, desc);
189+
190+
pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
191+
writew_relaxed(pending, chip->base + ZX_GPIO_IC);
192+
if (pending) {
193+
for_each_set_bit(offset, &pending, ZX_GPIO_NR)
194+
generic_handle_irq(irq_find_mapping(gc->irqdomain,
195+
offset));
196+
}
197+
198+
chained_irq_exit(irqchip, desc);
199+
}
200+
201+
static void zx_irq_mask(struct irq_data *d)
202+
{
203+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
204+
struct zx_gpio *chip = to_zx(gc);
205+
u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
206+
u16 gpioie;
207+
208+
spin_lock(&chip->lock);
209+
gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
210+
writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
211+
gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
212+
writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
213+
spin_unlock(&chip->lock);
214+
}
215+
216+
static void zx_irq_unmask(struct irq_data *d)
217+
{
218+
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
219+
struct zx_gpio *chip = to_zx(gc);
220+
u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
221+
u16 gpioie;
222+
223+
spin_lock(&chip->lock);
224+
gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
225+
writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
226+
gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
227+
writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
228+
spin_unlock(&chip->lock);
229+
}
230+
231+
static struct irq_chip zx_irqchip = {
232+
.name = "zx-gpio",
233+
.irq_mask = zx_irq_mask,
234+
.irq_unmask = zx_irq_unmask,
235+
.irq_set_type = zx_irq_type,
236+
};
237+
238+
static int zx_gpio_probe(struct platform_device *pdev)
239+
{
240+
struct device *dev = &pdev->dev;
241+
struct zx_gpio *chip;
242+
struct resource *res;
243+
int irq, id, ret;
244+
245+
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
246+
if (!chip)
247+
return -ENOMEM;
248+
249+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
250+
chip->base = devm_ioremap_resource(dev, res);
251+
if (IS_ERR(chip->base))
252+
return PTR_ERR(chip->base);
253+
254+
spin_lock_init(&chip->lock);
255+
if (of_property_read_bool(dev->of_node, "gpio-ranges"))
256+
chip->uses_pinctrl = true;
257+
258+
id = of_alias_get_id(dev->of_node, "gpio");
259+
chip->gc.request = zx_gpio_request;
260+
chip->gc.free = zx_gpio_free;
261+
chip->gc.direction_input = zx_direction_input;
262+
chip->gc.direction_output = zx_direction_output;
263+
chip->gc.get = zx_get_value;
264+
chip->gc.set = zx_set_value;
265+
chip->gc.base = ZX_GPIO_NR * id;
266+
chip->gc.ngpio = ZX_GPIO_NR;
267+
chip->gc.label = dev_name(dev);
268+
chip->gc.dev = dev;
269+
chip->gc.owner = THIS_MODULE;
270+
271+
ret = gpiochip_add(&chip->gc);
272+
if (ret)
273+
return ret;
274+
275+
/*
276+
* irq_chip support
277+
*/
278+
writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
279+
writew_relaxed(0, chip->base + ZX_GPIO_IE);
280+
irq = platform_get_irq(pdev, 0);
281+
if (irq < 0) {
282+
dev_err(dev, "invalid IRQ\n");
283+
gpiochip_remove(&chip->gc);
284+
return -ENODEV;
285+
}
286+
287+
ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
288+
0, handle_simple_irq,
289+
IRQ_TYPE_NONE);
290+
if (ret) {
291+
dev_err(dev, "could not add irqchip\n");
292+
gpiochip_remove(&chip->gc);
293+
return ret;
294+
}
295+
gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
296+
irq, zx_irq_handler);
297+
298+
platform_set_drvdata(pdev, chip);
299+
dev_info(dev, "ZX GPIO chip registered\n");
300+
301+
return 0;
302+
}
303+
304+
static const struct of_device_id zx_gpio_match[] = {
305+
{
306+
.compatible = "zte,zx296702-gpio",
307+
},
308+
{ },
309+
};
310+
MODULE_DEVICE_TABLE(of, zx_gpio_match);
311+
312+
static struct platform_driver zx_gpio_driver = {
313+
.probe = zx_gpio_probe,
314+
.driver = {
315+
.name = "zx_gpio",
316+
.of_match_table = of_match_ptr(zx_gpio_match),
317+
},
318+
};
319+
320+
module_platform_driver(zx_gpio_driver)
321+
322+
MODULE_AUTHOR("Jun Nie <jun.nie@linaro.org>");
323+
MODULE_DESCRIPTION("ZTE ZX296702 GPIO driver");
324+
MODULE_LICENSE("GPL");

0 commit comments

Comments
 (0)