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rodrigovividanvet
rodrigovivi
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danvet
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drm/i915: Added debugfs support for PSR Status
Adding support for PSR Status, PSR entry counter and performance counters. Heavily based on initial work from Shobhit. v2: Fix PSR Status Link bits by Paulo Zanoni. v3: Prefer seq_puts to seq_printf by Paulo Zanoni. v4: Fix identation by Paulo Zanoni. v5: Return earlier if it isn't Haswell in order to avoid reading non-existing registers - by Paulo Zanoni. CC: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Credits-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Shobhit Kumar <shobhit.kumar@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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‎drivers/gpu/drm/i915/i915_debugfs.c

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1545,6 +1545,100 @@ static int i915_llc(struct seq_file *m, void *data)
15451545
return 0;
15461546
}
15471547

1548+
static int i915_edp_psr_status(struct seq_file *m, void *data)
1549+
{
1550+
struct drm_info_node *node = m->private;
1551+
struct drm_device *dev = node->minor->dev;
1552+
struct drm_i915_private *dev_priv = dev->dev_private;
1553+
u32 psrctl, psrstat, psrperf;
1554+
1555+
if (!IS_HASWELL(dev)) {
1556+
seq_puts(m, "PSR not supported on this platform\n");
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return 0;
1558+
}
1559+
1560+
psrctl = I915_READ(EDP_PSR_CTL);
1561+
seq_printf(m, "PSR Enabled: %s\n",
1562+
yesno(psrctl & EDP_PSR_ENABLE));
1563+
1564+
psrstat = I915_READ(EDP_PSR_STATUS_CTL);
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1566+
seq_puts(m, "PSR Current State: ");
1567+
switch (psrstat & EDP_PSR_STATUS_STATE_MASK) {
1568+
case EDP_PSR_STATUS_STATE_IDLE:
1569+
seq_puts(m, "Reset state\n");
1570+
break;
1571+
case EDP_PSR_STATUS_STATE_SRDONACK:
1572+
seq_puts(m, "Wait for TG/Stream to send on frame of data after SRD conditions are met\n");
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break;
1574+
case EDP_PSR_STATUS_STATE_SRDENT:
1575+
seq_puts(m, "SRD entry\n");
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break;
1577+
case EDP_PSR_STATUS_STATE_BUFOFF:
1578+
seq_puts(m, "Wait for buffer turn off\n");
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break;
1580+
case EDP_PSR_STATUS_STATE_BUFON:
1581+
seq_puts(m, "Wait for buffer turn on\n");
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break;
1583+
case EDP_PSR_STATUS_STATE_AUXACK:
1584+
seq_puts(m, "Wait for AUX to acknowledge on SRD exit\n");
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break;
1586+
case EDP_PSR_STATUS_STATE_SRDOFFACK:
1587+
seq_puts(m, "Wait for TG/Stream to acknowledge the SRD VDM exit\n");
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break;
1589+
default:
1590+
seq_puts(m, "Unknown\n");
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break;
1592+
}
1593+
1594+
seq_puts(m, "Link Status: ");
1595+
switch (psrstat & EDP_PSR_STATUS_LINK_MASK) {
1596+
case EDP_PSR_STATUS_LINK_FULL_OFF:
1597+
seq_puts(m, "Link is fully off\n");
1598+
break;
1599+
case EDP_PSR_STATUS_LINK_FULL_ON:
1600+
seq_puts(m, "Link is fully on\n");
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break;
1602+
case EDP_PSR_STATUS_LINK_STANDBY:
1603+
seq_puts(m, "Link is in standby\n");
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break;
1605+
default:
1606+
seq_puts(m, "Unknown\n");
1607+
break;
1608+
}
1609+
1610+
seq_printf(m, "PSR Entry Count: %u\n",
1611+
psrstat >> EDP_PSR_STATUS_COUNT_SHIFT &
1612+
EDP_PSR_STATUS_COUNT_MASK);
1613+
1614+
seq_printf(m, "Max Sleep Timer Counter: %u\n",
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psrstat >> EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT &
1616+
EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK);
1617+
1618+
seq_printf(m, "Had AUX error: %s\n",
1619+
yesno(psrstat & EDP_PSR_STATUS_AUX_ERROR));
1620+
1621+
seq_printf(m, "Sending AUX: %s\n",
1622+
yesno(psrstat & EDP_PSR_STATUS_AUX_SENDING));
1623+
1624+
seq_printf(m, "Sending Idle: %s\n",
1625+
yesno(psrstat & EDP_PSR_STATUS_SENDING_IDLE));
1626+
1627+
seq_printf(m, "Sending TP2 TP3: %s\n",
1628+
yesno(psrstat & EDP_PSR_STATUS_SENDING_TP2_TP3));
1629+
1630+
seq_printf(m, "Sending TP1: %s\n",
1631+
yesno(psrstat & EDP_PSR_STATUS_SENDING_TP1));
1632+
1633+
seq_printf(m, "Idle Count: %u\n",
1634+
psrstat & EDP_PSR_STATUS_IDLE_MASK);
1635+
1636+
psrperf = (I915_READ(EDP_PSR_PERF_CNT)) & EDP_PSR_PERF_CNT_MASK;
1637+
seq_printf(m, "Performance Counter: %u\n", psrperf);
1638+
1639+
return 0;
1640+
}
1641+
15481642
static int
15491643
i915_wedged_get(void *data, u64 *val)
15501644
{
@@ -1977,6 +2071,7 @@ static struct drm_info_list i915_debugfs_list[] = {
19772071
{"i915_ppgtt_info", i915_ppgtt_info, 0},
19782072
{"i915_dpio", i915_dpio_info, 0},
19792073
{"i915_llc", i915_llc, 0},
2074+
{"i915_edp_psr_status", i915_edp_psr_status, 0},
19802075
};
19812076
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
19822077

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1814,6 +1814,30 @@
18141814

18151815
#define EDP_PSR_STATUS_CTL 0x64840
18161816
#define EDP_PSR_STATUS_STATE_MASK (7<<29)
1817+
#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
1818+
#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
1819+
#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
1820+
#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
1821+
#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
1822+
#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
1823+
#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
1824+
#define EDP_PSR_STATUS_LINK_MASK (3<<26)
1825+
#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
1826+
#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
1827+
#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
1828+
#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
1829+
#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
1830+
#define EDP_PSR_STATUS_COUNT_SHIFT 16
1831+
#define EDP_PSR_STATUS_COUNT_MASK 0xf
1832+
#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
1833+
#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
1834+
#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
1835+
#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
1836+
#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
1837+
#define EDP_PSR_STATUS_IDLE_MASK 0xf
1838+
1839+
#define EDP_PSR_PERF_CNT 0x64844
1840+
#define EDP_PSR_PERF_CNT_MASK 0xffffff
18171841

18181842
#define EDP_PSR_DEBUG_CTL 0x64860
18191843
#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)

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