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vsyrjaladanvet
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drm/i915: Engage the DP scramble reset for pipe C on CHV
To get stable CRCs from the DP CRC source we need to reset the scrambler for each frame. Enable the reset feature when grabbing CRCs for pipe C on CHV. Pipes A and B were already covered due sharing the code with VLV. We can safely extend PIPE_SCRAMBLE_RESET_MASK to deal with CHV since the extra bit was MBZ on the older platforms. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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+24
-6
lines changed

2 files changed

+24
-6
lines changed

drivers/gpu/drm/i915/i915_debugfs.c

Lines changed: 22 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3120,11 +3120,19 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
31203120
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
31213121

31223122
tmp |= DC_BALANCE_RESET_VLV;
3123-
if (pipe == PIPE_A)
3123+
switch (pipe) {
3124+
case PIPE_A:
31243125
tmp |= PIPE_A_SCRAMBLE_RESET;
3125-
else
3126+
break;
3127+
case PIPE_B:
31263128
tmp |= PIPE_B_SCRAMBLE_RESET;
3127-
3129+
break;
3130+
case PIPE_C:
3131+
tmp |= PIPE_C_SCRAMBLE_RESET;
3132+
break;
3133+
default:
3134+
return -EINVAL;
3135+
}
31283136
I915_WRITE(PORT_DFT2_G4X, tmp);
31293137
}
31303138

@@ -3213,10 +3221,19 @@ static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
32133221
struct drm_i915_private *dev_priv = dev->dev_private;
32143222
uint32_t tmp = I915_READ(PORT_DFT2_G4X);
32153223

3216-
if (pipe == PIPE_A)
3224+
switch (pipe) {
3225+
case PIPE_A:
32173226
tmp &= ~PIPE_A_SCRAMBLE_RESET;
3218-
else
3227+
break;
3228+
case PIPE_B:
32193229
tmp &= ~PIPE_B_SCRAMBLE_RESET;
3230+
break;
3231+
case PIPE_C:
3232+
tmp &= ~PIPE_C_SCRAMBLE_RESET;
3233+
break;
3234+
default:
3235+
return;
3236+
}
32203237
if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
32213238
tmp &= ~DC_BALANCE_RESET_VLV;
32223239
I915_WRITE(PORT_DFT2_G4X, tmp);

drivers/gpu/drm/i915/i915_reg.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2789,7 +2789,8 @@ enum punit_power_well {
27892789
#define DC_BALANCE_RESET (1 << 25)
27902790
#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
27912791
#define DC_BALANCE_RESET_VLV (1 << 31)
2792-
#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2792+
#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
2793+
#define PIPE_C_SCRAMBLE_RESET (1 << 14) /* chv */
27932794
#define PIPE_B_SCRAMBLE_RESET (1 << 1)
27942795
#define PIPE_A_SCRAMBLE_RESET (1 << 0)
27952796

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