Skip to content

Commit ee036df

Browse files
arndbarndb
committed
Merge tag 'bitmain-initial-soc-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain into arm/newsoc
Bitmain SoC changes for v5.1: - Document Bitmain BM1880 SoC bindings - Add ARCH_BITMAIN for supporting Bitmain SoC platforms - Add devicetree support for Bitmain BM1880 SoC - Add devicetree support for Sophon Edge board - Add MAINTAINERS entry for Bitmain SoC platform * tag 'bitmain-initial-soc-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/linux-bitmain: MAINTAINERS: Add entry for Bitmain SoC platform arm64: dts: bitmain: Add Sophon Egde board support arm64: dts: bitmain: Add BM1880 SoC support arm64: Add ARCH_BITMAIN platform dt-bindings: arm: Document Bitmain BM1880 SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents d139371 + 51d7d93 commit ee036df

File tree

7 files changed

+203
-0
lines changed

7 files changed

+203
-0
lines changed

‎Documentation/devicetree/bindings/arm/bitmain.yaml

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
# SPDX-License-Identifier: GPL-2.0
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/arm/bitmain.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Bitmain platform device tree bindings
8+
9+
maintainers:
10+
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11+
12+
properties:
13+
compatible:
14+
items:
15+
- enum:
16+
- bitmain,sophon-edge
17+
- const: bitmain,bm1880
18+
...

‎MAINTAINERS

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1372,6 +1372,13 @@ F: arch/arm/mach-aspeed/
13721372
F: arch/arm/boot/dts/aspeed-*
13731373
N: aspeed
13741374

1375+
ARM/BITMAIN ARCHITECTURE
1376+
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
1377+
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1378+
S: Maintained
1379+
F: arch/arm64/boot/dts/bitmain/
1380+
F: Documentation/devicetree/bindings/arm/bitmain.yaml
1381+
13751382
ARM/CALXEDA HIGHBANK ARCHITECTURE
13761383
M: Rob Herring <robh@kernel.org>
13771384
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

‎arch/arm64/Kconfig.platforms

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,11 @@ config ARCH_BERLIN
5252
help
5353
This enables support for Marvell Berlin SoC Family
5454

55+
config ARCH_BITMAIN
56+
bool "Bitmain SoC Platforms"
57+
help
58+
This enables support for the Bitmain SoC Family.
59+
5560
config ARCH_BRCMSTB
5661
bool "Broadcom Set-Top-Box SoCs"
5762
select BRCMSTB_L2_IRQ

‎arch/arm64/boot/dts/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ subdir-y += amd
77
subdir-y += amlogic
88
subdir-y += apm
99
subdir-y += arm
10+
subdir-y += bitmain
1011
subdir-y += broadcom
1112
subdir-y += cavium
1213
subdir-y += exynos

‎arch/arm64/boot/dts/bitmain/Makefile

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
# SPDX-License-Identifier: GPL-2.0+
2+
3+
dtb-$(CONFIG_ARCH_BITMAIN) += bm1880-sophon-edge.dtb

‎arch/arm64/boot/dts/bitmain/bm1880-sophon-edge.dts

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2+
/*
3+
* Copyright (c) 2019 Linaro Ltd.
4+
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5+
*/
6+
7+
/dts-v1/;
8+
9+
#include "bm1880.dtsi"
10+
11+
/ {
12+
compatible = "bitmain,sophon-edge", "bitmain,bm1880";
13+
model = "Sophon Edge";
14+
15+
aliases {
16+
serial0 = &uart0;
17+
serial1 = &uart2;
18+
serial2 = &uart1;
19+
};
20+
21+
chosen {
22+
stdout-path = "serial0:115200n8";
23+
};
24+
25+
memory@0 {
26+
device_type = "memory";
27+
reg = <0x1 0x00000000 0x0 0x40000000>; // 1GB
28+
};
29+
30+
uart_clk: uart-clk {
31+
compatible = "fixed-clock";
32+
clock-frequency = <500000000>;
33+
#clock-cells = <0>;
34+
};
35+
};
36+
37+
&uart0 {
38+
status = "okay";
39+
clocks = <&uart_clk>;
40+
};
41+
42+
&uart1 {
43+
status = "okay";
44+
clocks = <&uart_clk>;
45+
};
46+
47+
&uart2 {
48+
status = "okay";
49+
clocks = <&uart_clk>;
50+
};

‎arch/arm64/boot/dts/bitmain/bm1880.dtsi

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,119 @@
1+
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2+
/*
3+
* Copyright (c) 2019 Linaro Ltd.
4+
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
5+
*/
6+
7+
#include <dt-bindings/interrupt-controller/arm-gic.h>
8+
9+
/ {
10+
compatible = "bitmain,bm1880";
11+
interrupt-parent = <&gic>;
12+
#address-cells = <2>;
13+
#size-cells = <2>;
14+
15+
cpus {
16+
#address-cells = <1>;
17+
#size-cells = <0>;
18+
19+
cpu0: cpu@0 {
20+
device_type = "cpu";
21+
compatible = "arm,cortex-a53";
22+
reg = <0x0>;
23+
enable-method = "psci";
24+
};
25+
26+
cpu1: cpu@1 {
27+
device_type = "cpu";
28+
compatible = "arm,cortex-a53";
29+
reg = <0x1>;
30+
enable-method = "psci";
31+
};
32+
};
33+
34+
reserved-memory {
35+
#address-cells = <2>;
36+
#size-cells = <2>;
37+
ranges;
38+
39+
secmon@100000000 {
40+
reg = <0x1 0x00000000 0x0 0x20000>;
41+
no-map;
42+
};
43+
44+
jpu@130000000 {
45+
reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
46+
no-map;
47+
};
48+
49+
vpu@138000000 {
50+
reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
51+
no-map;
52+
};
53+
};
54+
55+
psci {
56+
compatible = "arm,psci-0.2";
57+
method = "smc";
58+
};
59+
60+
timer {
61+
compatible = "arm,armv8-timer";
62+
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
63+
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
64+
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
65+
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
66+
};
67+
68+
soc {
69+
compatible = "simple-bus";
70+
#address-cells = <2>;
71+
#size-cells = <2>;
72+
ranges;
73+
74+
gic: interrupt-controller@50001000 {
75+
compatible = "arm,gic-400";
76+
reg = <0x0 0x50001000 0x0 0x1000>,
77+
<0x0 0x50002000 0x0 0x2000>;
78+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
79+
interrupt-controller;
80+
#interrupt-cells = <3>;
81+
};
82+
83+
uart0: serial@58018000 {
84+
compatible = "snps,dw-apb-uart";
85+
reg = <0x0 0x58018000 0x0 0x2000>;
86+
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
87+
reg-shift = <2>;
88+
reg-io-width = <4>;
89+
status = "disabled";
90+
};
91+
92+
uart1: serial@5801A000 {
93+
compatible = "snps,dw-apb-uart";
94+
reg = <0x0 0x5801a000 0x0 0x2000>;
95+
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
96+
reg-shift = <2>;
97+
reg-io-width = <4>;
98+
status = "disabled";
99+
};
100+
101+
uart2: serial@5801C000 {
102+
compatible = "snps,dw-apb-uart";
103+
reg = <0x0 0x5801c000 0x0 0x2000>;
104+
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
105+
reg-shift = <2>;
106+
reg-io-width = <4>;
107+
status = "disabled";
108+
};
109+
110+
uart3: serial@5801E000 {
111+
compatible = "snps,dw-apb-uart";
112+
reg = <0x0 0x5801e000 0x0 0x2000>;
113+
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
114+
reg-shift = <2>;
115+
reg-io-width = <4>;
116+
status = "disabled";
117+
};
118+
};
119+
};

0 commit comments

Comments
 (0)