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Merge branch 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Fixes for radeon and amdgpu: - Fix GPUVM flushing on CI and VI - Misc DPM and Powerplay fixes - VCE DPM fixes for CZ/ST - DP hotplug fix * 'drm-fixes-4.5' of git://people.freedesktop.org/~agd5f/linux: drm/amdgpu: return from atombios_dp_get_dpcd only when error drm/amdgpu/cz: remove commented out call to enable vce pg drm/amdgpu/powerplay/cz: enable/disable vce dpm independent of vce pg drm/amdgpu/cz: enable/disable vce dpm even if vce pg is disabled drm/amdgpu/gfx8: specify which engine to wait before vm flush drm/amdgpu: apply gfx_v8 fixes to gfx_v7 as well drm/amd/powerplay: send event to notify powerplay all modules are initialized. drm/amd/powerplay: export AMD_PP_EVENT_COMPLETE_INIT task to amdgpu. drm/radeon/pm: update current crtc info after setting the powerstate drm/amdgpu/pm: update current crtc info after setting the powerstate
2 parents 2d02b8b + 0b39c53 commit f0511e6

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10 files changed

+34
-17
lines changed

10 files changed

+34
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lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ void amdgpu_connector_hotplug(struct drm_connector *connector)
7777
} else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) {
7878
/* Don't try to start link training before we
7979
* have the dpcd */
80-
if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
80+
if (amdgpu_atombios_dp_get_dpcd(amdgpu_connector))
8181
return;
8282

8383
/* set it to OFF so that drm_helper_connector_dpms()

‎drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -649,9 +649,6 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
649649
/* update display watermarks based on new power state */
650650
amdgpu_display_bandwidth_update(adev);
651651

652-
adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
653-
adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
654-
655652
/* wait for the rings to drain */
656653
for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
657654
struct amdgpu_ring *ring = adev->rings[i];
@@ -670,6 +667,9 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
670667
/* update displays */
671668
amdgpu_dpm_display_configuration_changed(adev);
672669

670+
adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
671+
adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
672+
673673
if (adev->pm.funcs->force_performance_level) {
674674
if (adev->pm.dpm.thermal_active) {
675675
enum amdgpu_dpm_forced_level level = adev->pm.dpm.forced_level;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -143,8 +143,10 @@ static int amdgpu_pp_late_init(void *handle)
143143
adev->powerplay.pp_handle);
144144

145145
#ifdef CONFIG_DRM_AMD_POWERPLAY
146-
if (adev->pp_enabled)
146+
if (adev->pp_enabled) {
147147
amdgpu_pm_sysfs_init(adev);
148+
amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
149+
}
148150
#endif
149151
return ret;
150152
}

‎drivers/gpu/drm/amd/amdgpu/cz_dpm.c

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2202,8 +2202,7 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
22022202
AMD_PG_STATE_GATE);
22032203

22042204
cz_enable_vce_dpm(adev, false);
2205-
/* TODO: to figure out why vce can't be poweroff. */
2206-
/* cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF); */
2205+
cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerOFF);
22072206
pi->vce_power_gated = true;
22082207
} else {
22092208
cz_send_msg_to_smc(adev, PPSMC_MSG_VCEPowerON);
@@ -2226,10 +2225,8 @@ static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate)
22262225
}
22272226
} else { /*pi->caps_vce_pg*/
22282227
cz_update_vce_dpm(adev);
2229-
cz_enable_vce_dpm(adev, true);
2228+
cz_enable_vce_dpm(adev, !gate);
22302229
}
2231-
2232-
return;
22332230
}
22342231

22352232
const struct amd_ip_funcs cz_dpm_ip_funcs = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3628,6 +3628,19 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
36283628
unsigned vm_id, uint64_t pd_addr)
36293629
{
36303630
int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3631+
uint32_t seq = ring->fence_drv.sync_seq;
3632+
uint64_t addr = ring->fence_drv.gpu_addr;
3633+
3634+
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3635+
amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3636+
WAIT_REG_MEM_FUNCTION(3) | /* equal */
3637+
WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
3638+
amdgpu_ring_write(ring, addr & 0xfffffffc);
3639+
amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
3640+
amdgpu_ring_write(ring, seq);
3641+
amdgpu_ring_write(ring, 0xffffffff);
3642+
amdgpu_ring_write(ring, 4); /* poll interval */
3643+
36313644
if (usepfp) {
36323645
/* synce CE with ME to prevent CE fetch CEIB before context switch done */
36333646
amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4809,7 +4809,8 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
48094809

48104810
amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
48114811
amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4812-
WAIT_REG_MEM_FUNCTION(3))); /* equal */
4812+
WAIT_REG_MEM_FUNCTION(3) | /* equal */
4813+
WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
48134814
amdgpu_ring_write(ring, addr & 0xfffffffc);
48144815
amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
48154816
amdgpu_ring_write(ring, seq);

‎drivers/gpu/drm/amd/powerplay/amd_powerplay.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -402,8 +402,11 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,
402402

403403
data.requested_ui_label = power_state_convert(ps);
404404
ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
405+
break;
405406
}
406-
break;
407+
case AMD_PP_EVENT_COMPLETE_INIT:
408+
ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);
409+
break;
407410
default:
408411
break;
409412
}

‎drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -165,6 +165,7 @@ const struct action_chain resume_action_chain = {
165165
};
166166

167167
static const pem_event_action *complete_init_event[] = {
168+
unblock_adjust_power_state_tasks,
168169
adjust_power_state_tasks,
169170
enable_gfx_clock_gating_tasks,
170171
enable_gfx_voltage_island_power_gating_tasks,

‎drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -226,7 +226,7 @@ int cz_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
226226
}
227227
} else {
228228
cz_dpm_update_vce_dpm(hwmgr);
229-
cz_enable_disable_vce_dpm(hwmgr, true);
229+
cz_enable_disable_vce_dpm(hwmgr, !bgate);
230230
return 0;
231231
}
232232

‎drivers/gpu/drm/radeon/radeon_pm.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1080,10 +1080,6 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
10801080
/* update display watermarks based on new power state */
10811081
radeon_bandwidth_update(rdev);
10821082

1083-
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1084-
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1085-
rdev->pm.dpm.single_display = single_display;
1086-
10871083
/* wait for the rings to drain */
10881084
for (i = 0; i < RADEON_NUM_RINGS; i++) {
10891085
struct radeon_ring *ring = &rdev->ring[i];
@@ -1102,6 +1098,10 @@ static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
11021098
/* update displays */
11031099
radeon_dpm_display_configuration_changed(rdev);
11041100

1101+
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1102+
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1103+
rdev->pm.dpm.single_display = single_display;
1104+
11051105
if (rdev->asic->dpm.force_performance_level) {
11061106
if (rdev->pm.dpm.thermal_active) {
11071107
enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;

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