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torvaldstorvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq updates from Thomas Gleixner: "The irq department provides: - a major update to the auto affinity management code, which is used by multi-queue devices - move of the microblaze irq chip driver into the common driver code so it can be shared between microblaze, powerpc and MIPS - a series of updates to the ARM GICV3 interrupt controller - the usual pile of fixes and small improvements all over the place" * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (25 commits) powerpc/virtex: Use generic xilinx irqchip driver irqchip/xilinx: Try to fall back if xlnx,kind-of-intr not provided irqchip/xilinx: Add support for parent intc irqchip/xilinx: Rename get_irq to xintc_get_irq irqchip/xilinx: Restructure and use jump label api irqchip/xilinx: Clean up print messages microblaze/irqchip: Move intc driver to irqchip ARM: virt: Select ARM_GIC_V3_ITS ARM: gic-v3-its: Add 32bit support to GICv3 ITS irqchip/gic-v3-its: Specialise readq and writeq accesses irqchip/gic-v3-its: Specialise flush_dcache operation irqchip/gic-v3-its: Narrow down Entry Size when used as a divider irqchip/gic-v3-its: Change unsigned types for AArch32 compatibility irqchip/gic-v3: Use nops macro for Cavium ThunderX erratum 23154 irqchip/gic-v3: Convert arm64 GIC accessors to {read,write}_sysreg_s genirq/msi: Drop artificial PCI dependency irqchip/bcm7038-l1: Implement irq_cpu_offline() callback genirq/affinity: Use default affinity mask for reserved vectors genirq/affinity: Take reserved vectors into account when spreading irqs PCI: Remove the irq_affinity mask from struct pci_dev ...
2 parents 9465d9c + 2cae3a1 commit f082f02

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‎arch/arm/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -703,6 +703,7 @@ config ARCH_VIRT
703703
select ARM_GIC
704704
select ARM_GIC_V2M if PCI
705705
select ARM_GIC_V3
706+
select ARM_GIC_V3_ITS if PCI
706707
select ARM_PSCI
707708
select HAVE_ARM_ARCH_TIMER
708709

‎arch/arm/include/asm/arch_gicv3.h

Lines changed: 47 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@
2222

2323
#include <linux/io.h>
2424
#include <asm/barrier.h>
25+
#include <asm/cacheflush.h>
2526
#include <asm/cp15.h>
2627

2728
#define ICC_EOIR1 __ACCESS_CP15(c12, 0, c12, 1)
@@ -230,19 +231,14 @@ static inline void gic_write_bpr1(u32 val)
230231
* AArch32, since the syndrome register doesn't provide any information for
231232
* them.
232233
* Consequently, the following IO helpers use 32bit accesses.
233-
*
234-
* There are only two registers that need 64bit accesses in this driver:
235-
* - GICD_IROUTERn, contain the affinity values associated to each interrupt.
236-
* The upper-word (aff3) will always be 0, so there is no need for a lock.
237-
* - GICR_TYPER is an ID register and doesn't need atomicity.
238234
*/
239-
static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)
235+
static inline void __gic_writeq_nonatomic(u64 val, volatile void __iomem *addr)
240236
{
241237
writel_relaxed((u32)val, addr);
242238
writel_relaxed((u32)(val >> 32), addr + 4);
243239
}
244240

245-
static inline u64 gic_read_typer(const volatile void __iomem *addr)
241+
static inline u64 __gic_readq_nonatomic(const volatile void __iomem *addr)
246242
{
247243
u64 val;
248244

@@ -251,5 +247,49 @@ static inline u64 gic_read_typer(const volatile void __iomem *addr)
251247
return val;
252248
}
253249

250+
#define gic_flush_dcache_to_poc(a,l) __cpuc_flush_dcache_area((a), (l))
251+
252+
/*
253+
* GICD_IROUTERn, contain the affinity values associated to each interrupt.
254+
* The upper-word (aff3) will always be 0, so there is no need for a lock.
255+
*/
256+
#define gic_write_irouter(v, c) __gic_writeq_nonatomic(v, c)
257+
258+
/*
259+
* GICR_TYPER is an ID register and doesn't need atomicity.
260+
*/
261+
#define gic_read_typer(c) __gic_readq_nonatomic(c)
262+
263+
/*
264+
* GITS_BASER - hi and lo bits may be accessed independently.
265+
*/
266+
#define gits_read_baser(c) __gic_readq_nonatomic(c)
267+
#define gits_write_baser(v, c) __gic_writeq_nonatomic(v, c)
268+
269+
/*
270+
* GICR_PENDBASER and GICR_PROPBASE are changed with LPIs disabled, so they
271+
* won't be being used during any updates and can be changed non-atomically
272+
*/
273+
#define gicr_read_propbaser(c) __gic_readq_nonatomic(c)
274+
#define gicr_write_propbaser(v, c) __gic_writeq_nonatomic(v, c)
275+
#define gicr_read_pendbaser(c) __gic_readq_nonatomic(c)
276+
#define gicr_write_pendbaser(v, c) __gic_writeq_nonatomic(v, c)
277+
278+
/*
279+
* GITS_TYPER is an ID register and doesn't need atomicity.
280+
*/
281+
#define gits_read_typer(c) __gic_readq_nonatomic(c)
282+
283+
/*
284+
* GITS_CBASER - hi and lo bits may be accessed independently.
285+
*/
286+
#define gits_read_cbaser(c) __gic_readq_nonatomic(c)
287+
#define gits_write_cbaser(v, c) __gic_writeq_nonatomic(v, c)
288+
289+
/*
290+
* GITS_CWRITER - hi and lo bits may be accessed independently.
291+
*/
292+
#define gits_write_cwriter(v, c) __gic_writeq_nonatomic(v, c)
293+
254294
#endif /* !__ASSEMBLY__ */
255295
#endif /* !__ASM_ARCH_GICV3_H */

‎arch/arm64/include/asm/arch_gicv3.h

Lines changed: 31 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -79,19 +79,10 @@
7979

8080
#include <linux/stringify.h>
8181
#include <asm/barrier.h>
82+
#include <asm/cacheflush.h>
8283

83-
#define read_gicreg(r) \
84-
({ \
85-
u64 reg; \
86-
asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg)); \
87-
reg; \
88-
})
89-
90-
#define write_gicreg(v,r) \
91-
do { \
92-
u64 __val = (v); \
93-
asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
94-
} while (0)
84+
#define read_gicreg read_sysreg_s
85+
#define write_gicreg write_sysreg_s
9586

9687
/*
9788
* Low-level accessors
@@ -102,21 +93,21 @@
10293

10394
static inline void gic_write_eoir(u32 irq)
10495
{
105-
asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));
96+
write_sysreg_s(irq, ICC_EOIR1_EL1);
10697
isb();
10798
}
10899

109100
static inline void gic_write_dir(u32 irq)
110101
{
111-
asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));
102+
write_sysreg_s(irq, ICC_DIR_EL1);
112103
isb();
113104
}
114105

115106
static inline u64 gic_read_iar_common(void)
116107
{
117108
u64 irqstat;
118109

119-
asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
110+
irqstat = read_sysreg_s(ICC_IAR1_EL1);
120111
dsb(sy);
121112
return irqstat;
122113
}
@@ -132,50 +123,44 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
132123
{
133124
u64 irqstat;
134125

135-
asm volatile(
136-
"nop;nop;nop;nop\n\t"
137-
"nop;nop;nop;nop\n\t"
138-
"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
139-
"nop;nop;nop;nop"
140-
: "=r" (irqstat));
126+
nops(8);
127+
irqstat = read_sysreg_s(ICC_IAR1_EL1);
128+
nops(4);
141129
mb();
142130

143131
return irqstat;
144132
}
145133

146134
static inline void gic_write_pmr(u32 val)
147135
{
148-
asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
136+
write_sysreg_s(val, ICC_PMR_EL1);
149137
}
150138

151139
static inline void gic_write_ctlr(u32 val)
152140
{
153-
asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));
141+
write_sysreg_s(val, ICC_CTLR_EL1);
154142
isb();
155143
}
156144

157145
static inline void gic_write_grpen1(u32 val)
158146
{
159-
asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));
147+
write_sysreg_s(val, ICC_GRPEN1_EL1);
160148
isb();
161149
}
162150

163151
static inline void gic_write_sgi1r(u64 val)
164152
{
165-
asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
153+
write_sysreg_s(val, ICC_SGI1R_EL1);
166154
}
167155

168156
static inline u32 gic_read_sre(void)
169157
{
170-
u64 val;
171-
172-
asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
173-
return val;
158+
return read_sysreg_s(ICC_SRE_EL1);
174159
}
175160

176161
static inline void gic_write_sre(u32 val)
177162
{
178-
asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));
163+
write_sysreg_s(val, ICC_SRE_EL1);
179164
isb();
180165
}
181166

@@ -187,5 +172,21 @@ static inline void gic_write_bpr1(u32 val)
187172
#define gic_read_typer(c) readq_relaxed(c)
188173
#define gic_write_irouter(v, c) writeq_relaxed(v, c)
189174

175+
#define gic_flush_dcache_to_poc(a,l) __flush_dcache_area((a), (l))
176+
177+
#define gits_read_baser(c) readq_relaxed(c)
178+
#define gits_write_baser(v, c) writeq_relaxed(v, c)
179+
180+
#define gits_read_cbaser(c) readq_relaxed(c)
181+
#define gits_write_cbaser(v, c) writeq_relaxed(v, c)
182+
183+
#define gits_write_cwriter(v, c) writeq_relaxed(v, c)
184+
185+
#define gicr_read_propbaser(c) readq_relaxed(c)
186+
#define gicr_write_propbaser(v, c) writeq_relaxed(v, c)
187+
188+
#define gicr_write_pendbaser(v, c) writeq_relaxed(v, c)
189+
#define gicr_read_pendbaser(c) readq_relaxed(c)
190+
190191
#endif /* __ASSEMBLY__ */
191192
#endif /* __ASM_ARCH_GICV3_H */

‎arch/microblaze/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ config MICROBLAZE
2727
select HAVE_MEMBLOCK_NODE_MAP
2828
select HAVE_OPROFILE
2929
select IRQ_DOMAIN
30+
select XILINX_INTC
3031
select MODULES_USE_ELF_RELA
3132
select OF
3233
select OF_EARLY_FLATTREE

‎arch/microblaze/include/asm/irq.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,6 @@ struct pt_regs;
1616
extern void do_IRQ(struct pt_regs *regs);
1717

1818
/* should be defined in each interrupt controller driver */
19-
extern unsigned int get_irq(void);
19+
extern unsigned int xintc_get_irq(void);
2020

2121
#endif /* _ASM_MICROBLAZE_IRQ_H */

‎arch/microblaze/kernel/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ endif
1515
extra-y := head.o vmlinux.lds
1616

1717
obj-y += dma.o exceptions.o \
18-
hw_exception_handler.o intc.o irq.o \
18+
hw_exception_handler.o irq.o \
1919
platform.o process.o prom.o ptrace.o \
2020
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
2121

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