ARM: OMAP3: clock: use clk_features flags for omap3 DPLL4 checks

Tero Kristo · Paul Walmsley · commit f0d2f68a6387 · 2014-11-13T09:25:06.000-07:00
DPLL4 can't be reprogrammed on OMAP3430 ES1.0 due to hardware limitation.
Currently, the code does runtime omap_rev() check to see the chip it is
being executed on, instead, change this to use clk_features flags.
This avoids need for runtime omap_rev() checks.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Signed-off-by: Paul Walmsley &lt;paul@pwsan.com&gt;
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
@@ -771,4 +771,8 @@ void __init ti_clk_init_features(void)
 		ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
 	else if (cpu_is_omap34xx())
 		ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
+
+	/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
+	if (omap_rev() == OMAP3430_REV_ES1_0)
+		ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
 }
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
@@ -234,6 +234,7 @@ struct ti_clk_features {
 };
 
 #define TI_CLK_DPLL_HAS_FREQSEL		(1 << 0)
+#define TI_CLK_DPLL4_DENY_REPROGRAM	(1 << 1)
 
 extern struct ti_clk_features ti_clk_features;
 
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
@@ -46,7 +46,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
 	 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
 	 * on DPLL4.
 	 */
-	if (omap_rev() == OMAP3430_REV_ES1_0) {
+	if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
 		pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
 		return -EINVAL;
 	}

Original file line number	Diff line number	Diff line change
`@@ -771,4 +771,8 @@ void __init ti_clk_init_features(void)`
`771`	`771`	`ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;`
`772`	`772`	`else if (cpu_is_omap34xx())`
`773`	`773`	`ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;`
	`774`	`+`
	`775`	`+ /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */`
	`776`	`+ if (omap_rev() == OMAP3430_REV_ES1_0)`
	`777`	`+ ti_clk_features.flags \|= TI_CLK_DPLL4_DENY_REPROGRAM;`
`774`	`778`	`}`
Original file line number	Diff line number	Diff line change
`@@ -46,7 +46,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,`
`46`	`46`	`* on 3430ES1 prevents us from changing DPLL multipliers or dividers`
`47`	`47`	`* on DPLL4.`
`48`	`48`	`*/`
`49`		`- if (omap_rev() == OMAP3430_REV_ES1_0) {`
	`49`	`+ if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {`
`50`	`50`	`pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");`
`51`	`51`	`return -EINVAL;`
`52`	`52`	`}`