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crypto: arm - add support for GHASH using ARMv8 Crypto Extensions
This implements the GHASH hash algorithm (as used by the GCM AEAD chaining mode) using the AArch32 version of the 64x64 to 128 bit polynomial multiplication instruction (vmull.p64) that is part of the ARMv8 Crypto Extensions. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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arch/arm/crypto/Kconfig

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@@ -110,4 +110,14 @@ config CRYPTO_AES_ARM_CE
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Use an implementation of AES in CBC, CTR and XTS modes that uses
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ARMv8 Crypto Extensions
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config CRYPTO_GHASH_ARM_CE
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tristate "PMULL-accelerated GHASH using ARMv8 Crypto Extensions"
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depends on KERNEL_MODE_NEON
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select CRYPTO_HASH
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select CRYPTO_CRYPTD
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help
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Use an implementation of GHASH (used by the GCM AEAD chaining mode)
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that uses the 64x64 to 128 bit polynomial multiplication (vmull.p64)
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that is part of the ARMv8 Crypto Extensions
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endif

arch/arm/crypto/Makefile

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@@ -10,6 +10,7 @@ obj-$(CONFIG_CRYPTO_SHA1_ARM_NEON) += sha1-arm-neon.o
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obj-$(CONFIG_CRYPTO_SHA512_ARM_NEON) += sha512-arm-neon.o
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obj-$(CONFIG_CRYPTO_SHA1_ARM_CE) += sha1-arm-ce.o
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obj-$(CONFIG_CRYPTO_SHA2_ARM_CE) += sha2-arm-ce.o
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obj-$(CONFIG_CRYPTO_GHASH_ARM_CE) += ghash-arm-ce.o
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aes-arm-y := aes-armv4.o aes_glue.o
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aes-arm-bs-y := aesbs-core.o aesbs-glue.o
@@ -19,6 +20,7 @@ sha512-arm-neon-y := sha512-armv7-neon.o sha512_neon_glue.o
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sha1-arm-ce-y := sha1-ce-core.o sha1-ce-glue.o
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sha2-arm-ce-y := sha2-ce-core.o sha2-ce-glue.o
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aes-arm-ce-y := aes-ce-core.o aes-ce-glue.o
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ghash-arm-ce-y := ghash-ce-core.o ghash-ce-glue.o
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quiet_cmd_perl = PERL $@
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cmd_perl = $(PERL) $(<) > $(@)

arch/arm/crypto/ghash-ce-core.S

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/*
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* Accelerated GHASH implementation with ARMv8 vmull.p64 instructions.
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*
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* Copyright (C) 2015 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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SHASH .req q0
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SHASH2 .req q1
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T1 .req q2
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T2 .req q3
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MASK .req q4
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XL .req q5
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XM .req q6
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XH .req q7
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IN1 .req q7
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SHASH_L .req d0
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SHASH_H .req d1
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SHASH2_L .req d2
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T1_L .req d4
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MASK_L .req d8
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XL_L .req d10
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XL_H .req d11
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XM_L .req d12
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XM_H .req d13
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XH_L .req d14
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.text
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.fpu crypto-neon-fp-armv8
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/*
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* void pmull_ghash_update(int blocks, u64 dg[], const char *src,
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* struct ghash_key const *k, const char *head)
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*/
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ENTRY(pmull_ghash_update)
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vld1.8 {SHASH}, [r3]
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vld1.64 {XL}, [r1]
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vmov.i8 MASK, #0xe1
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vext.8 SHASH2, SHASH, SHASH, #8
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vshl.u64 MASK, MASK, #57
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veor SHASH2, SHASH2, SHASH
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/* do the head block first, if supplied */
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ldr ip, [sp]
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teq ip, #0
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beq 0f
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vld1.64 {T1}, [ip]
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teq r0, #0
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b 1f
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0: vld1.64 {T1}, [r2]!
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subs r0, r0, #1
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1: /* multiply XL by SHASH in GF(2^128) */
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#ifndef CONFIG_CPU_BIG_ENDIAN
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vrev64.8 T1, T1
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#endif
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vext.8 T2, XL, XL, #8
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vext.8 IN1, T1, T1, #8
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veor T1, T1, T2
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veor XL, XL, IN1
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vmull.p64 XH, SHASH_H, XL_H @ a1 * b1
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veor T1, T1, XL
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vmull.p64 XL, SHASH_L, XL_L @ a0 * b0
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vmull.p64 XM, SHASH2_L, T1_L @ (a1 + a0)(b1 + b0)
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vext.8 T1, XL, XH, #8
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veor T2, XL, XH
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veor XM, XM, T1
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veor XM, XM, T2
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vmull.p64 T2, XL_L, MASK_L
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vmov XH_L, XM_H
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vmov XM_H, XL_L
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veor XL, XM, T2
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vext.8 T2, XL, XL, #8
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vmull.p64 XL, XL_L, MASK_L
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veor T2, T2, XH
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veor XL, XL, T2
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bne 0b
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vst1.64 {XL}, [r1]
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bx lr
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ENDPROC(pmull_ghash_update)

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