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Ingo Molnar
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Merge branch 'clockevents/3.20' of http://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevents updates from Daniel Lezcano: - Add new driver for the Conexant Digicolor SoCs (Baruch Siach) - Add new driver for the rockchip rk3288 board (Daniel Lezcano) - Add new asm9260 driver for MIPS (Oleksij Rempel) - Add DT definitions for the versatile AB/PB boards (Rob Herring) - Rename the 'marco' timer to 'atlas7' (Barry Song) Signed-off-by: Ingo Molnar <mingo@kernel.org>
2 parents 4ebbda5 + 35a8578 commit f40d149

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‎Documentation/devicetree/bindings/arm/versatile-sysreg.txt

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@@ -0,0 +1,10 @@
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ARM Versatile system registers
2+
--------------------------------------
3+
4+
This is a system control registers block, providing multiple low level
5+
platform functions like board detection and identification, software
6+
interrupt generation, MMC and NOR Flash control etc.
7+
8+
Required node properties:
9+
- compatible value : = "arm,versatile-sysreg", "syscon"
10+
- reg : physical base address and the size of the registers window

‎Documentation/devicetree/bindings/timer/digicolor-timer.txt

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@@ -0,0 +1,18 @@
1+
Conexant Digicolor SoCs Timer Controller
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3+
Required properties:
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- compatible : should be "cnxt,cx92755-timer"
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- reg : Specifies base physical address and size of the "Agent Communication"
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timer registers
8+
- interrupts : Contains 8 interrupts, one for each timer
9+
- clocks: phandle to the main clock
10+
11+
Example:
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13+
timer@f0000fc0 {
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compatible = "cnxt,cx92755-timer";
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reg = <0xf0000fc0 0x40>;
16+
interrupts = <19>, <31>, <34>, <35>, <52>, <53>, <54>, <55>;
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clocks = <&main_clk>;
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};

‎Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt

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Rockchip rk3288 timer
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Required properties:
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- compatible: shall be "rockchip,rk3288-timer"
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- reg: base address of the timer register starting with TIMERS CONTROL register
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- interrupts: should contain the interrupts for Timer0
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- clocks : must contain an entry for each entry in clock-names
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- clock-names : must include the following entries:
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"timer", "pclk"
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Example:
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timer: timer@ff810000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0xff810000 0x20>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>, <&cru PCLK_TIMER>;
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clock-names = "timer", "pclk";
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};

‎MAINTAINERS

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@@ -958,7 +958,7 @@ S: Maintained
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F: arch/arm/mach-prima2/
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F: drivers/clk/sirf/
960960
F: drivers/clocksource/timer-prima2.c
961-
F: drivers/clocksource/timer-marco.c
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F: drivers/clocksource/timer-atlas7.c
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N: [^a-z]sirf
963963

964964
ARM/EBSA110 MACHINE SUPPORT

‎arch/arm/boot/dts/versatile-ab.dts

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@@ -252,6 +252,11 @@
252252
#size-cells = <1>;
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ranges = <0 0x10000000 0x10000>;
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sysreg@0 {
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compatible = "arm,versatile-sysreg", "syscon";
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reg = <0x00000 0x1000>;
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};
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aaci@4000 {
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compatible = "arm,primecell";
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reg = <0x4000 0x1000>;

‎arch/arm/mach-rockchip/Kconfig

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@@ -11,6 +11,7 @@ config ARCH_ROCKCHIP
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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select DW_APB_TIMER_OF
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select ROCKCHIP_TIMER
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select ARM_GLOBAL_TIMER
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select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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help

‎drivers/clocksource/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -18,6 +18,9 @@ config CLKBLD_I8253
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config CLKSRC_MMIO
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bool
2020

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config DIGICOLOR_TIMER
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bool
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config DW_APB_TIMER
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bool
2326

@@ -26,6 +29,10 @@ config DW_APB_TIMER_OF
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select DW_APB_TIMER
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select CLKSRC_OF
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config ROCKCHIP_TIMER
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bool
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select CLKSRC_OF
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config ARMADA_370_XP_TIMER
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bool
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select CLKSRC_OF
@@ -229,4 +236,14 @@ config CLKSRC_MIPS_GIC
229236
depends on MIPS_GIC
230237
select CLKSRC_OF
231238

239+
config ASM9260_TIMER
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bool "Alphascale ASM9260 timer driver"
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depends on GENERIC_CLOCKEVENTS
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select CLKSRC_MMIO
243+
select CLKSRC_OF
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default y if MACH_ASM9260
245+
help
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This enables build of a clocksource and clockevent driver for
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the 32-bit System Timer hardware available on a Alphascale ASM9260.
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232249
endmenu

‎drivers/clocksource/Makefile

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Original file line numberDiff line numberDiff line change
@@ -10,15 +10,17 @@ obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
1010
obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
1111
obj-$(CONFIG_CLKBLD_I8253) += i8253.o
1212
obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
13+
obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
1314
obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
1415
obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
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obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
1517
obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o
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obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
1719
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
1820
obj-$(CONFIG_ORION_TIMER) += time-orion.o
1921
obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
2022
obj-$(CONFIG_ARCH_CLPS711X) += clps711x-timer.o
21-
obj-$(CONFIG_ARCH_MARCO) += timer-marco.o
23+
obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o
2224
obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
2325
obj-$(CONFIG_ARCH_MXS) += mxs_timer.o
2426
obj-$(CONFIG_ARCH_PXA) += pxa_timer.o
@@ -48,3 +50,4 @@ obj-$(CONFIG_ARCH_KEYSTONE) += timer-keystone.o
4850
obj-$(CONFIG_ARCH_INTEGRATOR_AP) += timer-integrator-ap.o
4951
obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o
5052
obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o
53+
obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o

‎drivers/clocksource/asm9260_timer.c

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@@ -0,0 +1,220 @@
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/*
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* Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
13+
#include <linux/sched.h>
14+
#include <linux/clk.h>
15+
#include <linux/clocksource.h>
16+
#include <linux/clockchips.h>
17+
#include <linux/io.h>
18+
#include <linux/of.h>
19+
#include <linux/of_address.h>
20+
#include <linux/of_irq.h>
21+
#include <linux/bitops.h>
22+
23+
#define DRIVER_NAME "asm9260-timer"
24+
25+
/*
26+
* this device provide 4 offsets for each register:
27+
* 0x0 - plain read write mode
28+
* 0x4 - set mode, OR logic.
29+
* 0x8 - clr mode, XOR logic.
30+
* 0xc - togle mode.
31+
*/
32+
#define SET_REG 4
33+
#define CLR_REG 8
34+
35+
#define HW_IR 0x0000 /* RW. Interrupt */
36+
#define BM_IR_CR0 BIT(4)
37+
#define BM_IR_MR3 BIT(3)
38+
#define BM_IR_MR2 BIT(2)
39+
#define BM_IR_MR1 BIT(1)
40+
#define BM_IR_MR0 BIT(0)
41+
42+
#define HW_TCR 0x0010 /* RW. Timer controller */
43+
/* BM_C*_RST
44+
* Timer Counter and the Prescale Counter are synchronously reset on the
45+
* next positive edge of PCLK. The counters remain reset until TCR[1] is
46+
* returned to zero. */
47+
#define BM_C3_RST BIT(7)
48+
#define BM_C2_RST BIT(6)
49+
#define BM_C1_RST BIT(5)
50+
#define BM_C0_RST BIT(4)
51+
/* BM_C*_EN
52+
* 1 - Timer Counter and Prescale Counter are enabled for counting
53+
* 0 - counters are disabled */
54+
#define BM_C3_EN BIT(3)
55+
#define BM_C2_EN BIT(2)
56+
#define BM_C1_EN BIT(1)
57+
#define BM_C0_EN BIT(0)
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59+
#define HW_DIR 0x0020 /* RW. Direction? */
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/* 00 - count up
61+
* 01 - count down
62+
* 10 - ?? 2^n/2 */
63+
#define BM_DIR_COUNT_UP 0
64+
#define BM_DIR_COUNT_DOWN 1
65+
#define BM_DIR0_SHIFT 0
66+
#define BM_DIR1_SHIFT 4
67+
#define BM_DIR2_SHIFT 8
68+
#define BM_DIR3_SHIFT 12
69+
#define BM_DIR_DEFAULT (BM_DIR_COUNT_UP << BM_DIR0_SHIFT | \
70+
BM_DIR_COUNT_UP << BM_DIR1_SHIFT | \
71+
BM_DIR_COUNT_UP << BM_DIR2_SHIFT | \
72+
BM_DIR_COUNT_UP << BM_DIR3_SHIFT)
73+
74+
#define HW_TC0 0x0030 /* RO. Timer counter 0 */
75+
/* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate
76+
* interrupt. This registers can be used to detect overflow */
77+
#define HW_TC1 0x0040
78+
#define HW_TC2 0x0050
79+
#define HW_TC3 0x0060
80+
81+
#define HW_PR 0x0070 /* RW. prescaler */
82+
#define BM_PR_DISABLE 0
83+
#define HW_PC 0x0080 /* RO. Prescaler counter */
84+
#define HW_MCR 0x0090 /* RW. Match control */
85+
/* enable interrupt on match */
86+
#define BM_MCR_INT_EN(n) (1 << (n * 3 + 0))
87+
/* enable TC reset on match */
88+
#define BM_MCR_RES_EN(n) (1 << (n * 3 + 1))
89+
/* enable stop TC on match */
90+
#define BM_MCR_STOP_EN(n) (1 << (n * 3 + 2))
91+
92+
#define HW_MR0 0x00a0 /* RW. Match reg */
93+
#define HW_MR1 0x00b0
94+
#define HW_MR2 0x00C0
95+
#define HW_MR3 0x00D0
96+
97+
#define HW_CTCR 0x0180 /* Counter control */
98+
#define BM_CTCR0_SHIFT 0
99+
#define BM_CTCR1_SHIFT 2
100+
#define BM_CTCR2_SHIFT 4
101+
#define BM_CTCR3_SHIFT 6
102+
#define BM_CTCR_TM 0 /* Timer mode. Every rising PCLK edge. */
103+
#define BM_CTCR_DEFAULT (BM_CTCR_TM << BM_CTCR0_SHIFT | \
104+
BM_CTCR_TM << BM_CTCR1_SHIFT | \
105+
BM_CTCR_TM << BM_CTCR2_SHIFT | \
106+
BM_CTCR_TM << BM_CTCR3_SHIFT)
107+
108+
static struct asm9260_timer_priv {
109+
void __iomem *base;
110+
unsigned long ticks_per_jiffy;
111+
} priv;
112+
113+
static int asm9260_timer_set_next_event(unsigned long delta,
114+
struct clock_event_device *evt)
115+
{
116+
/* configure match count for TC0 */
117+
writel_relaxed(delta, priv.base + HW_MR0);
118+
/* enable TC0 */
119+
writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
120+
return 0;
121+
}
122+
123+
static void asm9260_timer_set_mode(enum clock_event_mode mode,
124+
struct clock_event_device *evt)
125+
{
126+
/* stop timer0 */
127+
writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG);
128+
129+
switch (mode) {
130+
case CLOCK_EVT_MODE_PERIODIC:
131+
/* disable reset and stop on match */
132+
writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
133+
priv.base + HW_MCR + CLR_REG);
134+
/* configure match count for TC0 */
135+
writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0);
136+
/* enable TC0 */
137+
writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
138+
break;
139+
case CLOCK_EVT_MODE_ONESHOT:
140+
/* enable reset and stop on match */
141+
writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0),
142+
priv.base + HW_MCR + SET_REG);
143+
break;
144+
default:
145+
break;
146+
}
147+
}
148+
149+
static struct clock_event_device event_dev = {
150+
.name = DRIVER_NAME,
151+
.rating = 200,
152+
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
153+
.set_next_event = asm9260_timer_set_next_event,
154+
.set_mode = asm9260_timer_set_mode,
155+
};
156+
157+
static irqreturn_t asm9260_timer_interrupt(int irq, void *dev_id)
158+
{
159+
struct clock_event_device *evt = dev_id;
160+
161+
evt->event_handler(evt);
162+
163+
writel_relaxed(BM_IR_MR0, priv.base + HW_IR);
164+
165+
return IRQ_HANDLED;
166+
}
167+
168+
/*
169+
* ---------------------------------------------------------------------------
170+
* Timer initialization
171+
* ---------------------------------------------------------------------------
172+
*/
173+
static void __init asm9260_timer_init(struct device_node *np)
174+
{
175+
int irq;
176+
struct clk *clk;
177+
int ret;
178+
unsigned long rate;
179+
180+
priv.base = of_io_request_and_map(np, 0, np->name);
181+
if (!priv.base)
182+
panic("%s: unable to map resource", np->name);
183+
184+
clk = of_clk_get(np, 0);
185+
186+
ret = clk_prepare_enable(clk);
187+
if (ret)
188+
panic("Failed to enable clk!\n");
189+
190+
irq = irq_of_parse_and_map(np, 0);
191+
ret = request_irq(irq, asm9260_timer_interrupt, IRQF_TIMER,
192+
DRIVER_NAME, &event_dev);
193+
if (ret)
194+
panic("Failed to setup irq!\n");
195+
196+
/* set all timers for count-up */
197+
writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR);
198+
/* disable divider */
199+
writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR);
200+
/* make sure all timers use every rising PCLK edge. */
201+
writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR);
202+
/* enable interrupt for TC0 and clean setting for all other lines */
203+
writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR);
204+
205+
rate = clk_get_rate(clk);
206+
clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate,
207+
200, 32, clocksource_mmio_readl_up);
208+
209+
/* Seems like we can't use counter without match register even if
210+
* actions for MR are disabled. So, set MR to max value. */
211+
writel_relaxed(0xffffffff, priv.base + HW_MR1);
212+
/* enable TC1 */
213+
writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);
214+
215+
priv.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
216+
event_dev.cpumask = cpumask_of(0);
217+
clockevents_config_and_register(&event_dev, rate, 0x2c00, 0xfffffffe);
218+
}
219+
CLOCKSOURCE_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
220+
asm9260_timer_init);

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