14
14
* Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15
15
* dealt with elsewhere; this file is concerned only with the EISA portions
16
16
* of Wax.
17
- *
18
- *
17
+ *
18
+ *
19
19
* HINT:
20
20
* -----
21
21
* To allow an ISA card to work properly in the EISA slot you need to
22
- * set an edge trigger level. This may be done on the palo command line
23
- * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
22
+ * set an edge trigger level. This may be done on the palo command line
23
+ * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
24
24
* n and n2 as the irq levels you want to use.
25
- *
26
- * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
25
+ *
26
+ * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
27
27
* irq levels 10 and 11.
28
28
*/
29
29
46
46
#include <asm/eisa_eeprom.h>
47
47
48
48
#if 0
49
- #define EISA_DBG (msg , arg ... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
49
+ #define EISA_DBG (msg , arg ...) printk(KERN_DEBUG "eisa: " msg, ## arg)
50
50
#else
51
- #define EISA_DBG (msg , arg ... )
51
+ #define EISA_DBG (msg , arg ...)
52
52
#endif
53
53
54
54
#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
@@ -108,7 +108,7 @@ void eisa_out8(unsigned char data, unsigned short port)
108
108
109
109
void eisa_out16 (unsigned short data , unsigned short port )
110
110
{
111
- if (EISA_bus )
111
+ if (EISA_bus )
112
112
gsc_writew (cpu_to_le16 (data ), eisa_permute (port ));
113
113
}
114
114
@@ -135,9 +135,9 @@ static int master_mask;
135
135
static int slave_mask ;
136
136
137
137
/* the trig level can be set with the
138
- * eisa_irq_edge=n,n,n commandline parameter
139
- * We should really read this from the EEPROM
140
- * in the furure.
138
+ * eisa_irq_edge=n,n,n commandline parameter
139
+ * We should really read this from the EEPROM
140
+ * in the furure.
141
141
*/
142
142
/* irq 13,8,2,1,0 must be edge */
143
143
static unsigned int eisa_irq_level __read_mostly ; /* default to edge triggered */
@@ -170,7 +170,7 @@ static void eisa_unmask_irq(struct irq_data *d)
170
170
unsigned int irq = d -> irq ;
171
171
unsigned long flags ;
172
172
EISA_DBG ("enable irq %d\n" , irq );
173
-
173
+
174
174
spin_lock_irqsave (& eisa_irq_lock , flags );
175
175
if (irq & 8 ) {
176
176
slave_mask &= ~(1 << (irq & 7 ));
@@ -194,39 +194,39 @@ static irqreturn_t eisa_irq(int wax_irq, void *intr_dev)
194
194
{
195
195
int irq = gsc_readb (0xfc01f000 ); /* EISA supports 16 irqs */
196
196
unsigned long flags ;
197
-
197
+
198
198
spin_lock_irqsave (& eisa_irq_lock , flags );
199
199
/* read IRR command */
200
200
eisa_out8 (0x0a , 0x20 );
201
201
eisa_out8 (0x0a , 0xa0 );
202
202
203
203
EISA_DBG ("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n" ,
204
204
irq , eisa_in8 (0x20 ), eisa_in8 (0xa0 ));
205
-
205
+
206
206
/* read ISR command */
207
207
eisa_out8 (0x0a , 0x20 );
208
208
eisa_out8 (0x0a , 0xa0 );
209
209
EISA_DBG ("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n" ,
210
210
eisa_in8 (0x20 ), eisa_in8 (0x21 ), eisa_in8 (0xa0 ), eisa_in8 (0xa1 ));
211
-
211
+
212
212
irq &= 0xf ;
213
-
213
+
214
214
/* mask irq and write eoi */
215
215
if (irq & 8 ) {
216
216
slave_mask |= (1 << (irq & 7 ));
217
217
eisa_out8 (slave_mask , 0xa1 );
218
218
eisa_out8 (0x60 | (irq & 7 ),0xa0 );/* 'Specific EOI' to slave */
219
- eisa_out8 (0x62 ,0x20 ); /* 'Specific EOI' to master-IRQ2 */
220
-
219
+ eisa_out8 (0x62 , 0x20 ); /* 'Specific EOI' to master-IRQ2 */
220
+
221
221
} else {
222
222
master_mask |= (1 << (irq & 7 ));
223
223
eisa_out8 (master_mask , 0x21 );
224
- eisa_out8 (0x60 |irq ,0x20 ); /* 'Specific EOI' to master */
224
+ eisa_out8 (0x60 |irq , 0x20 ); /* 'Specific EOI' to master */
225
225
}
226
226
spin_unlock_irqrestore (& eisa_irq_lock , flags );
227
227
228
228
generic_handle_irq (irq );
229
-
229
+
230
230
spin_lock_irqsave (& eisa_irq_lock , flags );
231
231
/* unmask */
232
232
if (irq & 8 ) {
@@ -254,44 +254,44 @@ static struct irqaction irq2_action = {
254
254
static void init_eisa_pic (void )
255
255
{
256
256
unsigned long flags ;
257
-
257
+
258
258
spin_lock_irqsave (& eisa_irq_lock , flags );
259
259
260
260
eisa_out8 (0xff , 0x21 ); /* mask during init */
261
261
eisa_out8 (0xff , 0xa1 ); /* mask during init */
262
-
262
+
263
263
/* master pic */
264
- eisa_out8 (0x11 ,0x20 ); /* ICW1 */
265
- eisa_out8 (0x00 ,0x21 ); /* ICW2 */
266
- eisa_out8 (0x04 ,0x21 ); /* ICW3 */
267
- eisa_out8 (0x01 ,0x21 ); /* ICW4 */
268
- eisa_out8 (0x40 ,0x20 ); /* OCW2 */
269
-
264
+ eisa_out8 (0x11 , 0x20 ); /* ICW1 */
265
+ eisa_out8 (0x00 , 0x21 ); /* ICW2 */
266
+ eisa_out8 (0x04 , 0x21 ); /* ICW3 */
267
+ eisa_out8 (0x01 , 0x21 ); /* ICW4 */
268
+ eisa_out8 (0x40 , 0x20 ); /* OCW2 */
269
+
270
270
/* slave pic */
271
- eisa_out8 (0x11 ,0xa0 ); /* ICW1 */
272
- eisa_out8 (0x08 ,0xa1 ); /* ICW2 */
273
- eisa_out8 (0x02 ,0xa1 ); /* ICW3 */
274
- eisa_out8 (0x01 ,0xa1 ); /* ICW4 */
275
- eisa_out8 (0x40 ,0xa0 ); /* OCW2 */
276
-
271
+ eisa_out8 (0x11 , 0xa0 ); /* ICW1 */
272
+ eisa_out8 (0x08 , 0xa1 ); /* ICW2 */
273
+ eisa_out8 (0x02 , 0xa1 ); /* ICW3 */
274
+ eisa_out8 (0x01 , 0xa1 ); /* ICW4 */
275
+ eisa_out8 (0x40 , 0xa0 ); /* OCW2 */
276
+
277
277
udelay (100 );
278
-
279
- slave_mask = 0xff ;
280
- master_mask = 0xfb ;
278
+
279
+ slave_mask = 0xff ;
280
+ master_mask = 0xfb ;
281
281
eisa_out8 (slave_mask , 0xa1 ); /* OCW1 */
282
282
eisa_out8 (master_mask , 0x21 ); /* OCW1 */
283
-
283
+
284
284
/* setup trig level */
285
285
EISA_DBG ("EISA edge/level %04x\n" , eisa_irq_level );
286
-
286
+
287
287
eisa_out8 (eisa_irq_level & 0xff , 0x4d0 ); /* Set all irq's to edge */
288
- eisa_out8 ((eisa_irq_level >> 8 ) & 0xff , 0x4d1 );
289
-
288
+ eisa_out8 ((eisa_irq_level >> 8 ) & 0xff , 0x4d1 );
289
+
290
290
EISA_DBG ("pic0 mask %02x\n" , eisa_in8 (0x21 ));
291
291
EISA_DBG ("pic1 mask %02x\n" , eisa_in8 (0xa1 ));
292
292
EISA_DBG ("pic0 edge/level %02x\n" , eisa_in8 (0x4d0 ));
293
293
EISA_DBG ("pic1 edge/level %02x\n" , eisa_in8 (0x4d1 ));
294
-
294
+
295
295
spin_unlock_irqrestore (& eisa_irq_lock , flags );
296
296
}
297
297
@@ -305,7 +305,7 @@ static int __init eisa_probe(struct parisc_device *dev)
305
305
306
306
char * name = is_mongoose (dev ) ? "Mongoose" : "Wax" ;
307
307
308
- printk (KERN_INFO "%s EISA Adapter found at 0x%08lx\n" ,
308
+ printk (KERN_INFO "%s EISA Adapter found at 0x%08lx\n" ,
309
309
name , (unsigned long )dev -> hpa .start );
310
310
311
311
eisa_dev .hba .dev = dev ;
@@ -334,16 +334,16 @@ static int __init eisa_probe(struct parisc_device *dev)
334
334
result = request_irq (dev -> irq , eisa_irq , IRQF_SHARED , "EISA" , & eisa_dev );
335
335
if (result ) {
336
336
printk (KERN_ERR "EISA: request_irq failed!\n" );
337
- return result ;
337
+ goto error_release ;
338
338
}
339
-
339
+
340
340
/* Reserve IRQ2 */
341
341
setup_irq (2 , & irq2_action );
342
342
for (i = 0 ; i < 16 ; i ++ ) {
343
343
irq_set_chip_and_handler (i , & eisa_interrupt_type ,
344
344
handle_simple_irq );
345
345
}
346
-
346
+
347
347
EISA_bus = 1 ;
348
348
349
349
if (dev -> num_addrs ) {
@@ -358,6 +358,11 @@ static int __init eisa_probe(struct parisc_device *dev)
358
358
}
359
359
}
360
360
eisa_eeprom_addr = ioremap_nocache (eisa_dev .eeprom_addr , HPEE_MAX_LENGTH );
361
+ if (!eisa_eeprom_addr ) {
362
+ result = - ENOMEM ;
363
+ printk (KERN_ERR "EISA: ioremap_nocache failed!\n" );
364
+ goto error_free_irq ;
365
+ }
361
366
result = eisa_enumerator (eisa_dev .eeprom_addr , & eisa_dev .hba .io_space ,
362
367
& eisa_dev .hba .lmmio_space );
363
368
init_eisa_pic ();
@@ -372,11 +377,20 @@ static int __init eisa_probe(struct parisc_device *dev)
372
377
eisa_dev .root .dma_mask = 0xffffffff ; /* wild guess */
373
378
if (eisa_root_register (& eisa_dev .root )) {
374
379
printk (KERN_ERR "EISA: Failed to register EISA root\n" );
375
- return -1 ;
380
+ result = - ENOMEM ;
381
+ goto error_iounmap ;
376
382
}
377
383
}
378
-
384
+
379
385
return 0 ;
386
+
387
+ error_iounmap :
388
+ iounmap (eisa_eeprom_addr );
389
+ error_free_irq :
390
+ free_irq (dev -> irq , & eisa_dev );
391
+ error_release :
392
+ release_resource (& eisa_dev .hba .io_space );
393
+ return result ;
380
394
}
381
395
382
396
static const struct parisc_device_id eisa_tbl [] = {
@@ -404,7 +418,7 @@ void eisa_make_irq_level(int num)
404
418
{
405
419
if (eisa_irq_configured & (1 <<num )) {
406
420
printk (KERN_WARNING
407
- "IRQ %d polarity configured twice (last to level)\n" ,
421
+ "IRQ %d polarity configured twice (last to level)\n" ,
408
422
num );
409
423
}
410
424
eisa_irq_level |= (1 <<num ); /* set the corresponding bit */
@@ -414,7 +428,7 @@ void eisa_make_irq_level(int num)
414
428
void eisa_make_irq_edge (int num )
415
429
{
416
430
if (eisa_irq_configured & (1 <<num )) {
417
- printk (KERN_WARNING
431
+ printk (KERN_WARNING
418
432
"IRQ %d polarity configured twice (last to edge)\n" ,
419
433
num );
420
434
}
@@ -430,18 +444,18 @@ static int __init eisa_irq_setup(char *str)
430
444
EISA_DBG ("IRQ setup\n" );
431
445
while (cur != NULL ) {
432
446
char * pe ;
433
-
447
+
434
448
val = (int ) simple_strtoul (cur , & pe , 0 );
435
449
if (val > 15 || val < 0 ) {
436
450
printk (KERN_ERR "eisa: EISA irq value are 0-15\n" );
437
451
continue ;
438
452
}
439
- if (val == 2 ) {
453
+ if (val == 2 ) {
440
454
val = 9 ;
441
455
}
442
456
eisa_make_irq_edge (val ); /* clear the corresponding bit */
443
457
EISA_DBG ("setting IRQ %d to edge-triggered mode\n" , val );
444
-
458
+
445
459
if ((cur = strchr (cur , ',' ))) {
446
460
cur ++ ;
447
461
} else {
0 commit comments