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Ingo Molnar
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Merge tag 'efi-urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/mfleming/efi into efi/urgent
Pull EFI/arm64 fix from Matt Fleming: " * Fix a boot crash on arm64 caused by a recent commit to mark the EFI memory map as 'MEMBLOCK_NOMAP' which causes the regions to be omitted from the kernel direct mapping - Ard Biesheuvel " Signed-off-by: Ingo Molnar <mingo@kernel.org>
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‎Documentation/x86/protection-keys.txt

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Memory Protection Keys for Userspace (PKU aka PKEYs) is a CPU feature
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which will be found on future Intel CPUs.
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Memory Protection Keys provides a mechanism for enforcing page-based
5+
protections, but without requiring modification of the page tables
6+
when an application changes protection domains. It works by
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dedicating 4 previously ignored bits in each page table entry to a
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"protection key", giving 16 possible keys.
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There is also a new user-accessible register (PKRU) with two separate
11+
bits (Access Disable and Write Disable) for each key. Being a CPU
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register, PKRU is inherently thread-local, potentially giving each
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thread a different set of protections from every other thread.
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15+
There are two new instructions (RDPKRU/WRPKRU) for reading and writing
16+
to the new register. The feature is only available in 64-bit mode,
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even though there is theoretically space in the PAE PTEs. These
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permissions are enforced on data access only and have no effect on
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instruction fetches.
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=========================== Config Option ===========================
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This config option adds approximately 1.5kb of text. and 50 bytes of
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data to the executable. A workload which does large O_DIRECT reads
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of holes in XFS files was run to exercise get_user_pages_fast(). No
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performance delta was observed with the config option
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enabled or disabled.

‎Documentation/x86/topology.txt

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x86 Topology
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============
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This documents and clarifies the main aspects of x86 topology modelling and
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representation in the kernel. Update/change when doing changes to the
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respective code.
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The architecture-agnostic topology definitions are in
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Documentation/cputopology.txt. This file holds x86-specific
10+
differences/specialities which must not necessarily apply to the generic
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definitions. Thus, the way to read up on Linux topology on x86 is to start
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with the generic one and look at this one in parallel for the x86 specifics.
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Needless to say, code should use the generic functions - this file is *only*
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here to *document* the inner workings of x86 topology.
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Started by Thomas Gleixner <tglx@linutronix.de> and Borislav Petkov <bp@alien8.de>.
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The main aim of the topology facilities is to present adequate interfaces to
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code which needs to know/query/use the structure of the running system wrt
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threads, cores, packages, etc.
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The kernel does not care about the concept of physical sockets because a
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socket has no relevance to software. It's an electromechanical component. In
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the past a socket always contained a single package (see below), but with the
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advent of Multi Chip Modules (MCM) a socket can hold more than one package. So
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there might be still references to sockets in the code, but they are of
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historical nature and should be cleaned up.
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The topology of a system is described in the units of:
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- packages
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- cores
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- threads
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* Package:
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Packages contain a number of cores plus shared resources, e.g. DRAM
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controller, shared caches etc.
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AMD nomenclature for package is 'Node'.
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Package-related topology information in the kernel:
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- cpuinfo_x86.x86_max_cores:
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The number of cores in a package. This information is retrieved via CPUID.
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- cpuinfo_x86.phys_proc_id:
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The physical ID of the package. This information is retrieved via CPUID
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and deduced from the APIC IDs of the cores in the package.
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- cpuinfo_x86.logical_id:
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The logical ID of the package. As we do not trust BIOSes to enumerate the
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packages in a consistent way, we introduced the concept of logical package
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ID so we can sanely calculate the number of maximum possible packages in
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the system and have the packages enumerated linearly.
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- topology_max_packages():
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The maximum possible number of packages in the system. Helpful for per
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package facilities to preallocate per package information.
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* Cores:
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A core consists of 1 or more threads. It does not matter whether the threads
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are SMT- or CMT-type threads.
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AMDs nomenclature for a CMT core is "Compute Unit". The kernel always uses
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"core".
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Core-related topology information in the kernel:
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- smp_num_siblings:
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The number of threads in a core. The number of threads in a package can be
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calculated by:
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threads_per_package = cpuinfo_x86.x86_max_cores * smp_num_siblings
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84+
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* Threads:
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A thread is a single scheduling unit. It's the equivalent to a logical Linux
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CPU.
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AMDs nomenclature for CMT threads is "Compute Unit Core". The kernel always
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uses "thread".
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Thread-related topology information in the kernel:
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- topology_core_cpumask():
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The cpumask contains all online threads in the package to which a thread
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belongs.
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The number of online threads is also printed in /proc/cpuinfo "siblings."
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- topology_sibling_mask():
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The cpumask contains all online threads in the core to which a thread
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belongs.
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- topology_logical_package_id():
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The logical package ID to which a thread belongs.
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- topology_physical_package_id():
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The physical package ID to which a thread belongs.
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- topology_core_id();
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The ID of the core to which a thread belongs. It is also printed in /proc/cpuinfo
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"core_id."
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System topology examples
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Note:
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The alternative Linux CPU enumeration depends on how the BIOS enumerates the
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threads. Many BIOSes enumerate all threads 0 first and then all threads 1.
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That has the "advantage" that the logical Linux CPU numbers of threads 0 stay
129+
the same whether threads are enabled or not. That's merely an implementation
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detail and has no practical impact.
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1) Single Package, Single Core
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[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
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2) Single Package, Dual Core
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a) One thread per core
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[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
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-> [core 1] -> [thread 0] -> Linux CPU 1
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b) Two threads per core
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[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
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-> [thread 1] -> Linux CPU 1
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-> [core 1] -> [thread 0] -> Linux CPU 2
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-> [thread 1] -> Linux CPU 3
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Alternative enumeration:
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[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
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-> [thread 1] -> Linux CPU 2
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-> [core 1] -> [thread 0] -> Linux CPU 1
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-> [thread 1] -> Linux CPU 3
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AMD nomenclature for CMT systems:
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[node 0] -> [Compute Unit 0] -> [Compute Unit Core 0] -> Linux CPU 0
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-> [Compute Unit Core 1] -> Linux CPU 1
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-> [Compute Unit 1] -> [Compute Unit Core 0] -> Linux CPU 2
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-> [Compute Unit Core 1] -> Linux CPU 3
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4) Dual Package, Dual Core
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a) One thread per core
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[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
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-> [core 1] -> [thread 0] -> Linux CPU 1
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[package 1] -> [core 0] -> [thread 0] -> Linux CPU 2
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-> [core 1] -> [thread 0] -> Linux CPU 3
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b) Two threads per core
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[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
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-> [thread 1] -> Linux CPU 1
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-> [core 1] -> [thread 0] -> Linux CPU 2
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-> [thread 1] -> Linux CPU 3
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181+
[package 1] -> [core 0] -> [thread 0] -> Linux CPU 4
182+
-> [thread 1] -> Linux CPU 5
183+
-> [core 1] -> [thread 0] -> Linux CPU 6
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-> [thread 1] -> Linux CPU 7
185+
186+
Alternative enumeration:
187+
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[package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
189+
-> [thread 1] -> Linux CPU 4
190+
-> [core 1] -> [thread 0] -> Linux CPU 1
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-> [thread 1] -> Linux CPU 5
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193+
[package 1] -> [core 0] -> [thread 0] -> Linux CPU 2
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-> [thread 1] -> Linux CPU 6
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-> [core 1] -> [thread 0] -> Linux CPU 3
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-> [thread 1] -> Linux CPU 7
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AMD nomenclature for CMT systems:
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[node 0] -> [Compute Unit 0] -> [Compute Unit Core 0] -> Linux CPU 0
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-> [Compute Unit Core 1] -> Linux CPU 1
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-> [Compute Unit 1] -> [Compute Unit Core 0] -> Linux CPU 2
203+
-> [Compute Unit Core 1] -> Linux CPU 3
204+
205+
[node 1] -> [Compute Unit 0] -> [Compute Unit Core 0] -> Linux CPU 4
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-> [Compute Unit Core 1] -> Linux CPU 5
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-> [Compute Unit 1] -> [Compute Unit Core 0] -> Linux CPU 6
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-> [Compute Unit Core 1] -> Linux CPU 7

‎arch/x86/events/amd/core.c

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@@ -369,7 +369,7 @@ static int amd_pmu_cpu_prepare(int cpu)
369369

370370
WARN_ON_ONCE(cpuc->amd_nb);
371371

372-
if (boot_cpu_data.x86_max_cores < 2)
372+
if (!x86_pmu.amd_nb_constraints)
373373
return NOTIFY_OK;
374374

375375
cpuc->amd_nb = amd_alloc_nb(cpu);
@@ -388,7 +388,7 @@ static void amd_pmu_cpu_starting(int cpu)
388388

389389
cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY;
390390

391-
if (boot_cpu_data.x86_max_cores < 2)
391+
if (!x86_pmu.amd_nb_constraints)
392392
return;
393393

394394
nb_id = amd_get_nb_id(cpu);
@@ -414,7 +414,7 @@ static void amd_pmu_cpu_dead(int cpu)
414414
{
415415
struct cpu_hw_events *cpuhw;
416416

417-
if (boot_cpu_data.x86_max_cores < 2)
417+
if (!x86_pmu.amd_nb_constraints)
418418
return;
419419

420420
cpuhw = &per_cpu(cpu_hw_events, cpu);
@@ -648,6 +648,8 @@ static __initconst const struct x86_pmu amd_pmu = {
648648
.cpu_prepare = amd_pmu_cpu_prepare,
649649
.cpu_starting = amd_pmu_cpu_starting,
650650
.cpu_dead = amd_pmu_cpu_dead,
651+
652+
.amd_nb_constraints = 1,
651653
};
652654

653655
static int __init amd_core_pmu_init(void)
@@ -674,6 +676,11 @@ static int __init amd_core_pmu_init(void)
674676
x86_pmu.eventsel = MSR_F15H_PERF_CTL;
675677
x86_pmu.perfctr = MSR_F15H_PERF_CTR;
676678
x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE;
679+
/*
680+
* AMD Core perfctr has separate MSRs for the NB events, see
681+
* the amd/uncore.c driver.
682+
*/
683+
x86_pmu.amd_nb_constraints = 0;
677684

678685
pr_cont("core perfctr, ");
679686
return 0;
@@ -693,6 +700,14 @@ __init int amd_pmu_init(void)
693700
if (ret)
694701
return ret;
695702

703+
if (num_possible_cpus() == 1) {
704+
/*
705+
* No point in allocating data structures to serialize
706+
* against other CPUs, when there is only the one CPU.
707+
*/
708+
x86_pmu.amd_nb_constraints = 0;
709+
}
710+
696711
/* Events are common for all AMDs */
697712
memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
698713
sizeof(hw_cache_event_ids));

‎arch/x86/events/perf_event.h

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@@ -607,6 +607,11 @@ struct x86_pmu {
607607
*/
608608
atomic_t lbr_exclusive[x86_lbr_exclusive_max];
609609

610+
/*
611+
* AMD bits
612+
*/
613+
unsigned int amd_nb_constraints : 1;
614+
610615
/*
611616
* Extra registers for events
612617
*/

‎arch/x86/include/asm/msr-index.h

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@@ -190,6 +190,7 @@
190190
#define MSR_PP1_ENERGY_STATUS 0x00000641
191191
#define MSR_PP1_POLICY 0x00000642
192192

193+
/* Config TDP MSRs */
193194
#define MSR_CONFIG_TDP_NOMINAL 0x00000648
194195
#define MSR_CONFIG_TDP_LEVEL_1 0x00000649
195196
#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A
@@ -210,13 +211,6 @@
210211
#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0
211212
#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1
212213

213-
/* Config TDP MSRs */
214-
#define MSR_CONFIG_TDP_NOMINAL 0x00000648
215-
#define MSR_CONFIG_TDP_LEVEL1 0x00000649
216-
#define MSR_CONFIG_TDP_LEVEL2 0x0000064A
217-
#define MSR_CONFIG_TDP_CONTROL 0x0000064B
218-
#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C
219-
220214
/* Hardware P state interface */
221215
#define MSR_PPERF 0x0000064e
222216
#define MSR_PERF_LIMIT_REASONS 0x0000064f

‎arch/x86/include/asm/processor.h

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@@ -132,8 +132,6 @@ struct cpuinfo_x86 {
132132
u16 logical_proc_id;
133133
/* Core id: */
134134
u16 cpu_core_id;
135-
/* Compute unit id */
136-
u8 compute_unit_id;
137135
/* Index into per_cpu list: */
138136
u16 cpu_index;
139137
u32 microcode;

‎arch/x86/include/asm/smp.h

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@@ -155,6 +155,7 @@ static inline int wbinvd_on_all_cpus(void)
155155
wbinvd();
156156
return 0;
157157
}
158+
#define smp_num_siblings 1
158159
#endif /* CONFIG_SMP */
159160

160161
extern unsigned disabled_cpus;

‎arch/x86/include/asm/thread_info.h

Lines changed: 2 additions & 4 deletions
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@@ -276,11 +276,9 @@ static inline bool is_ia32_task(void)
276276
*/
277277
#define force_iret() set_thread_flag(TIF_NOTIFY_RESUME)
278278

279-
#endif /* !__ASSEMBLY__ */
280-
281-
#ifndef __ASSEMBLY__
282279
extern void arch_task_cache_init(void);
283280
extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
284281
extern void arch_release_task_struct(struct task_struct *tsk);
285-
#endif
282+
#endif /* !__ASSEMBLY__ */
283+
286284
#endif /* _ASM_X86_THREAD_INFO_H */

‎arch/x86/kernel/amd_nb.c

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -170,15 +170,13 @@ int amd_get_subcaches(int cpu)
170170
{
171171
struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
172172
unsigned int mask;
173-
int cuid;
174173

175174
if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
176175
return 0;
177176

178177
pci_read_config_dword(link, 0x1d4, &mask);
179178

180-
cuid = cpu_data(cpu).compute_unit_id;
181-
return (mask >> (4 * cuid)) & 0xf;
179+
return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
182180
}
183181

184182
int amd_set_subcaches(int cpu, unsigned long mask)
@@ -204,7 +202,7 @@ int amd_set_subcaches(int cpu, unsigned long mask)
204202
pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
205203
}
206204

207-
cuid = cpu_data(cpu).compute_unit_id;
205+
cuid = cpu_data(cpu).cpu_core_id;
208206
mask <<= 4 * cuid;
209207
mask |= (0xf ^ (1 << cuid)) << 26;
210208

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