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cpufreq: ap806: add cpufreq driver for Armada 8K
Add cpufreq driver for Marvell AP-806 found on Aramda 8K. The AP-806 has DFS (Dynamic Frequency Scaling) with coupled clock domain for two clusters, so this driver will directly use generic cpufreq-dt driver as backend. Based on the work of Omri Itach <omrii@marvell.com>. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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‎drivers/cpufreq/Kconfig.arm

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@@ -25,6 +25,17 @@ config ARM_ARMADA_37XX_CPUFREQ
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This adds the CPUFreq driver support for Marvell Armada 37xx SoCs.
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The Armada 37xx PMU supports 4 frequency and VDD levels.
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config ARM_ARMADA_8K_CPUFREQ
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tristate "Armada 8K CPUFreq driver"
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depends on ARCH_MVEBU && CPUFREQ_DT
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help
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This enables the CPUFreq driver support for Marvell
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Armada8k SOCs.
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Armada8K device has the AP806 which supports scaling
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to any full integer divider.
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If in doubt, say N.
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# big LITTLE core layer and glue drivers
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config ARM_BIG_LITTLE_CPUFREQ
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tristate "Generic ARM big LITTLE CPUfreq driver"

‎drivers/cpufreq/Makefile

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@@ -50,6 +50,7 @@ obj-$(CONFIG_X86_SFI_CPUFREQ) += sfi-cpufreq.o
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obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ) += arm_big_little.o
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obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o
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obj-$(CONFIG_ARM_ARMADA_8K_CPUFREQ) += armada-8k-cpufreq.o
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obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o
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obj-$(CONFIG_ACPI_CPPC_CPUFREQ) += cppc_cpufreq.o
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obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o

‎drivers/cpufreq/armada-8k-cpufreq.c

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// SPDX-License-Identifier: GPL-2.0+
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/*
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* CPUFreq support for Armada 8K
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*
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* Copyright (C) 2018 Marvell
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*
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* Omri Itach <omrii@marvell.com>
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* Gregory Clement <gregory.clement@bootlin.com>
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/cpu.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/slab.h>
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/*
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* Setup the opps list with the divider for the max frequency, that
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* will be filled at runtime.
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*/
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static const int opps_div[] __initconst = {1, 2, 3, 4};
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static struct platform_device *armada_8k_pdev;
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struct freq_table {
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struct device *cpu_dev;
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unsigned int freq[ARRAY_SIZE(opps_div)];
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};
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/* If the CPUs share the same clock, then they are in the same cluster. */
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static void __init armada_8k_get_sharing_cpus(struct clk *cur_clk,
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struct cpumask *cpumask)
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{
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int cpu;
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for_each_possible_cpu(cpu) {
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struct device *cpu_dev;
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struct clk *clk;
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cpu_dev = get_cpu_device(cpu);
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if (!cpu_dev) {
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pr_warn("Failed to get cpu%d device\n", cpu);
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continue;
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}
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clk = clk_get(cpu_dev, 0);
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if (IS_ERR(clk)) {
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pr_warn("Cannot get clock for CPU %d\n", cpu);
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} else {
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if (clk_is_match(clk, cur_clk))
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cpumask_set_cpu(cpu, cpumask);
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clk_put(clk);
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}
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}
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}
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static int __init armada_8k_add_opp(struct clk *clk, struct device *cpu_dev,
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struct freq_table *freq_tables,
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int opps_index)
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{
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unsigned int cur_frequency;
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unsigned int freq;
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int i, ret;
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/* Get nominal (current) CPU frequency. */
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cur_frequency = clk_get_rate(clk);
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if (!cur_frequency) {
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dev_err(cpu_dev, "Failed to get clock rate for this CPU\n");
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return -EINVAL;
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}
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freq_tables[opps_index].cpu_dev = cpu_dev;
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for (i = 0; i < ARRAY_SIZE(opps_div); i++) {
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freq = cur_frequency / opps_div[i];
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ret = dev_pm_opp_add(cpu_dev, freq, 0);
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if (ret)
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return ret;
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freq_tables[opps_index].freq[i] = freq;
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}
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return 0;
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}
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static void armada_8k_cpufreq_free_table(struct freq_table *freq_tables)
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{
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int opps_index, nb_cpus = num_possible_cpus();
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for (opps_index = 0 ; opps_index <= nb_cpus; opps_index++) {
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int i;
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/* If cpu_dev is NULL then we reached the end of the array */
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if (!freq_tables[opps_index].cpu_dev)
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break;
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for (i = 0; i < ARRAY_SIZE(opps_div); i++) {
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/*
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* A 0Hz frequency is not valid, this meant
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* that it was not yet initialized so there is
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* no more opp to free
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*/
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if (freq_tables[opps_index].freq[i] == 0)
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break;
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dev_pm_opp_remove(freq_tables[opps_index].cpu_dev,
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freq_tables[opps_index].freq[i]);
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}
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}
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kfree(freq_tables);
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}
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static int __init armada_8k_cpufreq_init(void)
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{
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int ret = 0, opps_index = 0, cpu, nb_cpus;
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struct freq_table *freq_tables;
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struct device_node *node;
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struct cpumask cpus;
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node = of_find_compatible_node(NULL, NULL, "marvell,ap806-cpu-clock");
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if (!node || !of_device_is_available(node))
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return -ENODEV;
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nb_cpus = num_possible_cpus();
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freq_tables = kcalloc(nb_cpus, sizeof(*freq_tables), GFP_KERNEL);
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cpumask_copy(&cpus, cpu_possible_mask);
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/*
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* For each CPU, this loop registers the operating points
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* supported (which are the nominal CPU frequency and full integer
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* divisions of it).
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*/
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for_each_cpu(cpu, &cpus) {
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struct cpumask shared_cpus;
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struct device *cpu_dev;
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struct clk *clk;
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cpu_dev = get_cpu_device(cpu);
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if (!cpu_dev) {
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pr_err("Cannot get CPU %d\n", cpu);
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continue;
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}
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clk = clk_get(cpu_dev, 0);
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if (IS_ERR(clk)) {
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pr_err("Cannot get clock for CPU %d\n", cpu);
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ret = PTR_ERR(clk);
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goto remove_opp;
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}
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ret = armada_8k_add_opp(clk, cpu_dev, freq_tables, opps_index);
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if (ret) {
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clk_put(clk);
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goto remove_opp;
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}
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opps_index++;
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cpumask_clear(&shared_cpus);
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armada_8k_get_sharing_cpus(clk, &shared_cpus);
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dev_pm_opp_set_sharing_cpus(cpu_dev, &shared_cpus);
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cpumask_andnot(&cpus, &cpus, &shared_cpus);
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clk_put(clk);
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}
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armada_8k_pdev = platform_device_register_simple("cpufreq-dt", -1,
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NULL, 0);
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ret = PTR_ERR_OR_ZERO(armada_8k_pdev);
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if (ret)
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goto remove_opp;
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platform_set_drvdata(armada_8k_pdev, freq_tables);
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return 0;
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remove_opp:
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armada_8k_cpufreq_free_table(freq_tables);
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return ret;
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}
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module_init(armada_8k_cpufreq_init);
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static void __exit armada_8k_cpufreq_exit(void)
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{
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struct freq_table *freq_tables = platform_get_drvdata(armada_8k_pdev);
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platform_device_unregister(armada_8k_pdev);
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armada_8k_cpufreq_free_table(freq_tables);
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}
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module_exit(armada_8k_cpufreq_exit);
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MODULE_AUTHOR("Gregory Clement <gregory.clement@bootlin.com>");
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MODULE_DESCRIPTION("Armada 8K cpufreq driver");
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MODULE_LICENSE("GPL");

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