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Andrey Grodzovskyalexdeucher
Andrey Grodzovsky
authored and
alexdeucher
committed
drm/amdgpu: Add support for SRBM selection v3
Also remove code duplication in write and read regs functions. This also fixes potential missing unlock in amdgpu_debugfs_regs_write in case get_user would fail. v2: Add SRBM mutex locking. v3: Fix TO counter and fix comment location. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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+72
-79
lines changed

6 files changed

+72
-79
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -890,6 +890,7 @@ struct amdgpu_gfx_funcs {
890890
void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
891891
void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
892892
void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
893+
void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue);
893894
};
894895

895896
struct amdgpu_ngg_buf {
@@ -1812,6 +1813,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
18121813
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
18131814
#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
18141815
#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
1816+
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
18151817

18161818
/* Common functions */
18171819
int amdgpu_device_gpu_recover(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

Lines changed: 40 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -64,16 +64,21 @@ int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
6464

6565
#if defined(CONFIG_DEBUG_FS)
6666

67-
static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
68-
size_t size, loff_t *pos)
67+
68+
static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
69+
char __user *buf, size_t size, loff_t *pos)
6970
{
7071
struct amdgpu_device *adev = file_inode(f)->i_private;
7172
ssize_t result = 0;
7273
int r;
73-
bool pm_pg_lock, use_bank;
74-
unsigned instance_bank, sh_bank, se_bank;
74+
bool pm_pg_lock, use_bank, use_ring;
75+
unsigned instance_bank, sh_bank, se_bank, me, pipe, queue;
7576

76-
if (size & 0x3 || *pos & 0x3)
77+
pm_pg_lock = use_bank = use_ring = false;
78+
instance_bank = sh_bank = se_bank = me = pipe = queue = 0;
79+
80+
if (size & 0x3 || *pos & 0x3 ||
81+
((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
7782
return -EINVAL;
7883

7984
/* are we reading registers for which a PG lock is necessary? */
@@ -91,8 +96,15 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
9196
if (instance_bank == 0x3FF)
9297
instance_bank = 0xFFFFFFFF;
9398
use_bank = 1;
99+
} else if (*pos & (1ULL << 61)) {
100+
101+
me = (*pos & GENMASK_ULL(33, 24)) >> 24;
102+
pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
103+
queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
104+
105+
use_ring = 1;
94106
} else {
95-
use_bank = 0;
107+
use_bank = use_ring = 0;
96108
}
97109

98110
*pos &= (1UL << 22) - 1;
@@ -104,6 +116,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
104116
mutex_lock(&adev->grbm_idx_mutex);
105117
amdgpu_gfx_select_se_sh(adev, se_bank,
106118
sh_bank, instance_bank);
119+
} else if (use_ring) {
120+
mutex_lock(&adev->srbm_mutex);
121+
amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue);
107122
}
108123

109124
if (pm_pg_lock)
@@ -115,8 +130,14 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
115130
if (*pos > adev->rmmio_size)
116131
goto end;
117132

118-
value = RREG32(*pos >> 2);
119-
r = put_user(value, (uint32_t *)buf);
133+
if (read) {
134+
value = RREG32(*pos >> 2);
135+
r = put_user(value, (uint32_t *)buf);
136+
} else {
137+
r = get_user(value, (uint32_t *)buf);
138+
if (!r)
139+
WREG32(*pos >> 2, value);
140+
}
120141
if (r) {
121142
result = r;
122143
goto end;
@@ -132,6 +153,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
132153
if (use_bank) {
133154
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
134155
mutex_unlock(&adev->grbm_idx_mutex);
156+
} else if (use_ring) {
157+
amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0);
158+
mutex_unlock(&adev->srbm_mutex);
135159
}
136160

137161
if (pm_pg_lock)
@@ -140,78 +164,17 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
140164
return result;
141165
}
142166

167+
168+
static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
169+
size_t size, loff_t *pos)
170+
{
171+
return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
172+
}
173+
143174
static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
144175
size_t size, loff_t *pos)
145176
{
146-
struct amdgpu_device *adev = file_inode(f)->i_private;
147-
ssize_t result = 0;
148-
int r;
149-
bool pm_pg_lock, use_bank;
150-
unsigned instance_bank, sh_bank, se_bank;
151-
152-
if (size & 0x3 || *pos & 0x3)
153-
return -EINVAL;
154-
155-
/* are we reading registers for which a PG lock is necessary? */
156-
pm_pg_lock = (*pos >> 23) & 1;
157-
158-
if (*pos & (1ULL << 62)) {
159-
se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
160-
sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
161-
instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
162-
163-
if (se_bank == 0x3FF)
164-
se_bank = 0xFFFFFFFF;
165-
if (sh_bank == 0x3FF)
166-
sh_bank = 0xFFFFFFFF;
167-
if (instance_bank == 0x3FF)
168-
instance_bank = 0xFFFFFFFF;
169-
use_bank = 1;
170-
} else {
171-
use_bank = 0;
172-
}
173-
174-
*pos &= (1UL << 22) - 1;
175-
176-
if (use_bank) {
177-
if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
178-
(se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
179-
return -EINVAL;
180-
mutex_lock(&adev->grbm_idx_mutex);
181-
amdgpu_gfx_select_se_sh(adev, se_bank,
182-
sh_bank, instance_bank);
183-
}
184-
185-
if (pm_pg_lock)
186-
mutex_lock(&adev->pm.mutex);
187-
188-
while (size) {
189-
uint32_t value;
190-
191-
if (*pos > adev->rmmio_size)
192-
return result;
193-
194-
r = get_user(value, (uint32_t *)buf);
195-
if (r)
196-
return r;
197-
198-
WREG32(*pos >> 2, value);
199-
200-
result += 4;
201-
buf += 4;
202-
*pos += 4;
203-
size -= 4;
204-
}
205-
206-
if (use_bank) {
207-
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
208-
mutex_unlock(&adev->grbm_idx_mutex);
209-
}
210-
211-
if (pm_pg_lock)
212-
mutex_unlock(&adev->pm.mutex);
213-
214-
return result;
177+
return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
215178
}
216179

217180
static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,

‎drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3061,11 +3061,18 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
30613061
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
30623062
}
30633063

3064+
static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3065+
u32 me, u32 pipe, u32 q)
3066+
{
3067+
DRM_INFO("Not implemented\n");
3068+
}
3069+
30643070
static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
30653071
.get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
30663072
.select_se_sh = &gfx_v6_0_select_se_sh,
30673073
.read_wave_data = &gfx_v6_0_read_wave_data,
30683074
.read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3075+
.select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
30693076
};
30703077

30713078
static int gfx_v6_0_early_init(void *handle)

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4270,11 +4270,18 @@ static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
42704270
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
42714271
}
42724272

4273+
static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
4274+
u32 me, u32 pipe, u32 q)
4275+
{
4276+
cik_srbm_select(adev, me, pipe, q, 0);
4277+
}
4278+
42734279
static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
42744280
.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
42754281
.select_se_sh = &gfx_v7_0_select_se_sh,
42764282
.read_wave_data = &gfx_v7_0_read_wave_data,
42774283
.read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4284+
.select_me_pipe_q = &gfx_v7_0_select_me_pipe_q
42784285
};
42794286

42804287
static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3475,6 +3475,12 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
34753475
WREG32(mmGRBM_GFX_INDEX, data);
34763476
}
34773477

3478+
static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3479+
u32 me, u32 pipe, u32 q)
3480+
{
3481+
vi_srbm_select(adev, me, pipe, q, 0);
3482+
}
3483+
34783484
static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
34793485
{
34803486
u32 data, mask;
@@ -5442,6 +5448,7 @@ static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
54425448
.select_se_sh = &gfx_v8_0_select_se_sh,
54435449
.read_wave_data = &gfx_v8_0_read_wave_data,
54445450
.read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5451+
.select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
54455452
};
54465453

54475454
static int gfx_v8_0_early_init(void *handle)

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -998,12 +998,19 @@ static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
998998
start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
999999
}
10001000

1001+
static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1002+
u32 me, u32 pipe, u32 q)
1003+
{
1004+
soc15_grbm_select(adev, me, pipe, q, 0);
1005+
}
1006+
10011007
static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
10021008
.get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
10031009
.select_se_sh = &gfx_v9_0_select_se_sh,
10041010
.read_wave_data = &gfx_v9_0_read_wave_data,
10051011
.read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
10061012
.read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1013+
.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
10071014
};
10081015

10091016
static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
@@ -2773,13 +2780,13 @@ static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
27732780
udelay(1);
27742781
}
27752782

2776-
if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
2783+
if (j == AMDGPU_MAX_USEC_TIMEOUT) {
27772784
DRM_DEBUG("KIQ dequeue request failed.\n");
27782785

2786+
/* Manual disable if dequeue request times out */
27792787
WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
27802788
}
27812789

2782-
/* Manual disable if dequeue request times out */
27832790
WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
27842791
0);
27852792
}

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