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MIPS: Abstract CPU core & VP(E) ID access through accessor functions
We currently have fields in struct cpuinfo_mips for the core & VP(E) ID of a particular CPU, and various pieces of code directly access those fields. This patch abstracts such access by introducing accessor functions cpu_core(), cpu_set_core(), cpu_vpe_id() & cpu_set_vpe_id() and having code that needs to access these values call those functions rather than directly accessing the struct cpuinfo_mips fields. This prepares us for changes to the way in which those values are stored in later patches. The cpu_vpe_id() function is introduced even though we already had a cpu_vpe_id() macro for a couple of reasons: 1) It's more consistent with the core, and future cluster, accessors. 2) It ensures a sensible return type without explicit casts. 3) It's generally preferable to use functions rather than macros. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17009/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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-46
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16 files changed

+71
-46
lines changed

‎arch/mips/include/asm/cpu-info.h

Lines changed: 24 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -144,11 +144,32 @@ struct proc_cpuinfo_notifier_args {
144144
unsigned long n;
145145
};
146146

147+
static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
148+
{
149+
return cpuinfo->core;
150+
}
151+
152+
static inline void cpu_set_core(struct cpuinfo_mips *cpuinfo,
153+
unsigned int core)
154+
{
155+
cpuinfo->core = core;
156+
}
157+
158+
static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
159+
{
147160
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
148-
# define cpu_vpe_id(cpuinfo) ((cpuinfo)->vpe_id)
149-
#else
150-
# define cpu_vpe_id(cpuinfo) ({ (void)cpuinfo; 0; })
161+
return cpuinfo->vpe_id;
151162
#endif
163+
return 0;
164+
}
165+
166+
static inline void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo,
167+
unsigned int vpe)
168+
{
169+
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
170+
cpuinfo->vpe_id = vpe;
171+
#endif
172+
}
152173

153174
static inline unsigned long cpu_asid_inc(void)
154175
{

‎arch/mips/include/asm/mips-cm.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -428,7 +428,7 @@ static inline unsigned int mips_cm_max_vp_width(void)
428428
*/
429429
static inline unsigned int mips_cm_vp_id(unsigned int cpu)
430430
{
431-
unsigned int core = cpu_data[cpu].core;
431+
unsigned int core = cpu_core(&cpu_data[cpu]);
432432
unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
433433

434434
return (core * mips_cm_max_vp_width()) + vp;

‎arch/mips/include/asm/topology.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313

1414
#ifdef CONFIG_SMP
1515
#define topology_physical_package_id(cpu) (cpu_data[cpu].package)
16-
#define topology_core_id(cpu) (cpu_data[cpu].core)
16+
#define topology_core_id(cpu) (cpu_core(&cpu_data[cpu]))
1717
#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
1818
#define topology_sibling_cpumask(cpu) (&cpu_sibling_map[cpu])
1919
#endif

‎arch/mips/kernel/cpu-probe.c

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -919,9 +919,12 @@ static void decode_configs(struct cpuinfo_mips *c)
919919

920920
#ifndef CONFIG_MIPS_CPS
921921
if (cpu_has_mips_r2_r6) {
922-
c->core = get_ebase_cpunum();
922+
unsigned int core;
923+
924+
core = get_ebase_cpunum();
923925
if (cpu_has_mipsmt)
924-
c->core >>= fls(core_nvpes()) - 1;
926+
core >>= fls(core_nvpes()) - 1;
927+
cpu_set_core(c, core);
925928
}
926929
#endif
927930
}

‎arch/mips/kernel/mips-cm.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -287,7 +287,7 @@ void mips_cm_lock_other(unsigned int core, unsigned int vp)
287287
* CM 2.5 & older, so have to ensure other VP(E)s don't
288288
* race with us.
289289
*/
290-
curr_core = current_cpu_data.core;
290+
curr_core = cpu_core(&current_cpu_data);
291291
spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
292292
per_cpu(cm_core_lock_flags, curr_core));
293293

@@ -308,7 +308,7 @@ void mips_cm_unlock_other(void)
308308
unsigned int curr_core;
309309

310310
if (mips_cm_revision() < CM_REV_CM3) {
311-
curr_core = current_cpu_data.core;
311+
curr_core = cpu_core(&current_cpu_data);
312312
spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
313313
per_cpu(cm_core_lock_flags, curr_core));
314314
} else {

‎arch/mips/kernel/mips-cpc.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ void mips_cpc_lock_other(unsigned int core)
8686
return;
8787

8888
preempt_disable();
89-
curr_core = current_cpu_data.core;
89+
curr_core = cpu_core(&current_cpu_data);
9090
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
9191
per_cpu(cpc_core_lock_flags, curr_core));
9292
write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
@@ -106,7 +106,7 @@ void mips_cpc_unlock_other(void)
106106
/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
107107
return;
108108

109-
curr_core = current_cpu_data.core;
109+
curr_core = cpu_core(&current_cpu_data);
110110
spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
111111
per_cpu(cpc_core_lock_flags, curr_core));
112112
preempt_enable();

‎arch/mips/kernel/pm-cps.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,7 @@ static void coupled_barrier(atomic_t *a, unsigned online)
114114
int cps_pm_enter_state(enum cps_pm_state state)
115115
{
116116
unsigned cpu = smp_processor_id();
117-
unsigned core = current_cpu_data.core;
117+
unsigned core = cpu_core(&current_cpu_data);
118118
unsigned online, left;
119119
cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled);
120120
u32 *core_ready_count, *nc_core_ready_count;
@@ -486,7 +486,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
486486
* defined by the interAptiv & proAptiv SUMs as ensuring that the
487487
* operation resulting from the preceding store is complete.
488488
*/
489-
uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core);
489+
uasm_i_addiu(&p, t0, zero, 1 << cpu_core(&cpu_data[cpu]));
490490
uasm_i_sw(&p, t0, 0, r_pcohctl);
491491
uasm_i_lw(&p, t0, 0, r_pcohctl);
492492

@@ -640,7 +640,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
640640
static int cps_pm_online_cpu(unsigned int cpu)
641641
{
642642
enum cps_pm_state state;
643-
unsigned core = cpu_data[cpu].core;
643+
unsigned core = cpu_core(&cpu_data[cpu]);
644644
void *entry_fn, *core_rc;
645645

646646
for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {

‎arch/mips/kernel/proc.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -134,13 +134,13 @@ static int show_cpuinfo(struct seq_file *m, void *v)
134134
seq_printf(m, "kscratch registers\t: %d\n",
135135
hweight8(cpu_data[n].kscratch_mask));
136136
seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
137-
seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
137+
seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
138138

139139
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
140140
if (cpu_has_mipsmt)
141-
seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
141+
seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
142142
else if (cpu_has_vp)
143-
seq_printf(m, "VP\t\t\t: %d\n", cpu_data[n].vpe_id);
143+
seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
144144
#endif
145145

146146
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",

‎arch/mips/kernel/smp-bmips.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ static void bmips_init_secondary(void)
245245
break;
246246
case CPU_BMIPS5000:
247247
write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
248-
current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3;
248+
cpu_set_core(&current_cpu_data, (read_c0_brcm_config() >> 25) & 3);
249249
break;
250250
}
251251
}

‎arch/mips/kernel/smp-cps.c

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -76,10 +76,8 @@ static void __init cps_smp_setup(void)
7676
smp_num_siblings = core_vpes;
7777

7878
for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
79-
cpu_data[nvpes + v].core = c;
80-
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
81-
cpu_data[nvpes + v].vpe_id = v;
82-
#endif
79+
cpu_set_core(&cpu_data[nvpes + v], c);
80+
cpu_set_vpe_id(&cpu_data[nvpes + v], v);
8381
}
8482

8583
nvpes += core_vpes;
@@ -149,7 +147,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
149147
cpu_has_dc_aliases ? "dcache aliasing" : "");
150148

151149
for_each_present_cpu(c) {
152-
if (cpu_data[c].core)
150+
if (cpu_core(&cpu_data[c]))
153151
set_cpu_present(c, false);
154152
}
155153
}
@@ -189,7 +187,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
189187
}
190188

191189
/* Mark this CPU as booted */
192-
atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
190+
atomic_set(&mips_cps_core_bootcfg[cpu_core(&current_cpu_data)].vpe_mask,
193191
1 << cpu_vpe_id(&current_cpu_data));
194192

195193
return;
@@ -284,15 +282,15 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
284282

285283
static void remote_vpe_boot(void *dummy)
286284
{
287-
unsigned core = current_cpu_data.core;
285+
unsigned core = cpu_core(&current_cpu_data);
288286
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
289287

290288
mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
291289
}
292290

293291
static void cps_boot_secondary(int cpu, struct task_struct *idle)
294292
{
295-
unsigned core = cpu_data[cpu].core;
293+
unsigned core = cpu_core(&cpu_data[cpu]);
296294
unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
297295
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
298296
struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
@@ -321,10 +319,10 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle)
321319
mips_cm_unlock_other();
322320
}
323321

324-
if (core != current_cpu_data.core) {
322+
if (core != cpu_core(&current_cpu_data)) {
325323
/* Boot a VPE on another powered up core */
326324
for (remote = 0; remote < NR_CPUS; remote++) {
327-
if (cpu_data[remote].core != core)
325+
if (cpu_core(&cpu_data[remote]) != core)
328326
continue;
329327
if (cpu_online(remote))
330328
break;
@@ -401,7 +399,7 @@ static int cps_cpu_disable(void)
401399
if (!cps_pm_support_state(CPS_PM_POWER_GATED))
402400
return -EINVAL;
403401

404-
core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
402+
core_cfg = &mips_cps_core_bootcfg[cpu_core(&current_cpu_data)];
405403
atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
406404
smp_mb__after_atomic();
407405
set_cpu_online(cpu, false);
@@ -423,15 +421,17 @@ void play_dead(void)
423421
local_irq_disable();
424422
idle_task_exit();
425423
cpu = smp_processor_id();
426-
core = cpu_data[cpu].core;
424+
core = cpu_core(&cpu_data[cpu]);
427425
cpu_death = CPU_DEATH_POWER;
428426

429427
pr_debug("CPU%d going offline\n", cpu);
430428

431429
if (cpu_has_mipsmt || cpu_has_vp) {
430+
core = cpu_core(&cpu_data[cpu]);
431+
432432
/* Look for another online VPE within the core */
433433
for_each_online_cpu(cpu_death_sibling) {
434-
if (cpu_data[cpu_death_sibling].core != core)
434+
if (cpu_core(&cpu_data[cpu_death_sibling]) != core)
435435
continue;
436436

437437
/*
@@ -487,7 +487,7 @@ static void wait_for_sibling_halt(void *ptr_cpu)
487487

488488
static void cps_cpu_die(unsigned int cpu)
489489
{
490-
unsigned core = cpu_data[cpu].core;
490+
unsigned core = cpu_core(&cpu_data[cpu]);
491491
unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
492492
ktime_t fail_time;
493493
unsigned stat;

‎arch/mips/kernel/smp-mt.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
8383
if (tc != 0)
8484
smvp_copy_vpe_config();
8585

86-
cpu_data[ncpu].vpe_id = tc;
86+
cpu_set_vpe_id(&cpu_data[ncpu], tc);
8787

8888
return ncpu;
8989
}

‎arch/mips/kernel/smp.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ static inline void set_cpu_sibling_map(int cpu)
9797
if (smp_num_siblings > 1) {
9898
for_each_cpu(i, &cpu_sibling_setup_map) {
9999
if (cpu_data[cpu].package == cpu_data[i].package &&
100-
cpu_data[cpu].core == cpu_data[i].core) {
100+
cpu_core(&cpu_data[cpu]) == cpu_core(&cpu_data[i])) {
101101
cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
102102
cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
103103
}
@@ -135,7 +135,7 @@ void calculate_cpu_foreign_map(void)
135135
core_present = 0;
136136
for_each_cpu(k, &temp_foreign_map)
137137
if (cpu_data[i].package == cpu_data[k].package &&
138-
cpu_data[i].core == cpu_data[k].core)
138+
cpu_core(&cpu_data[i]) == cpu_core(&cpu_data[k]))
139139
core_present = 1;
140140
if (!core_present)
141141
cpumask_set_cpu(i, &temp_foreign_map);
@@ -186,9 +186,9 @@ void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
186186

187187
if (mips_cpc_present()) {
188188
for_each_cpu(cpu, mask) {
189-
core = cpu_data[cpu].core;
189+
core = cpu_core(&cpu_data[cpu]);
190190

191-
if (core == current_cpu_data.core)
191+
if (core == cpu_core(&current_cpu_data))
192192
continue;
193193

194194
while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {

‎arch/mips/loongson64/loongson-3/smp.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -319,8 +319,8 @@ static void loongson3_init_secondary(void)
319319
loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
320320

321321
per_cpu(cpu_state, cpu) = CPU_ONLINE;
322-
cpu_data[cpu].core =
323-
cpu_logical_map(cpu) % loongson_sysconf.cores_per_package;
322+
cpu_set_core(&cpu_data[cpu],
323+
cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
324324
cpu_data[cpu].package =
325325
cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
326326

@@ -386,7 +386,8 @@ static void __init loongson3_smp_setup(void)
386386
ipi_status0_regs_init();
387387
ipi_en0_regs_init();
388388
ipi_mailbox_buf_init();
389-
cpu_data[0].core = cpu_logical_map(0) % loongson_sysconf.cores_per_package;
389+
cpu_set_core(&cpu_data[0],
390+
cpu_logical_map(0) % loongson_sysconf.cores_per_package);
390391
cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
391392
}
392393

@@ -697,7 +698,7 @@ void play_dead(void)
697698

698699
static int loongson3_disable_clock(unsigned int cpu)
699700
{
700-
uint64_t core_id = cpu_data[cpu].core;
701+
uint64_t core_id = cpu_core(&cpu_data[cpu]);
701702
uint64_t package_id = cpu_data[cpu].package;
702703

703704
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
@@ -711,7 +712,7 @@ static int loongson3_disable_clock(unsigned int cpu)
711712

712713
static int loongson3_enable_clock(unsigned int cpu)
713714
{
714-
uint64_t core_id = cpu_data[cpu].core;
715+
uint64_t core_id = cpu_core(&cpu_data[cpu]);
715716
uint64_t package_id = cpu_data[cpu].package;
716717

717718
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {

‎arch/mips/netlogic/common/smp.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,7 @@ static void nlm_init_secondary(void)
122122
int hwtid;
123123

124124
hwtid = hard_smp_processor_id();
125-
current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
125+
cpu_set_core(&current_cpu_data, hwtid / NLM_THREADS_PER_CORE);
126126
current_cpu_data.package = nlm_nodeid();
127127
nlm_percpu_init(hwtid);
128128
nlm_smp_irq_init(hwtid);

‎arch/mips/oprofile/op_model_mipsxx.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,9 @@ static int perfcount_irq;
3838
#ifdef CONFIG_MIPS_MT_SMP
3939
static int cpu_has_mipsmt_pertccounters;
4040
#define WHAT (MIPS_PERFCTRL_MT_EN_VPE | \
41-
M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
41+
M_PERFCTL_VPEID(cpu_vpe_id(&current_cpu_data)))
4242
#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
43-
0 : cpu_data[smp_processor_id()].vpe_id)
43+
0 : cpu_vpe_id(&current_cpu_data))
4444

4545
/*
4646
* The number of bits to shift to convert between counters per core and

‎drivers/cpuidle/cpuidle-cps.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ static int cps_nc_enter(struct cpuidle_device *dev,
3737
* TODO: don't treat core 0 specially, just prevent the final core
3838
* TODO: remap interrupt affinity temporarily
3939
*/
40-
if (!cpu_data[dev->cpu].core && (index > STATE_NC_WAIT))
40+
if (!cpu_core(&cpu_data[dev->cpu]) && (index > STATE_NC_WAIT))
4141
index = STATE_NC_WAIT;
4242

4343
/* Select the appropriate cps_pm_state */

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