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Eyal DavidovichSaeed Mahameed
Eyal Davidovich
authored and
Saeed Mahameed
committed
net/mlx5: Add monitor commands layout and event data
Will be used in downstream patch to monitor counter changes by the HCA and report it to the driver by an event. The driver will update its counters cached data accordingly. Signed-off-by: Eyal Davidovich <eyald@mellanox.com> Reviewed-by: Eran Ben Elisha <eranbe@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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‎drivers/net/ethernet/mellanox/mlx5/core/cmd.c

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -373,6 +373,8 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
373373
case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
374374
case MLX5_CMD_OP_ALLOC_Q_COUNTER:
375375
case MLX5_CMD_OP_QUERY_Q_COUNTER:
376+
case MLX5_CMD_OP_SET_MONITOR_COUNTER:
377+
case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
376378
case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
377379
case MLX5_CMD_OP_QUERY_RATE_LIMIT:
378380
case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
@@ -522,6 +524,8 @@ const char *mlx5_command_str(int command)
522524
MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
523525
MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
524526
MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
527+
MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
528+
MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
525529
MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
526530
MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
527531
MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);

‎drivers/net/ethernet/mellanox/mlx5/core/eq.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -527,6 +527,9 @@ static u64 gather_async_events_mask(struct mlx5_core_dev *dev)
527527
if (MLX5_CAP_MCAM_REG(dev, tracer_registers))
528528
async_event_mask |= (1ull << MLX5_EVENT_TYPE_DEVICE_TRACER);
529529

530+
if (MLX5_CAP_GEN(dev, max_num_of_monitor_counters))
531+
async_event_mask |= (1ull << MLX5_EVENT_TYPE_MONITOR_COUNTER);
532+
530533
return async_event_mask;
531534
}
532535

‎drivers/net/ethernet/mellanox/mlx5/core/events.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,8 @@ static const char *eqe_type_str(u8 type)
117117
return "MLX5_EVENT_TYPE_FPGA_QP_ERROR";
118118
case MLX5_EVENT_TYPE_GENERAL_EVENT:
119119
return "MLX5_EVENT_TYPE_GENERAL_EVENT";
120+
case MLX5_EVENT_TYPE_MONITOR_COUNTER:
121+
return "MLX5_EVENT_TYPE_MONITOR_COUNTER";
120122
case MLX5_EVENT_TYPE_DEVICE_TRACER:
121123
return "MLX5_EVENT_TYPE_DEVICE_TRACER";
122124
default:

‎include/linux/mlx5/device.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -330,6 +330,7 @@ enum mlx5_event {
330330
MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
331331
MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
332332
MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
333+
MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
333334
MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
334335

335336
MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,

‎include/linux/mlx5/mlx5_ifc.h

Lines changed: 86 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -161,6 +161,8 @@ enum {
161161
MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
162162
MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
163163
MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
164+
MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
165+
MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
164166
MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
165167
MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
166168
MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
@@ -1200,7 +1202,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {
12001202
u8 sw_owner_id[0x1];
12011203
u8 reserved_at_61f[0x1];
12021204

1203-
u8 reserved_at_620[0x80];
1205+
u8 max_num_of_monitor_counters[0x10];
1206+
u8 num_ppcnt_monitor_counters[0x10];
1207+
1208+
u8 reserved_at_640[0x10];
1209+
u8 num_q_monitor_counters[0x10];
1210+
1211+
u8 reserved_at_660[0x40];
12041212

12051213
u8 uctx_cap[0x20];
12061214

@@ -3808,6 +3816,83 @@ enum {
38083816
MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
38093817
};
38103818

3819+
struct mlx5_ifc_arm_monitor_counter_in_bits {
3820+
u8 opcode[0x10];
3821+
u8 uid[0x10];
3822+
3823+
u8 reserved_at_20[0x10];
3824+
u8 op_mod[0x10];
3825+
3826+
u8 reserved_at_40[0x20];
3827+
3828+
u8 reserved_at_60[0x20];
3829+
};
3830+
3831+
struct mlx5_ifc_arm_monitor_counter_out_bits {
3832+
u8 status[0x8];
3833+
u8 reserved_at_8[0x18];
3834+
3835+
u8 syndrome[0x20];
3836+
3837+
u8 reserved_at_40[0x40];
3838+
};
3839+
3840+
enum {
3841+
MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
3842+
MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
3843+
};
3844+
3845+
enum mlx5_monitor_counter_ppcnt {
3846+
MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0X0,
3847+
MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0X1,
3848+
MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0X2,
3849+
MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0X3,
3850+
MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0X4,
3851+
MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0X5,
3852+
};
3853+
3854+
enum {
3855+
MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0X4,
3856+
};
3857+
3858+
struct mlx5_ifc_monitor_counter_output_bits {
3859+
u8 reserved_at_0[0x4];
3860+
u8 type[0x4];
3861+
u8 reserved_at_8[0x8];
3862+
u8 counter[0x10];
3863+
3864+
u8 counter_group_id[0x20];
3865+
};
3866+
3867+
#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
3868+
#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
3869+
#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
3870+
MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
3871+
3872+
struct mlx5_ifc_set_monitor_counter_in_bits {
3873+
u8 opcode[0x10];
3874+
u8 uid[0x10];
3875+
3876+
u8 reserved_at_20[0x10];
3877+
u8 op_mod[0x10];
3878+
3879+
u8 reserved_at_40[0x10];
3880+
u8 num_of_counters[0x10];
3881+
3882+
u8 reserved_at_60[0x20];
3883+
3884+
struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
3885+
};
3886+
3887+
struct mlx5_ifc_set_monitor_counter_out_bits {
3888+
u8 status[0x8];
3889+
u8 reserved_at_8[0x18];
3890+
3891+
u8 syndrome[0x20];
3892+
3893+
u8 reserved_at_40[0x40];
3894+
};
3895+
38113896
struct mlx5_ifc_query_vport_state_in_bits {
38123897
u8 opcode[0x10];
38133898
u8 reserved_at_10[0x10];

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