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torvaldstorvalds
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Merge tag 'perf-urgent-2022-10-02' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull misc perf fixes from Ingo Molnar: - Fix a PMU enumeration/initialization bug on Intel Alder Lake CPUs - Fix KVM guest PEBS register handling - Fix race/reentry bug in perf_output_read_group() reading of PMU counters * tag 'perf-urgent-2022-10-02' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/core: Fix reentry problem in perf_output_read_group() perf/x86/core: Completely disable guest PEBS via guest's global_ctrl perf/x86/intel: Fix unchecked MSR access error for Alder Lake N
2 parents 534b0ab + 6b959ba commit febae48

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lines changed

4 files changed

+57
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lines changed

‎arch/x86/events/intel/core.c

Lines changed: 39 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2102,6 +2102,15 @@ static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
21022102
EVENT_EXTRA_END
21032103
};
21042104

2105+
EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2106+
EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2107+
2108+
static struct attribute *grt_mem_attrs[] = {
2109+
EVENT_PTR(mem_ld_grt),
2110+
EVENT_PTR(mem_st_grt),
2111+
NULL
2112+
};
2113+
21052114
static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
21062115
/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
21072116
INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
@@ -5975,6 +5984,36 @@ __init int intel_pmu_init(void)
59755984
name = "Tremont";
59765985
break;
59775986

5987+
case INTEL_FAM6_ALDERLAKE_N:
5988+
x86_pmu.mid_ack = true;
5989+
memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5990+
sizeof(hw_cache_event_ids));
5991+
memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5992+
sizeof(hw_cache_extra_regs));
5993+
hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5994+
5995+
x86_pmu.event_constraints = intel_slm_event_constraints;
5996+
x86_pmu.pebs_constraints = intel_grt_pebs_event_constraints;
5997+
x86_pmu.extra_regs = intel_grt_extra_regs;
5998+
5999+
x86_pmu.pebs_aliases = NULL;
6000+
x86_pmu.pebs_prec_dist = true;
6001+
x86_pmu.pebs_block = true;
6002+
x86_pmu.lbr_pt_coexist = true;
6003+
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
6004+
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
6005+
6006+
intel_pmu_pebs_data_source_grt();
6007+
x86_pmu.pebs_latency_data = adl_latency_data_small;
6008+
x86_pmu.get_event_constraints = tnt_get_event_constraints;
6009+
x86_pmu.limit_period = spr_limit_period;
6010+
td_attr = tnt_events_attrs;
6011+
mem_attr = grt_mem_attrs;
6012+
extra_attr = nhm_format_attr;
6013+
pr_cont("Gracemont events, ");
6014+
name = "gracemont";
6015+
break;
6016+
59786017
case INTEL_FAM6_WESTMERE:
59796018
case INTEL_FAM6_WESTMERE_EP:
59806019
case INTEL_FAM6_WESTMERE_EX:
@@ -6317,7 +6356,6 @@ __init int intel_pmu_init(void)
63176356

63186357
case INTEL_FAM6_ALDERLAKE:
63196358
case INTEL_FAM6_ALDERLAKE_L:
6320-
case INTEL_FAM6_ALDERLAKE_N:
63216359
case INTEL_FAM6_RAPTORLAKE:
63226360
case INTEL_FAM6_RAPTORLAKE_P:
63236361
/*

‎arch/x86/events/intel/ds.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -110,13 +110,18 @@ void __init intel_pmu_pebs_data_source_skl(bool pmem)
110110
__intel_pmu_pebs_data_source_skl(pmem, pebs_data_source);
111111
}
112112

113-
static void __init intel_pmu_pebs_data_source_grt(u64 *data_source)
113+
static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source)
114114
{
115115
data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
116116
data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
117117
data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
118118
}
119119

120+
void __init intel_pmu_pebs_data_source_grt(void)
121+
{
122+
__intel_pmu_pebs_data_source_grt(pebs_data_source);
123+
}
124+
120125
void __init intel_pmu_pebs_data_source_adl(void)
121126
{
122127
u64 *data_source;
@@ -127,7 +132,7 @@ void __init intel_pmu_pebs_data_source_adl(void)
127132

128133
data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
129134
memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
130-
intel_pmu_pebs_data_source_grt(data_source);
135+
__intel_pmu_pebs_data_source_grt(data_source);
131136
}
132137

133138
static u64 precise_store_data(u64 status)

‎arch/x86/events/perf_event.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1516,6 +1516,8 @@ void intel_pmu_pebs_data_source_skl(bool pmem);
15161516

15171517
void intel_pmu_pebs_data_source_adl(void);
15181518

1519+
void intel_pmu_pebs_data_source_grt(void);
1520+
15191521
int intel_pmu_setup_lbr_filter(struct perf_event *event);
15201522

15211523
void intel_pt_interrupt(void);

‎kernel/events/core.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6893,9 +6893,16 @@ static void perf_output_read_group(struct perf_output_handle *handle,
68936893
{
68946894
struct perf_event *leader = event->group_leader, *sub;
68956895
u64 read_format = event->attr.read_format;
6896+
unsigned long flags;
68966897
u64 values[6];
68976898
int n = 0;
68986899

6900+
/*
6901+
* Disabling interrupts avoids all counter scheduling
6902+
* (context switches, timer based rotation and IPIs).
6903+
*/
6904+
local_irq_save(flags);
6905+
68996906
values[n++] = 1 + leader->nr_siblings;
69006907

69016908
if (read_format & PERF_FORMAT_TOTAL_TIME_ENABLED)
@@ -6931,6 +6938,8 @@ static void perf_output_read_group(struct perf_output_handle *handle,
69316938

69326939
__output_copy(handle, values, n * sizeof(u64));
69336940
}
6941+
6942+
local_irq_restore(flags);
69346943
}
69356944

69366945
#define PERF_FORMAT_TOTAL_TIMES (PERF_FORMAT_TOTAL_TIME_ENABLED|\

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