drm/i915: Fix AVI/HDMI/SPD infoframes on HSW+

vsyrjala · vsyrjala · commit ffc85daba535 · 2015-12-16T19:01:09.000+02:00
I broke AVI/HDMI/SPD infoframes on HSW+ with the register type safety changes. We were supposed to check that the infoframe data register is valid before writing the infoframe data, but the check ended up inverted, and so in practice we never wrote or enabled these infoframes. We were still sending out the GCP infoframe when the sink was deep-color capable. That and the fact that we use a single bool to track our infoframe state meant that the state checker only caught this when a HDMI sink that doesn't do deep-color was used. We really need to fix our infoframe state checking to be much more anal. But in the meantime let's just fix the regression. In fact let's just throw out the register validity check and convert some of the "unknown info frame type" debug messages into MISSING_CASE(). So far we support the same set of infoframe types on all platforms, so the silent debug messages make no sense. Cc: drm-intel-fixes@lists.freedesktop.org Fixes: f0f59a0 ("drm/i915: Type safe register read/write") Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (irc) Tested-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> (irc) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1450282200-4203-1-git-send-email-ville.syrjala@linux.intel.com Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93119 Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -78,7 +78,7 @@ static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
 	case HDMI_INFOFRAME_TYPE_VENDOR:
 		return VIDEO_DIP_SELECT_VENDOR;
 	default:
-		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
+		MISSING_CASE(type);
 		return 0;
 	}
 }
@@ -93,7 +93,7 @@ static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
 	case HDMI_INFOFRAME_TYPE_VENDOR:
 		return VIDEO_DIP_ENABLE_VENDOR;
 	default:
-		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
+		MISSING_CASE(type);
 		return 0;
 	}
 }
@@ -108,7 +108,7 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
 	case HDMI_INFOFRAME_TYPE_VENDOR:
 		return VIDEO_DIP_ENABLE_VS_HSW;
 	default:
-		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
+		MISSING_CASE(type);
 		return 0;
 	}
 }
@@ -127,7 +127,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 	case HDMI_INFOFRAME_TYPE_VENDOR:
 		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 	default:
-		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
+		MISSING_CASE(type);
 		return INVALID_MMIO_REG;
 	}
 }
@@ -375,8 +375,6 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
 	u32 val = I915_READ(ctl_reg);
 
 	data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
-	if (i915_mmio_reg_valid(data_reg))
-		return;
 
 	val &= ~hsw_infoframe_enable(type);
 	I915_WRITE(ctl_reg, val);

Original file line number	Diff line number	Diff line change
`@@ -78,7 +78,7 @@ static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)`
`78`	`78`	`case HDMI_INFOFRAME_TYPE_VENDOR:`
`79`	`79`	`return VIDEO_DIP_SELECT_VENDOR;`
`80`	`80`	`default:`
`81`		`- DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);`
	`81`	`+ MISSING_CASE(type);`
`82`	`82`	`return 0;`
`83`	`83`	`}`
`84`	`84`	`}`
`@@ -93,7 +93,7 @@ static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)`
`93`	`93`	`case HDMI_INFOFRAME_TYPE_VENDOR:`
`94`	`94`	`return VIDEO_DIP_ENABLE_VENDOR;`
`95`	`95`	`default:`
`96`		`- DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);`
	`96`	`+ MISSING_CASE(type);`
`97`	`97`	`return 0;`
`98`	`98`	`}`
`99`	`99`	`}`
`@@ -108,7 +108,7 @@ static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)`
`108`	`108`	`case HDMI_INFOFRAME_TYPE_VENDOR:`
`109`	`109`	`return VIDEO_DIP_ENABLE_VS_HSW;`
`110`	`110`	`default:`
`111`		`- DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);`
	`111`	`+ MISSING_CASE(type);`
`112`	`112`	`return 0;`
`113`	`113`	`}`
`114`	`114`	`}`
`@@ -127,7 +127,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,`
`127`	`127`	`case HDMI_INFOFRAME_TYPE_VENDOR:`
`128`	`128`	`return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);`
`129`	`129`	`default:`
`130`		`- DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);`
	`130`	`+ MISSING_CASE(type);`
`131`	`131`	`return INVALID_MMIO_REG;`
`132`	`132`	`}`
`133`	`133`	`}`
`@@ -375,8 +375,6 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,`
`375`	`375`	`u32 val = I915_READ(ctl_reg);`
`376`	`376`
`377`	`377`	`data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);`
`378`		`- if (i915_mmio_reg_valid(data_reg))`
`379`		`- return;`
`380`	`378`
`381`	`379`	`val &= ~hsw_infoframe_enable(type);`
`382`	`380`	`I915_WRITE(ctl_reg, val);`