diff --git a/LICENSE b/LICENSE index d29b3726..686d8a91 100644 --- a/LICENSE +++ b/LICENSE @@ -1,4 +1,4 @@ -Copyright (c) 2015 The Go Authors. All rights reserved. +Copyright 2015 The Go Authors. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are @@ -10,7 +10,7 @@ notice, this list of conditions and the following disclaimer. copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - * Neither the name of Google Inc. nor the names of its + * Neither the name of Google LLC nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. diff --git a/README.md b/README.md index d2351348..9995b5e9 100644 --- a/README.md +++ b/README.md @@ -8,8 +8,10 @@ The parts needed in the main Go repository are copied in. ## Report Issues / Send Patches This repository uses Gerrit for code changes. To learn how to submit changes to -this repository, see https://golang.org/doc/contribute.html. +this repository, see https://go.dev/doc/contribute. + +The git repository is https://go.googlesource.com/arch. The main issue tracker for the arch repository is located at -https://github.com/golang/go/issues. Prefix your issue with "x/arch:" in the +https://go.dev/issues. Prefix your issue with "x/arch:" in the subject line, so it is easy to find. diff --git a/arm/armasm/plan9x.go b/arm/armasm/plan9x.go index a143d2ef..842ab980 100644 --- a/arm/armasm/plan9x.go +++ b/arm/armasm/plan9x.go @@ -253,10 +253,13 @@ func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg // [r2, r0, ror #1] -> (R2)(R0@>1) // inst [r2, -r0, ror #1] -> INST.U (R2)(R0@>1) // input: -// a memory operand +// +// a memory operand +// // return values: -// corresponding memory operand in Plan 9 syntax -// .W/.P/.U suffix +// +// corresponding memory operand in Plan 9 syntax +// .W/.P/.U suffix func memOpTrans(mem Mem) (string, string) { suffix := "" switch mem.Mode { diff --git a/arm/armmap/map.go b/arm/armmap/map.go index f5053052..3e8f3072 100644 --- a/arm/armmap/map.go +++ b/arm/armmap/map.go @@ -5,12 +5,13 @@ // Armmap constructs the ARM opcode map from the instruction set CSV file. // // Usage: +// // armmap [-fmt=format] arm.csv // // The known output formats are: // -// text (default) - print decoding tree in text form -// decoder - print decoding tables for the armasm package +// text (default) - print decoding tree in text form +// decoder - print decoding tables for the armasm package package main import ( diff --git a/arm/armspec/spec.go b/arm/armspec/spec.go index f5bad801..5b458e1e 100644 --- a/arm/armspec/spec.go +++ b/arm/armspec/spec.go @@ -2,21 +2,14 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. -//go:build go1.6 && (!386 || go1.8) -// +build go1.6 -// +build !386 go1.8 - -// ... see golang.org/issue/12840 - -// Armspec reads the ``ARM Architecture Reference Manual'' +// Armspec reads the “ARM Architecture Reference Manual” // to collect instruction encoding details and writes those details to standard output // in JSON format. // -// Warning Warning Warning +// # Warning Warning Warning // // This program is unfinished. It is being published in this incomplete form // for interested readers, but do not expect it to be runnable or useful. -// package main import ( @@ -588,7 +581,14 @@ func findWords(chars []pdf.Text) (words []pdf.Text) { f := ck.Font f = strings.TrimSuffix(f, ",Italic") f = strings.TrimSuffix(f, "-Italic") - words = append(words, pdf.Text{f, ck.FontSize, ck.X, ck.Y, end - ck.X, s}) + words = append(words, pdf.Text{ + Font: f, + FontSize: ck.FontSize, + X: ck.X, + Y: ck.Y, + W: end - ck.X, + S: s, + }) k = l } i = j @@ -606,10 +606,10 @@ func sameFont(f1, f2 string) bool { } var jsFix = strings.NewReplacer( -// `\u003c`, `<`, -// `\u003e`, `>`, -// `\u0026`, `&`, -// `\u0009`, `\t`, +// `\u003c`, `<`, +// `\u003e`, `>`, +// `\u0026`, `&`, +// `\u0009`, `\t`, ) func printTable(name string, table []Inst) { diff --git a/arm/armspec/specmap.go b/arm/armspec/specmap.go index b881082a..973030f9 100644 --- a/arm/armspec/specmap.go +++ b/arm/armspec/specmap.go @@ -3,7 +3,6 @@ // license that can be found in the LICENSE file. //go:build ignore -// +build ignore package main diff --git a/arm64/arm64asm/ext_test.go b/arm64/arm64asm/ext_test.go index f432203e..839eb3fd 100644 --- a/arm64/arm64asm/ext_test.go +++ b/arm64/arm64asm/ext_test.go @@ -31,7 +31,6 @@ import ( var ( dumpTest = flag.Bool("dump", false, "dump all encodings") mismatch = flag.Bool("mismatch", false, "log allowed mismatches") - longTest = flag.Bool("long", false, "long test") keep = flag.Bool("keep", false, "keep object files around") debug = false ) @@ -164,7 +163,7 @@ func testExtDis( totalTests++ if *dumpTest { - fmt.Printf("%x -> %s [%d]\n", enc[:len(enc)], dec.text, dec.nenc) + fmt.Printf("%x -> %s [%d]\n", enc, dec.text, dec.nenc) } if text != dec.text && !strings.Contains(dec.text, "unknown") && syntax == "gnu" { suffix := "" @@ -256,7 +255,6 @@ func disasm(syntax string, src []byte) (inst Inst, text string) { text = "error: " + err.Error() return } - text = inst.String() switch syntax { case "gnu": text = GNUSyntax(inst) @@ -268,7 +266,7 @@ func disasm(syntax string, src []byte) (inst Inst, text string) { return } -// decodecoverage returns a floating point number denoting the +// decodeCoverage returns a floating point number denoting the // decoder coverage. func decodeCoverage() float64 { n := 0 @@ -424,7 +422,7 @@ var condmark bool = false func doFuzzy(inst *InstJson, Ninst int) { var testdata uint32 var NonDigRE = regexp.MustCompile(`[\D]`) - rand.Seed(int64(Round + Ninst)) + rand := rand.New(rand.NewSource(int64(Round + Ninst))) off := 0 DigBit := "" if condmark == true && !strings.Contains(inst.Bits, "cond") { @@ -518,11 +516,8 @@ func JSONCases(t *testing.T) func(func([]byte)) { t.Fatal(err) } // Append instructions to get more test cases. - for i := 0; i < N; { - for _, inst := range insts { - instsN = append(instsN, inst) - } - i++ + for i := 0; i < N; i++ { + instsN = append(instsN, insts...) } Round = 0 for i := range instsN { diff --git a/arm64/arm64asm/inst.go b/arm64/arm64asm/inst.go index 8c633fef..39ddaf75 100644 --- a/arm64/arm64asm/inst.go +++ b/arm64/arm64asm/inst.go @@ -469,7 +469,7 @@ func (rea RegExtshiftAmount) String() string { if rea.amount != 0 { buf += fmt.Sprintf(" #%d", rea.amount) } else { - if rea.show_zero == true { + if rea.show_zero { buf += fmt.Sprintf(" #%d", rea.amount) } } @@ -527,7 +527,7 @@ func (m MemImmediate) String() string { postR := post.String() return fmt.Sprintf("[%s], %s", R, postR) } - return fmt.Sprintf("unimplemented!") + return "unimplemented!" } // A MemExtend is a memory reference made up of a base R and index expression X. @@ -934,8 +934,10 @@ func (r RegisterWithArrangement) String() string { return result } -// Register with arrangement and index: .[], -// { .B, .B }[]. +// Register with arrangement and index: +// +// .[], +// { .B, .B }[]. type RegisterWithArrangementAndIndex struct { r Reg a Arrangement @@ -1019,110 +1021,110 @@ func (s sysInstFields) getType() sys { } var sysInstsAttrs = map[sysInstFields]sysInstAttrs{ - sysInstFields{0, 8, 3, 0}: {sys_TLBI, "VMALLE1IS", false}, - sysInstFields{0, 8, 3, 1}: {sys_TLBI, "VAE1IS", true}, - sysInstFields{0, 8, 3, 2}: {sys_TLBI, "ASIDE1IS", true}, - sysInstFields{0, 8, 3, 3}: {sys_TLBI, "VAAE1IS", true}, - sysInstFields{0, 8, 3, 5}: {sys_TLBI, "VALE1IS", true}, - sysInstFields{0, 8, 3, 7}: {sys_TLBI, "VAALE1IS", true}, - sysInstFields{0, 8, 7, 0}: {sys_TLBI, "VMALLE1", false}, - sysInstFields{0, 8, 7, 1}: {sys_TLBI, "VAE1", true}, - sysInstFields{0, 8, 7, 2}: {sys_TLBI, "ASIDE1", true}, - sysInstFields{0, 8, 7, 3}: {sys_TLBI, "VAAE1", true}, - sysInstFields{0, 8, 7, 5}: {sys_TLBI, "VALE1", true}, - sysInstFields{0, 8, 7, 7}: {sys_TLBI, "VAALE1", true}, - sysInstFields{4, 8, 0, 1}: {sys_TLBI, "IPAS2E1IS", true}, - sysInstFields{4, 8, 0, 5}: {sys_TLBI, "IPAS2LE1IS", true}, - sysInstFields{4, 8, 3, 0}: {sys_TLBI, "ALLE2IS", false}, - sysInstFields{4, 8, 3, 1}: {sys_TLBI, "VAE2IS", true}, - sysInstFields{4, 8, 3, 4}: {sys_TLBI, "ALLE1IS", false}, - sysInstFields{4, 8, 3, 5}: {sys_TLBI, "VALE2IS", true}, - sysInstFields{4, 8, 3, 6}: {sys_TLBI, "VMALLS12E1IS", false}, - sysInstFields{4, 8, 4, 1}: {sys_TLBI, "IPAS2E1", true}, - sysInstFields{4, 8, 4, 5}: {sys_TLBI, "IPAS2LE1", true}, - sysInstFields{4, 8, 7, 0}: {sys_TLBI, "ALLE2", false}, - sysInstFields{4, 8, 7, 1}: {sys_TLBI, "VAE2", true}, - sysInstFields{4, 8, 7, 4}: {sys_TLBI, "ALLE1", false}, - sysInstFields{4, 8, 7, 5}: {sys_TLBI, "VALE2", true}, - sysInstFields{4, 8, 7, 6}: {sys_TLBI, "VMALLS12E1", false}, - sysInstFields{6, 8, 3, 0}: {sys_TLBI, "ALLE3IS", false}, - sysInstFields{6, 8, 3, 1}: {sys_TLBI, "VAE3IS", true}, - sysInstFields{6, 8, 3, 5}: {sys_TLBI, "VALE3IS", true}, - sysInstFields{6, 8, 7, 0}: {sys_TLBI, "ALLE3", false}, - sysInstFields{6, 8, 7, 1}: {sys_TLBI, "VAE3", true}, - sysInstFields{6, 8, 7, 5}: {sys_TLBI, "VALE3", true}, - sysInstFields{0, 8, 1, 0}: {sys_TLBI, "VMALLE1OS", false}, - sysInstFields{0, 8, 1, 1}: {sys_TLBI, "VAE1OS", true}, - sysInstFields{0, 8, 1, 2}: {sys_TLBI, "ASIDE1OS", true}, - sysInstFields{0, 8, 1, 3}: {sys_TLBI, "VAAE1OS", true}, - sysInstFields{0, 8, 1, 5}: {sys_TLBI, "VALE1OS", true}, - sysInstFields{0, 8, 1, 7}: {sys_TLBI, "VAALE1OS", true}, - sysInstFields{0, 8, 2, 1}: {sys_TLBI, "RVAE1IS", true}, - sysInstFields{0, 8, 2, 3}: {sys_TLBI, "RVAAE1IS", true}, - sysInstFields{0, 8, 2, 5}: {sys_TLBI, "RVALE1IS", true}, - sysInstFields{0, 8, 2, 7}: {sys_TLBI, "RVAALE1IS", true}, - sysInstFields{0, 8, 5, 1}: {sys_TLBI, "RVAE1OS", true}, - sysInstFields{0, 8, 5, 3}: {sys_TLBI, "RVAAE1OS", true}, - sysInstFields{0, 8, 5, 5}: {sys_TLBI, "RVALE1OS", true}, - sysInstFields{0, 8, 5, 7}: {sys_TLBI, "RVAALE1OS", true}, - sysInstFields{0, 8, 6, 1}: {sys_TLBI, "RVAE1", true}, - sysInstFields{0, 8, 6, 3}: {sys_TLBI, "RVAAE1", true}, - sysInstFields{0, 8, 6, 5}: {sys_TLBI, "RVALE1", true}, - sysInstFields{0, 8, 6, 7}: {sys_TLBI, "RVAALE1", true}, - sysInstFields{4, 8, 0, 2}: {sys_TLBI, "RIPAS2E1IS", true}, - sysInstFields{4, 8, 0, 6}: {sys_TLBI, "RIPAS2LE1IS", true}, - sysInstFields{4, 8, 1, 0}: {sys_TLBI, "ALLE2OS", false}, - sysInstFields{4, 8, 1, 1}: {sys_TLBI, "VAE2OS", true}, - sysInstFields{4, 8, 1, 4}: {sys_TLBI, "ALLE1OS", false}, - sysInstFields{4, 8, 1, 5}: {sys_TLBI, "VALE2OS", true}, - sysInstFields{4, 8, 1, 6}: {sys_TLBI, "VMALLS12E1OS", false}, - sysInstFields{4, 8, 2, 1}: {sys_TLBI, "RVAE2IS", true}, - sysInstFields{4, 8, 2, 5}: {sys_TLBI, "RVALE2IS", true}, - sysInstFields{4, 8, 4, 0}: {sys_TLBI, "IPAS2E1OS", true}, - sysInstFields{4, 8, 4, 2}: {sys_TLBI, "RIPAS2E1", true}, - sysInstFields{4, 8, 4, 3}: {sys_TLBI, "RIPAS2E1OS", true}, - sysInstFields{4, 8, 4, 4}: {sys_TLBI, "IPAS2LE1OS", true}, - sysInstFields{4, 8, 4, 6}: {sys_TLBI, "RIPAS2LE1", true}, - sysInstFields{4, 8, 4, 7}: {sys_TLBI, "RIPAS2LE1OS", true}, - sysInstFields{4, 8, 5, 1}: {sys_TLBI, "RVAE2OS", true}, - sysInstFields{4, 8, 5, 5}: {sys_TLBI, "RVALE2OS", true}, - sysInstFields{4, 8, 6, 1}: {sys_TLBI, "RVAE2", true}, - sysInstFields{4, 8, 6, 5}: {sys_TLBI, "RVALE2", true}, - sysInstFields{6, 8, 1, 0}: {sys_TLBI, "ALLE3OS", false}, - sysInstFields{6, 8, 1, 1}: {sys_TLBI, "VAE3OS", true}, - sysInstFields{6, 8, 1, 5}: {sys_TLBI, "VALE3OS", true}, - sysInstFields{6, 8, 2, 1}: {sys_TLBI, "RVAE3IS", true}, - sysInstFields{6, 8, 2, 5}: {sys_TLBI, "RVALE3IS", true}, - sysInstFields{6, 8, 5, 1}: {sys_TLBI, "RVAE3OS", true}, - sysInstFields{6, 8, 5, 5}: {sys_TLBI, "RVALE3OS", true}, - sysInstFields{6, 8, 6, 1}: {sys_TLBI, "RVAE3", true}, - sysInstFields{6, 8, 6, 5}: {sys_TLBI, "RVALE3", true}, - sysInstFields{0, 7, 6, 1}: {sys_DC, "IVAC", true}, - sysInstFields{0, 7, 6, 2}: {sys_DC, "ISW", true}, - sysInstFields{0, 7, 10, 2}: {sys_DC, "CSW", true}, - sysInstFields{0, 7, 14, 2}: {sys_DC, "CISW", true}, - sysInstFields{3, 7, 4, 1}: {sys_DC, "ZVA", true}, - sysInstFields{3, 7, 10, 1}: {sys_DC, "CVAC", true}, - sysInstFields{3, 7, 11, 1}: {sys_DC, "CVAU", true}, - sysInstFields{3, 7, 14, 1}: {sys_DC, "CIVAC", true}, - sysInstFields{0, 7, 6, 3}: {sys_DC, "IGVAC", true}, - sysInstFields{0, 7, 6, 4}: {sys_DC, "IGSW", true}, - sysInstFields{0, 7, 6, 5}: {sys_DC, "IGDVAC", true}, - sysInstFields{0, 7, 6, 6}: {sys_DC, "IGDSW", true}, - sysInstFields{0, 7, 10, 4}: {sys_DC, "CGSW", true}, - sysInstFields{0, 7, 10, 6}: {sys_DC, "CGDSW", true}, - sysInstFields{0, 7, 14, 4}: {sys_DC, "CIGSW", true}, - sysInstFields{0, 7, 14, 6}: {sys_DC, "CIGDSW", true}, - sysInstFields{3, 7, 4, 3}: {sys_DC, "GVA", true}, - sysInstFields{3, 7, 4, 4}: {sys_DC, "GZVA", true}, - sysInstFields{3, 7, 10, 3}: {sys_DC, "CGVAC", true}, - sysInstFields{3, 7, 10, 5}: {sys_DC, "CGDVAC", true}, - sysInstFields{3, 7, 12, 3}: {sys_DC, "CGVAP", true}, - sysInstFields{3, 7, 12, 5}: {sys_DC, "CGDVAP", true}, - sysInstFields{3, 7, 13, 3}: {sys_DC, "CGVADP", true}, - sysInstFields{3, 7, 13, 5}: {sys_DC, "CGDVADP", true}, - sysInstFields{3, 7, 14, 3}: {sys_DC, "CIGVAC", true}, - sysInstFields{3, 7, 14, 5}: {sys_DC, "CIGDVAC", true}, - sysInstFields{3, 7, 12, 1}: {sys_DC, "CVAP", true}, - sysInstFields{3, 7, 13, 1}: {sys_DC, "CVADP", true}, + {0, 8, 3, 0}: {sys_TLBI, "VMALLE1IS", false}, + {0, 8, 3, 1}: {sys_TLBI, "VAE1IS", true}, + {0, 8, 3, 2}: {sys_TLBI, "ASIDE1IS", true}, + {0, 8, 3, 3}: {sys_TLBI, "VAAE1IS", true}, + {0, 8, 3, 5}: {sys_TLBI, "VALE1IS", true}, + {0, 8, 3, 7}: {sys_TLBI, "VAALE1IS", true}, + {0, 8, 7, 0}: {sys_TLBI, "VMALLE1", false}, + {0, 8, 7, 1}: {sys_TLBI, "VAE1", true}, + {0, 8, 7, 2}: {sys_TLBI, "ASIDE1", true}, + {0, 8, 7, 3}: {sys_TLBI, "VAAE1", true}, + {0, 8, 7, 5}: {sys_TLBI, "VALE1", true}, + {0, 8, 7, 7}: {sys_TLBI, "VAALE1", true}, + {4, 8, 0, 1}: {sys_TLBI, "IPAS2E1IS", true}, + {4, 8, 0, 5}: {sys_TLBI, "IPAS2LE1IS", true}, + {4, 8, 3, 0}: {sys_TLBI, "ALLE2IS", false}, + {4, 8, 3, 1}: {sys_TLBI, "VAE2IS", true}, + {4, 8, 3, 4}: {sys_TLBI, "ALLE1IS", false}, + {4, 8, 3, 5}: {sys_TLBI, "VALE2IS", true}, + {4, 8, 3, 6}: {sys_TLBI, "VMALLS12E1IS", false}, + {4, 8, 4, 1}: {sys_TLBI, "IPAS2E1", true}, + {4, 8, 4, 5}: {sys_TLBI, "IPAS2LE1", true}, + {4, 8, 7, 0}: {sys_TLBI, "ALLE2", false}, + {4, 8, 7, 1}: {sys_TLBI, "VAE2", true}, + {4, 8, 7, 4}: {sys_TLBI, "ALLE1", false}, + {4, 8, 7, 5}: {sys_TLBI, "VALE2", true}, + {4, 8, 7, 6}: {sys_TLBI, "VMALLS12E1", false}, + {6, 8, 3, 0}: {sys_TLBI, "ALLE3IS", false}, + {6, 8, 3, 1}: {sys_TLBI, "VAE3IS", true}, + {6, 8, 3, 5}: {sys_TLBI, "VALE3IS", true}, + {6, 8, 7, 0}: {sys_TLBI, "ALLE3", false}, + {6, 8, 7, 1}: {sys_TLBI, "VAE3", true}, + {6, 8, 7, 5}: {sys_TLBI, "VALE3", true}, + {0, 8, 1, 0}: {sys_TLBI, "VMALLE1OS", false}, + {0, 8, 1, 1}: {sys_TLBI, "VAE1OS", true}, + {0, 8, 1, 2}: {sys_TLBI, "ASIDE1OS", true}, + {0, 8, 1, 3}: {sys_TLBI, "VAAE1OS", true}, + {0, 8, 1, 5}: {sys_TLBI, "VALE1OS", true}, + {0, 8, 1, 7}: {sys_TLBI, "VAALE1OS", true}, + {0, 8, 2, 1}: {sys_TLBI, "RVAE1IS", true}, + {0, 8, 2, 3}: {sys_TLBI, "RVAAE1IS", true}, + {0, 8, 2, 5}: {sys_TLBI, "RVALE1IS", true}, + {0, 8, 2, 7}: {sys_TLBI, "RVAALE1IS", true}, + {0, 8, 5, 1}: {sys_TLBI, "RVAE1OS", true}, + {0, 8, 5, 3}: {sys_TLBI, "RVAAE1OS", true}, + {0, 8, 5, 5}: {sys_TLBI, "RVALE1OS", true}, + {0, 8, 5, 7}: {sys_TLBI, "RVAALE1OS", true}, + {0, 8, 6, 1}: {sys_TLBI, "RVAE1", true}, + {0, 8, 6, 3}: {sys_TLBI, "RVAAE1", true}, + {0, 8, 6, 5}: {sys_TLBI, "RVALE1", true}, + {0, 8, 6, 7}: {sys_TLBI, "RVAALE1", true}, + {4, 8, 0, 2}: {sys_TLBI, "RIPAS2E1IS", true}, + {4, 8, 0, 6}: {sys_TLBI, "RIPAS2LE1IS", true}, + {4, 8, 1, 0}: {sys_TLBI, "ALLE2OS", false}, + {4, 8, 1, 1}: {sys_TLBI, "VAE2OS", true}, + {4, 8, 1, 4}: {sys_TLBI, "ALLE1OS", false}, + {4, 8, 1, 5}: {sys_TLBI, "VALE2OS", true}, + {4, 8, 1, 6}: {sys_TLBI, "VMALLS12E1OS", false}, + {4, 8, 2, 1}: {sys_TLBI, "RVAE2IS", true}, + {4, 8, 2, 5}: {sys_TLBI, "RVALE2IS", true}, + {4, 8, 4, 0}: {sys_TLBI, "IPAS2E1OS", true}, + {4, 8, 4, 2}: {sys_TLBI, "RIPAS2E1", true}, + {4, 8, 4, 3}: {sys_TLBI, "RIPAS2E1OS", true}, + {4, 8, 4, 4}: {sys_TLBI, "IPAS2LE1OS", true}, + {4, 8, 4, 6}: {sys_TLBI, "RIPAS2LE1", true}, + {4, 8, 4, 7}: {sys_TLBI, "RIPAS2LE1OS", true}, + {4, 8, 5, 1}: {sys_TLBI, "RVAE2OS", true}, + {4, 8, 5, 5}: {sys_TLBI, "RVALE2OS", true}, + {4, 8, 6, 1}: {sys_TLBI, "RVAE2", true}, + {4, 8, 6, 5}: {sys_TLBI, "RVALE2", true}, + {6, 8, 1, 0}: {sys_TLBI, "ALLE3OS", false}, + {6, 8, 1, 1}: {sys_TLBI, "VAE3OS", true}, + {6, 8, 1, 5}: {sys_TLBI, "VALE3OS", true}, + {6, 8, 2, 1}: {sys_TLBI, "RVAE3IS", true}, + {6, 8, 2, 5}: {sys_TLBI, "RVALE3IS", true}, + {6, 8, 5, 1}: {sys_TLBI, "RVAE3OS", true}, + {6, 8, 5, 5}: {sys_TLBI, "RVALE3OS", true}, + {6, 8, 6, 1}: {sys_TLBI, "RVAE3", true}, + {6, 8, 6, 5}: {sys_TLBI, "RVALE3", true}, + {0, 7, 6, 1}: {sys_DC, "IVAC", true}, + {0, 7, 6, 2}: {sys_DC, "ISW", true}, + {0, 7, 10, 2}: {sys_DC, "CSW", true}, + {0, 7, 14, 2}: {sys_DC, "CISW", true}, + {3, 7, 4, 1}: {sys_DC, "ZVA", true}, + {3, 7, 10, 1}: {sys_DC, "CVAC", true}, + {3, 7, 11, 1}: {sys_DC, "CVAU", true}, + {3, 7, 14, 1}: {sys_DC, "CIVAC", true}, + {0, 7, 6, 3}: {sys_DC, "IGVAC", true}, + {0, 7, 6, 4}: {sys_DC, "IGSW", true}, + {0, 7, 6, 5}: {sys_DC, "IGDVAC", true}, + {0, 7, 6, 6}: {sys_DC, "IGDSW", true}, + {0, 7, 10, 4}: {sys_DC, "CGSW", true}, + {0, 7, 10, 6}: {sys_DC, "CGDSW", true}, + {0, 7, 14, 4}: {sys_DC, "CIGSW", true}, + {0, 7, 14, 6}: {sys_DC, "CIGDSW", true}, + {3, 7, 4, 3}: {sys_DC, "GVA", true}, + {3, 7, 4, 4}: {sys_DC, "GZVA", true}, + {3, 7, 10, 3}: {sys_DC, "CGVAC", true}, + {3, 7, 10, 5}: {sys_DC, "CGDVAC", true}, + {3, 7, 12, 3}: {sys_DC, "CGVAP", true}, + {3, 7, 12, 5}: {sys_DC, "CGDVAP", true}, + {3, 7, 13, 3}: {sys_DC, "CGVADP", true}, + {3, 7, 13, 5}: {sys_DC, "CGDVADP", true}, + {3, 7, 14, 3}: {sys_DC, "CIGVAC", true}, + {3, 7, 14, 5}: {sys_DC, "CIGDVAC", true}, + {3, 7, 12, 1}: {sys_DC, "CVAP", true}, + {3, 7, 13, 1}: {sys_DC, "CVADP", true}, } diff --git a/arm64/arm64spec/spec.go b/arm64/arm64spec/spec.go index 08b487cd..feedf83c 100644 --- a/arm64/arm64spec/spec.go +++ b/arm64/arm64spec/spec.go @@ -2,9 +2,6 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. -//go:build (go1.6 && amd64) || go1.8 -// +build go1.6,amd64 go1.8 - // arm64spec reads the ``ARMv8-A Reference Manual'' // to collect instruction encoding details and writes those // details to standard output in JSON format. @@ -688,7 +685,14 @@ func findWords(chars []pdf.Text) (words []pdf.Text) { f := ck.Font f = strings.TrimSuffix(f, ",Italic") f = strings.TrimSuffix(f, "-Italic") - words = append(words, pdf.Text{f, ck.FontSize, ck.X, ck.Y, end - ck.X, s}) + words = append(words, pdf.Text{ + Font: f, + FontSize: ck.FontSize, + X: ck.X, + Y: ck.Y, + W: end - ck.X, + S: s, + }) k = l } i = j diff --git a/go.mod b/go.mod index d29c9298..0db7aa41 100644 --- a/go.mod +++ b/go.mod @@ -1,5 +1,5 @@ module golang.org/x/arch -go 1.17 +go 1.24.0 require rsc.io/pdf v0.1.1 diff --git a/loong64/loong64asm/arg.go b/loong64/loong64asm/arg.go new file mode 100644 index 00000000..460af3d1 --- /dev/null +++ b/loong64/loong64asm/arg.go @@ -0,0 +1,93 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +// Naming for Go decoder arguments: +// +// - arg_fd: a Floating Point operand register fd encoded in the fd[4:0] field +// +// - arg_fj: a Floating Point operand register fj encoded in the fj[9:5] field +// +// - arg_fk: a Floating Point operand register fk encoded in the fk[14:10] field +// +// - arg_fa: a Floating Point operand register fa encoded in the fa[19:15] field +// +// - arg_rd: a general-purpose register rd encoded in the rd[4:0] field +// +// - arg_rj: a general-purpose register rj encoded in the rj[9:5] field +// +// - arg_rk: a general-purpose register rk encoded in the rk[14:10] field +// +// - arg_fcsr_4_0: float control status register encoded in [4:0] field +// +// - arg_cd_2_0: condition flag register encoded in [2:0] field +// +// - arg_sa2_16_15: shift bits constant encoded in [16:15] field +// +// - arg_code_14_0: arg for exception process routine encoded in [14:0] field +// +// - arg_ui5_14_10: 5bits unsigned immediate +// +// - arg_lsbw: For details, please refer to chapter 2.2.3.8 of instruction manual +// +// - arg_msbw: For details, please refer to chapter 2.2.3.9 of instruction manual +// +// - arg_hint_4_0: hint field implied the prefetch type and the data should fetch to cache's level +// 0: load to data cache level 1 +// 8: store to data cache level 1 +// other: no define +// +// - arg_si12_21_10: 12bits signed immediate + +type instArg uint16 + +const ( + _ instArg = iota + // 1-5 + arg_fd + arg_fj + arg_fk + arg_fa + arg_rd + // 6-10 + arg_rj + arg_rk + arg_op_4_0 + arg_fcsr_4_0 + arg_fcsr_9_5 + // 11-15 + arg_csr_23_10 + arg_cd + arg_cj + arg_ca + arg_sa2_16_15 + // 16-20 + arg_sa3_17_15 + arg_code_4_0 + arg_code_14_0 + arg_ui5_14_10 + arg_ui6_15_10 + // 21-25 + arg_ui12_21_10 + arg_lsbw + arg_msbw + arg_lsbd + arg_msbd + // 26-30 + arg_hint_4_0 + arg_hint_14_0 + arg_level_14_0 + arg_level_17_10 + arg_seq_17_10 + // 31-35 + arg_si12_21_10 + arg_si14_23_10 + arg_si16_25_10 + arg_si20_24_5 + arg_offset_20_0 + // 36~ + arg_offset_25_0 + arg_offset_15_0 +) diff --git a/loong64/loong64asm/decode.go b/loong64/loong64asm/decode.go new file mode 100644 index 00000000..3aca0074 --- /dev/null +++ b/loong64/loong64asm/decode.go @@ -0,0 +1,269 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +import ( + "encoding/binary" + "fmt" +) + +type instArgs [5]instArg + +// An instFormat describes the format of an instruction encoding. +type instFormat struct { + mask uint32 + value uint32 + op Op + // args describe how to decode the instruction arguments. + // args is stored as a fixed-size array. + // if there are fewer than len(args) arguments, args[i] == 0 marks + // the end of the argument list. + args instArgs +} + +var ( + errShort = fmt.Errorf("truncated instruction") + errUnknown = fmt.Errorf("unknown instruction") +) + +var decoderCover []bool + +func init() { + decoderCover = make([]bool, len(instFormats)) +} + +// Decode decodes the 4 bytes in src as a single instruction. +func Decode(src []byte) (inst Inst, err error) { + if len(src) < 4 { + return Inst{}, errShort + } + + x := binary.LittleEndian.Uint32(src) + +Search: + for i := range instFormats { + f := &instFormats[i] + + if (x & f.mask) != f.value { + continue + } + + // Decode args. + var args Args + for j, aop := range f.args { + if aop == 0 { + break + } + + arg := decodeArg(aop, x, i) + if arg == nil { + // Cannot decode argument + continue Search + } + + args[j] = arg + } + + decoderCover[i] = true + inst = Inst{ + Op: f.op, + Args: args, + Enc: x, + } + return inst, nil + } + + return Inst{}, errUnknown +} + +// decodeArg decodes the arg described by aop from the instruction bits x. +// It returns nil if x cannot be decoded according to aop. +func decodeArg(aop instArg, x uint32, index int) Arg { + switch aop { + case arg_fd: + return F0 + Reg(x&((1<<5)-1)) + + case arg_fj: + return F0 + Reg((x>>5)&((1<<5)-1)) + + case arg_fk: + return F0 + Reg((x>>10)&((1<<5)-1)) + + case arg_fa: + return F0 + Reg((x>>15)&((1<<5)-1)) + + case arg_rd: + return R0 + Reg(x&((1<<5)-1)) + + case arg_rj: + return R0 + Reg((x>>5)&((1<<5)-1)) + + case arg_rk: + return R0 + Reg((x>>10)&((1<<5)-1)) + + case arg_fcsr_4_0: + return FCSR0 + Fcsr(x&((1<<5)-1)) + + case arg_fcsr_9_5: + return FCSR0 + Fcsr((x>>5)&((1<<5)-1)) + + case arg_cd: + return FCC0 + Fcc(x&((1<<3)-1)) + + case arg_cj: + return FCC0 + Fcc((x>>5)&((1<<3)-1)) + + case arg_ca: + return FCC0 + Fcc((x>>15)&((1<<3)-1)) + + case arg_op_4_0: + tmp := x & ((1 << 5) - 1) + return Uimm{tmp, false} + + case arg_csr_23_10: + tmp := (x >> 10) & ((1 << 14) - 1) + return Uimm{tmp, false} + + case arg_sa2_16_15: + f := &instFormats[index] + tmp := SaSimm((x >> 15) & ((1 << 2) - 1)) + if (f.op == ALSL_D) || (f.op == ALSL_W) || (f.op == ALSL_WU) { + return tmp + 1 + } else { + return tmp + 0 + } + + case arg_sa3_17_15: + return SaSimm((x >> 15) & ((1 << 3) - 1)) + + case arg_code_4_0: + return CodeSimm(x & ((1 << 5) - 1)) + + case arg_code_14_0: + return CodeSimm(x & ((1 << 15) - 1)) + + case arg_ui5_14_10: + tmp := (x >> 10) & ((1 << 5) - 1) + return Uimm{tmp, false} + + case arg_ui6_15_10: + tmp := (x >> 10) & ((1 << 6) - 1) + return Uimm{tmp, false} + + case arg_ui12_21_10: + tmp := ((x >> 10) & ((1 << 12) - 1) & 0xfff) + return Uimm{tmp, false} + + case arg_lsbw: + tmp := (x >> 10) & ((1 << 5) - 1) + return Uimm{tmp, false} + + case arg_msbw: + tmp := (x >> 16) & ((1 << 5) - 1) + return Uimm{tmp, false} + + case arg_lsbd: + tmp := (x >> 10) & ((1 << 6) - 1) + return Uimm{tmp, false} + + case arg_msbd: + tmp := (x >> 16) & ((1 << 6) - 1) + return Uimm{tmp, false} + + case arg_hint_4_0: + tmp := x & ((1 << 5) - 1) + return Uimm{tmp, false} + + case arg_hint_14_0: + tmp := x & ((1 << 15) - 1) + return Uimm{tmp, false} + + case arg_level_14_0: + tmp := x & ((1 << 15) - 1) + return Uimm{tmp, false} + + case arg_level_17_10: + tmp := (x >> 10) & ((1 << 8) - 1) + return Uimm{tmp, false} + + case arg_seq_17_10: + tmp := (x >> 10) & ((1 << 8) - 1) + return Uimm{tmp, false} + + case arg_si12_21_10: + var tmp int16 + + // no int12, so sign-extend a 12-bit signed to 16-bit signed + if (x & 0x200000) == 0x200000 { + tmp = int16(((x >> 10) & ((1 << 12) - 1)) | 0xf000) + } else { + tmp = int16(((x >> 10) & ((1 << 12) - 1)) | 0x0000) + } + return Simm16{tmp, 12} + + case arg_si14_23_10: + var tmp int32 + if (x & 0x800000) == 0x800000 { + tmp = int32((((x >> 10) & ((1 << 14) - 1)) << 2) | 0xffff0000) + } else { + tmp = int32((((x >> 10) & ((1 << 14) - 1)) << 2) | 0x00000000) + } + return Simm32{tmp, 14} + + case arg_si16_25_10: + var tmp int32 + + if (x & 0x2000000) == 0x2000000 { + tmp = int32(((x >> 10) & ((1 << 16) - 1)) | 0xffff0000) + } else { + tmp = int32(((x >> 10) & ((1 << 16) - 1)) | 0x00000000) + } + + return Simm32{tmp, 16} + + case arg_si20_24_5: + var tmp int32 + if (x & 0x1000000) == 0x1000000 { + tmp = int32(((x >> 5) & ((1 << 20) - 1)) | 0xfff00000) + } else { + tmp = int32(((x >> 5) & ((1 << 20) - 1)) | 0x00000000) + } + return Simm32{tmp, 20} + + case arg_offset_20_0: + var tmp int32 + + if (x & 0x10) == 0x10 { + tmp = int32(((((x << 16) | ((x >> 10) & ((1 << 16) - 1))) & ((1 << 21) - 1)) << 2) | 0xff800000) + } else { + tmp = int32((((x << 16) | ((x >> 10) & ((1 << 16) - 1))) & ((1 << 21) - 1)) << 2) + } + + return OffsetSimm{tmp, 21} + + case arg_offset_15_0: + var tmp int32 + if (x & 0x2000000) == 0x2000000 { + tmp = int32((((x >> 10) & ((1 << 16) - 1)) << 2) | 0xfffc0000) + } else { + tmp = int32((((x >> 10) & ((1 << 16) - 1)) << 2) | 0x00000000) + } + + return OffsetSimm{tmp, 16} + + case arg_offset_25_0: + var tmp int32 + + if (x & 0x200) == 0x200 { + tmp = int32(((((x << 16) | ((x >> 10) & ((1 << 16) - 1))) & ((1 << 26) - 1)) << 2) | 0xf0000000) + } else { + tmp = int32(((((x << 16) | ((x >> 10) & ((1 << 16) - 1))) & ((1 << 26) - 1)) << 2) | 0x00000000) + } + + return OffsetSimm{tmp, 26} + default: + return nil + } +} diff --git a/loong64/loong64asm/decode_test.go b/loong64/loong64asm/decode_test.go new file mode 100644 index 00000000..74a32773 --- /dev/null +++ b/loong64/loong64asm/decode_test.go @@ -0,0 +1,76 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +import ( + "encoding/hex" + "io/ioutil" + "path/filepath" + "strings" + "testing" +) + +func testDecode(t *testing.T, syntax string) { + input := filepath.Join("testdata", syntax+"cases.txt") + data, err := ioutil.ReadFile(input) + if err != nil { + t.Fatal(err) + } + all := string(data) + for strings.Contains(all, "\t\t") { + all = strings.Replace(all, "\t\t", "\t", -1) + } + for _, line := range strings.Split(all, "\n") { + line = strings.TrimSpace(line) + if line == "" || strings.HasPrefix(line, "#") { + continue + } + f := strings.SplitN(line, "\t", 2) + i := strings.Index(f[0], "|") + if i < 0 { + t.Errorf("parsing %q: missing | separator", f[0]) + continue + } + if i%2 != 0 { + t.Errorf("parsing %q: misaligned | separator", f[0]) + } + code, err := hex.DecodeString(f[0][:i] + f[0][i+1:]) + if err != nil { + t.Errorf("parsing %q: %v", f[0], err) + continue + } + asm := f[1] + inst, decodeErr := Decode(code) + if decodeErr != nil && decodeErr != errUnknown { + // Some rarely used system instructions are not supported + // Following logicals will filter such unknown instructions + t.Errorf("parsing %x: %s", code, decodeErr) + continue + } + var out string + switch syntax { + case "gnu": + out = GNUSyntax(inst) + case "plan9": + out = GoSyntax(inst, 0, nil) + default: + t.Errorf("unknown syntax %q", syntax) + continue + } + + // var out string + if asm != out || len(asm) != len(out) { + t.Errorf("Decode(%s) [%s] = %s want %s", f[0], syntax, out, asm) + } + } +} + +func TestDecodeGNUSyntax(t *testing.T) { + testDecode(t, "gnu") +} + +func TestDecodeGoSyntax(t *testing.T) { + testDecode(t, "plan9") +} diff --git a/loong64/loong64asm/ext_test.go b/loong64/loong64asm/ext_test.go new file mode 100644 index 00000000..5e73c80d --- /dev/null +++ b/loong64/loong64asm/ext_test.go @@ -0,0 +1,405 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Support for testing against external disassembler program. + +package loong64asm + +import ( + "bufio" + "bytes" + "encoding/hex" + "flag" + "fmt" + "io" + "io/ioutil" + "log" + "math/rand" + "os" + "os/exec" + "path/filepath" + "strings" + "testing" + "time" +) + +var ( + dumpTest = flag.Bool("dump", false, "dump all encodings") + mismatch = flag.Bool("mismatch", false, "log allowed mismatches") + keep = flag.Bool("keep", false, "keep object files around") + debug = false +) + +// An ExtInst represents a single decoded instruction parsed +// from an external disassembler's output. +type ExtInst struct { + addr uint64 + enc [4]byte + nenc int + text string +} + +func (r ExtInst) String() string { + return fmt.Sprintf("%#x: % x: %s", r.addr, r.enc, r.text) +} + +// An ExtDis is a connection between an external disassembler and a test. +type ExtDis struct { + Dec chan ExtInst + File *os.File + Size int + Cmd *exec.Cmd +} + +// Run runs the given command - the external disassembler - and returns +// a buffered reader of its standard output. +func (ext *ExtDis) Run(cmd ...string) (*bufio.Reader, error) { + if *keep { + log.Printf("%s\n", strings.Join(cmd, " ")) + } + ext.Cmd = exec.Command(cmd[0], cmd[1:]...) + out, err := ext.Cmd.StdoutPipe() + if err != nil { + return nil, fmt.Errorf("stdoutpipe: %v", err) + } + if err := ext.Cmd.Start(); err != nil { + return nil, fmt.Errorf("exec: %v", err) + } + + b := bufio.NewReaderSize(out, 1<<20) + return b, nil +} + +// Wait waits for the command started with Run to exit. +func (ext *ExtDis) Wait() error { + return ext.Cmd.Wait() +} + +// testExtDis tests a set of byte sequences against an external disassembler. +// The disassembler is expected to produce the given syntax and run +// in the given architecture mode (16, 32, or 64-bit). +// The extdis function must start the external disassembler +// and then parse its output, sending the parsed instructions on ext.Dec. +// The generate function calls its argument f once for each byte sequence +// to be tested. The generate function itself will be called twice, and it must +// make the same sequence of calls to f each time. +// When a disassembly does not match the internal decoding, +// allowedMismatch determines whether this mismatch should be +// allowed, or else considered an error. +func testExtDis( + t *testing.T, + syntax string, + extdis func(ext *ExtDis) error, + generate func(f func([]byte)), + allowedMismatch func(text string, inst *Inst, dec ExtInst) bool, +) { + start := time.Now() + ext := &ExtDis{ + Dec: make(chan ExtInst), + } + errc := make(chan error) + + // First pass: write instructions to input file for external disassembler. + file, f, size, err := writeInst(generate) + if err != nil { + t.Fatal(err) + } + ext.Size = size + ext.File = f + defer func() { + f.Close() + if !*keep { + os.Remove(file) + } + }() + + // Second pass: compare disassembly against our decodings. + var ( + totalTests = 0 + totalSkips = 0 + totalErrors = 0 + + errors = make([]string, 0, 100) // Sampled errors, at most cap + ) + go func() { + errc <- extdis(ext) + }() + + generate(func(enc []byte) { + dec, ok := <-ext.Dec + if !ok { + t.Errorf("decoding stream ended early") + return + } + inst, text := disasm(syntax, pad(enc)) + + totalTests++ + if *dumpTest { + fmt.Printf("%x -> %s [%d]\n", enc[:len(enc)], dec.text, dec.nenc) + } + + if text != dec.text && !strings.Contains(dec.text, "unknown") && syntax == "gnu" { + suffix := "" + if allowedMismatch(text, &inst, dec) { + totalSkips++ + if !*mismatch { + return + } + suffix += " (allowed mismatch)" + } + totalErrors++ + cmp := fmt.Sprintf("decode(%x) = %q, %d, want %q, %d%s\n", enc, text, len(enc), dec.text, dec.nenc, suffix) + + if len(errors) >= cap(errors) { + j := rand.Intn(totalErrors) + if j >= cap(errors) { + return + } + errors = append(errors[:j], errors[j+1:]...) + } + errors = append(errors, cmp) + } + }) + + if *mismatch { + totalErrors -= totalSkips + } + + fmt.Printf("totalTest: %d total skip: %d total error: %d\n", totalTests, totalSkips, totalErrors) + + // Here are some errors about mismatches(44) + for _, b := range errors { + t.Log(b) + } + + if totalErrors > 0 { + t.Fail() + } + t.Logf("%d test cases, %d expected mismatches, %d failures; %.0f cases/second", totalTests, totalSkips, totalErrors, float64(totalTests)/time.Since(start).Seconds()) + t.Logf("decoder coverage: %.1f%%;\n", decodeCoverage()) +} + +// Start address of text. +const start = 0x8000 + +// writeInst writes the generated byte sequences to a new file +// starting at offset start. That file is intended to be the input to +// the external disassembler. +func writeInst(generate func(func([]byte))) (file string, f *os.File, size int, err error) { + f, err = ioutil.TempFile("", "loong64asm") + if err != nil { + return + } + + file = f.Name() + + f.Seek(start, io.SeekStart) + w := bufio.NewWriter(f) + defer w.Flush() + size = 0 + generate(func(x []byte) { + if debug { + fmt.Printf("%#x: %x%x\n", start+size, x, zeros[len(x):]) + } + w.Write(x) + w.Write(zeros[len(x):]) + size += len(zeros) + }) + return file, f, size, nil +} + +var zeros = []byte{0, 0, 0, 0} + +// pad pads the code sequence with pops. +func pad(enc []byte) []byte { + if len(enc) < 4 { + enc = append(enc[:len(enc):len(enc)], zeros[:4-len(enc)]...) + } + return enc +} + +// disasm returns the decoded instruction and text +// for the given source bytes, using the given syntax and mode. +func disasm(syntax string, src []byte) (inst Inst, text string) { + var err error + inst, err = Decode(src) + if err != nil { + text = "error: " + err.Error() + return + } + text = inst.String() + switch syntax { + case "gnu": + text = GNUSyntax(inst) + case "plan9": // [sic] + text = GoSyntax(inst, 0, nil) + default: + text = "error: unknown syntax " + syntax + } + return +} + +// decodeCoverage returns a floating point number denoting the +// decoder coverage. +func decodeCoverage() float64 { + n := 0 + for _, t := range decoderCover { + if t { + n++ + } + } + return 100 * float64(1+n) / float64(1+len(decoderCover)) +} + +// Helpers for writing disassembler output parsers. + +// isHex reports whether b is a hexadecimal character (0-9a-fA-F). +func isHex(b byte) bool { + return ('0' <= b && b <= '9') || ('a' <= b && b <= 'f') || ('A' <= b && b <= 'F') +} + +// parseHex parses the hexadecimal byte dump in hex, +// appending the parsed bytes to raw and returning the updated slice. +// The returned bool reports whether any invalid hex was found. +// Spaces and tabs between bytes are okay but any other non-hex is not. +func parseHex(hex []byte, raw []byte) ([]byte, bool) { + hex = bytes.TrimSpace(hex) + for j := 0; j < len(hex); { + for hex[j] == ' ' || hex[j] == '\t' { + j++ + } + if j >= len(hex) { + break + } + if j+2 > len(hex) || !isHex(hex[j]) || !isHex(hex[j+1]) { + return nil, false + } + raw = append(raw, unhex(hex[j])<<4|unhex(hex[j+1])) + j += 2 + } + return raw, true +} + +func unhex(b byte) byte { + if '0' <= b && b <= '9' { + return b - '0' + } else if 'A' <= b && b <= 'F' { + return b - 'A' + 10 + } else if 'a' <= b && b <= 'f' { + return b - 'a' + 10 + } + return 0 +} + +// index is like bytes.Index(s, []byte(t)) but avoids the allocation. +func index(s []byte, t string) int { + i := 0 + for { + j := bytes.IndexByte(s[i:], t[0]) + if j < 0 { + return -1 + } + i = i + j + if i+len(t) > len(s) { + return -1 + } + for k := 1; k < len(t); k++ { + if s[i+k] != t[k] { + goto nomatch + } + } + return i + nomatch: + i++ + } +} + +// fixSpace rewrites runs of spaces, tabs, and newline characters into single spaces in s. +// If s must be rewritten, it is rewritten in place. +func fixSpace(s []byte) []byte { + s = bytes.TrimSpace(s) + for i := 0; i < len(s); i++ { + if s[i] == '\t' || s[i] == '\n' || i > 0 && s[i] == ' ' && s[i-1] == ' ' { + goto Fix + } + } + return s + +Fix: + b := s + w := 0 + for i := 0; i < len(s); i++ { + c := s[i] + if c == '\t' || c == '\n' { + c = ' ' + } + if c == ' ' && w > 0 && b[w-1] == ' ' { + continue + } + b[w] = c + w++ + } + if w > 0 && b[w-1] == ' ' { + w-- + } + return b[:w] +} + +// Generators. +// +// The test cases are described as functions that invoke a callback repeatedly, +// with a new input sequence each time. These helpers make writing those +// a little easier. + +// hexCases generates the cases written in hexadecimal in the encoded string. +// Spaces in 'encoded' separate entire test cases, not individual bytes. +func hexCases(t *testing.T, encoded string) func(func([]byte)) { + return func(try func([]byte)) { + for _, x := range strings.Fields(encoded) { + src, err := hex.DecodeString(x) + if err != nil { + t.Errorf("parsing %q: %v", x, err) + } + try(src) + } + } +} + +// testdataCases generates the test cases recorded in testdata/cases.txt. +// It only uses the inputs; it ignores the answers recorded in that file. +func testdataCases(t *testing.T, syntax string) func(func([]byte)) { + var codes [][]byte + input := filepath.Join("testdata", syntax+"cases.txt") + data, err := ioutil.ReadFile(input) + if err != nil { + t.Fatal(err) + } + for _, line := range strings.Split(string(data), "\n") { + line = strings.TrimSpace(line) + if line == "" || strings.HasPrefix(line, "#") { + continue + } + f := strings.Fields(line)[0] + i := strings.Index(f, "|") + if i < 0 { + t.Errorf("parsing %q: missing | separator", f) + continue + } + if i%2 != 0 { + t.Errorf("parsing %q: misaligned | separator", f) + } + code, err := hex.DecodeString(f[:i] + f[i+1:]) + if err != nil { + t.Errorf("parsing %q: %v", f, err) + continue + } + codes = append(codes, code) + } + + return func(try func([]byte)) { + for _, code := range codes { + try(code) + } + } +} diff --git a/loong64/loong64asm/gnu.go b/loong64/loong64asm/gnu.go new file mode 100644 index 00000000..4807abc5 --- /dev/null +++ b/loong64/loong64asm/gnu.go @@ -0,0 +1,16 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +import ( + "strings" +) + +// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. +// This form typically matches the syntax defined in the Loong64 Reference Manual. See +// https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html +func GNUSyntax(inst Inst) string { + return strings.ToLower(inst.String()) +} diff --git a/loong64/loong64asm/inst.go b/loong64/loong64asm/inst.go new file mode 100644 index 00000000..362d73ba --- /dev/null +++ b/loong64/loong64asm/inst.go @@ -0,0 +1,300 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +import ( + "fmt" + "strings" +) + +// An Inst is a single instruction. +type Inst struct { + Op Op // Opcode mnemonic + Enc uint32 // Raw encoding bits. + Args Args // Instruction arguments, in Loong64 manual order. +} + +func (i Inst) String() string { + var op string = i.Op.String() + var args []string + + for _, arg := range i.Args { + if arg == nil { + break + } + args = append(args, arg.String()) + } + + switch i.Op { + case OR: + if i.Args[2].(Reg) == R0 { + op = "move" + args = args[0:2] + } + + case ANDI: + if i.Args[0].(Reg) == R0 && i.Args[1].(Reg) == R0 { + return "nop" + } + + case JIRL: + if i.Args[0].(Reg) == R0 && i.Args[1].(Reg) == R1 && i.Args[2].(OffsetSimm).Imm == 0 { + return "ret" + } else if i.Args[0].(Reg) == R0 && i.Args[2].(OffsetSimm).Imm == 0 { + return "jr " + args[1] + } + + case BLT: + if i.Args[0].(Reg) == R0 { + op = "bgtz" + args = args[1:] + } else if i.Args[1].(Reg) == R0 { + op = "bltz" + args = append(args[:1], args[2:]...) + } + + case BGE: + if i.Args[0].(Reg) == R0 { + op = "blez" + args = args[1:] + } else if i.Args[1].(Reg) == R0 { + op = "bgez" + args = append(args[:1], args[2:]...) + } + } + + if len(args) == 0 { + return op + } else { + return op + " " + strings.Join(args, ", ") + } +} + +// An Op is an Loong64 opcode. +type Op uint16 + +// NOTE: The actual Op values are defined in tables.go. +// They are chosen to simplify instruction decoding and +// are not a dense packing from 0 to N, although the +// density is high, probably at least 90%. +func (op Op) String() string { + if (op >= Op(len(opstr))) || (opstr[op] == "") { + return fmt.Sprintf("Op(%d)", int(op)) + } + + return opstr[op] +} + +// An Args holds the instruction arguments. +// If an instruction has fewer than 5 arguments, +// the final elements in the array are nil. +type Args [5]Arg + +// An Arg is a single instruction argument +type Arg interface { + String() string +} + +// A Reg is a single register. +// The zero value denotes R0, not the absence of a register. +type Reg uint16 + +const ( + // General-purpose register + R0 Reg = iota + R1 + R2 + R3 + R4 + R5 + R6 + R7 + R8 + R9 + R10 + R11 + R12 + R13 + R14 + R15 + R16 + R17 + R18 + R19 + R20 + R21 + R22 + R23 + R24 + R25 + R26 + R27 + R28 + R29 + R30 + R31 + + // Float point register + F0 + F1 + F2 + F3 + F4 + F5 + F6 + F7 + F8 + F9 + F10 + F11 + F12 + F13 + F14 + F15 + F16 + F17 + F18 + F19 + F20 + F21 + F22 + F23 + F24 + F25 + F26 + F27 + F28 + F29 + F30 + F31 +) + +func (r Reg) String() string { + switch { + case r == R0: + return "$zero" + + case r == R1: + return "$ra" + + case r == R2: + return "$tp" + + case r == R3: + return "$sp" + + case (r >= R4) && (r <= R11): + return fmt.Sprintf("$a%d", int(r-R4)) + + case (r >= R12) && (r <= R20): + return fmt.Sprintf("$t%d", int(r-R12)) + + case r == R21: + return "$r21" + + case r == R22: + return "$fp" + + case (r >= R23) && (r <= R31): + return fmt.Sprintf("$s%d", int(r-R23)) + + case (r >= F0) && (r <= F7): + return fmt.Sprintf("$fa%d", int(r-F0)) + + case (r >= F8) && (r <= F23): + return fmt.Sprintf("$ft%d", int(r-F8)) + + case (r >= F24) && (r <= F31): + return fmt.Sprintf("$fs%d", int(r-F24)) + + default: + return fmt.Sprintf("Unknown(%d)", int(r)) + } +} + +// float control status register +type Fcsr uint8 + +const ( + FCSR0 Fcsr = iota + FCSR1 + FCSR2 + FCSR3 +) + +func (f Fcsr) String() string { + return fmt.Sprintf("$fcsr%d", uint8(f)) +} + +// float condition flags register +type Fcc uint8 + +const ( + FCC0 Fcc = iota + FCC1 + FCC2 + FCC3 + FCC4 + FCC5 + FCC6 + FCC7 +) + +func (f Fcc) String() string { + return fmt.Sprintf("$fcc%d", uint8(f)) +} + +// An Imm is an integer constant. +type Uimm struct { + Imm uint32 + Decimal bool +} + +func (i Uimm) String() string { + if i.Decimal == true { + return fmt.Sprintf("%d", i.Imm) + } else { + return fmt.Sprintf("%#x", i.Imm) + } +} + +type Simm16 struct { + Imm int16 + Width uint8 +} + +func (si Simm16) String() string { + return fmt.Sprintf("%d", int32(si.Imm)) +} + +type Simm32 struct { + Imm int32 + Width uint8 +} + +func (si Simm32) String() string { + return fmt.Sprintf("%d", int32(si.Imm)) +} + +type OffsetSimm struct { + Imm int32 + Width uint8 +} + +func (o OffsetSimm) String() string { + return fmt.Sprintf("%d", int32(o.Imm)) +} + +type SaSimm int16 + +func (s SaSimm) String() string { + return fmt.Sprintf("%#x", int(s)) +} + +type CodeSimm int16 + +func (c CodeSimm) String() string { + return fmt.Sprintf("%#x", int(c)) +} diff --git a/loong64/loong64asm/objdump_test.go b/loong64/loong64asm/objdump_test.go new file mode 100644 index 00000000..04766557 --- /dev/null +++ b/loong64/loong64asm/objdump_test.go @@ -0,0 +1,145 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +import ( + "strconv" + "strings" + "testing" +) + +func TestObjdumpLoong64TestDecodeGNUSyntaxdata(t *testing.T) { + testObjdumpLoong64(t, testdataCases(t, "gnu")) +} + +func TestObjdumpLoong64TestDecodeGoSyntaxdata(t *testing.T) { + testObjdumpLoong64(t, testdataCases(t, "plan9")) +} + +func TestObjdumpLoong64Manual(t *testing.T) { + testObjdumpLoong64(t, hexCases(t, objdumpManualTests)) +} + +// objdumpManualTests holds test cases that will be run by TestObjdumpLoong64Manual. +// If you are debugging a few cases that turned up in a longer run, it can be useful +// to list them here and then use -run=Manual, particularly with tracing enabled. +// Note that these are byte sequences, so they must be reversed from the usual +// word presentation. +var objdumpManualTests = ` +00007238 +00807238 +00004003 +00100050 +ac410028 +ac41002a +ac41c028 +ac414028 +ac41402a +ac418028 +ac41802a +ac397838 +acb97938 +acb97838 +ac397938 +ac397a38 +acb97b38 +acb97a38 +ac397b38 +ac110026 +ac110024 +ac390038 +ac392038 +ac390c38 +ac390438 +ac392438 +ac390838 +ac392838 +ac391600 +ac391400 +ac391500 +ac418003 +` + +// allowedMismatchObjdump reports whether the mismatch between text and dec +// should be allowed by the test. +func allowedMismatchObjdump(text string, inst *Inst, dec ExtInst) bool { + // GNU objdump use register, decode use alias of register, so corrected it in here + var dec_text = strings.Replace(dec.text, " ", ",", -1) + var decsp []string = strings.Split(dec_text, ",") + var num int = cap(decsp) + for i := 0; i < num; i++ { + dex := strings.Index(decsp[i], "$r") + fdex := strings.Index(decsp[i], "$f") + ddex := strings.Index(decsp[i], "(") + if ddex > 0 { + // ldptr.w $r12,$r13,16(0x10) + decsp[i] = decsp[i][0:ddex] + } + xdex := strings.Index(decsp[i], "0x") + // convert registers to registers aliases + if dex >= 0 { + reg, _ := strconv.Atoi(decsp[i][dex+2:]) + // r12~r20 $t0~t8 + if reg >= 12 && reg <= 20 { + decsp[i] = strings.Join([]string{"t", strconv.Itoa(reg - 12)}, "") + } + // r4~r11 $a0~a7 + if reg >= 4 && reg <= 11 { + decsp[i] = strings.Join([]string{"a", strconv.Itoa(reg - 4)}, "") + } + // r23~r31 $s0~s8 + if reg >= 23 && reg <= 31 { + decsp[i] = strings.Join([]string{"s", strconv.Itoa(reg - 23)}, "") + } + // r0 zero + if reg == 0 { + decsp[i] = strings.Join([]string{"zero"}, "") + } + // r1 ra + if reg == 1 { + decsp[i] = strings.Join([]string{"ra"}, "") + } + // r2 tp + if reg == 2 { + decsp[i] = strings.Join([]string{"tp"}, "") + } + // r3 sp + if reg == 3 { + decsp[i] = strings.Join([]string{"sp"}, "") + } + // r21 x + if reg == 21 { + decsp[i] = strings.Join([]string{"x"}, "") + } + // r22 fp + if reg == 22 { + decsp[i] = strings.Join([]string{"fp"}, "") + } + } + // convert hexadecimal to decimal + if xdex >= 0 { + parseint, _ := strconv.ParseInt(decsp[i][xdex+2:], 16, 32) + decsp[i] = strings.Join([]string{strconv.Itoa(int(parseint))}, "") + } + // convert floating-point registers to floating-point aliases + if fdex >= 0 && !strings.Contains(decsp[i], "$fcc") { + freg, _ := strconv.Atoi(decsp[i][fdex+2:]) + // f0~f7 fa0~fa7 + if freg >= 0 && freg <= 7 { + decsp[i] = strings.Join([]string{"fa", strconv.Itoa(freg - 0)}, "") + } + // f8~f23 ft0~ft15 + if freg >= 8 && freg <= 23 { + decsp[i] = strings.Join([]string{"ft", strconv.Itoa(freg - 8)}, "") + } + // f24~f31 fs0~fs7 + if freg >= 24 && freg <= 31 { + decsp[i] = strings.Join([]string{"fs", strconv.Itoa(freg - 24)}, "") + } + } + } + + return false +} diff --git a/loong64/loong64asm/objdumpext_test.go b/loong64/loong64asm/objdumpext_test.go new file mode 100644 index 00000000..80396d99 --- /dev/null +++ b/loong64/loong64asm/objdumpext_test.go @@ -0,0 +1,249 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +import ( + "bytes" + "debug/elf" + "encoding/binary" + "fmt" + "io" + "log" + "os" + "os/exec" + "strconv" + "strings" + "testing" +) + +const objdumpPath = "/usr/bin/objdump" + +func testObjdumpLoong64(t *testing.T, generate func(func([]byte))) { + testObjdumpArch(t, generate) +} + +func testObjdumpArch(t *testing.T, generate func(func([]byte))) { + checkObjdumpLoong64(t) + testExtDis(t, "gnu", objdump, generate, allowedMismatchObjdump) + testExtDis(t, "plan9", objdump, generate, allowedMismatchObjdump) +} + +func checkObjdumpLoong64(t *testing.T) { + out, err := exec.Command(objdumpPath, "-i").Output() + if err != nil { + t.Skipf("cannot run objdump: %v\n%s", err, out) + } + if !strings.Contains(string(out), "Loongarch64") { + t.Skip("objdump does not have loong64 support") + } +} + +func objdump(ext *ExtDis) error { + // File already written with instructions; add ELF header. + if err := writeELF64(ext.File, ext.Size); err != nil { + return err + } + + b, err := ext.Run(objdumpPath, "-d", "-z", ext.File.Name()) + if err != nil { + return err + } + + var ( + nmatch int + reading bool + next uint64 = start + addr uint64 + encbuf [4]byte + enc []byte + text string + ) + flush := func() { + if addr == next { + // PC-relative addresses are translated to absolute addresses based on PC by GNU objdump + // Following logical rewrites the absolute addresses back to PC-relative ones for comparing + // with our disassembler output which are PC-relative + if text == "undefined" && len(enc) == 4 { + text = "error: unknown instruction" + enc = nil + } + if len(enc) == 4 { + // prints as word but we want to record bytes + enc[0], enc[3] = enc[3], enc[0] + enc[1], enc[2] = enc[2], enc[1] + } + ext.Dec <- ExtInst{addr, encbuf, len(enc), text} + encbuf = [4]byte{} + enc = nil + next += 4 + } + } + var textangle = []byte("<.text>:") + for { + line, err := b.ReadSlice('\n') + if err != nil { + if err == io.EOF { + break + } + return fmt.Errorf("reading objdump output: %v", err) + } + if bytes.Contains(line, textangle) { + reading = true + continue + } + if !reading { + continue + } + if debug { + os.Stdout.Write(line) + } + if enc1 := parseContinuation(line, encbuf[:len(enc)]); enc1 != nil { + enc = enc1 + continue + } + flush() + nmatch++ + addr, enc, text = parseLine(line, encbuf[:0]) + if addr > next { + return fmt.Errorf("address out of sync expected <= %#x at %q in:\n%s", next, line, line) + } + } + flush() + if next != start+uint64(ext.Size) { + return fmt.Errorf("not enough results found [%d %d]", next, start+ext.Size) + } + if err := ext.Wait(); err != nil { + return fmt.Errorf("exec: %v", err) + } + + return nil +} + +var ( + undefined = []byte("undefined") + unpredictable = []byte("unpredictable") + slashslash = []byte("//") +) + +func parseLine(line []byte, encstart []byte) (addr uint64, enc []byte, text string) { + ok := false + oline := line + i := index(line, ":\t") + if i < 0 { + log.Fatalf("cannot parse disassembly: %q", oline) + } + x, err := strconv.ParseUint(string(bytes.TrimSpace(line[:i])), 16, 32) + if err != nil { + log.Fatalf("cannot parse disassembly: %q", oline) + } + addr = uint64(x) + line = line[i+2:] + i = bytes.IndexByte(line, '\t') + if i < 0 { + log.Fatalf("cannot parse disassembly: %q", oline) + } + enc, ok = parseHex(line[:i], encstart) + if !ok { + log.Fatalf("cannot parse disassembly: %q", oline) + } + line = bytes.TrimSpace(line[i:]) + if bytes.Contains(line, undefined) { + text = "undefined" + return + } + if false && bytes.Contains(line, unpredictable) { + text = "unpredictable" + return + } + // Strip trailing comment starting with '#' + if i := bytes.IndexByte(line, '#'); i >= 0 { + line = bytes.TrimSpace(line[:i]) + } + // Strip trailing comment starting with "//" + if i := bytes.Index(line, slashslash); i >= 0 { + line = bytes.TrimSpace(line[:i]) + } + text = string(fixSpace(line)) + return +} + +func parseContinuation(line []byte, enc []byte) []byte { + i := index(line, ":\t") + if i < 0 { + return nil + } + line = line[i+1:] + enc, _ = parseHex(line, enc) + return enc +} + +// writeELF64 writes an ELF64 header to the file, describing a text +// segment that starts at start (0x8000) and extends for size bytes. +func writeELF64(f *os.File, size int) error { + f.Seek(0, io.SeekStart) + var hdr elf.Header64 + var prog elf.Prog64 + var sect elf.Section64 + var buf bytes.Buffer + binary.Write(&buf, binary.LittleEndian, &hdr) + off1 := buf.Len() + binary.Write(&buf, binary.LittleEndian, &prog) + off2 := buf.Len() + binary.Write(&buf, binary.LittleEndian, §) + off3 := buf.Len() + buf.Reset() + data := byte(elf.ELFDATA2LSB) + hdr = elf.Header64{ + Ident: [16]byte{0x7F, 'E', 'L', 'F', 2, data, 1}, + Type: 2, + Machine: uint16(elf.EM_LOONGARCH), + Version: 1, + Entry: start, + Phoff: uint64(off1), + Shoff: uint64(off2), + Flags: 0x3, + Ehsize: uint16(off1), + Phentsize: uint16(off2 - off1), + Phnum: 1, + Shentsize: uint16(off3 - off2), + Shnum: 3, + Shstrndx: 2, + } + binary.Write(&buf, binary.LittleEndian, &hdr) + prog = elf.Prog64{ + Type: 1, + Off: start, + Vaddr: start, + Paddr: start, + Filesz: uint64(size), + Memsz: uint64(size), + Flags: 5, + Align: start, + } + binary.Write(&buf, binary.LittleEndian, &prog) + binary.Write(&buf, binary.LittleEndian, §) // NULL section + sect = elf.Section64{ + Name: 1, + Type: uint32(elf.SHT_PROGBITS), + Addr: start, + Off: start, + Size: uint64(size), + Flags: uint64(elf.SHF_ALLOC | elf.SHF_EXECINSTR), + Addralign: 4, + } + binary.Write(&buf, binary.LittleEndian, §) // .text + sect = elf.Section64{ + Name: uint32(len("\x00.text\x00")), + Type: uint32(elf.SHT_STRTAB), + Addr: 0, + Off: uint64(off2 + (off3-off2)*3), + Size: uint64(len("\x00.text\x00.shstrtab\x00")), + Addralign: 1, + } + binary.Write(&buf, binary.LittleEndian, §) + buf.WriteString("\x00.text\x00.shstrtab\x00") + f.Write(buf.Bytes()) + return nil +} diff --git a/loong64/loong64asm/plan9x.go b/loong64/loong64asm/plan9x.go new file mode 100644 index 00000000..4e3c4f1e --- /dev/null +++ b/loong64/loong64asm/plan9x.go @@ -0,0 +1,541 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +import ( + "fmt" + "strings" +) + +// GoSyntax returns the Go assembler syntax for the instruction. +// The syntax was originally defined by Plan 9. +// The pc is the program counter of the instruction, used for +// expanding PC-relative addresses into absolute ones. +// The symname function queries the symbol table for the program +// being disassembled. Given a target address it returns the name +// and base address of the symbol containing the target, if any; +// otherwise it returns "", 0. +func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string { + if symname == nil { + symname = func(uint64) (string, uint64) { return "", 0 } + } + if inst.Op == 0 && inst.Enc == 0 { + return "WORD $0" + } else if inst.Op == 0 { + return "?" + } + + var args []string + for _, a := range inst.Args { + if a == nil { + break + } + args = append(args, plan9Arg(&inst, pc, symname, a)) + } + + var op string = plan9OpMap[inst.Op] + if op == "" { + op = "Unknown " + inst.Op.String() + } + + switch inst.Op { + case BSTRPICK_W, BSTRPICK_D, BSTRINS_W, BSTRINS_D: + msbw, lsbw := inst.Args[2].(Uimm), inst.Args[3].(Uimm) + if inst.Op == BSTRPICK_D && msbw.Imm == 15 && lsbw.Imm == 0 { + op = "MOVHU" + args = append(args[1:2], args[0:1]...) + } else { + args[0], args[2], args[3] = args[2], args[3], args[0] + } + + case BCNEZ, BCEQZ: + args = args[1:2] + + case BEQ, BNE: + rj := inst.Args[0].(Reg) + rd := inst.Args[1].(Reg) + if rj == rd && inst.Op == BEQ { + op = "JMP" + args = args[2:] + } else if rj == R0 { + args = args[1:] + } else if rd == R0 { + args = append(args[:1], args[2:]...) + } + + case BEQZ, BNEZ: + if inst.Args[0].(Reg) == R0 && inst.Op == BEQ { + op = "JMP" + args = args[1:] + } + + case BLT, BLTU, BGE, BGEU: + rj := inst.Args[0].(Reg) + rd := inst.Args[1].(Reg) + if rj == rd && (inst.Op == BGE || inst.Op == BGEU) { + op = "JMP" + args = args[2:] + } else if rj == R0 { + switch inst.Op { + case BGE: + op = "BLEZ" + case BLT: + op = "BGTZ" + } + args = args[1:] + } else if rd == R0 { + if !strings.HasSuffix(op, "U") { + op += "Z" + } + args = append(args[:1], args[2:]...) + } + + case JIRL: + rd := inst.Args[0].(Reg) + rj := inst.Args[1].(Reg) + regno := uint16(rj) & 31 + off := inst.Args[2].(OffsetSimm).Imm + if rd == R0 && rj == R1 && off == 0 { + return fmt.Sprintf("RET") + } else if rd == R0 && off == 0 { + return fmt.Sprintf("JMP (R%d)", regno) + } else if rd == R0 { + return fmt.Sprintf("JMP %d(R%d)", off, regno) + } + return fmt.Sprintf("CALL (R%d)", regno) + + case LD_B, LD_H, LD_W, LD_D, LD_BU, LD_HU, LD_WU, LL_W, LL_D, + ST_B, ST_H, ST_W, ST_D, SC_W, SC_D, FLD_S, FLD_D, FST_S, FST_D: + var off int32 + switch a := inst.Args[2].(type) { + case Simm16: + off = signumConvInt32(int32(a.Imm), a.Width) + case Simm32: + off = signumConvInt32(int32(a.Imm), a.Width) >> 2 + } + Iop := strings.ToUpper(inst.Op.String()) + if strings.HasPrefix(Iop, "L") || strings.HasPrefix(Iop, "FL") { + return fmt.Sprintf("%s %d(%s), %s", op, off, args[1], args[0]) + } + return fmt.Sprintf("%s %s, %d(%s)", op, args[0], off, args[1]) + + case LDX_B, LDX_H, LDX_W, LDX_D, LDX_BU, LDX_HU, LDX_WU, FLDX_S, FLDX_D, + STX_B, STX_H, STX_W, STX_D, FSTX_S, FSTX_D: + Iop := strings.ToUpper(inst.Op.String()) + if strings.HasPrefix(Iop, "L") || strings.HasPrefix(Iop, "FL") { + return fmt.Sprintf("%s (%s)(%s), %s", op, args[1], args[2], args[0]) + } + return fmt.Sprintf("%s %s, (%s)(%s)", op, args[0], args[1], args[2]) + + case AMADD_B, AMADD_D, AMADD_DB_B, AMADD_DB_D, AMADD_DB_H, AMADD_DB_W, AMADD_H, + AMADD_W, AMAND_D, AMAND_DB_D, AMAND_DB_W, AMAND_W, AMCAS_B, AMCAS_D, AMCAS_DB_B, + AMCAS_DB_D, AMCAS_DB_H, AMCAS_DB_W, AMCAS_H, AMCAS_W, AMMAX_D, AMMAX_DB_D, + AMMAX_DB_DU, AMMAX_DB_W, AMMAX_DB_WU, AMMAX_DU, AMMAX_W, AMMAX_WU, AMMIN_D, + AMMIN_DB_D, AMMIN_DB_DU, AMMIN_DB_W, AMMIN_DB_WU, AMMIN_DU, AMMIN_W, AMMIN_WU, + AMOR_D, AMOR_DB_D, AMOR_DB_W, AMOR_W, AMSWAP_B, AMSWAP_D, AMSWAP_DB_B, AMSWAP_DB_D, + AMSWAP_DB_H, AMSWAP_DB_W, AMSWAP_H, AMSWAP_W, AMXOR_D, AMXOR_DB_D, AMXOR_DB_W, AMXOR_W: + return fmt.Sprintf("%s %s, (%s), %s", op, args[1], args[2], args[0]) + + default: + // Reverse args, placing dest last + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + switch len(args) { // Special use cases + case 0, 1: + if inst.Op != B && inst.Op != BL { + return op + } + + case 3: + switch a0 := inst.Args[0].(type) { + case Reg: + rj := inst.Args[1].(Reg) + if a0 == rj && a0 != R0 { + args = args[0:2] + } + } + switch inst.Op { + case SUB_W, SUB_D, ADDI_W, ADDI_D, ORI: + rj := inst.Args[1].(Reg) + if rj == R0 { + args = append(args[0:1], args[2:]...) + if inst.Op == SUB_W { + op = "NEGW" + } else if inst.Op == SUB_D { + op = "NEGV" + } else { + op = "MOVW" + } + } + + case ANDI: + ui12 := inst.Args[2].(Uimm) + if ui12.Imm == uint32(0xff) { + op = "MOVBU" + args = args[1:] + } else if ui12.Imm == 0 && inst.Args[0].(Reg) == R0 && inst.Args[1].(Reg) == R0 { + return "NOOP" + } + + case SLL_W, OR: + rk := inst.Args[2].(Reg) + if rk == R0 { + args = args[1:] + if inst.Op == SLL_W { + op = "MOVW" + } else { + op = "MOVV" + } + } + } + } + } + + if args != nil { + op += " " + strings.Join(args, ", ") + } + return op +} + +func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string { + // Reg: gpr[0, 31] and fpr[0, 31] + // Fcsr: fcsr[0, 3] + // Fcc: fcc[0, 7] + // Uimm: unsigned integer constant + // Simm16: si16 + // Simm32: si32 + // OffsetSimm: si32 + switch a := arg.(type) { + case Reg: + regenum := uint16(a) + regno := uint16(a) & 0x1f + // General-purpose register + if regenum >= uint16(R0) && regenum <= uint16(R31) { + return fmt.Sprintf("R%d", regno) + } else { // Float point register + return fmt.Sprintf("F%d", regno) + } + + case Fcsr: + regno := uint8(a) & 0x1f + return fmt.Sprintf("FCSR%d", regno) + + case Fcc: + regno := uint8(a) & 0x1f + return fmt.Sprintf("FCC%d", regno) + + case Uimm: + return fmt.Sprintf("$%d", a.Imm) + + case Simm16: + si16 := signumConvInt32(int32(a.Imm), a.Width) + return fmt.Sprintf("$%d", si16) + + case Simm32: + si32 := signumConvInt32(a.Imm, a.Width) + return fmt.Sprintf("$%d", si32) + + case OffsetSimm: + offs := offsConvInt32(a.Imm, a.Width) + if inst.Op == B || inst.Op == BL { + addr := int64(pc) + int64(a.Imm) + if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base { + return fmt.Sprintf("%s(SB)", s) + } + } + return fmt.Sprintf("%d(PC)", offs>>2) + + case SaSimm: + return fmt.Sprintf("$%d", a) + + case CodeSimm: + return fmt.Sprintf("$%d", a) + + } + return strings.ToUpper(arg.String()) +} + +func signumConvInt32(imm int32, width uint8) int32 { + active := uint32(1<> (width - 1)) & 0x1) == 1 { + signum |= ^active + } + return int32(signum) +} + +func offsConvInt32(imm int32, width uint8) int32 { + relWidth := width + 2 + return signumConvInt32(imm, relWidth) +} + +var plan9OpMap = map[Op]string{ + ADD_W: "ADD", + ADD_D: "ADDV", + SUB_W: "SUB", + SUB_D: "SUBV", + ADDI_W: "ADD", + ADDI_D: "ADDV", + LU12I_W: "LU12IW", + LU32I_D: "LU32ID", + LU52I_D: "LU52ID", + SLT: "SGT", + SLTU: "SGTU", + SLTI: "SGT", + SLTUI: "SGTU", + PCADDU12I: "PCADDU12I", + PCALAU12I: "PCALAU12I", + AND: "AND", + OR: "OR", + NOR: "NOR", + XOR: "XOR", + ANDI: "AND", + ORI: "OR", + XORI: "XOR", + MUL_W: "MUL", + MULH_W: "MULH", + MULH_WU: "MULHU", + MUL_D: "MULV", + MULH_D: "MULHV", + MULH_DU: "MULHVU", + DIV_W: "DIV", + DIV_WU: "DIVU", + DIV_D: "DIVV", + DIV_DU: "DIVVU", + MOD_W: "REM", + MOD_WU: "REMU", + MOD_D: "REMV", + MOD_DU: "REMVU", + SLL_W: "SLL", + SRL_W: "SRL", + SRA_W: "SRA", + ROTR_W: "ROTR", + SLL_D: "SLLV", + SRL_D: "SRLV", + SRA_D: "SRAV", + ROTR_D: "ROTRV", + SLLI_W: "SLL", + SRLI_W: "SRL", + SRAI_W: "SRA", + ROTRI_W: "ROTR", + SLLI_D: "SLLV", + SRLI_D: "SRLV", + SRAI_D: "SRAV", + ROTRI_D: "ROTRV", + EXT_W_B: "?", + EXT_W_H: "?", + BITREV_W: "BITREVW", + BITREV_D: "BITREVV", + CLO_W: "CLOW", + CLO_D: "CLOV", + CLZ_W: "CLZW", + CLZ_D: "CLZV", + CTO_W: "CTOW", + CTO_D: "CTOV", + CTZ_W: "CTZW", + CTZ_D: "CTZV", + REVB_2H: "REVB2H", + REVB_2W: "REVB2W", + REVB_4H: "REVB4H", + REVB_D: "REVBV", + BSTRPICK_W: "BSTRPICKW", + BSTRPICK_D: "BSTRPICKV", + BSTRINS_W: "BSTRINSW", + BSTRINS_D: "BSTRINSV", + MASKEQZ: "MASKEQZ", + MASKNEZ: "MASKNEZ", + BCNEZ: "BFPT", + BCEQZ: "BFPF", + BEQ: "BEQ", + BNE: "BNE", + BEQZ: "BEQ", + BNEZ: "BNE", + BLT: "BLT", + BLTU: "BLTU", + BGE: "BGE", + BGEU: "BGEU", + B: "JMP", + BL: "CALL", + LD_B: "MOVB", + LD_H: "MOVH", + LD_W: "MOVW", + LD_D: "MOVV", + LD_BU: "MOVBU", + LD_HU: "MOVHU", + LD_WU: "MOVWU", + ST_B: "MOVB", + ST_H: "MOVH", + ST_W: "MOVW", + ST_D: "MOVV", + LDX_B: "MOVB", + LDX_BU: "MOVBU", + LDX_D: "MOVV", + LDX_H: "MOVH", + LDX_HU: "MOVHU", + LDX_W: "MOVW", + LDX_WU: "MOVWU", + STX_B: "MOVB", + STX_D: "MOVV", + STX_H: "MOVH", + STX_W: "MOVW", + AMADD_B: "AMADDB", + AMADD_D: "AMADDV", + AMADD_DB_B: "AMADDDBB", + AMADD_DB_D: "AMADDDBV", + AMADD_DB_H: "AMADDDBH", + AMADD_DB_W: "AMADDDBW", + AMADD_H: "AMADDH", + AMADD_W: "AMADDW", + AMAND_D: "AMANDV", + AMAND_DB_D: "AMANDDBV", + AMAND_DB_W: "AMANDDBW", + AMAND_W: "AMANDW", + AMCAS_B: "AMCASB", + AMCAS_D: "AMCASV", + AMCAS_DB_B: "AMCASDBB", + AMCAS_DB_D: "AMCASDBV", + AMCAS_DB_H: "AMCASDBH", + AMCAS_DB_W: "AMCASDBW", + AMCAS_H: "AMCASH", + AMCAS_W: "AMCASW", + AMMAX_D: "AMMAXV", + AMMAX_DB_D: "AMMAXDBV", + AMMAX_DB_DU: "AMMAXDBVU", + AMMAX_DB_W: "AMMAXDBW", + AMMAX_DB_WU: "AMMAXDBWU", + AMMAX_DU: "AMMAXVU", + AMMAX_W: "AMMAXW", + AMMAX_WU: "AMMAXWU", + AMMIN_D: "AMMINV", + AMMIN_DB_D: "AMMINDBV", + AMMIN_DB_DU: "AMMINDBVU", + AMMIN_DB_W: "AMMINDBW", + AMMIN_DB_WU: "AMMINDBWU", + AMMIN_DU: "AMMINVU", + AMMIN_W: "AMMINW", + AMMIN_WU: "AMMINWU", + AMOR_D: "AMORV", + AMOR_DB_D: "AMORDBV", + AMOR_DB_W: "AMORDBW", + AMOR_W: "AMORW", + AMSWAP_B: "AMSWAPB", + AMSWAP_D: "AMSWAPV", + AMSWAP_DB_B: "AMSWAPDBB", + AMSWAP_DB_D: "AMSWAPDBV", + AMSWAP_DB_H: "AMSWAPDBH", + AMSWAP_DB_W: "AMSWAPDBW", + AMSWAP_H: "AMSWAPH", + AMSWAP_W: "AMSWAPW", + AMXOR_D: "AMXORV", + AMXOR_DB_D: "AMXORDBV", + AMXOR_DB_W: "AMXORDBW", + AMXOR_W: "AMXORW", + LL_W: "LL", + LL_D: "LLV", + SC_W: "SC", + SC_D: "SCV", + CRCC_W_B_W: "CRCCWBW", + CRCC_W_D_W: "CRCCWVW", + CRCC_W_H_W: "CRCCWHW", + CRCC_W_W_W: "CRCCWWW", + CRC_W_B_W: "CRCWBW", + CRC_W_D_W: "CRCWVW", + CRC_W_H_W: "CRCWHW", + CRC_W_W_W: "CRCWWW", + DBAR: "DBAR", + SYSCALL: "SYSCALL", + BREAK: "BREAK", + RDTIMEL_W: "RDTIMELW", + RDTIMEH_W: "RDTIMEHW", + RDTIME_D: "RDTIMED", + CPUCFG: "CPUCFG", + + // Floating-point instructions + FADD_S: "ADDF", + FADD_D: "ADDD", + FSUB_S: "SUBF", + FSUB_D: "SUBD", + FMUL_S: "MULF", + FMUL_D: "MULD", + FDIV_S: "DIVF", + FDIV_D: "DIVD", + FMSUB_S: "FMSUBF", + FMSUB_D: "FMSUBD", + FMADD_S: "FMADDF", + FMADD_D: "FMADDD", + FNMADD_S: "FNMADDF", + FNMADD_D: "FNMADDD", + FNMSUB_S: "FNMSUBF", + FNMSUB_D: "FNMSUBD", + FABS_S: "ABSF", + FABS_D: "ABSD", + FNEG_S: "NEGF", + FNEG_D: "NEGD", + FSQRT_S: "SQRTF", + FSQRT_D: "SQRTD", + FCOPYSIGN_S: "FCOPYSGF", + FCOPYSIGN_D: "FCOPYSGD", + FMAX_S: "FMAXF", + FMAX_D: "FMAXD", + FMIN_S: "FMINF", + FMIN_D: "FMIND", + FCLASS_S: "FCLASSF", + FCLASS_D: "FCLASSD", + FCMP_CEQ_S: "CMPEQF", + FCMP_CEQ_D: "CMPEQD", + FCMP_SLE_S: "CMPGEF", + FCMP_SLE_D: "CMPGED", + FCMP_SLT_S: "CMPGTF", + FCMP_SLT_D: "CMPGTD", + FCVT_D_S: "MOVFD", + FCVT_S_D: "MOVDF", + FFINT_S_W: "FFINTFW", + FFINT_S_L: "FFINTFV", + FFINT_D_W: "FFINTDW", + FFINT_D_L: "FFINTDV", + FTINTRM_L_D: "FTINTRMVD", + FTINTRM_L_S: "FTINTRMVF", + FTINTRM_W_D: "FTINTRMWD", + FTINTRM_W_S: "FTINTRMWF", + FTINTRNE_L_D: "FTINTRNEVD", + FTINTRNE_L_S: "FTINTRNEVF", + FTINTRNE_W_D: "FTINTRNEWD", + FTINTRNE_W_S: "FTINTRNEWF", + FTINTRP_L_D: "FTINTRPVD", + FTINTRP_L_S: "FTINTRPVF", + FTINTRP_W_D: "FTINTRPWD", + FTINTRP_W_S: "FTINTRPWF", + FTINTRZ_L_D: "FTINTRZVD", + FTINTRZ_L_S: "FTINTRZVF", + FTINTRZ_W_D: "FTINTRZWD", + FTINTRZ_W_S: "FTINTRZWF", + FTINT_L_D: "FTINTVD", + FTINT_L_S: "FTINTVF", + FTINT_W_D: "FTINTWD", + FTINT_W_S: "FTINTWF", + FRINT_S: "FRINTS", + FRINT_D: "FRINTD", + FMOV_S: "MOVF", + FMOV_D: "MOVD", + MOVGR2FR_W: "MOVW", + MOVGR2FR_D: "MOVV", + MOVFR2GR_S: "MOVW", + MOVFR2GR_D: "MOVV", + MOVGR2CF: "MOVV", + MOVCF2GR: "MOVV", + MOVFCSR2GR: "MOVV", + MOVGR2FCSR: "MOVV", + MOVFR2CF: "MOVV", + MOVCF2FR: "MOVV", + FLD_S: "MOVF", + FLD_D: "MOVD", + FST_S: "MOVF", + FST_D: "MOVD", + FLDX_S: "MOVF", + FLDX_D: "MOVD", + FSTX_S: "MOVF", + FSTX_D: "MOVD", +} diff --git a/loong64/loong64asm/tables.go b/loong64/loong64asm/tables.go new file mode 100644 index 00000000..ad34195b --- /dev/null +++ b/loong64/loong64asm/tables.go @@ -0,0 +1,1613 @@ +// Code generated by loong64spec LoongArch-Vol1-EN.pdf, DO NOT EDIT. + +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package loong64asm + +const ( + _ Op = iota + ADDI_D + ADDI_W + ADDU16I_D + ADD_D + ADD_W + ALSL_D + ALSL_W + ALSL_WU + AMADD_B + AMADD_D + AMADD_DB_B + AMADD_DB_D + AMADD_DB_H + AMADD_DB_W + AMADD_H + AMADD_W + AMAND_D + AMAND_DB_D + AMAND_DB_W + AMAND_W + AMCAS_B + AMCAS_D + AMCAS_DB_B + AMCAS_DB_D + AMCAS_DB_H + AMCAS_DB_W + AMCAS_H + AMCAS_W + AMMAX_D + AMMAX_DB_D + AMMAX_DB_DU + AMMAX_DB_W + AMMAX_DB_WU + AMMAX_DU + AMMAX_W + AMMAX_WU + AMMIN_D + AMMIN_DB_D + AMMIN_DB_DU + AMMIN_DB_W + AMMIN_DB_WU + AMMIN_DU + AMMIN_W + AMMIN_WU + AMOR_D + AMOR_DB_D + AMOR_DB_W + AMOR_W + AMSWAP_B + AMSWAP_D + AMSWAP_DB_B + AMSWAP_DB_D + AMSWAP_DB_H + AMSWAP_DB_W + AMSWAP_H + AMSWAP_W + AMXOR_D + AMXOR_DB_D + AMXOR_DB_W + AMXOR_W + AND + ANDI + ANDN + ASRTGT_D + ASRTLE_D + B + BCEQZ + BCNEZ + BEQ + BEQZ + BGE + BGEU + BITREV_4B + BITREV_8B + BITREV_D + BITREV_W + BL + BLT + BLTU + BNE + BNEZ + BREAK + BSTRINS_D + BSTRINS_W + BSTRPICK_D + BSTRPICK_W + BYTEPICK_D + BYTEPICK_W + CACOP + CLO_D + CLO_W + CLZ_D + CLZ_W + CPUCFG + CRCC_W_B_W + CRCC_W_D_W + CRCC_W_H_W + CRCC_W_W_W + CRC_W_B_W + CRC_W_D_W + CRC_W_H_W + CRC_W_W_W + CSRRD + CSRWR + CSRXCHG + CTO_D + CTO_W + CTZ_D + CTZ_W + DBAR + DBCL + DIV_D + DIV_DU + DIV_W + DIV_WU + ERTN + EXT_W_B + EXT_W_H + FABS_D + FABS_S + FADD_D + FADD_S + FCLASS_D + FCLASS_S + FCMP_CAF_D + FCMP_CAF_S + FCMP_CEQ_D + FCMP_CEQ_S + FCMP_CLE_D + FCMP_CLE_S + FCMP_CLT_D + FCMP_CLT_S + FCMP_CNE_D + FCMP_CNE_S + FCMP_COR_D + FCMP_COR_S + FCMP_CUEQ_D + FCMP_CUEQ_S + FCMP_CULE_D + FCMP_CULE_S + FCMP_CULT_D + FCMP_CULT_S + FCMP_CUNE_D + FCMP_CUNE_S + FCMP_CUN_D + FCMP_CUN_S + FCMP_SAF_D + FCMP_SAF_S + FCMP_SEQ_D + FCMP_SEQ_S + FCMP_SLE_D + FCMP_SLE_S + FCMP_SLT_D + FCMP_SLT_S + FCMP_SNE_D + FCMP_SNE_S + FCMP_SOR_D + FCMP_SOR_S + FCMP_SUEQ_D + FCMP_SUEQ_S + FCMP_SULE_D + FCMP_SULE_S + FCMP_SULT_D + FCMP_SULT_S + FCMP_SUNE_D + FCMP_SUNE_S + FCMP_SUN_D + FCMP_SUN_S + FCOPYSIGN_D + FCOPYSIGN_S + FCVT_D_S + FCVT_S_D + FDIV_D + FDIV_S + FFINT_D_L + FFINT_D_W + FFINT_S_L + FFINT_S_W + FLDGT_D + FLDGT_S + FLDLE_D + FLDLE_S + FLDX_D + FLDX_S + FLD_D + FLD_S + FLOGB_D + FLOGB_S + FMADD_D + FMADD_S + FMAXA_D + FMAXA_S + FMAX_D + FMAX_S + FMINA_D + FMINA_S + FMIN_D + FMIN_S + FMOV_D + FMOV_S + FMSUB_D + FMSUB_S + FMUL_D + FMUL_S + FNEG_D + FNEG_S + FNMADD_D + FNMADD_S + FNMSUB_D + FNMSUB_S + FRECIPE_D + FRECIPE_S + FRECIP_D + FRECIP_S + FRINT_D + FRINT_S + FRSQRTE_D + FRSQRTE_S + FRSQRT_D + FRSQRT_S + FSCALEB_D + FSCALEB_S + FSEL + FSQRT_D + FSQRT_S + FSTGT_D + FSTGT_S + FSTLE_D + FSTLE_S + FSTX_D + FSTX_S + FST_D + FST_S + FSUB_D + FSUB_S + FTINTRM_L_D + FTINTRM_L_S + FTINTRM_W_D + FTINTRM_W_S + FTINTRNE_L_D + FTINTRNE_L_S + FTINTRNE_W_D + FTINTRNE_W_S + FTINTRP_L_D + FTINTRP_L_S + FTINTRP_W_D + FTINTRP_W_S + FTINTRZ_L_D + FTINTRZ_L_S + FTINTRZ_W_D + FTINTRZ_W_S + FTINT_L_D + FTINT_L_S + FTINT_W_D + FTINT_W_S + IBAR + IDLE + INVTLB + IOCSRRD_B + IOCSRRD_D + IOCSRRD_H + IOCSRRD_W + IOCSRWR_B + IOCSRWR_D + IOCSRWR_H + IOCSRWR_W + JIRL + LDDIR + LDGT_B + LDGT_D + LDGT_H + LDGT_W + LDLE_B + LDLE_D + LDLE_H + LDLE_W + LDPTE + LDPTR_D + LDPTR_W + LDX_B + LDX_BU + LDX_D + LDX_H + LDX_HU + LDX_W + LDX_WU + LD_B + LD_BU + LD_D + LD_H + LD_HU + LD_W + LD_WU + LLACQ_D + LLACQ_W + LL_D + LL_W + LU12I_W + LU32I_D + LU52I_D + MASKEQZ + MASKNEZ + MOD_D + MOD_DU + MOD_W + MOD_WU + MOVCF2FR + MOVCF2GR + MOVFCSR2GR + MOVFR2CF + MOVFR2GR_D + MOVFR2GR_S + MOVFRH2GR_S + MOVGR2CF + MOVGR2FCSR + MOVGR2FRH_W + MOVGR2FR_D + MOVGR2FR_W + MULH_D + MULH_DU + MULH_W + MULH_WU + MULW_D_W + MULW_D_WU + MUL_D + MUL_W + NOR + OR + ORI + ORN + PCADDI + PCADDU12I + PCADDU18I + PCALAU12I + PRELD + PRELDX + RDTIMEH_W + RDTIMEL_W + RDTIME_D + REVB_2H + REVB_2W + REVB_4H + REVB_D + REVH_2W + REVH_D + ROTRI_D + ROTRI_W + ROTR_D + ROTR_W + SCREL_D + SCREL_W + SC_D + SC_Q + SC_W + SLLI_D + SLLI_W + SLL_D + SLL_W + SLT + SLTI + SLTU + SLTUI + SRAI_D + SRAI_W + SRA_D + SRA_W + SRLI_D + SRLI_W + SRL_D + SRL_W + STGT_B + STGT_D + STGT_H + STGT_W + STLE_B + STLE_D + STLE_H + STLE_W + STPTR_D + STPTR_W + STX_B + STX_D + STX_H + STX_W + ST_B + ST_D + ST_H + ST_W + SUB_D + SUB_W + SYSCALL + TLBCLR + TLBFILL + TLBFLUSH + TLBRD + TLBSRCH + TLBWR + XOR + XORI +) + +var opstr = [...]string{ + ADDI_D: "ADDI.D", + ADDI_W: "ADDI.W", + ADDU16I_D: "ADDU16I.D", + ADD_D: "ADD.D", + ADD_W: "ADD.W", + ALSL_D: "ALSL.D", + ALSL_W: "ALSL.W", + ALSL_WU: "ALSL.WU", + AMADD_B: "AMADD.B", + AMADD_D: "AMADD.D", + AMADD_DB_B: "AMADD_DB.B", + AMADD_DB_D: "AMADD_DB.D", + AMADD_DB_H: "AMADD_DB.H", + AMADD_DB_W: "AMADD_DB.W", + AMADD_H: "AMADD.H", + AMADD_W: "AMADD.W", + AMAND_D: "AMAND.D", + AMAND_DB_D: "AMAND_DB.D", + AMAND_DB_W: "AMAND_DB.W", + AMAND_W: "AMAND.W", + AMCAS_B: "AMCAS.B", + AMCAS_D: "AMCAS.D", + AMCAS_DB_B: "AMCAS_DB.B", + AMCAS_DB_D: "AMCAS_DB.D", + AMCAS_DB_H: "AMCAS_DB.H", + AMCAS_DB_W: "AMCAS_DB.W", + AMCAS_H: "AMCAS.H", + AMCAS_W: "AMCAS.W", + AMMAX_D: "AMMAX.D", + AMMAX_DB_D: "AMMAX_DB.D", + AMMAX_DB_DU: "AMMAX_DB.DU", + AMMAX_DB_W: "AMMAX_DB.W", + AMMAX_DB_WU: "AMMAX_DB.WU", + AMMAX_DU: "AMMAX.DU", + AMMAX_W: "AMMAX.W", + AMMAX_WU: "AMMAX.WU", + AMMIN_D: "AMMIN.D", + AMMIN_DB_D: "AMMIN_DB.D", + AMMIN_DB_DU: "AMMIN_DB.DU", + AMMIN_DB_W: "AMMIN_DB.W", + AMMIN_DB_WU: "AMMIN_DB.WU", + AMMIN_DU: "AMMIN.DU", + AMMIN_W: "AMMIN.W", + AMMIN_WU: "AMMIN.WU", + AMOR_D: "AMOR.D", + AMOR_DB_D: "AMOR_DB.D", + AMOR_DB_W: "AMOR_DB.W", + AMOR_W: "AMOR.W", + AMSWAP_B: "AMSWAP.B", + AMSWAP_D: "AMSWAP.D", + AMSWAP_DB_B: "AMSWAP_DB.B", + AMSWAP_DB_D: "AMSWAP_DB.D", + AMSWAP_DB_H: "AMSWAP_DB.H", + AMSWAP_DB_W: "AMSWAP_DB.W", + AMSWAP_H: "AMSWAP.H", + AMSWAP_W: "AMSWAP.W", + AMXOR_D: "AMXOR.D", + AMXOR_DB_D: "AMXOR_DB.D", + AMXOR_DB_W: "AMXOR_DB.W", + AMXOR_W: "AMXOR.W", + AND: "AND", + ANDI: "ANDI", + ANDN: "ANDN", + ASRTGT_D: "ASRTGT.D", + ASRTLE_D: "ASRTLE.D", + B: "B", + BCEQZ: "BCEQZ", + BCNEZ: "BCNEZ", + BEQ: "BEQ", + BEQZ: "BEQZ", + BGE: "BGE", + BGEU: "BGEU", + BITREV_4B: "BITREV.4B", + BITREV_8B: "BITREV.8B", + BITREV_D: "BITREV.D", + BITREV_W: "BITREV.W", + BL: "BL", + BLT: "BLT", + BLTU: "BLTU", + BNE: "BNE", + BNEZ: "BNEZ", + BREAK: "BREAK", + BSTRINS_D: "BSTRINS.D", + BSTRINS_W: "BSTRINS.W", + BSTRPICK_D: "BSTRPICK.D", + BSTRPICK_W: "BSTRPICK.W", + BYTEPICK_D: "BYTEPICK.D", + BYTEPICK_W: "BYTEPICK.W", + CACOP: "CACOP", + CLO_D: "CLO.D", + CLO_W: "CLO.W", + CLZ_D: "CLZ.D", + CLZ_W: "CLZ.W", + CPUCFG: "CPUCFG", + CRCC_W_B_W: "CRCC.W.B.W", + CRCC_W_D_W: "CRCC.W.D.W", + CRCC_W_H_W: "CRCC.W.H.W", + CRCC_W_W_W: "CRCC.W.W.W", + CRC_W_B_W: "CRC.W.B.W", + CRC_W_D_W: "CRC.W.D.W", + CRC_W_H_W: "CRC.W.H.W", + CRC_W_W_W: "CRC.W.W.W", + CSRRD: "CSRRD", + CSRWR: "CSRWR", + CSRXCHG: "CSRXCHG", + CTO_D: "CTO.D", + CTO_W: "CTO.W", + CTZ_D: "CTZ.D", + CTZ_W: "CTZ.W", + DBAR: "DBAR", + DBCL: "DBCL", + DIV_D: "DIV.D", + DIV_DU: "DIV.DU", + DIV_W: "DIV.W", + DIV_WU: "DIV.WU", + ERTN: "ERTN", + EXT_W_B: "EXT.W.B", + EXT_W_H: "EXT.W.H", + FABS_D: "FABS.D", + FABS_S: "FABS.S", + FADD_D: "FADD.D", + FADD_S: "FADD.S", + FCLASS_D: "FCLASS.D", + FCLASS_S: "FCLASS.S", + FCMP_CAF_D: "FCMP.CAF.D", + FCMP_CAF_S: "FCMP.CAF.S", + FCMP_CEQ_D: "FCMP.CEQ.D", + FCMP_CEQ_S: "FCMP.CEQ.S", + FCMP_CLE_D: "FCMP.CLE.D", + FCMP_CLE_S: "FCMP.CLE.S", + FCMP_CLT_D: "FCMP.CLT.D", + FCMP_CLT_S: "FCMP.CLT.S", + FCMP_CNE_D: "FCMP.CNE.D", + FCMP_CNE_S: "FCMP.CNE.S", + FCMP_COR_D: "FCMP.COR.D", + FCMP_COR_S: "FCMP.COR.S", + FCMP_CUEQ_D: "FCMP.CUEQ.D", + FCMP_CUEQ_S: "FCMP.CUEQ.S", + FCMP_CULE_D: "FCMP.CULE.D", + FCMP_CULE_S: "FCMP.CULE.S", + FCMP_CULT_D: "FCMP.CULT.D", + FCMP_CULT_S: "FCMP.CULT.S", + FCMP_CUNE_D: "FCMP.CUNE.D", + FCMP_CUNE_S: "FCMP.CUNE.S", + FCMP_CUN_D: "FCMP.CUN.D", + FCMP_CUN_S: "FCMP.CUN.S", + FCMP_SAF_D: "FCMP.SAF.D", + FCMP_SAF_S: "FCMP.SAF.S", + FCMP_SEQ_D: "FCMP.SEQ.D", + FCMP_SEQ_S: "FCMP.SEQ.S", + FCMP_SLE_D: "FCMP.SLE.D", + FCMP_SLE_S: "FCMP.SLE.S", + FCMP_SLT_D: "FCMP.SLT.D", + FCMP_SLT_S: "FCMP.SLT.S", + FCMP_SNE_D: "FCMP.SNE.D", + FCMP_SNE_S: "FCMP.SNE.S", + FCMP_SOR_D: "FCMP.SOR.D", + FCMP_SOR_S: "FCMP.SOR.S", + FCMP_SUEQ_D: "FCMP.SUEQ.D", + FCMP_SUEQ_S: "FCMP.SUEQ.S", + FCMP_SULE_D: "FCMP.SULE.D", + FCMP_SULE_S: "FCMP.SULE.S", + FCMP_SULT_D: "FCMP.SULT.D", + FCMP_SULT_S: "FCMP.SULT.S", + FCMP_SUNE_D: "FCMP.SUNE.D", + FCMP_SUNE_S: "FCMP.SUNE.S", + FCMP_SUN_D: "FCMP.SUN.D", + FCMP_SUN_S: "FCMP.SUN.S", + FCOPYSIGN_D: "FCOPYSIGN.D", + FCOPYSIGN_S: "FCOPYSIGN.S", + FCVT_D_S: "FCVT.D.S", + FCVT_S_D: "FCVT.S.D", + FDIV_D: "FDIV.D", + FDIV_S: "FDIV.S", + FFINT_D_L: "FFINT.D.L", + FFINT_D_W: "FFINT.D.W", + FFINT_S_L: "FFINT.S.L", + FFINT_S_W: "FFINT.S.W", + FLDGT_D: "FLDGT.D", + FLDGT_S: "FLDGT.S", + FLDLE_D: "FLDLE.D", + FLDLE_S: "FLDLE.S", + FLDX_D: "FLDX.D", + FLDX_S: "FLDX.S", + FLD_D: "FLD.D", + FLD_S: "FLD.S", + FLOGB_D: "FLOGB.D", + FLOGB_S: "FLOGB.S", + FMADD_D: "FMADD.D", + FMADD_S: "FMADD.S", + FMAXA_D: "FMAXA.D", + FMAXA_S: "FMAXA.S", + FMAX_D: "FMAX.D", + FMAX_S: "FMAX.S", + FMINA_D: "FMINA.D", + FMINA_S: "FMINA.S", + FMIN_D: "FMIN.D", + FMIN_S: "FMIN.S", + FMOV_D: "FMOV.D", + FMOV_S: "FMOV.S", + FMSUB_D: "FMSUB.D", + FMSUB_S: "FMSUB.S", + FMUL_D: "FMUL.D", + FMUL_S: "FMUL.S", + FNEG_D: "FNEG.D", + FNEG_S: "FNEG.S", + FNMADD_D: "FNMADD.D", + FNMADD_S: "FNMADD.S", + FNMSUB_D: "FNMSUB.D", + FNMSUB_S: "FNMSUB.S", + FRECIPE_D: "FRECIPE.D", + FRECIPE_S: "FRECIPE.S", + FRECIP_D: "FRECIP.D", + FRECIP_S: "FRECIP.S", + FRINT_D: "FRINT.D", + FRINT_S: "FRINT.S", + FRSQRTE_D: "FRSQRTE.D", + FRSQRTE_S: "FRSQRTE.S", + FRSQRT_D: "FRSQRT.D", + FRSQRT_S: "FRSQRT.S", + FSCALEB_D: "FSCALEB.D", + FSCALEB_S: "FSCALEB.S", + FSEL: "FSEL", + FSQRT_D: "FSQRT.D", + FSQRT_S: "FSQRT.S", + FSTGT_D: "FSTGT.D", + FSTGT_S: "FSTGT.S", + FSTLE_D: "FSTLE.D", + FSTLE_S: "FSTLE.S", + FSTX_D: "FSTX.D", + FSTX_S: "FSTX.S", + FST_D: "FST.D", + FST_S: "FST.S", + FSUB_D: "FSUB.D", + FSUB_S: "FSUB.S", + FTINTRM_L_D: "FTINTRM.L.D", + FTINTRM_L_S: "FTINTRM.L.S", + FTINTRM_W_D: "FTINTRM.W.D", + FTINTRM_W_S: "FTINTRM.W.S", + FTINTRNE_L_D: "FTINTRNE.L.D", + FTINTRNE_L_S: "FTINTRNE.L.S", + FTINTRNE_W_D: "FTINTRNE.W.D", + FTINTRNE_W_S: "FTINTRNE.W.S", + FTINTRP_L_D: "FTINTRP.L.D", + FTINTRP_L_S: "FTINTRP.L.S", + FTINTRP_W_D: "FTINTRP.W.D", + FTINTRP_W_S: "FTINTRP.W.S", + FTINTRZ_L_D: "FTINTRZ.L.D", + FTINTRZ_L_S: "FTINTRZ.L.S", + FTINTRZ_W_D: "FTINTRZ.W.D", + FTINTRZ_W_S: "FTINTRZ.W.S", + FTINT_L_D: "FTINT.L.D", + FTINT_L_S: "FTINT.L.S", + FTINT_W_D: "FTINT.W.D", + FTINT_W_S: "FTINT.W.S", + IBAR: "IBAR", + IDLE: "IDLE", + INVTLB: "INVTLB", + IOCSRRD_B: "IOCSRRD.B", + IOCSRRD_D: "IOCSRRD.D", + IOCSRRD_H: "IOCSRRD.H", + IOCSRRD_W: "IOCSRRD.W", + IOCSRWR_B: "IOCSRWR.B", + IOCSRWR_D: "IOCSRWR.D", + IOCSRWR_H: "IOCSRWR.H", + IOCSRWR_W: "IOCSRWR.W", + JIRL: "JIRL", + LDDIR: "LDDIR", + LDGT_B: "LDGT.B", + LDGT_D: "LDGT.D", + LDGT_H: "LDGT.H", + LDGT_W: "LDGT.W", + LDLE_B: "LDLE.B", + LDLE_D: "LDLE.D", + LDLE_H: "LDLE.H", + LDLE_W: "LDLE.W", + LDPTE: "LDPTE", + LDPTR_D: "LDPTR.D", + LDPTR_W: "LDPTR.W", + LDX_B: "LDX.B", + LDX_BU: "LDX.BU", + LDX_D: "LDX.D", + LDX_H: "LDX.H", + LDX_HU: "LDX.HU", + LDX_W: "LDX.W", + LDX_WU: "LDX.WU", + LD_B: "LD.B", + LD_BU: "LD.BU", + LD_D: "LD.D", + LD_H: "LD.H", + LD_HU: "LD.HU", + LD_W: "LD.W", + LD_WU: "LD.WU", + LLACQ_D: "LLACQ.D", + LLACQ_W: "LLACQ.W", + LL_D: "LL.D", + LL_W: "LL.W", + LU12I_W: "LU12I.W", + LU32I_D: "LU32I.D", + LU52I_D: "LU52I.D", + MASKEQZ: "MASKEQZ", + MASKNEZ: "MASKNEZ", + MOD_D: "MOD.D", + MOD_DU: "MOD.DU", + MOD_W: "MOD.W", + MOD_WU: "MOD.WU", + MOVCF2FR: "MOVCF2FR", + MOVCF2GR: "MOVCF2GR", + MOVFCSR2GR: "MOVFCSR2GR", + MOVFR2CF: "MOVFR2CF", + MOVFR2GR_D: "MOVFR2GR.D", + MOVFR2GR_S: "MOVFR2GR.S", + MOVFRH2GR_S: "MOVFRH2GR.S", + MOVGR2CF: "MOVGR2CF", + MOVGR2FCSR: "MOVGR2FCSR", + MOVGR2FRH_W: "MOVGR2FRH.W", + MOVGR2FR_D: "MOVGR2FR.D", + MOVGR2FR_W: "MOVGR2FR.W", + MULH_D: "MULH.D", + MULH_DU: "MULH.DU", + MULH_W: "MULH.W", + MULH_WU: "MULH.WU", + MULW_D_W: "MULW.D.W", + MULW_D_WU: "MULW.D.WU", + MUL_D: "MUL.D", + MUL_W: "MUL.W", + NOR: "NOR", + OR: "OR", + ORI: "ORI", + ORN: "ORN", + PCADDI: "PCADDI", + PCADDU12I: "PCADDU12I", + PCADDU18I: "PCADDU18I", + PCALAU12I: "PCALAU12I", + PRELD: "PRELD", + PRELDX: "PRELDX", + RDTIMEH_W: "RDTIMEH.W", + RDTIMEL_W: "RDTIMEL.W", + RDTIME_D: "RDTIME.D", + REVB_2H: "REVB.2H", + REVB_2W: "REVB.2W", + REVB_4H: "REVB.4H", + REVB_D: "REVB.D", + REVH_2W: "REVH.2W", + REVH_D: "REVH.D", + ROTRI_D: "ROTRI.D", + ROTRI_W: "ROTRI.W", + ROTR_D: "ROTR.D", + ROTR_W: "ROTR.W", + SCREL_D: "SCREL.D", + SCREL_W: "SCREL.W", + SC_D: "SC.D", + SC_Q: "SC.Q", + SC_W: "SC.W", + SLLI_D: "SLLI.D", + SLLI_W: "SLLI.W", + SLL_D: "SLL.D", + SLL_W: "SLL.W", + SLT: "SLT", + SLTI: "SLTI", + SLTU: "SLTU", + SLTUI: "SLTUI", + SRAI_D: "SRAI.D", + SRAI_W: "SRAI.W", + SRA_D: "SRA.D", + SRA_W: "SRA.W", + SRLI_D: "SRLI.D", + SRLI_W: "SRLI.W", + SRL_D: "SRL.D", + SRL_W: "SRL.W", + STGT_B: "STGT.B", + STGT_D: "STGT.D", + STGT_H: "STGT.H", + STGT_W: "STGT.W", + STLE_B: "STLE.B", + STLE_D: "STLE.D", + STLE_H: "STLE.H", + STLE_W: "STLE.W", + STPTR_D: "STPTR.D", + STPTR_W: "STPTR.W", + STX_B: "STX.B", + STX_D: "STX.D", + STX_H: "STX.H", + STX_W: "STX.W", + ST_B: "ST.B", + ST_D: "ST.D", + ST_H: "ST.H", + ST_W: "ST.W", + SUB_D: "SUB.D", + SUB_W: "SUB.W", + SYSCALL: "SYSCALL", + TLBCLR: "TLBCLR", + TLBFILL: "TLBFILL", + TLBFLUSH: "TLBFLUSH", + TLBRD: "TLBRD", + TLBSRCH: "TLBSRCH", + TLBWR: "TLBWR", + XOR: "XOR", + XORI: "XORI", +} + +var instFormats = [...]instFormat{ + // ADDI.D rd, rj, si12 + {mask: 0xffc00000, value: 0x02c00000, op: ADDI_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // ADDI.W rd, rj, si12 + {mask: 0xffc00000, value: 0x02800000, op: ADDI_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // ADDU16I.D rd, rj, si16 + {mask: 0xfc000000, value: 0x10000000, op: ADDU16I_D, args: instArgs{arg_rd, arg_rj, arg_si16_25_10}}, + // ADD.D rd, rj, rk + {mask: 0xffff8000, value: 0x00108000, op: ADD_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // ADD.W rd, rj, rk + {mask: 0xffff8000, value: 0x00100000, op: ADD_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // ALSL.D rd, rj, rk, sa2 + {mask: 0xfffe0000, value: 0x002c0000, op: ALSL_D, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}}, + // ALSL.W rd, rj, rk, sa2 + {mask: 0xfffe0000, value: 0x00040000, op: ALSL_W, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}}, + // ALSL.WU rd, rj, rk, sa2 + {mask: 0xfffe0000, value: 0x00060000, op: ALSL_WU, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}}, + // AMADD.B rd, rk, rj + {mask: 0xffff8000, value: 0x385d0000, op: AMADD_B, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMADD.D rd, rk, rj + {mask: 0xffff8000, value: 0x38618000, op: AMADD_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMADD_DB.B rd, rk, rj + {mask: 0xffff8000, value: 0x385f0000, op: AMADD_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMADD_DB.D rd, rk, rj + {mask: 0xffff8000, value: 0x386a8000, op: AMADD_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMADD_DB.H rd, rk, rj + {mask: 0xffff8000, value: 0x385f8000, op: AMADD_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMADD_DB.W rd, rk, rj + {mask: 0xffff8000, value: 0x386a0000, op: AMADD_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMADD.H rd, rk, rj + {mask: 0xffff8000, value: 0x385d8000, op: AMADD_H, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMADD.W rd, rk, rj + {mask: 0xffff8000, value: 0x38610000, op: AMADD_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMAND.D rd, rk, rj + {mask: 0xffff8000, value: 0x38628000, op: AMAND_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMAND_DB.D rd, rk, rj + {mask: 0xffff8000, value: 0x386b8000, op: AMAND_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMAND_DB.W rd, rk, rj + {mask: 0xffff8000, value: 0x386b0000, op: AMAND_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMAND.W rd, rk, rj + {mask: 0xffff8000, value: 0x38620000, op: AMAND_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMCAS.B rd, rk, rj + {mask: 0xffff8000, value: 0x38580000, op: AMCAS_B, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMCAS.D rd, rk, rj + {mask: 0xffff8000, value: 0x38598000, op: AMCAS_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMCAS_DB.B rd, rk, rj + {mask: 0xffff8000, value: 0x385a0000, op: AMCAS_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMCAS_DB.D rd, rk, rj + {mask: 0xffff8000, value: 0x385b8000, op: AMCAS_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMCAS_DB.H rd, rk, rj + {mask: 0xffff8000, value: 0x385a8000, op: AMCAS_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMCAS_DB.W rd, rk, rj + {mask: 0xffff8000, value: 0x385b0000, op: AMCAS_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMCAS.H rd, rk, rj + {mask: 0xffff8000, value: 0x38588000, op: AMCAS_H, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMCAS.W rd, rk, rj + {mask: 0xffff8000, value: 0x38590000, op: AMCAS_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMAX.D rd, rk, rj + {mask: 0xffff8000, value: 0x38658000, op: AMMAX_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMAX_DB.D rd, rk, rj + {mask: 0xffff8000, value: 0x386e8000, op: AMMAX_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMAX_DB.DU rd, rk, rj + {mask: 0xffff8000, value: 0x38708000, op: AMMAX_DB_DU, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMAX_DB.W rd, rk, rj + {mask: 0xffff8000, value: 0x386e0000, op: AMMAX_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMAX_DB.WU rd, rk, rj + {mask: 0xffff8000, value: 0x38700000, op: AMMAX_DB_WU, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMAX.DU rd, rk, rj + {mask: 0xffff8000, value: 0x38678000, op: AMMAX_DU, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMAX.W rd, rk, rj + {mask: 0xffff8000, value: 0x38650000, op: AMMAX_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMAX.WU rd, rk, rj + {mask: 0xffff8000, value: 0x38670000, op: AMMAX_WU, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMIN.D rd, rk, rj + {mask: 0xffff8000, value: 0x38668000, op: AMMIN_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMIN_DB.D rd, rk, rj + {mask: 0xffff8000, value: 0x386f8000, op: AMMIN_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMIN_DB.DU rd, rk, rj + {mask: 0xffff8000, value: 0x38718000, op: AMMIN_DB_DU, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMIN_DB.W rd, rk, rj + {mask: 0xffff8000, value: 0x386f0000, op: AMMIN_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMIN_DB.WU rd, rk, rj + {mask: 0xffff8000, value: 0x38710000, op: AMMIN_DB_WU, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMIN.DU rd, rk, rj + {mask: 0xffff8000, value: 0x38688000, op: AMMIN_DU, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMIN.W rd, rk, rj + {mask: 0xffff8000, value: 0x38660000, op: AMMIN_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMMIN.WU rd, rk, rj + {mask: 0xffff8000, value: 0x38680000, op: AMMIN_WU, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMOR.D rd, rk, rj + {mask: 0xffff8000, value: 0x38638000, op: AMOR_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMOR_DB.D rd, rk, rj + {mask: 0xffff8000, value: 0x386c8000, op: AMOR_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMOR_DB.W rd, rk, rj + {mask: 0xffff8000, value: 0x386c0000, op: AMOR_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMOR.W rd, rk, rj + {mask: 0xffff8000, value: 0x38630000, op: AMOR_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMSWAP.B rd, rk, rj + {mask: 0xffff8000, value: 0x385c0000, op: AMSWAP_B, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMSWAP.D rd, rk, rj + {mask: 0xffff8000, value: 0x38608000, op: AMSWAP_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMSWAP_DB.B rd, rk, rj + {mask: 0xffff8000, value: 0x385e0000, op: AMSWAP_DB_B, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMSWAP_DB.D rd, rk, rj + {mask: 0xffff8000, value: 0x38698000, op: AMSWAP_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMSWAP_DB.H rd, rk, rj + {mask: 0xffff8000, value: 0x385e8000, op: AMSWAP_DB_H, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMSWAP_DB.W rd, rk, rj + {mask: 0xffff8000, value: 0x38690000, op: AMSWAP_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMSWAP.H rd, rk, rj + {mask: 0xffff8000, value: 0x385c8000, op: AMSWAP_H, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMSWAP.W rd, rk, rj + {mask: 0xffff8000, value: 0x38600000, op: AMSWAP_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMXOR.D rd, rk, rj + {mask: 0xffff8000, value: 0x38648000, op: AMXOR_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMXOR_DB.D rd, rk, rj + {mask: 0xffff8000, value: 0x386d8000, op: AMXOR_DB_D, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMXOR_DB.W rd, rk, rj + {mask: 0xffff8000, value: 0x386d0000, op: AMXOR_DB_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AMXOR.W rd, rk, rj + {mask: 0xffff8000, value: 0x38640000, op: AMXOR_W, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // AND rd, rj, rk + {mask: 0xffff8000, value: 0x00148000, op: AND, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // ANDI rd, rj, ui12 + {mask: 0xffc00000, value: 0x03400000, op: ANDI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}}, + // ANDN rd, rj, rk + {mask: 0xffff8000, value: 0x00168000, op: ANDN, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // ASRTGT.D rj, rk + {mask: 0xffff801f, value: 0x00018000, op: ASRTGT_D, args: instArgs{arg_rj, arg_rk}}, + // ASRTLE.D rj, rk + {mask: 0xffff801f, value: 0x00010000, op: ASRTLE_D, args: instArgs{arg_rj, arg_rk}}, + // B offs + {mask: 0xfc000000, value: 0x50000000, op: B, args: instArgs{arg_offset_25_0}}, + // BCEQZ cj, offs + {mask: 0xfc000300, value: 0x48000000, op: BCEQZ, args: instArgs{arg_cj, arg_offset_20_0}}, + // BCNEZ cj, offs + {mask: 0xfc000300, value: 0x48000100, op: BCNEZ, args: instArgs{arg_cj, arg_offset_20_0}}, + // BEQ rj, rd, offs + {mask: 0xfc000000, value: 0x58000000, op: BEQ, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}}, + // BEQZ rj, offs + {mask: 0xfc000000, value: 0x40000000, op: BEQZ, args: instArgs{arg_rj, arg_offset_20_0}}, + // BGE rj, rd, offs + {mask: 0xfc000000, value: 0x64000000, op: BGE, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}}, + // BGEU rj, rd, offs + {mask: 0xfc000000, value: 0x6c000000, op: BGEU, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}}, + // BITREV.4B rd, rj + {mask: 0xfffffc00, value: 0x00004800, op: BITREV_4B, args: instArgs{arg_rd, arg_rj}}, + // BITREV.8B rd, rj + {mask: 0xfffffc00, value: 0x00004c00, op: BITREV_8B, args: instArgs{arg_rd, arg_rj}}, + // BITREV.D rd, rj + {mask: 0xfffffc00, value: 0x00005400, op: BITREV_D, args: instArgs{arg_rd, arg_rj}}, + // BITREV.W rd, rj + {mask: 0xfffffc00, value: 0x00005000, op: BITREV_W, args: instArgs{arg_rd, arg_rj}}, + // BL offs + {mask: 0xfc000000, value: 0x54000000, op: BL, args: instArgs{arg_offset_25_0}}, + // BLT rj, rd, offs + {mask: 0xfc000000, value: 0x60000000, op: BLT, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}}, + // BLTU rj, rd, offs + {mask: 0xfc000000, value: 0x68000000, op: BLTU, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}}, + // BNE rj, rd, offs + {mask: 0xfc000000, value: 0x5c000000, op: BNE, args: instArgs{arg_rj, arg_rd, arg_offset_15_0}}, + // BNEZ rj, offs + {mask: 0xfc000000, value: 0x44000000, op: BNEZ, args: instArgs{arg_rj, arg_offset_20_0}}, + // BREAK code + {mask: 0xffff8000, value: 0x002a0000, op: BREAK, args: instArgs{arg_code_14_0}}, + // BSTRINS.D rd, rj, msbd, lsbd + {mask: 0xffc00000, value: 0x00800000, op: BSTRINS_D, args: instArgs{arg_rd, arg_rj, arg_msbd, arg_lsbd}}, + // BSTRINS.W rd, rj, msbw, lsbw + {mask: 0xffe08000, value: 0x00600000, op: BSTRINS_W, args: instArgs{arg_rd, arg_rj, arg_msbw, arg_lsbw}}, + // BSTRPICK.D rd, rj, msbd, lsbd + {mask: 0xffc00000, value: 0x00c00000, op: BSTRPICK_D, args: instArgs{arg_rd, arg_rj, arg_msbd, arg_lsbd}}, + // BSTRPICK.W rd, rj, msbw, lsbw + {mask: 0xffe08000, value: 0x00608000, op: BSTRPICK_W, args: instArgs{arg_rd, arg_rj, arg_msbw, arg_lsbw}}, + // BYTEPICK.D rd, rj, rk, sa3 + {mask: 0xfffc0000, value: 0x000c0000, op: BYTEPICK_D, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa3_17_15}}, + // BYTEPICK.W rd, rj, rk, sa2 + {mask: 0xfffe0000, value: 0x00080000, op: BYTEPICK_W, args: instArgs{arg_rd, arg_rj, arg_rk, arg_sa2_16_15}}, + // CACOP code, rj, si12 + {mask: 0xffc00000, value: 0x06000000, op: CACOP, args: instArgs{arg_code_4_0, arg_rj, arg_si12_21_10}}, + // CLO.D rd, rj + {mask: 0xfffffc00, value: 0x00002000, op: CLO_D, args: instArgs{arg_rd, arg_rj}}, + // CLO.W rd, rj + {mask: 0xfffffc00, value: 0x00001000, op: CLO_W, args: instArgs{arg_rd, arg_rj}}, + // CLZ.D rd, rj + {mask: 0xfffffc00, value: 0x00002400, op: CLZ_D, args: instArgs{arg_rd, arg_rj}}, + // CLZ.W rd, rj + {mask: 0xfffffc00, value: 0x00001400, op: CLZ_W, args: instArgs{arg_rd, arg_rj}}, + // CPUCFG rd, rj + {mask: 0xfffffc00, value: 0x00006c00, op: CPUCFG, args: instArgs{arg_rd, arg_rj}}, + // CRCC.W.B.W rd, rj, rk + {mask: 0xffff8000, value: 0x00260000, op: CRCC_W_B_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // CRCC.W.D.W rd, rj, rk + {mask: 0xffff8000, value: 0x00278000, op: CRCC_W_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // CRCC.W.H.W rd, rj, rk + {mask: 0xffff8000, value: 0x00268000, op: CRCC_W_H_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // CRCC.W.W.W rd, rj, rk + {mask: 0xffff8000, value: 0x00270000, op: CRCC_W_W_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // CRC.W.B.W rd, rj, rk + {mask: 0xffff8000, value: 0x00240000, op: CRC_W_B_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // CRC.W.D.W rd, rj, rk + {mask: 0xffff8000, value: 0x00258000, op: CRC_W_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // CRC.W.H.W rd, rj, rk + {mask: 0xffff8000, value: 0x00248000, op: CRC_W_H_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // CRC.W.W.W rd, rj, rk + {mask: 0xffff8000, value: 0x00250000, op: CRC_W_W_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // CSRRD rd, csr + {mask: 0xff0003e0, value: 0x04000000, op: CSRRD, args: instArgs{arg_rd, arg_csr_23_10}}, + // CSRWR rd, csr + {mask: 0xff0003e0, value: 0x04000020, op: CSRWR, args: instArgs{arg_rd, arg_csr_23_10}}, + // CSRXCHG rd, rj, csr + {mask: 0xff000000, value: 0x04000000, op: CSRXCHG, args: instArgs{arg_rd, arg_rj, arg_csr_23_10}}, + // CTO.D rd, rj + {mask: 0xfffffc00, value: 0x00002800, op: CTO_D, args: instArgs{arg_rd, arg_rj}}, + // CTO.W rd, rj + {mask: 0xfffffc00, value: 0x00001800, op: CTO_W, args: instArgs{arg_rd, arg_rj}}, + // CTZ.D rd, rj + {mask: 0xfffffc00, value: 0x00002c00, op: CTZ_D, args: instArgs{arg_rd, arg_rj}}, + // CTZ.W rd, rj + {mask: 0xfffffc00, value: 0x00001c00, op: CTZ_W, args: instArgs{arg_rd, arg_rj}}, + // DBAR hint + {mask: 0xffff8000, value: 0x38720000, op: DBAR, args: instArgs{arg_hint_14_0}}, + // DBCL code + {mask: 0xffff8000, value: 0x002a8000, op: DBCL, args: instArgs{arg_code_14_0}}, + // DIV.D rd, rj, rk + {mask: 0xffff8000, value: 0x00220000, op: DIV_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // DIV.DU rd, rj, rk + {mask: 0xffff8000, value: 0x00230000, op: DIV_DU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // DIV.W rd, rj, rk + {mask: 0xffff8000, value: 0x00200000, op: DIV_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // DIV.WU rd, rj, rk + {mask: 0xffff8000, value: 0x00210000, op: DIV_WU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // ERTN + {mask: 0xffffffff, value: 0x06483800, op: ERTN, args: instArgs{}}, + // EXT.W.B rd, rj + {mask: 0xfffffc00, value: 0x00005c00, op: EXT_W_B, args: instArgs{arg_rd, arg_rj}}, + // EXT.W.H rd, rj + {mask: 0xfffffc00, value: 0x00005800, op: EXT_W_H, args: instArgs{arg_rd, arg_rj}}, + // FABS.D fd, fj + {mask: 0xfffffc00, value: 0x01140800, op: FABS_D, args: instArgs{arg_fd, arg_fj}}, + // FABS.S fd, fj + {mask: 0xfffffc00, value: 0x01140400, op: FABS_S, args: instArgs{arg_fd, arg_fj}}, + // FADD.D fd, fj, fk + {mask: 0xffff8000, value: 0x01010000, op: FADD_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FADD.S fd, fj, fk + {mask: 0xffff8000, value: 0x01008000, op: FADD_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FCLASS.D fd, fj + {mask: 0xfffffc00, value: 0x01143800, op: FCLASS_D, args: instArgs{arg_fd, arg_fj}}, + // FCLASS.S fd, fj + {mask: 0xfffffc00, value: 0x01143400, op: FCLASS_S, args: instArgs{arg_fd, arg_fj}}, + // FCMP.CAF.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c200000, op: FCMP_CAF_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CAF.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c100000, op: FCMP_CAF_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CEQ.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c220000, op: FCMP_CEQ_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CEQ.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c120000, op: FCMP_CEQ_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CLE.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c230000, op: FCMP_CLE_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CLE.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c130000, op: FCMP_CLE_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CLT.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c210000, op: FCMP_CLT_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CLT.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c110000, op: FCMP_CLT_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CNE.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c280000, op: FCMP_CNE_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CNE.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c180000, op: FCMP_CNE_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.COR.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c2a0000, op: FCMP_COR_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.COR.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c1a0000, op: FCMP_COR_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CUEQ.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c260000, op: FCMP_CUEQ_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CUEQ.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c160000, op: FCMP_CUEQ_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CULE.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c270000, op: FCMP_CULE_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CULE.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c170000, op: FCMP_CULE_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CULT.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c250000, op: FCMP_CULT_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CULT.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c150000, op: FCMP_CULT_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CUNE.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c2c0000, op: FCMP_CUNE_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CUNE.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c1c0000, op: FCMP_CUNE_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CUN.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c240000, op: FCMP_CUN_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.CUN.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c140000, op: FCMP_CUN_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SAF.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c208000, op: FCMP_SAF_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SAF.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c108000, op: FCMP_SAF_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SEQ.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c228000, op: FCMP_SEQ_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SEQ.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c128000, op: FCMP_SEQ_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SLE.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c238000, op: FCMP_SLE_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SLE.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c138000, op: FCMP_SLE_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SLT.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c218000, op: FCMP_SLT_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SLT.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c118000, op: FCMP_SLT_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SNE.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c288000, op: FCMP_SNE_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SNE.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c188000, op: FCMP_SNE_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SOR.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c2a8000, op: FCMP_SOR_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SOR.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c1a8000, op: FCMP_SOR_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SUEQ.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c268000, op: FCMP_SUEQ_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SUEQ.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c168000, op: FCMP_SUEQ_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SULE.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c278000, op: FCMP_SULE_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SULE.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c178000, op: FCMP_SULE_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SULT.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c258000, op: FCMP_SULT_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SULT.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c158000, op: FCMP_SULT_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SUNE.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c2c8000, op: FCMP_SUNE_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SUNE.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c1c8000, op: FCMP_SUNE_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SUN.D cd, fj, fk + {mask: 0xffff8018, value: 0x0c248000, op: FCMP_SUN_D, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCMP.SUN.S cd, fj, fk + {mask: 0xffff8018, value: 0x0c148000, op: FCMP_SUN_S, args: instArgs{arg_cd, arg_fj, arg_fk}}, + // FCOPYSIGN.D fd, fj, fk + {mask: 0xffff8000, value: 0x01130000, op: FCOPYSIGN_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FCOPYSIGN.S fd, fj, fk + {mask: 0xffff8000, value: 0x01128000, op: FCOPYSIGN_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FCVT.D.S fd, fj + {mask: 0xfffffc00, value: 0x01192400, op: FCVT_D_S, args: instArgs{arg_fd, arg_fj}}, + // FCVT.S.D fd, fj + {mask: 0xfffffc00, value: 0x01191800, op: FCVT_S_D, args: instArgs{arg_fd, arg_fj}}, + // FDIV.D fd, fj, fk + {mask: 0xffff8000, value: 0x01070000, op: FDIV_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FDIV.S fd, fj, fk + {mask: 0xffff8000, value: 0x01068000, op: FDIV_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FFINT.D.L fd, fj + {mask: 0xfffffc00, value: 0x011d2800, op: FFINT_D_L, args: instArgs{arg_fd, arg_fj}}, + // FFINT.D.W fd, fj + {mask: 0xfffffc00, value: 0x011d2000, op: FFINT_D_W, args: instArgs{arg_fd, arg_fj}}, + // FFINT.S.L fd, fj + {mask: 0xfffffc00, value: 0x011d1800, op: FFINT_S_L, args: instArgs{arg_fd, arg_fj}}, + // FFINT.S.W fd, fj + {mask: 0xfffffc00, value: 0x011d1000, op: FFINT_S_W, args: instArgs{arg_fd, arg_fj}}, + // FLDGT.D fd, rj, rk + {mask: 0xffff8000, value: 0x38748000, op: FLDGT_D, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FLDGT.S fd, rj, rk + {mask: 0xffff8000, value: 0x38740000, op: FLDGT_S, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FLDLE.D fd, rj, rk + {mask: 0xffff8000, value: 0x38758000, op: FLDLE_D, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FLDLE.S fd, rj, rk + {mask: 0xffff8000, value: 0x38750000, op: FLDLE_S, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FLDX.D fd, rj, rk + {mask: 0xffff8000, value: 0x38340000, op: FLDX_D, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FLDX.S fd, rj, rk + {mask: 0xffff8000, value: 0x38300000, op: FLDX_S, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FLD.D fd, rj, si12 + {mask: 0xffc00000, value: 0x2b800000, op: FLD_D, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}}, + // FLD.S fd, rj, si12 + {mask: 0xffc00000, value: 0x2b000000, op: FLD_S, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}}, + // FLOGB.D fd, fj + {mask: 0xfffffc00, value: 0x01142800, op: FLOGB_D, args: instArgs{arg_fd, arg_fj}}, + // FLOGB.S fd, fj + {mask: 0xfffffc00, value: 0x01142400, op: FLOGB_S, args: instArgs{arg_fd, arg_fj}}, + // FMADD.D fd, fj, fk, fa + {mask: 0xfff00000, value: 0x08200000, op: FMADD_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}}, + // FMADD.S fd, fj, fk, fa + {mask: 0xfff00000, value: 0x08100000, op: FMADD_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}}, + // FMAXA.D fd, fj, fk + {mask: 0xffff8000, value: 0x010d0000, op: FMAXA_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMAXA.S fd, fj, fk + {mask: 0xffff8000, value: 0x010c8000, op: FMAXA_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMAX.D fd, fj, fk + {mask: 0xffff8000, value: 0x01090000, op: FMAX_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMAX.S fd, fj, fk + {mask: 0xffff8000, value: 0x01088000, op: FMAX_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMINA.D fd, fj, fk + {mask: 0xffff8000, value: 0x010f0000, op: FMINA_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMINA.S fd, fj, fk + {mask: 0xffff8000, value: 0x010e8000, op: FMINA_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMIN.D fd, fj, fk + {mask: 0xffff8000, value: 0x010b0000, op: FMIN_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMIN.S fd, fj, fk + {mask: 0xffff8000, value: 0x010a8000, op: FMIN_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMOV.D fd, fj + {mask: 0xfffffc00, value: 0x01149800, op: FMOV_D, args: instArgs{arg_fd, arg_fj}}, + // FMOV.S fd, fj + {mask: 0xfffffc00, value: 0x01149400, op: FMOV_S, args: instArgs{arg_fd, arg_fj}}, + // FMSUB.D fd, fj, fk, fa + {mask: 0xfff00000, value: 0x08600000, op: FMSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}}, + // FMSUB.S fd, fj, fk, fa + {mask: 0xfff00000, value: 0x08500000, op: FMSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}}, + // FMUL.D fd, fj, fk + {mask: 0xffff8000, value: 0x01050000, op: FMUL_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FMUL.S fd, fj, fk + {mask: 0xffff8000, value: 0x01048000, op: FMUL_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FNEG.D fd, fj + {mask: 0xfffffc00, value: 0x01141800, op: FNEG_D, args: instArgs{arg_fd, arg_fj}}, + // FNEG.S fd, fj + {mask: 0xfffffc00, value: 0x01141400, op: FNEG_S, args: instArgs{arg_fd, arg_fj}}, + // FNMADD.D fd, fj, fk, fa + {mask: 0xfff00000, value: 0x08a00000, op: FNMADD_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}}, + // FNMADD.S fd, fj, fk, fa + {mask: 0xfff00000, value: 0x08900000, op: FNMADD_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}}, + // FNMSUB.D fd, fj, fk, fa + {mask: 0xfff00000, value: 0x08e00000, op: FNMSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}}, + // FNMSUB.S fd, fj, fk, fa + {mask: 0xfff00000, value: 0x08d00000, op: FNMSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk, arg_fa}}, + // FRECIPE.D fd, fj + {mask: 0xfffffc00, value: 0x01147800, op: FRECIPE_D, args: instArgs{arg_fd, arg_fj}}, + // FRECIPE.S fd, fj + {mask: 0xfffffc00, value: 0x01147400, op: FRECIPE_S, args: instArgs{arg_fd, arg_fj}}, + // FRECIP.D fd, fj + {mask: 0xfffffc00, value: 0x01145800, op: FRECIP_D, args: instArgs{arg_fd, arg_fj}}, + // FRECIP.S fd, fj + {mask: 0xfffffc00, value: 0x01145400, op: FRECIP_S, args: instArgs{arg_fd, arg_fj}}, + // FRINT.D fd, fj + {mask: 0xfffffc00, value: 0x011e4800, op: FRINT_D, args: instArgs{arg_fd, arg_fj}}, + // FRINT.S fd, fj + {mask: 0xfffffc00, value: 0x011e4400, op: FRINT_S, args: instArgs{arg_fd, arg_fj}}, + // FRSQRTE.D fd, fj + {mask: 0xfffffc00, value: 0x01148800, op: FRSQRTE_D, args: instArgs{arg_fd, arg_fj}}, + // FRSQRTE.S fd, fj + {mask: 0xfffffc00, value: 0x01148400, op: FRSQRTE_S, args: instArgs{arg_fd, arg_fj}}, + // FRSQRT.D fd, fj + {mask: 0xfffffc00, value: 0x01146800, op: FRSQRT_D, args: instArgs{arg_fd, arg_fj}}, + // FRSQRT.S fd, fj + {mask: 0xfffffc00, value: 0x01146400, op: FRSQRT_S, args: instArgs{arg_fd, arg_fj}}, + // FSCALEB.D fd, fj, fk + {mask: 0xffff8000, value: 0x01110000, op: FSCALEB_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FSCALEB.S fd, fj, fk + {mask: 0xffff8000, value: 0x01108000, op: FSCALEB_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FSEL fd, fj, fk, ca + {mask: 0xfffc0000, value: 0x0d000000, op: FSEL, args: instArgs{arg_fd, arg_fj, arg_fk, arg_ca}}, + // FSQRT.D fd, fj + {mask: 0xfffffc00, value: 0x01144800, op: FSQRT_D, args: instArgs{arg_fd, arg_fj}}, + // FSQRT.S fd, fj + {mask: 0xfffffc00, value: 0x01144400, op: FSQRT_S, args: instArgs{arg_fd, arg_fj}}, + // FSTGT.D fd, rj, rk + {mask: 0xffff8000, value: 0x38768000, op: FSTGT_D, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FSTGT.S fd, rj, rk + {mask: 0xffff8000, value: 0x38760000, op: FSTGT_S, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FSTLE.D fd, rj, rk + {mask: 0xffff8000, value: 0x38778000, op: FSTLE_D, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FSTLE.S fd, rj, rk + {mask: 0xffff8000, value: 0x38770000, op: FSTLE_S, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FSTX.D fd, rj, rk + {mask: 0xffff8000, value: 0x383c0000, op: FSTX_D, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FSTX.S fd, rj, rk + {mask: 0xffff8000, value: 0x38380000, op: FSTX_S, args: instArgs{arg_fd, arg_rj, arg_rk}}, + // FST.D fd, rj, si12 + {mask: 0xffc00000, value: 0x2bc00000, op: FST_D, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}}, + // FST.S fd, rj, si12 + {mask: 0xffc00000, value: 0x2b400000, op: FST_S, args: instArgs{arg_fd, arg_rj, arg_si12_21_10}}, + // FSUB.D fd, fj, fk + {mask: 0xffff8000, value: 0x01030000, op: FSUB_D, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FSUB.S fd, fj, fk + {mask: 0xffff8000, value: 0x01028000, op: FSUB_S, args: instArgs{arg_fd, arg_fj, arg_fk}}, + // FTINTRM.L.D fd, fj + {mask: 0xfffffc00, value: 0x011a2800, op: FTINTRM_L_D, args: instArgs{arg_fd, arg_fj}}, + // FTINTRM.L.S fd, fj + {mask: 0xfffffc00, value: 0x011a2400, op: FTINTRM_L_S, args: instArgs{arg_fd, arg_fj}}, + // FTINTRM.W.D fd, fj + {mask: 0xfffffc00, value: 0x011a0800, op: FTINTRM_W_D, args: instArgs{arg_fd, arg_fj}}, + // FTINTRM.W.S fd, fj + {mask: 0xfffffc00, value: 0x011a0400, op: FTINTRM_W_S, args: instArgs{arg_fd, arg_fj}}, + // FTINTRNE.L.D fd, fj + {mask: 0xfffffc00, value: 0x011ae800, op: FTINTRNE_L_D, args: instArgs{arg_fd, arg_fj}}, + // FTINTRNE.L.S fd, fj + {mask: 0xfffffc00, value: 0x011ae400, op: FTINTRNE_L_S, args: instArgs{arg_fd, arg_fj}}, + // FTINTRNE.W.D fd, fj + {mask: 0xfffffc00, value: 0x011ac800, op: FTINTRNE_W_D, args: instArgs{arg_fd, arg_fj}}, + // FTINTRNE.W.S fd, fj + {mask: 0xfffffc00, value: 0x011ac400, op: FTINTRNE_W_S, args: instArgs{arg_fd, arg_fj}}, + // FTINTRP.L.D fd, fj + {mask: 0xfffffc00, value: 0x011a6800, op: FTINTRP_L_D, args: instArgs{arg_fd, arg_fj}}, + // FTINTRP.L.S fd, fj + {mask: 0xfffffc00, value: 0x011a6400, op: FTINTRP_L_S, args: instArgs{arg_fd, arg_fj}}, + // FTINTRP.W.D fd, fj + {mask: 0xfffffc00, value: 0x011a4800, op: FTINTRP_W_D, args: instArgs{arg_fd, arg_fj}}, + // FTINTRP.W.S fd, fj + {mask: 0xfffffc00, value: 0x011a4400, op: FTINTRP_W_S, args: instArgs{arg_fd, arg_fj}}, + // FTINTRZ.L.D fd, fj + {mask: 0xfffffc00, value: 0x011aa800, op: FTINTRZ_L_D, args: instArgs{arg_fd, arg_fj}}, + // FTINTRZ.L.S fd, fj + {mask: 0xfffffc00, value: 0x011aa400, op: FTINTRZ_L_S, args: instArgs{arg_fd, arg_fj}}, + // FTINTRZ.W.D fd, fj + {mask: 0xfffffc00, value: 0x011a8800, op: FTINTRZ_W_D, args: instArgs{arg_fd, arg_fj}}, + // FTINTRZ.W.S fd, fj + {mask: 0xfffffc00, value: 0x011a8400, op: FTINTRZ_W_S, args: instArgs{arg_fd, arg_fj}}, + // FTINT.L.D fd, fj + {mask: 0xfffffc00, value: 0x011b2800, op: FTINT_L_D, args: instArgs{arg_fd, arg_fj}}, + // FTINT.L.S fd, fj + {mask: 0xfffffc00, value: 0x011b2400, op: FTINT_L_S, args: instArgs{arg_fd, arg_fj}}, + // FTINT.W.D fd, fj + {mask: 0xfffffc00, value: 0x011b0800, op: FTINT_W_D, args: instArgs{arg_fd, arg_fj}}, + // FTINT.W.S fd, fj + {mask: 0xfffffc00, value: 0x011b0400, op: FTINT_W_S, args: instArgs{arg_fd, arg_fj}}, + // IBAR hint + {mask: 0xffff8000, value: 0x38728000, op: IBAR, args: instArgs{arg_hint_14_0}}, + // IDLE level + {mask: 0xffff8000, value: 0x06488000, op: IDLE, args: instArgs{arg_level_14_0}}, + // INVTLB op, rj, rk + {mask: 0xffff8000, value: 0x06498000, op: INVTLB, args: instArgs{arg_op_4_0, arg_rj, arg_rk}}, + // IOCSRRD.B rd, rj + {mask: 0xfffffc00, value: 0x06480000, op: IOCSRRD_B, args: instArgs{arg_rd, arg_rj}}, + // IOCSRRD.D rd, rj + {mask: 0xfffffc00, value: 0x06480c00, op: IOCSRRD_D, args: instArgs{arg_rd, arg_rj}}, + // IOCSRRD.H rd, rj + {mask: 0xfffffc00, value: 0x06480400, op: IOCSRRD_H, args: instArgs{arg_rd, arg_rj}}, + // IOCSRRD.W rd, rj + {mask: 0xfffffc00, value: 0x06480800, op: IOCSRRD_W, args: instArgs{arg_rd, arg_rj}}, + // IOCSRWR.B rd, rj + {mask: 0xfffffc00, value: 0x06481000, op: IOCSRWR_B, args: instArgs{arg_rd, arg_rj}}, + // IOCSRWR.D rd, rj + {mask: 0xfffffc00, value: 0x06481c00, op: IOCSRWR_D, args: instArgs{arg_rd, arg_rj}}, + // IOCSRWR.H rd, rj + {mask: 0xfffffc00, value: 0x06481400, op: IOCSRWR_H, args: instArgs{arg_rd, arg_rj}}, + // IOCSRWR.W rd, rj + {mask: 0xfffffc00, value: 0x06481800, op: IOCSRWR_W, args: instArgs{arg_rd, arg_rj}}, + // JIRL rd, rj, offs + {mask: 0xfc000000, value: 0x4c000000, op: JIRL, args: instArgs{arg_rd, arg_rj, arg_offset_15_0}}, + // LDDIR rd, rj, level + {mask: 0xfffc0000, value: 0x06400000, op: LDDIR, args: instArgs{arg_rd, arg_rj, arg_level_17_10}}, + // LDGT.B rd, rj, rk + {mask: 0xffff8000, value: 0x38780000, op: LDGT_B, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDGT.D rd, rj, rk + {mask: 0xffff8000, value: 0x38798000, op: LDGT_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDGT.H rd, rj, rk + {mask: 0xffff8000, value: 0x38788000, op: LDGT_H, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDGT.W rd, rj, rk + {mask: 0xffff8000, value: 0x38790000, op: LDGT_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDLE.B rd, rj, rk + {mask: 0xffff8000, value: 0x387a0000, op: LDLE_B, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDLE.D rd, rj, rk + {mask: 0xffff8000, value: 0x387b8000, op: LDLE_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDLE.H rd, rj, rk + {mask: 0xffff8000, value: 0x387a8000, op: LDLE_H, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDLE.W rd, rj, rk + {mask: 0xffff8000, value: 0x387b0000, op: LDLE_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDPTE rj, seq + {mask: 0xfffc001f, value: 0x06440000, op: LDPTE, args: instArgs{arg_rj, arg_seq_17_10}}, + // LDPTR.D rd, rj, si14 + {mask: 0xff000000, value: 0x26000000, op: LDPTR_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}}, + // LDPTR.W rd, rj, si14 + {mask: 0xff000000, value: 0x24000000, op: LDPTR_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}}, + // LDX.B rd, rj, rk + {mask: 0xffff8000, value: 0x38000000, op: LDX_B, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDX.BU rd, rj, rk + {mask: 0xffff8000, value: 0x38200000, op: LDX_BU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDX.D rd, rj, rk + {mask: 0xffff8000, value: 0x380c0000, op: LDX_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDX.H rd, rj, rk + {mask: 0xffff8000, value: 0x38040000, op: LDX_H, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDX.HU rd, rj, rk + {mask: 0xffff8000, value: 0x38240000, op: LDX_HU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDX.W rd, rj, rk + {mask: 0xffff8000, value: 0x38080000, op: LDX_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LDX.WU rd, rj, rk + {mask: 0xffff8000, value: 0x38280000, op: LDX_WU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // LD.B rd, rj, si12 + {mask: 0xffc00000, value: 0x28000000, op: LD_B, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // LD.BU rd, rj, si12 + {mask: 0xffc00000, value: 0x2a000000, op: LD_BU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // LD.D rd, rj, si12 + {mask: 0xffc00000, value: 0x28c00000, op: LD_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // LD.H rd, rj, si12 + {mask: 0xffc00000, value: 0x28400000, op: LD_H, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // LD.HU rd, rj, si12 + {mask: 0xffc00000, value: 0x2a400000, op: LD_HU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // LD.W rd, rj, si12 + {mask: 0xffc00000, value: 0x28800000, op: LD_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // LD.WU rd, rj, si12 + {mask: 0xffc00000, value: 0x2a800000, op: LD_WU, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // LLACQ.D rd, rj + {mask: 0xfffffc00, value: 0x38578800, op: LLACQ_D, args: instArgs{arg_rd, arg_rj}}, + // LLACQ.W rd, rj + {mask: 0xfffffc00, value: 0x38578000, op: LLACQ_W, args: instArgs{arg_rd, arg_rj}}, + // LL.D rd, rj, si14 + {mask: 0xff000000, value: 0x22000000, op: LL_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}}, + // LL.W rd, rj, si14 + {mask: 0xff000000, value: 0x20000000, op: LL_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}}, + // LU12I.W rd, si20 + {mask: 0xfe000000, value: 0x14000000, op: LU12I_W, args: instArgs{arg_rd, arg_si20_24_5}}, + // LU32I.D rd, si20 + {mask: 0xfe000000, value: 0x16000000, op: LU32I_D, args: instArgs{arg_rd, arg_si20_24_5}}, + // LU52I.D rd, rj, si12 + {mask: 0xffc00000, value: 0x03000000, op: LU52I_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // MASKEQZ rd, rj, rk + {mask: 0xffff8000, value: 0x00130000, op: MASKEQZ, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MASKNEZ rd, rj, rk + {mask: 0xffff8000, value: 0x00138000, op: MASKNEZ, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MOD.D rd, rj, rk + {mask: 0xffff8000, value: 0x00228000, op: MOD_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MOD.DU rd, rj, rk + {mask: 0xffff8000, value: 0x00238000, op: MOD_DU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MOD.W rd, rj, rk + {mask: 0xffff8000, value: 0x00208000, op: MOD_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MOD.WU rd, rj, rk + {mask: 0xffff8000, value: 0x00218000, op: MOD_WU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MOVCF2FR fd, cj + {mask: 0xffffff00, value: 0x0114d400, op: MOVCF2FR, args: instArgs{arg_fd, arg_cj}}, + // MOVCF2GR rd, cj + {mask: 0xffffff00, value: 0x0114dc00, op: MOVCF2GR, args: instArgs{arg_rd, arg_cj}}, + // MOVFCSR2GR rd, fcsr + {mask: 0xfffffc00, value: 0x0114c800, op: MOVFCSR2GR, args: instArgs{arg_rd, arg_fcsr_9_5}}, + // MOVFR2CF cd, fj + {mask: 0xfffffc18, value: 0x0114d000, op: MOVFR2CF, args: instArgs{arg_cd, arg_fj}}, + // MOVFR2GR.D rd, fj + {mask: 0xfffffc00, value: 0x0114b800, op: MOVFR2GR_D, args: instArgs{arg_rd, arg_fj}}, + // MOVFR2GR.S rd, fj + {mask: 0xfffffc00, value: 0x0114b400, op: MOVFR2GR_S, args: instArgs{arg_rd, arg_fj}}, + // MOVFRH2GR.S rd, fj + {mask: 0xfffffc00, value: 0x0114bc00, op: MOVFRH2GR_S, args: instArgs{arg_rd, arg_fj}}, + // MOVGR2CF cd, rj + {mask: 0xfffffc18, value: 0x0114d800, op: MOVGR2CF, args: instArgs{arg_cd, arg_rj}}, + // MOVGR2FCSR fcsr, rj + {mask: 0xfffffc00, value: 0x0114c000, op: MOVGR2FCSR, args: instArgs{arg_fcsr_4_0, arg_rj}}, + // MOVGR2FRH.W fd, rj + {mask: 0xfffffc00, value: 0x0114ac00, op: MOVGR2FRH_W, args: instArgs{arg_fd, arg_rj}}, + // MOVGR2FR.D fd, rj + {mask: 0xfffffc00, value: 0x0114a800, op: MOVGR2FR_D, args: instArgs{arg_fd, arg_rj}}, + // MOVGR2FR.W fd, rj + {mask: 0xfffffc00, value: 0x0114a400, op: MOVGR2FR_W, args: instArgs{arg_fd, arg_rj}}, + // MULH.D rd, rj, rk + {mask: 0xffff8000, value: 0x001e0000, op: MULH_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MULH.DU rd, rj, rk + {mask: 0xffff8000, value: 0x001e8000, op: MULH_DU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MULH.W rd, rj, rk + {mask: 0xffff8000, value: 0x001c8000, op: MULH_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MULH.WU rd, rj, rk + {mask: 0xffff8000, value: 0x001d0000, op: MULH_WU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MULW.D.W rd, rj, rk + {mask: 0xffff8000, value: 0x001f0000, op: MULW_D_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MULW.D.WU rd, rj, rk + {mask: 0xffff8000, value: 0x001f8000, op: MULW_D_WU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MUL.D rd, rj, rk + {mask: 0xffff8000, value: 0x001d8000, op: MUL_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // MUL.W rd, rj, rk + {mask: 0xffff8000, value: 0x001c0000, op: MUL_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // NOR rd, rj, rk + {mask: 0xffff8000, value: 0x00140000, op: NOR, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // OR rd, rj, rk + {mask: 0xffff8000, value: 0x00150000, op: OR, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // ORI rd, rj, ui12 + {mask: 0xffc00000, value: 0x03800000, op: ORI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}}, + // ORN rd, rj, rk + {mask: 0xffff8000, value: 0x00160000, op: ORN, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // PCADDI rd, si20 + {mask: 0xfe000000, value: 0x18000000, op: PCADDI, args: instArgs{arg_rd, arg_si20_24_5}}, + // PCADDU12I rd, si20 + {mask: 0xfe000000, value: 0x1c000000, op: PCADDU12I, args: instArgs{arg_rd, arg_si20_24_5}}, + // PCADDU18I rd, si20 + {mask: 0xfe000000, value: 0x1e000000, op: PCADDU18I, args: instArgs{arg_rd, arg_si20_24_5}}, + // PCALAU12I rd, si20 + {mask: 0xfe000000, value: 0x1a000000, op: PCALAU12I, args: instArgs{arg_rd, arg_si20_24_5}}, + // PRELD hint, rj, si12 + {mask: 0xffc00000, value: 0x2ac00000, op: PRELD, args: instArgs{arg_hint_4_0, arg_rj, arg_si12_21_10}}, + // PRELDX hint, rj, rk + {mask: 0xffff8000, value: 0x382c0000, op: PRELDX, args: instArgs{arg_hint_4_0, arg_rj, arg_rk}}, + // RDTIMEH.W rd, rj + {mask: 0xfffffc00, value: 0x00006400, op: RDTIMEH_W, args: instArgs{arg_rd, arg_rj}}, + // RDTIMEL.W rd, rj + {mask: 0xfffffc00, value: 0x00006000, op: RDTIMEL_W, args: instArgs{arg_rd, arg_rj}}, + // RDTIME.D rd, rj + {mask: 0xfffffc00, value: 0x00006800, op: RDTIME_D, args: instArgs{arg_rd, arg_rj}}, + // REVB.2H rd, rj + {mask: 0xfffffc00, value: 0x00003000, op: REVB_2H, args: instArgs{arg_rd, arg_rj}}, + // REVB.2W rd, rj + {mask: 0xfffffc00, value: 0x00003800, op: REVB_2W, args: instArgs{arg_rd, arg_rj}}, + // REVB.4H rd, rj + {mask: 0xfffffc00, value: 0x00003400, op: REVB_4H, args: instArgs{arg_rd, arg_rj}}, + // REVB.D rd, rj + {mask: 0xfffffc00, value: 0x00003c00, op: REVB_D, args: instArgs{arg_rd, arg_rj}}, + // REVH.2W rd, rj + {mask: 0xfffffc00, value: 0x00004000, op: REVH_2W, args: instArgs{arg_rd, arg_rj}}, + // REVH.D rd, rj + {mask: 0xfffffc00, value: 0x00004400, op: REVH_D, args: instArgs{arg_rd, arg_rj}}, + // ROTRI.D rd, rj, ui6 + {mask: 0xffff0000, value: 0x004d0000, op: ROTRI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}}, + // ROTRI.W rd, rj, ui5 + {mask: 0xffff8000, value: 0x004c8000, op: ROTRI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}}, + // ROTR.D rd, rj, rk + {mask: 0xffff8000, value: 0x001b8000, op: ROTR_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // ROTR.W rd, rj, rk + {mask: 0xffff8000, value: 0x001b0000, op: ROTR_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SCREL.D rd, rj + {mask: 0xfffffc00, value: 0x38578c00, op: SCREL_D, args: instArgs{arg_rd, arg_rj}}, + // SCREL.W rd, rj + {mask: 0xfffffc00, value: 0x38578400, op: SCREL_W, args: instArgs{arg_rd, arg_rj}}, + // SC.D rd, rj, si14 + {mask: 0xff000000, value: 0x23000000, op: SC_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}}, + // SC.Q rd, rk, rj + {mask: 0xffff8000, value: 0x38570000, op: SC_Q, args: instArgs{arg_rd, arg_rk, arg_rj}}, + // SC.W rd, rj, si14 + {mask: 0xff000000, value: 0x21000000, op: SC_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}}, + // SLLI.D rd, rj, ui6 + {mask: 0xffff0000, value: 0x00410000, op: SLLI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}}, + // SLLI.W rd, rj, ui5 + {mask: 0xffff8000, value: 0x00408000, op: SLLI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}}, + // SLL.D rd, rj, rk + {mask: 0xffff8000, value: 0x00188000, op: SLL_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SLL.W rd, rj, rk + {mask: 0xffff8000, value: 0x00170000, op: SLL_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SLT rd, rj, rk + {mask: 0xffff8000, value: 0x00120000, op: SLT, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SLTI rd, rj, si12 + {mask: 0xffc00000, value: 0x02000000, op: SLTI, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // SLTU rd, rj, rk + {mask: 0xffff8000, value: 0x00128000, op: SLTU, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SLTUI rd, rj, si12 + {mask: 0xffc00000, value: 0x02400000, op: SLTUI, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // SRAI.D rd, rj, ui6 + {mask: 0xffff0000, value: 0x00490000, op: SRAI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}}, + // SRAI.W rd, rj, ui5 + {mask: 0xffff8000, value: 0x00488000, op: SRAI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}}, + // SRA.D rd, rj, rk + {mask: 0xffff8000, value: 0x00198000, op: SRA_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SRA.W rd, rj, rk + {mask: 0xffff8000, value: 0x00180000, op: SRA_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SRLI.D rd, rj, ui6 + {mask: 0xffff0000, value: 0x00450000, op: SRLI_D, args: instArgs{arg_rd, arg_rj, arg_ui6_15_10}}, + // SRLI.W rd, rj, ui5 + {mask: 0xffff8000, value: 0x00448000, op: SRLI_W, args: instArgs{arg_rd, arg_rj, arg_ui5_14_10}}, + // SRL.D rd, rj, rk + {mask: 0xffff8000, value: 0x00190000, op: SRL_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SRL.W rd, rj, rk + {mask: 0xffff8000, value: 0x00178000, op: SRL_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STGT.B rd, rj, rk + {mask: 0xffff8000, value: 0x387c0000, op: STGT_B, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STGT.D rd, rj, rk + {mask: 0xffff8000, value: 0x387d8000, op: STGT_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STGT.H rd, rj, rk + {mask: 0xffff8000, value: 0x387c8000, op: STGT_H, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STGT.W rd, rj, rk + {mask: 0xffff8000, value: 0x387d0000, op: STGT_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STLE.B rd, rj, rk + {mask: 0xffff8000, value: 0x387e0000, op: STLE_B, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STLE.D rd, rj, rk + {mask: 0xffff8000, value: 0x387f8000, op: STLE_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STLE.H rd, rj, rk + {mask: 0xffff8000, value: 0x387e8000, op: STLE_H, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STLE.W rd, rj, rk + {mask: 0xffff8000, value: 0x387f0000, op: STLE_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STPTR.D rd, rj, si14 + {mask: 0xff000000, value: 0x27000000, op: STPTR_D, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}}, + // STPTR.W rd, rj, si14 + {mask: 0xff000000, value: 0x25000000, op: STPTR_W, args: instArgs{arg_rd, arg_rj, arg_si14_23_10}}, + // STX.B rd, rj, rk + {mask: 0xffff8000, value: 0x38100000, op: STX_B, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STX.D rd, rj, rk + {mask: 0xffff8000, value: 0x381c0000, op: STX_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STX.H rd, rj, rk + {mask: 0xffff8000, value: 0x38140000, op: STX_H, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // STX.W rd, rj, rk + {mask: 0xffff8000, value: 0x38180000, op: STX_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // ST.B rd, rj, si12 + {mask: 0xffc00000, value: 0x29000000, op: ST_B, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // ST.D rd, rj, si12 + {mask: 0xffc00000, value: 0x29c00000, op: ST_D, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // ST.H rd, rj, si12 + {mask: 0xffc00000, value: 0x29400000, op: ST_H, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // ST.W rd, rj, si12 + {mask: 0xffc00000, value: 0x29800000, op: ST_W, args: instArgs{arg_rd, arg_rj, arg_si12_21_10}}, + // SUB.D rd, rj, rk + {mask: 0xffff8000, value: 0x00118000, op: SUB_D, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SUB.W rd, rj, rk + {mask: 0xffff8000, value: 0x00110000, op: SUB_W, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // SYSCALL code + {mask: 0xffff8000, value: 0x002b0000, op: SYSCALL, args: instArgs{arg_code_14_0}}, + // TLBCLR + {mask: 0xffffffff, value: 0x06482000, op: TLBCLR, args: instArgs{}}, + // TLBFILL + {mask: 0xffffffff, value: 0x06483400, op: TLBFILL, args: instArgs{}}, + // TLBFLUSH + {mask: 0xffffffff, value: 0x06482400, op: TLBFLUSH, args: instArgs{}}, + // TLBRD + {mask: 0xffffffff, value: 0x06482c00, op: TLBRD, args: instArgs{}}, + // TLBSRCH + {mask: 0xffffffff, value: 0x06482800, op: TLBSRCH, args: instArgs{}}, + // TLBWR + {mask: 0xffffffff, value: 0x06483000, op: TLBWR, args: instArgs{}}, + // XOR rd, rj, rk + {mask: 0xffff8000, value: 0x00158000, op: XOR, args: instArgs{arg_rd, arg_rj, arg_rk}}, + // XORI rd, rj, ui12 + {mask: 0xffc00000, value: 0x03c00000, op: XORI, args: instArgs{arg_rd, arg_rj, arg_ui12_21_10}}, +} diff --git a/loong64/loong64asm/testdata/gnucases.txt b/loong64/loong64asm/testdata/gnucases.txt new file mode 100644 index 00000000..90ad9b7e --- /dev/null +++ b/loong64/loong64asm/testdata/gnucases.txt @@ -0,0 +1,417 @@ +ac391000| add.w $t0, $t1, $t2 +acb91000| add.d $t0, $t1, $t2 +ac41c002| addi.d $t0, $t1, 16 +ac01e002| addi.d $t0, $t1, -2048 +acfdff02| addi.d $t0, $t1, -1 +ac05e002| addi.d $t0, $t1, -2047 +acf9ff02| addi.d $t0, $t1, -2 +acfdff02| addi.d $t0, $t1, -1 +ac418002| addi.w $t0, $t1, 16 +ac410010| addu16i.d $t0, $t1, 16 +a4fcff13| addu16i.d $a0, $a1, -1 +acb92c00| alsl.d $t0, $t1, $t2, 0x2 +acb90400| alsl.w $t0, $t1, $t2, 0x2 +acb90600| alsl.wu $t0, $t1, $t2, 0x2 +ccb56138| amadd.d $t0, $t1, $t2 +cc356138| amadd.w $t0, $t1, $t2 +ccb56a38| amadd_db.d $t0, $t1, $t2 +cc356a38| amadd_db.w $t0, $t1, $t2 +ccb56238| amand.d $t0, $t1, $t2 +cc356238| amand.w $t0, $t1, $t2 +ccb56b38| amand_db.d $t0, $t1, $t2 +cc356b38| amand_db.w $t0, $t1, $t2 +ccb56538| ammax.d $t0, $t1, $t2 +ccb56738| ammax.du $t0, $t1, $t2 +cc356538| ammax.w $t0, $t1, $t2 +cc356738| ammax.wu $t0, $t1, $t2 +ccb56e38| ammax_db.d $t0, $t1, $t2 +ccb57038| ammax_db.du $t0, $t1, $t2 +cc356e38| ammax_db.w $t0, $t1, $t2 +cc357038| ammax_db.wu $t0, $t1, $t2 +ccb56638| ammin.d $t0, $t1, $t2 +ccb56838| ammin.du $t0, $t1, $t2 +cc356638| ammin.w $t0, $t1, $t2 +cc356838| ammin.wu $t0, $t1, $t2 +ccb56f38| ammin_db.d $t0, $t1, $t2 +ccb57138| ammin_db.du $t0, $t1, $t2 +cc356f38| ammin_db.w $t0, $t1, $t2 +cc357138| ammin_db.wu $t0, $t1, $t2 +ccb56338| amor.d $t0, $t1, $t2 +cc356338| amor.w $t0, $t1, $t2 +ccb56c38| amor_db.d $t0, $t1, $t2 +cc356c38| amor_db.w $t0, $t1, $t2 +ccb56038| amswap.d $t0, $t1, $t2 +cc356038| amswap.w $t0, $t1, $t2 +ccb56938| amswap_db.d $t0, $t1, $t2 +cc356938| amswap_db.w $t0, $t1, $t2 +ccb56438| amxor.d $t0, $t1, $t2 +cc356438| amxor.w $t0, $t1, $t2 +ccb56d38| amxor_db.d $t0, $t1, $t2 +cc356d38| amxor_db.w $t0, $t1, $t2 +acb91400| and $t0, $t1, $t2 +ac414003| andi $t0, $t1, 0x10 +acb91600| andn $t0, $t1, $t2 +00004003| nop +a0b90100| asrtgt.d $t1, $t2 +a0390100| asrtle.d $t1, $t2 +00100050| b 16 +20100048| bceqz $fcc1, 16 +20110048| bcnez $fcc1, 16 +1ff1ff4b| bcnez $fcc0, -16 +8d110058| beq $t0, $t1, 16 +a0110040| beqz $t1, 16 +9ff1ff43| beqz $t0, -16 +8d110064| bge $t0, $t1, 16 +8d11006c| bgeu $t0, $t1, 16 +ac490000| bitrev.4b $t0, $t1 +ac4d0000| bitrev.8b $t0, $t1 +ac550000| bitrev.d $t0, $t1 +ac510000| bitrev.w $t0, $t1 +00100054| bl 16 +8d110060| blt $t0, $t1, 16 +8d110068| bltu $t0, $t1, 16 +8d11005c| bne $t0, $t1, 16 +a0110044| bnez $t1, 16 +00002a00| break 0x0 +ac158a00| bstrins.d $t0, $t1, 0xa, 0x5 +ac156a00| bstrins.w $t0, $t1, 0xa, 0x5 +ac15ca00| bstrpick.d $t0, $t1, 0xa, 0x5 +ac956a00| bstrpick.w $t0, $t1, 0xa, 0x5 +ac390d00| bytepick.d $t0, $t1, $t2, 0x2 +ac390900| bytepick.w $t0, $t1, $t2, 0x2 +84010406| cacop 0x4, $t0, 256 +ac210000| clo.d $t0, $t1 +ac110000| clo.w $t0, $t1 +ac250000| clz.d $t0, $t1 +ac150000| clz.w $t0, $t1 +ac6d0000| cpucfg $t0, $t1 +ac392400| crc.w.b.w $t0, $t1, $t2 +acb92500| crc.w.d.w $t0, $t1, $t2 +acb92400| crc.w.h.w $t0, $t1, $t2 +ac392500| crc.w.w.w $t0, $t1, $t2 +ac392600| crcc.w.b.w $t0, $t1, $t2 +acb92700| crcc.w.d.w $t0, $t1, $t2 +acb92600| crcc.w.h.w $t0, $t1, $t2 +ac392700| crcc.w.w.w $t0, $t1, $t2 +0c040004| csrrd $t0, 0x1 +2c040004| csrwr $t0, 0x1 +ac050004| csrxchg $t0, $t1, 0x1 +ac290000| cto.d $t0, $t1 +ac190000| cto.w $t0, $t1 +ac2d0000| ctz.d $t0, $t1 +ac1d0000| ctz.w $t0, $t1 +00007238| dbar 0x0 +10802a00| dbcl 0x10 +ac392200| div.d $t0, $t1, $t2 +ac392300| div.du $t0, $t1, $t2 +ac392000| div.w $t0, $t1, $t2 +ac392100| div.wu $t0, $t1, $t2 +00384806| ertn +ac5d0000| ext.w.b $t0, $t1 +ac590000| ext.w.h $t0, $t1 +28091401| fabs.d $ft0, $ft1 +28051401| fabs.s $ft0, $ft1 +28250101| fadd.d $ft0, $ft1, $ft1 +28a50001| fadd.s $ft0, $ft1, $ft1 +28391401| fclass.d $ft0, $ft1 +28351401| fclass.s $ft0, $ft1 +2029200c| fcmp.caf.d $fcc0, $ft1, $ft2 +2029100c| fcmp.caf.s $fcc0, $ft1, $ft2 +2029220c| fcmp.ceq.d $fcc0, $ft1, $ft2 +2029120c| fcmp.ceq.s $fcc0, $ft1, $ft2 +2029230c| fcmp.cle.d $fcc0, $ft1, $ft2 +2029130c| fcmp.cle.s $fcc0, $ft1, $ft2 +2029210c| fcmp.clt.d $fcc0, $ft1, $ft2 +2029110c| fcmp.clt.s $fcc0, $ft1, $ft2 +2029280c| fcmp.cne.d $fcc0, $ft1, $ft2 +2029180c| fcmp.cne.s $fcc0, $ft1, $ft2 +20292a0c| fcmp.cor.d $fcc0, $ft1, $ft2 +20291a0c| fcmp.cor.s $fcc0, $ft1, $ft2 +2029260c| fcmp.cueq.d $fcc0, $ft1, $ft2 +2029160c| fcmp.cueq.s $fcc0, $ft1, $ft2 +2029270c| fcmp.cule.d $fcc0, $ft1, $ft2 +2029170c| fcmp.cule.s $fcc0, $ft1, $ft2 +2029250c| fcmp.cult.d $fcc0, $ft1, $ft2 +2029150c| fcmp.cult.s $fcc0, $ft1, $ft2 +20292c0c| fcmp.cune.d $fcc0, $ft1, $ft2 +20291c0c| fcmp.cune.s $fcc0, $ft1, $ft2 +2029240c| fcmp.cun.d $fcc0, $ft1, $ft2 +2029140c| fcmp.cun.s $fcc0, $ft1, $ft2 +20a9200c| fcmp.saf.d $fcc0, $ft1, $ft2 +20a9100c| fcmp.saf.s $fcc0, $ft1, $ft2 +20a9220c| fcmp.seq.d $fcc0, $ft1, $ft2 +20a9120c| fcmp.seq.s $fcc0, $ft1, $ft2 +20a9230c| fcmp.sle.d $fcc0, $ft1, $ft2 +20a9130c| fcmp.sle.s $fcc0, $ft1, $ft2 +20a9210c| fcmp.slt.d $fcc0, $ft1, $ft2 +20a9110c| fcmp.slt.s $fcc0, $ft1, $ft2 +20a9280c| fcmp.sne.d $fcc0, $ft1, $ft2 +20a9180c| fcmp.sne.s $fcc0, $ft1, $ft2 +20a92a0c| fcmp.sor.d $fcc0, $ft1, $ft2 +20a91a0c| fcmp.sor.s $fcc0, $ft1, $ft2 +20a9260c| fcmp.sueq.d $fcc0, $ft1, $ft2 +20a9160c| fcmp.sueq.s $fcc0, $ft1, $ft2 +20a9270c| fcmp.sule.d $fcc0, $ft1, $ft2 +20a9170c| fcmp.sule.s $fcc0, $ft1, $ft2 +20a9250c| fcmp.sult.d $fcc0, $ft1, $ft2 +20a9150c| fcmp.sult.s $fcc0, $ft1, $ft2 +20a92c0c| fcmp.sune.d $fcc0, $ft1, $ft2 +20a91c0c| fcmp.sune.s $fcc0, $ft1, $ft2 +20a9240c| fcmp.sun.d $fcc0, $ft1, $ft2 +20a9140c| fcmp.sun.s $fcc0, $ft1, $ft2 +28291301| fcopysign.d $ft0, $ft1, $ft2 +28a91201| fcopysign.s $ft0, $ft1, $ft2 +28251901| fcvt.d.s $ft0, $ft1 +28191901| fcvt.s.d $ft0, $ft1 +28290701| fdiv.d $ft0, $ft1, $ft2 +28a90601| fdiv.s $ft0, $ft1, $ft2 +28291d01| ffint.d.l $ft0, $ft1 +28211d01| ffint.d.w $ft0, $ft1 +28191d01| ffint.s.l $ft0, $ft1 +28111d01| ffint.s.w $ft0, $ft1 +a841802b| fld.d $ft0, $t1, 16 +a841002b| fld.s $ft0, $t1, 16 +a8b97438| fldgt.d $ft0, $t1, $t2 +a8397438| fldgt.s $ft0, $t1, $t2 +a8b97538| fldle.d $ft0, $t1, $t2 +a8397538| fldle.s $ft0, $t1, $t2 +a8393438| fldx.d $ft0, $t1, $t2 +a8393038| fldx.s $ft0, $t1, $t2 +28291401| flogb.d $ft0, $ft1 +28251401| flogb.s $ft0, $ft1 +28a92508| fmadd.d $ft0, $ft1, $ft2, $ft3 +28a91508| fmadd.s $ft0, $ft1, $ft2, $ft3 +28290901| fmax.d $ft0, $ft1, $ft2 +28a90801| fmax.s $ft0, $ft1, $ft2 +28290d01| fmaxa.d $ft0, $ft1, $ft2 +28a90c01| fmaxa.s $ft0, $ft1, $ft2 +28290b01| fmin.d $ft0, $ft1, $ft2 +28a90a01| fmin.s $ft0, $ft1, $ft2 +28290f01| fmina.d $ft0, $ft1, $ft2 +28a90e01| fmina.s $ft0, $ft1, $ft2 +48991401| fmov.d $ft0, $ft2 +48951401| fmov.s $ft0, $ft2 +28a96508| fmsub.d $ft0, $ft1, $ft2, $ft3 +28a95508| fmsub.s $ft0, $ft1, $ft2, $ft3 +28290501| fmul.d $ft0, $ft1, $ft2 +28a90401| fmul.s $ft0, $ft1, $ft2 +28191401| fneg.d $ft0, $ft1 +28151401| fneg.s $ft0, $ft1 +28a9a508| fnmadd.d $ft0, $ft1, $ft2, $ft3 +28a99508| fnmadd.s $ft0, $ft1, $ft2, $ft3 +28a9e508| fnmsub.d $ft0, $ft1, $ft2, $ft3 +28a9d508| fnmsub.s $ft0, $ft1, $ft2, $ft3 +28591401| frecip.d $ft0, $ft1 +28551401| frecip.s $ft0, $ft1 +28491e01| frint.d $ft0, $ft1 +28451e01| frint.s $ft0, $ft1 +28691401| frsqrt.d $ft0, $ft1 +28651401| frsqrt.s $ft0, $ft1 +28291101| fscaleb.d $ft0, $ft1, $ft2 +28a91001| fscaleb.s $ft0, $ft1, $ft2 +28a9000d| fsel $ft0, $ft1, $ft2, $fcc1 +28491401| fsqrt.d $ft0, $ft1 +28451401| fsqrt.s $ft0, $ft1 +a841c02b| fst.d $ft0, $t1, 16 +a841402b| fst.s $ft0, $t1, 16 +a8b97638| fstgt.d $ft0, $t1, $t2 +a8397638| fstgt.s $ft0, $t1, $t2 +a8b97738| fstle.d $ft0, $t1, $t2 +a8397738| fstle.s $ft0, $t1, $t2 +a8393c38| fstx.d $ft0, $t1, $t2 +a8393838| fstx.s $ft0, $t1, $t2 +28290301| fsub.d $ft0, $ft1, $ft2 +28a90201| fsub.s $ft0, $ft1, $ft2 +28291b01| ftint.l.d $ft0, $ft1 +28251b01| ftint.l.s $ft0, $ft1 +28091b01| ftint.w.d $ft0, $ft1 +28051b01| ftint.w.s $ft0, $ft1 +28291a01| ftintrm.l.d $ft0, $ft1 +28251a01| ftintrm.l.s $ft0, $ft1 +28091a01| ftintrm.w.d $ft0, $ft1 +28051a01| ftintrm.w.s $ft0, $ft1 +28e91a01| ftintrne.l.d $ft0, $ft1 +28e51a01| ftintrne.l.s $ft0, $ft1 +28c91a01| ftintrne.w.d $ft0, $ft1 +28c51a01| ftintrne.w.s $ft0, $ft1 +28691a01| ftintrp.l.d $ft0, $ft1 +28651a01| ftintrp.l.s $ft0, $ft1 +28491a01| ftintrp.w.d $ft0, $ft1 +28451a01| ftintrp.w.s $ft0, $ft1 +28a91a01| ftintrz.l.d $ft0, $ft1 +28a51a01| ftintrz.l.s $ft0, $ft1 +28891a01| ftintrz.w.d $ft0, $ft1 +28851a01| ftintrz.w.s $ft0, $ft1 +00807238| ibar 0x0 +10804806| idle 0x10 +ac014806| iocsrrd.b $t0, $t1 +ac054806| iocsrrd.h $t0, $t1 +ac094806| iocsrrd.w $t0, $t1 +ac0d4806| iocsrrd.d $t0, $t1 +ac114806| iocsrwr.b $t0, $t1 +ac154806| iocsrwr.h $t0, $t1 +ac194806| iocsrwr.w $t0, $t1 +ac1d4806| iocsrwr.d $t0, $t1 +82b54906| invtlb 0x2, $t0, $t1 +2000004c| ret +2008004c| jirl $zero, $ra, 8 +ac11004c| jirl $t0, $t1, 16 +ac410028| ld.b $t0, $t1, 16 +ac41002a| ld.bu $t0, $t1, 16 +ac41c028| ld.d $t0, $t1, 16 +ac414028| ld.h $t0, $t1, 16 +ac41402a| ld.hu $t0, $t1, 16 +ac418028| ld.w $t0, $t1, 16 +ac41802a| ld.wu $t0, $t1, 16 +ac414006| lddir $t0, $t1, 0x10 +ac397838| ldgt.b $t0, $t1, $t2 +acb97938| ldgt.d $t0, $t1, $t2 +acb97838| ldgt.h $t0, $t1, $t2 +ac397938| ldgt.w $t0, $t1, $t2 +ac397a38| ldle.b $t0, $t1, $t2 +acb97b38| ldle.d $t0, $t1, $t2 +acb97a38| ldle.h $t0, $t1, $t2 +ac397b38| ldle.w $t0, $t1, $t2 +ac110026| ldptr.d $t0, $t1, 16 +ac01e024| ldptr.w $t0, $t1, -8192 +ac05f024| ldptr.w $t0, $t1, -4092 +acfd1f24| ldptr.w $t0, $t1, 8188 +acfdff24| ldptr.w $t0, $t1, -4 +ac050024| ldptr.w $t0, $t1, 4 +ac110024| ldptr.w $t0, $t1, 16 +80094406| ldpte $t0, 0x2 +ac390038| ldx.b $t0, $t1, $t2 +ac392038| ldx.bu $t0, $t1, $t2 +ac390c38| ldx.d $t0, $t1, $t2 +ac390438| ldx.h $t0, $t1, $t2 +ac392438| ldx.hu $t0, $t1, $t2 +ac390838| ldx.w $t0, $t1, $t2 +ac392838| ldx.wu $t0, $t1, $t2 +ac110022| ll.d $t0, $t1, 16 +ac110020| ll.w $t0, $t1, 16 +0c020014| lu12i.w $t0, 16 +0c000015| lu12i.w $t0, -524288 +ecffff15| lu12i.w $t0, -1 +ecffff14| lu12i.w $t0, 524287 +0c020016| lu32i.d $t0, 16 +ac410003| lu52i.d $t0, $t1, 16 +ac391300| maskeqz $t0, $t1, $t2 +acb91300| masknez $t0, $t1, $t2 +acb92200| mod.d $t0, $t1, $t2 +acb92300| mod.du $t0, $t1, $t2 +acb92000| mod.w $t0, $t1, $t2 +acb92100| mod.wu $t0, $t1, $t2 +28d41401| movcf2fr $ft0, $fcc1 +2cdc1401| movcf2gr $t0, $fcc1 +0cc81401| movfcsr2gr $t0, $fcsr0 +20d11401| movfr2cf $fcc0, $ft1 +2cb91401| movfr2gr.d $t0, $ft1 +2cb51401| movfr2gr.s $t0, $ft1 +2cbd1401| movfrh2gr.s $t0, $ft1 +a0d91401| movgr2cf $fcc0, $t1 +80c11401| movgr2fcsr $fcsr0, $t0 +a8a91401| movgr2fr.d $ft0, $t1 +a8a51401| movgr2fr.w $ft0, $t1 +a8ad1401| movgr2frh.w $ft0, $t1 +acb91d00| mul.d $t0, $t1, $t2 +ac391c00| mul.w $t0, $t1, $t2 +ac391e00| mulh.d $t0, $t1, $t2 +acb91e00| mulh.du $t0, $t1, $t2 +acb91c00| mulh.w $t0, $t1, $t2 +ac391d00| mulh.wu $t0, $t1, $t2 +ac391f00| mulw.d.w $t0, $t1, $t2 +acb91f00| mulw.d.wu $t0, $t1, $t2 +ac391400| nor $t0, $t1, $t2 +ac391500| or $t0, $t1, $t2 +ac418003| ori $t0, $t1, 0x10 +ac391600| orn $t0, $t1, $t2 +0c020018| pcaddi $t0, 16 +0c02001c| pcaddu12i $t0, 16 +0c02001e| pcaddu18i $t0, 16 +0c02001a| pcalau12i $t0, 16 +a041c02a| preld 0x0, $t1, 16 +a0392c38| preldx 0x0, $t1, $t2 +ac690000| rdtime.d $t0, $t1 +ac650000| rdtimeh.w $t0, $t1 +ac610000| rdtimel.w $t0, $t1 +ac310000| revb.2h $t0, $t1 +ac390000| revb.2w $t0, $t1 +ac350000| revb.4h $t0, $t1 +ac3d0000| revb.d $t0, $t1 +ac410000| revh.2w $t0, $t1 +ac450000| revh.d $t0, $t1 +acb91b00| rotr.d $t0, $t1, $t2 +ac391b00| rotr.w $t0, $t1, $t2 +ac414d00| rotri.d $t0, $t1, 0x10 +acc14c00| rotri.w $t0, $t1, 0x10 +ac110023| sc.d $t0, $t1, 16 +ac110021| sc.w $t0, $t1, 16 +acb91800| sll.d $t0, $t1, $t2 +ac391700| sll.w $t0, $t1, $t2 +ac414100| slli.d $t0, $t1, 0x10 +acc14000| slli.w $t0, $t1, 0x10 +ac391200| slt $t0, $t1, $t2 +ac410002| slti $t0, $t1, 16 +acb91200| sltu $t0, $t1, $t2 +ac414002| sltui $t0, $t1, 16 +acb91900| sra.d $t0, $t1, $t2 +ac391800| sra.w $t0, $t1, $t2 +ac414900| srai.d $t0, $t1, 0x10 +acc14800| srai.w $t0, $t1, 0x10 +ac391900| srl.d $t0, $t1, $t2 +acb91700| srl.w $t0, $t1, $t2 +ac414500| srli.d $t0, $t1, 0x10 +acc14400| srli.w $t0, $t1, 0x10 +ac410029| st.b $t0, $t1, 16 +ac41c029| st.d $t0, $t1, 16 +ac414029| st.h $t0, $t1, 16 +ac418029| st.w $t0, $t1, 16 +ac397c38| stgt.b $t0, $t1, $t2 +acb97d38| stgt.d $t0, $t1, $t2 +acb97c38| stgt.h $t0, $t1, $t2 +ac397d38| stgt.w $t0, $t1, $t2 +ac397e38| stle.b $t0, $t1, $t2 +acb97f38| stle.d $t0, $t1, $t2 +acb97e38| stle.h $t0, $t1, $t2 +ac397f38| stle.w $t0, $t1, $t2 +ac110027| stptr.d $t0, $t1, 16 +ac110025| stptr.w $t0, $t1, 16 +ac391038| stx.b $t0, $t1, $t2 +ac391c38| stx.d $t0, $t1, $t2 +ac391438| stx.h $t0, $t1, $t2 +ac391838| stx.w $t0, $t1, $t2 +acb91100| sub.d $t0, $t1, $t2 +ac391100| sub.w $t0, $t1, $t2 +00002b00| syscall 0x0 +00204806| tlbclr +00344806| tlbfill +00244806| tlbflush +002c4806| tlbrd +00284806| tlbsrch +00304806| tlbwr +acb91500| xor $t0, $t1, $t2 +ac41c003| xori $t0, $t1, 0x10 +cc355d38| amadd.b $t0, $t1, $t2 +cc355f38| amadd_db.b $t0, $t1, $t2 +ccb55f38| amadd_db.h $t0, $t1, $t2 +ccb55d38| amadd.h $t0, $t1, $t2 +cc355838| amcas.b $t0, $t1, $t2 +ccb55938| amcas.d $t0, $t1, $t2 +cc355a38| amcas_db.b $t0, $t1, $t2 +ccb55b38| amcas_db.d $t0, $t1, $t2 +ccb55a38| amcas_db.h $t0, $t1, $t2 +cc355b38| amcas_db.w $t0, $t1, $t2 +ccb55838| amcas.h $t0, $t1, $t2 +cc355938| amcas.w $t0, $t1, $t2 +cc355c38| amswap.b $t0, $t1, $t2 +cc355e38| amswap_db.b $t0, $t1, $t2 +ccb55e38| amswap_db.h $t0, $t1, $t2 +ccb55c38| amswap.h $t0, $t1, $t2 +28791401| frecipe.d $ft0, $ft1 +28751401| frecipe.s $ft0, $ft1 +28891401| frsqrte.d $ft0, $ft1 +28851401| frsqrte.s $ft0, $ft1 +ac895738| llacq.d $t0, $t1 +ac815738| llacq.w $t0, $t1 +ac8d5738| screl.d $t0, $t1 +ac855738| screl.w $t0, $t1 diff --git a/loong64/loong64asm/testdata/plan9cases.txt b/loong64/loong64asm/testdata/plan9cases.txt new file mode 100644 index 00000000..c6a5bd57 --- /dev/null +++ b/loong64/loong64asm/testdata/plan9cases.txt @@ -0,0 +1,367 @@ +a6101000| ADD R4, R5, R6 +a6901000| ADDV R4, R5, R6 +a5101000| ADD R4, R5 +a5901000| ADDV R4, R5 +85fcbf02| ADD $-1, R4, R5 +84fcbf02| ADD $-1, R4 +85fcff02| ADDV $-1, R4, R5 +84fcff02| ADDV $-1, R4 +ac391000| ADD R14, R13, R12 +acb91000| ADDV R14, R13, R12 +ac41c002| ADDV $16, R13, R12 +ac01e002| ADDV $-2048, R13, R12 +acfdff02| ADDV $-1, R13, R12 +ac05e002| ADDV $-2047, R13, R12 +acf9ff02| ADDV $-2, R13, R12 +ac418002| ADD $16, R13, R12 +a6101100| SUB R4, R5, R6 +a6901100| SUBV R4, R5, R6 +a5101100| SUB R4, R5 +a5901100| SUBV R4, R5 +05101100| NEGW R4, R5 +05901100| NEGV R4, R5 +84781200| SGT R30, R4 +85781200| SGT R30, R4, R5 +84f81200| SGTU R30, R4 +85f81200| SGTU R30, R4, R5 +a6901400| AND R4, R5, R6 +a5901400| AND R4, R5 +85044003| AND $1, R4, R5 +84044003| AND $1, R4 +a5101c00| MUL R4, R5 +a6101c00| MUL R4, R5, R6 +a5901d00| MULV R4, R5 +a6901d00| MULV R4, R5, R6 +a5101e00| MULHV R4, R5 +a6101e00| MULHV R4, R5, R6 +a5901e00| MULHVU R4, R5 +a6901e00| MULHVU R4, R5, R6 +28290501| MULD F10, F9, F8 +28a90401| MULF F10, F9, F8 +a5102000| DIV R4, R5 +a6102000| DIV R4, R5, R6 +a5102100| DIVU R4, R5 +a6102100| DIVU R4, R5, R6 +a5102200| DIVV R4, R5 +a6102200| DIVV R4, R5, R6 +a5102300| DIVVU R4, R5 +a6102300| DIVVU R4, R5, R6 +28290701| DIVD F10, F9, F8 +28a90601| DIVF F10, F9, F8 +a5902000| REM R4, R5 +a6902000| REM R4, R5, R6 +a5902100| REMU R4, R5 +a6902100| REMU R4, R5, R6 +a5902200| REMV R4, R5 +a6902200| REMV R4, R5, R6 +a5902300| REMVU R4, R5 +a6902300| REMVU R4, R5, R6 +04020014| LU12IW $16, R4 +24000014| LU12IW $1, R4 +85001700| MOVW R4, R5 +85001500| MOVV R4, R5 +85fc4303| MOVBU R4, R5 +1e020014| LU12IW $16, R30 +85781000| ADD R30, R4, R5 +de038003| OR $0, R30 +ac391400| NOR R14, R13, R12 +acb91500| XOR R14, R13, R12 +ac41c003| XOR $16, R13, R12 +85f81000| ADDV R30, R4, R5 +8500cf00| MOVHU R4, R5 +a5101700| SLL R4, R5 +a6101700| SLL R4, R5, R6 +a5901700| SRL R4, R5 +a6901700| SRL R4, R5, R6 +a5101800| SRA R4, R5 +a6101800| SRA R4, R5, R6 +a5101b00| ROTR R4, R5 +a6101b00| ROTR R4, R5, R6 +a5901800| SLLV R4, R5 +a6901800| SLLV R4, R5, R6 +a5901b00| ROTRV R4, R5 +a6901b00| ROTRV R4, R5, R6 +85904000| SLL $4, R4, R5 +84904000| SLL $4, R4 +85904400| SRL $4, R4, R5 +84904400| SRL $4, R4 +85904800| SRA $4, R4, R5 +84904800| SRA $4, R4 +85904c00| ROTR $4, R4, R5 +84904c00| ROTR $4, R4 +85104100| SLLV $4, R4, R5 +84104100| SLLV $4, R4 +85104d00| ROTRV $4, R4, R5 +84104d00| ROTRV $4, R4 +a6101300| MASKEQZ R4, R5, R6 +a6901300| MASKNEZ R4, R5, R6 +00050048| BFPT 1(PC) +00040048| BFPF 1(PC) +80040058| BEQ R4, 1(PC) +8d110058| BEQ R12, R13, 4(PC) +a0110040| BEQ R13, 4(PC) +9ff1ff43| BEQ R12, -4(PC) +8504005c| BNE R4, R5, 1(PC) +8004005c| BNE R4, 1(PC) +8004005c| BNE R4, 1(PC) +a0140058| BEQ R5, 5(PC) +a0110058| BEQ R13, 4(PC) +00ebff5f| BNE R24, -6(PC) +801d005c| BNE R12, 7(PC) +85040060| BLT R4, R5, 1(PC) +80fcff63| BLTZ R4, -1(PC) +05040060| BGTZ R5, 1(PC) +80040060| BLTZ R4, 1(PC) +47d5ff6b| BLTU R10, R7, -11(PC) +802c0068| BLTU R4, 11(PC) +85040064| BGE R4, R5, 1(PC) +80fcff67| BGEZ R4, -1(PC) +47d5ff6f| BGEU R10, R7, -11(PC) +802c006c| BGEU R4, 11(PC) +04d8ff67| BLEZ R4, -10(PC) +2000004c| RET +2008004c| JMP 8(R1) +00040058| JMP 1(PC) +8000004c| JMP (R4) +00340050| JMP 13(PC) +00100050| JMP 4(PC) +00100054| CALL 4(PC) +8100004c| CALL (R4) +00140054| CALL 5(PC) +a4048029| MOVW R4, 1(R5) +a404c029| MOVV R4, 1(R5) +a4040029| MOVB R4, 1(R5) +ac410029| MOVB R12, 16(R13) +a4040021| SC R4, 1(R5) +a4040023| SCV R4, 1(R5) +a4040028| MOVB 1(R5), R4 +a404002a| MOVBU 1(R5), R4 +a4044028| MOVH 1(R5), R4 +a404402a| MOVHU 1(R5), R4 +a4048028| MOVW 1(R5), R4 +a404802a| MOVWU 1(R5), R4 +a404c028| MOVV 1(R5), R4 +a4040020| LL 1(R5), R4 +a4040022| LLV 1(R5), R4 +a4fc3f20| LL -1(R5), R4 +a4fc3f22| LLV -1(R5), R4 +00002a00| BREAK +00007238| DBAR +00002b00| SYSCALL +00004003| NOOP +a5900001| ADDF F4, F5 +a6900001| ADDF F4, F5, F6 +28a50001| ADDF F9, F9, F8 +28250101| ADDD F9, F9, F8 +85041401| ABSF F4, F5 +85081401| ABSD F4, F5 +85141401| NEGF F4, F5 +85181401| NEGD F4, F5 +85441401| SQRTF F4, F5 +85481401| SQRTD F4, F5 +a090110c| CMPGTF F4, F5, FCC0 +a090210c| CMPGTD F4, F5, FCC0 +a090130c| CMPGEF F4, F5, FCC0 +a090230c| CMPGED F4, F5, FCC0 +a010220c| CMPEQD F4, F5, FCC0 +2029120c| CMPEQF F10, F9, FCC0 +85241901| MOVFD F4, F5 +85181901| MOVDF F4, F5 +85101d01| FFINTFW F4, F5 +85201d01| FFINTDW F4, F5 +85181d01| FFINTFV F4, F5 +85281d01| FFINTDV F4, F5 +85041b01| FTINTWF F4, F5 +85241b01| FTINTVF F4, F5 +85081b01| FTINTWD F4, F5 +85281b01| FTINTVD F4, F5 +85881a01| FTINTRZWD F4, F5 +85841a01| FTINTRZWF F4, F5 +85a81a01| FTINTRZVD F4, F5 +85a41a01| FTINTRZVF F4, F5 +85941401| MOVF F4, F5 +85981401| MOVD F4, F5 +85a41401| MOVW R4, F5 +85b41401| MOVW F4, R5 +85a81401| MOVV R4, F5 +85b81401| MOVV F4, R5 +04dc1401| MOVV FCC0, R4 +80d81401| MOVV R4, FCC0 +6440002b| MOVF 16(R3), F4 +6440802b| MOVD 16(R3), F4 +a404002b| MOVF 1(R5), F4 +a404802b| MOVD 1(R5), F4 +6460402b| MOVF F4, 24(R3) +6460c02b| MOVD F4, 24(R3) +a404402b| MOVF F4, 1(R5) +a404c02b| MOVD F4, 1(R5) +5e020014| LU12IW $18, R30 +64a95214| LU12IW $169291, R4 +84d08703| OR $500, R4 +84428614| LU12IW $274964, R4 +84848c03| OR $801, R4 +24640816| LU32ID $17185, R4 +84000003| LU52ID $0, R4 +24a93615| LU12IW $-412343, R4 +84849003| OR $1057, R4 +8464c817| LU32ID $-113884, R4 +848c0203| LU52ID $163, R4 +80600000| RDTIMELW R4, R0 +80640000| RDTIMEHW R4, R0 +85680000| RDTIMED R4, R5 +1e00001a| PCALAU12I $0, R30 +0c02001c| PCADDU12I $16, R12 +c4038029| MOVW R4, 0(R30) +ac395c38| AMSWAPB R14, (R13), R12 +acb95c38| AMSWAPH R14, (R13), R12 +ac396038| AMSWAPW R14, (R13), R12 +acb96038| AMSWAPV R14, (R13), R12 +ac395838| AMCASB R14, (R13), R12 +acb95838| AMCASH R14, (R13), R12 +ac395938| AMCASW R14, (R13), R12 +acb95938| AMCASV R14, (R13), R12 +ac396138| AMADDW R14, (R13), R12 +acb96138| AMADDV R14, (R13), R12 +ac396238| AMANDW R14, (R13), R12 +acb96238| AMANDV R14, (R13), R12 +ac396338| AMORW R14, (R13), R12 +acb96338| AMORV R14, (R13), R12 +ac396438| AMXORW R14, (R13), R12 +acb96438| AMXORV R14, (R13), R12 +ac396538| AMMAXW R14, (R13), R12 +acb96538| AMMAXV R14, (R13), R12 +ac396638| AMMINW R14, (R13), R12 +acb96638| AMMINV R14, (R13), R12 +ac396738| AMMAXWU R14, (R13), R12 +acb96738| AMMAXVU R14, (R13), R12 +ac396838| AMMINWU R14, (R13), R12 +acb96838| AMMINVU R14, (R13), R12 +ac395e38| AMSWAPDBB R14, (R13), R12 +acb95e38| AMSWAPDBH R14, (R13), R12 +ac396938| AMSWAPDBW R14, (R13), R12 +acb96938| AMSWAPDBV R14, (R13), R12 +ac395a38| AMCASDBB R14, (R13), R12 +acb95a38| AMCASDBH R14, (R13), R12 +ac395b38| AMCASDBW R14, (R13), R12 +acb95b38| AMCASDBV R14, (R13), R12 +ac396a38| AMADDDBW R14, (R13), R12 +acb96a38| AMADDDBV R14, (R13), R12 +ac396b38| AMANDDBW R14, (R13), R12 +acb96b38| AMANDDBV R14, (R13), R12 +ac396c38| AMORDBW R14, (R13), R12 +acb96c38| AMORDBV R14, (R13), R12 +ac396d38| AMXORDBW R14, (R13), R12 +acb96d38| AMXORDBV R14, (R13), R12 +ac396e38| AMMAXDBW R14, (R13), R12 +acb96e38| AMMAXDBV R14, (R13), R12 +ac396f38| AMMINDBW R14, (R13), R12 +acb96f38| AMMINDBV R14, (R13), R12 +ac397038| AMMAXDBWU R14, (R13), R12 +acb97038| AMMAXDBVU R14, (R13), R12 +ac397138| AMMINDBWU R14, (R13), R12 +acb97138| AMMINDBVU R14, (R13), R12 +856c0000| CPUCFG R4, R5 +85481e01| FRINTD F4, F5 +83c01401| MOVV R4, FCSR3 +64c81401| MOVV FCSR3, R4 +80d01401| MOVV F4, FCC0 +04d41401| MOVV FCC0, F4 +a6901201| FCOPYSGF F4, F5, F6 +a6101301| FCOPYSGD F4, F5, F6 +85500000| BITREVW R4, R5 +85540000| BITREVV R4, R5 +a6102400| CRCWBW R4, R5, R6 +a6902400| CRCWHW R4, R5, R6 +a6102500| CRCWWW R4, R5, R6 +a6902500| CRCWVW R4, R5, R6 +a6102600| CRCCWBW R4, R5, R6 +a6902600| CRCCWHW R4, R5, R6 +a6102700| CRCCWWW R4, R5, R6 +a6902700| CRCCWVW R4, R5, R6 +cc350038| MOVB (R14)(R13), R12 +cc352038| MOVBU (R14)(R13), R12 +cc350438| MOVH (R14)(R13), R12 +cc352438| MOVHU (R14)(R13), R12 +cc350838| MOVW (R14)(R13), R12 +cc352838| MOVWU (R14)(R13), R12 +cc350c38| MOVV (R14)(R13), R12 +cc351038| MOVB R12, (R14)(R13) +cc351438| MOVH R12, (R14)(R13) +cc351838| MOVW R12, (R14)(R13) +cc351c38| MOVV R12, (R14)(R13) +c2353038| MOVF (R14)(R13), F2 +c2353438| MOVD (R14)(R13), F2 +c2353838| MOVF F2, (R14)(R13) +c2353c38| MOVD F2, (R14)(R13) +a010120c| CMPEQF F4, F5, FCC0 +a190110c| CMPGTF F4, F5, FCC1 +a290210c| CMPGTD F4, F5, FCC2 +a390130c| CMPGEF F4, F5, FCC3 +a490230c| CMPGED F4, F5, FCC4 +a510220c| CMPEQD F4, F5, FCC5 +85100000| CLOW R4, R5 +85200000| CLOV R4, R5 +85140000| CLZW R4, R5 +85240000| CLZV R4, R5 +85180000| CTOW R4, R5 +85280000| CTOV R4, R5 +851c0000| CTZW R4, R5 +852c0000| CTZV R4, R5 +853c0000| REVBV R4, R5 +85380000| REVB2W R4, R5 +85340000| REVB4H R4, R5 +85300000| REVB2H R4, R5 +a6900a01| FMINF F4, F5, F6 +a5900a01| FMINF F4, F5 +a6100b01| FMIND F4, F5, F6 +a5100b01| FMIND F4, F5 +a6900801| FMAXF F4, F5, F6 +a5900801| FMAXF F4, F5 +a6100901| FMAXD F4, F5, F6 +a5100901| FMAXD F4, F5 +85341401| FCLASSF F4, F5 +85381401| FCLASSD F4, F5 +02041a01| FTINTRMWF F0, F2 +02081a01| FTINTRMWD F0, F2 +02241a01| FTINTRMVF F0, F2 +02281a01| FTINTRMVD F0, F2 +02441a01| FTINTRPWF F0, F2 +02481a01| FTINTRPWD F0, F2 +02641a01| FTINTRPVF F0, F2 +02681a01| FTINTRPVD F0, F2 +02841a01| FTINTRZWF F0, F2 +02881a01| FTINTRZWD F0, F2 +02a41a01| FTINTRZVF F0, F2 +02a81a01| FTINTRZVD F0, F2 +02c41a01| FTINTRNEWF F0, F2 +02c81a01| FTINTRNEWD F0, F2 +02e41a01| FTINTRNEVF F0, F2 +02e81a01| FTINTRNEVD F0, F2 +01101d01| FFINTFW F0, F1 +01181d01| FFINTFV F0, F1 +01201d01| FFINTDW F0, F1 +01281d01| FFINTDV F0, F1 +01041b01| FTINTWF F0, F1 +01081b01| FTINTWD F0, F1 +01241b01| FTINTVF F0, F1 +01281b01| FTINTVD F0, F1 +c7901208| FMADDF F5, F4, F6, F7 +c7902208| FMADDD F5, F4, F6, F7 +c7905208| FMSUBF F5, F4, F6, F7 +c7906208| FMSUBD F5, F4, F6, F7 +c7909208| FNMADDF F5, F4, F6, F7 +c790a208| FNMADDD F5, F4, F6, F7 +c790d208| FNMSUBF F5, F4, F6, F7 +c790e208| FNMSUBD F5, F4, F6, F7 +85806000| BSTRPICKW $0, R4, $0, R5 +85807f00| BSTRPICKW $31, R4, $0, R5 +85986f00| BSTRPICKW $15, R4, $6, R5 +8500c000| BSTRPICKV $0, R4, $0, R5 +8500ff00| BSTRPICKV $63, R4, $0, R5 +8518cf00| BSTRPICKV $15, R4, $6, R5 +85006000| BSTRINSW $0, R4, $0, R5 +85007f00| BSTRINSW $31, R4, $0, R5 +85186f00| BSTRINSW $15, R4, $6, R5 +85008000| BSTRINSV $0, R4, $0, R5 +8500bf00| BSTRINSV $63, R4, $0, R5 +85188f00| BSTRINSV $15, R4, $6, R5 diff --git a/loong64/loong64spec/spec.go b/loong64/loong64spec/spec.go new file mode 100644 index 00000000..177df41b --- /dev/null +++ b/loong64/loong64spec/spec.go @@ -0,0 +1,535 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// loong64spec reads the "LoongArch-Vol1-EN.pdf" [1] to collect instruction +// encoding details and output to tables.go. +// +// usage: go run spec.go LoongArch-Vol1-EN.pdf +// +// [1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.pdf + +package main + +import ( + "bytes" + "fmt" + "log" + "math" + "os" + "regexp" + "sort" + "strconv" + "strings" + + "rsc.io/pdf" +) + +func mergeMap(m1 map[string]string, m2 map[string]string) { + for k := range m2 { + m1[k] = m2[k] + } +} + +func main() { + log.SetFlags(0) + log.SetPrefix("loong64spec: ") + + if len(os.Args) != 2 { + fmt.Fprintf(os.Stderr, "usage: loong64spec LoongArch-Vol1-EN.pdf\n") + os.Exit(2) + } + f, err := pdf.Open(os.Args[1]) + if err != nil { + log.Fatal(err) + } + var prologue bytes.Buffer + prologue.Write([]byte("// Code generated by loong64spec LoongArch-Vol1-EN.pdf, DO NOT EDIT.\n\n// Copyright 2024 The Go Authors. All rights reserved.\n// Use of this source code is governed by a BSD-style\n// license that can be found in the LICENSE file.\n\npackage loong64asm\n\n")) + + var op_f bytes.Buffer + op_f.Write([]byte("const (\n\t_ Op = iota\n")) + + var opstr_f bytes.Buffer + opstr_f.Write([]byte("var opstr = [...]string{\n")) + + var instFormats_f bytes.Buffer + instFormats_f.Write([]byte("var instFormats = [...]instFormat{\n")) + + // Scan document looking for instructions. + n := f.NumPage() + var ops []string + opstrs := map[string]string{} + instFormatComments := map[string]string{} + instFormats := map[string]string{} + var fp int + for pageNum := 1; pageNum <= n; pageNum++ { + p := f.Page(pageNum) + if fp == 0 { + if !isFirstPage(p) { + continue + } + fp = pageNum + } + cPageOps, cPageOpstrs, cPageInstFormatComments, cPageInstFormats := parsePage(pageNum, p, fp == pageNum) + ops = append(ops, cPageOps...) + mergeMap(opstrs, cPageOpstrs) + mergeMap(instFormatComments, cPageInstFormatComments) + mergeMap(instFormats, cPageInstFormats) + } + + sort.Strings(ops) + + for _, op := range ops { + // 1. write op + op_f.Write([]byte(fmt.Sprintf("\t%s\n", op))) + // 2. write opstr + opstr_f.Write([]byte(fmt.Sprintf("\t%s\n", opstrs[op]))) + // 3. write instFormat + instFormats_f.Write([]byte(fmt.Sprintf("\t%s\n\t%s\n", instFormatComments[op], instFormats[op]))) + } + + op_f.Write([]byte(")\n\n")) + opstr_f.Write([]byte("}\n\n")) + instFormats_f.Write([]byte("}\n")) + + fileTables, err := os.Create("tables.go") + defer fileTables.Close() + + fileTables.Write(prologue.Bytes()) + fileTables.Write(op_f.Bytes()) + fileTables.Write(opstr_f.Bytes()) + fileTables.Write(instFormats_f.Bytes()) + + fileTables.Close() +} + +func isFirstPage(page pdf.Page) bool { + content := page.Content() + appendixb := "AppendixB" + ct := "" + for _, t := range content.Text { + ct += t.S + if ct == "AppendixB" { + return true + } + if strings.HasPrefix(appendixb, ct) { + continue + } else { + return false + } + } + return false +} + +func getArg(name string) (length int, argName string) { + switch { + case strings.Contains("arg_fd", name): + return 5, "arg_fd" + case strings.Contains("arg_fj", name): + return 5, "arg_fj" + case strings.Contains("arg_fk", name): + return 5, "arg_fk" + case strings.Contains("arg_fa", name): + return 5, "arg_fa" + case strings.Contains("arg_rd", name): + return 5, "arg_rd" + case strings.Contains("arg_rj", name) || name == "rj!=0,1": + return 5, "arg_rj" + case strings.Contains("arg_rk", name): + return 5, "arg_rk" + case name == "csr": + return 14, "arg_csr_23_10" + case strings.Contains("arg_cd", name): + return 5, "arg_cd" + case strings.Contains("arg_cj", name): + return 5, "arg_cj" + case strings.Contains("arg_ca", name): + return 5, "arg_ca" + case strings.Contains(name, "sa"): + length, _ := strconv.Atoi(strings.Split(name, "sa")[1]) + if length == 2 { + argName = "arg_sa2_16_15" + } else { + argName = "arg_sa3_17_15" + } + return length, argName + case strings.Contains("arg_seq_17_10", name): + return 8, "arg_seq_17_10" + case strings.Contains("arg_op_4_0", name): + return 5, "arg_op_4_0" + case strings.Contains(name, "ui"): + length, _ := strconv.Atoi(strings.Split(name, "ui")[1]) + if length == 5 { + argName = "arg_ui5_14_10" + } else if length == 6 { + argName = "arg_ui6_15_10" + } else { + argName = "arg_ui12_21_10" + } + return length, argName + case strings.Contains("arg_lsbw", name): + return 5, "arg_lsbw" + case strings.Contains("arg_msbw", name): + return 5, "arg_msbw" + case strings.Contains("arg_lsbd", name): + return 6, "arg_lsbd" + case strings.Contains("arg_msbd", name): + return 6, "arg_msbd" + case strings.Contains(name, "si"): + length, _ := strconv.Atoi(strings.Split(name, "si")[1]) + if length == 12 { + argName = "arg_si12_21_10" + } else if length == 14 { + argName = "arg_si14_23_10" + } else if length == 16 { + argName = "arg_si16_25_10" + } else { + argName = "arg_si20_24_5" + } + return length, argName + case strings.Contains(name, "offs"): + splitName := strings.Split(name, ":") + left, _ := strconv.Atoi(strings.Split(splitName[0], "[")[1]) + right, _ := strconv.Atoi(strings.Split(splitName[1], "]")[0]) + return left - right + 1, "offs" + default: + return 0, "" + } +} + +func binstrToHex(str string) string { + rst := 0 + hex := "0x" + charArray := []byte(str) + for i := 0; i < 32; { + rst = 1*(int(charArray[i+3])-48) + 2*(int(charArray[i+2])-48) + 4*(int(charArray[i+1])-48) + 8*(int(charArray[i])-48) + switch rst { + case 10: + hex = hex + "a" + case 11: + hex = hex + "b" + case 12: + hex = hex + "c" + case 13: + hex = hex + "d" + case 14: + hex = hex + "e" + case 15: + hex = hex + "f" + default: + hex += strconv.Itoa(rst) + } + + i = i + 4 + } + return hex +} + +/* +Here we deal with the instruction FCMP.cond.S/D, which has the following format: + + | 31 - 20 | 19 - 15 | 14 - 10 | 9 - 5 | 4 | 3 | 2 - 0 | + |---------|---------|---------|-------|---|---|-------| + | op | cond | fk | fj | 0 | 0 | cd | + +The `cond` field has these possible values: + + "CAF": "00", + "CUN": "08", + "CEQ": "04", + "CUEQ": "0c", + "CLT": "02", + "CULT": "0a", + "CLE": "06", + "CULE": "0e", + "CNE": "10", + "COR": "14", + "CUNE": "18", + "SAF": "01", + "SUN": "09", + "SEQ": "05", + "SUEQ": "0d", + "SLT": "03", + "SULT": "0b", + "SLE": "07", + "SULE": "0f", + "SNE": "11", + "SOR": "15", + "SUNE": "19", + +These values are the hexadecimal numbers of bits 19 to 15, the same as +described in the instruction set manual. + +The following code defines a map, the values in it represent the hexadecimal +encoding of the cond field in the entire instruction. In this case, the upper +4 bits and the lowest 1 bit are encoded separately, so the encoding is +different from the encoding described above. +*/ +func dealWithFcmp(ds string) (fcmpConditions map[string]map[string]string) { + conds := map[string]string{ + "CAF": "00", + "CUN": "40", + "CEQ": "20", + "CUEQ": "60", + "CLT": "10", + "CULT": "50", + "CLE": "30", + "CULE": "70", + "CNE": "80", + "COR": "a0", + "CUNE": "c0", + "SAF": "08", + "SUN": "48", + "SEQ": "28", + "SUEQ": "68", + "SLT": "18", + "SULT": "58", + "SLE": "38", + "SULE": "78", + "SNE": "88", + "SOR": "a8", + "SUNE": "c8", + } + fcmpConditions = make(map[string]map[string]string) + for k, v := range conds { + op := fmt.Sprintf("FCMP_%s_%s", k, ds) + opstr := fmt.Sprintf("FCMP_%s_%s:\t\"FCMP.%s.%s\",", k, ds, k, ds) + instFormatComment := fmt.Sprintf("// FCMP.%s.%s cd, fj, fk", k, ds) + var instFormat string + if ds == "D" { + instFormat = fmt.Sprintf("{mask: 0xffff8018, value: 0x0c2%s000, op: FCMP_%s_%s, args: instArgs{arg_cd, arg_fj, arg_fk}},", v, k, ds) + } else { + instFormat = fmt.Sprintf("{mask: 0xffff8018, value: 0x0c1%s000, op: FCMP_%s_%s, args: instArgs{arg_cd, arg_fj, arg_fk}},", v, k, ds) + } + + fcmpConditions[op] = make(map[string]string) + fcmpConditions[op]["op"] = op + fcmpConditions[op]["opstr"] = opstr + fcmpConditions[op]["instFormatComment"] = instFormatComment + fcmpConditions[op]["instFormat"] = instFormat + } + return +} + +func findWords(chars []pdf.Text) (words []pdf.Text) { + for i := 0; i < len(chars); { + xRange := []float64{chars[i].X, chars[i].X} + j := i + 1 + + // Find all chars on one line. + for j < len(chars) && chars[j].Y == chars[i].Y { + xRange[1] = chars[j].X + j++ + } + + // we need to note that the word may change line(Y) but belong to one cell. So, after loop over all continued + // chars whose Y are same, check if the next char's X belong to the range of xRange, if true, means it should + // be contact to current word, because the next word's X should bigger than current one. + for j < len(chars) && chars[j].X >= xRange[0] && chars[j].X <= xRange[1] { + j++ + } + + var end float64 + // Split line into words (really, phrases). + for k := i; k < j; { + ck := &chars[k] + s := ck.S + end = ck.X + ck.W + charSpace := ck.FontSize / 6 + wordSpace := ck.FontSize * 2 / 3 + l := k + 1 + for l < j { + // Grow word. + cl := &chars[l] + + if math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+charSpace { + s += cl.S + end = cl.X + cl.W + l++ + continue + } + // Add space to phrase before next word. + if math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+wordSpace { + s += " " + cl.S + end = cl.X + cl.W + l++ + continue + } + break + } + f := ck.Font + words = append(words, pdf.Text{ + Font: f, + FontSize: ck.FontSize, + X: ck.X, + Y: ck.Y, + W: end - ck.X, + S: s, + }) + k = l + } + i = j + } + + return words +} + +func parsePage(num int, p pdf.Page, isFP bool) (ops []string, opstrs map[string]string, instFormatComments map[string]string, instFormats map[string]string) { + opstrs = make(map[string]string) + instFormatComments = make(map[string]string) + instFormats = make(map[string]string) + + content := p.Content() + + var text []pdf.Text + for _, t := range content.Text { + text = append(text, t) + } + + // table name(70), table header(64), page num(3) + if isFP { + text = text[134 : len(text)-3] + } else { + text = text[64 : len(text)-3] + } + + text = findWords(text) + + for i := 0; i < len(text); { + var fcmpConditions map[string]map[string]string + if strings.HasPrefix(text[i].S, "FCMP") { + fcmpConditions = dealWithFcmp(strings.Split(text[i].S, ".")[2]) + + for fc, inst := range fcmpConditions { + ops = append(ops, inst["op"]) + opstrs[fc] = inst["opstr"] + instFormatComments[fc] = inst["instFormatComment"] + instFormats[fc] = inst["instFormat"] + } + t := i + 1 + for ; text[t].Y == text[i].Y; t++ { + continue + } + i = t + continue + } + + op := strings.Replace(text[i].S, ".", "_", -1) + opstr := fmt.Sprintf("%s:\t\"%s\",", op, text[i].S) + instFormatComment := "" + binValue := "" + binMask := "" + instArgs := "" + offs := false + var offArgs []string + + j := i + 1 + for ; j < len(text) && text[j].Y == text[i].Y; j++ { + + // Some instruction has no arguments, so the next word(text[j].S) is not the arguments string but 0/1 bit, it shouldn't be skipped. + if res, _ := regexp.MatchString("^\\d+$", text[j].S); j == i+1 && res == false { + instFormatComment = fmt.Sprintf("// %s %s", text[i].S, strings.Replace(text[j].S, ",", ", ", -1)) + continue + } + if text[j].S == "0" || text[j].S == "1" { + binValue += text[j].S + binMask += "1" + } else { + argLen, argName := getArg(text[j].S) + + // Get argument's length failed, compute it by other arguments. + if argLen == 0 { + left := 31 - len(binValue) + right := 0 + l := j + 1 + if l < len(text) && text[l].Y == text[j].Y { + for ; text[l].Y == text[j].Y; l++ { + if text[l].S == "0" || text[l].S == "1" { + right += 1 + } else { + tArgLen, _ := getArg(text[l].S) + if tArgLen == 0 { + fmt.Fprintf(os.Stderr, "there are more than two args whose length is unknown.\n") + } + right += tArgLen + } + } + } + argLen = left - right + 1 + argName = "arg_" + text[j].S + "_" + strconv.FormatInt(int64(left), 10) + "_" + strconv.FormatInt(int64(right), 10) + } + + for k := 0; k < argLen; k++ { + binValue += "0" + binMask += "0" + } + + if argName != "offs" { + if instArgs != "" { + instArgs = ", " + instArgs + } + instArgs = argName + instArgs + } else { + offs = true + offArgs = append(offArgs, text[j].S) + } + } + } + + // The real offset is a combination of two offsets in the binary code of the instruction, for example: BEQZ + if offs && offArgs != nil { + var left int + var right int + if len(offArgs) == 1 { + left, _ = strconv.Atoi(strings.Split(strings.Split(offArgs[0], ":")[0], "[")[1]) + right, _ = strconv.Atoi(strings.Split(strings.Split(offArgs[0], ":")[1], "]")[0]) + } else if len(offArgs) == 2 { + left, _ = strconv.Atoi(strings.Split(strings.Split(offArgs[1], ":")[0], "[")[1]) + right, _ = strconv.Atoi(strings.Split(strings.Split(offArgs[0], ":")[1], "]")[0]) + } + + if instArgs == "" { + instArgs = fmt.Sprintf("arg_offset_%d_%d", left, right) + } else { + instArgs += fmt.Sprintf(", arg_offset_%d_%d", left, right) + } + } + + ops = append(ops, op) + opstrs[op] = opstr + if instFormatComment == "" { + instFormatComment = "// " + text[i].S + } else if strings.HasPrefix(op, "AM") { + instFormatComment = fmt.Sprintf("// %s rd, rk, rj", text[i].S) + } + instFormatComments[op] = instFormatComment + // The parameter order of some instructions is inconsistent in encoding and syntax, such as BSTRINS.* + if instArgs != "" { + args := strings.Split(instFormatComment, " ")[2:] + tInstArgs := strings.Split(instArgs, ", ") + newOrderedInstArgs := []string{} + for _, a := range args { + a = strings.Split(a, ",")[0] + for _, aa := range tInstArgs { + if strings.Contains(aa, a) { + newOrderedInstArgs = append(newOrderedInstArgs, aa) + break + } else if a == "rd" && aa == "arg_fd" { + newOrderedInstArgs = append(newOrderedInstArgs, "arg_rd") + break + } + } + } + instArgs = strings.Join(newOrderedInstArgs, ", ") + } + if strings.HasPrefix(op, "AM") { + instArgs = "arg_rd, arg_rk, arg_rj" + } + instFormat := fmt.Sprintf("{mask: %s, value: %s, op: %s, args: instArgs{%s}},", binstrToHex(binMask), binstrToHex(binValue), op, instArgs) + instFormats[op] = instFormat + + i = j // next instruction + } + + return +} diff --git a/ppc64/ppc64asm/decode.go b/ppc64/ppc64asm/decode.go index b8d857c6..6c25c5c3 100644 --- a/ppc64/ppc64asm/decode.go +++ b/ppc64/ppc64asm/decode.go @@ -8,6 +8,8 @@ import ( "encoding/binary" "fmt" "log" + "sort" + "sync" ) const debugDecode = false @@ -111,6 +113,47 @@ const ( TypeLast // must be the last one ) +type InstMaskMap struct { + mask uint64 + insn map[uint64]*instFormat +} + +// Note, plxv/pstxv have a 5 bit opcode in the second instruction word. Only match the most significant 5 of 6 bits of the second primary opcode. +const lookupOpcodeMask = uint64(0xFC000000F8000000) + +// Three level lookup for any instruction: +// 1. Primary opcode map to a list of secondary opcode maps. +// 2. A list of opcodes with distinct masks, sorted by largest to smallest mask. +// 3. A map to a specific opcodes with a given mask. +var getLookupMap = sync.OnceValue(func() map[uint64][]InstMaskMap { + lMap := make(map[uint64][]InstMaskMap) + for idx, _ := range instFormats { + i := &instFormats[idx] + pop := i.Value & lookupOpcodeMask + var me *InstMaskMap + masks := lMap[pop] + for im, m := range masks { + if m.mask == i.Mask { + me = &masks[im] + break + } + } + if me == nil { + me = &InstMaskMap{i.Mask, map[uint64]*instFormat{}} + masks = append(masks, *me) + } + me.insn[i.Value] = i + lMap[pop] = masks + } + // Reverse sort masks to ensure extended mnemonics match before more generic forms of an opcode (e.x nop over ori 0,0,0) + for _, v := range lMap { + sort.Slice(v, func(i, j int) bool { + return v[i].mask > v[j].mask + }) + } + return lMap +}) + func (t ArgType) String() string { switch t { default: @@ -191,10 +234,13 @@ func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error) { ui |= uint64(ui_extn[1]) inst.SuffixEnc = ui_extn[1] } - for i, iform := range instFormats { - if ui&iform.Mask != iform.Value { + + fmts := getLookupMap()[ui&lookupOpcodeMask] + for i, masks := range fmts { + if _, fnd := masks.insn[masks.mask&ui]; !fnd { continue } + iform := masks.insn[masks.mask&ui] if ui&iform.DontCare != 0 { if debugDecode { log.Printf("Decode(%#x): unused bit is 1 for Op %s", ui, iform.Op) diff --git a/ppc64/ppc64asm/field.go b/ppc64/ppc64asm/field.go index 37794460..b47f672d 100644 --- a/ppc64/ppc64asm/field.go +++ b/ppc64/ppc64asm/field.go @@ -80,7 +80,7 @@ func (bs BitFields) Parse(i [2]uint32) uint64 { return u } -// Parse extracts the bitfields from i, concatenate them and return the result +// ParseSigned extracts the bitfields from i, concatenate them and return the result // as a signed integer. Parse will panic if any bitfield in b is invalid. func (bs BitFields) ParseSigned(i [2]uint32) int64 { u, l := bs.parse(i) diff --git a/ppc64/ppc64asm/gnu.go b/ppc64/ppc64asm/gnu.go index b4c9bf8d..367acdd4 100644 --- a/ppc64/ppc64asm/gnu.go +++ b/ppc64/ppc64asm/gnu.go @@ -359,7 +359,7 @@ func GNUSyntax(inst Inst, pc uint64) string { // gnuArg formats arg (which is the argIndex's arg in inst) according to GNU rules. // NOTE: because GNUSyntax is the only caller of this func, and it receives a copy -// of inst, it's ok to modify inst.Args here. +// of inst, it's ok to modify inst.Args here. func gnuArg(inst *Inst, argIndex int, arg Arg, pc uint64) string { // special cases for load/store instructions if _, ok := arg.(Offset); ok { diff --git a/ppc64/ppc64map/map.go b/ppc64/ppc64map/map.go index 1e3b1b6e..4e50843c 100644 --- a/ppc64/ppc64map/map.go +++ b/ppc64/ppc64map/map.go @@ -24,7 +24,6 @@ import ( "flag" "fmt" gofmt "go/format" - asm "golang.org/x/arch/ppc64/ppc64asm" "log" "math/bits" "os" @@ -33,6 +32,8 @@ import ( "strconv" "strings" "text/template" + + asm "golang.org/x/arch/ppc64/ppc64asm" ) var format = flag.String("fmt", "text", "output format: text, decoder, asm") @@ -287,7 +288,6 @@ func parseFields(encoding, text string, word int8) Args { if j < 0 { fmt.Fprintf(os.Stderr, "%s: wrong %d-th encoding field: %q\n", text, i, f) panic("Invalid encoding entry.") - continue } k := strings.Index(f[j+1:], " ") if k >= 0 { diff --git a/ppc64/ppc64spec/spec.go b/ppc64/ppc64spec/spec.go index 54e05353..ad9411f1 100644 --- a/ppc64/ppc64spec/spec.go +++ b/ppc64/ppc64spec/spec.go @@ -2,14 +2,12 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. -//go:build (go1.6 && amd64) || go1.8 -// +build go1.6,amd64 go1.8 - -// Power64spec reads the ``Power ISA V2.07'' Manual +// Power64spec reads the “Power ISA V2.07” Manual // to collect instruction encoding details and writes those details to standard output // in CSV format. // // Usage: +// // ppc64spec PowerISA_V2.07_PUBLIC.pdf >ppc64.csv // // Each CSV line contains four fields: @@ -24,7 +22,6 @@ // For now, empty. // // For more on the exact meaning of these fields, see the Power manual. -// package main import ( @@ -468,7 +465,14 @@ func findWords(chars []pdf.Text) (words []pdf.Text) { f := ck.Font f = strings.TrimSuffix(f, ",Italic") f = strings.TrimSuffix(f, "-Italic") - words = append(words, pdf.Text{f, ck.FontSize, ck.X, ck.Y, end - ck.X, s}) + words = append(words, pdf.Text{ + Font: f, + FontSize: ck.FontSize, + X: ck.X, + Y: ck.Y, + W: end - ck.X, + S: s, + }) k = l } i = j @@ -495,10 +499,10 @@ func sameFont(f1, f2 string) bool { } var jsFix = strings.NewReplacer( -// `\u003c`, `<`, -// `\u003e`, `>`, -// `\u0026`, `&`, -// `\u0009`, `\t`, +// `\u003c`, `<`, +// `\u003e`, `>`, +// `\u0026`, `&`, +// `\u0009`, `\t`, ) func printTable(name string, table []Inst) { diff --git a/ppc64/ppc64util/util.go b/ppc64/ppc64util/util.go index b2f19103..dcb8e428 100644 --- a/ppc64/ppc64util/util.go +++ b/ppc64/ppc64util/util.go @@ -3,7 +3,6 @@ // license that can be found in the LICENSE file. //go:build ignore -// +build ignore // Generate interesting test cases from ppc64 objdump via // go run util.go diff --git a/riscv64/riscv64asm/arg.go b/riscv64/riscv64asm/arg.go new file mode 100644 index 00000000..7898c273 --- /dev/null +++ b/riscv64/riscv64asm/arg.go @@ -0,0 +1,116 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +// Naming for Go decoder arguments: +// +// - arg_rd: a general purpose register rd encoded in rd[11:7] field +// +// - arg_rs1: a general purpose register rs1 encoded in rs1[19:15] field +// +// - arg_rs2: a general purpose register rs2 encoded in rs2[24:20] field +// +// - arg_rs3: a general purpose register rs3 encoded in rs3[31:27] field +// +// - arg_fd: a floating point register rd encoded in rd[11:7] field +// +// - arg_fs1: a floating point register rs1 encoded in rs1[19:15] field +// +// - arg_fs2: a floating point register rs2 encoded in rs2[24:20] field +// +// - arg_fs3: a floating point register rs3 encoded in rs3[31:27] field +// +// - arg_csr: a control status register encoded in csr[31:20] field +// +// - arg_rs1_mem: source register with offset in load commands +// +// - arg_rs1_store: source register with offset in store commands +// +// - arg_rs1_amo: source register with offset in atomic commands +// +// - arg_pred: predecessor memory ordering information encoded in pred[27:24] field +// For details, please refer to chapter 2.7 of ISA manual volume 1 +// +// - arg_succ: successor memory ordering information encoded in succ[23:20] field +// For details, please refer to chapter 2.7 of ISA manual volume 1 +// +// - arg_zimm: a unsigned immediate encoded in zimm[19:15] field +// +// - arg_imm12: an I-type immediate encoded in imm12[31:20] field +// +// - arg_simm12: a S-type immediate encoded in simm12[31:25|11:7] field +// +// - arg_bimm12: a B-type immediate encoded in bimm12[31:25|11:7] field +// +// - arg_imm20: an U-type immediate encoded in imm20[31:12] field +// +// - arg_jimm20: a J-type immediate encoded in jimm20[31:12] field +// +// - arg_shamt5: a shift amount encoded in shamt5[24:20] field +// +// - arg_shamt6: a shift amount encoded in shamt6[25:20] field +// + +type argType uint16 + +const ( + _ argType = iota + arg_rd + arg_rs1 + arg_rs2 + arg_rs3 + arg_fd + arg_fs1 + arg_fs2 + arg_fs3 + arg_csr + + arg_rs1_amo + arg_rs1_mem + arg_rs1_store + + arg_pred + arg_succ + + arg_zimm + arg_imm12 + arg_simm12 + arg_bimm12 + arg_imm20 + arg_jimm20 + arg_shamt5 + arg_shamt6 + + // RISC-V Compressed Extension Args + arg_rd_p + arg_fd_p + arg_rs1_p + arg_rd_rs1_p + arg_fs2_p + arg_rs2_p + arg_rd_n0 + arg_rs1_n0 + arg_rd_rs1_n0 + arg_c_rs1_n0 + arg_c_rs2_n0 + arg_c_fs2 + arg_c_rs2 + arg_rd_n2 + + arg_c_imm6 + arg_c_nzimm6 + arg_c_nzuimm6 + arg_c_uimm7 + arg_c_uimm8 + arg_c_uimm8sp_s + arg_c_uimm8sp + arg_c_uimm9sp_s + arg_c_uimm9sp + arg_c_bimm9 + arg_c_nzimm10 + arg_c_nzuimm10 + arg_c_imm12 + arg_c_nzimm18 +) diff --git a/riscv64/riscv64asm/csr_string.go b/riscv64/riscv64asm/csr_string.go new file mode 100644 index 00000000..addf91aa --- /dev/null +++ b/riscv64/riscv64asm/csr_string.go @@ -0,0 +1,577 @@ +// Code generated by "stringer -type=CSR"; DO NOT EDIT. + +package riscv64asm + +import "strconv" + +func _() { + // An "invalid array index" compiler error signifies that the constant values have changed. + // Re-run the stringer command to generate them again. + var x [1]struct{} + _ = x[USTATUS-0] + _ = x[FFLAGS-1] + _ = x[FRM-2] + _ = x[FCSR-3] + _ = x[UIE-4] + _ = x[UTVEC-5] + _ = x[UTVT-7] + _ = x[VSTART-8] + _ = x[VXSAT-9] + _ = x[VXRM-10] + _ = x[VCSR-15] + _ = x[USCRATCH-64] + _ = x[UEPC-65] + _ = x[UCAUSE-66] + _ = x[UTVAL-67] + _ = x[UIP-68] + _ = x[UNXTI-69] + _ = x[UINTSTATUS-70] + _ = x[USCRATCHCSW-72] + _ = x[USCRATCHCSWL-73] + _ = x[SSTATUS-256] + _ = x[SEDELEG-258] + _ = x[SIDELEG-259] + _ = x[SIE-260] + _ = x[STVEC-261] + _ = x[SCOUNTEREN-262] + _ = x[STVT-263] + _ = x[SSCRATCH-320] + _ = x[SEPC-321] + _ = x[SCAUSE-322] + _ = x[STVAL-323] + _ = x[SIP-324] + _ = x[SNXTI-325] + _ = x[SINTSTATUS-326] + _ = x[SSCRATCHCSW-328] + _ = x[SSCRATCHCSWL-329] + _ = x[SATP-384] + _ = x[VSSTATUS-512] + _ = x[VSIE-516] + _ = x[VSTVEC-517] + _ = x[VSSCRATCH-576] + _ = x[VSEPC-577] + _ = x[VSCAUSE-578] + _ = x[VSTVAL-579] + _ = x[VSIP-580] + _ = x[VSATP-640] + _ = x[MSTATUS-768] + _ = x[MISA-769] + _ = x[MEDELEG-770] + _ = x[MIDELEG-771] + _ = x[MIE-772] + _ = x[MTVEC-773] + _ = x[MCOUNTEREN-774] + _ = x[MTVT-775] + _ = x[MSTATUSH-784] + _ = x[MCOUNTINHIBIT-800] + _ = x[MHPMEVENT3-803] + _ = x[MHPMEVENT4-804] + _ = x[MHPMEVENT5-805] + _ = x[MHPMEVENT6-806] + _ = x[MHPMEVENT7-807] + _ = x[MHPMEVENT8-808] + _ = x[MHPMEVENT9-809] + _ = x[MHPMEVENT10-810] + _ = x[MHPMEVENT11-811] + _ = x[MHPMEVENT12-812] + _ = x[MHPMEVENT13-813] + _ = x[MHPMEVENT14-814] + _ = x[MHPMEVENT15-815] + _ = x[MHPMEVENT16-816] + _ = x[MHPMEVENT17-817] + _ = x[MHPMEVENT18-818] + _ = x[MHPMEVENT19-819] + _ = x[MHPMEVENT20-820] + _ = x[MHPMEVENT21-821] + _ = x[MHPMEVENT22-822] + _ = x[MHPMEVENT23-823] + _ = x[MHPMEVENT24-824] + _ = x[MHPMEVENT25-825] + _ = x[MHPMEVENT26-826] + _ = x[MHPMEVENT27-827] + _ = x[MHPMEVENT28-828] + _ = x[MHPMEVENT29-829] + _ = x[MHPMEVENT30-830] + _ = x[MHPMEVENT31-831] + _ = x[MSCRATCH-832] + _ = x[MEPC-833] + _ = x[MCAUSE-834] + _ = x[MTVAL-835] + _ = x[MIP-836] + _ = x[MNXTI-837] + _ = x[MINTSTATUS-838] + _ = x[MSCRATCHCSW-840] + _ = x[MSCRATCHCSWL-841] + _ = x[MTINST-842] + _ = x[MTVAL2-843] + _ = x[PMPCFG0-928] + _ = x[PMPCFG1-929] + _ = x[PMPCFG2-930] + _ = x[PMPCFG3-931] + _ = x[PMPADDR0-944] + _ = x[PMPADDR1-945] + _ = x[PMPADDR2-946] + _ = x[PMPADDR3-947] + _ = x[PMPADDR4-948] + _ = x[PMPADDR5-949] + _ = x[PMPADDR6-950] + _ = x[PMPADDR7-951] + _ = x[PMPADDR8-952] + _ = x[PMPADDR9-953] + _ = x[PMPADDR10-954] + _ = x[PMPADDR11-955] + _ = x[PMPADDR12-956] + _ = x[PMPADDR13-957] + _ = x[PMPADDR14-958] + _ = x[PMPADDR15-959] + _ = x[HSTATUS-1536] + _ = x[HEDELEG-1538] + _ = x[HIDELEG-1539] + _ = x[HIE-1540] + _ = x[HTIMEDELTA-1541] + _ = x[HCOUNTEREN-1542] + _ = x[HGEIE-1543] + _ = x[HTIMEDELTAH-1557] + _ = x[HTVAL-1603] + _ = x[HIP-1604] + _ = x[HVIP-1605] + _ = x[HTINST-1610] + _ = x[HGATP-1664] + _ = x[TSELECT-1952] + _ = x[TDATA1-1953] + _ = x[TDATA2-1954] + _ = x[TDATA3-1955] + _ = x[TINFO-1956] + _ = x[TCONTROL-1957] + _ = x[MCONTEXT-1960] + _ = x[MNOISE-1961] + _ = x[SCONTEXT-1962] + _ = x[DCSR-1968] + _ = x[DPC-1969] + _ = x[DSCRATCH0-1970] + _ = x[DSCRATCH1-1971] + _ = x[MCYCLE-2816] + _ = x[MINSTRET-2818] + _ = x[MHPMCOUNTER3-2819] + _ = x[MHPMCOUNTER4-2820] + _ = x[MHPMCOUNTER5-2821] + _ = x[MHPMCOUNTER6-2822] + _ = x[MHPMCOUNTER7-2823] + _ = x[MHPMCOUNTER8-2824] + _ = x[MHPMCOUNTER9-2825] + _ = x[MHPMCOUNTER10-2826] + _ = x[MHPMCOUNTER11-2827] + _ = x[MHPMCOUNTER12-2828] + _ = x[MHPMCOUNTER13-2829] + _ = x[MHPMCOUNTER14-2830] + _ = x[MHPMCOUNTER15-2831] + _ = x[MHPMCOUNTER16-2832] + _ = x[MHPMCOUNTER17-2833] + _ = x[MHPMCOUNTER18-2834] + _ = x[MHPMCOUNTER19-2835] + _ = x[MHPMCOUNTER20-2836] + _ = x[MHPMCOUNTER21-2837] + _ = x[MHPMCOUNTER22-2838] + _ = x[MHPMCOUNTER23-2839] + _ = x[MHPMCOUNTER24-2840] + _ = x[MHPMCOUNTER25-2841] + _ = x[MHPMCOUNTER26-2842] + _ = x[MHPMCOUNTER27-2843] + _ = x[MHPMCOUNTER28-2844] + _ = x[MHPMCOUNTER29-2845] + _ = x[MHPMCOUNTER30-2846] + _ = x[MHPMCOUNTER31-2847] + _ = x[MCYCLEH-2944] + _ = x[MINSTRETH-2946] + _ = x[MHPMCOUNTER3H-2947] + _ = x[MHPMCOUNTER4H-2948] + _ = x[MHPMCOUNTER5H-2949] + _ = x[MHPMCOUNTER6H-2950] + _ = x[MHPMCOUNTER7H-2951] + _ = x[MHPMCOUNTER8H-2952] + _ = x[MHPMCOUNTER9H-2953] + _ = x[MHPMCOUNTER10H-2954] + _ = x[MHPMCOUNTER11H-2955] + _ = x[MHPMCOUNTER12H-2956] + _ = x[MHPMCOUNTER13H-2957] + _ = x[MHPMCOUNTER14H-2958] + _ = x[MHPMCOUNTER15H-2959] + _ = x[MHPMCOUNTER16H-2960] + _ = x[MHPMCOUNTER17H-2961] + _ = x[MHPMCOUNTER18H-2962] + _ = x[MHPMCOUNTER19H-2963] + _ = x[MHPMCOUNTER20H-2964] + _ = x[MHPMCOUNTER21H-2965] + _ = x[MHPMCOUNTER22H-2966] + _ = x[MHPMCOUNTER23H-2967] + _ = x[MHPMCOUNTER24H-2968] + _ = x[MHPMCOUNTER25H-2969] + _ = x[MHPMCOUNTER26H-2970] + _ = x[MHPMCOUNTER27H-2971] + _ = x[MHPMCOUNTER28H-2972] + _ = x[MHPMCOUNTER29H-2973] + _ = x[MHPMCOUNTER30H-2974] + _ = x[MHPMCOUNTER31H-2975] + _ = x[CYCLE-3072] + _ = x[TIME-3073] + _ = x[INSTRET-3074] + _ = x[HPMCOUNTER3-3075] + _ = x[HPMCOUNTER4-3076] + _ = x[HPMCOUNTER5-3077] + _ = x[HPMCOUNTER6-3078] + _ = x[HPMCOUNTER7-3079] + _ = x[HPMCOUNTER8-3080] + _ = x[HPMCOUNTER9-3081] + _ = x[HPMCOUNTER10-3082] + _ = x[HPMCOUNTER11-3083] + _ = x[HPMCOUNTER12-3084] + _ = x[HPMCOUNTER13-3085] + _ = x[HPMCOUNTER14-3086] + _ = x[HPMCOUNTER15-3087] + _ = x[HPMCOUNTER16-3088] + _ = x[HPMCOUNTER17-3089] + _ = x[HPMCOUNTER18-3090] + _ = x[HPMCOUNTER19-3091] + _ = x[HPMCOUNTER20-3092] + _ = x[HPMCOUNTER21-3093] + _ = x[HPMCOUNTER22-3094] + _ = x[HPMCOUNTER23-3095] + _ = x[HPMCOUNTER24-3096] + _ = x[HPMCOUNTER25-3097] + _ = x[HPMCOUNTER26-3098] + _ = x[HPMCOUNTER27-3099] + _ = x[HPMCOUNTER28-3100] + _ = x[HPMCOUNTER29-3101] + _ = x[HPMCOUNTER30-3102] + _ = x[HPMCOUNTER31-3103] + _ = x[VL-3104] + _ = x[VTYPE-3105] + _ = x[VLENB-3106] + _ = x[CYCLEH-3200] + _ = x[TIMEH-3201] + _ = x[INSTRETH-3202] + _ = x[HPMCOUNTER3H-3203] + _ = x[HPMCOUNTER4H-3204] + _ = x[HPMCOUNTER5H-3205] + _ = x[HPMCOUNTER6H-3206] + _ = x[HPMCOUNTER7H-3207] + _ = x[HPMCOUNTER8H-3208] + _ = x[HPMCOUNTER9H-3209] + _ = x[HPMCOUNTER10H-3210] + _ = x[HPMCOUNTER11H-3211] + _ = x[HPMCOUNTER12H-3212] + _ = x[HPMCOUNTER13H-3213] + _ = x[HPMCOUNTER14H-3214] + _ = x[HPMCOUNTER15H-3215] + _ = x[HPMCOUNTER16H-3216] + _ = x[HPMCOUNTER17H-3217] + _ = x[HPMCOUNTER18H-3218] + _ = x[HPMCOUNTER19H-3219] + _ = x[HPMCOUNTER20H-3220] + _ = x[HPMCOUNTER21H-3221] + _ = x[HPMCOUNTER22H-3222] + _ = x[HPMCOUNTER23H-3223] + _ = x[HPMCOUNTER24H-3224] + _ = x[HPMCOUNTER25H-3225] + _ = x[HPMCOUNTER26H-3226] + _ = x[HPMCOUNTER27H-3227] + _ = x[HPMCOUNTER28H-3228] + _ = x[HPMCOUNTER29H-3229] + _ = x[HPMCOUNTER30H-3230] + _ = x[HPMCOUNTER31H-3231] + _ = x[HGEIP-3602] + _ = x[MVENDORID-3857] + _ = x[MARCHID-3858] + _ = x[MIMPID-3859] + _ = x[MHARTID-3860] + _ = x[MENTROPY-3861] +} + +const _CSR_name = "USTATUSFFLAGSFRMFCSRUIEUTVECUTVTVSTARTVXSATVXRMVCSRUSCRATCHUEPCUCAUSEUTVALUIPUNXTIUINTSTATUSUSCRATCHCSWUSCRATCHCSWLSSTATUSSEDELEGSIDELEGSIESTVECSCOUNTERENSTVTSSCRATCHSEPCSCAUSESTVALSIPSNXTISINTSTATUSSSCRATCHCSWSSCRATCHCSWLSATPVSSTATUSVSIEVSTVECVSSCRATCHVSEPCVSCAUSEVSTVALVSIPVSATPMSTATUSMISAMEDELEGMIDELEGMIEMTVECMCOUNTERENMTVTMSTATUSHMCOUNTINHIBITMHPMEVENT3MHPMEVENT4MHPMEVENT5MHPMEVENT6MHPMEVENT7MHPMEVENT8MHPMEVENT9MHPMEVENT10MHPMEVENT11MHPMEVENT12MHPMEVENT13MHPMEVENT14MHPMEVENT15MHPMEVENT16MHPMEVENT17MHPMEVENT18MHPMEVENT19MHPMEVENT20MHPMEVENT21MHPMEVENT22MHPMEVENT23MHPMEVENT24MHPMEVENT25MHPMEVENT26MHPMEVENT27MHPMEVENT28MHPMEVENT29MHPMEVENT30MHPMEVENT31MSCRATCHMEPCMCAUSEMTVALMIPMNXTIMINTSTATUSMSCRATCHCSWMSCRATCHCSWLMTINSTMTVAL2PMPCFG0PMPCFG1PMPCFG2PMPCFG3PMPADDR0PMPADDR1PMPADDR2PMPADDR3PMPADDR4PMPADDR5PMPADDR6PMPADDR7PMPADDR8PMPADDR9PMPADDR10PMPADDR11PMPADDR12PMPADDR13PMPADDR14PMPADDR15HSTATUSHEDELEGHIDELEGHIEHTIMEDELTAHCOUNTERENHGEIEHTIMEDELTAHHTVALHIPHVIPHTINSTHGATPTSELECTTDATA1TDATA2TDATA3TINFOTCONTROLMCONTEXTMNOISESCONTEXTDCSRDPCDSCRATCH0DSCRATCH1MCYCLEMINSTRETMHPMCOUNTER3MHPMCOUNTER4MHPMCOUNTER5MHPMCOUNTER6MHPMCOUNTER7MHPMCOUNTER8MHPMCOUNTER9MHPMCOUNTER10MHPMCOUNTER11MHPMCOUNTER12MHPMCOUNTER13MHPMCOUNTER14MHPMCOUNTER15MHPMCOUNTER16MHPMCOUNTER17MHPMCOUNTER18MHPMCOUNTER19MHPMCOUNTER20MHPMCOUNTER21MHPMCOUNTER22MHPMCOUNTER23MHPMCOUNTER24MHPMCOUNTER25MHPMCOUNTER26MHPMCOUNTER27MHPMCOUNTER28MHPMCOUNTER29MHPMCOUNTER30MHPMCOUNTER31MCYCLEHMINSTRETHMHPMCOUNTER3HMHPMCOUNTER4HMHPMCOUNTER5HMHPMCOUNTER6HMHPMCOUNTER7HMHPMCOUNTER8HMHPMCOUNTER9HMHPMCOUNTER10HMHPMCOUNTER11HMHPMCOUNTER12HMHPMCOUNTER13HMHPMCOUNTER14HMHPMCOUNTER15HMHPMCOUNTER16HMHPMCOUNTER17HMHPMCOUNTER18HMHPMCOUNTER19HMHPMCOUNTER20HMHPMCOUNTER21HMHPMCOUNTER22HMHPMCOUNTER23HMHPMCOUNTER24HMHPMCOUNTER25HMHPMCOUNTER26HMHPMCOUNTER27HMHPMCOUNTER28HMHPMCOUNTER29HMHPMCOUNTER30HMHPMCOUNTER31HCYCLETIMEINSTRETHPMCOUNTER3HPMCOUNTER4HPMCOUNTER5HPMCOUNTER6HPMCOUNTER7HPMCOUNTER8HPMCOUNTER9HPMCOUNTER10HPMCOUNTER11HPMCOUNTER12HPMCOUNTER13HPMCOUNTER14HPMCOUNTER15HPMCOUNTER16HPMCOUNTER17HPMCOUNTER18HPMCOUNTER19HPMCOUNTER20HPMCOUNTER21HPMCOUNTER22HPMCOUNTER23HPMCOUNTER24HPMCOUNTER25HPMCOUNTER26HPMCOUNTER27HPMCOUNTER28HPMCOUNTER29HPMCOUNTER30HPMCOUNTER31VLVTYPEVLENBCYCLEHTIMEHINSTRETHHPMCOUNTER3HHPMCOUNTER4HHPMCOUNTER5HHPMCOUNTER6HHPMCOUNTER7HHPMCOUNTER8HHPMCOUNTER9HHPMCOUNTER10HHPMCOUNTER11HHPMCOUNTER12HHPMCOUNTER13HHPMCOUNTER14HHPMCOUNTER15HHPMCOUNTER16HHPMCOUNTER17HHPMCOUNTER18HHPMCOUNTER19HHPMCOUNTER20HHPMCOUNTER21HHPMCOUNTER22HHPMCOUNTER23HHPMCOUNTER24HHPMCOUNTER25HHPMCOUNTER26HHPMCOUNTER27HHPMCOUNTER28HHPMCOUNTER29HHPMCOUNTER30HHPMCOUNTER31HHGEIPMVENDORIDMARCHIDMIMPIDMHARTIDMENTROPY" + +var _CSR_map = map[CSR]string{ + 0: _CSR_name[0:7], + 1: _CSR_name[7:13], + 2: _CSR_name[13:16], + 3: _CSR_name[16:20], + 4: _CSR_name[20:23], + 5: _CSR_name[23:28], + 7: _CSR_name[28:32], + 8: _CSR_name[32:38], + 9: _CSR_name[38:43], + 10: _CSR_name[43:47], + 15: _CSR_name[47:51], + 64: _CSR_name[51:59], + 65: _CSR_name[59:63], + 66: _CSR_name[63:69], + 67: _CSR_name[69:74], + 68: _CSR_name[74:77], + 69: _CSR_name[77:82], + 70: _CSR_name[82:92], + 72: _CSR_name[92:103], + 73: _CSR_name[103:115], + 256: _CSR_name[115:122], + 258: _CSR_name[122:129], + 259: _CSR_name[129:136], + 260: _CSR_name[136:139], + 261: _CSR_name[139:144], + 262: _CSR_name[144:154], + 263: _CSR_name[154:158], + 320: _CSR_name[158:166], + 321: _CSR_name[166:170], + 322: _CSR_name[170:176], + 323: _CSR_name[176:181], + 324: _CSR_name[181:184], + 325: _CSR_name[184:189], + 326: _CSR_name[189:199], + 328: _CSR_name[199:210], + 329: _CSR_name[210:222], + 384: _CSR_name[222:226], + 512: _CSR_name[226:234], + 516: _CSR_name[234:238], + 517: _CSR_name[238:244], + 576: _CSR_name[244:253], + 577: _CSR_name[253:258], + 578: _CSR_name[258:265], + 579: _CSR_name[265:271], + 580: _CSR_name[271:275], + 640: _CSR_name[275:280], + 768: _CSR_name[280:287], + 769: _CSR_name[287:291], + 770: _CSR_name[291:298], + 771: _CSR_name[298:305], + 772: _CSR_name[305:308], + 773: _CSR_name[308:313], + 774: _CSR_name[313:323], + 775: _CSR_name[323:327], + 784: _CSR_name[327:335], + 800: _CSR_name[335:348], + 803: _CSR_name[348:358], + 804: _CSR_name[358:368], + 805: _CSR_name[368:378], + 806: _CSR_name[378:388], + 807: _CSR_name[388:398], + 808: _CSR_name[398:408], + 809: _CSR_name[408:418], + 810: _CSR_name[418:429], + 811: _CSR_name[429:440], + 812: _CSR_name[440:451], + 813: _CSR_name[451:462], + 814: _CSR_name[462:473], + 815: _CSR_name[473:484], + 816: _CSR_name[484:495], + 817: _CSR_name[495:506], + 818: _CSR_name[506:517], + 819: _CSR_name[517:528], + 820: _CSR_name[528:539], + 821: _CSR_name[539:550], + 822: _CSR_name[550:561], + 823: _CSR_name[561:572], + 824: _CSR_name[572:583], + 825: _CSR_name[583:594], + 826: _CSR_name[594:605], + 827: _CSR_name[605:616], + 828: _CSR_name[616:627], + 829: _CSR_name[627:638], + 830: _CSR_name[638:649], + 831: _CSR_name[649:660], + 832: _CSR_name[660:668], + 833: _CSR_name[668:672], + 834: _CSR_name[672:678], + 835: _CSR_name[678:683], + 836: _CSR_name[683:686], + 837: _CSR_name[686:691], + 838: _CSR_name[691:701], + 840: _CSR_name[701:712], + 841: _CSR_name[712:724], + 842: _CSR_name[724:730], + 843: _CSR_name[730:736], + 928: _CSR_name[736:743], + 929: _CSR_name[743:750], + 930: _CSR_name[750:757], + 931: _CSR_name[757:764], + 944: _CSR_name[764:772], + 945: _CSR_name[772:780], + 946: _CSR_name[780:788], + 947: _CSR_name[788:796], + 948: _CSR_name[796:804], + 949: _CSR_name[804:812], + 950: _CSR_name[812:820], + 951: _CSR_name[820:828], + 952: _CSR_name[828:836], + 953: _CSR_name[836:844], + 954: _CSR_name[844:853], + 955: _CSR_name[853:862], + 956: _CSR_name[862:871], + 957: _CSR_name[871:880], + 958: _CSR_name[880:889], + 959: _CSR_name[889:898], + 1536: _CSR_name[898:905], + 1538: _CSR_name[905:912], + 1539: _CSR_name[912:919], + 1540: _CSR_name[919:922], + 1541: _CSR_name[922:932], + 1542: _CSR_name[932:942], + 1543: _CSR_name[942:947], + 1557: _CSR_name[947:958], + 1603: _CSR_name[958:963], + 1604: _CSR_name[963:966], + 1605: _CSR_name[966:970], + 1610: _CSR_name[970:976], + 1664: _CSR_name[976:981], + 1952: _CSR_name[981:988], + 1953: _CSR_name[988:994], + 1954: _CSR_name[994:1000], + 1955: _CSR_name[1000:1006], + 1956: _CSR_name[1006:1011], + 1957: _CSR_name[1011:1019], + 1960: _CSR_name[1019:1027], + 1961: _CSR_name[1027:1033], + 1962: _CSR_name[1033:1041], + 1968: _CSR_name[1041:1045], + 1969: _CSR_name[1045:1048], + 1970: _CSR_name[1048:1057], + 1971: _CSR_name[1057:1066], + 2816: _CSR_name[1066:1072], + 2818: _CSR_name[1072:1080], + 2819: _CSR_name[1080:1092], + 2820: _CSR_name[1092:1104], + 2821: _CSR_name[1104:1116], + 2822: _CSR_name[1116:1128], + 2823: _CSR_name[1128:1140], + 2824: _CSR_name[1140:1152], + 2825: _CSR_name[1152:1164], + 2826: _CSR_name[1164:1177], + 2827: _CSR_name[1177:1190], + 2828: _CSR_name[1190:1203], + 2829: _CSR_name[1203:1216], + 2830: _CSR_name[1216:1229], + 2831: _CSR_name[1229:1242], + 2832: _CSR_name[1242:1255], + 2833: _CSR_name[1255:1268], + 2834: _CSR_name[1268:1281], + 2835: _CSR_name[1281:1294], + 2836: _CSR_name[1294:1307], + 2837: _CSR_name[1307:1320], + 2838: _CSR_name[1320:1333], + 2839: _CSR_name[1333:1346], + 2840: _CSR_name[1346:1359], + 2841: _CSR_name[1359:1372], + 2842: _CSR_name[1372:1385], + 2843: _CSR_name[1385:1398], + 2844: _CSR_name[1398:1411], + 2845: _CSR_name[1411:1424], + 2846: _CSR_name[1424:1437], + 2847: _CSR_name[1437:1450], + 2944: _CSR_name[1450:1457], + 2946: _CSR_name[1457:1466], + 2947: _CSR_name[1466:1479], + 2948: _CSR_name[1479:1492], + 2949: _CSR_name[1492:1505], + 2950: _CSR_name[1505:1518], + 2951: _CSR_name[1518:1531], + 2952: _CSR_name[1531:1544], + 2953: _CSR_name[1544:1557], + 2954: _CSR_name[1557:1571], + 2955: _CSR_name[1571:1585], + 2956: _CSR_name[1585:1599], + 2957: _CSR_name[1599:1613], + 2958: _CSR_name[1613:1627], + 2959: _CSR_name[1627:1641], + 2960: _CSR_name[1641:1655], + 2961: _CSR_name[1655:1669], + 2962: _CSR_name[1669:1683], + 2963: _CSR_name[1683:1697], + 2964: _CSR_name[1697:1711], + 2965: _CSR_name[1711:1725], + 2966: _CSR_name[1725:1739], + 2967: _CSR_name[1739:1753], + 2968: _CSR_name[1753:1767], + 2969: _CSR_name[1767:1781], + 2970: _CSR_name[1781:1795], + 2971: _CSR_name[1795:1809], + 2972: _CSR_name[1809:1823], + 2973: _CSR_name[1823:1837], + 2974: _CSR_name[1837:1851], + 2975: _CSR_name[1851:1865], + 3072: _CSR_name[1865:1870], + 3073: _CSR_name[1870:1874], + 3074: _CSR_name[1874:1881], + 3075: _CSR_name[1881:1892], + 3076: _CSR_name[1892:1903], + 3077: _CSR_name[1903:1914], + 3078: _CSR_name[1914:1925], + 3079: _CSR_name[1925:1936], + 3080: _CSR_name[1936:1947], + 3081: _CSR_name[1947:1958], + 3082: _CSR_name[1958:1970], + 3083: _CSR_name[1970:1982], + 3084: _CSR_name[1982:1994], + 3085: _CSR_name[1994:2006], + 3086: _CSR_name[2006:2018], + 3087: _CSR_name[2018:2030], + 3088: _CSR_name[2030:2042], + 3089: _CSR_name[2042:2054], + 3090: _CSR_name[2054:2066], + 3091: _CSR_name[2066:2078], + 3092: _CSR_name[2078:2090], + 3093: _CSR_name[2090:2102], + 3094: _CSR_name[2102:2114], + 3095: _CSR_name[2114:2126], + 3096: _CSR_name[2126:2138], + 3097: _CSR_name[2138:2150], + 3098: _CSR_name[2150:2162], + 3099: _CSR_name[2162:2174], + 3100: _CSR_name[2174:2186], + 3101: _CSR_name[2186:2198], + 3102: _CSR_name[2198:2210], + 3103: _CSR_name[2210:2222], + 3104: _CSR_name[2222:2224], + 3105: _CSR_name[2224:2229], + 3106: _CSR_name[2229:2234], + 3200: _CSR_name[2234:2240], + 3201: _CSR_name[2240:2245], + 3202: _CSR_name[2245:2253], + 3203: _CSR_name[2253:2265], + 3204: _CSR_name[2265:2277], + 3205: _CSR_name[2277:2289], + 3206: _CSR_name[2289:2301], + 3207: _CSR_name[2301:2313], + 3208: _CSR_name[2313:2325], + 3209: _CSR_name[2325:2337], + 3210: _CSR_name[2337:2350], + 3211: _CSR_name[2350:2363], + 3212: _CSR_name[2363:2376], + 3213: _CSR_name[2376:2389], + 3214: _CSR_name[2389:2402], + 3215: _CSR_name[2402:2415], + 3216: _CSR_name[2415:2428], + 3217: _CSR_name[2428:2441], + 3218: _CSR_name[2441:2454], + 3219: _CSR_name[2454:2467], + 3220: _CSR_name[2467:2480], + 3221: _CSR_name[2480:2493], + 3222: _CSR_name[2493:2506], + 3223: _CSR_name[2506:2519], + 3224: _CSR_name[2519:2532], + 3225: _CSR_name[2532:2545], + 3226: _CSR_name[2545:2558], + 3227: _CSR_name[2558:2571], + 3228: _CSR_name[2571:2584], + 3229: _CSR_name[2584:2597], + 3230: _CSR_name[2597:2610], + 3231: _CSR_name[2610:2623], + 3602: _CSR_name[2623:2628], + 3857: _CSR_name[2628:2637], + 3858: _CSR_name[2637:2644], + 3859: _CSR_name[2644:2650], + 3860: _CSR_name[2650:2657], + 3861: _CSR_name[2657:2665], +} + +func (i CSR) String() string { + if str, ok := _CSR_map[i]; ok { + return str + } + return "CSR(" + strconv.FormatInt(int64(i), 10) + ")" +} diff --git a/riscv64/riscv64asm/decode.go b/riscv64/riscv64asm/decode.go new file mode 100644 index 00000000..d78fef9e --- /dev/null +++ b/riscv64/riscv64asm/decode.go @@ -0,0 +1,550 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +import ( + "encoding/binary" + "errors" +) + +type argTypeList [6]argType + +// An instFormat describes the format of an instruction encoding. +type instFormat struct { + mask uint32 + value uint32 + op Op + // args describe how to decode the instruction arguments. + // args is stored as a fixed-size array. + // if there are fewer than len(args) arguments, args[i] == 0 marks + // the end of the argument list. + args argTypeList +} + +var ( + errShort = errors.New("truncated instruction") + errUnknown = errors.New("unknown instruction") +) + +var decoderCover []bool + +func init() { + decoderCover = make([]bool, len(instFormats)) +} + +// Decode decodes the 4 bytes in src as a single instruction. +func Decode(src []byte) (Inst, error) { + length := len(src) + if length < 2 { + return Inst{}, errShort + } + + var x uint32 + // Non-RVC instructions always starts with 0x11 + // So check whether src[0] & 3 == 3 + if src[0]&3 == 3 { + if length < 4 { + return Inst{}, errShort + } + length = 4 + x = binary.LittleEndian.Uint32(src) + } else { + length = 2 + x = uint32(binary.LittleEndian.Uint16(src)) + } + +Search: + for i, f := range instFormats { + if (x & f.mask) != f.value { + continue + } + + // Decode args. + var args Args + for j, aop := range f.args { + if aop == 0 { + break + } + arg := decodeArg(aop, x, i) + if arg == nil && f.op != C_NOP { + // Cannot decode argument. + continue Search + } + args[j] = arg + } + + if length == 2 { + args = convertCompressedIns(&f, args) + } + + decoderCover[i] = true + inst := Inst{ + Op: f.op, + Args: args, + Enc: x, + Len: length, + } + return inst, nil + } + return Inst{}, errUnknown +} + +// decodeArg decodes the arg described by aop from the instruction bits x. +// It returns nil if x cannot be decoded according to aop. +func decodeArg(aop argType, x uint32, index int) Arg { + switch aop { + case arg_rd: + return X0 + Reg((x>>7)&((1<<5)-1)) + + case arg_rs1: + return X0 + Reg((x>>15)&((1<<5)-1)) + + case arg_rs2: + return X0 + Reg((x>>20)&((1<<5)-1)) + + case arg_rs3: + return X0 + Reg((x>>27)&((1<<5)-1)) + + case arg_fd: + return F0 + Reg((x>>7)&((1<<5)-1)) + + case arg_fs1: + return F0 + Reg((x>>15)&((1<<5)-1)) + + case arg_fs2: + return F0 + Reg((x>>20)&((1<<5)-1)) + + case arg_fs3: + return F0 + Reg((x>>27)&((1<<5)-1)) + + case arg_rs1_amo: + return AmoReg{X0 + Reg((x>>15)&((1<<5)-1))} + + case arg_rs1_mem: + imm := x >> 20 + // Sign-extend + if imm>>uint32(12-1) == 1 { + imm |= 0xfffff << 12 + } + return RegOffset{X0 + Reg((x>>15)&((1<<5)-1)), Simm{int32(imm), true, 12}} + + case arg_rs1_store: + imm := (x<<20)>>27 | (x>>25)<<5 + // Sign-extend + if imm>>uint32(12-1) == 1 { + imm |= 0xfffff << 12 + } + return RegOffset{X0 + Reg((x>>15)&((1<<5)-1)), Simm{int32(imm), true, 12}} + + case arg_pred: + imm := x << 4 >> 28 + return MemOrder(uint8(imm)) + + case arg_succ: + imm := x << 8 >> 28 + return MemOrder(uint8(imm)) + + case arg_csr: + imm := x >> 20 + return CSR(imm) + + case arg_zimm: + imm := x << 12 >> 27 + return Uimm{imm, true} + + case arg_shamt5: + imm := x << 7 >> 27 + return Uimm{imm, false} + + case arg_shamt6: + imm := x << 6 >> 26 + return Uimm{imm, false} + + case arg_imm12: + imm := x >> 20 + // Sign-extend + if imm>>uint32(12-1) == 1 { + imm |= 0xfffff << 12 + } + return Simm{int32(imm), true, 12} + + case arg_imm20: + imm := x >> 12 + return Uimm{imm, false} + + case arg_jimm20: + imm := (x>>31)<<20 | (x<<1)>>22<<1 | (x<<11)>>31<<11 | (x<<12)>>24<<12 + // Sign-extend + if imm>>uint32(21-1) == 1 { + imm |= 0x7ff << 21 + } + return Simm{int32(imm), true, 21} + + case arg_simm12: + imm := (x<<20)>>27 | (x>>25)<<5 + // Sign-extend + if imm>>uint32(12-1) == 1 { + imm |= 0xfffff << 12 + } + return Simm{int32(imm), true, 12} + + case arg_bimm12: + imm := (x<<20)>>28<<1 | (x<<1)>>26<<5 | (x<<24)>>31<<11 | (x>>31)<<12 + // Sign-extend + if imm>>uint32(13-1) == 1 { + imm |= 0x7ffff << 13 + } + return Simm{int32(imm), true, 13} + + case arg_rd_p, arg_rs2_p: + return X8 + Reg((x>>2)&((1<<3)-1)) + + case arg_fd_p, arg_fs2_p: + return F8 + Reg((x>>2)&((1<<3)-1)) + + case arg_rs1_p, arg_rd_rs1_p: + return X8 + Reg((x>>7)&((1<<3)-1)) + + case arg_rd_n0, arg_rs1_n0, arg_rd_rs1_n0, arg_c_rs1_n0: + if X0+Reg((x>>7)&((1<<5)-1)) == X0 { + return nil + } + return X0 + Reg((x>>7)&((1<<5)-1)) + + case arg_c_rs2_n0: + if X0+Reg((x>>2)&((1<<5)-1)) == X0 { + return nil + } + return X0 + Reg((x>>2)&((1<<5)-1)) + + case arg_c_fs2: + return F0 + Reg((x>>2)&((1<<5)-1)) + + case arg_c_rs2: + return X0 + Reg((x>>2)&((1<<5)-1)) + + case arg_rd_n2: + if X0+Reg((x>>7)&((1<<5)-1)) == X0 || X0+Reg((x>>7)&((1<<5)-1)) == X2 { + return nil + } + return X0 + Reg((x>>7)&((1<<5)-1)) + + case arg_c_imm6: + imm := (x<<25)>>27 | (x<<19)>>31<<5 + // Sign-extend + if imm>>uint32(6-1) == 1 { + imm |= 0x3ffffff << 6 + } + return Simm{int32(imm), true, 6} + + case arg_c_nzimm6: + imm := (x<<25)>>27 | (x<<19)>>31<<5 + // Sign-extend + if imm>>uint32(6-1) == 1 { + imm |= 0x3ffffff << 6 + } + if int32(imm) == 0 { + return nil + } + return Simm{int32(imm), true, 6} + + case arg_c_nzuimm6: + imm := (x<<25)>>27 | (x<<19)>>31<<5 + if int32(imm) == 0 { + return nil + } + return Uimm{imm, false} + + case arg_c_uimm7: + imm := (x<<26)>>31<<6 | (x<<25)>>31<<2 | (x<<19)>>29<<3 + return Uimm{imm, false} + + case arg_c_uimm8: + imm := (x<<25)>>30<<6 | (x<<19)>>29<<3 + return Uimm{imm, false} + + case arg_c_uimm8sp_s: + imm := (x<<23)>>30<<6 | (x<<19)>>28<<2 + return Uimm{imm, false} + + case arg_c_uimm8sp: + imm := (x<<25)>>29<<2 | (x<<19)>>31<<5 | (x<<28)>>30<<6 + return Uimm{imm, false} + + case arg_c_uimm9sp_s: + imm := (x<<22)>>29<<6 | (x<<19)>>29<<3 + return Uimm{imm, false} + + case arg_c_uimm9sp: + imm := (x<<25)>>30<<3 | (x<<19)>>31<<5 | (x<<27)>>29<<6 + return Uimm{imm, false} + + case arg_c_bimm9: + imm := (x<<29)>>31<<5 | (x<<27)>>30<<1 | (x<<25)>>30<<6 | (x<<19)>>31<<8 | (x<<20)>>30<<3 + // Sign-extend + if imm>>uint32(9-1) == 1 { + imm |= 0x7fffff << 9 + } + return Simm{int32(imm), true, 9} + + case arg_c_nzimm10: + imm := (x<<29)>>31<<5 | (x<<27)>>30<<7 | (x<<26)>>31<<6 | (x<<25)>>31<<4 | (x<<19)>>31<<9 + // Sign-extend + if imm>>uint32(10-1) == 1 { + imm |= 0x3fffff << 10 + } + if int32(imm) == 0 { + return nil + } + return Simm{int32(imm), true, 10} + + case arg_c_nzuimm10: + imm := (x<<26)>>31<<3 | (x<<25)>>31<<2 | (x<<21)>>28<<6 | (x<<19)>>30<<4 + if int32(imm) == 0 { + return nil + } + return Uimm{imm, false} + + case arg_c_imm12: + imm := (x<<29)>>31<<5 | (x<<26)>>28<<1 | (x<<25)>>31<<7 | (x<<24)>>31<<6 | (x<<23)>>31<<10 | (x<<21)>>30<<8 | (x<<20)>>31<<4 | (x<<19)>>31<<11 + // Sign-extend + if imm>>uint32(12-1) == 1 { + imm |= 0xfffff << 12 + } + return Simm{int32(imm), true, 12} + + case arg_c_nzimm18: + imm := (x<<25)>>27<<12 | (x<<19)>>31<<17 + // Sign-extend + if imm>>uint32(18-1) == 1 { + imm |= 0x3fff << 18 + } + if int32(imm) == 0 { + return nil + } + return Simm{int32(imm), true, 18} + + default: + return nil + } +} + +// convertCompressedIns rewrites the RVC Instruction to regular Instructions +func convertCompressedIns(f *instFormat, args Args) Args { + var newargs Args + switch f.op { + case C_ADDI4SPN: + f.op = ADDI + newargs[0] = args[0] + newargs[1] = Reg(X2) + newargs[2] = Simm{int32(args[1].(Uimm).Imm), true, 12} + + case C_LW: + f.op = LW + newargs[0] = args[0] + newargs[1] = RegOffset{args[1].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}} + + case C_SW: + f.op = SW + newargs[0] = args[1] + newargs[1] = RegOffset{args[0].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}} + + case C_NOP: + f.op = ADDI + newargs[0] = X0 + newargs[1] = X0 + newargs[2] = Simm{0, true, 12} + + case C_ADDI: + f.op = ADDI + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = Simm{args[1].(Simm).Imm, true, 12} + + case C_LI: + f.op = ADDI + newargs[0] = args[0] + newargs[1] = Reg(X0) + newargs[2] = Simm{args[1].(Simm).Imm, true, 12} + + case C_ADDI16SP: + f.op = ADDI + newargs[0] = Reg(X2) + newargs[1] = Reg(X2) + newargs[2] = Simm{args[0].(Simm).Imm, true, 12} + + case C_LUI: + f.op = LUI + newargs[0] = args[0] + newargs[1] = Uimm{uint32(args[1].(Simm).Imm >> 12), false} + + case C_ANDI: + f.op = ANDI + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = Simm{args[1].(Simm).Imm, true, 12} + + case C_SUB: + f.op = SUB + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_XOR: + f.op = XOR + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_OR: + f.op = OR + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_AND: + f.op = AND + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_J: + f.op = JAL + newargs[0] = Reg(X0) + newargs[1] = Simm{args[0].(Simm).Imm, true, 21} + + case C_BEQZ: + f.op = BEQ + newargs[0] = args[0] + newargs[1] = Reg(X0) + newargs[2] = Simm{args[1].(Simm).Imm, true, 13} + + case C_BNEZ: + f.op = BNE + newargs[0] = args[0] + newargs[1] = Reg(X0) + newargs[2] = Simm{args[1].(Simm).Imm, true, 13} + + case C_LWSP: + f.op = LW + newargs[0] = args[0] + newargs[1] = RegOffset{Reg(X2), Simm{int32(args[1].(Uimm).Imm), true, 12}} + + case C_JR: + f.op = JALR + newargs[0] = Reg(X0) + newargs[1] = RegOffset{args[0].(Reg), Simm{0, true, 12}} + + case C_MV: + f.op = ADD + newargs[0] = args[0] + newargs[1] = Reg(X0) + newargs[2] = args[1] + + case C_EBREAK: + f.op = EBREAK + + case C_JALR: + f.op = JALR + newargs[0] = Reg(X1) + newargs[1] = RegOffset{args[0].(Reg), Simm{0, true, 12}} + + case C_ADD: + f.op = ADD + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_SWSP: + f.op = SW + newargs[0] = args[0] + newargs[1] = RegOffset{Reg(X2), Simm{int32(args[1].(Uimm).Imm), true, 12}} + + // riscv64 compressed instructions + case C_LD: + f.op = LD + newargs[0] = args[0] + newargs[1] = RegOffset{args[1].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}} + + case C_SD: + f.op = SD + newargs[0] = args[1] + newargs[1] = RegOffset{args[0].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}} + + case C_ADDIW: + f.op = ADDIW + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = Simm{args[1].(Simm).Imm, true, 12} + + case C_SRLI: + f.op = SRLI + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_SRAI: + f.op = SRAI + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_SUBW: + f.op = SUBW + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_ADDW: + f.op = ADDW + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_SLLI: + f.op = SLLI + newargs[0] = args[0] + newargs[1] = args[0] + newargs[2] = args[1] + + case C_LDSP: + f.op = LD + newargs[0] = args[0] + newargs[1] = RegOffset{Reg(X2), Simm{int32(args[1].(Uimm).Imm), true, 12}} + + case C_SDSP: + f.op = SD + newargs[0] = args[0] + newargs[1] = RegOffset{Reg(X2), Simm{int32(args[1].(Uimm).Imm), true, 12}} + + // riscv double precision floating point compressed instructions + case C_FLD: + f.op = FLD + newargs[0] = args[0] + newargs[1] = RegOffset{args[1].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}} + + case C_FSD: + f.op = FSD + newargs[0] = args[1] + newargs[1] = RegOffset{args[0].(Reg), Simm{int32(args[2].(Uimm).Imm), true, 12}} + + case C_FLDSP: + f.op = FLD + newargs[0] = args[0] + newargs[1] = RegOffset{Reg(X2), Simm{int32(args[1].(Uimm).Imm), true, 12}} + + case C_FSDSP: + f.op = FSD + newargs[0] = args[0] + newargs[1] = RegOffset{Reg(X2), Simm{int32(args[1].(Uimm).Imm), true, 12}} + + case C_UNIMP: + f.op = CSRRW + newargs[0] = Reg(X0) + newargs[1] = CSR(CYCLE) + newargs[2] = Reg(X0) + } + return newargs +} diff --git a/riscv64/riscv64asm/decode_test.go b/riscv64/riscv64asm/decode_test.go new file mode 100644 index 00000000..1590aaac --- /dev/null +++ b/riscv64/riscv64asm/decode_test.go @@ -0,0 +1,80 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +import ( + "bufio" + "encoding/hex" + "os" + "path/filepath" + "strings" + "testing" +) + +func testDecode(t *testing.T, syntax string) { + input := filepath.Join("testdata", syntax+"cases.txt") + f, err := os.Open(input) + if err != nil { + t.Fatal(err) + } + defer f.Close() + scanner := bufio.NewScanner(f) + for scanner.Scan() { + line := strings.TrimSpace(scanner.Text()) + if line == "" || strings.HasPrefix(line, "#") { + continue + } + f := strings.SplitN(line, "\t", 2) + i := strings.Index(f[0], "|") + + if i < 0 { + t.Errorf("parsing %q: missing | separator", f[0]) + continue + } + if i%2 != 0 { + t.Errorf("parsing %q: misaligned | separator", f[0]) + } + code, err := hex.DecodeString(f[0][:i] + f[0][i+1:]) + if err != nil { + t.Errorf("parsing %q: %v", f[0], err) + continue + } + asm0 := strings.Replace(f[1], " ", " ", -1) + asm := strings.TrimSpace(asm0) + inst, decodeErr := Decode(code) + if decodeErr != nil && decodeErr != errUnknown { + if asm == "illegalins" && decodeErr == errShort { + continue + } + // Some rarely used system instructions are not supported + // Following logicals will filter such unknown instructions + t.Errorf("parsing %x: %s", code, decodeErr) + continue + } + + var out string + switch syntax { + case "gnu": + out = GNUSyntax(inst) + case "plan9": + out = GoSyntax(inst, 0, nil, nil) + default: + t.Errorf("unknown syntax %q", syntax) + continue + } + + if asm != out { + t.Errorf("Decode(%s) [%s] = %s want %s", f[0], syntax, out, asm) + } + } +} + +func TestDecodeGNUSyntax(t *testing.T) { + testDecode(t, "gnu") +} + +func TestDecodeGoSyntax(t *testing.T) { + testDecode(t, "plan9") +} diff --git a/riscv64/riscv64asm/ext_test.go b/riscv64/riscv64asm/ext_test.go new file mode 100644 index 00000000..556cd015 --- /dev/null +++ b/riscv64/riscv64asm/ext_test.go @@ -0,0 +1,333 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// Support for testing against external disassembler program. + +package riscv64asm + +import ( + "bufio" + "bytes" + "encoding/hex" + "flag" + "fmt" + "io" + "io/ioutil" + "log" + "math/rand" + "os" + "os/exec" + "path/filepath" + "strings" + "testing" + "time" +) + +var ( + dumpTest = flag.Bool("dump", false, "dump all encodings") + mismatch = flag.Bool("mismatch", false, "log allowed mismatches") + keep = flag.Bool("keep", false, "keep object files around") + debug = false +) + +// An ExtInst represents a single decoded instruction parsed +// from an external disassembler's output. +type ExtInst struct { + addr uint64 + enc [4]byte + nenc int + text string +} + +func (r ExtInst) String() string { + return fmt.Sprintf("%#x: % x: %s", r.addr, r.enc, r.text) +} + +// An ExtDis is a connection between an external disassembler and a test. +type ExtDis struct { + Dec chan ExtInst + File *os.File + Size int + Cmd *exec.Cmd +} + +// Run runs the given command - the external disassembler - and returns +// a buffered reader of its standard output. +func (ext *ExtDis) Run(cmd ...string) (*bufio.Reader, error) { + if *keep { + log.Printf("%s\n", strings.Join(cmd, " ")) + } + ext.Cmd = exec.Command(cmd[0], cmd[1:]...) + out, err := ext.Cmd.StdoutPipe() + if err != nil { + return nil, fmt.Errorf("stdoutpipe: %v", err) + } + if err := ext.Cmd.Start(); err != nil { + return nil, fmt.Errorf("exec: %v", err) + } + + b := bufio.NewReaderSize(out, 1<<20) + return b, nil +} + +// Wait waits for the command started with Run to exit. +func (ext *ExtDis) Wait() error { + return ext.Cmd.Wait() +} + +// testExtDis tests a set of byte sequences against an external disassembler. +// The disassembler is expected to produce the given syntax and run +// in the given architecture mode (16, 32, or 64-bit). +// The extdis function must start the external disassembler +// and then parse its output, sending the parsed instructions on ext.Dec. +// The generate function calls its argument f once for each byte sequence +// to be tested. The generate function itself will be called twice, and it must +// make the same sequence of calls to f each time. +// When a disassembly does not match the internal decoding, +// allowedMismatch determines whether this mismatch should be +// allowed, or else considered an error. +func testExtDis( + t *testing.T, + syntax string, + extdis func(ext *ExtDis) error, + generate func(f func([]byte)), + allowedMismatch func(text string, inst *Inst, dec ExtInst) bool, +) { + start := time.Now() + ext := &ExtDis{ + Dec: make(chan ExtInst), + } + errc := make(chan error) + + // First pass: write instructions to input file for external disassembler. + file, f, size, err := writeInst(generate) + if err != nil { + t.Fatal(err) + } + ext.Size = size + ext.File = f + defer func() { + f.Close() + if !*keep { + os.Remove(file) + } + }() + + // Second pass: compare disassembly against our decodings. + var ( + totalTests = 0 + totalSkips = 0 + totalErrors = 0 + + errors = make([]string, 0, 100) // Sampled errors, at most cap + ) + go func() { + errc <- extdis(ext) + }() + + generate(func(enc []byte) { + dec, ok := <-ext.Dec + if !ok { + t.Errorf("decoding stream ended early") + return + } + inst, text := disasm(syntax, pad(enc)) + + totalTests++ + if *dumpTest { + fmt.Printf("%x -> %s [%d]\n", enc, dec.text, dec.nenc) + } + + if text != dec.text && !strings.Contains(dec.text, "unknown") && syntax == "gnu" { + suffix := "" + if allowedMismatch(text, &inst, dec) { + totalSkips++ + if !*mismatch { + return + } + suffix += " (allowed mismatch)" + } + if strings.Contains(text, "unknown") && strings.Contains(dec.text, ".insn") { + return + } + totalErrors++ + cmp := fmt.Sprintf("decode(%x) = %q, %d, want %q, %d%s\n", enc, text, len(enc), dec.text, dec.nenc, suffix) + + if len(errors) >= cap(errors) { + j := rand.Intn(totalErrors) + if j >= cap(errors) { + return + } + errors = append(errors[:j], errors[j+1:]...) + } + errors = append(errors, cmp) + } + }) + + if *mismatch { + totalErrors -= totalSkips + } + + fmt.Printf("totalTest: %d total skip: %d total error: %d\n", totalTests, totalSkips, totalErrors) + // Here are some errors about mismatches(44) + for _, b := range errors { + t.Log(b) + } + + if totalErrors > 0 { + t.Fail() + } + t.Logf("%d test cases, %d expected mismatches, %d failures; %.0f cases/second", totalTests, totalSkips, totalErrors, float64(totalTests)/time.Since(start).Seconds()) + t.Logf("decoder coverage: %.1f%%;\n", decodeCoverage()) +} + +// Start address of text. +const start = 0x8000 + +// writeInst writes the generated byte sequences to a new file +// starting at offset start. That file is intended to be the input to +// the external disassembler. +func writeInst(generate func(func([]byte))) (file string, f *os.File, size int, err error) { + f, err = ioutil.TempFile("", "riscv64asm") + if err != nil { + return + } + + file = f.Name() + + f.Seek(start, io.SeekStart) + w := bufio.NewWriter(f) + defer w.Flush() + size = 0 + generate(func(x []byte) { + if debug { + fmt.Printf("%#x: %x%x\n", start+size, x, zeros[len(x):]) + } + w.Write(x) + w.Write(zeros[len(x):]) + size += len(zeros) + }) + return file, f, size, nil +} + +var zeros = []byte{0, 0, 0, 0} + +// pad pads the code sequence with pops. +func pad(enc []byte) []byte { + if len(enc) < 4 { + enc = append(enc[:len(enc):len(enc)], zeros[:4-len(enc)]...) + } + return enc +} + +// disasm returns the decoded instruction and text +// for the given source bytes, using the given syntax and mode. +func disasm(syntax string, src []byte) (inst Inst, text string) { + var err error + inst, err = Decode(src) + if err != nil { + text = "error: " + err.Error() + return + } + text = inst.String() + switch syntax { + case "gnu": + text = GNUSyntax(inst) + case "plan9": // [sic] + text = GoSyntax(inst, 0, nil, nil) + default: + text = "error: unknown syntax " + syntax + } + return +} + +// decodeCoverage returns a floating point number denoting the +// decoder coverage. +func decodeCoverage() float64 { + n := 0 + for _, t := range decoderCover { + if t { + n++ + } + } + return 100 * float64(1+n) / float64(1+len(decoderCover)) +} + +// Helpers for writing disassembler output parsers. + +// isHex reports whether b is a hexadecimal character (0-9a-fA-F). +func isHex(b byte) bool { + return ('0' <= b && b <= '9') || ('a' <= b && b <= 'f') || ('A' <= b && b <= 'F') +} + +// parseHex parses the hexadecimal byte dump in src, +// appending the parsed bytes to raw and returning the updated slice. +// The returned bool reports whether any invalid hex was found. +// Spaces and tabs between bytes are okay but any other non-hex is not. +func parseHex(src []byte, raw []byte) ([]byte, bool) { + src = bytes.TrimSpace(src) + raw, err := hex.AppendDecode(raw, src) + if err != nil { + return nil, false + } + return raw, true +} + +// Generators. +// +// The test cases are described as functions that invoke a callback repeatedly, +// with a new input sequence each time. These helpers make writing those +// a little easier. + +// hexCases generates the cases written in hexadecimal in the encoded string. +// Spaces in 'encoded' separate entire test cases, not individual bytes. +func hexCases(t *testing.T, encoded string) func(func([]byte)) { + return func(try func([]byte)) { + for _, x := range strings.Fields(encoded) { + src, err := hex.DecodeString(x) + if err != nil { + t.Errorf("parsing %q: %v", x, err) + } + try(src) + } + } +} + +// testdataCases generates the test cases recorded in testdata/cases.txt. +// It only uses the inputs; it ignores the answers recorded in that file. +func testdataCases(t *testing.T, syntax string) func(func([]byte)) { + var codes [][]byte + input := filepath.Join("testdata", syntax+"cases.txt") + data, err := ioutil.ReadFile(input) + if err != nil { + t.Fatal(err) + } + for _, line := range strings.Split(string(data), "\n") { + line = strings.TrimSpace(line) + if line == "" || strings.HasPrefix(line, "#") { + continue + } + f := strings.Fields(line)[0] + i := strings.Index(f, "|") + if i < 0 { + t.Errorf("parsing %q: missing | separator", f) + continue + } + if i%2 != 0 { + t.Errorf("parsing %q: misaligned | separator", f) + } + code, err := hex.DecodeString(f[:i] + f[i+1:]) + if err != nil { + t.Errorf("parsing %q: %v", f, err) + continue + } + codes = append(codes, code) + } + + return func(try func([]byte)) { + for _, code := range codes { + try(code) + } + } +} diff --git a/riscv64/riscv64asm/gnu.go b/riscv64/riscv64asm/gnu.go new file mode 100644 index 00000000..3ee04496 --- /dev/null +++ b/riscv64/riscv64asm/gnu.go @@ -0,0 +1,333 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +import ( + "strings" +) + +// GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. +// This form typically matches the syntax defined in the RISC-V Instruction Set Manual. See +// https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf +func GNUSyntax(inst Inst) string { + op := strings.ToLower(inst.Op.String()) + var args []string + for _, a := range inst.Args { + if a == nil { + break + } + args = append(args, strings.ToLower(a.String())) + } + + switch inst.Op { + case ADDI, ADDIW, ANDI, ORI, SLLI, SLLIW, SRAI, SRAIW, SRLI, SRLIW, XORI: + if inst.Op == ADDI { + if inst.Args[1].(Reg) == X0 && inst.Args[0].(Reg) != X0 { + op = "li" + args[1] = args[2] + args = args[:len(args)-1] + break + } + + if inst.Args[2].(Simm).Imm == 0 { + if inst.Args[0].(Reg) == X0 && inst.Args[1].(Reg) == X0 { + op = "nop" + args = nil + } else { + op = "mv" + args = args[:len(args)-1] + } + } + } + + if inst.Op == ANDI && inst.Args[2].(Simm).Imm == 255 { + op = "zext.b" + args = args[:len(args)-1] + } + + if inst.Op == ADDIW && inst.Args[2].(Simm).Imm == 0 { + op = "sext.w" + args = args[:len(args)-1] + } + + if inst.Op == XORI && inst.Args[2].(Simm).String() == "-1" { + op = "not" + args = args[:len(args)-1] + } + + case ADD: + if inst.Args[1].(Reg) == X0 { + op = "mv" + args[1] = args[2] + args = args[:len(args)-1] + } + + case BEQ: + if inst.Args[1].(Reg) == X0 { + op = "beqz" + args[1] = args[2] + args = args[:len(args)-1] + } + + case BGE: + if inst.Args[1].(Reg) == X0 { + op = "bgez" + args[1] = args[2] + args = args[:len(args)-1] + } else if inst.Args[0].(Reg) == X0 { + op = "blez" + args[0], args[1] = args[1], args[2] + args = args[:len(args)-1] + } + + case BLT: + if inst.Args[1].(Reg) == X0 { + op = "bltz" + args[1] = args[2] + args = args[:len(args)-1] + } else if inst.Args[0].(Reg) == X0 { + op = "bgtz" + args[0], args[1] = args[1], args[2] + args = args[:len(args)-1] + } + + case BNE: + if inst.Args[1].(Reg) == X0 { + op = "bnez" + args[1] = args[2] + args = args[:len(args)-1] + } + + case CSRRC: + if inst.Args[0].(Reg) == X0 { + op = "csrc" + args[0], args[1] = args[1], args[2] + args = args[:len(args)-1] + } + + case CSRRCI: + if inst.Args[0].(Reg) == X0 { + op = "csrci" + args[0], args[1] = args[1], args[2] + args = args[:len(args)-1] + } + + case CSRRS: + if inst.Args[2].(Reg) == X0 { + switch inst.Args[1].(CSR) { + case FCSR: + op = "frcsr" + args = args[:len(args)-2] + + case FFLAGS: + op = "frflags" + args = args[:len(args)-2] + + case FRM: + op = "frrm" + args = args[:len(args)-2] + + // rdcycleh, rdinstreth and rdtimeh are RV-32 only instructions. + // So not included there. + case CYCLE: + op = "rdcycle" + args = args[:len(args)-2] + + case INSTRET: + op = "rdinstret" + args = args[:len(args)-2] + + case TIME: + op = "rdtime" + args = args[:len(args)-2] + + default: + op = "csrr" + args = args[:len(args)-1] + } + } else if inst.Args[0].(Reg) == X0 { + op = "csrs" + args[0], args[1] = args[1], args[2] + args = args[:len(args)-1] + } + + case CSRRSI: + if inst.Args[0].(Reg) == X0 { + op = "csrsi" + args[0], args[1] = args[1], args[2] + args = args[:len(args)-1] + } + + case CSRRW: + switch inst.Args[1].(CSR) { + case FCSR: + op = "fscsr" + if inst.Args[0].(Reg) == X0 { + args[0] = args[2] + args = args[:len(args)-2] + } else { + args[1] = args[2] + args = args[:len(args)-1] + } + + case FFLAGS: + op = "fsflags" + if inst.Args[0].(Reg) == X0 { + args[0] = args[2] + args = args[:len(args)-2] + } else { + args[1] = args[2] + args = args[:len(args)-1] + } + + case FRM: + op = "fsrm" + if inst.Args[0].(Reg) == X0 { + args[0] = args[2] + args = args[:len(args)-2] + } else { + args[1] = args[2] + args = args[:len(args)-1] + } + + case CYCLE: + if inst.Args[0].(Reg) == X0 && inst.Args[2].(Reg) == X0 { + op = "unimp" + args = nil + } + + default: + if inst.Args[0].(Reg) == X0 { + op = "csrw" + args[0], args[1] = args[1], args[2] + args = args[:len(args)-1] + } + } + + case CSRRWI: + if inst.Args[0].(Reg) == X0 { + op = "csrwi" + args[0], args[1] = args[1], args[2] + args = args[:len(args)-1] + } + + // When both pred and succ equals to iorw, the GNU objdump will omit them. + case FENCE: + if inst.Args[0].(MemOrder).String() == "iorw" && + inst.Args[1].(MemOrder).String() == "iorw" { + args = nil + } + + case FSGNJX_D: + if inst.Args[1].(Reg) == inst.Args[2].(Reg) { + op = "fabs.d" + args = args[:len(args)-1] + } + + case FSGNJX_S: + if inst.Args[1].(Reg) == inst.Args[2].(Reg) { + op = "fabs.s" + args = args[:len(args)-1] + } + + case FSGNJ_D: + if inst.Args[1].(Reg) == inst.Args[2].(Reg) { + op = "fmv.d" + args = args[:len(args)-1] + } + + case FSGNJ_S: + if inst.Args[1].(Reg) == inst.Args[2].(Reg) { + op = "fmv.s" + args = args[:len(args)-1] + } + + case FSGNJN_D: + if inst.Args[1].(Reg) == inst.Args[2].(Reg) { + op = "fneg.d" + args = args[:len(args)-1] + } + + case FSGNJN_S: + if inst.Args[1].(Reg) == inst.Args[2].(Reg) { + op = "fneg.s" + args = args[:len(args)-1] + } + + case JAL: + if inst.Args[0].(Reg) == X0 { + op = "j" + args[0] = args[1] + args = args[:len(args)-1] + } else if inst.Args[0].(Reg) == X1 { + op = "jal" + args[0] = args[1] + args = args[:len(args)-1] + } + + case JALR: + if inst.Args[0].(Reg) == X1 && inst.Args[1].(RegOffset).Ofs.Imm == 0 { + args[0] = inst.Args[1].(RegOffset).OfsReg.String() + args = args[:len(args)-1] + } + + if inst.Args[0].(Reg) == X0 { + if inst.Args[1].(RegOffset).OfsReg == X1 && inst.Args[1].(RegOffset).Ofs.Imm == 0 { + op = "ret" + args = nil + } else if inst.Args[1].(RegOffset).Ofs.Imm == 0 { + op = "jr" + args[0] = inst.Args[1].(RegOffset).OfsReg.String() + args = args[:len(args)-1] + } else { + op = "jr" + args[0] = inst.Args[1].(RegOffset).String() + args = args[:len(args)-1] + } + } + + case SLTIU: + if inst.Args[2].(Simm).String() == "1" { + op = "seqz" + args = args[:len(args)-1] + } + + case SLT: + if inst.Args[1].(Reg) == X0 { + op = "sgtz" + args[1] = args[2] + args = args[:len(args)-1] + } else if inst.Args[2].(Reg) == X0 { + op = "sltz" + args = args[:len(args)-1] + } + + case SLTU: + if inst.Args[1].(Reg) == X0 { + op = "snez" + args[1] = args[2] + args = args[:len(args)-1] + } + + case SUB: + if inst.Args[1].(Reg) == X0 { + op = "neg" + args[1] = args[2] + args = args[:len(args)-1] + } + + case SUBW: + if inst.Args[1].(Reg) == X0 { + op = "negw" + args[1] = args[2] + args = args[:len(args)-1] + } + } + + if args != nil { + op += " " + strings.Join(args, ",") + } + return op +} diff --git a/riscv64/riscv64asm/inst.go b/riscv64/riscv64asm/inst.go new file mode 100644 index 00000000..3c13567c --- /dev/null +++ b/riscv64/riscv64asm/inst.go @@ -0,0 +1,495 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +import ( + "fmt" + "strings" +) + +// An Op is a RISC-V opcode. +type Op uint16 + +// NOTE: The actual Op values are defined in tables.go. +func (op Op) String() string { + if op >= Op(len(opstr)) || opstr[op] == "" { + return fmt.Sprintf("Op(%d)", op) + } + + return opstr[op] +} + +// An Arg is a single instruction argument. +type Arg interface { + String() string +} + +// An Args holds the instruction arguments. +// If an instruction has fewer than 6 arguments, +// the final elements in the array are nil. +type Args [6]Arg + +// An Inst is a single instruction. +type Inst struct { + Op Op // Opcode mnemonic. + Enc uint32 // Raw encoding bits. + Args Args // Instruction arguments, in RISC-V mamual order. + Len int // Length of encoded instruction in bytes +} + +func (i Inst) String() string { + var args []string + for _, arg := range i.Args { + if arg == nil { + break + } + args = append(args, arg.String()) + } + + if len(args) == 0 { + return i.Op.String() + } + return i.Op.String() + " " + strings.Join(args, ",") +} + +// A Reg is a single register. +// The zero value denotes X0, not the absence of a register. +type Reg uint16 + +const ( + // General-purpose register + X0 Reg = iota + X1 + X2 + X3 + X4 + X5 + X6 + X7 + X8 + X9 + X10 + X11 + X12 + X13 + X14 + X15 + X16 + X17 + X18 + X19 + X20 + X21 + X22 + X23 + X24 + X25 + X26 + X27 + X28 + X29 + X30 + X31 + + //Float point register + F0 + F1 + F2 + F3 + F4 + F5 + F6 + F7 + F8 + F9 + F10 + F11 + F12 + F13 + F14 + F15 + F16 + F17 + F18 + F19 + F20 + F21 + F22 + F23 + F24 + F25 + F26 + F27 + F28 + F29 + F30 + F31 +) + +func (r Reg) String() string { + switch { + case r >= X0 && r <= X31: + return fmt.Sprintf("x%d", r) + + case r >= F0 && r <= F31: + return fmt.Sprintf("f%d", r-F0) + + default: + return fmt.Sprintf("Unknown(%d)", r) + } +} + +// A CSR is a single control and status register. +// Use stringer to generate CSR match table. +// +//go:generate stringer -type=CSR +type CSR uint16 + +const ( + // Control status register + USTATUS CSR = 0x0000 + FFLAGS CSR = 0x0001 + FRM CSR = 0x0002 + FCSR CSR = 0x0003 + UIE CSR = 0x0004 + UTVEC CSR = 0x0005 + UTVT CSR = 0x0007 + VSTART CSR = 0x0008 + VXSAT CSR = 0x0009 + VXRM CSR = 0x000a + VCSR CSR = 0x000f + USCRATCH CSR = 0x0040 + UEPC CSR = 0x0041 + UCAUSE CSR = 0x0042 + UTVAL CSR = 0x0043 + UIP CSR = 0x0044 + UNXTI CSR = 0x0045 + UINTSTATUS CSR = 0x0046 + USCRATCHCSW CSR = 0x0048 + USCRATCHCSWL CSR = 0x0049 + SSTATUS CSR = 0x0100 + SEDELEG CSR = 0x0102 + SIDELEG CSR = 0x0103 + SIE CSR = 0x0104 + STVEC CSR = 0x0105 + SCOUNTEREN CSR = 0x0106 + STVT CSR = 0x0107 + SSCRATCH CSR = 0x0140 + SEPC CSR = 0x0141 + SCAUSE CSR = 0x0142 + STVAL CSR = 0x0143 + SIP CSR = 0x0144 + SNXTI CSR = 0x0145 + SINTSTATUS CSR = 0x0146 + SSCRATCHCSW CSR = 0x0148 + SSCRATCHCSWL CSR = 0x0149 + SATP CSR = 0x0180 + VSSTATUS CSR = 0x0200 + VSIE CSR = 0x0204 + VSTVEC CSR = 0x0205 + VSSCRATCH CSR = 0x0240 + VSEPC CSR = 0x0241 + VSCAUSE CSR = 0x0242 + VSTVAL CSR = 0x0243 + VSIP CSR = 0x0244 + VSATP CSR = 0x0280 + MSTATUS CSR = 0x0300 + MISA CSR = 0x0301 + MEDELEG CSR = 0x0302 + MIDELEG CSR = 0x0303 + MIE CSR = 0x0304 + MTVEC CSR = 0x0305 + MCOUNTEREN CSR = 0x0306 + MTVT CSR = 0x0307 + MSTATUSH CSR = 0x0310 + MCOUNTINHIBIT CSR = 0x0320 + MHPMEVENT3 CSR = 0x0323 + MHPMEVENT4 CSR = 0x0324 + MHPMEVENT5 CSR = 0x0325 + MHPMEVENT6 CSR = 0x0326 + MHPMEVENT7 CSR = 0x0327 + MHPMEVENT8 CSR = 0x0328 + MHPMEVENT9 CSR = 0x0329 + MHPMEVENT10 CSR = 0x032a + MHPMEVENT11 CSR = 0x032b + MHPMEVENT12 CSR = 0x032c + MHPMEVENT13 CSR = 0x032d + MHPMEVENT14 CSR = 0x032e + MHPMEVENT15 CSR = 0x032f + MHPMEVENT16 CSR = 0x0330 + MHPMEVENT17 CSR = 0x0331 + MHPMEVENT18 CSR = 0x0332 + MHPMEVENT19 CSR = 0x0333 + MHPMEVENT20 CSR = 0x0334 + MHPMEVENT21 CSR = 0x0335 + MHPMEVENT22 CSR = 0x0336 + MHPMEVENT23 CSR = 0x0337 + MHPMEVENT24 CSR = 0x0338 + MHPMEVENT25 CSR = 0x0339 + MHPMEVENT26 CSR = 0x033a + MHPMEVENT27 CSR = 0x033b + MHPMEVENT28 CSR = 0x033c + MHPMEVENT29 CSR = 0x033d + MHPMEVENT30 CSR = 0x033e + MHPMEVENT31 CSR = 0x033f + MSCRATCH CSR = 0x0340 + MEPC CSR = 0x0341 + MCAUSE CSR = 0x0342 + MTVAL CSR = 0x0343 + MIP CSR = 0x0344 + MNXTI CSR = 0x0345 + MINTSTATUS CSR = 0x0346 + MSCRATCHCSW CSR = 0x0348 + MSCRATCHCSWL CSR = 0x0349 + MTINST CSR = 0x034a + MTVAL2 CSR = 0x034b + PMPCFG0 CSR = 0x03a0 + PMPCFG1 CSR = 0x03a1 + PMPCFG2 CSR = 0x03a2 + PMPCFG3 CSR = 0x03a3 + PMPADDR0 CSR = 0x03b0 + PMPADDR1 CSR = 0x03b1 + PMPADDR2 CSR = 0x03b2 + PMPADDR3 CSR = 0x03b3 + PMPADDR4 CSR = 0x03b4 + PMPADDR5 CSR = 0x03b5 + PMPADDR6 CSR = 0x03b6 + PMPADDR7 CSR = 0x03b7 + PMPADDR8 CSR = 0x03b8 + PMPADDR9 CSR = 0x03b9 + PMPADDR10 CSR = 0x03ba + PMPADDR11 CSR = 0x03bb + PMPADDR12 CSR = 0x03bc + PMPADDR13 CSR = 0x03bd + PMPADDR14 CSR = 0x03be + PMPADDR15 CSR = 0x03bf + HSTATUS CSR = 0x0600 + HEDELEG CSR = 0x0602 + HIDELEG CSR = 0x0603 + HIE CSR = 0x0604 + HTIMEDELTA CSR = 0x0605 + HCOUNTEREN CSR = 0x0606 + HGEIE CSR = 0x0607 + HTIMEDELTAH CSR = 0x0615 + HTVAL CSR = 0x0643 + HIP CSR = 0x0644 + HVIP CSR = 0x0645 + HTINST CSR = 0x064a + HGATP CSR = 0x0680 + TSELECT CSR = 0x07a0 + TDATA1 CSR = 0x07a1 + TDATA2 CSR = 0x07a2 + TDATA3 CSR = 0x07a3 + TINFO CSR = 0x07a4 + TCONTROL CSR = 0x07a5 + MCONTEXT CSR = 0x07a8 + MNOISE CSR = 0x07a9 + SCONTEXT CSR = 0x07aa + DCSR CSR = 0x07b0 + DPC CSR = 0x07b1 + DSCRATCH0 CSR = 0x07b2 + DSCRATCH1 CSR = 0x07b3 + MCYCLE CSR = 0x0b00 + MINSTRET CSR = 0x0b02 + MHPMCOUNTER3 CSR = 0x0b03 + MHPMCOUNTER4 CSR = 0x0b04 + MHPMCOUNTER5 CSR = 0x0b05 + MHPMCOUNTER6 CSR = 0x0b06 + MHPMCOUNTER7 CSR = 0x0b07 + MHPMCOUNTER8 CSR = 0x0b08 + MHPMCOUNTER9 CSR = 0x0b09 + MHPMCOUNTER10 CSR = 0x0b0a + MHPMCOUNTER11 CSR = 0x0b0b + MHPMCOUNTER12 CSR = 0x0b0c + MHPMCOUNTER13 CSR = 0x0b0d + MHPMCOUNTER14 CSR = 0x0b0e + MHPMCOUNTER15 CSR = 0x0b0f + MHPMCOUNTER16 CSR = 0x0b10 + MHPMCOUNTER17 CSR = 0x0b11 + MHPMCOUNTER18 CSR = 0x0b12 + MHPMCOUNTER19 CSR = 0x0b13 + MHPMCOUNTER20 CSR = 0x0b14 + MHPMCOUNTER21 CSR = 0x0b15 + MHPMCOUNTER22 CSR = 0x0b16 + MHPMCOUNTER23 CSR = 0x0b17 + MHPMCOUNTER24 CSR = 0x0b18 + MHPMCOUNTER25 CSR = 0x0b19 + MHPMCOUNTER26 CSR = 0x0b1a + MHPMCOUNTER27 CSR = 0x0b1b + MHPMCOUNTER28 CSR = 0x0b1c + MHPMCOUNTER29 CSR = 0x0b1d + MHPMCOUNTER30 CSR = 0x0b1e + MHPMCOUNTER31 CSR = 0x0b1f + MCYCLEH CSR = 0x0b80 + MINSTRETH CSR = 0x0b82 + MHPMCOUNTER3H CSR = 0x0b83 + MHPMCOUNTER4H CSR = 0x0b84 + MHPMCOUNTER5H CSR = 0x0b85 + MHPMCOUNTER6H CSR = 0x0b86 + MHPMCOUNTER7H CSR = 0x0b87 + MHPMCOUNTER8H CSR = 0x0b88 + MHPMCOUNTER9H CSR = 0x0b89 + MHPMCOUNTER10H CSR = 0x0b8a + MHPMCOUNTER11H CSR = 0x0b8b + MHPMCOUNTER12H CSR = 0x0b8c + MHPMCOUNTER13H CSR = 0x0b8d + MHPMCOUNTER14H CSR = 0x0b8e + MHPMCOUNTER15H CSR = 0x0b8f + MHPMCOUNTER16H CSR = 0x0b90 + MHPMCOUNTER17H CSR = 0x0b91 + MHPMCOUNTER18H CSR = 0x0b92 + MHPMCOUNTER19H CSR = 0x0b93 + MHPMCOUNTER20H CSR = 0x0b94 + MHPMCOUNTER21H CSR = 0x0b95 + MHPMCOUNTER22H CSR = 0x0b96 + MHPMCOUNTER23H CSR = 0x0b97 + MHPMCOUNTER24H CSR = 0x0b98 + MHPMCOUNTER25H CSR = 0x0b99 + MHPMCOUNTER26H CSR = 0x0b9a + MHPMCOUNTER27H CSR = 0x0b9b + MHPMCOUNTER28H CSR = 0x0b9c + MHPMCOUNTER29H CSR = 0x0b9d + MHPMCOUNTER30H CSR = 0x0b9e + MHPMCOUNTER31H CSR = 0x0b9f + CYCLE CSR = 0x0c00 + TIME CSR = 0x0c01 + INSTRET CSR = 0x0c02 + HPMCOUNTER3 CSR = 0x0c03 + HPMCOUNTER4 CSR = 0x0c04 + HPMCOUNTER5 CSR = 0x0c05 + HPMCOUNTER6 CSR = 0x0c06 + HPMCOUNTER7 CSR = 0x0c07 + HPMCOUNTER8 CSR = 0x0c08 + HPMCOUNTER9 CSR = 0x0c09 + HPMCOUNTER10 CSR = 0x0c0a + HPMCOUNTER11 CSR = 0x0c0b + HPMCOUNTER12 CSR = 0x0c0c + HPMCOUNTER13 CSR = 0x0c0d + HPMCOUNTER14 CSR = 0x0c0e + HPMCOUNTER15 CSR = 0x0c0f + HPMCOUNTER16 CSR = 0x0c10 + HPMCOUNTER17 CSR = 0x0c11 + HPMCOUNTER18 CSR = 0x0c12 + HPMCOUNTER19 CSR = 0x0c13 + HPMCOUNTER20 CSR = 0x0c14 + HPMCOUNTER21 CSR = 0x0c15 + HPMCOUNTER22 CSR = 0x0c16 + HPMCOUNTER23 CSR = 0x0c17 + HPMCOUNTER24 CSR = 0x0c18 + HPMCOUNTER25 CSR = 0x0c19 + HPMCOUNTER26 CSR = 0x0c1a + HPMCOUNTER27 CSR = 0x0c1b + HPMCOUNTER28 CSR = 0x0c1c + HPMCOUNTER29 CSR = 0x0c1d + HPMCOUNTER30 CSR = 0x0c1e + HPMCOUNTER31 CSR = 0x0c1f + VL CSR = 0x0c20 + VTYPE CSR = 0x0c21 + VLENB CSR = 0x0c22 + CYCLEH CSR = 0x0c80 + TIMEH CSR = 0x0c81 + INSTRETH CSR = 0x0c82 + HPMCOUNTER3H CSR = 0x0c83 + HPMCOUNTER4H CSR = 0x0c84 + HPMCOUNTER5H CSR = 0x0c85 + HPMCOUNTER6H CSR = 0x0c86 + HPMCOUNTER7H CSR = 0x0c87 + HPMCOUNTER8H CSR = 0x0c88 + HPMCOUNTER9H CSR = 0x0c89 + HPMCOUNTER10H CSR = 0x0c8a + HPMCOUNTER11H CSR = 0x0c8b + HPMCOUNTER12H CSR = 0x0c8c + HPMCOUNTER13H CSR = 0x0c8d + HPMCOUNTER14H CSR = 0x0c8e + HPMCOUNTER15H CSR = 0x0c8f + HPMCOUNTER16H CSR = 0x0c90 + HPMCOUNTER17H CSR = 0x0c91 + HPMCOUNTER18H CSR = 0x0c92 + HPMCOUNTER19H CSR = 0x0c93 + HPMCOUNTER20H CSR = 0x0c94 + HPMCOUNTER21H CSR = 0x0c95 + HPMCOUNTER22H CSR = 0x0c96 + HPMCOUNTER23H CSR = 0x0c97 + HPMCOUNTER24H CSR = 0x0c98 + HPMCOUNTER25H CSR = 0x0c99 + HPMCOUNTER26H CSR = 0x0c9a + HPMCOUNTER27H CSR = 0x0c9b + HPMCOUNTER28H CSR = 0x0c9c + HPMCOUNTER29H CSR = 0x0c9d + HPMCOUNTER30H CSR = 0x0c9e + HPMCOUNTER31H CSR = 0x0c9f + HGEIP CSR = 0x0e12 + MVENDORID CSR = 0x0f11 + MARCHID CSR = 0x0f12 + MIMPID CSR = 0x0f13 + MHARTID CSR = 0x0f14 + MENTROPY CSR = 0x0f15 +) + +// An Uimm is an unsigned immediate number +type Uimm struct { + Imm uint32 // 32-bit unsigned integer + Decimal bool // Print format of the immediate, either decimal or hexadecimal +} + +func (ui Uimm) String() string { + if ui.Decimal { + return fmt.Sprintf("%d", ui.Imm) + } + return fmt.Sprintf("%#x", ui.Imm) +} + +// A Simm is a signed immediate number +type Simm struct { + Imm int32 // 32-bit signed integer + Decimal bool // Print format of the immediate, either decimal or hexadecimal + Width uint8 // Actual width of the Simm +} + +func (si Simm) String() string { + if si.Decimal { + return fmt.Sprintf("%d", si.Imm) + } + return fmt.Sprintf("%#x", si.Imm) +} + +// An AmoReg is an atomic address register used in AMO instructions +type AmoReg struct { + reg Reg // Avoid promoted String method +} + +func (amoReg AmoReg) String() string { + return fmt.Sprintf("(%s)", amoReg.reg) +} + +// A RegOffset is a register with offset value +type RegOffset struct { + OfsReg Reg + Ofs Simm +} + +func (regofs RegOffset) String() string { + return fmt.Sprintf("%s(%s)", regofs.Ofs, regofs.OfsReg) +} + +// A MemOrder is a memory order hint in fence instruction +type MemOrder uint8 + +func (memOrder MemOrder) String() string { + var str string + if memOrder<<7>>7 == 1 { + str += "i" + } + if memOrder>>1<<7>>7 == 1 { + str += "o" + } + if memOrder>>2<<7>>7 == 1 { + str += "r" + } + if memOrder>>3<<7>>7 == 1 { + str += "w" + } + return str +} diff --git a/riscv64/riscv64asm/objdump_test.go b/riscv64/riscv64asm/objdump_test.go new file mode 100644 index 00000000..479301bb --- /dev/null +++ b/riscv64/riscv64asm/objdump_test.go @@ -0,0 +1,86 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +import ( + "strings" + "testing" +) + +func TestObjdumpRISCV64TestDecodeGNUSyntaxdata(t *testing.T) { + testObjdumpRISCV64(t, testdataCases(t, "gnu")) +} +func TestObjdumpRISCV64TestDecodeGoSyntaxdata(t *testing.T) { + testObjdumpRISCV64(t, testdataCases(t, "plan9")) +} + +func TestObjdumpRISCV64Manual(t *testing.T) { + testObjdumpRISCV64(t, hexCases(t, objdumpManualTests)) +} + +// objdumpManualTests holds test cases that will be run by TestObjdumpRISCV64Manual. +// If you are debugging a few cases that turned up in a longer run, it can be useful +// to list them here and then use -run=Manual, particularly with tracing enabled. +// Note that these are byte sequences, so they must be reversed from the usual +// word presentation. +var objdumpManualTests = ` +93020300 +13000000 +9b020300 +afb5b50e +73b012c0 +73f01fc0 +73a012c0 +73e01fc0 +f3223000 +f3221000 +f3222000 +f3123300 +f3121300 +f3122300 +739012c0 +73d01fc0 +53a01022 +53a01020 +53801022 +53801020 +53901022 +53901020 +67800000 +67800200 +b3026040 +bb026040 +9342f3ff +f32200c0 +f32200c8 +f32220c0 +f32220c8 +f32210c0 +f32210c8 +` + +// allowedMismatchObjdump reports whether the mismatch between text and dec +// should be allowed by the test. +func allowedMismatchObjdump(text string, inst *Inst, dec ExtInst) bool { + // Allow the mismatch of Branch/Jump instruction's offset. + decsp := strings.Split(dec.text, ",") + + switch inst.Op { + case BEQ, BGE, BGEU, BLT, BLTU, BNE: + if inst.Args[2].(Simm).String() != decsp[len(decsp)-1] { + return true + } + case JAL: + if inst.Args[1].(Simm).String() != decsp[len(decsp)-1] { + return true + } + case JALR: + if inst.Args[1].(RegOffset).Ofs.String() != decsp[len(decsp)-1] { + return true + } + } + + return false +} diff --git a/riscv64/riscv64asm/objdumpext_test.go b/riscv64/riscv64asm/objdumpext_test.go new file mode 100644 index 00000000..1dc09641 --- /dev/null +++ b/riscv64/riscv64asm/objdumpext_test.go @@ -0,0 +1,299 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +import ( + "bytes" + "debug/elf" + "encoding/binary" + "fmt" + "io" + "log" + "os" + "os/exec" + "strconv" + "strings" + "testing" +) + +var objdumpPath = "riscv64-linux-gnu-objdump" + +func testObjdumpRISCV64(t *testing.T, generate func(func([]byte))) { + testObjdumpArch(t, generate) +} + +func testObjdumpArch(t *testing.T, generate func(func([]byte))) { + checkObjdumpRISCV64(t) + testExtDis(t, "gnu", objdump, generate, allowedMismatchObjdump) + testExtDis(t, "plan9", objdump, generate, allowedMismatchObjdump) +} + +func checkObjdumpRISCV64(t *testing.T) { + objdumpPath, err := exec.LookPath(objdumpPath) + if err != nil { + objdumpPath = "objdump" + } + out, err := exec.Command(objdumpPath, "-i").Output() + if err != nil { + t.Skipf("cannot run objdump: %v\n%s", err, out) + } + if !strings.Contains(string(out), "riscv") { + t.Skip("objdump does not have RISC-V support") + } +} + +func objdump(ext *ExtDis) error { + // File already written with instructions; add ELF header. + if err := writeELF64(ext.File, ext.Size); err != nil { + return err + } + + b, err := ext.Run(objdumpPath, "-M numeric", "-d", "-z", ext.File.Name()) + if err != nil { + return err + } + + var ( + nmatch int + reading bool + next uint64 = start + addr uint64 + encbuf [4]byte + enc []byte + text string + ) + flush := func() { + if addr == next { + // PC-relative addresses are translated to absolute addresses based on PC by GNU objdump + // Following logical rewrites the absolute addresses back to PC-relative ones for comparing + // with our disassembler output which are PC-relative + if text == "undefined" && len(enc) == 4 { + text = "error: unknown instruction" + enc = nil + } + if len(enc) == 4 { + // prints as word but we want to record bytes + enc[0], enc[3] = enc[3], enc[0] + enc[1], enc[2] = enc[2], enc[1] + } + ext.Dec <- ExtInst{addr, encbuf, len(enc), text} + encbuf = [4]byte{} + enc = nil + next += 4 + } + } + var textangle = []byte("<.text>:") + for { + line, err := b.ReadSlice('\n') + if err != nil { + if err == io.EOF { + break + } + return fmt.Errorf("reading objdump output: %v", err) + } + if bytes.Contains(line, textangle) { + reading = true + continue + } + if !reading { + continue + } + if debug { + os.Stdout.Write(line) + } + if enc1 := parseContinuation(line, encbuf[:len(enc)]); enc1 != nil { + enc = enc1 + continue + } + flush() + nmatch++ + addr, enc, text = parseLine(line, encbuf[:0]) + if addr > next { + return fmt.Errorf("address out of sync expected <= %#x at %q in:\n%s", next, line, line) + } + } + flush() + if next != start+uint64(ext.Size) { + return fmt.Errorf("not enough results found [%d %d]", next, start+ext.Size) + } + if err := ext.Wait(); err != nil { + return fmt.Errorf("exec: %v", err) + } + + return nil +} + +var ( + undefined = []byte("undefined") + unpredictable = []byte("unpredictable") + slashslash = []byte("//") +) + +func parseLine(line []byte, encstart []byte) (addr uint64, enc []byte, text string) { + ok := false + oline := line + i := bytes.Index(line, []byte(":\t")) + if i < 0 { + log.Fatalf("cannot parse disassembly: %q", oline) + } + x, err := strconv.ParseUint(string(bytes.TrimSpace(line[:i])), 16, 32) + if err != nil { + log.Fatalf("cannot parse disassembly: %q", oline) + } + addr = uint64(x) + line = line[i+2:] + i = bytes.IndexByte(line, '\t') + if i < 0 { + log.Fatalf("cannot parse disassembly: %q", oline) + } + enc, ok = parseHex(line[:i], encstart) + if !ok { + log.Fatalf("cannot parse disassembly: %q", oline) + } + line = bytes.TrimSpace(line[i:]) + if bytes.Contains(line, undefined) { + text = "undefined" + return + } + if false && bytes.Contains(line, unpredictable) { + text = "unpredictable" + return + } + // Strip trailing comment starting with '#' + if i := bytes.IndexByte(line, '#'); i >= 0 { + line = bytes.TrimSpace(line[:i]) + } + // Strip trailing comment starting with "//" + if i := bytes.Index(line, slashslash); i >= 0 { + line = bytes.TrimSpace(line[:i]) + } + text = string(fixSpace(line)) + return +} + +// fixSpace rewrites runs of spaces, tabs, and newline characters into single spaces in s. +// If s must be rewritten, it is rewritten in place. +func fixSpace(s []byte) []byte { + s = bytes.TrimSpace(s) + for i := 0; i < len(s); i++ { + if s[i] == '\t' || s[i] == '\n' || i > 0 && s[i] == ' ' && s[i-1] == ' ' { + goto Fix + } + } + return s + +Fix: + b := s + w := 0 + for i := 0; i < len(s); i++ { + c := s[i] + if c == '\t' || c == '\n' { + c = ' ' + } + if c == ' ' && w > 0 && b[w-1] == ' ' { + continue + } + b[w] = c + w++ + } + if w > 0 && b[w-1] == ' ' { + w-- + } + return b[:w] +} + +func parseContinuation(line []byte, enc []byte) []byte { + i := bytes.Index(line, []byte(":\t")) + if i < 0 { + return nil + } + line = line[i+1:] + enc, _ = parseHex(line, enc) + return enc +} + +// writeELF64 writes an ELF64 header to the file, describing a text +// segment that starts at start (0x8000) and extends for size bytes. +func writeELF64(f *os.File, size int) error { + f.Seek(0, io.SeekStart) + var hdr elf.Header64 + var prog elf.Prog64 + var sect elf.Section64 + var buf bytes.Buffer + binary.Write(&buf, binary.LittleEndian, &hdr) + off1 := buf.Len() + binary.Write(&buf, binary.LittleEndian, &prog) + off2 := buf.Len() + binary.Write(&buf, binary.LittleEndian, §) + off3 := buf.Len() + buf.Reset() + data := byte(elf.ELFDATA2LSB) + hdr = elf.Header64{ + Ident: [16]byte{0x7F, 'E', 'L', 'F', 2, data, 1}, + Type: 2, + Machine: uint16(elf.EM_RISCV), + Version: 1, + Entry: start, + Phoff: uint64(off1), + Shoff: uint64(off2), + Flags: 0x5, + Ehsize: uint16(off1), + Phentsize: uint16(off2 - off1), + Phnum: 1, + Shentsize: uint16(off3 - off2), + Shnum: 4, + Shstrndx: 3, + } + binary.Write(&buf, binary.LittleEndian, &hdr) + prog = elf.Prog64{ + Type: 1, + Off: start, + Vaddr: start, + Paddr: start, + Filesz: uint64(size), + Memsz: uint64(size), + Flags: 5, + Align: start, + } + binary.Write(&buf, binary.LittleEndian, &prog) + binary.Write(&buf, binary.LittleEndian, §) // NULL section + sect = elf.Section64{ + Name: 1, + Type: uint32(elf.SHT_PROGBITS), + Addr: start, + Off: start, + Size: uint64(size), + Flags: uint64(elf.SHF_ALLOC | elf.SHF_EXECINSTR), + Addralign: 4, + } + binary.Write(&buf, binary.LittleEndian, §) // .text + strtabsize := len("\x00.text\x00.riscv.attributes\x00.shstrtab\x00") + // RISC-V objdump needs the .riscv.attributes section to identify + // the RV64G (not include compressed) extensions. + sect = elf.Section64{ + Name: uint32(len("\x00.text\x00")), + Type: uint32(0x70000003), // SHT_RISCV_ATTRIBUTES + Addr: 0, + Off: uint64(off2 + (off3-off2)*4 + strtabsize), + Size: 114, + Addralign: 1, + } + binary.Write(&buf, binary.LittleEndian, §) + sect = elf.Section64{ + Name: uint32(len("\x00.text\x00.riscv.attributes\x00")), + Type: uint32(elf.SHT_STRTAB), + Addr: 0, + Off: uint64(off2 + (off3-off2)*4), + Size: uint64(strtabsize), + Addralign: 1, + } + binary.Write(&buf, binary.LittleEndian, §) + buf.WriteString("\x00.text\x00.riscv.attributes\x00.shstrtab\x00") + // Contents of .riscv.attributes section + // which specify the extension and priv spec version. (1.11) + buf.WriteString("Aq\x00\x00\x00riscv\x00\x01g\x00\x00\x00\x05rv64i2p0_m2p0_a2p0_f2p0_d2p0_q2p0_c2p0_zmmul1p0_zfh1p0_zfhmin1p0_zba1p0_zbb1p0_zbc1p0_zbs1p0\x00\x08\x01\x0a\x0b") + f.Write(buf.Bytes()) + return nil +} diff --git a/riscv64/riscv64asm/plan9x.go b/riscv64/riscv64asm/plan9x.go new file mode 100644 index 00000000..367122d9 --- /dev/null +++ b/riscv64/riscv64asm/plan9x.go @@ -0,0 +1,377 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +import ( + "fmt" + "io" + "strconv" + "strings" +) + +// GoSyntax returns the Go assembler syntax for the instruction. +// The syntax was originally defined by Plan 9. +// The pc is the program counter of the instruction, used for +// expanding PC-relative addresses into absolute ones. +// The symname function queries the symbol table for the program +// being disassembled. Given a target address it returns the name +// and base address of the symbol containing the target, if any; +// otherwise it returns "", 0. +// The reader text should read from the text segment using text addresses +// as offsets; it is used to display pc-relative loads as constant loads. +func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64), text io.ReaderAt) string { + if symname == nil { + symname = func(uint64) (string, uint64) { return "", 0 } + } + + var args []string + for _, a := range inst.Args { + if a == nil { + break + } + args = append(args, plan9Arg(&inst, pc, symname, a)) + } + + op := inst.Op.String() + + switch inst.Op { + + case AMOADD_D, AMOADD_D_AQ, AMOADD_D_RL, AMOADD_D_AQRL, AMOADD_W, AMOADD_W_AQ, + AMOADD_W_RL, AMOADD_W_AQRL, AMOAND_D, AMOAND_D_AQ, AMOAND_D_RL, AMOAND_D_AQRL, + AMOAND_W, AMOAND_W_AQ, AMOAND_W_RL, AMOAND_W_AQRL, AMOMAXU_D, AMOMAXU_D_AQ, + AMOMAXU_D_RL, AMOMAXU_D_AQRL, AMOMAXU_W, AMOMAXU_W_AQ, AMOMAXU_W_RL, AMOMAXU_W_AQRL, + AMOMAX_D, AMOMAX_D_AQ, AMOMAX_D_RL, AMOMAX_D_AQRL, AMOMAX_W, AMOMAX_W_AQ, AMOMAX_W_RL, + AMOMAX_W_AQRL, AMOMINU_D, AMOMINU_D_AQ, AMOMINU_D_RL, AMOMINU_D_AQRL, AMOMINU_W, + AMOMINU_W_AQ, AMOMINU_W_RL, AMOMINU_W_AQRL, AMOMIN_D, AMOMIN_D_AQ, AMOMIN_D_RL, + AMOMIN_D_AQRL, AMOMIN_W, AMOMIN_W_AQ, AMOMIN_W_RL, AMOMIN_W_AQRL, AMOOR_D, AMOOR_D_AQ, + AMOOR_D_RL, AMOOR_D_AQRL, AMOOR_W, AMOOR_W_AQ, AMOOR_W_RL, AMOOR_W_AQRL, AMOSWAP_D, + AMOSWAP_D_AQ, AMOSWAP_D_RL, AMOSWAP_D_AQRL, AMOSWAP_W, AMOSWAP_W_AQ, AMOSWAP_W_RL, + AMOSWAP_W_AQRL, AMOXOR_D, AMOXOR_D_AQ, AMOXOR_D_RL, AMOXOR_D_AQRL, AMOXOR_W, + AMOXOR_W_AQ, AMOXOR_W_RL, AMOXOR_W_AQRL, SC_D, SC_D_AQ, SC_D_RL, SC_D_AQRL, + SC_W, SC_W_AQ, SC_W_RL, SC_W_AQRL: + // Atomic instructions have special operand order. + args[2], args[1] = args[1], args[2] + + case ADDI: + if inst.Args[2].(Simm).Imm == 0 { + op = "MOV" + args = args[:len(args)-1] + } + + case ADDIW: + if inst.Args[2].(Simm).Imm == 0 { + op = "MOVW" + args = args[:len(args)-1] + } + + case ANDI: + if inst.Args[2].(Simm).Imm == 255 { + op = "MOVBU" + args = args[:len(args)-1] + } + + case BEQ: + if inst.Args[1].(Reg) == X0 { + op = "BEQZ" + args[1] = args[2] + args = args[:len(args)-1] + } + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + + case BGE: + if inst.Args[1].(Reg) == X0 { + op = "BGEZ" + args[1] = args[2] + args = args[:len(args)-1] + } + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + + case BLT: + if inst.Args[1].(Reg) == X0 { + op = "BLTZ" + args[1] = args[2] + args = args[:len(args)-1] + } + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + + case BNE: + if inst.Args[1].(Reg) == X0 { + op = "BNEZ" + args[1] = args[2] + args = args[:len(args)-1] + } + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + + case BLTU, BGEU: + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + + case CSRRW: + switch inst.Args[1].(CSR) { + case FCSR: + op = "FSCSR" + args[1] = args[2] + args = args[:len(args)-1] + case FFLAGS: + op = "FSFLAGS" + args[1] = args[2] + args = args[:len(args)-1] + case FRM: + op = "FSRM" + args[1] = args[2] + args = args[:len(args)-1] + case CYCLE: + if inst.Args[0].(Reg) == X0 && inst.Args[2].(Reg) == X0 { + op = "UNIMP" + args = nil + } + } + + case CSRRS: + if inst.Args[2].(Reg) == X0 { + switch inst.Args[1].(CSR) { + case FCSR: + op = "FRCSR" + args = args[:len(args)-2] + case FFLAGS: + op = "FRFLAGS" + args = args[:len(args)-2] + case FRM: + op = "FRRM" + args = args[:len(args)-2] + case CYCLE: + op = "RDCYCLE" + args = args[:len(args)-2] + case CYCLEH: + op = "RDCYCLEH" + args = args[:len(args)-2] + case INSTRET: + op = "RDINSTRET" + args = args[:len(args)-2] + case INSTRETH: + op = "RDINSTRETH" + args = args[:len(args)-2] + case TIME: + op = "RDTIME" + args = args[:len(args)-2] + case TIMEH: + op = "RDTIMEH" + args = args[:len(args)-2] + } + } + + // Fence instruction in plan9 doesn't have any operands. + case FENCE: + args = nil + + case FMADD_D, FMADD_H, FMADD_Q, FMADD_S, FMSUB_D, FMSUB_H, + FMSUB_Q, FMSUB_S, FNMADD_D, FNMADD_H, FNMADD_Q, FNMADD_S, + FNMSUB_D, FNMSUB_H, FNMSUB_Q, FNMSUB_S: + args[1], args[3] = args[3], args[1] + + case FSGNJ_S: + if inst.Args[2] == inst.Args[1] { + op = "MOVF" + args = args[:len(args)-1] + } + + case FSGNJ_D: + if inst.Args[2] == inst.Args[1] { + op = "MOVD" + args = args[:len(args)-1] + } + + case FSGNJX_S: + if inst.Args[2] == inst.Args[1] { + op = "FABSS" + args = args[:len(args)-1] + } + + case FSGNJX_D: + if inst.Args[2] == inst.Args[1] { + op = "FABSD" + args = args[:len(args)-1] + } + + case FSGNJN_S: + if inst.Args[2] == inst.Args[1] { + op = "FNEGS" + args = args[:len(args)-1] + } + + case FSGNJN_D: + if inst.Args[2] == inst.Args[1] { + op = "FNESD" + args = args[:len(args)-1] + } + + case LD, SD: + op = "MOV" + if inst.Op == SD { + args[0], args[1] = args[1], args[0] + } + + case LB, SB: + op = "MOVB" + if inst.Op == SB { + args[0], args[1] = args[1], args[0] + } + + case LH, SH: + op = "MOVH" + if inst.Op == SH { + args[0], args[1] = args[1], args[0] + } + + case LW, SW: + op = "MOVW" + if inst.Op == SW { + args[0], args[1] = args[1], args[0] + } + + case LBU: + op = "MOVBU" + + case LHU: + op = "MOVHU" + + case LWU: + op = "MOVWU" + + case FLW, FSW: + op = "MOVF" + if inst.Op == FLW { + args[0], args[1] = args[1], args[0] + } + + case FLD, FSD: + op = "MOVD" + if inst.Op == FLD { + args[0], args[1] = args[1], args[0] + } + + case SUB: + if inst.Args[1].(Reg) == X0 { + op = "NEG" + args[1] = args[2] + args = args[:len(args)-1] + } + + case XORI: + if inst.Args[2].(Simm).String() == "-1" { + op = "NOT" + args = args[:len(args)-1] + } + + case SLTIU: + if inst.Args[2].(Simm).Imm == 1 { + op = "SEQZ" + args = args[:len(args)-1] + } + + case SLTU: + if inst.Args[1].(Reg) == X0 { + op = "SNEZ" + args[1] = args[2] + args = args[:len(args)-1] + } + + case JAL: + if inst.Args[0].(Reg) == X0 { + op = "JMP" + args[0] = args[1] + args = args[:len(args)-1] + } else if inst.Args[0].(Reg) == X1 { + op = "CALL" + args[0] = args[1] + args = args[:len(args)-1] + } else { + args[0], args[1] = args[1], args[0] + } + + case JALR: + if inst.Args[0].(Reg) == X0 { + if inst.Args[1].(RegOffset).OfsReg == X1 && inst.Args[1].(RegOffset).Ofs.Imm == 0 { + op = "RET" + args = nil + break + } + op = "JMP" + args[0] = args[1] + args = args[:len(args)-1] + } else if inst.Args[0].(Reg) == X1 { + op = "CALL" + args[0] = args[1] + args = args[:len(args)-1] + } else { + args[0], args[1] = args[1], args[0] + } + } + + // Reverse args, placing dest last. + for i, j := 0, len(args)-1; i < j; i, j = i+1, j-1 { + args[i], args[j] = args[j], args[i] + } + + // Change to plan9 opcode format + // Atomic instructions do not have reorder suffix, so remove them + op = strings.Replace(op, ".AQRL", "", -1) + op = strings.Replace(op, ".AQ", "", -1) + op = strings.Replace(op, ".RL", "", -1) + op = strings.Replace(op, ".", "", -1) + + if args != nil { + op += " " + strings.Join(args, ", ") + } + + return op +} + +func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string { + switch a := arg.(type) { + case Uimm: + return fmt.Sprintf("$%d", uint32(a.Imm)) + + case Simm: + imm, _ := strconv.Atoi(a.String()) + if a.Width == 13 || a.Width == 21 { + addr := int64(pc) + int64(imm) + if s, base := symname(uint64(addr)); s != "" && uint64(addr) == base { + return fmt.Sprintf("%s(SB)", s) + } + return fmt.Sprintf("%d(PC)", imm/4) + } + return fmt.Sprintf("$%d", int32(imm)) + + case Reg: + if a <= 31 { + return fmt.Sprintf("X%d", a) + } else { + return fmt.Sprintf("F%d", a-32) + } + + case RegOffset: + if a.Ofs.Imm == 0 { + return fmt.Sprintf("(X%d)", a.OfsReg) + } else { + return fmt.Sprintf("%s(X%d)", a.Ofs.String(), a.OfsReg) + } + + case AmoReg: + return fmt.Sprintf("(X%d)", a.reg) + + default: + return strings.ToUpper(arg.String()) + } +} diff --git a/riscv64/riscv64asm/tables.go b/riscv64/riscv64asm/tables.go new file mode 100644 index 00000000..3e5db415 --- /dev/null +++ b/riscv64/riscv64asm/tables.go @@ -0,0 +1,1474 @@ +// Code generated by riscv64spec riscv-opcodes +// DO NOT EDIT + +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package riscv64asm + +const ( + _ Op = iota + ADD + ADDI + ADDIW + ADDW + ADD_UW + AMOADD_D + AMOADD_D_AQ + AMOADD_D_AQRL + AMOADD_D_RL + AMOADD_W + AMOADD_W_AQ + AMOADD_W_AQRL + AMOADD_W_RL + AMOAND_D + AMOAND_D_AQ + AMOAND_D_AQRL + AMOAND_D_RL + AMOAND_W + AMOAND_W_AQ + AMOAND_W_AQRL + AMOAND_W_RL + AMOMAXU_D + AMOMAXU_D_AQ + AMOMAXU_D_AQRL + AMOMAXU_D_RL + AMOMAXU_W + AMOMAXU_W_AQ + AMOMAXU_W_AQRL + AMOMAXU_W_RL + AMOMAX_D + AMOMAX_D_AQ + AMOMAX_D_AQRL + AMOMAX_D_RL + AMOMAX_W + AMOMAX_W_AQ + AMOMAX_W_AQRL + AMOMAX_W_RL + AMOMINU_D + AMOMINU_D_AQ + AMOMINU_D_AQRL + AMOMINU_D_RL + AMOMINU_W + AMOMINU_W_AQ + AMOMINU_W_AQRL + AMOMINU_W_RL + AMOMIN_D + AMOMIN_D_AQ + AMOMIN_D_AQRL + AMOMIN_D_RL + AMOMIN_W + AMOMIN_W_AQ + AMOMIN_W_AQRL + AMOMIN_W_RL + AMOOR_D + AMOOR_D_AQ + AMOOR_D_AQRL + AMOOR_D_RL + AMOOR_W + AMOOR_W_AQ + AMOOR_W_AQRL + AMOOR_W_RL + AMOSWAP_D + AMOSWAP_D_AQ + AMOSWAP_D_AQRL + AMOSWAP_D_RL + AMOSWAP_W + AMOSWAP_W_AQ + AMOSWAP_W_AQRL + AMOSWAP_W_RL + AMOXOR_D + AMOXOR_D_AQ + AMOXOR_D_AQRL + AMOXOR_D_RL + AMOXOR_W + AMOXOR_W_AQ + AMOXOR_W_AQRL + AMOXOR_W_RL + AND + ANDI + ANDN + AUIPC + BCLR + BCLRI + BEQ + BEXT + BEXTI + BGE + BGEU + BINV + BINVI + BLT + BLTU + BNE + BSET + BSETI + CLZ + CLZW + CPOP + CPOPW + CSRRC + CSRRCI + CSRRS + CSRRSI + CSRRW + CSRRWI + CTZ + CTZW + C_ADD + C_ADDI + C_ADDI16SP + C_ADDI4SPN + C_ADDIW + C_ADDW + C_AND + C_ANDI + C_BEQZ + C_BNEZ + C_EBREAK + C_FLD + C_FLDSP + C_FSD + C_FSDSP + C_J + C_JALR + C_JR + C_LD + C_LDSP + C_LI + C_LUI + C_LW + C_LWSP + C_MV + C_NOP + C_OR + C_SD + C_SDSP + C_SLLI + C_SRAI + C_SRLI + C_SUB + C_SUBW + C_SW + C_SWSP + C_UNIMP + C_XOR + DIV + DIVU + DIVUW + DIVW + EBREAK + ECALL + FADD_D + FADD_H + FADD_Q + FADD_S + FCLASS_D + FCLASS_H + FCLASS_Q + FCLASS_S + FCVT_D_L + FCVT_D_LU + FCVT_D_Q + FCVT_D_S + FCVT_D_W + FCVT_D_WU + FCVT_H_L + FCVT_H_LU + FCVT_H_S + FCVT_H_W + FCVT_H_WU + FCVT_LU_D + FCVT_LU_H + FCVT_LU_Q + FCVT_LU_S + FCVT_L_D + FCVT_L_H + FCVT_L_Q + FCVT_L_S + FCVT_Q_D + FCVT_Q_L + FCVT_Q_LU + FCVT_Q_S + FCVT_Q_W + FCVT_Q_WU + FCVT_S_D + FCVT_S_H + FCVT_S_L + FCVT_S_LU + FCVT_S_Q + FCVT_S_W + FCVT_S_WU + FCVT_WU_D + FCVT_WU_H + FCVT_WU_Q + FCVT_WU_S + FCVT_W_D + FCVT_W_H + FCVT_W_Q + FCVT_W_S + FDIV_D + FDIV_H + FDIV_Q + FDIV_S + FENCE + FENCE_I + FEQ_D + FEQ_H + FEQ_Q + FEQ_S + FLD + FLE_D + FLE_H + FLE_Q + FLE_S + FLH + FLQ + FLT_D + FLT_H + FLT_Q + FLT_S + FLW + FMADD_D + FMADD_H + FMADD_Q + FMADD_S + FMAX_D + FMAX_H + FMAX_Q + FMAX_S + FMIN_D + FMIN_H + FMIN_Q + FMIN_S + FMSUB_D + FMSUB_H + FMSUB_Q + FMSUB_S + FMUL_D + FMUL_H + FMUL_Q + FMUL_S + FMV_D_X + FMV_H_X + FMV_W_X + FMV_X_D + FMV_X_H + FMV_X_W + FNMADD_D + FNMADD_H + FNMADD_Q + FNMADD_S + FNMSUB_D + FNMSUB_H + FNMSUB_Q + FNMSUB_S + FSD + FSGNJN_D + FSGNJN_H + FSGNJN_Q + FSGNJN_S + FSGNJX_D + FSGNJX_H + FSGNJX_Q + FSGNJX_S + FSGNJ_D + FSGNJ_H + FSGNJ_Q + FSGNJ_S + FSH + FSQ + FSQRT_D + FSQRT_H + FSQRT_Q + FSQRT_S + FSUB_D + FSUB_H + FSUB_Q + FSUB_S + FSW + JAL + JALR + LB + LBU + LD + LH + LHU + LR_D + LR_D_AQ + LR_D_AQRL + LR_D_RL + LR_W + LR_W_AQ + LR_W_AQRL + LR_W_RL + LUI + LW + LWU + MAX + MAXU + MIN + MINU + MUL + MULH + MULHSU + MULHU + MULW + OR + ORC_B + ORI + ORN + REM + REMU + REMUW + REMW + REV8 + ROL + ROLW + ROR + RORI + RORIW + RORW + SB + SC_D + SC_D_AQ + SC_D_AQRL + SC_D_RL + SC_W + SC_W_AQ + SC_W_AQRL + SC_W_RL + SD + SEXT_B + SEXT_H + SH + SH1ADD + SH1ADD_UW + SH2ADD + SH2ADD_UW + SH3ADD + SH3ADD_UW + SLL + SLLI + SLLIW + SLLI_UW + SLLW + SLT + SLTI + SLTIU + SLTU + SRA + SRAI + SRAIW + SRAW + SRL + SRLI + SRLIW + SRLW + SUB + SUBW + SW + XNOR + XOR + XORI + ZEXT_H +) + +var opstr = [...]string{ + ADD: "ADD", + ADDI: "ADDI", + ADDIW: "ADDIW", + ADDW: "ADDW", + ADD_UW: "ADD.UW", + AMOADD_D: "AMOADD.D", + AMOADD_D_AQ: "AMOADD.D.AQ", + AMOADD_D_AQRL: "AMOADD.D.AQRL", + AMOADD_D_RL: "AMOADD.D.RL", + AMOADD_W: "AMOADD.W", + AMOADD_W_AQ: "AMOADD.W.AQ", + AMOADD_W_AQRL: "AMOADD.W.AQRL", + AMOADD_W_RL: "AMOADD.W.RL", + AMOAND_D: "AMOAND.D", + AMOAND_D_AQ: "AMOAND.D.AQ", + AMOAND_D_AQRL: "AMOAND.D.AQRL", + AMOAND_D_RL: "AMOAND.D.RL", + AMOAND_W: "AMOAND.W", + AMOAND_W_AQ: "AMOAND.W.AQ", + AMOAND_W_AQRL: "AMOAND.W.AQRL", + AMOAND_W_RL: "AMOAND.W.RL", + AMOMAXU_D: "AMOMAXU.D", + AMOMAXU_D_AQ: "AMOMAXU.D.AQ", + AMOMAXU_D_AQRL: "AMOMAXU.D.AQRL", + AMOMAXU_D_RL: "AMOMAXU.D.RL", + AMOMAXU_W: "AMOMAXU.W", + AMOMAXU_W_AQ: "AMOMAXU.W.AQ", + AMOMAXU_W_AQRL: "AMOMAXU.W.AQRL", + AMOMAXU_W_RL: "AMOMAXU.W.RL", + AMOMAX_D: "AMOMAX.D", + AMOMAX_D_AQ: "AMOMAX.D.AQ", + AMOMAX_D_AQRL: "AMOMAX.D.AQRL", + AMOMAX_D_RL: "AMOMAX.D.RL", + AMOMAX_W: "AMOMAX.W", + AMOMAX_W_AQ: "AMOMAX.W.AQ", + AMOMAX_W_AQRL: "AMOMAX.W.AQRL", + AMOMAX_W_RL: "AMOMAX.W.RL", + AMOMINU_D: "AMOMINU.D", + AMOMINU_D_AQ: "AMOMINU.D.AQ", + AMOMINU_D_AQRL: "AMOMINU.D.AQRL", + AMOMINU_D_RL: "AMOMINU.D.RL", + AMOMINU_W: "AMOMINU.W", + AMOMINU_W_AQ: "AMOMINU.W.AQ", + AMOMINU_W_AQRL: "AMOMINU.W.AQRL", + AMOMINU_W_RL: "AMOMINU.W.RL", + AMOMIN_D: "AMOMIN.D", + AMOMIN_D_AQ: "AMOMIN.D.AQ", + AMOMIN_D_AQRL: "AMOMIN.D.AQRL", + AMOMIN_D_RL: "AMOMIN.D.RL", + AMOMIN_W: "AMOMIN.W", + AMOMIN_W_AQ: "AMOMIN.W.AQ", + AMOMIN_W_AQRL: "AMOMIN.W.AQRL", + AMOMIN_W_RL: "AMOMIN.W.RL", + AMOOR_D: "AMOOR.D", + AMOOR_D_AQ: "AMOOR.D.AQ", + AMOOR_D_AQRL: "AMOOR.D.AQRL", + AMOOR_D_RL: "AMOOR.D.RL", + AMOOR_W: "AMOOR.W", + AMOOR_W_AQ: "AMOOR.W.AQ", + AMOOR_W_AQRL: "AMOOR.W.AQRL", + AMOOR_W_RL: "AMOOR.W.RL", + AMOSWAP_D: "AMOSWAP.D", + AMOSWAP_D_AQ: "AMOSWAP.D.AQ", + AMOSWAP_D_AQRL: "AMOSWAP.D.AQRL", + AMOSWAP_D_RL: "AMOSWAP.D.RL", + AMOSWAP_W: "AMOSWAP.W", + AMOSWAP_W_AQ: "AMOSWAP.W.AQ", + AMOSWAP_W_AQRL: "AMOSWAP.W.AQRL", + AMOSWAP_W_RL: "AMOSWAP.W.RL", + AMOXOR_D: "AMOXOR.D", + AMOXOR_D_AQ: "AMOXOR.D.AQ", + AMOXOR_D_AQRL: "AMOXOR.D.AQRL", + AMOXOR_D_RL: "AMOXOR.D.RL", + AMOXOR_W: "AMOXOR.W", + AMOXOR_W_AQ: "AMOXOR.W.AQ", + AMOXOR_W_AQRL: "AMOXOR.W.AQRL", + AMOXOR_W_RL: "AMOXOR.W.RL", + AND: "AND", + ANDI: "ANDI", + ANDN: "ANDN", + AUIPC: "AUIPC", + BCLR: "BCLR", + BCLRI: "BCLRI", + BEQ: "BEQ", + BEXT: "BEXT", + BEXTI: "BEXTI", + BGE: "BGE", + BGEU: "BGEU", + BINV: "BINV", + BINVI: "BINVI", + BLT: "BLT", + BLTU: "BLTU", + BNE: "BNE", + BSET: "BSET", + BSETI: "BSETI", + CLZ: "CLZ", + CLZW: "CLZW", + CPOP: "CPOP", + CPOPW: "CPOPW", + CSRRC: "CSRRC", + CSRRCI: "CSRRCI", + CSRRS: "CSRRS", + CSRRSI: "CSRRSI", + CSRRW: "CSRRW", + CSRRWI: "CSRRWI", + CTZ: "CTZ", + CTZW: "CTZW", + C_ADD: "C.ADD", + C_ADDI: "C.ADDI", + C_ADDI16SP: "C.ADDI16SP", + C_ADDI4SPN: "C.ADDI4SPN", + C_ADDIW: "C.ADDIW", + C_ADDW: "C.ADDW", + C_AND: "C.AND", + C_ANDI: "C.ANDI", + C_BEQZ: "C.BEQZ", + C_BNEZ: "C.BNEZ", + C_EBREAK: "C.EBREAK", + C_FLD: "C.FLD", + C_FLDSP: "C.FLDSP", + C_FSD: "C.FSD", + C_FSDSP: "C.FSDSP", + C_J: "C.J", + C_JALR: "C.JALR", + C_JR: "C.JR", + C_LD: "C.LD", + C_LDSP: "C.LDSP", + C_LI: "C.LI", + C_LUI: "C.LUI", + C_LW: "C.LW", + C_LWSP: "C.LWSP", + C_MV: "C.MV", + C_NOP: "C.NOP", + C_OR: "C.OR", + C_SD: "C.SD", + C_SDSP: "C.SDSP", + C_SLLI: "C.SLLI", + C_SRAI: "C.SRAI", + C_SRLI: "C.SRLI", + C_SUB: "C.SUB", + C_SUBW: "C.SUBW", + C_SW: "C.SW", + C_SWSP: "C.SWSP", + C_UNIMP: "C.UNIMP", + C_XOR: "C.XOR", + DIV: "DIV", + DIVU: "DIVU", + DIVUW: "DIVUW", + DIVW: "DIVW", + EBREAK: "EBREAK", + ECALL: "ECALL", + FADD_D: "FADD.D", + FADD_H: "FADD.H", + FADD_Q: "FADD.Q", + FADD_S: "FADD.S", + FCLASS_D: "FCLASS.D", + FCLASS_H: "FCLASS.H", + FCLASS_Q: "FCLASS.Q", + FCLASS_S: "FCLASS.S", + FCVT_D_L: "FCVT.D.L", + FCVT_D_LU: "FCVT.D.LU", + FCVT_D_Q: "FCVT.D.Q", + FCVT_D_S: "FCVT.D.S", + FCVT_D_W: "FCVT.D.W", + FCVT_D_WU: "FCVT.D.WU", + FCVT_H_L: "FCVT.H.L", + FCVT_H_LU: "FCVT.H.LU", + FCVT_H_S: "FCVT.H.S", + FCVT_H_W: "FCVT.H.W", + FCVT_H_WU: "FCVT.H.WU", + FCVT_LU_D: "FCVT.LU.D", + FCVT_LU_H: "FCVT.LU.H", + FCVT_LU_Q: "FCVT.LU.Q", + FCVT_LU_S: "FCVT.LU.S", + FCVT_L_D: "FCVT.L.D", + FCVT_L_H: "FCVT.L.H", + FCVT_L_Q: "FCVT.L.Q", + FCVT_L_S: "FCVT.L.S", + FCVT_Q_D: "FCVT.Q.D", + FCVT_Q_L: "FCVT.Q.L", + FCVT_Q_LU: "FCVT.Q.LU", + FCVT_Q_S: "FCVT.Q.S", + FCVT_Q_W: "FCVT.Q.W", + FCVT_Q_WU: "FCVT.Q.WU", + FCVT_S_D: "FCVT.S.D", + FCVT_S_H: "FCVT.S.H", + FCVT_S_L: "FCVT.S.L", + FCVT_S_LU: "FCVT.S.LU", + FCVT_S_Q: "FCVT.S.Q", + FCVT_S_W: "FCVT.S.W", + FCVT_S_WU: "FCVT.S.WU", + FCVT_WU_D: "FCVT.WU.D", + FCVT_WU_H: "FCVT.WU.H", + FCVT_WU_Q: "FCVT.WU.Q", + FCVT_WU_S: "FCVT.WU.S", + FCVT_W_D: "FCVT.W.D", + FCVT_W_H: "FCVT.W.H", + FCVT_W_Q: "FCVT.W.Q", + FCVT_W_S: "FCVT.W.S", + FDIV_D: "FDIV.D", + FDIV_H: "FDIV.H", + FDIV_Q: "FDIV.Q", + FDIV_S: "FDIV.S", + FENCE: "FENCE", + FENCE_I: "FENCE.I", + FEQ_D: "FEQ.D", + FEQ_H: "FEQ.H", + FEQ_Q: "FEQ.Q", + FEQ_S: "FEQ.S", + FLD: "FLD", + FLE_D: "FLE.D", + FLE_H: "FLE.H", + FLE_Q: "FLE.Q", + FLE_S: "FLE.S", + FLH: "FLH", + FLQ: "FLQ", + FLT_D: "FLT.D", + FLT_H: "FLT.H", + FLT_Q: "FLT.Q", + FLT_S: "FLT.S", + FLW: "FLW", + FMADD_D: "FMADD.D", + FMADD_H: "FMADD.H", + FMADD_Q: "FMADD.Q", + FMADD_S: "FMADD.S", + FMAX_D: "FMAX.D", + FMAX_H: "FMAX.H", + FMAX_Q: "FMAX.Q", + FMAX_S: "FMAX.S", + FMIN_D: "FMIN.D", + FMIN_H: "FMIN.H", + FMIN_Q: "FMIN.Q", + FMIN_S: "FMIN.S", + FMSUB_D: "FMSUB.D", + FMSUB_H: "FMSUB.H", + FMSUB_Q: "FMSUB.Q", + FMSUB_S: "FMSUB.S", + FMUL_D: "FMUL.D", + FMUL_H: "FMUL.H", + FMUL_Q: "FMUL.Q", + FMUL_S: "FMUL.S", + FMV_D_X: "FMV.D.X", + FMV_H_X: "FMV.H.X", + FMV_W_X: "FMV.W.X", + FMV_X_D: "FMV.X.D", + FMV_X_H: "FMV.X.H", + FMV_X_W: "FMV.X.W", + FNMADD_D: "FNMADD.D", + FNMADD_H: "FNMADD.H", + FNMADD_Q: "FNMADD.Q", + FNMADD_S: "FNMADD.S", + FNMSUB_D: "FNMSUB.D", + FNMSUB_H: "FNMSUB.H", + FNMSUB_Q: "FNMSUB.Q", + FNMSUB_S: "FNMSUB.S", + FSD: "FSD", + FSGNJN_D: "FSGNJN.D", + FSGNJN_H: "FSGNJN.H", + FSGNJN_Q: "FSGNJN.Q", + FSGNJN_S: "FSGNJN.S", + FSGNJX_D: "FSGNJX.D", + FSGNJX_H: "FSGNJX.H", + FSGNJX_Q: "FSGNJX.Q", + FSGNJX_S: "FSGNJX.S", + FSGNJ_D: "FSGNJ.D", + FSGNJ_H: "FSGNJ.H", + FSGNJ_Q: "FSGNJ.Q", + FSGNJ_S: "FSGNJ.S", + FSH: "FSH", + FSQ: "FSQ", + FSQRT_D: "FSQRT.D", + FSQRT_H: "FSQRT.H", + FSQRT_Q: "FSQRT.Q", + FSQRT_S: "FSQRT.S", + FSUB_D: "FSUB.D", + FSUB_H: "FSUB.H", + FSUB_Q: "FSUB.Q", + FSUB_S: "FSUB.S", + FSW: "FSW", + JAL: "JAL", + JALR: "JALR", + LB: "LB", + LBU: "LBU", + LD: "LD", + LH: "LH", + LHU: "LHU", + LR_D: "LR.D", + LR_D_AQ: "LR.D.AQ", + LR_D_AQRL: "LR.D.AQRL", + LR_D_RL: "LR.D.RL", + LR_W: "LR.W", + LR_W_AQ: "LR.W.AQ", + LR_W_AQRL: "LR.W.AQRL", + LR_W_RL: "LR.W.RL", + LUI: "LUI", + LW: "LW", + LWU: "LWU", + MAX: "MAX", + MAXU: "MAXU", + MIN: "MIN", + MINU: "MINU", + MUL: "MUL", + MULH: "MULH", + MULHSU: "MULHSU", + MULHU: "MULHU", + MULW: "MULW", + OR: "OR", + ORC_B: "ORC.B", + ORI: "ORI", + ORN: "ORN", + REM: "REM", + REMU: "REMU", + REMUW: "REMUW", + REMW: "REMW", + REV8: "REV8", + ROL: "ROL", + ROLW: "ROLW", + ROR: "ROR", + RORI: "RORI", + RORIW: "RORIW", + RORW: "RORW", + SB: "SB", + SC_D: "SC.D", + SC_D_AQ: "SC.D.AQ", + SC_D_AQRL: "SC.D.AQRL", + SC_D_RL: "SC.D.RL", + SC_W: "SC.W", + SC_W_AQ: "SC.W.AQ", + SC_W_AQRL: "SC.W.AQRL", + SC_W_RL: "SC.W.RL", + SD: "SD", + SEXT_B: "SEXT.B", + SEXT_H: "SEXT.H", + SH: "SH", + SH1ADD: "SH1ADD", + SH1ADD_UW: "SH1ADD.UW", + SH2ADD: "SH2ADD", + SH2ADD_UW: "SH2ADD.UW", + SH3ADD: "SH3ADD", + SH3ADD_UW: "SH3ADD.UW", + SLL: "SLL", + SLLI: "SLLI", + SLLIW: "SLLIW", + SLLI_UW: "SLLI.UW", + SLLW: "SLLW", + SLT: "SLT", + SLTI: "SLTI", + SLTIU: "SLTIU", + SLTU: "SLTU", + SRA: "SRA", + SRAI: "SRAI", + SRAIW: "SRAIW", + SRAW: "SRAW", + SRL: "SRL", + SRLI: "SRLI", + SRLIW: "SRLIW", + SRLW: "SRLW", + SUB: "SUB", + SUBW: "SUBW", + SW: "SW", + XNOR: "XNOR", + XOR: "XOR", + XORI: "XORI", + ZEXT_H: "ZEXT.H", +} + +var instFormats = [...]instFormat{ + // ADD rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x00000033, op: ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // ADDI rd, rs1, imm12 + {mask: 0x0000707f, value: 0x00000013, op: ADDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, + // ADDIW rd, rs1, imm12 + {mask: 0x0000707f, value: 0x0000001b, op: ADDIW, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, + // ADDW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0000003b, op: ADDW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // ADD.UW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0800003b, op: ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // AMOADD.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0000302f, op: AMOADD_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOADD.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0400302f, op: AMOADD_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOADD.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0600302f, op: AMOADD_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOADD.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0200302f, op: AMOADD_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOADD.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0000202f, op: AMOADD_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOADD.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0400202f, op: AMOADD_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOADD.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0600202f, op: AMOADD_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOADD.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0200202f, op: AMOADD_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOAND.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x6000302f, op: AMOAND_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOAND.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x6400302f, op: AMOAND_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOAND.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x6600302f, op: AMOAND_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOAND.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x6200302f, op: AMOAND_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOAND.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x6000202f, op: AMOAND_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOAND.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x6400202f, op: AMOAND_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOAND.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x6600202f, op: AMOAND_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOAND.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x6200202f, op: AMOAND_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAXU.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xe000302f, op: AMOMAXU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAXU.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xe400302f, op: AMOMAXU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAXU.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xe600302f, op: AMOMAXU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAXU.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xe200302f, op: AMOMAXU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAXU.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xe000202f, op: AMOMAXU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAXU.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xe400202f, op: AMOMAXU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAXU.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xe600202f, op: AMOMAXU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAXU.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xe200202f, op: AMOMAXU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAX.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xa000302f, op: AMOMAX_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAX.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xa400302f, op: AMOMAX_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAX.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xa600302f, op: AMOMAX_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAX.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xa200302f, op: AMOMAX_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAX.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xa000202f, op: AMOMAX_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAX.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xa400202f, op: AMOMAX_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAX.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xa600202f, op: AMOMAX_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMAX.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xa200202f, op: AMOMAX_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMINU.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xc000302f, op: AMOMINU_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMINU.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xc400302f, op: AMOMINU_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMINU.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xc600302f, op: AMOMINU_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMINU.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xc200302f, op: AMOMINU_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMINU.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xc000202f, op: AMOMINU_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMINU.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xc400202f, op: AMOMINU_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMINU.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xc600202f, op: AMOMINU_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMINU.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0xc200202f, op: AMOMINU_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMIN.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x8000302f, op: AMOMIN_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMIN.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x8400302f, op: AMOMIN_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMIN.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x8600302f, op: AMOMIN_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMIN.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x8200302f, op: AMOMIN_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMIN.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x8000202f, op: AMOMIN_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMIN.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x8400202f, op: AMOMIN_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMIN.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x8600202f, op: AMOMIN_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOMIN.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x8200202f, op: AMOMIN_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOOR.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x4000302f, op: AMOOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOOR.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x4400302f, op: AMOOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOOR.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x4600302f, op: AMOOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOOR.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x4200302f, op: AMOOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOOR.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x4000202f, op: AMOOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOOR.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x4400202f, op: AMOOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOOR.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x4600202f, op: AMOOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOOR.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x4200202f, op: AMOOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOSWAP.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0800302f, op: AMOSWAP_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOSWAP.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0c00302f, op: AMOSWAP_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOSWAP.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0e00302f, op: AMOSWAP_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOSWAP.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0a00302f, op: AMOSWAP_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOSWAP.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0800202f, op: AMOSWAP_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOSWAP.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0c00202f, op: AMOSWAP_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOSWAP.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0e00202f, op: AMOSWAP_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOSWAP.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x0a00202f, op: AMOSWAP_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOXOR.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x2000302f, op: AMOXOR_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOXOR.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x2400302f, op: AMOXOR_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOXOR.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x2600302f, op: AMOXOR_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOXOR.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x2200302f, op: AMOXOR_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOXOR.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x2000202f, op: AMOXOR_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOXOR.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x2400202f, op: AMOXOR_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOXOR.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x2600202f, op: AMOXOR_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AMOXOR.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x2200202f, op: AMOXOR_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // AND rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x00007033, op: AND, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // ANDI rd, rs1, imm12 + {mask: 0x0000707f, value: 0x00007013, op: ANDI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, + // ANDN rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x40007033, op: ANDN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // AUIPC rd, imm20 + {mask: 0x0000007f, value: 0x00000017, op: AUIPC, args: argTypeList{arg_rd, arg_imm20}}, + // BCLR rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x48001033, op: BCLR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // BCLRI rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x48001013, op: BCLRI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // BEQ rs1, rs2, bimm12 + {mask: 0x0000707f, value: 0x00000063, op: BEQ, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, + // BEXT rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x48005033, op: BEXT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // BEXTI rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x48005013, op: BEXTI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // BGE rs1, rs2, bimm12 + {mask: 0x0000707f, value: 0x00005063, op: BGE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, + // BGEU rs1, rs2, bimm12 + {mask: 0x0000707f, value: 0x00007063, op: BGEU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, + // BINV rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x68001033, op: BINV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // BINVI rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x68001013, op: BINVI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // BLT rs1, rs2, bimm12 + {mask: 0x0000707f, value: 0x00004063, op: BLT, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, + // BLTU rs1, rs2, bimm12 + {mask: 0x0000707f, value: 0x00006063, op: BLTU, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, + // BNE rs1, rs2, bimm12 + {mask: 0x0000707f, value: 0x00001063, op: BNE, args: argTypeList{arg_rs1, arg_rs2, arg_bimm12}}, + // BSET rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x28001033, op: BSET, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // BSETI rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x28001013, op: BSETI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // CLZ rd, rs1 + {mask: 0xfff0707f, value: 0x60001013, op: CLZ, args: argTypeList{arg_rd, arg_rs1}}, + // CLZW rd, rs1 + {mask: 0xfff0707f, value: 0x6000101b, op: CLZW, args: argTypeList{arg_rd, arg_rs1}}, + // CPOP rd, rs1 + {mask: 0xfff0707f, value: 0x60201013, op: CPOP, args: argTypeList{arg_rd, arg_rs1}}, + // CPOPW rd, rs1 + {mask: 0xfff0707f, value: 0x6020101b, op: CPOPW, args: argTypeList{arg_rd, arg_rs1}}, + // CSRRC rd, csr, rs1 + {mask: 0x0000707f, value: 0x00003073, op: CSRRC, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, + // CSRRCI rd, csr, zimm + {mask: 0x0000707f, value: 0x00007073, op: CSRRCI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, + // CSRRS rd, csr, rs1 + {mask: 0x0000707f, value: 0x00002073, op: CSRRS, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, + // CSRRSI rd, csr, zimm + {mask: 0x0000707f, value: 0x00006073, op: CSRRSI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, + // CSRRW rd, csr, rs1 + {mask: 0x0000707f, value: 0x00001073, op: CSRRW, args: argTypeList{arg_rd, arg_csr, arg_rs1}}, + // CSRRWI rd, csr, zimm + {mask: 0x0000707f, value: 0x00005073, op: CSRRWI, args: argTypeList{arg_rd, arg_csr, arg_zimm}}, + // CTZ rd, rs1 + {mask: 0xfff0707f, value: 0x60101013, op: CTZ, args: argTypeList{arg_rd, arg_rs1}}, + // CTZW rd, rs1 + {mask: 0xfff0707f, value: 0x6010101b, op: CTZW, args: argTypeList{arg_rd, arg_rs1}}, + // C.ADD rd_rs1_n0, c_rs2_n0 + {mask: 0x0000f003, value: 0x00009002, op: C_ADD, args: argTypeList{arg_rd_rs1_n0, arg_c_rs2_n0}}, + // C.ADDI rd_rs1_n0, c_nzimm6 + {mask: 0x0000e003, value: 0x00000001, op: C_ADDI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzimm6}}, + // C.ADDI16SP c_nzimm10 + {mask: 0x0000ef83, value: 0x00006101, op: C_ADDI16SP, args: argTypeList{arg_c_nzimm10}}, + // C.ADDI4SPN rd_p, c_nzuimm10 + {mask: 0x0000e003, value: 0x00000000, op: C_ADDI4SPN, args: argTypeList{arg_rd_p, arg_c_nzuimm10}}, + // C.ADDIW rd_rs1_n0, c_imm6 + {mask: 0x0000e003, value: 0x00002001, op: C_ADDIW, args: argTypeList{arg_rd_rs1_n0, arg_c_imm6}}, + // C.ADDW rd_rs1_p, rs2_p + {mask: 0x0000fc63, value: 0x00009c21, op: C_ADDW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, + // C.AND rd_rs1_p, rs2_p + {mask: 0x0000fc63, value: 0x00008c61, op: C_AND, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, + // C.ANDI rd_rs1_p, c_imm6 + {mask: 0x0000ec03, value: 0x00008801, op: C_ANDI, args: argTypeList{arg_rd_rs1_p, arg_c_imm6}}, + // C.BEQZ rs1_p, c_bimm9 + {mask: 0x0000e003, value: 0x0000c001, op: C_BEQZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}}, + // C.BNEZ rs1_p, c_bimm9 + {mask: 0x0000e003, value: 0x0000e001, op: C_BNEZ, args: argTypeList{arg_rs1_p, arg_c_bimm9}}, + // C.EBREAK + {mask: 0x0000ffff, value: 0x00009002, op: C_EBREAK, args: argTypeList{}}, + // C.FLD fd_p, rs1_p, c_uimm8 + {mask: 0x0000e003, value: 0x00002000, op: C_FLD, args: argTypeList{arg_fd_p, arg_rs1_p, arg_c_uimm8}}, + // C.FLDSP fd, c_uimm9sp + {mask: 0x0000e003, value: 0x00002002, op: C_FLDSP, args: argTypeList{arg_fd, arg_c_uimm9sp}}, + // C.FSD rs1_p, fs2_p, c_uimm8 + {mask: 0x0000e003, value: 0x0000a000, op: C_FSD, args: argTypeList{arg_rs1_p, arg_fs2_p, arg_c_uimm8}}, + // C.FSDSP c_fs2, c_uimm9sp_s + {mask: 0x0000e003, value: 0x0000a002, op: C_FSDSP, args: argTypeList{arg_c_fs2, arg_c_uimm9sp_s}}, + // C.J c_imm12 + {mask: 0x0000e003, value: 0x0000a001, op: C_J, args: argTypeList{arg_c_imm12}}, + // C.JALR c_rs1_n0 + {mask: 0x0000f07f, value: 0x00009002, op: C_JALR, args: argTypeList{arg_c_rs1_n0}}, + // C.JR rs1_n0 + {mask: 0x0000f07f, value: 0x00008002, op: C_JR, args: argTypeList{arg_rs1_n0}}, + // C.LD rd_p, rs1_p, c_uimm8 + {mask: 0x0000e003, value: 0x00006000, op: C_LD, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm8}}, + // C.LDSP rd_n0, c_uimm9sp + {mask: 0x0000e003, value: 0x00006002, op: C_LDSP, args: argTypeList{arg_rd_n0, arg_c_uimm9sp}}, + // C.LI rd_n0, c_imm6 + {mask: 0x0000e003, value: 0x00004001, op: C_LI, args: argTypeList{arg_rd_n0, arg_c_imm6}}, + // C.LUI rd_n2, c_nzimm18 + {mask: 0x0000e003, value: 0x00006001, op: C_LUI, args: argTypeList{arg_rd_n2, arg_c_nzimm18}}, + // C.LW rd_p, rs1_p, c_uimm7 + {mask: 0x0000e003, value: 0x00004000, op: C_LW, args: argTypeList{arg_rd_p, arg_rs1_p, arg_c_uimm7}}, + // C.LWSP rd_n0, c_uimm8sp + {mask: 0x0000e003, value: 0x00004002, op: C_LWSP, args: argTypeList{arg_rd_n0, arg_c_uimm8sp}}, + // C.MV rd_n0, c_rs2_n0 + {mask: 0x0000f003, value: 0x00008002, op: C_MV, args: argTypeList{arg_rd_n0, arg_c_rs2_n0}}, + // C.NOP c_nzimm6 + {mask: 0x0000ef83, value: 0x00000001, op: C_NOP, args: argTypeList{arg_c_nzimm6}}, + // C.OR rd_rs1_p, rs2_p + {mask: 0x0000fc63, value: 0x00008c41, op: C_OR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, + // C.SD rs1_p, rs2_p, c_uimm8 + {mask: 0x0000e003, value: 0x0000e000, op: C_SD, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm8}}, + // C.SDSP c_rs2, c_uimm9sp_s + {mask: 0x0000e003, value: 0x0000e002, op: C_SDSP, args: argTypeList{arg_c_rs2, arg_c_uimm9sp_s}}, + // C.SLLI rd_rs1_n0, c_nzuimm6 + {mask: 0x0000e003, value: 0x00000002, op: C_SLLI, args: argTypeList{arg_rd_rs1_n0, arg_c_nzuimm6}}, + // C.SRAI rd_rs1_p, c_nzuimm6 + {mask: 0x0000ec03, value: 0x00008401, op: C_SRAI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}}, + // C.SRLI rd_rs1_p, c_nzuimm6 + {mask: 0x0000ec03, value: 0x00008001, op: C_SRLI, args: argTypeList{arg_rd_rs1_p, arg_c_nzuimm6}}, + // C.SUB rd_rs1_p, rs2_p + {mask: 0x0000fc63, value: 0x00008c01, op: C_SUB, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, + // C.SUBW rd_rs1_p, rs2_p + {mask: 0x0000fc63, value: 0x00009c01, op: C_SUBW, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, + // C.SW rs1_p, rs2_p, c_uimm7 + {mask: 0x0000e003, value: 0x0000c000, op: C_SW, args: argTypeList{arg_rs1_p, arg_rs2_p, arg_c_uimm7}}, + // C.SWSP c_rs2, c_uimm8sp_s + {mask: 0x0000e003, value: 0x0000c002, op: C_SWSP, args: argTypeList{arg_c_rs2, arg_c_uimm8sp_s}}, + // C.UNIMP + {mask: 0x0000ffff, value: 0x00000000, op: C_UNIMP, args: argTypeList{}}, + // C.XOR rd_rs1_p, rs2_p + {mask: 0x0000fc63, value: 0x00008c21, op: C_XOR, args: argTypeList{arg_rd_rs1_p, arg_rs2_p}}, + // DIV rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x02004033, op: DIV, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // DIVU rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x02005033, op: DIVU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // DIVUW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0200503b, op: DIVUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // DIVW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0200403b, op: DIVW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // EBREAK + {mask: 0xffffffff, value: 0x00100073, op: EBREAK, args: argTypeList{}}, + // ECALL + {mask: 0xffffffff, value: 0x00000073, op: ECALL, args: argTypeList{}}, + // FADD.D fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x02000053, op: FADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FADD.H fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x04000053, op: FADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FADD.Q fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x06000053, op: FADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FADD.S fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x00000053, op: FADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FCLASS.D rd, fs1 + {mask: 0xfff0707f, value: 0xe2001053, op: FCLASS_D, args: argTypeList{arg_rd, arg_fs1}}, + // FCLASS.H rd, fs1 + {mask: 0xfff0707f, value: 0xe4001053, op: FCLASS_H, args: argTypeList{arg_rd, arg_fs1}}, + // FCLASS.Q rd, fs1 + {mask: 0xfff0707f, value: 0xe6001053, op: FCLASS_Q, args: argTypeList{arg_rd, arg_fs1}}, + // FCLASS.S rd, fs1 + {mask: 0xfff0707f, value: 0xe0001053, op: FCLASS_S, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.D.L fd, rs1 + {mask: 0xfff0007f, value: 0xd2200053, op: FCVT_D_L, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.D.LU fd, rs1 + {mask: 0xfff0007f, value: 0xd2300053, op: FCVT_D_LU, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.D.Q fd, fs1 + {mask: 0xfff0007f, value: 0x42300053, op: FCVT_D_Q, args: argTypeList{arg_fd, arg_fs1}}, + // FCVT.D.S fd, fs1 + {mask: 0xfff0007f, value: 0x42000053, op: FCVT_D_S, args: argTypeList{arg_fd, arg_fs1}}, + // FCVT.D.W fd, rs1 + {mask: 0xfff0007f, value: 0xd2000053, op: FCVT_D_W, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.D.WU fd, rs1 + {mask: 0xfff0007f, value: 0xd2100053, op: FCVT_D_WU, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.H.L fd, rs1 + {mask: 0xfff0007f, value: 0xd4200053, op: FCVT_H_L, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.H.LU fd, rs1 + {mask: 0xfff0007f, value: 0xd4300053, op: FCVT_H_LU, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.H.S fd, fs1 + {mask: 0xfff0007f, value: 0x44000053, op: FCVT_H_S, args: argTypeList{arg_fd, arg_fs1}}, + // FCVT.H.W fd, rs1 + {mask: 0xfff0007f, value: 0xd4000053, op: FCVT_H_W, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.H.WU fd, rs1 + {mask: 0xfff0007f, value: 0xd4100053, op: FCVT_H_WU, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.LU.D rd, fs1 + {mask: 0xfff0007f, value: 0xc2300053, op: FCVT_LU_D, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.LU.H rd, fs1 + {mask: 0xfff0007f, value: 0xc4300053, op: FCVT_LU_H, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.LU.Q rd, fs1 + {mask: 0xfff0007f, value: 0xc6300053, op: FCVT_LU_Q, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.LU.S rd, fs1 + {mask: 0xfff0007f, value: 0xc0300053, op: FCVT_LU_S, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.L.D rd, fs1 + {mask: 0xfff0007f, value: 0xc2200053, op: FCVT_L_D, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.L.H rd, fs1 + {mask: 0xfff0007f, value: 0xc4200053, op: FCVT_L_H, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.L.Q rd, fs1 + {mask: 0xfff0007f, value: 0xc6200053, op: FCVT_L_Q, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.L.S rd, fs1 + {mask: 0xfff0007f, value: 0xc0200053, op: FCVT_L_S, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.Q.D fd, fs1 + {mask: 0xfff0007f, value: 0x46100053, op: FCVT_Q_D, args: argTypeList{arg_fd, arg_fs1}}, + // FCVT.Q.L fd, rs1 + {mask: 0xfff0007f, value: 0xd6200053, op: FCVT_Q_L, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.Q.LU fd, rs1 + {mask: 0xfff0007f, value: 0xd6300053, op: FCVT_Q_LU, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.Q.S fd, fs1 + {mask: 0xfff0007f, value: 0x46000053, op: FCVT_Q_S, args: argTypeList{arg_fd, arg_fs1}}, + // FCVT.Q.W fd, rs1 + {mask: 0xfff0007f, value: 0xd6000053, op: FCVT_Q_W, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.Q.WU fd, rs1 + {mask: 0xfff0007f, value: 0xd6100053, op: FCVT_Q_WU, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.S.D fd, fs1 + {mask: 0xfff0007f, value: 0x40100053, op: FCVT_S_D, args: argTypeList{arg_fd, arg_fs1}}, + // FCVT.S.H fd, fs1 + {mask: 0xfff0007f, value: 0x40200053, op: FCVT_S_H, args: argTypeList{arg_fd, arg_fs1}}, + // FCVT.S.L fd, rs1 + {mask: 0xfff0007f, value: 0xd0200053, op: FCVT_S_L, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.S.LU fd, rs1 + {mask: 0xfff0007f, value: 0xd0300053, op: FCVT_S_LU, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.S.Q fd, fs1 + {mask: 0xfff0007f, value: 0x40300053, op: FCVT_S_Q, args: argTypeList{arg_fd, arg_fs1}}, + // FCVT.S.W fd, rs1 + {mask: 0xfff0007f, value: 0xd0000053, op: FCVT_S_W, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.S.WU fd, rs1 + {mask: 0xfff0007f, value: 0xd0100053, op: FCVT_S_WU, args: argTypeList{arg_fd, arg_rs1}}, + // FCVT.WU.D rd, fs1 + {mask: 0xfff0007f, value: 0xc2100053, op: FCVT_WU_D, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.WU.H rd, fs1 + {mask: 0xfff0007f, value: 0xc4100053, op: FCVT_WU_H, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.WU.Q rd, fs1 + {mask: 0xfff0007f, value: 0xc6100053, op: FCVT_WU_Q, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.WU.S rd, fs1 + {mask: 0xfff0007f, value: 0xc0100053, op: FCVT_WU_S, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.W.D rd, fs1 + {mask: 0xfff0007f, value: 0xc2000053, op: FCVT_W_D, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.W.H rd, fs1 + {mask: 0xfff0007f, value: 0xc4000053, op: FCVT_W_H, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.W.Q rd, fs1 + {mask: 0xfff0007f, value: 0xc6000053, op: FCVT_W_Q, args: argTypeList{arg_rd, arg_fs1}}, + // FCVT.W.S rd, fs1 + {mask: 0xfff0007f, value: 0xc0000053, op: FCVT_W_S, args: argTypeList{arg_rd, arg_fs1}}, + // FDIV.D fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x1a000053, op: FDIV_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FDIV.H fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x1c000053, op: FDIV_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FDIV.Q fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x1e000053, op: FDIV_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FDIV.S fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x18000053, op: FDIV_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FENCE pred, succ + {mask: 0x0000707f, value: 0x0000000f, op: FENCE, args: argTypeList{arg_pred, arg_succ}}, + // FENCE.I + {mask: 0x0000707f, value: 0x0000100f, op: FENCE_I, args: argTypeList{}}, + // FEQ.D rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa2002053, op: FEQ_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FEQ.H rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa4002053, op: FEQ_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FEQ.Q rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa6002053, op: FEQ_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FEQ.S rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa0002053, op: FEQ_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLD fd, rs1_mem + {mask: 0x0000707f, value: 0x00003007, op: FLD, args: argTypeList{arg_fd, arg_rs1_mem}}, + // FLE.D rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa2000053, op: FLE_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLE.H rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa4000053, op: FLE_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLE.Q rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa6000053, op: FLE_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLE.S rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa0000053, op: FLE_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLH fd, rs1_mem + {mask: 0x0000707f, value: 0x00001007, op: FLH, args: argTypeList{arg_fd, arg_rs1_mem}}, + // FLQ fd, rs1_mem + {mask: 0x0000707f, value: 0x00004007, op: FLQ, args: argTypeList{arg_fd, arg_rs1_mem}}, + // FLT.D rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa2001053, op: FLT_D, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLT.H rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa4001053, op: FLT_H, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLT.Q rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa6001053, op: FLT_Q, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLT.S rd, fs1, fs2 + {mask: 0xfe00707f, value: 0xa0001053, op: FLT_S, args: argTypeList{arg_rd, arg_fs1, arg_fs2}}, + // FLW fd, rs1_mem + {mask: 0x0000707f, value: 0x00002007, op: FLW, args: argTypeList{arg_fd, arg_rs1_mem}}, + // FMADD.D fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x02000043, op: FMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FMADD.H fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x04000043, op: FMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FMADD.Q fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x06000043, op: FMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FMADD.S fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x00000043, op: FMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FMAX.D fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x2a001053, op: FMAX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMAX.H fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x2c001053, op: FMAX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMAX.Q fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x2e001053, op: FMAX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMAX.S fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x28001053, op: FMAX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMIN.D fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x2a000053, op: FMIN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMIN.H fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x2c000053, op: FMIN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMIN.Q fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x2e000053, op: FMIN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMIN.S fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x28000053, op: FMIN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMSUB.D fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x02000047, op: FMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FMSUB.H fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x04000047, op: FMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FMSUB.Q fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x06000047, op: FMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FMSUB.S fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x00000047, op: FMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FMUL.D fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x12000053, op: FMUL_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMUL.H fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x14000053, op: FMUL_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMUL.Q fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x16000053, op: FMUL_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMUL.S fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x10000053, op: FMUL_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FMV.D.X fd, rs1 + {mask: 0xfff0707f, value: 0xf2000053, op: FMV_D_X, args: argTypeList{arg_fd, arg_rs1}}, + // FMV.H.X fd, rs1 + {mask: 0xfff0707f, value: 0xf4000053, op: FMV_H_X, args: argTypeList{arg_fd, arg_rs1}}, + // FMV.W.X fd, rs1 + {mask: 0xfff0707f, value: 0xf0000053, op: FMV_W_X, args: argTypeList{arg_fd, arg_rs1}}, + // FMV.X.D rd, fs1 + {mask: 0xfff0707f, value: 0xe2000053, op: FMV_X_D, args: argTypeList{arg_rd, arg_fs1}}, + // FMV.X.H rd, fs1 + {mask: 0xfff0707f, value: 0xe4000053, op: FMV_X_H, args: argTypeList{arg_rd, arg_fs1}}, + // FMV.X.W rd, fs1 + {mask: 0xfff0707f, value: 0xe0000053, op: FMV_X_W, args: argTypeList{arg_rd, arg_fs1}}, + // FNMADD.D fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x0200004f, op: FNMADD_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FNMADD.H fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x0400004f, op: FNMADD_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FNMADD.Q fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x0600004f, op: FNMADD_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FNMADD.S fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x0000004f, op: FNMADD_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FNMSUB.D fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x0200004b, op: FNMSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FNMSUB.H fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x0400004b, op: FNMSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FNMSUB.Q fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x0600004b, op: FNMSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FNMSUB.S fd, fs1, fs2, fs3 + {mask: 0x0600007f, value: 0x0000004b, op: FNMSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2, arg_fs3}}, + // FSD fs2, rs1_store + {mask: 0x0000707f, value: 0x00003027, op: FSD, args: argTypeList{arg_fs2, arg_rs1_store}}, + // FSGNJN.D fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x22001053, op: FSGNJN_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJN.H fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x24001053, op: FSGNJN_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJN.Q fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x26001053, op: FSGNJN_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJN.S fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x20001053, op: FSGNJN_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJX.D fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x22002053, op: FSGNJX_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJX.H fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x24002053, op: FSGNJX_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJX.Q fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x26002053, op: FSGNJX_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJX.S fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x20002053, op: FSGNJX_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJ.D fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x22000053, op: FSGNJ_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJ.H fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x24000053, op: FSGNJ_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJ.Q fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x26000053, op: FSGNJ_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSGNJ.S fd, fs1, fs2 + {mask: 0xfe00707f, value: 0x20000053, op: FSGNJ_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSH fs2, rs1_store + {mask: 0x0000707f, value: 0x00001027, op: FSH, args: argTypeList{arg_fs2, arg_rs1_store}}, + // FSQ fs2, rs1_store + {mask: 0x0000707f, value: 0x00004027, op: FSQ, args: argTypeList{arg_fs2, arg_rs1_store}}, + // FSQRT.D fd, fs1 + {mask: 0xfff0007f, value: 0x5a000053, op: FSQRT_D, args: argTypeList{arg_fd, arg_fs1}}, + // FSQRT.H fd, fs1 + {mask: 0xfff0007f, value: 0x5c000053, op: FSQRT_H, args: argTypeList{arg_fd, arg_fs1}}, + // FSQRT.Q fd, fs1 + {mask: 0xfff0007f, value: 0x5e000053, op: FSQRT_Q, args: argTypeList{arg_fd, arg_fs1}}, + // FSQRT.S fd, fs1 + {mask: 0xfff0007f, value: 0x58000053, op: FSQRT_S, args: argTypeList{arg_fd, arg_fs1}}, + // FSUB.D fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x0a000053, op: FSUB_D, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSUB.H fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x0c000053, op: FSUB_H, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSUB.Q fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x0e000053, op: FSUB_Q, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSUB.S fd, fs1, fs2 + {mask: 0xfe00007f, value: 0x08000053, op: FSUB_S, args: argTypeList{arg_fd, arg_fs1, arg_fs2}}, + // FSW fs2, rs1_store + {mask: 0x0000707f, value: 0x00002027, op: FSW, args: argTypeList{arg_fs2, arg_rs1_store}}, + // JAL rd, jimm20 + {mask: 0x0000007f, value: 0x0000006f, op: JAL, args: argTypeList{arg_rd, arg_jimm20}}, + // JALR rd, rs1_mem + {mask: 0x0000707f, value: 0x00000067, op: JALR, args: argTypeList{arg_rd, arg_rs1_mem}}, + // LB rd, rs1_mem + {mask: 0x0000707f, value: 0x00000003, op: LB, args: argTypeList{arg_rd, arg_rs1_mem}}, + // LBU rd, rs1_mem + {mask: 0x0000707f, value: 0x00004003, op: LBU, args: argTypeList{arg_rd, arg_rs1_mem}}, + // LD rd, rs1_mem + {mask: 0x0000707f, value: 0x00003003, op: LD, args: argTypeList{arg_rd, arg_rs1_mem}}, + // LH rd, rs1_mem + {mask: 0x0000707f, value: 0x00001003, op: LH, args: argTypeList{arg_rd, arg_rs1_mem}}, + // LHU rd, rs1_mem + {mask: 0x0000707f, value: 0x00005003, op: LHU, args: argTypeList{arg_rd, arg_rs1_mem}}, + // LR.D rd, rs1_amo + {mask: 0xfff0707f, value: 0x1000302f, op: LR_D, args: argTypeList{arg_rd, arg_rs1_amo}}, + // LR.D.AQ rd, rs1_amo + {mask: 0xfff0707f, value: 0x1400302f, op: LR_D_AQ, args: argTypeList{arg_rd, arg_rs1_amo}}, + // LR.D.AQRL rd, rs1_amo + {mask: 0xfff0707f, value: 0x1600302f, op: LR_D_AQRL, args: argTypeList{arg_rd, arg_rs1_amo}}, + // LR.D.RL rd, rs1_amo + {mask: 0xfff0707f, value: 0x1200302f, op: LR_D_RL, args: argTypeList{arg_rd, arg_rs1_amo}}, + // LR.W rd, rs1_amo + {mask: 0xfff0707f, value: 0x1000202f, op: LR_W, args: argTypeList{arg_rd, arg_rs1_amo}}, + // LR.W.AQ rd, rs1_amo + {mask: 0xfff0707f, value: 0x1400202f, op: LR_W_AQ, args: argTypeList{arg_rd, arg_rs1_amo}}, + // LR.W.AQRL rd, rs1_amo + {mask: 0xfff0707f, value: 0x1600202f, op: LR_W_AQRL, args: argTypeList{arg_rd, arg_rs1_amo}}, + // LR.W.RL rd, rs1_amo + {mask: 0xfff0707f, value: 0x1200202f, op: LR_W_RL, args: argTypeList{arg_rd, arg_rs1_amo}}, + // LUI rd, imm20 + {mask: 0x0000007f, value: 0x00000037, op: LUI, args: argTypeList{arg_rd, arg_imm20}}, + // LW rd, rs1_mem + {mask: 0x0000707f, value: 0x00002003, op: LW, args: argTypeList{arg_rd, arg_rs1_mem}}, + // LWU rd, rs1_mem + {mask: 0x0000707f, value: 0x00006003, op: LWU, args: argTypeList{arg_rd, arg_rs1_mem}}, + // MAX rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0a006033, op: MAX, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // MAXU rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0a007033, op: MAXU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // MIN rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0a004033, op: MIN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // MINU rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0a005033, op: MINU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // MUL rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x02000033, op: MUL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // MULH rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x02001033, op: MULH, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // MULHSU rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x02002033, op: MULHSU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // MULHU rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x02003033, op: MULHU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // MULW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0200003b, op: MULW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // OR rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x00006033, op: OR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // ORC.B rd, rs1 + {mask: 0xfff0707f, value: 0x28705013, op: ORC_B, args: argTypeList{arg_rd, arg_rs1}}, + // ORI rd, rs1, imm12 + {mask: 0x0000707f, value: 0x00006013, op: ORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, + // ORN rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x40006033, op: ORN, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // REM rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x02006033, op: REM, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // REMU rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x02007033, op: REMU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // REMUW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0200703b, op: REMUW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // REMW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0200603b, op: REMW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // REV8 rd, rs1 + {mask: 0xfff0707f, value: 0x6b805013, op: REV8, args: argTypeList{arg_rd, arg_rs1}}, + // ROL rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x60001033, op: ROL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // ROLW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x6000103b, op: ROLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // ROR rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x60005033, op: ROR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // RORI rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x60005013, op: RORI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // RORIW rd, rs1, shamt5 + {mask: 0xfe00707f, value: 0x6000501b, op: RORIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, + // RORW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x6000503b, op: RORW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SB rs2, rs1_store + {mask: 0x0000707f, value: 0x00000023, op: SB, args: argTypeList{arg_rs2, arg_rs1_store}}, + // SC.D rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x1800302f, op: SC_D, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // SC.D.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x1c00302f, op: SC_D_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // SC.D.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x1e00302f, op: SC_D_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // SC.D.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x1a00302f, op: SC_D_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // SC.W rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x1800202f, op: SC_W, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // SC.W.AQ rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x1c00202f, op: SC_W_AQ, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // SC.W.AQRL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x1e00202f, op: SC_W_AQRL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // SC.W.RL rd, rs2, rs1_amo + {mask: 0xfe00707f, value: 0x1a00202f, op: SC_W_RL, args: argTypeList{arg_rd, arg_rs2, arg_rs1_amo}}, + // SD rs2, rs1_store + {mask: 0x0000707f, value: 0x00003023, op: SD, args: argTypeList{arg_rs2, arg_rs1_store}}, + // SEXT.B rd, rs1 + {mask: 0xfff0707f, value: 0x60401013, op: SEXT_B, args: argTypeList{arg_rd, arg_rs1}}, + // SEXT.H rd, rs1 + {mask: 0xfff0707f, value: 0x60501013, op: SEXT_H, args: argTypeList{arg_rd, arg_rs1}}, + // SH rs2, rs1_store + {mask: 0x0000707f, value: 0x00001023, op: SH, args: argTypeList{arg_rs2, arg_rs1_store}}, + // SH1ADD rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x20002033, op: SH1ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SH1ADD.UW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x2000203b, op: SH1ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SH2ADD rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x20004033, op: SH2ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SH2ADD.UW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x2000403b, op: SH2ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SH3ADD rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x20006033, op: SH3ADD, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SH3ADD.UW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x2000603b, op: SH3ADD_UW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SLL rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x00001033, op: SLL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SLLI rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x00001013, op: SLLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // SLLIW rd, rs1, shamt5 + {mask: 0xfe00707f, value: 0x0000101b, op: SLLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, + // SLLI.UW rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x0800101b, op: SLLI_UW, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // SLLW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0000103b, op: SLLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SLT rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x00002033, op: SLT, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SLTI rd, rs1, imm12 + {mask: 0x0000707f, value: 0x00002013, op: SLTI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, + // SLTIU rd, rs1, imm12 + {mask: 0x0000707f, value: 0x00003013, op: SLTIU, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, + // SLTU rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x00003033, op: SLTU, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SRA rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x40005033, op: SRA, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SRAI rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x40005013, op: SRAI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // SRAIW rd, rs1, shamt5 + {mask: 0xfe00707f, value: 0x4000501b, op: SRAIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, + // SRAW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x4000503b, op: SRAW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SRL rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x00005033, op: SRL, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SRLI rd, rs1, shamt6 + {mask: 0xfc00707f, value: 0x00005013, op: SRLI, args: argTypeList{arg_rd, arg_rs1, arg_shamt6}}, + // SRLIW rd, rs1, shamt5 + {mask: 0xfe00707f, value: 0x0000501b, op: SRLIW, args: argTypeList{arg_rd, arg_rs1, arg_shamt5}}, + // SRLW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x0000503b, op: SRLW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SUB rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x40000033, op: SUB, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SUBW rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x4000003b, op: SUBW, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // SW rs2, rs1_store + {mask: 0x0000707f, value: 0x00002023, op: SW, args: argTypeList{arg_rs2, arg_rs1_store}}, + // XNOR rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x40004033, op: XNOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // XOR rd, rs1, rs2 + {mask: 0xfe00707f, value: 0x00004033, op: XOR, args: argTypeList{arg_rd, arg_rs1, arg_rs2}}, + // XORI rd, rs1, imm12 + {mask: 0x0000707f, value: 0x00004013, op: XORI, args: argTypeList{arg_rd, arg_rs1, arg_imm12}}, + // ZEXT.H rd, rs1 + {mask: 0xfff0707f, value: 0x0800403b, op: ZEXT_H, args: argTypeList{arg_rd, arg_rs1}}, +} diff --git a/riscv64/riscv64asm/testdata/Makefile b/riscv64/riscv64asm/testdata/Makefile new file mode 100644 index 00000000..8ac7835b --- /dev/null +++ b/riscv64/riscv64asm/testdata/Makefile @@ -0,0 +1,9 @@ +go test command: + cd ..; go generate + cd ..; go test -run 'ObjdumpRISCV64TestGUNSyntaxdata' -v -timeout 10h 2>&1 | tee -a log + cd ..; go test -run 'ObjdumpRISCV64TestGoSyntaxdata' -v -timeout 10h 2>&1 | tee -a log + cd ..; go test -run 'ObjdumpRISCV64' -v -timeout 10h 2>&1 | tee -a log + cd ..; go test -run 'ObjdumpRISCV64Manual' -v -timeout 10h 2>&1 | tee -a log + cd ..; go test -run 'TestDecodeGNUSyntax' + cd ..; go test -run 'TestDecodeGoSyntax' + cd ..; go test -run '.*' diff --git a/riscv64/riscv64asm/testdata/gnucases.txt b/riscv64/riscv64asm/testdata/gnucases.txt new file mode 100644 index 00000000..dad05a7e --- /dev/null +++ b/riscv64/riscv64asm/testdata/gnucases.txt @@ -0,0 +1,390 @@ +b3027300| add x5,x6,x7 +9302f3ff| addi x5,x6,-1 +9302f37f| addi x5,x6,2047 +1305a000| li x10,10 +13000000| nop +93870900| mv x15,x19 +9b02f37f| addiw x5,x6,2047 +1b830a00| sext.w x6,x21 +bb027300| addw x5,x6,x7 +afb26300| amoadd.d x5,x6,(x7) +afb26304| amoadd.d.aq x5,x6,(x7) +afb26302| amoadd.d.rl x5,x6,(x7) +afa26300| amoadd.w x5,x6,(x7) +afa26304| amoadd.w.aq x5,x6,(x7) +afa26302| amoadd.w.rl x5,x6,(x7) +afb26360| amoand.d x5,x6,(x7) +afb26364| amoand.d.aq x5,x6,(x7) +afb26362| amoand.d.rl x5,x6,(x7) +afa26360| amoand.w x5,x6,(x7) +afa26364| amoand.w.aq x5,x6,(x7) +afa26362| amoand.w.rl x5,x6,(x7) +afb263e0| amomaxu.d x5,x6,(x7) +afb263e4| amomaxu.d.aq x5,x6,(x7) +afb263e2| amomaxu.d.rl x5,x6,(x7) +afa263e0| amomaxu.w x5,x6,(x7) +afa263e4| amomaxu.w.aq x5,x6,(x7) +afa263e2| amomaxu.w.rl x5,x6,(x7) +afb263a0| amomax.d x5,x6,(x7) +afb263a4| amomax.d.aq x5,x6,(x7) +afb263a2| amomax.d.rl x5,x6,(x7) +afa263a0| amomax.w x5,x6,(x7) +afa263a4| amomax.w.aq x5,x6,(x7) +afa263a2| amomax.w.rl x5,x6,(x7) +afb263c0| amominu.d x5,x6,(x7) +afb263c4| amominu.d.aq x5,x6,(x7) +afb263c2| amominu.d.rl x5,x6,(x7) +afa263c0| amominu.w x5,x6,(x7) +afa263c4| amominu.w.aq x5,x6,(x7) +afa263c2| amominu.w.rl x5,x6,(x7) +afb26380| amomin.d x5,x6,(x7) +afb26384| amomin.d.aq x5,x6,(x7) +afb26382| amomin.d.rl x5,x6,(x7) +afa26380| amomin.w x5,x6,(x7) +afa26384| amomin.w.aq x5,x6,(x7) +afa26382| amomin.w.rl x5,x6,(x7) +afb26340| amoor.d x5,x6,(x7) +afb26344| amoor.d.aq x5,x6,(x7) +afb26342| amoor.d.rl x5,x6,(x7) +afa26340| amoor.w x5,x6,(x7) +afa26344| amoor.w.aq x5,x6,(x7) +afa26342| amoor.w.rl x5,x6,(x7) +afb26308| amoswap.d x5,x6,(x7) +afb2630c| amoswap.d.aq x5,x6,(x7) +afb2630a| amoswap.d.rl x5,x6,(x7) +afa26308| amoswap.w x5,x6,(x7) +afa2630c| amoswap.w.aq x5,x6,(x7) +afa2630a| amoswap.w.rl x5,x6,(x7) +afb26320| amoxor.d x5,x6,(x7) +afb26324| amoxor.d.aq x5,x6,(x7) +afb26322| amoxor.d.rl x5,x6,(x7) +afa26320| amoxor.w x5,x6,(x7) +afa26324| amoxor.w.aq x5,x6,(x7) +afa26322| amoxor.w.rl x5,x6,(x7) +b3727300| and x5,x6,x7 +9372f3ff| andi x5,x6,-1 +9372f37f| andi x5,x6,2047 +97020000| auipc x5,0x0 +97028000| auipc x5,0x800 +e38062f0| beq x5,x6,-256 +e3de62ee| bge x5,x6,-260 +e3fc62ee| bgeu x5,x6,-264 +e3ca62ee| blt x5,x6,-268 +e3e862ee| bltu x5,x6,-272 +e39662ee| bne x5,x6,-276 +63940200| bnez x5,8 +63c40400| bltz x9,8 +63447000| bgtz x7,8 +63d40900| bgez x19,8 +6354d001| blez x29,8 +63040800| beqz x16,8 +f33213c0| csrrc x5,time,x6 +f3f21fc0| csrrci x5,time,31 +f32213c0| csrrs x5,time,x6 +f3e21fc0| csrrsi x5,time,31 +f31213c0| csrrw x5,time,x6 +f3d21fc0| csrrwi x5,time,31 +733015c0| csrc time,x10 +73f010c0| csrci time,1 +73253000| frcsr x10 +f3251000| frflags x11 +73262000| frrm x12 +f32400c0| rdcycle x9 +732920c0| rdinstret x18 +f32910c0| rdtime x19 +f3224014| csrr x5,sip +73201bc0| csrs time,x22 +736014c8| csrsi timeh,8 +73903700| fscsr x15 +73101800| fsflags x16 +73902800| fsrm x17 +731014c0| csrw time,x8 +735016c8| csrwi timeh,12 +b3427302| div x5,x6,x7 +b3527302| divu x5,x6,x7 +bb527302| divuw x5,x6,x7 +bb427302| divw x5,x6,x7 +73001000| ebreak +73000000| ecall +0f00f00f| fence +53f02002| fadd.d f0,f1,f2 +53f02004| fadd.h f0,f1,f2 +53f02006| fadd.q f0,f1,f2 +53f02000| fadd.s f0,f1,f2 +d31200e2| fclass.d x5,f0 +d31200e4| fclass.h x5,f0 +d31200e6| fclass.q x5,f0 +d31200e0| fclass.s x5,f0 +53f022d2| fcvt.d.l f0,x5 +53f032d2| fcvt.d.lu f0,x5 +53f03042| fcvt.d.q f0,f1 +53800042| fcvt.d.s f0,f1 +538002d2| fcvt.d.w f0,x5 +538012d2| fcvt.d.wu f0,x5 +53f022d4| fcvt.h.l f0,x5 +53f032d4| fcvt.h.lu f0,x5 +53f00044| fcvt.h.s f0,f1 +53f002d4| fcvt.h.w f0,x5 +53f012d4| fcvt.h.wu f0,x5 +d37230c2| fcvt.lu.d x5,f0 +d37230c4| fcvt.lu.h x5,f0 +d37230c6| fcvt.lu.q x5,f0 +d37230c0| fcvt.lu.s x5,f0 +d37220c2| fcvt.l.d x5,f0 +d37220c4| fcvt.l.h x5,f0 +d37220c6| fcvt.l.q x5,f0 +d37220c0| fcvt.l.s x5,f0 +53801046| fcvt.q.d f0,f1 +538022d6| fcvt.q.l f0,x5 +538032d6| fcvt.q.lu f0,x5 +53800046| fcvt.q.s f0,f1 +538002d6| fcvt.q.w f0,x5 +538012d6| fcvt.q.wu f0,x5 +53f01040| fcvt.s.d f0,f1 +53802040| fcvt.s.h f0,f1 +53f022d0| fcvt.s.l f0,x5 +53f032d0| fcvt.s.lu f0,x5 +53f03040| fcvt.s.q f0,f1 +53f002d0| fcvt.s.w f0,x5 +53f012d0| fcvt.s.wu f0,x5 +d37210c2| fcvt.wu.d x5,f0 +d37210c4| fcvt.wu.h x5,f0 +d37210c6| fcvt.wu.q x5,f0 +d37210c0| fcvt.wu.s x5,f0 +d37200c2| fcvt.w.d x5,f0 +d37200c4| fcvt.w.h x5,f0 +d37200c6| fcvt.w.q x5,f0 +d37200c0| fcvt.w.s x5,f0 +53f0201a| fdiv.d f0,f1,f2 +53f0201c| fdiv.h f0,f1,f2 +53f0201e| fdiv.q f0,f1,f2 +53f02018| fdiv.s f0,f1,f2 +0f00f00f| fence +0f100000| fence.i +d32210a2| feq.d x5,f0,f1 +d32210a4| feq.h x5,f0,f1 +d32210a6| feq.q x5,f0,f1 +d32210a0| feq.s x5,f0,f1 +07b0f27f| fld f0,2047(x5) +d30210a2| fle.d x5,f0,f1 +d30210a4| fle.h x5,f0,f1 +d30210a6| fle.q x5,f0,f1 +d30210a0| fle.s x5,f0,f1 +0790f27f| flh f0,2047(x5) +07c0f27f| flq f0,2047(x5) +d31210a2| flt.d x5,f0,f1 +d31210a4| flt.h x5,f0,f1 +d31210a6| flt.q x5,f0,f1 +d31210a0| flt.s x5,f0,f1 +07a0f27f| flw f0,2047(x5) +43f0201a| fmadd.d f0,f1,f2,f3 +43f0201c| fmadd.h f0,f1,f2,f3 +43f0201e| fmadd.q f0,f1,f2,f3 +43f02018| fmadd.s f0,f1,f2,f3 +5390202a| fmax.d f0,f1,f2 +5390202c| fmax.h f0,f1,f2 +5390202e| fmax.q f0,f1,f2 +53902028| fmax.s f0,f1,f2 +5380202a| fmin.d f0,f1,f2 +5380202c| fmin.h f0,f1,f2 +5380202e| fmin.q f0,f1,f2 +53802028| fmin.s f0,f1,f2 +47f0201a| fmsub.d f0,f1,f2,f3 +47f0201c| fmsub.h f0,f1,f2,f3 +47f0201e| fmsub.q f0,f1,f2,f3 +47f02018| fmsub.s f0,f1,f2,f3 +53f02012| fmul.d f0,f1,f2 +53f02014| fmul.h f0,f1,f2 +53f02016| fmul.q f0,f1,f2 +53f02010| fmul.s f0,f1,f2 +538002f2| fmv.d.x f0,x5 +538002f4| fmv.h.x f0,x5 +d30200e2| fmv.x.d x5,f0 +d30200e4| fmv.x.h x5,f0 +d30200e0| fmv.x.w x5,f0 +4ff0201a| fnmadd.d f0,f1,f2,f3 +4ff0201c| fnmadd.h f0,f1,f2,f3 +4ff0201e| fnmadd.q f0,f1,f2,f3 +4ff02018| fnmadd.s f0,f1,f2,f3 +4bf0201a| fnmsub.d f0,f1,f2,f3 +4bf0201c| fnmsub.h f0,f1,f2,f3 +4bf0201e| fnmsub.q f0,f1,f2,f3 +4bf02018| fnmsub.s f0,f1,f2,f3 +a7bf027e| fsd f0,2047(x5) +53902022| fsgnjn.d f0,f1,f2 +53902024| fsgnjn.h f0,f1,f2 +53902026| fsgnjn.q f0,f1,f2 +53902020| fsgnjn.s f0,f1,f2 +53a02022| fsgnjx.d f0,f1,f2 +53a02024| fsgnjx.h f0,f1,f2 +53a02026| fsgnjx.q f0,f1,f2 +53a02020| fsgnjx.s f0,f1,f2 +53802022| fsgnj.d f0,f1,f2 +53802024| fsgnj.h f0,f1,f2 +53802026| fsgnj.q f0,f1,f2 +53802020| fsgnj.s f0,f1,f2 +53a01022| fabs.d f0,f1 +53a49420| fabs.s f8,f9 +d305c622| fmv.d f11,f12 +d306e720| fmv.s f13,f14 +d3170823| fneg.d f15,f16 +d398f720| fneg.s f17,f15 +a79f027e| fsh f0,2047(x5) +a7cf027e| fsq f0,2047(x5) +53f0005a| fsqrt.d f0,f1 +53f0005c| fsqrt.h f0,f1 +53f0005e| fsqrt.q f0,f1 +53f00058| fsqrt.s f0,f1 +53f0200a| fsub.d f0,f1,f2 +53f0200c| fsub.h f0,f1,f2 +53f0200e| fsub.q f0,f1,f2 +53f02008| fsub.s f0,f1,f2 +a7af027e| fsw f0,2047(x5) +6ff0dfcb| j -836 +eff09fcb| jal -840 +eff25fcb| jal x5,-844 +67800200| jr x5 +e7800202| jalr x1,32(x5) +67800000| ret +6700a500| jr 10(x10) +8302f37f| lb x5,2047(x6) +8342f37f| lbu x5,2047(x6) +af320310| lr.d x5,(x6) +af320314| lr.d.aq x5,(x6) +af320312| lr.d.rl x5,(x6) +af220310| lr.w x5,(x6) +af220314| lr.w.aq x5,(x6) +af220312| lr.w.rl x5,(x6) +b7829102| lui x5,0x2918 +8322f37f| lw x5,2047(x6) +8362f37f| lwu x5,2047(x6) +b3027302| mul x5,x6,x7 +b3127302| mulh x5,x6,x7 +b3227302| mulhsu x5,x6,x7 +b3327302| mulhu x5,x6,x7 +bb027302| mulw x5,x6,x7 +b3627300| or x5,x6,x7 +93620380| ori x5,x6,-2048 +b3627302| rem x5,x6,x7 +b3727302| remu x5,x6,x7 +bb627302| remw x5,x6,x7 +a30f537e| sb x5,2047(x6) +afb26318| sc.d x5,x6,(x7) +afb2631c| sc.d.aq x5,x6,(x7) +afb2631a| sc.d.rl x5,x6,(x7) +afa26318| sc.w x5,x6,(x7) +afa2631c| sc.w.aq x5,x6,(x7) +afa2631a| sc.w.rl x5,x6,(x7) +a33f537e| sd x5,2047(x6) +23105380| sh x5,-2048(x6) +b3127300| sll x5,x6,x7 +93124303| slli x5,x6,0x34 +9b127301| slliw x5,x6,0x17 +b3227300| slt x5,x6,x7 +b3226000| sgtz x5,x6 +b32e0f00| sltz x29,x30 +9322f37f| slti x5,x6,2047 +93320380| sltiu x5,x6,-2048 +93321300| seqz x5,x6 +b3327300| sltu x5,x6,x7 +33394001| snez x18,x20 +b3527340| sra x5,x6,x7 +93524343| srai x5,x6,0x34 +9b526341| sraiw x5,x6,0x16 +bb527340| sraw x5,x6,x7 +b3527300| srl x5,x6,x7 +93524303| srli x5,x6,0x34 +9b526301| srliw x5,x6,0x16 +bb527300| srlw x5,x6,x7 +b3027340| sub x5,x6,x7 +b3026040| neg x5,x6 +bb027340| subw x5,x6,x7 +3b0ff041| negw x30,x31 +a32f537e| sw x5,2047(x6) +b3427300| xor x5,x6,x7 +9342f37f| xori x5,x6,2047 +93c2ffff| not x5,x31 +bb003108| add.uw x1,x2,x3 +33a26220| sh1add x4,x5,x6 +bb239420| sh1add.uw x7,x8,x9 +33c5c520| sh2add x10,x11,x12 +bb46f720| sh2add.uw x13,x14,x15 +33e82821| sh3add x16,x17,x18 +bb695a21| sh3add.uw x19,x20,x21 +1b9b7b09| slli.uw x22,x23,0x17 +33fcac41| andn x24,x25,x26 +b36dde41| orn x27,x28,x29 +33cf1f40| xnor x30,x31,x1 +13910160| clz x2,x3 +1b920260| clzw x4,x5 +13931360| ctz x6,x7 +1b941460| ctzw x8,x9 +13952560| cpop x10,x11 +1b962660| cpopw x12,x13 +33e7070b| max x14,x15,x16 +b378390b| maxu x17,x18,x19 +33ca6a0b| min x20,x21,x22 +b35b9c0b| minu x23,x24,x25 +139d4d60| sext.b x26,x27 +139e5e60| sext.h x28,x29 +3bcf0f08| zext.h x30,x31 +b3102060| rol x1,x0,x2 +bb115260| rolw x3,x4,x5 +33d38360| ror x6,x7,x8 +9354a560| rori x9,x10,0xa +9b55e660| roriw x11,x12,0xe +bb56f760| rorw x13,x14,x15 +13d87828| orc.b x16,x17 +13d9896b| rev8 x18,x19 +339a6a49| bclr x20,x21,x22 +931bfc48| bclri x23,x24,0xf +b35cbd49| bext x25,x26,x27 +13de8e48| bexti x28,x29,0x8 +339f0f68| binv x30,x31,x0 +9310016a| binvi x1,x2,0x20 +b3115228| bset x3,x4,x5 +1393f32b| bseti x6,x7,0x3f +4000| addi x8,x2,4 +2041| lw x8,64(x10) +94d0| sw x13,32(x9) +0100| nop +811f| addi x31,x31,-32 +4111| addi x2,x2,-16 +8158| li x17,-32 +4161| addi x2,x2,16 +4163| lui x6,0x10 +819b| andi x15,x15,-32 +0d8c| sub x8,x8,x11 +b18c| xor x9,x9,x12 +558c| or x8,x8,x13 +f98c| and x9,x9,x14 +01a8| j 16 +99c5| beqz x11,14 +85e3| bnez x15,32 +c248| lw x17,16(x2) +8283| jr x7 +fa88| mv x17,x30 +0290| ebreak +0295| jalr x10 +c297| add x15,x15,x16 +76c4| sw x29,8(x2) +8873| ld x10,32(x15) +00ea| sd x8,16(x12) +3d31| addiw x2,x2,-17 +2180| srli x8,x8,0x8 +c184| srai x9,x9,0x10 +919d| subw x11,x11,x12 +b99e| addw x13,x13,x14 +4a01| slli x2,x2,0x12 +027d| ld x26,32(x2) +a260| ld x1,8(x2) +864d| lw x27,64(x2) +2021| fld f8,64(x10) +8cb0| fsd f11,32(x9) +8624| fld f9,64(x2) +3eb0| fsd f15,32(x2) +0000| unimp +ab| illegalins +f3| illegalins +abc3| illegalins +abcde3| illegalins diff --git a/riscv64/riscv64asm/testdata/plan9cases.txt b/riscv64/riscv64asm/testdata/plan9cases.txt new file mode 100644 index 00000000..d38c5eba --- /dev/null +++ b/riscv64/riscv64asm/testdata/plan9cases.txt @@ -0,0 +1,336 @@ +b3027300| ADD X7, X6, X5 +9302f3ff| ADDI $-1, X6, X5 +9302f37f| ADDI $2047, X6, X5 +93870900| MOV X19, X15 +93070100| MOV X2, X15 +9b02f37f| ADDIW $2047, X6, X5 +1b830a00| MOVW X21, X6 +1b810a00| MOVW X21, X2 +bb027300| ADDW X7, X6, X5 +afb26300| AMOADDD X6, (X7), X5 +afb26304| AMOADDD X6, (X7), X5 +afb26302| AMOADDD X6, (X7), X5 +afa26300| AMOADDW X6, (X7), X5 +afa26304| AMOADDW X6, (X7), X5 +afa26302| AMOADDW X6, (X7), X5 +afb26360| AMOANDD X6, (X7), X5 +afb26364| AMOANDD X6, (X7), X5 +afb26362| AMOANDD X6, (X7), X5 +afa26360| AMOANDW X6, (X7), X5 +afa26364| AMOANDW X6, (X7), X5 +afa26362| AMOANDW X6, (X7), X5 +afb263e0| AMOMAXUD X6, (X7), X5 +afb263e4| AMOMAXUD X6, (X7), X5 +afb263e2| AMOMAXUD X6, (X7), X5 +afa263e0| AMOMAXUW X6, (X7), X5 +afa263e4| AMOMAXUW X6, (X7), X5 +afa263e2| AMOMAXUW X6, (X7), X5 +afb263a0| AMOMAXD X6, (X7), X5 +afb263a4| AMOMAXD X6, (X7), X5 +afb263a2| AMOMAXD X6, (X7), X5 +afa263a0| AMOMAXW X6, (X7), X5 +afa263a4| AMOMAXW X6, (X7), X5 +afa263a2| AMOMAXW X6, (X7), X5 +afb263c0| AMOMINUD X6, (X7), X5 +afb263c4| AMOMINUD X6, (X7), X5 +afb263c2| AMOMINUD X6, (X7), X5 +afa263c0| AMOMINUW X6, (X7), X5 +afa263c4| AMOMINUW X6, (X7), X5 +afa263c2| AMOMINUW X6, (X7), X5 +afb26380| AMOMIND X6, (X7), X5 +afb26384| AMOMIND X6, (X7), X5 +afb26382| AMOMIND X6, (X7), X5 +afa26380| AMOMINW X6, (X7), X5 +afa26384| AMOMINW X6, (X7), X5 +afa26382| AMOMINW X6, (X7), X5 +afb26340| AMOORD X6, (X7), X5 +afb26344| AMOORD X6, (X7), X5 +afb26342| AMOORD X6, (X7), X5 +afa26340| AMOORW X6, (X7), X5 +afa26344| AMOORW X6, (X7), X5 +afa26342| AMOORW X6, (X7), X5 +afb26308| AMOSWAPD X6, (X7), X5 +afb2630c| AMOSWAPD X6, (X7), X5 +afb2630a| AMOSWAPD X6, (X7), X5 +afa26308| AMOSWAPW X6, (X7), X5 +afa2630c| AMOSWAPW X6, (X7), X5 +afa2630a| AMOSWAPW X6, (X7), X5 +afb26320| AMOXORD X6, (X7), X5 +afb26324| AMOXORD X6, (X7), X5 +afb26322| AMOXORD X6, (X7), X5 +afa26320| AMOXORW X6, (X7), X5 +afa26324| AMOXORW X6, (X7), X5 +afa26322| AMOXORW X6, (X7), X5 +b3727300| AND X7, X6, X5 +9372f3ff| ANDI $-1, X6, X5 +9372f37f| ANDI $2047, X6, X5 +9372f30f| MOVBU X6, X5 +97020000| AUIPC $0, X5 +97028000| AUIPC $2048, X5 +e38062f0| BEQ X5, X6, -64(PC) +e3de62ee| BGE X5, X6, -65(PC) +e3fc62ee| BGEU X5, X6, -66(PC) +e3ca62ee| BLT X5, X6, -67(PC) +e3e862ee| BLTU X5, X6, -68(PC) +e39662ee| BNE X5, X6, -69(PC) +e30403ee| BEQZ X6, -70(PC) +e35203ee| BGEZ X6, -71(PC) +e34003ee| BLTZ X6, -72(PC) +e31e03ec| BNEZ X6, -73(PC) +f33213c0| CSRRC X6, TIME, X5 +f3f21fc0| CSRRCI $31, TIME, X5 +f32213c0| CSRRS X6, TIME, X5 +f3e21fc0| CSRRSI $31, TIME, X5 +f31213c0| CSRRW X6, TIME, X5 +f3d21fc0| CSRRWI $31, TIME, X5 +733015c0| CSRRC X10, TIME, X0 +73f010c0| CSRRCI $1, TIME, X0 +73253000| FRCSR X10 +f3251000| FRFLAGS X11 +73262000| FRRM X12 +f32400c0| RDCYCLE X9 +732920c0| RDINSTRET X18 +f32910c0| RDTIME X19 +f3224014| CSRRS X0, SIP, X5 +73201bc0| CSRRS X22, TIME, X0 +736014c8| CSRRSI $8, TIMEH, X0 +73903700| FSCSR X15, X0 +73101800| FSFLAGS X16, X0 +73902800| FSRM X17, X0 +731014c0| CSRRW X8, TIME, X0 +735016c8| CSRRWI $12, TIMEH, X0 +b3427302| DIV X7, X6, X5 +b3527302| DIVU X7, X6, X5 +bb527302| DIVUW X7, X6, X5 +bb427302| DIVW X7, X6, X5 +73001000| EBREAK +73000000| ECALL +53f02002| FADDD F2, F1, F0 +53f02004| FADDH F2, F1, F0 +53f02006| FADDQ F2, F1, F0 +53f02000| FADDS F2, F1, F0 +d31200e2| FCLASSD F0, X5 +d31200e4| FCLASSH F0, X5 +d31200e6| FCLASSQ F0, X5 +d31200e0| FCLASSS F0, X5 +53f022d2| FCVTDL X5, F0 +53f032d2| FCVTDLU X5, F0 +53f03042| FCVTDQ F1, F0 +53800042| FCVTDS F1, F0 +538002d2| FCVTDW X5, F0 +538012d2| FCVTDWU X5, F0 +53f022d4| FCVTHL X5, F0 +53f032d4| FCVTHLU X5, F0 +53f00044| FCVTHS F1, F0 +53f002d4| FCVTHW X5, F0 +53f012d4| FCVTHWU X5, F0 +d37230c2| FCVTLUD F0, X5 +d37230c4| FCVTLUH F0, X5 +d37230c6| FCVTLUQ F0, X5 +d37230c0| FCVTLUS F0, X5 +d37220c2| FCVTLD F0, X5 +d37220c4| FCVTLH F0, X5 +d37220c6| FCVTLQ F0, X5 +d37220c0| FCVTLS F0, X5 +53801046| FCVTQD F1, F0 +538022d6| FCVTQL X5, F0 +538032d6| FCVTQLU X5, F0 +53800046| FCVTQS F1, F0 +538002d6| FCVTQW X5, F0 +538012d6| FCVTQWU X5, F0 +53f01040| FCVTSD F1, F0 +53802040| FCVTSH F1, F0 +53f022d0| FCVTSL X5, F0 +53f032d0| FCVTSLU X5, F0 +53f03040| FCVTSQ F1, F0 +53f002d0| FCVTSW X5, F0 +53f012d0| FCVTSWU X5, F0 +d37210c2| FCVTWUD F0, X5 +d37210c4| FCVTWUH F0, X5 +d37210c6| FCVTWUQ F0, X5 +d37210c0| FCVTWUS F0, X5 +d37200c2| FCVTWD F0, X5 +d37200c4| FCVTWH F0, X5 +d37200c6| FCVTWQ F0, X5 +d37200c0| FCVTWS F0, X5 +53f0201a| FDIVD F2, F1, F0 +53f0201c| FDIVH F2, F1, F0 +53f0201e| FDIVQ F2, F1, F0 +53f02018| FDIVS F2, F1, F0 +0f00f00f| FENCE +0f100000| FENCEI +d32210a2| FEQD F1, F0, X5 +d32210a4| FEQH F1, F0, X5 +d32210a6| FEQQ F1, F0, X5 +d32210a0| FEQS F1, F0, X5 +07b0f27f| MOVD F0, 2047(X5) +d30210a2| FLED F1, F0, X5 +d30210a4| FLEH F1, F0, X5 +d30210a6| FLEQ F1, F0, X5 +d30210a0| FLES F1, F0, X5 +0790f27f| FLH 2047(X5), F0 +07c0f27f| FLQ 2047(X5), F0 +d31210a2| FLTD F1, F0, X5 +d31210a4| FLTH F1, F0, X5 +d31210a6| FLTQ F1, F0, X5 +d31210a0| FLTS F1, F0, X5 +07a0f27f| MOVF F0, 2047(X5) +43f0201a| FMADDD F1, F2, F3, F0 +43f0201c| FMADDH F1, F2, F3, F0 +43f0201e| FMADDQ F1, F2, F3, F0 +43f02018| FMADDS F1, F2, F3, F0 +5390202a| FMAXD F2, F1, F0 +5390202c| FMAXH F2, F1, F0 +5390202e| FMAXQ F2, F1, F0 +53902028| FMAXS F2, F1, F0 +5380202a| FMIND F2, F1, F0 +5380202c| FMINH F2, F1, F0 +5380202e| FMINQ F2, F1, F0 +53802028| FMINS F2, F1, F0 +47f0201a| FMSUBD F1, F2, F3, F0 +47f0201c| FMSUBH F1, F2, F3, F0 +47f0201e| FMSUBQ F1, F2, F3, F0 +47f02018| FMSUBS F1, F2, F3, F0 +53f02012| FMULD F2, F1, F0 +53f02014| FMULH F2, F1, F0 +53f02016| FMULQ F2, F1, F0 +53f02010| FMULS F2, F1, F0 +538002f2| FMVDX X5, F0 +538002f4| FMVHX X5, F0 +d30200e2| FMVXD F0, X5 +d30200e4| FMVXH F0, X5 +d30200e0| FMVXW F0, X5 +4ff0201a| FNMADDD F1, F2, F3, F0 +4ff0201c| FNMADDH F1, F2, F3, F0 +4ff0201e| FNMADDQ F1, F2, F3, F0 +4ff02018| FNMADDS F1, F2, F3, F0 +4bf0201a| FNMSUBD F1, F2, F3, F0 +4bf0201c| FNMSUBH F1, F2, F3, F0 +4bf0201e| FNMSUBQ F1, F2, F3, F0 +4bf02018| FNMSUBS F1, F2, F3, F0 +a7bf027e| MOVD 2047(X5), F0 +53902022| FSGNJND F2, F1, F0 +53902024| FSGNJNH F2, F1, F0 +53902026| FSGNJNQ F2, F1, F0 +53902020| FSGNJNS F2, F1, F0 +53a02022| FSGNJXD F2, F1, F0 +53a02024| FSGNJXH F2, F1, F0 +53a02026| FSGNJXQ F2, F1, F0 +53a02020| FSGNJXS F2, F1, F0 +53802022| FSGNJD F2, F1, F0 +53802024| FSGNJH F2, F1, F0 +53802026| FSGNJQ F2, F1, F0 +53802020| FSGNJS F2, F1, F0 +a79f027e| FSH 2047(X5), F0 +a7cf027e| FSQ 2047(X5), F0 +53f0005a| FSQRTD F1, F0 +53f0005c| FSQRTH F1, F0 +53f0005e| FSQRTQ F1, F0 +53f00058| FSQRTS F1, F0 +53f0200a| FSUBD F2, F1, F0 +53f0200c| FSUBH F2, F1, F0 +53f0200e| FSUBQ F2, F1, F0 +53f02008| FSUBS F2, F1, F0 +a7af027e| MOVF 2047(X5), F0 +6ff0dfcb| JMP -209(PC) +eff09fcb| CALL -210(PC) +eff25fcb| JAL X5, -211(PC) +67800202| JMP 32(X5) +e7800202| CALL 32(X5) +e7820202| JALR X5, 32(X5) +67800000| RET +8302f37f| MOVB 2047(X6), X5 +8342f37f| MOVBU 2047(X6), X5 +af320310| LRD (X6), X5 +af320314| LRD (X6), X5 +af320312| LRD (X6), X5 +af220310| LRW (X6), X5 +af220314| LRW (X6), X5 +af220312| LRW (X6), X5 +b7829102| LUI $10520, X5 +8322f37f| MOVW 2047(X6), X5 +8362f37f| MOVWU 2047(X6), X5 +b3027302| MUL X7, X6, X5 +b3127302| MULH X7, X6, X5 +b3227302| MULHSU X7, X6, X5 +b3327302| MULHU X7, X6, X5 +bb027302| MULW X7, X6, X5 +b3627300| OR X7, X6, X5 +93620380| ORI $-2048, X6, X5 +b3627302| REM X7, X6, X5 +b3727302| REMU X7, X6, X5 +bb627302| REMW X7, X6, X5 +a30f537e| MOVB X5, 2047(X6) +afb26318| SCD X6, (X7), X5 +afb2631c| SCD X6, (X7), X5 +afb2631a| SCD X6, (X7), X5 +afa26318| SCW X6, (X7), X5 +afa2631c| SCW X6, (X7), X5 +afa2631a| SCW X6, (X7), X5 +a33f537e| MOV X5, 2047(X6) +23105380| MOVH X5, -2048(X6) +b3127300| SLL X7, X6, X5 +93124303| SLLI $52, X6, X5 +9b127301| SLLIW $23, X6, X5 +b3227300| SLT X7, X6, X5 +9322f37f| SLTI $2047, X6, X5 +93320380| SLTIU $-2048, X6, X5 +93321300| SEQZ X6, X5 +b3327300| SLTU X7, X6, X5 +33394001| SNEZ X20, X18 +b3527340| SRA X7, X6, X5 +93524343| SRAI $52, X6, X5 +9b526341| SRAIW $22, X6, X5 +bb527340| SRAW X7, X6, X5 +b3527300| SRL X7, X6, X5 +93524303| SRLI $52, X6, X5 +9b526301| SRLIW $22, X6, X5 +bb527300| SRLW X7, X6, X5 +b3027340| SUB X7, X6, X5 +b3026040| NEG X6, X5 +bb027340| SUBW X7, X6, X5 +a32f537e| MOVW X5, 2047(X6) +b3427300| XOR X7, X6, X5 +9342f37f| XORI $2047, X6, X5 +93c2ffff| NOT X31, X5 +bb003108| ADDUW X3, X2, X1 +33a26220| SH1ADD X6, X5, X4 +bb239420| SH1ADDUW X9, X8, X7 +33c5c520| SH2ADD X12, X11, X10 +bb46f720| SH2ADDUW X15, X14, X13 +33e82821| SH3ADD X18, X17, X16 +bb695a21| SH3ADDUW X21, X20, X19 +1b9b7b09| SLLIUW $23, X23, X22 +33fcac41| ANDN X26, X25, X24 +b36dde41| ORN X29, X28, X27 +33cf1f40| XNOR X1, X31, X30 +13910160| CLZ X3, X2 +1b920260| CLZW X5, X4 +13931360| CTZ X7, X6 +1b941460| CTZW X9, X8 +13952560| CPOP X11, X10 +1b962660| CPOPW X13, X12 +33e7070b| MAX X16, X15, X14 +b378390b| MAXU X19, X18, X17 +33ca6a0b| MIN X22, X21, X20 +b35b9c0b| MINU X25, X24, X23 +139d4d60| SEXTB X27, X26 +139e5e60| SEXTH X29, X28 +3bcf0f08| ZEXTH X31, X30 +b3102060| ROL X2, X0, X1 +bb115260| ROLW X5, X4, X3 +33d38360| ROR X8, X7, X6 +9354a560| RORI $10, X10, X9 +9b55e660| RORIW $14, X12, X11 +bb56f760| RORW X15, X14, X13 +13d87828| ORCB X17, X16 +13d9896b| REV8 X19, X18 +339a6a49| BCLR X22, X21, X20 +931bfc48| BCLRI $15, X24, X23 +b35cbd49| BEXT X27, X26, X25 +13de8e48| BEXTI $8, X29, X28 +339f0f68| BINV X0, X31, X30 +9310016a| BINVI $32, X2, X1 +b3115228| BSET X5, X4, X3 +1393f32b| BSETI $63, X7, X6 +0000| UNIMP diff --git a/riscv64/riscv64spec/spec.go b/riscv64/riscv64spec/spec.go new file mode 100644 index 00000000..5b80c868 --- /dev/null +++ b/riscv64/riscv64spec/spec.go @@ -0,0 +1,475 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// riscv64spec reads the files contained in riscv-opcodes repo +// to collect instruction encoding details. +// repo url: https://github.com/riscv/riscv-opcodes +// usage: go run spec.go + +package main + +import ( + "bufio" + "fmt" + "log" + "os" + "path/filepath" + "sort" + "strconv" + "strings" +) + +// RV64GC_zba_zbb_zbs Extensions Listing +// Reference: $GOROOT/src/src/cmd/internal/obj/riscv/inst.go +var extensions = []string{ + "rv_a", + "rv_c", + "rv_c_d", + "rv_d", + "rv_f", + "rv_i", + "rv_m", + "rv_q", + "rv_zba", + "rv_zbb", + "rv_zbs", + "rv_zfh", + "rv_zicsr", + "rv_zifencei", + "rv64_a", + "rv64_c", + "rv64_d", + "rv64_f", + "rv64_i", + "rv64_m", + "rv64_q", + "rv64_zba", + "rv64_zbb", + "rv64_zbs", + "rv64_zfh", +} + +const ( + prologueSec = "// Code generated by riscv64spec riscv-opcodes\n// DO NOT EDIT\n\n// Copyright 2024 The Go Authors. All rights reserved.\n// Use of this source code is governed by a BSD-style\n// license that can be found in the LICENSE file.\n\npackage riscv64asm\n\n" + opSec = "const (\n\t_ Op = iota\n" + opstrSec = "var opstr = [...]string{\n" + instFormatsSec = "var instFormats = [...]instFormat{\n" +) + +var ( + ops []string + opstrs = make(map[string]string) + instFormatComments = make(map[string]string) + instFormats = make(map[string]string) +) + +func main() { + log.SetFlags(0) + log.SetPrefix("riscv64spec: ") + + if len(os.Args) < 2 { + log.Fatal("usage: go run spec.go ") + } + extensionsPath := filepath.Join(os.Args[1], "extensions") + + fileTables, err := os.Create("tables.go") + if err != nil { + log.Fatal(err) + } + + buf := bufio.NewWriter(fileTables) + _, err = buf.Write([]byte(prologueSec)) + if err != nil { + log.Fatal(err) + } + + for _, ext := range extensions { + f, err := os.Open(filepath.Join(extensionsPath, ext)) + if err != nil { + log.Fatal(err) + } + defer f.Close() + + buf := bufio.NewScanner(f) + for buf.Scan() { + line := buf.Text() + if len(line) == 0 { + continue + } + words := strings.Fields(line) + if len(words) == 0 || words[0][0] == '#' { + continue + } + + // skip $pseudo_op except rv_zbb/rv64_zbb + if words[0][0] == '$' { + if ext != "rv_zbb" && ext != "rv64_zbb" { + continue + } + words = words[2:] + } + + genInst(words) + } + } + + // c.unimp wasn't in riscv-opcodes, so add it there + c_unimp := "c.unimp 15..0=0" + genInst(strings.Fields(c_unimp)) + + sort.Strings(ops) + + // 1. write op + if _, err := buf.Write([]byte(opSec)); err != nil { + log.Fatal(err) + } + for _, op := range ops { + if _, err := fmt.Fprintf(buf, "\t%s\n", op); err != nil { + log.Fatal(err) + } + } + if _, err := buf.Write([]byte(")\n\n")); err != nil { + log.Fatal(err) + } + + // 2. write opstr + if _, err := buf.Write([]byte(opstrSec)); err != nil { + log.Fatal(err) + } + for _, op := range ops { + if _, err := fmt.Fprintf(buf, "\t%s\n", opstrs[op]); err != nil { + log.Fatal(err) + } + } + if _, err := buf.Write([]byte("}\n\n")); err != nil { + log.Fatal(err) + } + + // 3. write instFormatComment and instFormat + if _, err := buf.Write([]byte(instFormatsSec)); err != nil { + log.Fatal(err) + } + for _, op := range ops { + if _, err := fmt.Fprintf(buf, "\t%s\n\t%s\n", instFormatComments[op], instFormats[op]); err != nil { + log.Fatal(err) + } + } + if _, err = buf.Write([]byte("}\n")); err != nil { + log.Fatal(err) + } + + if err := buf.Flush(); err != nil { + log.Fatal(err) + } + + if err := fileTables.Close(); err != nil { + log.Fatal(err) + } +} + +func genInst(words []string) { + op := strings.ToUpper(strings.Replace(words[0], ".", "_", -1)) + opstr := fmt.Sprintf("%s:\t\"%s\",", op, strings.ToUpper(words[0])) + + var value uint32 + var mask uint32 + var argTypeList []string + + for i := 1; i < len(words); i++ { + if strings.Contains(words[i], "=") { + val := strings.Split(words[i], "=") + sec := strings.Split(val[0], "..") + if len(sec) < 2 { + sec[0] = val[0] + } + subval, submsk := genValueAndMask(val, sec) + value |= subval + mask |= submsk + } else if len(words[i]) > 0 { + argTypeList = append(argTypeList, words[i]) + } + } + + instArgsStr := inferFormats(argTypeList, op) + instFormatComment := "// " + strings.Replace(op, "_", ".", -1) + " " + strings.Replace(instArgsStr, "arg_", "", -1) + instFormat := fmt.Sprintf("{mask: %#08x, value: %#08x, op: %s, args: argTypeList{%s}},", mask, value, op, instArgsStr) + + // Handle the suffix of atomic instruction. + if isAtomic(op) { + suffix := []string{"", ".RL", ".AQ", ".AQRL"} + // Re-generate the opcode string, opcode value and mask. + for i, suf := range suffix { + aop := op + strings.Replace(suf, ".", "_", -1) + aopstr := fmt.Sprintf("%s:\t\"%s\",", aop, strings.ToUpper(words[0])+suf) + avalue := value | (uint32(i) << 25) + amask := mask | 0x06000000 + ainstFormatComment := "// " + strings.Replace(aop, "_", ".", -1) + " " + strings.Replace(instArgsStr, "arg_", "", -1) + ainstFormat := fmt.Sprintf("{mask: %#08x, value: %#08x, op: %s, args: argTypeList{%s}},", amask, avalue, aop, instArgsStr) + ops = append(ops, aop) + opstrs[aop] = aopstr + instFormats[aop] = ainstFormat + instFormatComments[aop] = ainstFormatComment + } + } else { + ops = append(ops, op) + opstrs[op] = opstr + instFormats[op] = instFormat + instFormatComments[op] = instFormatComment + } +} + +// inferFormats identifies inst format: +// R-Type (inst rd, rs1, rs2), +// I-Type (inst rd, rs1, imm / inst rd, offset(rs1)), +// UJ-Type (inst rd, imm), +// U-Type (inst rd, imm), +// SB-Type (inst rs1, rs2, offset) +// S-Type (inst rs2, offset(rs1)) +func inferFormats(argTypeList []string, op string) string { + switch { + case strings.Contains(op, "AMO") || strings.Contains(op, "SC_"): + return "arg_rd, arg_rs2, arg_rs1_amo" + + case strings.Contains(op, "LR_"): + return "arg_rd, arg_rs1_amo" + + case op == "LB" || op == "LBU" || op == "LD" || + op == "LH" || op == "LHU" || op == "LW" || op == "LWU": + return "arg_rd, arg_rs1_mem" + + case op == "FLD" || op == "FLW" || op == "FLH" || op == "FLQ": + return "arg_fd, arg_rs1_mem" + + case op == "FSD" || op == "FSW" || op == "FSH" || op == "FSQ": + return "arg_fs2, arg_rs1_store" + + case op == "SD" || op == "SB" || op == "SW" || op == "SH": + return "arg_rs2, arg_rs1_store" + + case op == "CSRRW" || op == "CSRRS" || op == "CSRRC": + return "arg_rd, arg_csr, arg_rs1" + + case op == "CSRRWI" || op == "CSRRSI" || op == "CSRRCI": + return "arg_rd, arg_csr, arg_zimm" + + case op == "JALR": + return "arg_rd, arg_rs1_mem" + + case op == "FENCE_I": + return "" + + case op == "FENCE": + return "arg_pred, arg_succ" + + default: + var instStr []string + for _, arg := range argTypeList { + if decodeArgs(arg, op) != "" { + instStr = append(instStr, decodeArgs(arg, op)) + } + } + return strings.Join(instStr, ", ") + } +} + +// decodeArgs turns the args into formats defined in arg.go +func decodeArgs(arg string, op string) string { + switch { + case strings.Contains("arg_rd", arg): + if isFloatReg(op, "rd") || strings.Contains(op, "C_FLDSP") { + return "arg_fd" + } + return "arg_rd" + + case strings.Contains("arg_rs1", arg): + if isFloatReg(op, "rs") { + return "arg_fs1" + } + return "arg_rs1" + + case strings.Contains("arg_rs2", arg): + if isFloatReg(op, "rs") { + return "arg_fs2" + } + return "arg_rs2" + + case strings.Contains("arg_rs3", arg): + if isFloatReg(op, "rs") { + return "arg_fs3" + } + return "arg_rs3" + + case arg == "imm12": + return "arg_imm12" + + case arg == "imm20": + return "arg_imm20" + + case arg == "jimm20": + return "arg_jimm20" + + case arg == "bimm12lo": + return "arg_bimm12" + + case arg == "imm12lo": + return "arg_simm12" + + case arg == "shamtw": + return "arg_shamt5" + + case arg == "shamtd": + return "arg_shamt6" + + case arg == "rd_p": + if strings.Contains(op, "C_FLD") { + return "arg_fd_p" + } + return "arg_rd_p" + + case arg == "rs1_p": + return "arg_rs1_p" + + case arg == "rd_rs1_p": + return "arg_rd_rs1_p" + + case arg == "rs2_p": + if strings.Contains(op, "C_FSD") { + return "arg_fs2_p" + } + return "arg_rs2_p" + + case arg == "rd_n0": + return "arg_rd_n0" + + case arg == "rs1_n0": + return "arg_rs1_n0" + + case arg == "rd_rs1_n0": + return "arg_rd_rs1_n0" + + case arg == "c_rs1_n0": + return "arg_c_rs1_n0" + + case arg == "c_rs2_n0": + return "arg_c_rs2_n0" + + case arg == "c_rs2": + if strings.Contains(op, "C_FSDSP") { + return "arg_c_fs2" + } + return "arg_c_rs2" + + case arg == "rd_n2": + return "arg_rd_n2" + + case arg == "c_imm6lo": + return "arg_c_imm6" + + case arg == "c_nzimm6lo": + return "arg_c_nzimm6" + + case arg == "c_nzuimm6lo": + return "arg_c_nzuimm6" + + case arg == "c_uimm7lo": + return "arg_c_uimm7" + + case arg == "c_uimm8lo": + return "arg_c_uimm8" + + case arg == "c_uimm8sp_s": + return "arg_c_uimm8sp_s" + + case arg == "c_uimm8splo": + return "arg_c_uimm8sp" + + case arg == "c_uimm9sp_s": + return "arg_c_uimm9sp_s" + + case arg == "c_uimm9splo": + return "arg_c_uimm9sp" + + case arg == "c_bimm9lo": + return "arg_c_bimm9" + + case arg == "c_nzimm10lo": + return "arg_c_nzimm10" + + case arg == "c_nzuimm10": + return "arg_c_nzuimm10" + + case arg == "c_imm12": + return "arg_c_imm12" + + case arg == "c_nzimm18lo": + return "arg_c_nzimm18" + } + return "" +} + +// genValueAndMask generates instruction value and relative mask. +func genValueAndMask(valStr []string, secStr []string) (uint32, uint32) { + var val int64 + + val, err := strconv.ParseInt(valStr[1], 0, 32) + if err != nil { + log.Fatal(err) + } + + l, err := strconv.Atoi(secStr[0]) + if err != nil { + log.Fatal(err) + } + var r int + if len(secStr) == 1 { + r = l + } else { + r, err = strconv.Atoi(secStr[1]) + if err != nil { + log.Fatal(err) + } + } + + subval := uint32(val << r) + submsk := ^uint32(0) << (31 - l) >> (31 - l + r) << r + return subval, submsk +} + +// isAtomic reports whether the instruction is atomic. +func isAtomic(op string) bool { + return strings.HasPrefix(op, "AMO") || strings.HasPrefix(op, "LR_") || strings.HasPrefix(op, "SC_") +} + +// isFloatReg reports whether the register of a floating point instruction is a floating point register. +func isFloatReg(op string, reg string) bool { + switch { + case strings.Contains(op, "FADD") || strings.Contains(op, "FSUB") || + strings.Contains(op, "FDIV") || strings.Contains(op, "FMUL") || + strings.Contains(op, "FMIN") || strings.Contains(op, "FMAX") || + strings.Contains(op, "FMADD") || strings.Contains(op, "FMSUB") || + strings.Contains(op, "FCVT_D_S") || strings.Contains(op, "FCVT_S_D") || + strings.Contains(op, "FCVT_D_Q") || strings.Contains(op, "FCVT_Q_D") || + strings.Contains(op, "FCVT_S_Q") || strings.Contains(op, "FCVT_Q_S") || + strings.Contains(op, "FCVT_H_S") || strings.Contains(op, "FCVT_S_H") || + strings.Contains(op, "FNM") || strings.Contains(op, "FNEG") || + strings.Contains(op, "FSQRT") || strings.Contains(op, "FSGNJ"): + return true + + case strings.Contains(op, "FCLASS") || strings.Contains(op, "FCVT_L") || + strings.Contains(op, "FCVT_W") || strings.Contains(op, "FEQ") || + strings.Contains(op, "FLE") || strings.Contains(op, "FLT") || + strings.Contains(op, "FMV_X_H") || strings.Contains(op, "FMV_X_D") || + strings.Contains(op, "FMV_X_W"): + return reg != "rd" + + case strings.Contains(op, "FCVT_D") || strings.Contains(op, "FCVT_S") || + strings.Contains(op, "FCVT_H") || strings.Contains(op, "FCVT_Q") || + strings.Contains(op, "FMV_H_X") || strings.Contains(op, "FMV_D_X") || + strings.Contains(op, "FMV_W_X"): + return reg != "rs" + + default: + return false + } +} diff --git a/s390x/s390x.csv b/s390x/s390x.csv new file mode 100644 index 00000000..a53942d8 --- /dev/null +++ b/s390x/s390x.csv @@ -0,0 +1,1277 @@ +# Copyright 2024 The Go Authors. All rights reserved. +# Use of this source code is governed by a BSD-style +# license that can be found in the LICENSE file. +# +# This file is generated by the s390xspec program. +# +# Command to generate this file is: +# ./s390xspec > s390x.csv +# +# For eg: ./s390xspec z_Architecture_Principles_of_Operation.pdf > s390x.csv +# +# Specific Edition of the PDF manual used (Publication No): SA22-7832-13 +# Document link: https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-13.pdf +# +# IBM Z-ISA Principles of Operation PDF instruction description. +# +# This file contains comment lines, each beginning with #, +# followed by entries in CSV format. +# +# Each line in the CSV section contains 4 fields: +# +# instruction mnemonic encoding isa-level +# +# The instruction is list of instructions picked from the Appendix-B "Lists of Instructions" heading. +# The mnemonic is the instruction mnemonics, separated by | characters. +# The encoding is the encoding, a sequence of name@startbit| describing each bit field in turn or +# a list of sequences of the form (,sequence)+. A leading comma is used to signify an +# instruction encoding requiring multiple instruction words. +# The fourth field represents instruction characteristics string +# + + +"ADD (32)","A R1,D2(X2,B2)","90@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"ADD (32)","AR R1,R2","26@0|R1@8|R2@12|??@16","1A" +"ADD (32)","ARK R1,R2,R3","47608@0|R3@16|//@20|R1@24|R2@28|??@32","B9F8" +"ADD (32)","AY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|90@40|??@48","B" +"ADD (64)","AG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|8@40|??@48","B" +"ADD (64)","AGR R1,R2","47368@0|//@16|R1@24|R2@28|??@32","B908" +"ADD (64)","AGRK R1,R2,R3","47592@0|R3@16|//@20|R1@24|R2@28|??@32","B9E8" +"ADD (64←32)","AGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|24@40|??@48","B" +"ADD (64←32)","AGFR R1,R2","47384@0|//@16|R1@24|R2@28|??@32","B918" +"ADD (extended BFP)","AXBR R1,R2","45898@0|//@16|R1@24|R2@28|??@32","SP Db" +"ADD (extended DFP)","AXTR R1,R2,R3","46042@0|R3@16|//@20|R1@24|R2@28|??@32","SP Dt" +"ADD (extended DFP)","AXTRA R1,R2,R3,M4","46042@0|R3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"ADD (long BFP)","ADB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|26@40|??@48","Db" +"ADD (long BFP)","ADBR R1,R2","45850@0|//@16|R1@24|R2@28|??@32","Db" +"ADD (long DFP)","ADTR R1,R2,R3","46034@0|R3@16|//@20|R1@24|R2@28|??@32","Dt" +"ADD (long DFP)","ADTRA R1,R2,R3,M4","46034@0|R3@16|M4@20|R1@24|R2@28|??@32","Dt" +"ADD (short BFP)","AEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|10@40|??@48","Db" +"ADD (short BFP)","AEBR R1,R2","45834@0|//@16|R1@24|R2@28|??@32","Db" +"ADD DECIMAL","AP D1(L1,B1),D2(L2,B2)","250@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","Dg" +"ADD HALFWORD (32←16)","AH R1,D2(X2,B2)","74@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"ADD HALFWORD (32←16)","AHY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|122@40|??@48","B" +"ADD HALFWORD (64→16)","AGH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|56@40|??@48","B" +"ADD HALFWORD IMMEDIATE (32←16)","AHI R1,I2","167@0|R1@8|10@12|I2@16|??@32","A7A" +"ADD HALFWORD IMMEDIATE (64←16)","AGHI R1,I2","167@0|R1@8|11@12|I2@16|??@32","A7B" +"ADD HIGH (32)","AHHHR R1,R2,R3","47560@0|R3@16|//@20|R1@24|R2@28|??@32","B9C8" +"ADD HIGH (32)","AHHLR R1,R2,R3","47576@0|R3@16|//@20|R1@24|R2@28|??@32","B9D8" +"ADD IMMEDIATE (32)","AFI R1,I2","194@0|R1@8|9@12|I2@16|??@48","C29" +"ADD IMMEDIATE (32←16)","AHIK R1,R3,I2","236@0|R1@8|R3@12|I2@16|//@32|216@40|??@48","ECD8" +"ADD IMMEDIATE (32←8)","ASI D1(B1),I2","235@0|I2@8|B1@16|D1@20|106@40|??@48","ST" +"ADD IMMEDIATE (64←16)","AGHIK R1,R3,I2","236@0|R1@8|R3@12|I2@16|//@32|217@40|??@48","ECD9" +"ADD IMMEDIATE (64←32)","AGFI R1,I2","194@0|R1@8|8@12|I2@16|??@48","C28" +"ADD IMMEDIATE (64←8)","AGSI D1(B1),I2","235@0|I2@8|B1@16|D1@20|122@40|??@48","ST" +"ADD IMMEDIATE HIGH (32)","AIH R1,I2","204@0|R1@8|8@12|I2@16|??@48","CC8" +"ADD LOGICAL (32)","AL R1,D2(X2,B2)","94@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"ADD LOGICAL (32)","ALR R1,R2","30@0|R1@8|R2@12|??@16","1E" +"ADD LOGICAL (32)","ALRK R1,R2,R3","47610@0|R3@16|//@20|R1@24|R2@28|??@32","B9FA" +"ADD LOGICAL (32)","ALY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|94@40|??@48","B" +"ADD LOGICAL (64)","ALG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|10@40|??@48","B" +"ADD LOGICAL (64)","ALGR R1,R2","47370@0|//@16|R1@24|R2@28|??@32","B90A" +"ADD LOGICAL (64)","ALGRK R1,R2,R3","47594@0|R3@16|//@20|R1@24|R2@28|??@32","B9EA" +"ADD LOGICAL (64←32)","ALGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|26@40|??@48","B" +"ADD LOGICAL (64←32)","ALGFR R1,R2","47386@0|//@16|R1@24|R2@28|??@32","B91A" +"ADD LOGICAL HIGH (32)","ALHHHR R1,R2,R3","47562@0|R3@16|//@20|R1@24|R2@28|??@32","B9CA" +"ADD LOGICAL HIGH (32)","ALHHLR R1,R2,R3","47578@0|R3@16|//@20|R1@24|R2@28|??@32","B9DA" +"ADD LOGICAL IMMEDIATE (32)","ALFI R1,I2","194@0|R1@8|11@12|I2@16|??@48","C2B" +"ADD LOGICAL IMMEDIATE (64←32)","ALGFI R1,I2","194@0|R1@8|10@12|I2@16|??@48","C2A" +"ADD LOGICAL WITH CARRY (32)","ALC R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|152@40|??@48","B" +"ADD LOGICAL WITH CARRY (32)","ALCR R1,R2","47512@0|//@16|R1@24|R2@28|??@32","B998" +"ADD LOGICAL WITH CARRY (64)","ALCG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|136@40|??@48","B" +"ADD LOGICAL WITH CARRY (64)","ALCGR R1,R2","47496@0|//@16|R1@24|R2@28|??@32","B988" +"ADD LOGICAL WITH SIGNED IMMEDIATE(32→16)","ALHSIK R1,R3,I2","236@0|R1@8|R3@12|I2@16|//@32|218@40|??@48","ECDA 7-31" +"ADD LOGICAL WITH SIGNED IMMEDIATE (32←8)","ALSI D1(B1),I2","235@0|I2@8|B1@16|D1@20|110@40|??@48","ST" +"ADD LOGICAL WITH SIGNED IMMEDIATE(64→16)","ALGHSIK R1,R3,I2","236@0|R1@8|R3@12|I2@16|//@32|219@40|??@48","ECDB 7-31" +"ADD LOGICAL WITH SIGNED IMMEDIATE (64→8)","ALGSI D1(B1),I2","235@0|I2@8|B1@16|D1@20|126@40|??@48","ST" +"ADD LOGICAL WITH SIGNED IMMEDIATE HIGH(32)","ALSIH R1,I2","204@0|R1@8|10@12|I2@16|??@48","CCA" +"ADD LOGICAL WITH SIGNED IMMEDIATE HIGH(32)","ALSIHN R1,I2","204@0|R1@8|11@12|I2@16|??@48","CCB" +"ADD NORMALIZED (extended HFP)","AXR R1,R2","54@0|R1@8|R2@12|??@16","SP Da" +"ADD NORMALIZED (long HFP)","AD R1,D2(X2,B2)","106@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"ADD NORMALIZED (long HFP)","ADR R1,R2","42@0|R1@8|R2@12|??@16","Da" +"ADD NORMALIZED (short HFP)","AE R1,D2(X2,B2)","122@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"ADD NORMALIZED (short HFP)","AER R1,R2","58@0|R1@8|R2@12|??@16","Da" +"ADD UNNORMALIZED (long HFP)","AW R1,D2(X2,B2)","110@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"ADD UNNORMALIZED (long HFP)","AWR R1,R2","46@0|R1@8|R2@12|??@16","Da" +"ADD UNNORMALIZED (short HFP)","AU R1,D2(X2,B2)","126@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"ADD UNNORMALIZED (short HFP)","AUR R1,R2","62@0|R1@8|R2@12|??@16","Da" +"AND (32)","N R1,D2(X2,B2)","84@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"AND (32)","NR R1,R2","20@0|R1@8|R2@12|??@16","14" +"AND (32)","NRK R1,R2,R3","47604@0|R3@16|//@20|R1@24|R2@28|??@32","B9F4" +"AND (32)","NY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|84@40|??@48","B" +"AND (64)","NG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|128@40|??@48","B" +"AND (64)","NGR R1,R2","47488@0|//@16|R1@24|R2@28|??@32","B980" +"AND (64)","NGRK R1,R2,R3","47588@0|R3@16|//@20|R1@24|R2@28|??@32","B9E4" +"AND (character)","NC D1(L1,B1),D2(B2)","212@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"AND (immediate)","NI D1(B1),I2","148@0|I2@8|B1@16|D1@20|??@32","ST" +"AND (immediate)","NIY D1(B1),I2","235@0|I2@8|B1@16|D1@20|84@40|??@48","ST" +"AND IMMEDIATE (high high)","NIHH R1,I2","165@0|R1@8|4@12|I2@16|??@32","A54" +"AND IMMEDIATE (high low)","NIHL R1,I2","165@0|R1@8|5@12|I2@16|??@32","A55" +"AND IMMEDIATE (high)","NIHF R1,I2","192@0|R1@8|10@12|I2@16|??@48","C0A" +"AND IMMEDIATE (low high)","NILH R1,I2","165@0|R1@8|6@12|I2@16|??@32","A56" +"AND IMMEDIATE (low low)","NILL R1,I2","165@0|R1@8|7@12|I2@16|??@32","A57" +"AND IMMEDIATE (low)","NILF R1,I2","192@0|R1@8|11@12|I2@16|??@48","C0B" +"AND WITH COMPLEMENT(32)","NCRK R1,R2,R3","47605@0|R3@16|//@20|R1@24|R2@28|??@32","B9F5" +"AND WITH COMPLEMENT(64)","NCGRK R1,R2,R3","47589@0|R3@16|//@20|R1@24|R2@28|??@32","B9E5" +"BRANCH AND LINK","BAL R1,D2(X2,B2)","69@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"BRANCH AND LINK","BALR R1,R2","5@0|R1@8|R2@12|??@16","B" +"BRANCH AND SAVE","BAS R1,D2(X2,B2)","77@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"BRANCH AND SAVE","BASR R1,R2","13@0|R1@8|R2@12|??@16","B" +"BRANCH AND SAVE AND SET MODE","BASSM R1,R2","12@0|R1@8|R2@12|??@16","B" +"BRANCH AND SET AUTHORITY","BSA R1,R2","45658@0|//@16|R1@24|R2@28|??@32","SO" +"BRANCH AND SET MODE","BSM R1,R2","11@0|R1@8|R2@12|??@16","B" +"BRANCH AND STACK","BAKR R1,R2","45632@0|//@16|R1@24|R2@28|??@32","Z" +"BRANCH IN SUBSPACE GROUP","BSG R1,R2","45656@0|//@16|R1@24|R2@28|??@32","SO" +"BRANCH INDIRECT ON CONDITION","BIC M1,D2(X2,B2)","227@0|M1@8|X2@12|B2@16|D2@20|71@40|??@48","B" +"BRANCH ON CONDITION","BC M1,D2(X2,B2)","71@0|M1@8|X2@12|B2@16|D2@20|??@32","B" +"BRANCH ON CONDITION","BCR M1,R2","7@0|M1@8|R2@12|??@16","B" +"BRANCH ON COUNT (32)","BCT R1,D2(X2,B2)","70@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"BRANCH ON COUNT (32)","BCTR R1,R2","6@0|R1@8|R2@12|??@16","B" +"BRANCH ON COUNT (64)","BCTG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|70@40|??@48","B" +"BRANCH ON COUNT (64)","BCTGR R1,R2","47430@0|//@16|R1@24|R2@28|??@32","B" +"BRANCH ON INDEX HIGH (32)","BXH R1,R3,D2(B2)","134@0|R1@8|R3@12|B2@16|D2@20|??@32","B" +"BRANCH ON INDEX HIGH (64)","BXHG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|68@40|??@48","B" +"BRANCH ON INDEX LOW OR EQUAL (32)","BXLE R1,R3,D2(B2)","135@0|R1@8|R3@12|B2@16|D2@20|??@32","B" +"BRANCH ON INDEX LOW OR EQUAL (64)","BXLEG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|69@40|??@48","B" +"BRANCH PREDICTION PRELOAD","BPP M1,RI2,D3(B3)","199@0|M1@8|//@12|B3@16|D3@20|RI2@32|??@48","C7" +"BRANCH PREDICTION RELATIVE PRELOAD","BPRP M1,RI2,RI3","197@0|M1@8|RI2@12|RI3@24|??@48","C5" +"BRANCH RELATIVE AND SAVE","BRAS R1,RI2","167@0|R1@8|5@12|RI2@16|??@32","B" +"BRANCH RELATIVE AND SAVE LONG","BRASL R1,RI2","192@0|R1@8|5@12|RI2@16|??@48","B" +"BRANCH RELATIVE ON CONDITION","BRC M1,RI2","167@0|M1@8|4@12|RI2@16|??@32","B" +"BRANCH RELATIVE ON CONDITION LONG","BRCL M1,RI2","192@0|M1@8|4@12|RI2@16|??@48","B" +"BRANCH RELATIVE ON COUNT (32)","BRCT R1,RI2","167@0|R1@8|6@12|RI2@16|??@32","B" +"BRANCH RELATIVE ON COUNT (64)","BRCTG R1,RI2","167@0|R1@8|7@12|RI2@16|??@32","B" +"BRANCH RELATIVE ON COUNT HIGH (32)","BRCTH R1,RI2","204@0|R1@8|6@12|RI2@16|??@48","B" +"BRANCH RELATIVE ON INDEX HIGH (32)","BRXH R1,R3,RI2","132@0|R1@8|R3@12|RI2@16|??@32","B" +"BRANCH RELATIVE ON INDEX HIGH (64)","BRXHG R1,R3,RI2","236@0|R1@8|R3@12|RI2@16|//@32|68@40|??@48","B" +"BRANCH RELATIVE ON INDEX LOW OR EQ. (32)","BRXLE R1,R3,RI2","133@0|R1@8|R3@12|RI2@16|??@32","B" +"BRANCH RELATIVE ON INDEX LOW OR EQ. (64)","BRXLG R1,R3,RI2","236@0|R1@8|R3@12|RI2@16|//@32|69@40|??@48","B" +"CANCEL SUBCHANNEL","XSCH","45686@0|//@16|??@32","OP" +"CHECKSUM","CKSM R1,R2","45633@0|//@16|R1@24|R2@28|??@32","SP IC" +"CIPHER MESSAGE","KM R1,R2","47406@0|//@16|R1@24|R2@28|??@32","SP IC" +"CIPHER MESSAGE WITH AUTHENTICATION","KMA R1,R3,R2","47401@0|R3@16|//@20|R1@24|R2@28|??@32","SP IC" +"CIPHER MESSAGE WITH CHAINING","KMC R1,R2","47407@0|//@16|R1@24|R2@28|??@32","SP IC" +"CIPHER MESSAGE WITH CIPHER FEEDBACK","KMF R1,R2","47402@0|//@16|R1@24|R2@28|??@32","SP IC" +"CIPHER MESSAGE WITH COUNTER","KMCTR R1,R3,R2","47405@0|R3@16|//@20|R1@24|R2@28|??@32","SP IC" +"CIPHER MESSAGE WITH OUTPUT FEEDBACK","KMO R1,R2","47403@0|//@16|R1@24|R2@28|??@32","SP IC" +"CLEAR SUBCHANNEL","CSCH","45616@0|//@16|??@32","OP" +"COMPARE (32)","C R1,D2(X2,B2)","89@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"COMPARE (32)","CR R1,R2","25@0|R1@8|R2@12|??@16","19" +"COMPARE (32)","CY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|89@40|??@48","B" +"COMPARE (64)","CG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|32@40|??@48","B" +"COMPARE (64)","CGR R1,R2","47392@0|//@16|R1@24|R2@28|??@32","B920" +"COMPARE (64←32)","CGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|48@40|??@48","B" +"COMPARE (64←32)","CGFR R1,R2","47408@0|//@16|R1@24|R2@28|??@32","B930" +"COMPARE (extended BFP)","CXBR R1,R2","45897@0|//@16|R1@24|R2@28|??@32","SP Db" +"COMPARE (extended DFP)","CXTR R1,R2","46060@0|//@16|R1@24|R2@28|??@32","SP Dt" +"COMPARE (extended HFP)","CXR R1,R2","45929@0|//@16|R1@24|R2@28|??@32","SP Da" +"COMPARE (long BFP)","CDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|25@40|??@48","Db" +"COMPARE (long BFP)","CDBR R1,R2","45849@0|//@16|R1@24|R2@28|??@32","Db" +"COMPARE (long DFP)","CDTR R1,R2","46052@0|//@16|R1@24|R2@28|??@32","Dt" +"COMPARE (long HFP)","CD R1,D2(X2,B2)","105@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"COMPARE (long HFP)","CDR R1,R2","41@0|R1@8|R2@12|??@16","Da" +"COMPARE (short BFP)","CEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|9@40|??@48","Db" +"COMPARE (short BFP)","CEBR R1,R2","45833@0|//@16|R1@24|R2@28|??@32","Db" +"COMPARE (short HFP)","CE R1,D2(X2,B2)","121@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"COMPARE (short HFP)","CER R1,R2","57@0|R1@8|R2@12|??@16","Da" +"COMPARE AND BRANCH (32)","CRB R1,R2,M3,D4(B4)","236@0|R1@8|R2@12|B4@16|D4@20|M3@32|//@36|246@40|??@48","B" +"COMPARE AND BRANCH (64)","CGRB R1,R2,M3,D4(B4)","236@0|R1@8|R2@12|B4@16|D4@20|M3@32|//@36|228@40|??@48","B" +"COMPARE AND BRANCH RELATIVE (32)","CRJ R1,R2,M3,RI4","236@0|R1@8|R2@12|RI4@16|M3@32|//@36|118@40|??@48","B" +"COMPARE AND BRANCH RELATIVE (64)","CGRJ R1,R2,M3,RI4","236@0|R1@8|R2@12|RI4@16|M3@32|//@36|100@40|??@48","B" +"COMPARE AND FORM CODEWORD","CFC D2(B2)","45594@0|B2@16|D2@20|??@32","SP II" +"COMPARE AND REPLACE DAT TABLE ENTRY","CRDTE R1,R3,R2,M4","47503@0|R3@16|M4@20|R1@24|R2@28|??@32","SP" +"COMPARE AND SIGNAL (extended BFP)","KXBR R1,R2","45896@0|//@16|R1@24|R2@28|??@32","SP Db" +"COMPARE AND SIGNAL (extended DFP)","KXTR R1,R2","46056@0|//@16|R1@24|R2@28|??@32","SP Dt" +"COMPARE AND SIGNAL (long BFP)","KDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|24@40|??@48","Db" +"COMPARE AND SIGNAL (long BFP)","KDBR R1,R2","45848@0|//@16|R1@24|R2@28|??@32","Db" +"COMPARE AND SIGNAL (long DFP)","KDTR R1,R2","46048@0|//@16|R1@24|R2@28|??@32","Dt" +"COMPARE AND SIGNAL (short BFP)","KEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|8@40|??@48","Db" +"COMPARE AND SIGNAL (short BFP)","KEBR R1,R2","45832@0|//@16|R1@24|R2@28|??@32","Db" +"COMPARE AND SWAP (32)","CS R1,R3,D2(B2)","186@0|R1@8|R3@12|B2@16|D2@20|??@32","SP" +"COMPARE AND SWAP (32)","CSY R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|20@40|??@48","SP" +"COMPARE AND SWAP (64)","CSG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|48@40|??@48","SP" +"COMPARE AND SWAP AND PURGE (32)","CSP R1,R2","45648@0|//@16|R1@24|R2@28|??@32","SP" +"COMPARE AND SWAP AND PURGE (64)","CSPG R1,R2","47498@0|//@16|R1@24|R2@28|??@32","SP" +"COMPARE AND SWAP AND STORE","CSST D1(B1),D2(B2),R3","200@0|R3@8|2@12|B1@16|D1@20|B2@32|D2@36|??@48","SP" +"COMPARE AND TRAP (32)","CRT R1,R2,M3","47474@0|M3@16|//@20|R1@24|R2@28|??@32","B972" +"COMPARE AND TRAP (64)","CGRT R1,R2,M3","47456@0|M3@16|//@20|R1@24|R2@28|??@32","B960" +"COMPARE BIASED EXPONENT (extended DFP)","CEXTR R1,R2","46076@0|//@16|R1@24|R2@28|??@32","SP Dt" +"COMPARE BIASED EXPONENT (long DFP)","CEDTR R1,R2","46068@0|//@16|R1@24|R2@28|??@32","Dt" +"COMPARE DECIMAL","CP D1(L1,B1),D2(L2,B2)","249@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","Dg" +"COMPARE DOUBLE AND SWAP (32)","CDS R1,R3,D2(B2)","187@0|R1@8|R3@12|B2@16|D2@20|??@32","SP" +"COMPARE DOUBLE AND SWAP (32)","CDSY R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|49@40|??@48","SP" +"COMPARE DOUBLE AND SWAP (64)","CDSG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|62@40|??@48","SP" +"COMPARE HALFWORD (32→16)","CH R1,D2(X2,B2)","73@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"COMPARE HALFWORD (32→16)","CHY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|121@40|??@48","B" +"COMPARE HALFWORD (64←16)","CGH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|52@40|??@48","B" +"COMPARE HALFWORD IMMEDIATE (16→16)","CHHSI D1(B1),I2","58708@0|B1@16|D1@20|I2@32|??@48","B" +"COMPARE HALFWORD IMMEDIATE (32←16)","CHI R1,I2","167@0|R1@8|14@12|I2@16|??@32","A7E" +"COMPARE HALFWORD IMMEDIATE (32←16)","CHSI D1(B1),I2","58716@0|B1@16|D1@20|I2@32|??@48","B" +"COMPARE HALFWORD IMMEDIATE (64←16)","CGHI R1,I2","167@0|R1@8|15@12|I2@16|??@32","A7F" +"COMPARE HALFWORD IMMEDIATE (64←16)","CGHSI D1(B1),I2","58712@0|B1@16|D1@20|I2@32|??@48","B" +"COMPAREHALFWORDRELATIVE LONG (32→16)","CHRL R1,RI2","198@0|R1@8|5@12|RI2@16|??@48","C65" +"COMPAREHALFWORDRELATIVE LONG (64←16)","CGHRL R1,RI2","198@0|R1@8|4@12|RI2@16|??@48","C64" +"COMPARE HIGH (32)","CHF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|205@40|??@48","B" +"COMPARE HIGH (32)","CHHR R1,R2","47565@0|//@16|R1@24|R2@28|??@32","B9CD" +"COMPARE HIGH (32)","CHLR R1,R2","47581@0|//@16|R1@24|R2@28|??@32","B9DD" +"COMPARE IMMEDIATE (32)","CFI R1,I2","194@0|R1@8|13@12|I2@16|??@48","C2D" +"COMPARE IMMEDIATE (64←32)","CGFI R1,I2","194@0|R1@8|12@12|I2@16|??@48","C2C" +"COMPARE IMMEDIATE AND BRANCH (32←8)","CIB R1,I2,M3,D4(B4)","236@0|R1@8|M3@12|B4@16|D4@20|I2@32|254@40|??@48","B" +"COMPARE IMMEDIATE AND BRANCH (64←8)","CGIB R1,I2,M3,D4(B4)","236@0|R1@8|M3@12|B4@16|D4@20|I2@32|252@40|??@48","B" +"COMPARE IMMEDIATE AND BRANCH RELATIVE(32→8)","CIJ R1,I2,M3,RI4","236@0|R1@8|M3@12|RI4@16|I2@32|126@40|??@48","B" +"COMPARE IMMEDIATE AND BRANCH RELATIVE(64→8)","CGIJ R1,I2,M3,RI4","236@0|R1@8|M3@12|RI4@16|I2@32|124@40|??@48","B" +"COMPARE IMMEDIATE AND TRAP (32→16)","CIT R1,I2,M3","236@0|R1@8|//@12|I2@16|M3@32|//@36|114@40|??@48","EC72" +"COMPARE IMMEDIATE AND TRAP (64←16)","CGIT R1,I2,M3","236@0|R1@8|//@12|I2@16|M3@32|//@36|112@40|??@48","EC70" +"COMPARE IMMEDIATE HIGH (32)","CIH R1,I2","204@0|R1@8|13@12|I2@16|??@48","CCD" +"COMPARE LOGICAL (32)","CL R1,D2(X2,B2)","85@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"COMPARE LOGICAL (32)","CLR R1,R2","21@0|R1@8|R2@12|??@16","15" +"COMPARE LOGICAL (32)","CLY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|85@40|??@48","B" +"COMPARE LOGICAL (64)","CLG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|33@40|??@48","B" +"COMPARE LOGICAL (64)","CLGR R1,R2","47393@0|//@16|R1@24|R2@28|??@32","B921" +"COMPARE LOGICAL (64→32)","CLGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|49@40|??@48","B" +"COMPARE LOGICAL (64→32)","CLGFR R1,R2","47409@0|//@16|R1@24|R2@28|??@32","B931" +"COMPARE LOGICAL (character)","CLC D1(L1,B1),D2(B2)","213@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","B" +"COMPARE LOGICAL (immediate)","CLI D1(B1),I2","149@0|I2@8|B1@16|D1@20|??@32","B" +"COMPARE LOGICAL (immediate)","CLIY D1(B1),I2","235@0|I2@8|B1@16|D1@20|85@40|??@48","B" +"COMPARE LOGICAL AND BRANCH (32)","CLRB R1,R2,M3,D4(B4)","236@0|R1@8|R2@12|B4@16|D4@20|M3@32|//@36|247@40|??@48","B" +"COMPARE LOGICAL AND BRANCH (64)","CLGRB R1,R2,M3,D4(B4)","236@0|R1@8|R2@12|B4@16|D4@20|M3@32|//@36|229@40|??@48","B" +"COMPARE LOGICAL AND BRANCH RELATIVE(32)","CLRJ R1,R2,M3,RI4","236@0|R1@8|R2@12|RI4@16|M3@32|//@36|119@40|??@48","B" +"COMPARE LOGICAL AND BRANCH RELATIVE(64)","CLGRJ R1,R2,M3,RI4","236@0|R1@8|R2@12|RI4@16|M3@32|//@36|101@40|??@48","B" +"COMPARE LOGICAL AND TRAP (32)","CLRT R1,R2,M3","47475@0|M3@16|//@20|R1@24|R2@28|??@32","B973" +"COMPARE LOGICAL AND TRAP (32)","CLT R1,M3,D2(B2)","235@0|R1@8|M3@12|B2@16|D2@20|35@40|??@48","B" +"COMPARE LOGICAL AND TRAP (64)","CLGRT R1,R2,M3","47457@0|M3@16|//@20|R1@24|R2@28|??@32","B961" +"COMPARE LOGICAL AND TRAP (64)","CLGT R1,M3,D2(B2)","235@0|R1@8|M3@12|B2@16|D2@20|43@40|??@48","B" +"COMPARE LOGICAL CHAR. UNDER MASK (high)","CLMH R1,M3,D2(B2)","235@0|R1@8|M3@12|B2@16|D2@20|32@40|??@48","B" +"COMPARE LOGICAL CHAR. UNDER MASK (low)","CLM R1,M3,D2(B2)","189@0|R1@8|M3@12|B2@16|D2@20|??@32","B" +"COMPARE LOGICAL CHAR. UNDER MASK (low)","CLMY R1,M3,D2(B2)","235@0|R1@8|M3@12|B2@16|D2@20|33@40|??@48","B" +"COMPARE LOGICAL HIGH (32)","CLHF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|207@40|??@48","B" +"COMPARE LOGICAL HIGH (32)","CLHHR R1,R2","47567@0|//@16|R1@24|R2@28|??@32","B9CF" +"COMPARE LOGICAL HIGH (32)","CLHLR R1,R2","47583@0|//@16|R1@24|R2@28|??@32","B9DF" +"COMPARE LOGICAL IMMEDIATE (16←16)","CLHHSI D1(B1),I2","58709@0|B1@16|D1@20|I2@32|??@48","B" +"COMPARE LOGICAL IMMEDIATE (32)","CLFI R1,I2","194@0|R1@8|15@12|I2@16|??@48","C2F" +"COMPARE LOGICAL IMMEDIATE (32←16)","CLFHSI D1(B1),I2","58717@0|B1@16|D1@20|I2@32|??@48","B" +"COMPARE LOGICAL IMMEDIATE (64←16)","CLGHSI D1(B1),I2","58713@0|B1@16|D1@20|I2@32|??@48","B" +"COMPARE LOGICAL IMMEDIATE (64←32)","CLGFI R1,I2","194@0|R1@8|14@12|I2@16|??@48","C2E" +"COMPARE LOGICAL IMMEDIATE AND BRANCH(32←8)","CLIB R1,I2,M3,D4(B4)","236@0|R1@8|M3@12|B4@16|D4@20|I2@32|255@40|??@48","B" +"COMPARE LOGICAL IMMEDIATE AND BRANCH(64→8)","CLGIB R1,I2,M3,D4(B4)","236@0|R1@8|M3@12|B4@16|D4@20|I2@32|253@40|??@48","B" +"COMPARE LOGICAL IMMEDIATE AND BRANCH","CLIJ R1,I2,M3,RI4","236@0|R1@8|M3@12|RI4@16|I2@32|127@40|??@48","B" +"RELATIVE (32→8)10COMPARE LOGICAL IMMEDIATE AND BRANCH","CLGIJ R1,I2,M3,RI4","236@0|R1@8|M3@12|RI4@16|I2@32|125@40|??@48","B" +"RELATIVE (64→8)COMPARE LOGICAL IMMEDIATE AND TRAP(32→16)","CLFIT R1,I2,M3","236@0|R1@8|//@12|I2@16|M3@32|//@36|115@40|??@48","EC73" +"COMPARE LOGICAL IMMEDIATE AND TRAP(64←16)","CLGIT R1,I2,M3","236@0|R1@8|//@12|I2@16|M3@32|//@36|113@40|??@48","EC71" +"COMPARE LOGICAL IMMEDIATE HIGH (32)","CLIH R1,I2","204@0|R1@8|15@12|I2@16|??@48","CCF" +"COMPARE LOGICAL LONG","CLCL R1,R2","15@0|R1@8|R2@12|??@16","SP II" +"COMPARE LOGICAL LONG EXTENDED","CLCLE R1,R3,D2(B2)","169@0|R1@8|R3@12|B2@16|D2@20|??@32","SP IC" +"COMPARE LOGICAL LONG UNICODE","CLCLU R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|143@40|??@48","SP IC" +"COMPARE LOGICAL RELATIVE LONG (32)","CLRL R1,RI2","198@0|R1@8|15@12|RI2@16|??@48","SP" +"COMPARE LOGICAL RELATIVE LONG (32→16)","CLHRL R1,RI2","198@0|R1@8|7@12|RI2@16|??@48","C67" +"COMPARE LOGICAL RELATIVE LONG (64)","CLGRL R1,RI2","198@0|R1@8|10@12|RI2@16|??@48","SP" +"COMPARE LOGICAL RELATIVE LONG (64→16)","CLGHRL R1,RI2","198@0|R1@8|6@12|RI2@16|??@48","C66" +"COMPARE LOGICAL RELATIVE LONG (64→32)","CLGFRL R1,RI2","198@0|R1@8|14@12|RI2@16|??@48","SP" +"COMPARE LOGICAL STRING","CLST R1,R2","45661@0|//@16|R1@24|R2@28|??@32","SP IC" +"COMPARE RELATIVE LONG (32)","CRL R1,RI2","198@0|R1@8|13@12|RI2@16|??@48","SP" +"COMPARE RELATIVE LONG (64)","CGRL R1,RI2","198@0|R1@8|8@12|RI2@16|??@48","SP" +"COMPARE RELATIVE LONG (64←32)","CGFRL R1,RI2","198@0|R1@8|12@12|RI2@16|??@48","SP" +"COMPARE UNTIL SUBSTRING EQUAL","CUSE R1,R2","45655@0|//@16|R1@24|R2@28|??@32","SP II" +"COMPRESSION CALL","CMPSC R1,R2","45667@0|//@16|R1@24|R2@28|??@32","SP II" +"COMPUTE DIGITAL SIGNATURE AUTHENTICATION","KDSA R1,R2","47418@0|//@16|R1@24|R2@28|??@32","SP IC" +"COMPUTE INTERMEDIATE MESSAGE DIGEST","KIMD R1,R2","47422@0|//@16|R1@24|R2@28|??@32","SP IC" +"COMPUTE LAST MESSAGE DIGEST","KLMD R1,R2","47423@0|//@16|R1@24|R2@28|??@32","SP IC" +"COMPUTE MESSAGE AUTHENTICATION CODE","KMAC R1,R2","47390@0|//@16|R1@24|R2@28|??@32","SP IC" +"CONVERT BFP TO HFP (long)","THDR R1,R2","45913@0|//@16|R1@24|R2@28|??@32","Da" +"CONVERT BFP TO HFP (short to long)","THDER R1,R2","45912@0|//@16|R1@24|R2@28|??@32","Da" +"CONVERT FROM FIXED (32 to extended BFP)","CXFBR R1,R2","45974@0|//@16|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM FIXED (32 to extended BFP)","CXFBRA R1,M3,R2,M4","45974@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM FIXED (32 to extended DFP)","CXFTR R1,M3,R2,M4","47449@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT FROM FIXED (32 to extended HFP)","CXFR R1,R2","46006@0|//@16|R1@24|R2@28|??@32","SP Da" +"CONVERT FROM FIXED (32 to long BFP)","CDFBR R1,R2","45973@0|//@16|R1@24|R2@28|??@32","Db" +"CONVERT FROM FIXED (32 to long BFP)","CDFBRA R1,M3,R2,M4","45973@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM FIXED (32 to long DFP)","CDFTR R1,M3,R2,M4","47441@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERT FROM FIXED (32 to long HFP)","CDFR R1,R2","46005@0|//@16|R1@24|R2@28|??@32","Da" +"CONVERT FROM FIXED (32 to short BFP)","CEFBR R1,R2","45972@0|//@16|R1@24|R2@28|??@32","Db" +"CONVERT FROM FIXED (32 to short BFP)","CEFBRA R1,M3,R2,M4","45972@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM FIXED (32 to short HFP)","CEFR R1,R2","46004@0|//@16|R1@24|R2@28|??@32","Da" +"CONVERT FROM FIXED (64 to extended BFP)","CXGBR R1,R2","45990@0|//@16|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM FIXED (64 to extended BFP)","CXGBRA R1,M3,R2,M4","45990@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM FIXED (64 to extended DFP)","CXGTR R1,R2","46073@0|//@16|R1@24|R2@28|??@32","SP Dt" +"CONVERT FROM FIXED (64 to extended DFP)","CXGTRA R1,M3,R2,M4","46073@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT FROM FIXED (64 to extended HFP)","CXGR R1,R2","46022@0|//@16|R1@24|R2@28|??@32","SP Da" +"CONVERT FROM FIXED (64 to long BFP)","CDGBR R1,R2","45989@0|//@16|R1@24|R2@28|??@32","Db" +"CONVERT FROM FIXED (64 to long BFP)","CDGBRA R1,M3,R2,M4","45989@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM FIXED (64 to long DFP)","CDGTR R1,R2","46065@0|//@16|R1@24|R2@28|??@32","Dt" +"CONVERT FROM FIXED (64 to long DFP)","CDGTRA R1,M3,R2,M4","46065@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERT FROM FIXED (64 to long HFP)","CDGR R1,R2","46021@0|//@16|R1@24|R2@28|??@32","Da" +"CONVERT FROM FIXED (64 to short BFP)","CEGBR R1,R2","45988@0|//@16|R1@24|R2@28|??@32","Db" +"CONVERT FROM FIXED (64 to short BFP)","CEGBRA R1,M3,R2,M4","45988@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM FIXED (64 to short HFP)","CEGR R1,R2","46020@0|//@16|R1@24|R2@28|??@32","Da" +"CONVERT FROM LOGICAL (32 to extended BFP)","CXLFBR R1,M3,R2,M4","45970@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM LOGICAL (32 to extended DFP)","CXLFTR R1,M3,R2,M4","47451@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT FROM LOGICAL (32 to long BFP)","CDLFBR R1,M3,R2,M4","45969@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM LOGICAL (32 to long DFP)","CDLFTR R1,M3,R2,M4","47443@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERT FROM LOGICAL (32 to short BFP)","CELFBR R1,M3,R2,M4","45968@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM LOGICAL (64 to extended BFP)","CXLGBR R1,M3,R2,M4","45986@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM LOGICAL (64 to extended DFP)","CXLGTR R1,M3,R2,M4","47450@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT FROM LOGICAL (64 to long BFP)","CDLGBR R1,M3,R2,M4","45985@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM LOGICAL (64 to long DFP)","CDLGTR R1,M3,R2,M4","47442@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERT FROM LOGICAL (64 to short BFP)","CELGBR R1,M3,R2,M4","45984@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT FROM PACKED (to extended DFP)","CXPT R1,D2(L2,B2),M3","237@0|L2@8|B2@16|D2@20|R1@32|M3@36|175@40|??@48","SP Dt" +"CONVERT FROM PACKED (to long DFP)","CDPT R1,D2(L2,B2),M3","237@0|L2@8|B2@16|D2@20|R1@32|M3@36|174@40|??@48","SP Dt" +"CONVERT FROM SIGNED PACKED (128 to extended DFP)","CXSTR R1,R2","46075@0|//@16|R1@24|R2@28|??@32","SP Dt" +"CONVERT FROM SIGNED PACKED (64 to long DFP)","CDSTR R1,R2","46067@0|//@16|R1@24|R2@28|??@32","Dt" +"CONVERT FROM UNSIGNED PACKED (128 to ext. DFP)","CXUTR R1,R2","46074@0|//@16|R1@24|R2@28|??@32","SP Dt" +"CONVERT FROM UNSIGNED PACKED (64 to long DFP)","CDUTR R1,R2","46066@0|//@16|R1@24|R2@28|??@32","Dt" +"CONVERT FROM ZONED (to extended DFP)","CXZT R1,D2(L2,B2),M3","237@0|L2@8|B2@16|D2@20|R1@32|M3@36|171@40|??@48","SP Dt" +"CONVERT FROM ZONED (to long DFP)","CDZT R1,D2(L2,B2),M3","237@0|L2@8|B2@16|D2@20|R1@32|M3@36|170@40|??@48","SP Dt" +"CONVERT HFP TO BFP (long to short)","TBEDR R1,M3,R2","45904@0|M3@16|//@20|R1@24|R2@28|??@32","SP Da" +"CONVERT HFP TO BFP (long)","TBDR R1,M3,R2","45905@0|M3@16|//@20|R1@24|R2@28|??@32","SP Da" +"CONVERT TO BINARY (32)","CVB R1,D2(X2,B2)","79@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"CONVERT TO BINARY (32)","CVBY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|6@40|??@48","B" +"CONVERT TO BINARY (64)","CVBG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|14@40|??@48","B" +"CONVERT TO DECIMAL (32)","CVD R1,D2(X2,B2)","78@0|R1@8|X2@12|B2@16|D2@20|??@32","ST" +"CONVERT TO DECIMAL (32)","CVDY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|38@40|??@48","ST" +"CONVERT TO DECIMAL (64)","CVDG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|46@40|??@48","ST" +"CONVERT TO FIXED (extended BFP to 32)","CFXBR R1,M3,R2","45978@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (extended BFP to 32)","CFXBRA R1,M3,R2,M4","45978@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (extended BFP to 64)","CGXBR R1,M3,R2","45994@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (extended BFP to 64)","CGXBRA R1,M3,R2,M4","45994@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (extended DFP to 32)","CFXTR R1,M3,R2,M4","47433@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT TO FIXED (extended DFP to 64)","CGXTR R1,M3,R2","46057@0|M3@16|//@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT TO FIXED (extended DFP to 64)","CGXTRA R1,M3,R2,M4","46057@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT TO FIXED (extended HFP to 32)","CFXR R1,M3,R2","46010@0|M3@16|//@20|R1@24|R2@28|??@32","SP Da" +"CONVERT TO FIXED (extended HFP to 64)","CGXR R1,M3,R2","46026@0|M3@16|//@20|R1@24|R2@28|??@32","SP Da" +"CONVERT TO FIXED (long BFP to 32)","CFDBR R1,M3,R2","45977@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (long BFP to 32)","CFDBRA R1,M3,R2,M4","45977@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (long BFP to 64)","CGDBR R1,M3,R2","45993@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (long BFP to 64)","CGDBRA R1,M3,R2,M4","45993@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (long DFP to 32)","CFDTR R1,M3,R2,M4","47425@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERT TO FIXED (long DFP to 64)","CGDTR R1,M3,R2","46049@0|M3@16|//@20|R1@24|R2@28|??@32","Dt" +"CONVERT TO FIXED (long DFP to 64)","CGDTRA R1,M3,R2,M4","46049@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERT TO FIXED (long HFP to 32)","CFDR R1,M3,R2","46009@0|M3@16|//@20|R1@24|R2@28|??@32","SP Da" +"CONVERT TO FIXED (long HFP to 64)","CGDR R1,M3,R2","46025@0|M3@16|//@20|R1@24|R2@28|??@32","SP Da" +"CONVERT TO FIXED (short BFP to 32)","CFEBR R1,M3,R2","45976@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (short BFP to 32)","CFEBRA R1,M3,R2,M4","45976@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (short BFP to 64)","CGEBR R1,M3,R2","45992@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (short BFP to 64)","CGEBRA R1,M3,R2,M4","45992@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO FIXED (short HFP to 32)","CFER R1,M3,R2","46008@0|M3@16|//@20|R1@24|R2@28|??@32","SP Da" +"CONVERT TO FIXED (short HFP to 64)","CGER R1,M3,R2","46024@0|M3@16|//@20|R1@24|R2@28|??@32","SP Da" +"CONVERT TO LOGICAL (extended BFP to 32)","CLFXBR R1,M3,R2,M4","45982@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO LOGICAL (extended BFP to 64)","CLGXBR R1,M3,R2,M4","45998@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO LOGICAL (extended DFP to 32)","CLFXTR R1,M3,R2,M4","47435@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT TO LOGICAL (extended DFP to 64)","CLGXTR R1,M3,R2,M4","47434@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT TO LOGICAL (long BFP to 32)","CLFDBR R1,M3,R2,M4","45981@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO LOGICAL (long BFP to 64)","CLGDBR R1,M3,R2,M4","45997@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO LOGICAL (long DFP to 32)","CLFDTR R1,M3,R2,M4","47427@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERT TO LOGICAL (long DFP to 64)","CLGDTR R1,M3,R2,M4","47426@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERT TO LOGICAL (short BFP to 32)","CLFEBR R1,M3,R2,M4","45980@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO LOGICAL (short BFP to 64)","CLGEBR R1,M3,R2,M4","45996@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"CONVERT TO PACKED (from extended DFP)","CPXT R1,D2(L2,B2),M3","237@0|L2@8|B2@16|D2@20|R1@32|M3@36|173@40|??@48","SP Dt" +"CONVERT TO PACKED (from long DFP)","CPDT R1,D2(L2,B2),M3","237@0|L2@8|B2@16|D2@20|R1@32|M3@36|172@40|??@48","SP Dt" +"CONVERT TO SIGNED PACKED (extended DFP to 128)","CSXTR R1,R2,M4","46059@0|//@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"CONVERT TO SIGNED PACKED (long DFP to 64)","CSDTR R1,R2,M4","46051@0|//@16|M4@20|R1@24|R2@28|??@32","Dt" +"CONVERTTOUNSIGNEDPACKED(extendedDFP to 128)","CUXTR R1,R2","46058@0|//@16|R1@24|R2@28|??@32","SP Dt" +"CONVERT TO UNSIGNED PACKED (long DFP to 64)","CUDTR R1,R2","46050@0|//@16|R1@24|R2@28|??@32","Dt" +"CONVERT TO ZONED (from extended DFP)","CZXT R1,D2(L2,B2),M3","237@0|L2@8|B2@16|D2@20|R1@32|M3@36|169@40|??@48","SP" +"CONVERT TO ZONED (from long DFP)","CZDT R1,D2(L2,B2),M3","237@0|L2@8|B2@16|D2@20|R1@32|M3@36|168@40|??@48","SP" +"CONVERT UNICODE TO UTF-8","CUUTF R1,R2,M3","45734@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"CONVERT UTF-16 TO UTF-32","CU24 R1,R2,M3","47537@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"CONVERT UTF-16 TO UTF-8","CU21 R1,R2,M3","45734@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"CONVERT UTF-8 TO UNICODE","CUTFU R1,R2,M3","45735@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"CONVERT UTF-8 TO UTF-16","CU12 R1,R2,M3","45735@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"CONVERT UTF-8 TO UTF-32","CU14 R1,R2,M3","47536@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"CONVERT UTF-32 TO UTF-16","CU42 R1,R2","47539@0|//@16|R1@24|R2@28|??@32","SP IC" +"CONVERT UTF-32 TO UTF-8","CU41 R1,R2","47538@0|//@16|R1@24|R2@28|??@32","SP IC" +"COPY ACCESS","CPYA R1,R2","45645@0|//@16|R1@24|R2@28|??@32","U" +"COPY SIGN (long)","CPSDR R1,R3,R2","45938@0|R3@16|//@20|R1@24|R2@28|??@32","Da" +"DECIMAL SCALE AND CONVERT AND SPLIT TO HFP","VSCSHP V1,V2,V3","230@0|V1@8|V2@12|V3@16|//@20|RXB@36|124@40|??@48","Dv" +"DECIMAL SCALE AND CONVERT TO HFP","VSCHP V1,V2,V3,M4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|116@40|??@48","SP Dv" +"DEFLATE CONVERSION CALL","DFLTCC R1,R2,R3","47417@0|R3@16|//@20|R1@24|R2@28|??@32","SP IC" +"DIVIDE (32→64)","D R1,D2(X2,B2)","93@0|R1@8|X2@12|B2@16|D2@20|??@32","SP" +"DIVIDE (32←64)","DR R1,R2","29@0|R1@8|R2@12|??@16","SP" +"DIVIDE (extended BFP)","DXBR R1,R2","45901@0|//@16|R1@24|R2@28|??@32","SP Db" +"DIVIDE (extended DFP)","DXTR R1,R2,R3","46041@0|R3@16|//@20|R1@24|R2@28|??@32","SP Dt" +"DIVIDE (extended DFP)","DXTRA R1,R2,R3,M4","46041@0|R3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"DIVIDE (extended HFP)","DXR R1,R2","45613@0|//@16|R1@24|R2@28|??@32","SP Da" +"DIVIDE (long BFP)","DDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|29@40|??@48","Db" +"DIVIDE (long BFP)","DDBR R1,R2","45853@0|//@16|R1@24|R2@28|??@32","Db" +"DIVIDE (long DFP)","DDTR R1,R2,R3","46033@0|R3@16|//@20|R1@24|R2@28|??@32","Dt" +"DIVIDE (long DFP)","DDTRA R1,R2,R3,M4","46033@0|R3@16|M4@20|R1@24|R2@28|??@32","Dt" +"DIVIDE (long HFP)","DD R1,D2(X2,B2)","109@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"DIVIDE (long HFP)","DDR R1,R2","45@0|R1@8|R2@12|??@16","Da" +"DIVIDE (short BFP)","DEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|13@40|??@48","Db" +"DIVIDE (short BFP)","DEBR R1,R2","45837@0|//@16|R1@24|R2@28|??@32","Db" +"DIVIDE (short HFP)","DE R1,D2(X2,B2)","125@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"DIVIDE (short HFP)","DER R1,R2","61@0|R1@8|R2@12|??@16","Da" +"DIVIDE DECIMAL","DP D1(L1,B1),D2(L2,B2)","253@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","SP Dg" +"DIVIDE LOGICAL (32→64)","DL R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|151@40|??@48","SP" +"DIVIDE LOGICAL (32←64)","DLR R1,R2","47511@0|//@16|R1@24|R2@28|??@32","SP" +"DIVIDE LOGICAL (64←128)","DLG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|135@40|??@48","SP" +"DIVIDE LOGICAL (64→128)","DLGR R1,R2","47495@0|//@16|R1@24|R2@28|??@32","SP" +"DIVIDE SINGLE (64)","DSG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|13@40|??@48","SP" +"DIVIDE SINGLE (64)","DSGR R1,R2","47373@0|//@16|R1@24|R2@28|??@32","SP" +"DIVIDE SINGLE (64←32)","DSGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|29@40|??@48","SP" +"DIVIDE SINGLE (64→32)","DSGFR R1,R2","47389@0|//@16|R1@24|R2@28|??@32","SP" +"DIVIDE TO INTEGER (long BFP)","DIDBR R1,R3,R2,M4","45915@0|R3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"DIVIDE TO INTEGER (short BFP)","DIEBR R1,R3,R2,M4","45907@0|R3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"EDIT","ED D1(L1,B1),D2(B2)","222@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","Dg" +"EDIT AND MARK","EDMK D1(L1,B1),D2(B2)","223@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","Dg" +"EXCLUSIVE OR (32)","X R1,D2(X2,B2)","87@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"EXCLUSIVE OR (32)","XR R1,R2","23@0|R1@8|R2@12|??@16","17" +"EXCLUSIVE OR (32)","XRK R1,R2,R3","47607@0|R3@16|//@20|R1@24|R2@28|??@32","B9F7" +"EXCLUSIVE OR (32)","XY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|87@40|??@48","B" +"EXCLUSIVE OR (64)","XG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|130@40|??@48","B" +"EXCLUSIVE OR (64)","XGR R1,R2","47490@0|//@16|R1@24|R2@28|??@32","B982" +"EXCLUSIVE OR (64)","XGRK R1,R2,R3","47591@0|R3@16|//@20|R1@24|R2@28|??@32","B9E7" +"EXCLUSIVE OR (character)","XC D1(L1,B1),D2(B2)","215@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"EXCLUSIVE OR (immediate)","XI D1(B1),I2","151@0|I2@8|B1@16|D1@20|??@32","ST" +"EXCLUSIVE OR (immediate)","XIY D1(B1),I2","235@0|I2@8|B1@16|D1@20|87@40|??@48","ST" +"EXCLUSIVE OR IMMEDIATE (high)","XIHF R1,I2","192@0|R1@8|6@12|I2@16|??@48","C06" +"EXCLUSIVE OR IMMEDIATE (low)","XILF R1,I2","192@0|R1@8|7@12|I2@16|??@48","C07" +"EXECUTE","EX R1,D2(X2,B2)","68@0|R1@8|X2@12|B2@16|D2@20|??@32","SP" +"EXECUTE RELATIVE LONG","EXRL R1,RI2","198@0|R1@8|0@12|RI2@16|??@48","C60" +"EXTRACT ACCESS","EAR R1,R2","45647@0|//@16|R1@24|R2@28|??@32","U" +"EXTRACT AND SET EXTENDED AUTHORITY","ESEA R1","47517@0|//@16|R1@24|//@28|??@32","B99D" +"EXTRACT BIASED EXPONENT (extended DFP to 64)","EEXTR R1,R2","46061@0|//@16|R1@24|R2@28|??@32","SP Dt" +"EXTRACT BIASED EXPONENT (long DFP to 64)","EEDTR R1,R2","46053@0|//@16|R1@24|R2@28|??@32","Dt" +"EXTRACT CPU ATTRIBUTE","ECAG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|76@40|??@48","EB4C" +"EXTRACT CPU TIME","ECTG D1(B1),D2(B2),R3","200@0|R3@8|1@12|B1@16|D1@20|B2@32|D2@36|??@48","R" +"EXTRACT FPC","EFPC R1","45964@0|//@16|R1@24|//@28|??@32","Db" +"EXTRACT PRIMARY ASN","EPAR R1","45606@0|//@16|R1@24|//@28|??@32","SO" +"EXTRACT PRIMARY ASN AND INSTANCE","EPAIR R1","47514@0|//@16|R1@24|//@28|??@32","SO" +"EXTRACT PSW","EPSW R1,R2","47501@0|//@16|R1@24|R2@28|??@32","B98D" +"EXTRACT SECONDARY ASN","ESAR R1","45607@0|//@16|R1@24|//@28|??@32","SO" +"EXTRACT SECONDARY ASN AND INSTANCE","ESAIR R1","47515@0|//@16|R1@24|//@28|??@32","SO" +"EXTRACT SIGNIFICANCE (extended DFP to 64)","ESXTR R1,R2","46063@0|//@16|R1@24|R2@28|??@32","SP Dt" +"EXTRACT SIGNIFICANCE (long DFP to 64)","ESDTR R1,R2","46055@0|//@16|R1@24|R2@28|??@32","Dt" +"EXTRACT STACKED REGISTERS (32)","EREG R1,R2","45641@0|//@16|R1@24|R2@28|??@32","SE" +"EXTRACT STACKED REGISTERS (64)","EREGG R1,R2","47374@0|//@16|R1@24|R2@28|??@32","SE" +"EXTRACT STACKED STATE","ESTA R1,R2","45642@0|//@16|R1@24|R2@28|??@32","B24A" +"EXTRACT TRANSACTION NESTING DEPTH","ETND R1","45804@0|//@16|R1@24|//@28|??@32","SO" +"FIND LEFTMOST ONE","FLOGR R1,R2","47491@0|//@16|R1@24|R2@28|??@32","SP" +"HALT SUBCHANNEL","HSCH","45617@0|//@16|??@32","OP" +"HALVE (long HFP)","HDR R1,R2","36@0|R1@8|R2@12|??@16","Da" +"HALVE (short HFP)","HER R1,R2","52@0|R1@8|R2@12|??@16","Da" +"INSERT ADDRESS SPACE CONTROL","IAC R1","45604@0|//@16|R1@24|//@28|??@32","SO" +"INSERT BIASED EXPONENT (64 to extended DFP)","IEXTR R1,R3,R2","46078@0|R3@16|//@20|R1@24|R2@28|??@32","SP Dt" +"INSERT BIASED EXPONENT (64 to long DFP)","IEDTR R1,R3,R2","46070@0|R3@16|//@20|R1@24|R2@28|??@32","Dt" +"INSERT CHARACTER","IC R1,D2(X2,B2)","67@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"INSERT CHARACTER","ICY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|115@40|??@48","B" +"INSERT CHARACTERS UNDER MASK (high)","ICMH R1,M3,D2(B2)","235@0|R1@8|M3@12|B2@16|D2@20|128@40|??@48","B" +"INSERT CHARACTERS UNDER MASK (low)","ICM R1,M3,D2(B2)","191@0|R1@8|M3@12|B2@16|D2@20|??@32","B" +"INSERT CHARACTERS UNDER MASK (low)","ICMY R1,M3,D2(B2)","235@0|R1@8|M3@12|B2@16|D2@20|129@40|??@48","B" +"INSERT IMMEDIATE (high high)","IIHH R1,I2","165@0|R1@8|0@12|I2@16|??@32","A50" +"INSERT IMMEDIATE (high low)","IIHL R1,I2","165@0|R1@8|1@12|I2@16|??@32","A51" +"INSERT IMMEDIATE (high)","IIHF R1,I2","192@0|R1@8|8@12|I2@16|??@48","C08" +"INSERT IMMEDIATE (low high)","IILH R1,I2","165@0|R1@8|2@12|I2@16|??@32","A52" +"INSERT IMMEDIATE (low low)","IILL R1,I2","165@0|R1@8|3@12|I2@16|??@32","A53" +"INSERT IMMEDIATE (low)","IILF R1,I2","192@0|R1@8|9@12|I2@16|??@48","C09" +"INSERT PROGRAM MASK","IPM R1","45602@0|//@16|R1@24|//@28|??@32","B222" +"INSERT PSW KEY","IPK","45579@0|//@16|??@32","G2" +"INSERT REFERENCE BITS MULTIPLE","IRBM R1,R2","47532@0|//@16|R1@24|R2@28|??@32","B9AC" +"INSERT STORAGE KEY EXTENDED","ISKE R1,R2","45609@0|//@16|R1@24|R2@28|??@32","SO" +"INSERT VIRTUAL STORAGE KEY","IVSK R1,R2","45603@0|//@16|R1@24|R2@28|??@32","SO" +"INVALIDATE DAT TABLE ENTRY","IDTE R1,R3,R2,M4","47502@0|R3@16|M4@20|R1@24|R2@28|??@32","SP" +"INVALIDATE PAGE TABLE ENTRY","IPTE R1,R2,R3,M4","45601@0|R3@16|M4@20|R1@24|R2@28|??@32","SP II" +"LOAD (32)","L R1,D2(X2,B2)","88@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"LOAD (32)","LR R1,R2","24@0|R1@8|R2@12|??@16","18" +"LOAD (32)","LY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|88@40|??@48","B" +"LOAD (64)","LG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|4@40|??@48","B" +"LOAD (64)","LGR R1,R2","47364@0|//@16|R1@24|R2@28|??@32","B904" +"LOAD (64←32)","LGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|20@40|??@48","B" +"LOAD (64←32)","LGFR R1,R2","47380@0|//@16|R1@24|R2@28|??@32","B914" +"LOAD (extended)","LXR R1,R2","45925@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD (long)","LD R1,D2(X2,B2)","104@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"LOAD (long)","LDR R1,R2","40@0|R1@8|R2@12|??@16","Da" +"LOAD (long)","LDY R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|101@40|??@48","Da" +"LOAD (short)","LE R1,D2(X2,B2)","120@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"LOAD (short)","LER R1,R2","56@0|R1@8|R2@12|??@16","Da" +"LOAD (short)","LEY R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|100@40|??@48","Da" +"LOAD ACCESS MULTIPLE 7-268","LAM R1,R3,D2(B2)","154@0|R1@8|R3@12|B2@16|D2@20|??@32","SP" +"LOAD ACCESS MULTIPLE 7-268","LAMY R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|154@40|??@48","SP" +"LOAD ADDRESS","LA R1,D2(X2,B2)","65@0|R1@8|X2@12|B2@16|D2@20|??@32","41" +"LOAD ADDRESS","LAY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|113@40|??@48","E371" +"LOAD ADDRESS EXTENDED","LAE R1,D2(X2,B2)","81@0|R1@8|X2@12|B2@16|D2@20|??@32","U" +"LOAD ADDRESS EXTENDED","LAEY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|117@40|??@48","U" +"LOAD ADDRESS RELATIVE LONG","LARL R1,RI2","192@0|R1@8|0@12|RI2@16|??@48","C00" +"LOAD ADDRESS SPACE PARAMETERS","LASP D1(B1),D2(B2)","58624@0|B1@16|D1@20|B2@32|D2@36|??@48","SP SO" +"LOAD AND ADD (32)","LAA R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|248@40|??@48","SP" +"LOAD AND ADD (64)","LAAG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|232@40|??@48","SP" +"LOAD AND ADD LOGICAL (32)","LAAL R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|250@40|??@48","SP" +"LOAD AND ADD LOGICAL (64)","LAALG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|234@40|??@48","SP" +"LOAD AND AND (32)","LAN R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|244@40|??@48","SP" +"LOAD AND AND (64)","LANG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|228@40|??@48","SP" +"LOAD AND EXCLUSIVE OR (32)","LAX R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|247@40|??@48","SP" +"LOAD AND EXCLUSIVE OR (64)","LAXG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|231@40|??@48","SP" +"LOAD AND OR (32)","LAO R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|246@40|??@48","SP" +"LOAD AND OR (64)","LAOG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|230@40|??@48","SP" +"LOAD AND TEST (32)","LT R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|18@40|??@48","B" +"LOAD AND TEST (32)","LTR R1,R2","18@0|R1@8|R2@12|??@16","12" +"LOAD AND TEST (64)","LTG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|2@40|??@48","B" +"LOAD AND TEST (64)","LTGR R1,R2","47362@0|//@16|R1@24|R2@28|??@32","B902" +"LOAD AND TEST (64→32)","LTGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|50@40|??@48","B" +"LOAD AND TEST (64→32)","LTGFR R1,R2","47378@0|//@16|R1@24|R2@28|??@32","B912" +"LOAD AND TEST (extended BFP)","LTXBR R1,R2","45890@0|//@16|R1@24|R2@28|??@32","SP Db" +"LOAD AND TEST (extended DFP)","LTXTR R1,R2","46046@0|//@16|R1@24|R2@28|??@32","SP Dt" +"LOAD AND TEST (extended HFP)","LTXR R1,R2","45922@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD AND TEST (long BFP)","LTDBR R1,R2","45842@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD AND TEST (long DFP)","LTDTR R1,R2","46038@0|//@16|R1@24|R2@28|??@32","Dt" +"LOAD AND TEST (long HFP)","LTDR R1,R2","34@0|R1@8|R2@12|??@16","Da" +"LOAD AND TEST (short BFP)","LTEBR R1,R2","45826@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD AND TEST (short HFP)","LTER R1,R2","50@0|R1@8|R2@12|??@16","Da" +"LOAD AND TRAP (32L→32)","LAT R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|159@40|??@48","B" +"LOAD AND TRAP (64)","LGAT R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|133@40|??@48","B" +"LOAD AND ZERO RIGHTMOST BYTE (32)","LZRF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|59@40|??@48","B" +"LOAD AND ZERO RIGHTMOST BYTE (64)","LZRG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|42@40|??@48","B" +"LOAD BEAR","LBEAR D2(B2)","45568@0|B2@16|D2@20|??@32","SP" +"LOAD BYTE (32→8)","LB R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|118@40|??@48","E376" +"LOAD BYTE (32←8)","LBR R1,R2","47398@0|//@16|R1@24|R2@28|??@32","B926" +"LOAD BYTE (64→8)","LGB R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|119@40|??@48","E377" +"LOAD BYTE (64←8)","LGBR R1,R2","47366@0|//@16|R1@24|R2@28|??@32","B906" +"LOAD BYTE HIGH (32←8)","LBH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|192@40|??@48","B" +"LOAD COMPLEMENT (32)","LCR R1,R2","19@0|R1@8|R2@12|??@16","13" +"LOAD COMPLEMENT (64)","LCGR R1,R2","47363@0|//@16|R1@24|R2@28|??@32","B903" +"LOAD COMPLEMENT (64←32)","LCGFR R1,R2","47379@0|//@16|R1@24|R2@28|??@32","B913" +"LOAD COMPLEMENT (extended BFP)","LCXBR R1,R2","45891@0|//@16|R1@24|R2@28|??@32","SP Db" +"LOAD COMPLEMENT (extended HFP)","LCXR R1,R2","45923@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD COMPLEMENT (long BFP)","LCDBR R1,R2","45843@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD COMPLEMENT (long HFP)","LCDR R1,R2","35@0|R1@8|R2@12|??@16","Da" +"LOAD COMPLEMENT (long)","LCDFR R1,R2","45939@0|//@16|R1@24|R2@28|??@32","Da" +"LOAD COMPLEMENT (short BFP)","LCEBR R1,R2","45827@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD COMPLEMENT (short HFP)","LCER R1,R2","51@0|R1@8|R2@12|??@16","Da" +"LOAD CONTROL (32)","LCTL R1,R3,D2(B2)","183@0|R1@8|R3@12|B2@16|D2@20|??@32","SP" +"LOAD CONTROL (64)","LCTLG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|47@40|??@48","SP" +"LOAD COUNT TO BLOCK BOUNDARY","LCBB R1,D2(X2,B2),M3","231@0|R1@8|X2@12|B2@16|D2@20|M3@32|//@36|39@40|??@48","SP" +"LOAD FP INTEGER (extended BFP)","FIXBR R1,M3,R2","45895@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"LOAD FP INTEGER (extended BFP)","FIXBRA R1,M3,R2,M4","45895@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"LOAD FP INTEGER (extended DFP)","FIXTR R1,M3,R2,M4","46047@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"LOAD FP INTEGER (extended HFP)","FIXR R1,R2","45927@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD FP INTEGER (long BFP)","FIDBR R1,M3,R2","45919@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"LOAD FP INTEGER (long BFP)","FIDBRA R1,M3,R2,M4","45919@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"LOAD FP INTEGER (long DFP)","FIDTR R1,M3,R2,M4","46039@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"LOAD FP INTEGER (long HFP)","FIDR R1,R2","45951@0|//@16|R1@24|R2@28|??@32","Da" +"LOAD FP INTEGER (short BFP)","FIEBR R1,M3,R2","45911@0|M3@16|//@20|R1@24|R2@28|??@32","SP Db" +"LOAD FP INTEGER (short BFP)","FIEBRA R1,M3,R2,M4","45911@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"LOAD FP INTEGER (short HFP)","FIER R1,R2","45943@0|//@16|R1@24|R2@28|??@32","Da" +"LOAD FPC","LFPC D2(B2)","45725@0|B2@16|D2@20|??@32","SP Db" +"LOAD FPC AND SIGNAL","LFAS D2(B2)","45757@0|B2@16|D2@20|??@32","SP Dt" +"LOAD FPR FROM GR (64 to long)","LDGR R1,R2","46017@0|//@16|R1@24|R2@28|??@32","Da" +"LOAD GR FROM FPR (long to 64)","LGDR R1,R2","46029@0|//@16|R1@24|R2@28|??@32","Da" +"LOAD GUARDED (64)","LGG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|76@40|??@48","SP" +"LOAD GUARDED STORAGE CONTROLS","LGSC R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|77@40|??@48","SO" +"LOAD HALFWORD (32→16)","LH R1,D2(X2,B2)","72@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"LOAD HALFWORD (32←16)","LHR R1,R2","47399@0|//@16|R1@24|R2@28|??@32","B927" +"LOAD HALFWORD (32←16)","LHY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|120@40|??@48","B" +"LOAD HALFWORD (64←16)","LGH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|21@40|??@48","B" +"LOAD HALFWORD (64←16)","LGHR R1,R2","47367@0|//@16|R1@24|R2@28|??@32","B907" +"LOAD HALFWORD HIGH (32→16)","LHH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|196@40|??@48","B" +"LOAD HALFWORD HIGH IMMEDIATE ON","LOCHHI R1,I2,M3","236@0|R1@8|M3@12|I2@16|//@32|78@40|??@48","EC4E" +"CONDITION (32←16)LOAD HALFWORD IMMEDIATE (32)←16","LHI R1,I2","167@0|R1@8|8@12|I2@16|??@32","A78" +"LOAD HALFWORD IMMEDIATE (64→16)","LGHI R1,I2","167@0|R1@8|9@12|I2@16|??@32","A79" +"LOAD HALFWORD IMMEDIATE ON CONDITION(32←16)","LOCHI R1,I2,M3","236@0|R1@8|M3@12|I2@16|//@32|66@40|??@48","EC42" +"LOAD HALFWORD IMMEDIATE ON CONDITION(64→16)","LOCGHI R1,I2,M3","236@0|R1@8|M3@12|I2@16|//@32|70@40|??@48","EC46" +"LOAD HALFWORD RELATIVE LONG (32←16)","LHRL R1,RI2","196@0|R1@8|5@12|RI2@16|??@48","C45" +"LOAD HALFWORD RELATIVE LONG (64←16)","LGHRL R1,RI2","196@0|R1@8|4@12|RI2@16|??@48","C44" +"LOAD HIGH (32)","LFH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|202@40|??@48","B" +"LOAD HIGH AND TRAP (32H←32)","LFHAT R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|200@40|??@48","B" +"LOAD HIGH ON CONDITION (32)","LOCFH R1,D2(B2),M3","235@0|R1@8|M3@12|B2@16|D2@20|224@40|??@48","B" +"LOAD HIGH ON CONDITION (32)","LOCFHR R1,R2,M3","47584@0|M3@16|//@20|R1@24|R2@28|??@32","B9E0" +"LOAD IMMEDIATE (64→32)","LGFI R1,I2","192@0|R1@8|1@12|I2@16|??@48","C01" +"LOAD LENGTHENED (long to extended BFP)","LXDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|5@40|??@48","SP Db" +"LOAD LENGTHENED (long to extended BFP)","LXDBR R1,R2","45829@0|//@16|R1@24|R2@28|??@32","SP Db" +"LOAD LENGTHENED (long to extended DFP)","LXDTR R1,R2,M4","46044@0|//@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"LOAD LENGTHENED (long to extended HFP)","LXD R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|37@40|??@48","SP Da" +"LOAD LENGTHENED (long to extended HFP)","LXDR R1,R2","45861@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD LENGTHENED (short to extended BFP)","LXEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|6@40|??@48","SP Db" +"LOAD LENGTHENED (short to extended BFP)","LXEBR R1,R2","45830@0|//@16|R1@24|R2@28|??@32","SP Db" +"LOAD LENGTHENED (short to extended HFP)","LXE R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|38@40|??@48","SP Da" +"LOAD LENGTHENED (short to extended HFP)","LXER R1,R2","45862@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD LENGTHENED (short to long BFP)","LDEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|4@40|??@48","Db" +"LOAD LENGTHENED (short to long BFP)","LDEBR R1,R2","45828@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD LENGTHENED (short to long DFP)","LDETR R1,R2,M4","46036@0|//@16|M4@20|R1@24|R2@28|??@32","Dt" +"LOAD LENGTHENED (short to long HFP)","LDE R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|36@40|??@48","Da" +"LOAD LENGTHENED (short to long HFP)","LDER R1,R2","45860@0|//@16|R1@24|R2@28|??@32","Da" +"LOAD LOGICAL (64←32)","LLGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|22@40|??@48","B" +"LOAD LOGICAL (64←32)","LLGFR R1,R2","47382@0|//@16|R1@24|R2@28|??@32","B916" +"LOAD LOGICAL AND SHIFT GUARDED (64←32)","LLGFSG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|72@40|??@48","SP" +"LOAD LOGICAL AND TRAP (64→32)","LLGFAT R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|157@40|??@48","B" +"LOAD LOGICAL AND ZERO RIGHTMOST BYTE(64→32)","LLZRGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|58@40|??@48","B" +"LOAD LOGICAL CHARACTER (32→8)","LLC R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|148@40|??@48","B" +"LOAD LOGICAL CHARACTER (32←8)","LLCR R1,R2","47508@0|//@16|R1@24|R2@28|??@32","B994" +"LOAD LOGICAL CHARACTER (64←8)","LLGC R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|144@40|??@48","B" +"LOAD LOGICAL CHARACTER (64←8)","LLGCR R1,R2","47492@0|//@16|R1@24|R2@28|??@32","B984" +"LOAD LOGICAL CHARACTER HIGH (32←8)","LLCH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|194@40|??@48","B" +"LOAD LOGICAL HALFWORD (32←16)","LLH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|149@40|??@48","B" +"LOAD LOGICAL HALFWORD (32←16)","LLHR R1,R2","47509@0|//@16|R1@24|R2@28|??@32","B995" +"LOAD LOGICAL HALFWORD (64→16)","LLGH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|145@40|??@48","B" +"LOAD LOGICAL HALFWORD (64←16)","LLGHR R1,R2","47493@0|//@16|R1@24|R2@28|??@32","B985" +"LOAD LOGICAL HALFWORD HIGH (32→16)","LLHH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|198@40|??@48","B" +"LOAD LOGICAL HALFWORD RELATIVE LONG(32←16)","LLHRL R1,RI2","196@0|R1@8|2@12|RI2@16|??@48","C42" +"LOAD LOGICAL HALFWORD RELATIVE LONG(64→16)","LLGHRL R1,RI2","196@0|R1@8|6@12|RI2@16|??@48","C46" +"LOAD LOGICAL IMMEDIATE (high high)","LLIHH R1,I2","165@0|R1@8|12@12|I2@16|??@32","A5C" +"LOAD LOGICAL IMMEDIATE (high low)","LLIHL R1,I2","165@0|R1@8|13@12|I2@16|??@32","A5D" +"LOAD LOGICAL IMMEDIATE (high)","LLIHF R1,I2","192@0|R1@8|14@12|I2@16|??@48","C0E" +"LOAD LOGICAL IMMEDIATE (low high)","LLILH R1,I2","165@0|R1@8|14@12|I2@16|??@32","A5E" +"LOAD LOGICAL IMMEDIATE (low low)","LLILL R1,I2","165@0|R1@8|15@12|I2@16|??@32","A5F" +"LOAD LOGICAL IMMEDIATE (low)","LLILF R1,I2","192@0|R1@8|15@12|I2@16|??@48","C0F" +"LOAD LOGICAL RELATIVE LONG (64→32)","LLGFRL R1,RI2","196@0|R1@8|14@12|RI2@16|??@48","SP" +"LOAD LOGICAL THIRTY ONE BITS (64→31)","LLGT R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|23@40|??@48","B" +"LOAD LOGICAL THIRTY ONE BITS (64→31)","LLGTR R1,R2","47383@0|//@16|R1@24|R2@28|??@32","B917" +"LOAD LOGICAL THIRTY ONE BITS AND TRAP(64←31)","LLGTAT R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|156@40|??@48","B" +"LOAD MULTIPLE (32)","LM R1,R3,D2(B2)","152@0|R1@8|R3@12|B2@16|D2@20|??@32","B" +"LOAD MULTIPLE (32)","LMY R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|152@40|??@48","B" +"LOAD MULTIPLE (64)","LMG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|4@40|??@48","B" +"LOAD MULTIPLE DISJOINT (64→32&32)","LMD R1,R3,D2(B2),D4(B4)","239@0|R1@8|R3@12|B2@16|D2@20|B4@32|D4@36|??@48","B" +"LOAD MULTIPLE HIGH (32)","LMH R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|150@40|??@48","B" +"LOAD NEGATIVE (32)","LNR R1,R2","17@0|R1@8|R2@12|??@16","11" +"LOAD NEGATIVE (64)","LNGR R1,R2","47361@0|//@16|R1@24|R2@28|??@32","B901" +"LOAD NEGATIVE (64→32)","LNGFR R1,R2","47377@0|//@16|R1@24|R2@28|??@32","B911" +"LOAD NEGATIVE (extended BFP)","LNXBR R1,R2","45889@0|//@16|R1@24|R2@28|??@32","SP Db" +"LOAD NEGATIVE (extended HFP)","LNXR R1,R2","45921@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD NEGATIVE (long BFP)","LNDBR R1,R2","45841@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD NEGATIVE (long HFP)","LNDR R1,R2","33@0|R1@8|R2@12|??@16","Da" +"LOAD NEGATIVE (long)","LNDFR R1,R2","45937@0|//@16|R1@24|R2@28|??@32","Da" +"LOAD NEGATIVE (short BFP)","LNEBR R1,R2","45825@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD NEGATIVE (short HFP)","LNER R1,R2","49@0|R1@8|R2@12|??@16","Da" +"LOAD ON CONDITION (32)","LOC R1,D2(B2),M3","235@0|R1@8|M3@12|B2@16|D2@20|242@40|??@48","B" +"LOAD ON CONDITION (32)","LOCR R1,R2,M3","47602@0|M3@16|//@20|R1@24|R2@28|??@32","B9F2" +"LOAD ON CONDITION (64)","LOCG R1,D2(B2),M3","235@0|R1@8|M3@12|B2@16|D2@20|226@40|??@48","B" +"LOAD ON CONDITION (64)","LOCGR R1,R2,M3","47586@0|M3@16|//@20|R1@24|R2@28|??@32","B9E2" +"LOAD PAGE TABLE ENTRY ADDRESS","LPTEA R1,R3,R2,M4","47530@0|R3@16|M4@20|R1@24|R2@28|??@32","R" +"LOAD PAIR DISJOINT (32)","LPD R3,D1(B1),D2(B2)","200@0|R3@8|4@12|B1@16|D1@20|B2@32|D2@36|??@48","SP" +"LOAD PAIR DISJOINT (64)","LPDG R3,D1(B1),D2(B2)","200@0|R3@8|5@12|B1@16|D1@20|B2@32|D2@36|??@48","SP" +"LOAD PAIR FROM QUADWORD (64&64←128)","LPQ R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|143@40|??@48","SP" +"LOAD POSITIVE (32)","LPR R1,R2","16@0|R1@8|R2@12|??@16","10" +"LOAD POSITIVE (64)","LPGR R1,R2","47360@0|//@16|R1@24|R2@28|??@32","B900" +"LOAD POSITIVE (64→32)","LPGFR R1,R2","47376@0|//@16|R1@24|R2@28|??@32","B910" +"LOAD POSITIVE (extended BFP)","LPXBR R1,R2","45888@0|//@16|R1@24|R2@28|??@32","SP Db" +"LOAD POSITIVE (extended HFP)","LPXR R1,R2","45920@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD POSITIVE (long BFP)","LPDBR R1,R2","45840@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD POSITIVE (long HFP)","LPDR R1,R2","32@0|R1@8|R2@12|??@16","Da" +"LOAD POSITIVE (long)","LPDFR R1,R2","45936@0|//@16|R1@24|R2@28|??@32","Da" +"LOAD POSITIVE (short BFP)","LPEBR R1,R2","45824@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD POSITIVE (short HFP)","LPER R1,R2","48@0|R1@8|R2@12|??@16","Da" +"LOAD PSW","LPSW D1(B1)","130@0|I2@8|B1@16|D1@20|??@32","SP SO" +"LOAD PSW EXTENDED","LPSWE D2(B2)","45746@0|B2@16|D2@20|??@32","SP SO" +"LOAD PSW EXTENDED","LPSWEY D1(B1)","235@0|//@8|B1@16|D1@20|113@40|??@48","SP SO" +"LOAD REAL ADDRESS (32)","LRA R1,D2(X2,B2)","177@0|R1@8|X2@12|B2@16|D2@20|??@32","SO" +"LOAD REAL ADDRESS (32)","LRAY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|19@40|??@48","SO" +"LOAD REAL ADDRESS (64)","LRAG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|3@40|??@48","BP" +"LOAD RELATIVE LONG (32)","LRL R1,RI2","196@0|R1@8|13@12|RI2@16|??@48","SP" +"LOAD RELATIVE LONG (64)","LGRL R1,RI2","196@0|R1@8|8@12|RI2@16|??@48","SP" +"LOAD RELATIVE LONG (64→32)","LGFRL R1,RI2","196@0|R1@8|12@12|RI2@16|??@48","SP" +"LOAD REVERSED (16)","LRVH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|31@40|??@48","B" +"LOAD REVERSED (32)","LRV R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|30@40|??@48","B" +"LOAD REVERSED (32)","LRVR R1,R2","47391@0|//@16|R1@24|R2@28|??@32","B91F" +"LOAD REVERSED (64)","LRVG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|15@40|??@48","B" +"LOAD REVERSED (64)","LRVGR R1,R2","47375@0|//@16|R1@24|R2@28|??@32","B90F" +"LOAD ROUNDED (extended to long BFP)","LDXBR R1,R2","45893@0|//@16|R1@24|R2@28|??@32","SP Db" +"LOAD ROUNDED (extended to long BFP)","LDXBRA R1,M3,R2,M4","45893@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"LOAD ROUNDED (extended to long DFP)","LDXTR R1,M3,R2,M4","46045@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"LOAD ROUNDED (extended to long HFP)","LDXR R1,R2","37@0|R1@8|R2@12|??@16","SP Da" +"LOAD ROUNDED (extended to long HFP)","LRDR R1,R2","37@0|R1@8|R2@12|??@16","SP Da" +"LOAD ROUNDED (extended to short BFP)","LEXBR R1,R2","45894@0|//@16|R1@24|R2@28|??@32","SP Db" +"LOAD ROUNDED (extended to short BFP)","LEXBRA R1,M3,R2,M4","45894@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"LOAD ROUNDED (extended to short HFP)","LEXR R1,R2","45926@0|//@16|R1@24|R2@28|??@32","SP Da" +"LOAD ROUNDED (long to short BFP)","LEDBR R1,R2","45892@0|//@16|R1@24|R2@28|??@32","Db" +"LOAD ROUNDED (long to short BFP)","LEDBRA R1,M3,R2,M4","45892@0|M3@16|M4@20|R1@24|R2@28|??@32","SP Db" +"LOAD ROUNDED (long to short DFP)","LEDTR R1,M3,R2,M4","46037@0|M3@16|M4@20|R1@24|R2@28|??@32","Dt" +"LOAD ROUNDED (long to short HFP)","LEDR R1,R2","53@0|R1@8|R2@12|??@16","Da" +"LOAD ROUNDED (long to short HFP)","LRER R1,R2","53@0|R1@8|R2@12|??@16","Da" +"LOAD USING REAL ADDRESS (32)","LURA R1,R2","45643@0|//@16|R1@24|R2@28|??@32","SP" +"LOAD USING REAL ADDRESS (64)","LURAG R1,R2","47365@0|//@16|R1@24|R2@28|??@32","SP" +"LOAD ZERO (extended)","LZXR R1","45942@0|//@16|R1@24|//@28|??@32","SP Da" +"LOAD ZERO (long)","LZDR R1","45941@0|//@16|R1@24|//@28|??@32","Da" +"LOAD ZERO (short)","LZER R1","45940@0|//@16|R1@24|//@28|??@32","Da" +"MODIFY STACKED STATE","MSTA R1","45639@0|//@16|R1@24|//@28|??@32","ST" +"MODIFY SUBCHANNEL","MSCH D2(B2)","45618@0|B2@16|D2@20|??@32","SP OP" +"MONITOR CALL","MC D1(B1),I2","175@0|I2@8|B1@16|D1@20|??@32","SP" +"MOVE (16←16)","MVHHI D1(B1),I2","58692@0|B1@16|D1@20|I2@32|??@48","ST" +"MOVE (32→16)","MVHI D1(B1),I2","58700@0|B1@16|D1@20|I2@32|??@48","ST" +"MOVE (64←16)","MVGHI D1(B1),I2","58696@0|B1@16|D1@20|I2@32|??@48","ST" +"MOVE (character)","MVC D1(L1,B1),D2(B2)","210@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"MOVE (immediate)","MVI D1(B1),I2","146@0|I2@8|B1@16|D1@20|??@32","ST" +"MOVE (immediate)","MVIY D1(B1),I2","235@0|I2@8|B1@16|D1@20|82@40|??@48","ST" +"MOVE INVERSE","MVCIN D1(L1,B1),D2(B2)","232@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"MOVE LONG","MVCL R1,R2","14@0|R1@8|R2@12|??@16","SP II" +"MOVE LONG EXTENDED","MVCLE R1,R3,D2(B2)","168@0|R1@8|R3@12|B2@16|D2@20|??@32","SP IC" +"MOVE LONG UNICODE","MVCLU R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|142@40|??@48","SP IC" +"MOVE NUMERICS","MVN D1(L1,B1),D2(B2)","209@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"MOVE PAGE","MVPG R1,R2","45652@0|//@16|R1@24|R2@28|??@32","SP SO" +"MOVE RIGHT TO LEFT","MVCRL D1(B1),D2(B2)","58634@0|B1@16|D1@20|B2@32|D2@36|??@48","G0" +"MOVE STRING","MVST R1,R2","45653@0|//@16|R1@24|R2@28|??@32","SP IC" +"MOVE TO PRIMARY","MVCP D1(R1,B1),D2(B2),R3","218@0|R1@8|R3@12|B1@16|D1@20|B2@32|D2@36|??@48","SO" +"MOVE TO SECONDARY","MVCS D1(R1,B1),D2(B2),R3","219@0|R1@8|R3@12|B1@16|D1@20|B2@32|D2@36|??@48","SO" +"MOVE WITH DESTINATION KEY","MVCDK D1(B1),D2(B2)","58639@0|B1@16|D1@20|B2@32|D2@36|??@48","SO" +"MOVE WITH KEY","MVCK D1(R1,B1),D2(B2),R3","217@0|R1@8|R3@12|B1@16|D1@20|B2@32|D2@36|??@48","SO" +"MOVE WITH OFFSET","MVO D1(L1,B1),D2(L2,B2)","241@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"MOVE WITH OPTIONAL SPECIFICATIONS","MVCOS D1(B1),D2(B2),R3","200@0|R3@8|0@12|B1@16|D1@20|B2@32|D2@36|??@48","SO" +"MOVE WITH SOURCE KEY","MVCSK D1(B1),D2(B2)","58638@0|B1@16|D1@20|B2@32|D2@36|??@48","SO" +"MOVE ZONES","MVZ D1(L1,B1),D2(B2)","211@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"MULTIPLY (128←64)","MG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|132@40|??@48","SP" +"MULTIPLY (128←64)","MGRK R1,R2,R3","47596@0|R3@16|//@20|R1@24|R2@28|??@32","SP" +"MULTIPLY (64←32)","M R1,D2(X2,B2)","92@0|R1@8|X2@12|B2@16|D2@20|??@32","SP" +"MULTIPLY (64←32)","MFY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|92@40|??@48","SP" +"MULTIPLY (64←32)","MR R1,R2","28@0|R1@8|R2@12|??@16","SP" +"MULTIPLY (extended BFP)","MXBR R1,R2","45900@0|//@16|R1@24|R2@28|??@32","SP Db" +"MULTIPLY (extended DFP)","MXTR R1,R2,R3","46040@0|R3@16|//@20|R1@24|R2@28|??@32","SP Dt" +"MULTIPLY (extended DFP)","MXTRA R1,R2,R3,M4","46040@0|R3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"MULTIPLY (extended HFP)","MXR R1,R2","38@0|R1@8|R2@12|??@16","SP Da" +"MULTIPLY (long BFP)","MDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|28@40|??@48","Db" +"MULTIPLY (long BFP)","MDBR R1,R2","45852@0|//@16|R1@24|R2@28|??@32","Db" +"MULTIPLY (long DFP)","MDTR R1,R2,R3","46032@0|R3@16|//@20|R1@24|R2@28|??@32","Dt" +"MULTIPLY (long DFP)","MDTRA R1,R2,R3,M4","46032@0|R3@16|M4@20|R1@24|R2@28|??@32","Dt" +"MULTIPLY (long HFP)","MD R1,D2(X2,B2)","108@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"MULTIPLY (long HFP)","MDR R1,R2","44@0|R1@8|R2@12|??@16","Da" +"MULTIPLY (long to extended BFP)","MXDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|7@40|??@48","SP Db" +"MULTIPLY (long to extended BFP)","MXDBR R1,R2","45831@0|//@16|R1@24|R2@28|??@32","SP Db" +"MULTIPLY (long to extended HFP)","MXD R1,D2(X2,B2)","103@0|R1@8|X2@12|B2@16|D2@20|??@32","SP Da" +"MULTIPLY (long to extended HFP)","MXDR R1,R2","39@0|R1@8|R2@12|??@16","SP Da" +"MULTIPLY (short BFP)","MEEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|23@40|??@48","Db" +"MULTIPLY (short BFP)","MEEBR R1,R2","45847@0|//@16|R1@24|R2@28|??@32","Db" +"MULTIPLY (short HFP)","MEE R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|55@40|??@48","Da" +"MULTIPLY (short HFP)","MEER R1,R2","45879@0|//@16|R1@24|R2@28|??@32","Da" +"MULTIPLY (short to long BFP)","MDEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|12@40|??@48","Db" +"MULTIPLY (short to long BFP)","MDEBR R1,R2","45836@0|//@16|R1@24|R2@28|??@32","Db" +"MULTIPLY (short to long HFP)","MDE R1,D2(X2,B2)","124@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"MULTIPLY (short to long HFP)","MDER R1,R2","60@0|R1@8|R2@12|??@16","Da" +"MULTIPLY (short to long HFP)","ME R1,D2(X2,B2)","124@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"MULTIPLY (short to long HFP)","MER R1,R2","60@0|R1@8|R2@12|??@16","Da" +"MULTIPLY & ADD UNNORMALIZED (long to ext. HFP)","MAY R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|58@40|??@48","Da" +"MULTIPLY & ADD UNNORMALIZED (long to ext. HFP)","MAYR R1,R3,R2","45882@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY AND ADD (long BFP)","MADB R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|30@40|??@48","Db" +"MULTIPLY AND ADD (long BFP)","MADBR R1,R3,R2","45854@0|R1@16|//@20|R3@24|R2@28|??@32","Db" +"MULTIPLY AND ADD (long HFP)","MAD R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|62@40|??@48","Da" +"MULTIPLY AND ADD (long HFP)","MADR R1,R3,R2","45886@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY AND ADD (short BFP)","MAEB R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|14@40|??@48","Db" +"MULTIPLY AND ADD (short BFP)","MAEBR R1,R3,R2","45838@0|R1@16|//@20|R3@24|R2@28|??@32","Db" +"MULTIPLY AND ADD (short HFP)","MAE R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|46@40|??@48","Da" +"MULTIPLY AND ADD (short HFP)","MAER R1,R3,R2","45870@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY AND ADD UNNRM. (long to ext. high HFP)","MAYH R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|60@40|??@48","Da" +"MULTIPLY AND ADD UNNRM. (long to ext. high HFP)","MAYHR R1,R3,R2","45884@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY AND ADD UNNRM. (long to ext. low HFP)","MAYL R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|56@40|??@48","Da" +"MULTIPLY AND ADD UNNRM. (long to ext. low HFP)","MAYLR R1,R3,R2","45880@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY AND SUBTRACT (long BFP)","MSDB R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|31@40|??@48","Db" +"MULTIPLY AND SUBTRACT (long BFP)","MSDBR R1,R3,R2","45855@0|R1@16|//@20|R3@24|R2@28|??@32","Db" +"MULTIPLY AND SUBTRACT (long HFP)","MSD R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|63@40|??@48","Da" +"MULTIPLY AND SUBTRACT (long HFP)","MSDR R1,R3,R2","45887@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY AND SUBTRACT (short BFP)","MSEB R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|15@40|??@48","Db" +"MULTIPLY AND SUBTRACT (short BFP)","MSEBR R1,R3,R2","45839@0|R1@16|//@20|R3@24|R2@28|??@32","Db" +"MULTIPLY AND SUBTRACT (short HFP)","MSE R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|47@40|??@48","Da" +"MULTIPLY AND SUBTRACT (short HFP)","MSER R1,R3,R2","45871@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY DECIMAL","MP D1(L1,B1),D2(L2,B2)","252@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","SP Dg" +"MULTIPLY HALFWORD (32←16)","MH R1,D2(X2,B2)","76@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"MULTIPLY HALFWORD (32←16)","MHY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|124@40|??@48","B" +"MULTIPLY HALFWORD (64→16)","MGH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|60@40|??@48","B" +"MULTIPLY HALFWORD IMMEDIATE (32→16)","MHI R1,I2","167@0|R1@8|12@12|I2@16|??@32","A7C" +"MULTIPLY HALFWORD IMMEDIATE (64→16)","MGHI R1,I2","167@0|R1@8|13@12|I2@16|??@32","A7D" +"MULTIPLY LOGICAL (128→64)","MLG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|134@40|??@48","SP" +"MULTIPLY LOGICAL (128→64)","MLGR R1,R2","47494@0|//@16|R1@24|R2@28|??@32","SP" +"MULTIPLY LOGICAL (64←32)","ML R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|150@40|??@48","SP" +"MULTIPLY LOGICAL (64←32)","MLR R1,R2","47510@0|//@16|R1@24|R2@28|??@32","SP" +"MULTIPLY SINGLE (32)","MS R1,D2(X2,B2)","113@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"MULTIPLY SINGLE (32)","MSC R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|83@40|??@48","B" +"MULTIPLY SINGLE (32)","MSR R1,R2","45650@0|//@16|R1@24|R2@28|??@32","B252" +"MULTIPLY SINGLE (32)","MSRKC R1,R2,R3","47613@0|R3@16|//@20|R1@24|R2@28|??@32","B9FD" +"MULTIPLY SINGLE (32)","MSY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|81@40|??@48","B" +"MULTIPLY SINGLE (64)","MSG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|12@40|??@48","B" +"MULTIPLY SINGLE (64)","MSGC R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|131@40|??@48","B" +"MULTIPLY SINGLE (64)","MSGR R1,R2","47372@0|//@16|R1@24|R2@28|??@32","B90C" +"MULTIPLY SINGLE (64)","MSGRKC R1,R2,R3","47597@0|R3@16|//@20|R1@24|R2@28|??@32","B9ED" +"MULTIPLY SINGLE (64←32)","MSGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|28@40|??@48","B" +"MULTIPLY SINGLE (64←32)","MSGFR R1,R2","47388@0|//@16|R1@24|R2@28|??@32","B91C" +"MULTIPLY SINGLE IMMEDIATE (32)","MSFI R1,I2","194@0|R1@8|1@12|I2@16|??@48","C21" +"MULTIPLY SINGLE IMMEDIATE (64←32)","MSGFI R1,I2","194@0|R1@8|0@12|I2@16|??@48","C20" +"MULTIPLY UNNORM. (long to ext. high HFP)","MYH R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|61@40|??@48","Da" +"MULTIPLY UNNORM. (long to ext. high HFP)","MYHR R1,R3,R2","45885@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY UNNORM. (long to ext. low HFP)","MYL R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|57@40|??@48","Da" +"MULTIPLY UNNORM. (long to ext. low HFP)","MYLR R1,R3,R2","45881@0|R1@16|//@20|R3@24|R2@28|??@32","Da" +"MULTIPLY UNNORMALIZED (long to ext. HFP)","MY R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|59@40|??@48","SP Da" +"MULTIPLY UNNORMALIZED (long to ext. HFP)","MYR R1,R3,R2","45883@0|R1@16|//@20|R3@24|R2@28|??@32","SP Da" +"NAND (32)","NNRK R1,R2,R3","47476@0|R3@16|//@20|R1@24|R2@28|??@32","B974" +"NAND (64)","NNGRK R1,R2,R3","47460@0|R3@16|//@20|R1@24|R2@28|??@32","B964" +"NEURAL NETWORK PROCESSING ASSIST","NNPA","47419@0|//@16|??@32","SP IC" +"NEXT INSTRUCTION ACCESS INTENT","NIAI I1,I2","45818@0|//@16|I1@24|I2@28|??@32","B2FA" +"NONTRANSACTIONAL STORE (64)","NTSTG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|37@40|??@48","SP" +"NOR (32)","NORK R1,R2,R3","47478@0|R3@16|//@20|R1@24|R2@28|??@32","B976" +"NOR (64)","NOGRK R1,R2,R3","47462@0|R3@16|//@20|R1@24|R2@28|??@32","B966" +"NOT EXCLUSIVE OR (32)","NXRK R1,R2,R3","47479@0|R3@16|//@20|R1@24|R2@28|??@32","B977" +"NOT EXCLUSIVE OR (64)","NXGRK R1,R2,R3","47463@0|R3@16|//@20|R1@24|R2@28|??@32","B967" +"OR (32)","O R1,D2(X2,B2)","86@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"OR (32)","OR R1,R2","22@0|R1@8|R2@12|??@16","16" +"OR (32)","ORK R1,R2,R3","47606@0|R3@16|//@20|R1@24|R2@28|??@32","B9F6" +"OR (32)","OY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|86@40|??@48","B" +"OR (64)","OG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|129@40|??@48","B" +"OR (64)","OGR R1,R2","47489@0|//@16|R1@24|R2@28|??@32","B981" +"OR (64)","OGRK R1,R2,R3","47590@0|R3@16|//@20|R1@24|R2@28|??@32","B9E6" +"OR (character)","OC D1(L1,B1),D2(B2)","214@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"OR (immediate)","OI D1(B1),I2","150@0|I2@8|B1@16|D1@20|??@32","ST" +"OR (immediate)","OIY D1(B1),I2","235@0|I2@8|B1@16|D1@20|86@40|??@48","ST" +"OR IMMEDIATE (high high)","OIHH R1,I2","165@0|R1@8|8@12|I2@16|??@32","A58" +"OR IMMEDIATE (high low)","OIHL R1,I2","165@0|R1@8|9@12|I2@16|??@32","A59" +"OR IMMEDIATE (high)","OIHF R1,I2","192@0|R1@8|12@12|I2@16|??@48","C0C" +"OR IMMEDIATE (low high)","OILH R1,I2","165@0|R1@8|10@12|I2@16|??@32","A5A" +"OR IMMEDIATE (low low)","OILL R1,I2","165@0|R1@8|11@12|I2@16|??@32","A5B" +"OR IMMEDIATE (low)","OILF R1,I2","192@0|R1@8|13@12|I2@16|??@48","C0D" +"OR WITH COMPLEMENT (32)","OCRK R1,R2,R3","47477@0|R3@16|//@20|R1@24|R2@28|??@32","B975" +"OR WITH COMPLEMENT (64)","OCGRK R1,R2,R3","47461@0|R3@16|//@20|R1@24|R2@28|??@32","B965" +"PACK","PACK D1(L1,B1),D2(L2,B2)","242@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"PACK ASCII","PKA D1(B1),D2(L2,B2)","233@0|L2@8|B1@16|D1@20|B2@32|D2@36|??@48","SP" +"PACK UNICODE","PKU D1(B1),D2(L2,B2)","225@0|L2@8|B1@16|D1@20|B2@32|D2@36|??@48","SP" +"PAGE IN","PGIN R1,R2","45614@0|//@16|R1@24|R2@28|??@32","B22E" +"PAGE OUT","PGOUT R1,R2","45615@0|//@16|R1@24|R2@28|??@32","B22F" +"PERFORM CRYPTOGRAPHIC COMPUTATION","PCC","47404@0|//@16|??@32","SP IC" +"PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS","PCKMO","47400@0|//@16|??@32","SP" +"PERFORM FLOATING-POINT OPERATION","PFPO","266@0|??@16","SP Da" +"PERFORM FRAME MANAGEMENT FUNCTION","PFMF R1,R2","47535@0|//@16|R1@24|R2@28|??@32","SP IS" +"PERFORM LOCKED OPERATION","PLO R1,D2(B2),R3,D4(B4)","238@0|R1@8|R3@12|B2@16|D2@20|B4@32|D4@36|??@48","SP" +"PERFORM PROCESSOR ASSIST","PPA R1,R2,M3","45800@0|M3@16|//@20|R1@24|R2@28|??@32","B2E8" +"PERFORM RANDOM NUMBER OPERATION","PPNO R1,R2","47420@0|//@16|R1@24|R2@28|??@32","SP IC" +"PERFORM RANDOM NUMBER OPERATION","PRNO R1,R2","47420@0|//@16|R1@24|R2@28|??@32","SP IC" +"PERFORM TIMING FACILITY FUNCTION","PTFF","260@0|??@16","SP" +"PERFORM TOPOLOGY FUNCTION","PTF R1","47522@0|//@16|R1@24|//@28|??@32","SP" +"POPULATION COUNT","POPCNT R1,R2,M3","47585@0|M3@16|//@20|R1@24|R2@28|??@32","B9E1" +"PREFETCH DATA","PFD M1,D2(X2,B2)","227@0|M1@8|X2@12|B2@16|D2@20|54@40|??@48","B" +"PREFETCH DATA RELATIVE LONG","PFDRL M1,RI2","198@0|M1@8|2@12|RI2@16|??@48","C62" +"PROGRAM CALL","PC D2(B2)","45592@0|B2@16|D2@20|??@32","Z" +"PROGRAM RETURN","PR","257@0|??@16","B ST" +"PROGRAM TRANSFER","PT R1,R2","45608@0|//@16|R1@24|R2@28|??@32","B" +"PROGRAM TRANSFER WITH INSTANCE","PTI R1,R2","47518@0|//@16|R1@24|R2@28|??@32","B" +"PURGE ALB","PALB","45640@0|//@16|??@32","B248" +"PURGE TLB","PTLB","45581@0|//@16|??@32","B20D" +"QUANTIZE (extended DFP)","QAXTR R1,R3,R2,M4","46077@0|R3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"QUANTIZE (long DFP)","QADTR R1,R3,R2,M4","46069@0|R3@16|M4@20|R1@24|R2@28|??@32","Dt" +"QUERY PROCESSOR ACTIVITY COUNTER INFORMATION","QPACI D2(B2)","45711@0|B2@16|D2@20|??@32","ST" +"REROUND (extended DFP)","RRXTR R1,R3,R2,M4","46079@0|R3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"REROUND (long DFP)","RRDTR R1,R3,R2,M4","46071@0|R3@16|M4@20|R1@24|R2@28|??@32","Dt" +"RESET CHANNEL PATH","RCHP","45627@0|//@16|??@32","B23B" +"RESET DAT PROTECTION","RDP R1,R3,R2,M4","47499@0|R3@16|M4@20|R1@24|R2@28|??@32","B98B" +"RESET REFERENCE BIT EXTENDED","RRBE R1,R2","45610@0|//@16|R1@24|R2@28|??@32","SO" +"RESET REFERENCE BITS MULTIPLE","RRBM R1,R2","47534@0|//@16|R1@24|R2@28|??@32","B9AE" +"RESUME PROGRAM","RP D2(B2)","45687@0|B2@16|D2@20|??@32","SP WE T" +"RESUME SUBCHANNEL","RSCH","45624@0|//@16|??@32","OP" +"ROTATE LEFT SINGLE LOGICAL (32)","RLL R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|29@40|??@48","EB1D" +"ROTATE LEFT SINGLE LOGICAL (64)","RLLG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|28@40|??@48","EB1C" +"ROTATE THEN AND SELECTED BITS (64)","RNSBG R1,R2,I3,I4,I5","236@0|R1@8|R2@12|I3@16|I4@24|I5@32|84@40|??@48","EC54" +"ROTATETHENEXCLUSIVEORSELECT.BITS(64)","RXSBG R1,R2,I3,I4,I5","236@0|R1@8|R2@12|I3@16|I4@24|I5@32|87@40|??@48","EC57" +"ROTATE THEN INSERT SELECTED BITS (64)","RISBG R1,R2,I3,I4,I5","236@0|R1@8|R2@12|I3@16|I4@24|I5@32|85@40|??@48","EC55" +"ROTATE THEN INSERT SELECTED BITS (64)","RISBGN R1,R2,I3,I4,I5","236@0|R1@8|R2@12|I3@16|I4@24|I5@32|89@40|??@48","EC59" +"ROTATE THEN INSERT SELECTED BITS HIGH(64)","RISBHG R1,R2,I3,I4,I5","236@0|R1@8|R2@12|I3@16|I4@24|I5@32|93@40|??@48","EC5D" +"ROTATE THEN INSERT SELECTED BITS LOW (64)","RISBLG R1,R2,I3,I4,I5","236@0|R1@8|R2@12|I3@16|I4@24|I5@32|81@40|??@48","EC51" +"ROTATE THEN OR SELECTED BITS (64)","ROSBG R1,R2,I3,I4,I5","236@0|R1@8|R2@12|I3@16|I4@24|I5@32|86@40|??@48","EC56" +"SEARCH STRING","SRST R1,R2","45662@0|//@16|R1@24|R2@28|??@32","SP IC" +"SEARCH STRING UNICODE","SRSTU R1,R2","47550@0|//@16|R1@24|R2@28|??@32","SP IC" +"SELECT (32)","SELR R1,R2,R3,M4","47600@0|R3@16|M4@20|R1@24|R2@28|??@32","B9F0" +"SELECT (64)","SELGR R1,R2,R3,M4","47587@0|R3@16|M4@20|R1@24|R2@28|??@32","B9E3" +"SELECT HIGH (32)","SELFHR R1,R2,R3,M4","47552@0|R3@16|M4@20|R1@24|R2@28|??@32","B9C0" +"SET ACCESS","SAR R1,R2","45646@0|//@16|R1@24|R2@28|??@32","U" +"SET ADDRESS LIMIT","SAL","45623@0|//@16|??@32","OP" +"SET ADDRESS SPACE CONTROL","SAC D2(B2)","45593@0|B2@16|D2@20|??@32","SP SW" +"SET ADDRESS SPACE CONTROL FAST","SACF D2(B2)","45689@0|B2@16|D2@20|??@32","SP SW" +"SET ADDRESSING MODE (24)","SAM24","268@0|??@16","SP" +"SET ADDRESSING MODE (31)","SAM31","269@0|??@16","SP" +"SET ADDRESSING MODE (64)","SAM64","270@0|??@16","010E" +"SET BFP ROUNDING MODE (2 bit)","SRNM D2(B2)","45721@0|B2@16|D2@20|??@32","Db" +"SET BFP ROUNDING MODE (3 bit)","SRNMB D2(B2)","45752@0|B2@16|D2@20|??@32","SP Db" +"SET CHANNEL MONITOR","SCHM","45628@0|//@16|??@32","OP" +"SET CLOCK","SCK D2(B2)","45572@0|B2@16|D2@20|??@32","SP" +"SET CLOCK COMPARATOR","SCKC D2(B2)","45574@0|B2@16|D2@20|??@32","SP" +"SET CLOCK PROGRAMMABLE FIELD","SCKPF","263@0|??@16","SP" +"SET CPU TIMER","SPT D2(B2)","45576@0|B2@16|D2@20|??@32","SP" +"SET DFP ROUNDING MODE","SRNMT D2(B2)","45753@0|B2@16|D2@20|??@32","Dt" +"SET FPC","SFPC R1","45956@0|//@16|R1@24|//@28|??@32","SP Db" +"SET FPC AND SIGNAL","SFASR R1","45957@0|//@16|R1@24|//@28|??@32","SP Dt" +"SET PREFIX","SPX D2(B2)","45584@0|B2@16|D2@20|??@32","SP" +"SET PROGRAM MASK","SPM R1","4@0|R1@8|//@12|??@16","04" +"SET PSW KEY FROM ADDRESS","SPKA D2(B2)","45578@0|B2@16|D2@20|??@32","SO" +"SET SECONDARY ASN","SSAR R1","45605@0|//@16|R1@24|//@28|??@32","Z" +"SET SECONDARY ASN WITH INSTANCE","SSAIR R1","47519@0|//@16|R1@24|//@28|??@32","Z" +"SET STORAGE KEY EXTENDED","SSKE R1,R2,M3","45611@0|M3@16|//@20|R1@24|R2@28|??@32","IS" +"SET SYSTEM MASK","SSM D1(B1)","128@0|I2@8|B1@16|D1@20|??@32","SP SO" +"SHIFT AND ROUND DECIMAL","SRP D1(L1,B1),D2(B2),I3","240@0|L1@8|I3@12|B1@16|D1@20|B2@32|D2@36|??@48","Dg" +"SHIFT LEFT DOUBLE (64)","SLDA R1,D2(B2)","143@0|R1@8|//@12|B2@16|D2@20|??@32","SP" +"SHIFT LEFT DOUBLE LOGICAL (64)","SLDL R1,D2(B2)","141@0|R1@8|//@12|B2@16|D2@20|??@32","SP" +"SHIFT LEFT SINGLE (32)","SLA R1,D2(B2)","139@0|R1@8|//@12|B2@16|D2@20|??@32","8B" +"SHIFT LEFT SINGLE (32)","SLAK R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|221@40|??@48","EBDD 7-383" +"SHIFT LEFT SINGLE (64)","SLAG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|11@40|??@48","EB0B" +"SHIFT LEFT SINGLE LOGICAL (32)","SLL R1,D2(B2)","137@0|R1@8|//@12|B2@16|D2@20|??@32","89" +"SHIFT LEFT SINGLE LOGICAL (32)","SLLK R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|223@40|??@48","EBDF" +"SHIFT LEFT SINGLE LOGICAL (64)","SLLG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|13@40|??@48","EB0D" +"SHIFT RIGHT DOUBLE (64)","SRDA R1,D2(B2)","142@0|R1@8|//@12|B2@16|D2@20|??@32","SP" +"SHIFT RIGHT DOUBLE LOGICAL (64)","SRDL R1,D2(B2)","140@0|R1@8|//@12|B2@16|D2@20|??@32","SP" +"SHIFT RIGHT SINGLE (32)","SRA R1,D2(B2)","138@0|R1@8|//@12|B2@16|D2@20|??@32","8A" +"SHIFT RIGHT SINGLE (32)","SRAK R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|220@40|??@48","EBDC 7-386" +"SHIFT RIGHT SINGLE (64)","SRAG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|10@40|??@48","EB0A" +"SHIFT RIGHT SINGLE LOGICAL (32)","SRL R1,D2(B2)","136@0|R1@8|//@12|B2@16|D2@20|??@32","88" +"SHIFT RIGHT SINGLE LOGICAL (32)","SRLK R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|222@40|??@48","EBDE 7-387" +"SHIFT RIGHT SINGLE LOGICAL (64)","SRLG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|12@40|??@48","EB0C" +"SHIFT SIGNIFICAND LEFT (extended DFP)","SLXT R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|72@40|??@48","SP Dt" +"SHIFT SIGNIFICAND LEFT (long DFP)","SLDT R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|64@40|??@48","Dt" +"SHIFT SIGNIFICAND RIGHT (extended DFP)","SRXT R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|73@40|??@48","SP Dt" +"SHIFT SIGNIFICAND RIGHT (long DFP)","SRDT R1,R3,D2(X2,B2)","237@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|65@40|??@48","Dt" +"SIGNAL PROCESSOR","SIGP R1,R3,D2(B2)","174@0|R1@8|R3@12|B2@16|D2@20|??@32","AE" +"SORT LISTS","SORTL R1,R2","47416@0|//@16|R1@24|R2@28|??@32","SP IC" +"SQUARE ROOT (extended BFP)","SQXBR R1,R2","45846@0|//@16|R1@24|R2@28|??@32","SP Db" +"SQUARE ROOT (extended HFP)","SQXR R1,R2","45878@0|//@16|R1@24|R2@28|??@32","SP Da" +"SQUARE ROOT (long BFP)","SQDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|21@40|??@48","Db" +"SQUARE ROOT (long BFP)","SQDBR R1,R2","45845@0|//@16|R1@24|R2@28|??@32","Db" +"SQUARE ROOT (long HFP)","SQD R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|53@40|??@48","Da" +"SQUARE ROOT (long HFP)","SQDR R1,R2","45636@0|//@16|R1@24|R2@28|??@32","Da" +"SQUARE ROOT (short BFP)","SQEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|20@40|??@48","Db" +"SQUARE ROOT (short BFP)","SQEBR R1,R2","45844@0|//@16|R1@24|R2@28|??@32","Db" +"SQUARE ROOT (short HFP)","SQE R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|52@40|??@48","Da" +"SQUARE ROOT (short HFP)","SQER R1,R2","45637@0|//@16|R1@24|R2@28|??@32","Da" +"START SUBCHANNEL","SSCH D2(B2)","45619@0|B2@16|D2@20|??@32","SP OP" +"STORE (32)","ST R1,D2(X2,B2)","80@0|R1@8|X2@12|B2@16|D2@20|??@32","ST" +"STORE (32)","STY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|80@40|??@48","ST" +"STORE (64)","STG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|36@40|??@48","ST" +"STORE (long)","STD R1,D2(X2,B2)","96@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"STORE (long)","STDY R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|103@40|??@48","Da" +"STORE (short)","STE R1,D2(X2,B2)","112@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"STORE (short)","STEY R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|102@40|??@48","Da" +"STORE ACCESS MULTIPLE 7-389","STAM R1,R3,D2(B2)","155@0|R1@8|R3@12|B2@16|D2@20|??@32","SP" +"STORE ACCESS MULTIPLE 7-389","STAMY R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|155@40|??@48","SP" +"STORE BEAR","STBEAR D2(B2)","45569@0|B2@16|D2@20|??@32","SP" +"STORE CHANNEL PATH STATUS","STCPS D2(B2)","45626@0|B2@16|D2@20|??@32","SP" +"STORE CHANNEL REPORT WORD","STCRW D2(B2)","45625@0|B2@16|D2@20|??@32","SP" +"STORE CHARACTER","STC R1,D2(X2,B2)","66@0|R1@8|X2@12|B2@16|D2@20|??@32","ST" +"STORE CHARACTER","STCY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|114@40|??@48","ST" +"STORE CHARACTER HIGH (8)","STCH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|195@40|??@48","ST" +"STORE CHARACTERS UNDER MASK (high)","STCMH R1,M3,D2(B2)","235@0|R1@8|M3@12|B2@16|D2@20|44@40|??@48","ST" +"STORE CHARACTERS UNDER MASK (low)","STCM R1,M3,D2(B2)","190@0|R1@8|M3@12|B2@16|D2@20|??@32","ST" +"STORE CHARACTERS UNDER MASK (low)","STCMY R1,M3,D2(B2)","235@0|R1@8|M3@12|B2@16|D2@20|45@40|??@48","ST" +"STORE CLOCK","STCK D2(B2)","45573@0|B2@16|D2@20|??@32","ST" +"STORE CLOCK COMPARATOR","STCKC D2(B2)","45575@0|B2@16|D2@20|??@32","SP" +"STORE CLOCK EXTENDED","STCKE D2(B2)","45688@0|B2@16|D2@20|??@32","ST" +"STORE CLOCK FAST","STCKF D2(B2)","45692@0|B2@16|D2@20|??@32","ST" +"STORE CONTROL (32)","STCTL R1,R3,D2(B2)","182@0|R1@8|R3@12|B2@16|D2@20|??@32","SP" +"STORE CONTROL (64)","STCTG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|37@40|??@48","SP" +"STORE CPU ADDRESS","STAP D2(B2)","45586@0|B2@16|D2@20|??@32","SP" +"STORE CPU ID","STIDP D2(B2)","45570@0|B2@16|D2@20|??@32","SP" +"STORE CPU TIMER","STPT D2(B2)","45577@0|B2@16|D2@20|??@32","SP" +"STORE FACILITY LIST","STFL D2(B2)","45745@0|B2@16|D2@20|??@32","B2B1" +"STORE FACILITY LIST EXTENDED","STFLE D2(B2)","45744@0|B2@16|D2@20|??@32","SP" +"STORE FPC","STFPC D2(B2)","45724@0|B2@16|D2@20|??@32","Db" +"STORE GUARDED STORAGE CONTROLS","STGSC R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|73@40|??@48","SO" +"STORE HALFWORD (16)","STH R1,D2(X2,B2)","64@0|R1@8|X2@12|B2@16|D2@20|??@32","ST" +"STORE HALFWORD (16)","STHY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|112@40|??@48","ST" +"STORE HALFWORD HIGH (16)","STHH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|199@40|??@48","ST" +"STORE HALFWORD RELATIVE LONG (16)","STHRL R1,RI2","196@0|R1@8|7@12|RI2@16|??@48","ST" +"STORE HIGH (32)","STFH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|203@40|??@48","ST" +"STORE HIGH ON CONDITION","STOCFH R1,D2(B2),M3","235@0|R1@8|M3@12|B2@16|D2@20|225@40|??@48","ST" +"STORE MULTIPLE (32)","STM R1,R3,D2(B2)","144@0|R1@8|R3@12|B2@16|D2@20|??@32","ST" +"STORE MULTIPLE (32)","STMY R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|144@40|??@48","ST" +"STORE MULTIPLE (64)","STMG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|36@40|??@48","ST" +"STORE MULTIPLE HIGH (32)","STMH R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|38@40|??@48","ST" +"STORE ON CONDITION (32)","STOC R1,D2(B2),M3","235@0|R1@8|M3@12|B2@16|D2@20|243@40|??@48","ST" +"STORE ON CONDITION (64)","STOCG R1,D2(B2),M3","235@0|R1@8|M3@12|B2@16|D2@20|227@40|??@48","ST" +"STORE PAIR TO QUADWORD","STPQ R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|142@40|??@48","SP" +"STORE PREFIX","STPX D2(B2)","45585@0|B2@16|D2@20|??@32","SP" +"STORE REAL ADDRESS","STRAG D1(B1),D2(B2)","58626@0|B1@16|D1@20|B2@32|D2@36|??@48","SP" +"STORE RELATIVE LONG (32)","STRL R1,RI2","196@0|R1@8|15@12|RI2@16|??@48","SP" +"STORE RELATIVE LONG (64)","STGRL R1,RI2","196@0|R1@8|11@12|RI2@16|??@48","SP" +"STORE REVERSED (16)","STRVH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|63@40|??@48","ST" +"STORE REVERSED (32)","STRV R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|62@40|??@48","ST" +"STORE REVERSED (64)","STRVG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|47@40|??@48","ST" +"STORE SUBCHANNEL","STSCH D2(B2)","45620@0|B2@16|D2@20|??@32","SP OP" +"STORE SYSTEM INFORMATION","STSI D2(B2)","45693@0|B2@16|D2@20|??@32","SP" +"STORE THEN AND SYSTEM MASK","STNSM D1(B1),I2","172@0|I2@8|B1@16|D1@20|??@32","ST" +"STORE THEN OR SYSTEM MASK","STOSM D1(B1),I2","173@0|I2@8|B1@16|D1@20|??@32","SP" +"STORE USING REAL ADDRESS (32)","STURA R1,R2","45638@0|//@16|R1@24|R2@28|??@32","SP" +"STORE USING REAL ADDRESS (64)","STURG R1,R2","47397@0|//@16|R1@24|R2@28|??@32","SP" +"SUBTRACT (32)","S R1,D2(X2,B2)","91@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"SUBTRACT (32)","SR R1,R2","27@0|R1@8|R2@12|??@16","1B" +"SUBTRACT (32)","SRK R1,R2,R3","47609@0|R3@16|//@20|R1@24|R2@28|??@32","B9F9" +"SUBTRACT (32)","SY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|91@40|??@48","B" +"SUBTRACT (64)","SG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|9@40|??@48","B" +"SUBTRACT (64)","SGR R1,R2","47369@0|//@16|R1@24|R2@28|??@32","B909" +"SUBTRACT (64)","SGRK R1,R2,R3","47593@0|R3@16|//@20|R1@24|R2@28|??@32","B9E9" +"SUBTRACT (64←32)","SGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|25@40|??@48","B" +"SUBTRACT (64→32)","SGFR R1,R2","47385@0|//@16|R1@24|R2@28|??@32","B919" +"SUBTRACT (extended BFP)","SXBR R1,R2","45899@0|//@16|R1@24|R2@28|??@32","SP Db" +"SUBTRACT (extended DFP)","SXTR R1,R2,R3","46043@0|R3@16|//@20|R1@24|R2@28|??@32","SP Dt" +"SUBTRACT (extended DFP)","SXTRA R1,R2,R3,M4","46043@0|R3@16|M4@20|R1@24|R2@28|??@32","SP Dt" +"SUBTRACT (long BFP)","SDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|27@40|??@48","Db" +"SUBTRACT (long BFP)","SDBR R1,R2","45851@0|//@16|R1@24|R2@28|??@32","Db" +"SUBTRACT (long DFP)","SDTR R1,R2,R3","46035@0|R3@16|//@20|R1@24|R2@28|??@32","Dt" +"SUBTRACT (long DFP)","SDTRA R1,R2,R3,M4","46035@0|R3@16|M4@20|R1@24|R2@28|??@32","Dt" +"SUBTRACT (short BFP)","SEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|11@40|??@48","Db" +"SUBTRACT (short BFP)","SEBR R1,R2","45835@0|//@16|R1@24|R2@28|??@32","Db" +"SUBTRACT DECIMAL","SP D1(L1,B1),D2(L2,B2)","251@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","Dg" +"SUBTRACT HALFWORD (32←16)","SH R1,D2(X2,B2)","75@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"SUBTRACT HALFWORD (32→16)","SHY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|123@40|??@48","B" +"SUBTRACT HALFWORD (64→16)","SGH R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|57@40|??@48","B" +"SUBTRACT HIGH (32)","SHHHR R1,R2,R3","47561@0|R3@16|//@20|R1@24|R2@28|??@32","B9C9" +"SUBTRACT HIGH (32)","SHHLR R1,R2,R3","47577@0|R3@16|//@20|R1@24|R2@28|??@32","B9D9" +"SUBTRACT LOGICAL (32)","SL R1,D2(X2,B2)","95@0|R1@8|X2@12|B2@16|D2@20|??@32","B" +"SUBTRACT LOGICAL (32)","SLR R1,R2","31@0|R1@8|R2@12|??@16","1F" +"SUBTRACT LOGICAL (32)","SLRK R1,R2,R3","47611@0|R3@16|//@20|R1@24|R2@28|??@32","B9FB" +"SUBTRACT LOGICAL (32)","SLY R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|95@40|??@48","B" +"SUBTRACT LOGICAL (64)","SLG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|11@40|??@48","B" +"SUBTRACT LOGICAL (64)","SLGR R1,R2","47371@0|//@16|R1@24|R2@28|??@32","B90B" +"SUBTRACT LOGICAL (64)","SLGRK R1,R2,R3","47595@0|R3@16|//@20|R1@24|R2@28|??@32","B9EB" +"SUBTRACT LOGICAL (64←32)","SLGF R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|27@40|??@48","B" +"SUBTRACT LOGICAL (64←32)","SLGFR R1,R2","47387@0|//@16|R1@24|R2@28|??@32","B91B" +"SUBTRACT LOGICAL HIGH (32)","SLHHHR R1,R2,R3","47563@0|R3@16|//@20|R1@24|R2@28|??@32","B9CB" +"SUBTRACT LOGICAL HIGH (32)","SLHHLR R1,R2,R3","47579@0|R3@16|//@20|R1@24|R2@28|??@32","B9DB" +"SUBTRACT LOGICAL IMMEDIATE (32)","SLFI R1,I2","194@0|R1@8|5@12|I2@16|??@48","C25" +"SUBTRACT LOGICAL IMMEDIATE (64→32)","SLGFI R1,I2","194@0|R1@8|4@12|I2@16|??@48","C24" +"SUBTRACT LOGICAL WITH BORROW (32)","SLB R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|153@40|??@48","B" +"SUBTRACT LOGICAL WITH BORROW (32)","SLBR R1,R2","47513@0|//@16|R1@24|R2@28|??@32","B999" +"SUBTRACT LOGICAL WITH BORROW (64)","SLBG R1,D2(X2,B2)","227@0|R1@8|X2@12|B2@16|D2@20|137@40|??@48","B" +"SUBTRACT LOGICAL WITH BORROW (64)","SLBGR R1,R2","47497@0|//@16|R1@24|R2@28|??@32","B989" +"SUBTRACT NORMALIZED (extended HFP)","SXR R1,R2","55@0|R1@8|R2@12|??@16","SP Da" +"SUBTRACT NORMALIZED (long HFP)","SD R1,D2(X2,B2)","107@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"SUBTRACT NORMALIZED (long HFP)","SDR R1,R2","43@0|R1@8|R2@12|??@16","Da" +"SUBTRACT NORMALIZED (short HFP)","SE R1,D2(X2,B2)","123@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"SUBTRACT NORMALIZED (short HFP)","SER R1,R2","59@0|R1@8|R2@12|??@16","Da" +"SUBTRACT UNNORMALIZED (long HFP)","SW R1,D2(X2,B2)","111@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"SUBTRACT UNNORMALIZED (long HFP)","SWR R1,R2","47@0|R1@8|R2@12|??@16","Da" +"SUBTRACT UNNORMALIZED (short HFP)","SU R1,D2(X2,B2)","127@0|R1@8|X2@12|B2@16|D2@20|??@32","Da" +"SUBTRACT UNNORMALIZED (short HFP)","SUR R1,R2","63@0|R1@8|R2@12|??@16","Da" +"SUPERVISOR CALL","SVC I","10@0|I@8|??@16","0A" +"TEST ACCESS","TAR R1,R2","45644@0|//@16|R1@24|R2@28|??@32","U" +"TEST ADDRESSING MODE","TAM","267@0|??@16","010B" +"TEST AND SET","TS D1(B1)","147@0|I2@8|B1@16|D1@20|??@32","ST" +"TEST BLOCK","TB R1,R2","45612@0|//@16|R1@24|R2@28|??@32","II" +"TEST DATA CLASS (extended BFP)","TCXB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|18@40|??@48","SP Db" +"TEST DATA CLASS (extended DFP)","TDCXT R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|88@40|??@48","SP Dt" +"TEST DATA CLASS (long BFP)","TCDB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|17@40|??@48","Db" +"TEST DATA CLASS (long DFP)","TDCDT R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|84@40|??@48","Dt" +"TEST DATA CLASS (short BFP)","TCEB R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|16@40|??@48","Db" +"TEST DATA CLASS (short DFP)","TDCET R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|80@40|??@48","Dt" +"TEST DATA GROUP (extended DFP)","TDGXT R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|89@40|??@48","SP Dt" +"TEST DATA GROUP (long DFP)","TDGDT R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|85@40|??@48","Dt" +"TEST DATA GROUP (short DFP)","TDGET R1,D2(X2,B2)","237@0|R1@8|X2@12|B2@16|D2@20|//@32|81@40|??@48","Dt" +"TEST DECIMAL","TP D1(L1,B1)","235@0|L1@8|//@12|B1@16|D1@20|//@32|192@40|??@48","B" +"TEST PENDING EXTERNAL INTERRUPTION","TPEI R1,R2","47521@0|//@16|R1@24|R2@28|??@32","B9A1" +"TEST PENDING INTERRUPTION","TPI D2(B2)","45622@0|B2@16|D2@20|??@32","ST" +"TEST PROTECTION","TPROT D1(B1),D2(B2)","58625@0|B1@16|D1@20|B2@32|D2@36|??@48","SO" +"TEST SUBCHANNEL","TSCH D2(B2)","45621@0|B2@16|D2@20|??@32","SP OP" +"TEST UNDER MASK","TM D1(B1),I2","145@0|I2@8|B1@16|D1@20|??@32","B" +"TEST UNDER MASK","TMY D1(B1),I2","235@0|I2@8|B1@16|D1@20|81@40|??@48","B" +"TEST UNDER MASK (high high)","TMHH R1,I2","167@0|R1@8|2@12|I2@16|??@32","A72" +"TEST UNDER MASK (high low)","TMHL R1,I2","167@0|R1@8|3@12|I2@16|??@32","A73" +"TEST UNDER MASK (low high)","TMLH R1,I2","167@0|R1@8|0@12|I2@16|??@32","A70" +"TEST UNDER MASK (low low)","TMLL R1,I2","167@0|R1@8|1@12|I2@16|??@32","A71" +"TEST UNDER MASK HIGH","TMH R1,I2","167@0|R1@8|0@12|I2@16|??@32","A70" +"TEST UNDER MASK LOW","TML R1,I2","167@0|R1@8|1@12|I2@16|??@32","A71" +"TRACE (32)","TRACE R1,R3,D2(B2)","153@0|R1@8|R3@12|B2@16|D2@20|??@32","SP" +"TRACE (64)","TRACG R1,R3,D2(B2)","235@0|R1@8|R3@12|B2@16|D2@20|15@40|??@48","SP" +"TRANSACTION ABORT","TABORT D2(B2)","45820@0|B2@16|D2@20|??@32","SP SO" +"TRANSACTION BEGIN (constrained)","TBEGINC D1(B1),I2","58721@0|B1@16|D1@20|I2@32|??@48","SP SO" +"TRANSACTION BEGIN (nonconstrained)","TBEGIN D1(B1),I2","58720@0|B1@16|D1@20|I2@32|??@48","SP SO" +"TRANSACTION END","TEND","45816@0|//@16|??@32","SO" +"TRANSLATE","TR D1(L1,B1),D2(B2)","220@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"TRANSLATE AND TEST","TRT D1(L1,B1),D2(B2)","221@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","B" +"TRANSLATE AND TEST EXTENDED","TRTE R1,R2,M3","47551@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"TRANSLATE AND TEST REVERSE","TRTR D1(L1,B1),D2(B2)","208@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","B" +"TRANSLATE AND TEST REVERSE EXTENDED","TRTRE R1,R2,M3","47549@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"TRANSLATE EXTENDED","TRE R1,R2","45733@0|//@16|R1@24|R2@28|??@32","SP IC" +"TRANSLATE ONE TO ONE","TROO R1,R2,M3","47507@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"TRANSLATE ONE TO TWO","TROT R1,R2,M3","47506@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"TRANSLATE TWO TO ONE","TRTO R1,R2,M3","47505@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"TRANSLATE TWO TO TWO","TRTT R1,R2,M3","47504@0|M3@16|//@20|R1@24|R2@28|??@32","SP IC" +"TRAP","TRAP2","511@0|??@16","SO" +"TRAP","TRAP4 D2(B2)","45823@0|B2@16|D2@20|??@32","SO" +"UNPACK","UNPK D1(L1,B1),D2(L2,B2)","243@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","ST" +"UNPACK ASCII","UNPKA D1(L1,B1),D2(B2)","234@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","SP" +"UNPACK UNICODE","UNPKU D1(L1,B1),D2(B2)","226@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48","SP" +"UPDATE TREE","UPT","258@0|??@16","SP II" +"VECTOR ADD","VA V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|243@40|??@48","SP Dv" +"VECTOR ADD COMPUTE CARRY","VACC V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|241@40|??@48","SP Dv" +"VECTOR ADD DECIMAL","VAP V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|113@40|??@48","SP Dv" +"VECTOR ADD WITH CARRY","VAC V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|187@40|??@48","SP Dv" +"VECTOR ADD WITH CARRY COMPUTE CARRY","VACCC V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|185@40|??@48","SP Dv" +"VECTOR AND","VN V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|104@40|??@48","Dv" +"VECTOR AND WITH COMPLEMENT","VNC V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|105@40|??@48","Dv" +"VECTOR AVERAGE","VAVG V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|242@40|??@48","SP Dv" +"VECTOR AVERAGE LOGICAL","VAVGL V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|240@40|??@48","SP Dv" +"VECTOR BIT PERMUTE","VBPERM V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|133@40|??@48","Dv" +"VECTOR CHECKSUM","VCKSM V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|102@40|??@48","Dv" +"VECTOR COMPARE DECIMAL","VCP V1,V2,M3","230@0|//@8|V1@12|V2@16|//@20|M3@24|//@28|RXB@36|119@40|??@48","Dv" +"VECTOR COMPARE EQUAL","VCEQ V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|248@40|??@48","SP Dv" +"VECTOR COMPARE HIGH","VCH V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|251@40|??@48","SP Dv" +"VECTOR COMPARE HIGH LOGICAL","VCHL V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|249@40|??@48","SP Dv" +"VECTOR CONVERT HFP TO SCALED DECIMAL","VCSPH V1,V2,V3,M4","230@0|V1@8|V2@12|V3@16|//@20|M4@24|//@28|RXB@36|125@40|??@48","Dv" +"VECTOR CONVERT TO BINARY","VCVB R1,V2,M3,M4","230@0|R1@8|V2@12|//@16|M3@24|M4@28|//@32|RXB@36|80@40|??@48","Dv" +"VECTOR CONVERT TO BINARY","VCVBG R1,V2,M3,M4","230@0|R1@8|V2@12|//@16|M3@24|M4@28|//@32|RXB@36|82@40|??@48","Dv" +"VECTOR CONVERT TO DECIMAL","VCVD V1,R2,I3,M4","230@0|V1@8|R2@12|//@16|M4@24|I3@28|RXB@36|88@40|??@48","SP Dv" +"VECTOR CONVERT TO DECIMAL","VCVDG V1,R2,I3,M4","230@0|V1@8|R2@12|//@16|M4@24|I3@28|RXB@36|90@40|??@48","SP Dv" +"VECTOR COUNT LEADING ZERO DIGITS","VCLZDP V1,V2,M3","230@0|V1@8|V2@12|//@16|M3@24|//@28|RXB@36|81@40|??@48","Dv" +"VECTOR COUNT LEADING ZEROS","VCLZ V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|83@40|??@48","SP Dv" +"VECTOR COUNT TRAILING ZEROS","VCTZ V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|82@40|??@48","SP Dv" +"VECTOR DIVIDE DECIMAL","VDP V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|122@40|??@48","SP Dv" +"VECTOR ELEMENT COMPARE","VEC V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|219@40|??@48","SP Dv" +"VECTOR ELEMENT COMPARE LOGICAL","VECL V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|217@40|??@48","SP Dv" +"VECTORELEMENTROTATEANDINSERTUNDER MASK","VERIM V1,V2,V3,I4,M5","231@0|V1@8|V2@12|V3@16|//@20|I4@24|M5@32|RXB@36|114@40|??@48","SP Dv" +"VECTOR ELEMENT ROTATE LEFT LOGICAL","VERLL V1,V3,D2(B2),M4","231@0|V1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|51@40|??@48","SP Dv" +"VECTOR ELEMENT ROTATE LEFT LOGICAL","VERLLV V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|115@40|??@48","SP Dv" +"VECTOR ELEMENT SHIFT LEFT","VESLV V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|112@40|??@48","SP Dv" +"VECTOR ELEMENT SHIFT LEFT","VESL V1,V3,D2(B2),M4","231@0|V1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|48@40|??@48","SP Dv" +"VECTOR ELEMENT SHIFT RIGHT ARITHMETIC","VESRA V1,V3,D2(B2),M4","231@0|V1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|58@40|??@48","SP Dv" +"VECTOR ELEMENT SHIFT RIGHT ARITHMETIC","VESRAV V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|122@40|??@48","SP Dv" +"VECTOR ELEMENT SHIFT RIGHT LOGICAL","VESRL V1,V3,D2(B2),M4","231@0|V1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|56@40|??@48","SP Dv" +"VECTOR ELEMENT SHIFT RIGHT LOGICAL","VESRLV V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|120@40|??@48","SP Dv" +"VECTOR EXCLUSIVE OR","VX V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|109@40|??@48","Dv" +"VECTOR FIND ANY ELEMENT EQUAL","VFAE V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|130@40|??@48","SP Dv" +"VECTOR FIND ELEMENT EQUAL","VFEE V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|128@40|??@48","SP Dv" +"VECTOR FIND ELEMENT NOT EQUAL","VFENE V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|129@40|??@48","SP Dv" +"VECTOR FP ADD","VFA V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@28|M4@32|RXB@36|227@40|??@48","SP Dv" +"VECTOR FP COMPARE AND SIGNAL SCALAR","WFK V1,V2,M3,M4","231@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|202@40|??@48","SP Dv" +"VECTOR FP COMPARE EQUAL","VFCE V1,V2,V3,M4,M5,M6","231@0|V1@8|V2@12|V3@16|//@20|M6@24|M5@28|M4@32|RXB@36|232@40|??@48","SP Dv" +"VECTOR FP COMPARE HIGH","VFCH V1,V2,V3,M4,M5,M6","231@0|V1@8|V2@12|V3@16|//@20|M6@24|M5@28|M4@32|RXB@36|235@40|??@48","SP Dv" +"VECTOR FP COMPARE HIGH OR EQUAL","VFCHE V1,V2,V3,M4,M5,M6","231@0|V1@8|V2@12|V3@16|//@20|M6@24|M5@28|M4@32|RXB@36|234@40|??@48","SP Dv" +"VECTOR FP COMPARE SCALAR","WFC V1,V2,M3,M4","231@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|203@40|??@48","SP Dv" +"VECTOR FP CONVERT AND LENGTHEN FROM NNP HIGH","VCLFNH V1,V2,M3,M4","230@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|86@40|??@48","Dv" +"VECTOR FP CONVERT AND LENGTHEN FROM NNP LOW","VCLFNL V1,V2,M3,M4","230@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|94@40|??@48","Dv" +"VECTOR FP CONVERT AND ROUND TO NNP","VCRNF V1,V2,V3,M4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@28|M4@32|RXB@36|117@40|??@48","Dv" +"VECTOR FP CONVERT FROM FIXED","VCFPS V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|195@40|??@48","SP Dv" +"VECTOR FP CONVERT FROM FIXED 64-BIT","VCDG V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|195@40|??@48","SP Dv" +"VECTOR FP CONVERT FROM LOGICAL","VCFPL V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|193@40|??@48","SP Dv" +"VECTOR FP CONVERT FROM LOGICAL 64-BIT","VCDLG V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|193@40|??@48","SP Dv" +"VECTOR FP CONVERT FROM NNP","VCFN V1,V2,M3,M4","230@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|93@40|??@48","Dv" +"VECTOR FP CONVERT TO FIXED","VCSFP V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|194@40|??@48","SP Dv" +"VECTOR FP CONVERT TO FIXED 64-BIT","VCGD V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|194@40|??@48","SP Dv" +"VECTOR FP CONVERT TO LOGICAL","VCLFP V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|192@40|??@48","SP Dv" +"VECTOR FP CONVERT TO LOGICAL 64-BIT","VCLGD V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|192@40|??@48","SP Dv" +"VECTOR FP CONVERT TO NNP","VCNF V1,V2,M3,M4","230@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|85@40|??@48","Dv" +"VECTOR FP DIVIDE","VFD V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@28|M4@32|RXB@36|229@40|??@48","SP Dv" +"VECTOR FP LOAD LENGTHENED","VFLL V1,V2,M3,M4","231@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|196@40|??@48","SP Dv" +"VECTOR FP LOAD ROUNDED","VFLR V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|197@40|??@48","SP Dv" +"VECTOR FP MAXIMUM","VFMAX V1,V2,V3,M4,M5,M6","231@0|V1@8|V2@12|V3@16|//@20|M6@24|M5@28|M4@32|RXB@36|239@40|??@48","SP Dv" +"VECTOR FP MINIMUM","VFMIN V1,V2,V3,M4,M5,M6","231@0|V1@8|V2@12|V3@16|//@20|M6@24|M5@28|M4@32|RXB@36|238@40|??@48","SP Dv" +"VECTOR FP MULTIPLY","VFM V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@28|M4@32|RXB@36|231@40|??@48","SP Dv" +"VECTOR FP MULTIPLY AND ADD","VFMA V1,V2,V3,V4,M5,M6","231@0|V1@8|V2@12|V3@16|M6@20|//@24|M5@28|V4@32|RXB@36|143@40|??@48","SP Dv" +"VECTOR FP MULTIPLY AND SUBTRACT","VFMS V1,V2,V3,V4,M5,M6","231@0|V1@8|V2@12|V3@16|M6@20|//@24|M5@28|V4@32|RXB@36|142@40|??@48","SP Dv" +"VECTOR FP NEGATIVE MULTIPLY AND ADD","VFNMA V1,V2,V3,V4,M5,M6","231@0|V1@8|V2@12|V3@16|M6@20|//@24|M5@28|V4@32|RXB@36|159@40|??@48","SP Dv" +"VECTOR FP NEGATIVE MULTIPLY AND SUBTRACT","VFNMS V1,V2,V3,V4,M5,M6","231@0|V1@8|V2@12|V3@16|M6@20|//@24|M5@28|V4@32|RXB@36|158@40|??@48","SP Dv" +"VECTOR FP PERFORM SIGN OPERATION","VFPSO V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|204@40|??@48","SP Dv" +"VECTOR FP SQUARE ROOT","VFSQ V1,V2,M3,M4","231@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|206@40|??@48","SP Dv" +"VECTOR FP SUBTRACT","VFS V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@28|M4@32|RXB@36|226@40|??@48","SP Dv" +"VECTOR FP TEST DATA CLASS IMMEDIATE","VFTCI V1,V2,I3,M4,M5","231@0|V1@8|V2@12|I3@16|M5@28|M4@32|RXB@36|74@40|??@48","SP Dv" +"VECTOR GALOIS FIELD MULTIPLY SUM","VGFM V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|180@40|??@48","SP Dv" +"VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE","VGFMA V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|188@40|??@48","SP Dv" +"VECTOR GATHER ELEMENT (32)","VGEF V1,D2(V2,B2),M3","231@0|V1@8|V2@12|B2@16|D2@20|M3@32|RXB@36|19@40|??@48","SP Dv" +"VECTOR GATHER ELEMENT (64)","VGEG V1,D2(V2,B2),M3","231@0|V1@8|V2@12|B2@16|D2@20|M3@32|RXB@36|18@40|??@48","SP Dv" +"VECTOR GENERATE BYTE MASK","VGBM V1,I2","231@0|V1@8|//@12|I2@16|//@32|RXB@36|68@40|??@48","Dv" +"VECTOR GENERATE MASK","VGM V1,I2,I3,M4","231@0|V1@8|//@12|I2@16|I3@24|M4@32|RXB@36|70@40|??@48","SP Dv" +"VECTOR ISOLATE STRING","VISTR V1,V2,M3,M5","231@0|V1@8|V2@12|//@16|M5@24|//@28|M3@32|RXB@36|92@40|??@48","SP Dv" +"VECTOR LOAD","VL V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|6@40|??@48","Dv" +"VECTOR LOAD","VLR V1,V2","231@0|V1@8|V2@12|//@16|RXB@36|86@40|??@48","Dv" +"VECTOR LOAD AND REPLICATE","VLREP V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|5@40|??@48","SP Dv" +"VECTOR LOAD BYTE REVERSED ELEMENT (16)","VLEBRH V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|1@40|??@48","SP Dv" +"VECTOR LOAD BYTE REVERSED ELEMENT (32)","VLEBRF V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|3@40|??@48","SP Dv" +"VECTOR LOAD BYTE REVERSED ELEMENT (64)","VLEBRG V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|2@40|??@48","SP Dv" +"VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE","VLBRREP V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|5@40|??@48","SP Dv" +"VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO","VLLEBRZ V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|4@40|??@48","SP Dv" +"VECTOR LOAD BYTE REVERSED ELEMENTS","VLBR V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|6@40|??@48","SP Dv" +"VECTOR LOAD COMPLEMENT","VLC V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|222@40|??@48","SP Dv" +"VECTOR LOAD ELEMENT (16)","VLEH V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|1@40|??@48","SP Dv" +"VECTOR LOAD ELEMENT (32)","VLEF V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|3@40|??@48","SP Dv" +"VECTOR LOAD ELEMENT (64)","VLEG V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|2@40|??@48","SP Dv" +"VECTOR LOAD ELEMENT (8)","VLEB V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|0@40|??@48","SP Dv" +"VECTOR LOAD ELEMENT IMMEDIATE (16)","VLEIH V1,I2,M3","231@0|V1@8|//@12|I2@16|M3@32|RXB@36|65@40|??@48","SP Dv" +"VECTOR LOAD ELEMENT IMMEDIATE (32)","VLEIF V1,I2,M3","231@0|V1@8|//@12|I2@16|M3@32|RXB@36|67@40|??@48","SP Dv" +"VECTOR LOAD ELEMENT IMMEDIATE (64)","VLEIG V1,I2,M3","231@0|V1@8|//@12|I2@16|M3@32|RXB@36|66@40|??@48","SP Dv" +"VECTOR LOAD ELEMENT IMMEDIATE (8)","VLEIB V1,I2,M3","231@0|V1@8|//@12|I2@16|M3@32|RXB@36|64@40|??@48","SP Dv" +"VECTOR LOAD ELEMENTS REVERSED","VLER V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|7@40|??@48","SP Dv" +"VECTOR LOAD FP INTEGER","VFI V1,V2,M3,M4,M5","231@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|199@40|??@48","SP Dv" +"VECTOR LOAD GR FROM VR ELEMENT","VLGV R1,V3,D2(B2),M4","231@0|R1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|33@40|??@48","SP Dv" +"VECTOR LOAD IMMEDIATE DECIMAL","VLIP V1,I2,I3","230@0|V1@8|//@12|I2@16|I3@32|RXB@36|73@40|??@48","Dv" +"VECTOR LOAD LOGICAL ELEMENT AND ZERO","VLLEZ V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|4@40|??@48","SP Dv" +"VECTOR LOAD MULTIPLE","VLM V1,V3,D2(B2),M4","231@0|V1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|54@40|??@48","SP Dv" +"VECTOR LOAD POSITIVE","VLP V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|223@40|??@48","SP Dv" +"VECTOR LOAD RIGHTMOST WITH LENGTH","VLRL V1,D2(B2),I3","230@0|I3@8|B2@16|D2@20|V1@32|RXB@36|53@40|??@48","SP Dv" +"VECTOR LOAD RIGHTMOST WITH LENGTH","VLRLR V1,R3,D2(B2)","230@0|//@8|R3@12|B2@16|D2@20|V1@32|RXB@36|55@40|??@48","Dv" +"VECTOR LOAD TO BLOCK BOUNDARY","VLBB V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|7@40|??@48","SP Dv" +"VECTOR LOAD VR ELEMENT FROM GR","VLVG V1,R3,D2(B2),M4","231@0|V1@8|R3@12|B2@16|D2@20|M4@32|RXB@36|34@40|??@48","SP Dv" +"VECTOR LOAD VR FROM GRS DISJOINT","VLVGP V1,R2,R3","231@0|V1@8|R2@12|R3@16|//@20|RXB@36|98@40|??@48","Dv" +"VECTOR LOAD WITH LENGTH","VLL V1,R3,D2(B2)","231@0|V1@8|R3@12|B2@16|D2@20|//@32|RXB@36|55@40|??@48","Dv" +"VECTOR MAXIMUM","VMX V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|255@40|??@48","SP Dv" +"VECTOR MAXIMUM LOGICAL","VMXL V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|253@40|??@48","SP Dv" +"VECTOR MERGE HIGH","VMRH V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|97@40|??@48","SP Dv" +"VECTOR MERGE LOW","VMRL V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|96@40|??@48","SP Dv" +"VECTOR MINIMUM","VMN V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|254@40|??@48","SP Dv" +"VECTOR MINIMUM LOGICAL","VMNL V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|252@40|??@48","SP Dv" +"VECTOR MULTIPLY AND ADD EVEN","VMAE V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|174@40|??@48","SP Dv" +"VECTOR MULTIPLY AND ADD HIGH","VMAH V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|171@40|??@48","SP Dv" +"VECTOR MULTIPLY AND ADD LOGICAL EVEN","VMALE V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|172@40|??@48","SP Dv" +"VECTOR MULTIPLY AND ADD LOGICAL HIGH","VMALH V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|169@40|??@48","SP Dv" +"VECTOR MULTIPLY AND ADD LOGICAL ODD","VMALO V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|173@40|??@48","SP Dv" +"VECTOR MULTIPLY AND ADD LOW","VMAL V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|170@40|??@48","SP Dv" +"VECTOR MULTIPLY AND ADD ODD","VMAO V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|175@40|??@48","SP Dv" +"VECTOR MULTIPLY AND SHIFT DECIMAL","VMSP V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|121@40|??@48","SP Dv" +"VECTOR MULTIPLY DECIMAL","VMP V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|120@40|??@48","SP Dv" +"VECTOR MULTIPLY EVEN","VME V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|166@40|??@48","SP Dv" +"VECTOR MULTIPLY HIGH","VMH V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|163@40|??@48","SP Dv" +"VECTOR MULTIPLY LOGICAL EVEN","VMLE V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|164@40|??@48","SP Dv" +"VECTOR MULTIPLY LOGICAL HIGH","VMLH V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|161@40|??@48","SP Dv" +"VECTOR MULTIPLY LOGICAL ODD","VMLO V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|165@40|??@48","SP Dv" +"VECTOR MULTIPLY LOW","VML V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|162@40|??@48","SP Dv" +"VECTOR MULTIPLY ODD","VMO V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|167@40|??@48","SP Dv" +"VECTOR MULTIPLY SUM LOGICAL","VMSL V1,V2,V3,V4,M5,M6","231@0|V1@8|V2@12|V3@16|M5@20|M6@24|//@28|V4@32|RXB@36|184@40|??@48","SP Dv" +"VECTOR NAND","VNN V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|110@40|??@48","DV" +"VECTOR NOR","VNO V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|107@40|??@48","Dv" +"VECTOR NOT EXCLUSIVE OR","VNX V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|108@40|??@48","Dv" +"VECTOR OR","VO V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|106@40|??@48","Dv" +"VECTOR OR WITH COMPLEMENT","VOC V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|111@40|??@48","Dv" +"VECTOR PACK","VPK V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|148@40|??@48","SP Dv" +"VECTOR PACK LOGICAL SATURATE","VPKLS V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|149@40|??@48","SP Dv" +"VECTOR PACK SATURATE","VPKS V1,V2,V3,M4,M5","231@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|151@40|??@48","SP Dv" +"VECTOR PACK ZONED","VPKZ V1,D2(B2),I3","230@0|I3@8|B2@16|D2@20|V1@32|RXB@36|52@40|??@48","SP Dv" +"VECTOR PACK ZONED REGISTER","VPKZR V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|112@40|??@48","SP Dv" +"VECTOR PERFORM SIGN OPERATION DECIMAL","VPSOP V1,V2,I3,I4,M5","230@0|V1@8|V2@12|I4@16|M5@24|I3@28|RXB@36|91@40|??@48","SP Dv" +"VECTOR PERMUTE","VPERM V1,V2,V3,V4","231@0|V1@8|V2@12|V3@16|//@20|V4@32|RXB@36|140@40|??@48","Dv" +"VECTOR PERMUTE DOUBLEWORD IMMEDIATE","VPDI V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|132@40|??@48","Dv" +"VECTOR POPULATION COUNT","VPOPCT V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|80@40|??@48","SP Dv" +"VECTOR REMAINDER DECIMAL","VRP V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|123@40|??@48","SP Dv" +"VECTOR REPLICATE","VREP V1,V3,I2,M4","231@0|V1@8|V3@12|I2@16|M4@32|RXB@36|77@40|??@48","SP Dv" +"VECTOR REPLICATE IMMEDIATE","VREPI V1,I2,M3","231@0|V1@8|//@12|I2@16|M3@32|RXB@36|69@40|??@48","SP Dv" +"VECTOR SCATTER ELEMENT (32)","VSCEF V1,D2(V2,B2),M3","231@0|V1@8|V2@12|B2@16|D2@20|M3@32|RXB@36|27@40|??@48","SP Dv" +"VECTOR SCATTER ELEMENT (64)","VSCEG V1,D2(V2,B2),M3","231@0|V1@8|V2@12|B2@16|D2@20|M3@32|RXB@36|26@40|??@48","SP Dv" +"VECTOR SELECT","VSEL V1,V2,V3,V4","231@0|V1@8|V2@12|V3@16|//@20|V4@32|RXB@36|141@40|??@48","Dv" +"VECTOR SHIFT AND DIVIDE DECIMAL","VSDP V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|126@40|??@48","SP Dv" +"VECTOR SHIFT AND ROUND DECIMAL","VSRP V1,V2,I3,I4,M5","230@0|V1@8|V2@12|I4@16|M5@24|I3@28|RXB@36|89@40|??@48","SP Dv" +"VECTOR SHIFT AND ROUND DECIMAL REGISTER","VSRPR V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|114@40|??@48","SP Dv" +"VECTOR SHIFT LEFT","VSL V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|116@40|??@48","Dv" +"VECTOR SHIFT LEFT BY BYTE","VSLB V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|117@40|??@48","Dv" +"VECTOR SHIFT LEFT DOUBLE BY BIT","VSLD V1,V2,V3,I4","231@0|V1@8|V2@12|V3@16|//@20|I4@24|//@32|RXB@36|134@40|??@48","SP Dv" +"VECTOR SHIFT LEFT DOUBLE BY BYTE","VSLDB V1,V2,V3,I4","231@0|V1@8|V2@12|V3@16|//@20|I4@24|//@32|RXB@36|119@40|??@48","Dv" +"VECTOR SHIFT RIGHT ARITHMETIC","VSRA V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|126@40|??@48","Dv" +"VECTOR SHIFT RIGHT ARITHMETIC BY BYTE","VSRAB V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|127@40|??@48","Dv" +"VECTOR SHIFT RIGHT DOUBLE BY BIT","VSRD V1,V2,V3,I4","231@0|V1@8|V2@12|V3@16|//@20|I4@24|//@32|RXB@36|135@40|??@48","SP Dv" +"VECTOR SHIFT RIGHT LOGICAL","VSRL V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|124@40|??@48","Dv" +"VECTOR SHIFT RIGHT LOGICAL BY BYTE","VSRLB V1,V2,V3","231@0|V1@8|V2@12|V3@16|//@20|RXB@36|125@40|??@48","Dv" +"VECTOR SIGN EXTEND TO DOUBLEWORD","VSEG V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|95@40|??@48","SP Dv" +"VECTOR STORE","VST V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|14@40|??@48","Dv" +"VECTOR STORE BYTE REVERSED ELEMENT(16)","VSTEBRH V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|9@40|??@48","SP Dv" +"VECTOR STORE BYTE REVERSED ELEMENT(32)","VSTEBRF V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|11@40|??@48","SP Dv" +"VECTOR STORE BYTE REVERSED ELEMENT(64)","VSTEBRG V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|10@40|??@48","SP Dv" +"VECTOR STORE BYTE REVERSED ELEMENTS","VSTBR V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|14@40|??@48","SP Dv" +"VECTOR STORE ELEMENT (16)","VSTEH V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|9@40|??@48","SP Dv" +"VECTOR STORE ELEMENT (32)","VSTEF V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|11@40|??@48","SP Dv" +"VECTOR STORE ELEMENT (64)","VSTEG V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|10@40|??@48","SP Dv" +"VECTOR STORE ELEMENT (8)","VSTEB V1,D2(X2,B2),M3","231@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|8@40|??@48","SP Dv" +"VECTOR STORE ELEMENTS REVERSED","VSTER V1,D2(X2,B2),M3","230@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|15@40|??@48","SP Dv" +"VECTOR STORE MULTIPLE","VSTM V1,V3,D2(B2),M4","231@0|V1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|62@40|??@48","SP Dv" +"VECTOR STORE RIGHTMOST WITH LENGTH","VSTRL V1,D2(B2),I3","230@0|I3@8|B2@16|D2@20|V1@32|RXB@36|61@40|??@48","SP Dv" +"VECTOR STORE RIGHTMOST WITH LENGTH","VSTRLR V1,R3,D2(B2)","230@0|//@8|R3@12|B2@16|D2@20|V1@32|RXB@36|63@40|??@48","Dv" +"VECTOR STORE WITH LENGTH","VSTL V1,R3,D2(B2)","231@0|V1@8|R3@12|B2@16|D2@20|//@32|RXB@36|63@40|??@48","Dv" +"VECTOR STRING RANGE COMPARE","VSTRC V1,V2,V3,V4,M5,M6","231@0|V1@8|V2@12|V3@16|M5@20|M6@24|//@28|V4@32|RXB@36|138@40|??@48","SP Dv" +"VECTOR STRING SEARCH","VSTRS V1,V2,V3,V4,M5,M6","231@0|V1@8|V2@12|V3@16|M5@20|M6@24|//@28|V4@32|RXB@36|139@40|??@48","SP Dv" +"VECTOR SUBTRACT","VS V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|247@40|??@48","SP Dv" +"VECTOR SUBTRACT COMPUTE BORROW INDICATION","VSCBI V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|245@40|??@48","SP Dv" +"VECTOR SUBTRACT DECIMAL","VSP V1,V2,V3,I4,M5","230@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|115@40|??@48","SP Dv" +"VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION","VSBCBI V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|189@40|??@48","SP Dv" +"VECTOR SUBTRACT WITH BORROW INDICATION","VSBI V1,V2,V3,V4,M5","231@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|191@40|??@48","SP Dv" +"VECTOR SUM ACROSS DOUBLEWORD","VSUMG V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|101@40|??@48","SP Dv" +"VECTOR SUM ACROSS QUADWORD","VSUMQ V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|103@40|??@48","SP Dv" +"VECTOR SUM ACROSS WORD","VSUM V1,V2,V3,M4","231@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|100@40|??@48","SP Dv" +"VECTOR TEST DECIMAL","VTP V1","230@0|//@8|V1@12|//@16|RXB@36|95@40|??@48","Dv" +"VECTOR TEST UNDER MASK","VTM V1,V2","231@0|V1@8|V2@12|//@16|RXB@36|216@40|??@48","Dv" +"VECTOR UNPACK HIGH","VUPH V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|215@40|??@48","SP Dv" +"VECTOR UNPACK LOGICAL HIGH","VUPLH V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|213@40|??@48","SP Dv" +"VECTOR UNPACK LOGICAL LOW","VUPLL V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|212@40|??@48","SP Dv" +"VECTOR UNPACK LOW","VUPL V1,V2,M3","231@0|V1@8|V2@12|//@16|M3@32|RXB@36|214@40|??@48","SP Dv" +"VECTOR UNPACK ZONED","VUPKZ V1,D2(B2),I3","230@0|I3@8|B2@16|D2@20|V1@32|RXB@36|60@40|??@48","SP Dv" +"VECTOR UNPACK ZONED HIGH","VUPKZH V1,V2,M3","230@0|V1@8|V2@12|//@16|M3@24|//@28|RXB@36|84@40|??@48","Dv" +"VECTOR UNPACK ZONED LOW","VUPKZL V1,V2,M3","230@0|V1@8|V2@12|//@16|M3@24|//@28|RXB@36|92@40|??@48","Dv" +"ZERO AND ADD","ZAP D1(L1,B1),D2(L2,B2)","248@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48","Dg" diff --git a/s390x/s390xasm/Makefile b/s390x/s390xasm/Makefile new file mode 100644 index 00000000..6d02dac2 --- /dev/null +++ b/s390x/s390xasm/Makefile @@ -0,0 +1,2 @@ +tables.go: ../s390xmap/map.go ../s390x.csv + go run ../s390xmap/map.go -fmt=decoder ../s390x.csv >_tables.go && gofmt _tables.go >tables.go && rm _tables.go diff --git a/s390x/s390xasm/decode.go b/s390x/s390xasm/decode.go new file mode 100644 index 00000000..823fe591 --- /dev/null +++ b/s390x/s390xasm/decode.go @@ -0,0 +1,241 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package s390xasm + +import ( + "encoding/binary" + "fmt" +) + +// instFormat is a decoding rule for one specific instruction form. +// An instruction ins matches the rule if ins&Mask == Value. +// DontCare bits are mainly used for finding the same instruction +// name differing with the number of argument fields. +// The Args are stored in the same order as the instruction manual. +type instFormat struct { + Op Op + Mask uint64 + Value uint64 + DontCare uint64 + Args [8]*argField +} + +// argField indicate how to decode an argument to an instruction. +// First parse the value from the BitFields, shift it left by Shift +// bits to get the actual numerical value. +type argField struct { + Type ArgType + flags uint16 + BitField +} + +// Parse parses the Arg out from the given binary instruction i. +func (a argField) Parse(i uint64) Arg { + switch a.Type { + default: + return nil + case TypeUnknown: + return nil + case TypeReg: + return R0 + Reg(a.BitField.Parse(i)) + case TypeFPReg: + return F0 + Reg(a.BitField.Parse(i)) + case TypeCReg: + return C0 + Reg(a.BitField.Parse(i)) + case TypeACReg: + return A0 + Reg(a.BitField.Parse(i)) + case TypeBaseReg: + return B0 + Base(a.BitField.Parse(i)) + case TypeIndexReg: + return X0 + Index(a.BitField.Parse(i)) + case TypeDispUnsigned: + return Disp12(a.BitField.Parse(i)) + case TypeDispSigned20: + return Disp20(a.BitField.ParseSigned(i)) + case TypeVecReg: + m := i >> 24 // Handling RXB field(bits 36 to 39) + if ((m>>3)&0x1 == 1) && (a.BitField.Offs == 8) { + return V0 + VReg(a.BitField.Parse(i)) + VReg(16) + } else if ((m>>2)&0x1 == 1) && (a.BitField.Offs == 12) { + return V0 + VReg(a.BitField.Parse(i)) + VReg(16) + } else if ((m>>1)&0x1 == 1) && (a.BitField.Offs == 16) { + return V0 + VReg(a.BitField.Parse(i)) + VReg(16) + } else if ((m)&0x1 == 1) && (a.BitField.Offs == 32) { + return V0 + VReg(a.BitField.Parse(i)) + VReg(16) + } else { + return V0 + VReg(a.BitField.Parse(i)) + } + case TypeImmSigned8: + return Sign8(a.BitField.ParseSigned(i)) + case TypeImmSigned16: + return Sign16(a.BitField.ParseSigned(i)) + case TypeImmSigned32: + return Sign32(a.BitField.ParseSigned(i)) + case TypeImmUnsigned: + return Imm(a.BitField.Parse(i)) + case TypeRegImSigned12: + return RegIm12(a.BitField.ParseSigned(i)) + case TypeRegImSigned16: + return RegIm16(a.BitField.ParseSigned(i)) + case TypeRegImSigned24: + return RegIm24(a.BitField.ParseSigned(i)) + case TypeRegImSigned32: + return RegIm32(a.BitField.ParseSigned(i)) + case TypeMask: + return Mask(a.BitField.Parse(i)) + case TypeLen: + return Len(a.BitField.Parse(i)) + } +} + +type ArgType int8 + +const ( + TypeUnknown ArgType = iota + TypeReg // integer register + TypeFPReg // floating point register + TypeACReg // access register + TypeCReg // control register + TypeVecReg // vector register + TypeImmUnsigned // unsigned immediate/flag/mask, this is the catch-all type + TypeImmSigned8 // Signed 8-bit Immdediate + TypeImmSigned16 // Signed 16-bit Immdediate + TypeImmSigned32 // Signed 32-bit Immdediate + TypeBaseReg // Base Register for accessing memory + TypeIndexReg // Index Register + TypeDispUnsigned // Displacement 12-bit unsigned for memory address + TypeDispSigned20 // Displacement 20-bit signed for memory address + TypeRegImSigned12 // RegisterImmediate 12-bit signed data + TypeRegImSigned16 // RegisterImmediate 16-bit signed data + TypeRegImSigned24 // RegisterImmediate 24-bit signed data + TypeRegImSigned32 // RegisterImmediate 32-bit signed data + TypeMask // 4-bit Mask + TypeLen // Length of Memory Operand + TypeLast +) + +func (t ArgType) String() string { + switch t { + default: + return fmt.Sprintf("ArgType(%d)", int(t)) + case TypeUnknown: + return "Unknown" + case TypeReg: + return "Reg" + case TypeFPReg: + return "FPReg" + case TypeACReg: + return "ACReg" + case TypeCReg: + return "CReg" + case TypeDispUnsigned: + return "DispUnsigned" + case TypeDispSigned20: + return "DispSigned20" + case TypeBaseReg: + return "BaseReg" + case TypeIndexReg: + return "IndexReg" + case TypeVecReg: + return "VecReg" + case TypeImmSigned8: + return "ImmSigned8" + case TypeImmSigned16: + return "ImmSigned16" + case TypeImmSigned32: + return "ImmSigned32" + case TypeImmUnsigned: + return "ImmUnsigned" + case TypeRegImSigned12: + return "RegImSigned12" + case TypeRegImSigned16: + return "RegImSigned16" + case TypeRegImSigned24: + return "RegImSigned24" + case TypeRegImSigned32: + return "RegImSigned32" + case TypeMask: + return "Mask" + case TypeLen: + return "Len" + } +} + +func (t ArgType) GoString() string { + s := t.String() + if t > 0 && t < TypeLast { + return "Type" + s + } + return s +} + +var ( + // Errors + errShort = fmt.Errorf("truncated instruction") + errUnknown = fmt.Errorf("unknown instruction") +) + +var decoderCover []bool + +// Decode decodes the leading bytes in src as a single instruction using +// byte order ord. +func Decode(src []byte) (inst Inst, err error) { + if len(src) < 2 { + return inst, errShort + } + if decoderCover == nil { + decoderCover = make([]bool, len(instFormats)) + } + bit_check := binary.BigEndian.Uint16(src[:2]) + bit_check = bit_check >> 14 + l := int(0) + if (bit_check & 0x03) == 0 { + l = 2 + } else if bit_check&0x03 == 3 { + l = 6 + } else if (bit_check&0x01 == 1) || (bit_check&0x02 == 2) { + l = 4 + } + inst.Len = l + ui_extn := uint64(0) + switch l { + case 2: + ui_extn = uint64(binary.BigEndian.Uint16(src[:inst.Len])) + inst.Enc = ui_extn + ui_extn = ui_extn << 48 + case 4: + ui_extn = uint64(binary.BigEndian.Uint32(src[:inst.Len])) + inst.Enc = ui_extn + ui_extn = ui_extn << 32 + case 6: + u1 := binary.BigEndian.Uint32(src[:(inst.Len - 2)]) + u2 := binary.BigEndian.Uint16(src[(inst.Len - 2):inst.Len]) + ui_extn = uint64(u1)<<16 | uint64(u2) + ui_extn = ui_extn << 16 + inst.Enc = ui_extn + default: + return inst, errShort + } + for _, iform := range instFormats { + if ui_extn&iform.Mask != iform.Value { + continue + } + if (iform.DontCare & ^(ui_extn)) != iform.DontCare { + continue + } + for j, argfield := range iform.Args { + if argfield == nil { + break + } + inst.Args[j] = argfield.Parse(ui_extn) + } + inst.Op = iform.Op + break + } + if inst.Op == 0 && inst.Enc != 0 { + return inst, errUnknown + } + return inst, nil +} diff --git a/s390x/s390xasm/decode_test.go b/s390x/s390xasm/decode_test.go new file mode 100644 index 00000000..047ebeed --- /dev/null +++ b/s390x/s390xasm/decode_test.go @@ -0,0 +1,81 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package s390xasm + +import ( + "encoding/hex" + "io/ioutil" + "path" + "strings" + "testing" +) + +func TestDecode(t *testing.T) { + files, err := ioutil.ReadDir("testdata") + if err != nil { + t.Fatal(err) + } + for _, f := range files { + if !strings.HasPrefix(f.Name(), "decode") { + continue + } + filename := path.Join("testdata", f.Name()) + data, err := ioutil.ReadFile(filename) + if err != nil { + t.Fatal(err) + } + decode(data, t, filename) + } +} + +func decode(data []byte, t *testing.T, filename string) { + all := string(data) + // Simulate PC based on number of instructions found in the test file. + pc := uint64(0) + for strings.Contains(all, "\t\t") { + all = strings.Replace(all, "\t\t", "\t", -1) + } + for _, line := range strings.Split(all, "\n") { + line = strings.TrimSpace(line) + if line == "" || strings.HasPrefix(line, "#") { + continue + } + f := strings.SplitN(line, "\t", 3) + i := strings.Index(f[0], "|") + if i < 0 { + t.Errorf("%s: parsing %q: missing | separator", filename, f[0]) + continue + } + if i%2 != 0 { + t.Errorf("%s: parsing %q: misaligned | separator", filename, f[0]) + } + size := i / 2 + code, err := hex.DecodeString(f[0][:i] + f[0][i+1:]) + if err != nil { + t.Errorf("%s: parsing %q: %v", filename, f[0], err) + continue + } + syntax, asm := f[1], f[2] + inst, err := Decode(code) + var out string + if err != nil { + out = "error: " + err.Error() + } else { + switch syntax { + case "gnu": + out = GNUSyntax(inst, pc) + case "plan9": + out = GoSyntax(inst, pc, nil) + default: + t.Errorf("unknown syntax %q", syntax) + continue + } + } + pc += uint64(size) + if out != asm || inst.Len != size { + t.Errorf("%s: Decode(%s) [%s] = %s want %s", filename, f[0], syntax, out, asm) + } + } +} diff --git a/s390x/s390xasm/field.go b/s390x/s390xasm/field.go new file mode 100644 index 00000000..29adc821 --- /dev/null +++ b/s390x/s390xasm/field.go @@ -0,0 +1,47 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package s390xasm + +import ( + "fmt" +) + +// A BitField is a bit-field in a 64-bit double word. +// Bits are counted from 0 from the MSB to 63 as the LSB. +type BitField struct { + Offs uint8 // the offset of the left-most bit. + Bits uint8 // length in bits. +} + +func (b BitField) String() string { + if b.Bits > 1 { + return fmt.Sprintf("[%d:%d]", b.Offs, int(b.Offs+b.Bits)-1) + } else if b.Bits == 1 { + return fmt.Sprintf("[%d]", b.Offs) + } else { + return fmt.Sprintf("[%d, len=0]", b.Offs) + } +} + +// Parse extracts the bitfield b from i, and return it as an unsigned integer. +// Parse will panic if b is invalid. +func (b BitField) Parse(i uint64) uint64 { + if b.Bits > 64 || b.Bits == 0 || b.Offs > 63 || b.Offs+b.Bits > 64 { + panic(fmt.Sprintf("invalid bitfiled %v", b)) + } + if b.Bits == 20 { + return ((((i >> (64 - b.Offs - b.Bits)) & ((1 << 8) - 1)) << 12) | ((i >> (64 - b.Offs - b.Bits + 8)) & 0xFFF)) + + } else { + return (i >> (64 - b.Offs - b.Bits)) & ((1 << b.Bits) - 1) + } +} + +// ParseSigned extracts the bitfield b from i, and return it as a signed integer. +// ParseSigned will panic if b is invalid. +func (b BitField) ParseSigned(i uint64) int64 { + u := int64(b.Parse(i)) + return u << (64 - b.Bits) >> (64 - b.Bits) +} diff --git a/s390x/s390xasm/gnu.go b/s390x/s390xasm/gnu.go new file mode 100644 index 00000000..71b9f138 --- /dev/null +++ b/s390x/s390xasm/gnu.go @@ -0,0 +1,1020 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package s390xasm + +// Instructions with extended mnemonics fall under various categories. +// To handle each of them in one single function, various different +// structure types are defined as below. Corresponding instruction +// structures are created with the help of these base structures. +// Different instruction types are as below: + +// Typ1 - Instructions having different base and extended mnemonic strings. +// +// These instructions have single M-field value and single offset. +type typ1ExtndMnics struct { + BaseOpStr string + Value uint8 + Offset uint8 + ExtnOpStr string +} + +// Typ2 - Instructions having couple of extra strings added to the base mnemonic string, +// +// depending on the condition code evaluation. +// These instructions have single M-field value and single offset. +type typ2ExtndMnics struct { + Value uint8 + Offset uint8 + ExtnOpStr string +} + +// Typ3 - Instructions having couple of extra strings added to the base mnemonic string, +// +// depending on the condition code evaluation. +// These instructions have two M-field values and two offsets. +type typ3ExtndMnics struct { + Value1 uint8 + Value2 uint8 + Offset1 uint8 + Offset2 uint8 + ExtnOpStr string +} + +// Typ4 - Instructions having different base and extended mnemonic strings. +// +// These instructions have two M-field values and two offsets. +type typ4ExtndMnics struct { + BaseOpStr string + Value1 uint8 + Value2 uint8 + Offset1 uint8 + Offset2 uint8 + ExtnOpStr string +} + +// Typ5 - Instructions having different base and extended mnemonic strings. +// +// These instructions have three M-field values and three offsets. +type typ5ExtndMnics struct { + BaseOpStr string + Value1 uint8 + Value2 uint8 + Value3 uint8 + Offset1 uint8 + Offset2 uint8 + Offset3 uint8 + ExtnOpStr string +} + +// "func Handleextndmnemonic" - This is the function where the extended mnemonic logic +// is implemented. This function defines various structures to keep a list of base +// instructions and their extended mnemonic strings. These structure will also have +// M-field values and offset values defined, based on their type. +// HandleExtndMnemonic takes "inst" structure as the input variable. +// Inst structure will have all the details related to an instruction. Based on the +// opcode base string, a switch-case statement is executed. In that, based on the +// M-field value and the offset value of that particular M-field, extended mnemonic +// string is either searched or constructed by adding couple of extra strings to the base +// opcode string from one of the structure defined below. +func HandleExtndMnemonic(inst *Inst) string { + + brnchInstrExtndMnics := []typ1ExtndMnics{ + //BIC - BRANCH INDIRECT ON CONDITION instruction + typ1ExtndMnics{BaseOpStr: "bic", Value: 1, Offset: 0, ExtnOpStr: "bio"}, + typ1ExtndMnics{BaseOpStr: "bic", Value: 2, Offset: 0, ExtnOpStr: "bih"}, + typ1ExtndMnics{BaseOpStr: "bic", Value: 4, Offset: 0, ExtnOpStr: "bil"}, + typ1ExtndMnics{BaseOpStr: "bic", Value: 7, Offset: 0, ExtnOpStr: "bine"}, + typ1ExtndMnics{BaseOpStr: "bic", Value: 8, Offset: 0, ExtnOpStr: "bie"}, + typ1ExtndMnics{BaseOpStr: "bic", Value: 11, Offset: 0, ExtnOpStr: "binl"}, + typ1ExtndMnics{BaseOpStr: "bic", Value: 13, Offset: 0, ExtnOpStr: "binh"}, + typ1ExtndMnics{BaseOpStr: "bic", Value: 14, Offset: 0, ExtnOpStr: "bino"}, + typ1ExtndMnics{BaseOpStr: "bic", Value: 15, Offset: 0, ExtnOpStr: "bi"}, + + //BCR - BRANCH ON CONDITION instruction + typ1ExtndMnics{BaseOpStr: "bcr", Value: 0, Offset: 0, ExtnOpStr: "nopr"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 1, Offset: 0, ExtnOpStr: "bor"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 2, Offset: 0, ExtnOpStr: "bhr"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 4, Offset: 0, ExtnOpStr: "blr"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 7, Offset: 0, ExtnOpStr: "bner"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 8, Offset: 0, ExtnOpStr: "ber"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 11, Offset: 0, ExtnOpStr: "bnlr"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 13, Offset: 0, ExtnOpStr: "bnhr"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 14, Offset: 0, ExtnOpStr: "bnor"}, + typ1ExtndMnics{BaseOpStr: "bcr", Value: 15, Offset: 0, ExtnOpStr: "br"}, + + //BC - BRANCH ON CONDITION instruction + typ1ExtndMnics{BaseOpStr: "bc", Value: 0, Offset: 0, ExtnOpStr: "nopr"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 1, Offset: 0, ExtnOpStr: "bo"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 2, Offset: 0, ExtnOpStr: "bh"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 4, Offset: 0, ExtnOpStr: "bl"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 7, Offset: 0, ExtnOpStr: "bne"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 8, Offset: 0, ExtnOpStr: "be"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 11, Offset: 0, ExtnOpStr: "bnl"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 13, Offset: 0, ExtnOpStr: "bnh"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 14, Offset: 0, ExtnOpStr: "bno"}, + typ1ExtndMnics{BaseOpStr: "bc", Value: 15, Offset: 0, ExtnOpStr: "b"}, + + //BRC - BRANCH RELATIVE ON CONDITION instruction + typ1ExtndMnics{BaseOpStr: "brc", Value: 0, Offset: 0, ExtnOpStr: "jnop"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 1, Offset: 0, ExtnOpStr: "jo"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 2, Offset: 0, ExtnOpStr: "jh"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 4, Offset: 0, ExtnOpStr: "jl"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 7, Offset: 0, ExtnOpStr: "jne"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 8, Offset: 0, ExtnOpStr: "je"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 11, Offset: 0, ExtnOpStr: "jnl"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 13, Offset: 0, ExtnOpStr: "jnh"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 14, Offset: 0, ExtnOpStr: "jno"}, + typ1ExtndMnics{BaseOpStr: "brc", Value: 15, Offset: 0, ExtnOpStr: "j"}, + + //BRCL - BRANCH RELATIVE ON CONDITION LONG instruction + typ1ExtndMnics{BaseOpStr: "brcl", Value: 0, Offset: 0, ExtnOpStr: "jgnop"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 1, Offset: 0, ExtnOpStr: "jgo"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 2, Offset: 0, ExtnOpStr: "jgh"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 4, Offset: 0, ExtnOpStr: "jgl"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 7, Offset: 0, ExtnOpStr: "jgne"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 8, Offset: 0, ExtnOpStr: "jge"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 11, Offset: 0, ExtnOpStr: "jgnl"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 13, Offset: 0, ExtnOpStr: "jgnh"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 14, Offset: 0, ExtnOpStr: "jgno"}, + typ1ExtndMnics{BaseOpStr: "brcl", Value: 15, Offset: 0, ExtnOpStr: "jg"}, + } + + //Compare instructions + cmpInstrExtndMnics := []typ2ExtndMnics{ + typ2ExtndMnics{Value: 2, Offset: 2, ExtnOpStr: "h"}, + typ2ExtndMnics{Value: 4, Offset: 2, ExtnOpStr: "l"}, + typ2ExtndMnics{Value: 6, Offset: 2, ExtnOpStr: "ne"}, + typ2ExtndMnics{Value: 8, Offset: 2, ExtnOpStr: "e"}, + typ2ExtndMnics{Value: 10, Offset: 2, ExtnOpStr: "nl"}, + typ2ExtndMnics{Value: 12, Offset: 2, ExtnOpStr: "nh"}, + } + + //Load and Store instructions + ldSt_InstrExtndMnics := []typ2ExtndMnics{ + typ2ExtndMnics{Value: 1, Offset: 2, ExtnOpStr: "o"}, + typ2ExtndMnics{Value: 2, Offset: 2, ExtnOpStr: "h"}, + typ2ExtndMnics{Value: 3, Offset: 2, ExtnOpStr: "nle"}, + typ2ExtndMnics{Value: 4, Offset: 2, ExtnOpStr: "l"}, + typ2ExtndMnics{Value: 5, Offset: 2, ExtnOpStr: "nhe"}, + typ2ExtndMnics{Value: 6, Offset: 2, ExtnOpStr: "lh"}, + typ2ExtndMnics{Value: 7, Offset: 2, ExtnOpStr: "ne"}, + typ2ExtndMnics{Value: 8, Offset: 2, ExtnOpStr: "e"}, + typ2ExtndMnics{Value: 9, Offset: 2, ExtnOpStr: "nlh"}, + typ2ExtndMnics{Value: 10, Offset: 2, ExtnOpStr: "he"}, + typ2ExtndMnics{Value: 11, Offset: 2, ExtnOpStr: "nl"}, + typ2ExtndMnics{Value: 12, Offset: 2, ExtnOpStr: "le"}, + typ2ExtndMnics{Value: 13, Offset: 2, ExtnOpStr: "nh"}, + typ2ExtndMnics{Value: 14, Offset: 2, ExtnOpStr: "no"}, + } + + vecInstrExtndMnics := []typ2ExtndMnics{ + typ2ExtndMnics{Value: 0, Offset: 3, ExtnOpStr: "b"}, + typ2ExtndMnics{Value: 1, Offset: 3, ExtnOpStr: "h"}, + typ2ExtndMnics{Value: 2, Offset: 3, ExtnOpStr: "f"}, + typ2ExtndMnics{Value: 3, Offset: 3, ExtnOpStr: "g"}, + typ2ExtndMnics{Value: 4, Offset: 3, ExtnOpStr: "q"}, + typ2ExtndMnics{Value: 6, Offset: 3, ExtnOpStr: "lf"}, + } + + //VCEQ, VCH, VCHL + vec2InstrExtndMnics := []typ3ExtndMnics{ + typ3ExtndMnics{Value1: 0, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "b"}, + typ3ExtndMnics{Value1: 1, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "h"}, + typ3ExtndMnics{Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "f"}, + typ3ExtndMnics{Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "g"}, + typ3ExtndMnics{Value1: 0, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "bs"}, + typ3ExtndMnics{Value1: 1, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "hs"}, + typ3ExtndMnics{Value1: 2, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "fs"}, + typ3ExtndMnics{Value1: 3, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "gs"}, + } + + //VFAE, VFEE, VFENE + vec21InstrExtndMnics := []typ3ExtndMnics{ + typ3ExtndMnics{Value1: 0, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "b"}, + typ3ExtndMnics{Value1: 1, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "h"}, + typ3ExtndMnics{Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "f"}, + typ3ExtndMnics{Value1: 0, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "bs"}, + typ3ExtndMnics{Value1: 1, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "hs"}, + typ3ExtndMnics{Value1: 2, Value2: 1, Offset1: 3, Offset2: 4, ExtnOpStr: "fs"}, + typ3ExtndMnics{Value1: 0, Value2: 2, Offset1: 3, Offset2: 4, ExtnOpStr: "zb"}, + typ3ExtndMnics{Value1: 1, Value2: 2, Offset1: 3, Offset2: 4, ExtnOpStr: "zh"}, + typ3ExtndMnics{Value1: 2, Value2: 2, Offset1: 3, Offset2: 4, ExtnOpStr: "zf"}, + typ3ExtndMnics{Value1: 0, Value2: 3, Offset1: 3, Offset2: 4, ExtnOpStr: "zbs"}, + typ3ExtndMnics{Value1: 1, Value2: 3, Offset1: 3, Offset2: 4, ExtnOpStr: "zhs"}, + typ3ExtndMnics{Value1: 2, Value2: 3, Offset1: 3, Offset2: 4, ExtnOpStr: "zfs"}, + } + + vec3InstrExtndMnics := []typ3ExtndMnics{ + typ3ExtndMnics{Value1: 2, Value2: 0, Offset1: 2, Offset2: 3, ExtnOpStr: "sb"}, + typ3ExtndMnics{Value1: 3, Value2: 0, Offset1: 2, Offset2: 3, ExtnOpStr: "db"}, + typ3ExtndMnics{Value1: 4, Value2: 0, Offset1: 2, Offset2: 3, ExtnOpStr: "xb"}, + } + + vec4InstrExtndMnics := []typ4ExtndMnics{ + // VFA - VECTOR FP ADD + typ4ExtndMnics{BaseOpStr: "vfa", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfasb"}, + typ4ExtndMnics{BaseOpStr: "vfa", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfadb"}, + typ4ExtndMnics{BaseOpStr: "vfa", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfasb"}, + typ4ExtndMnics{BaseOpStr: "vfa", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfadb"}, + typ4ExtndMnics{BaseOpStr: "vfa", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfaxb"}, + + // VFD - VECTOR FP DIVIDE + typ4ExtndMnics{BaseOpStr: "vfd", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfdsb"}, + typ4ExtndMnics{BaseOpStr: "vfd", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfddb"}, + typ4ExtndMnics{BaseOpStr: "vfd", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfdsb"}, + typ4ExtndMnics{BaseOpStr: "vfd", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfddb"}, + typ4ExtndMnics{BaseOpStr: "vfd", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfdxb"}, + + // VFLL - VECTOR FP LOAD LENGTHENED + typ4ExtndMnics{BaseOpStr: "vfll", Value1: 2, Value2: 0, Offset1: 2, Offset2: 3, ExtnOpStr: "vflfs"}, + typ4ExtndMnics{BaseOpStr: "vfll", Value1: 2, Value2: 8, Offset1: 2, Offset2: 3, ExtnOpStr: "wflls"}, + typ4ExtndMnics{BaseOpStr: "vfll", Value1: 3, Value2: 8, Offset1: 2, Offset2: 3, ExtnOpStr: "wflld"}, + + // VFMAX - VECTOR FP MAXIMUM + typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmaxsb"}, + typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmaxdb"}, + typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmaxsb"}, + typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmaxdb"}, + typ4ExtndMnics{BaseOpStr: "vfmax", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmaxxb"}, + + // VFMIN - VECTOR FP MINIMUM + typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfminsb"}, + typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmindb"}, + typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfminsb"}, + typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmindb"}, + typ4ExtndMnics{BaseOpStr: "vfmin", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfminxb"}, + + // VFM - VECTOR FP MULTIPLY + typ4ExtndMnics{BaseOpStr: "vfm", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmsb"}, + typ4ExtndMnics{BaseOpStr: "vfm", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfmdb"}, + typ4ExtndMnics{BaseOpStr: "vfm", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmsb"}, + typ4ExtndMnics{BaseOpStr: "vfm", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmdb"}, + typ4ExtndMnics{BaseOpStr: "vfm", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfmxb"}, + + // VFSQ - VECTOR FP SQUARE ROOT + typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfsqsb"}, + typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfsqdb"}, + typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsqsb"}, + typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsqdb"}, + typ4ExtndMnics{BaseOpStr: "vfsq", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsqxb"}, + + // VFS - VECTOR FP SUBTRACT + typ4ExtndMnics{BaseOpStr: "vfs", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfssb"}, + typ4ExtndMnics{BaseOpStr: "vfs", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vfsdb"}, + typ4ExtndMnics{BaseOpStr: "vfs", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfssb"}, + typ4ExtndMnics{BaseOpStr: "vfs", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsdb"}, + typ4ExtndMnics{BaseOpStr: "vfs", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wfsxb"}, + + // VFTCI - VECTOR FP TEST DATA CLASS IMMEDIATE + typ4ExtndMnics{BaseOpStr: "vftci", Value1: 2, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vftcisb"}, + typ4ExtndMnics{BaseOpStr: "vftci", Value1: 3, Value2: 0, Offset1: 3, Offset2: 4, ExtnOpStr: "vftcidb"}, + typ4ExtndMnics{BaseOpStr: "vftci", Value1: 2, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wftcisb"}, + typ4ExtndMnics{BaseOpStr: "vftci", Value1: 3, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wftcidb"}, + typ4ExtndMnics{BaseOpStr: "vftci", Value1: 4, Value2: 8, Offset1: 3, Offset2: 4, ExtnOpStr: "wftcixb"}, + } + + vec6InstrExtndMnics := []typ5ExtndMnics{ + // VFCE - VECTOR FP COMPARE EQUAL + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcesb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcesbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcedb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfcedbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcesb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcesbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcedb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcedbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 4, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcexb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 4, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfcexbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkesb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkesbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkedb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkedbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkesb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 2, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkesbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkedb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 3, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkedbs"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 4, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkexb"}, + typ5ExtndMnics{BaseOpStr: "vfce", Value1: 4, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkexbs"}, + + // VFCH - VECTOR FP COMPARE HIGH + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchsb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchsbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchdb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchdbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchsb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchsbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchdb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchdbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 4, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchxb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 4, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchxbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhsb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhsbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhdb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhdbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhsb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 2, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhsbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhdb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 3, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhdbs"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 4, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhxb"}, + typ5ExtndMnics{BaseOpStr: "vfch", Value1: 4, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhxbs"}, + + // VFCHE - VECTOR FP COMPARE HIGH OR EQUAL + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchesb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchesbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 0, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchedb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 0, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfchedbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchesb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchesbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchedb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchedbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 4, Value2: 8, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchexb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 4, Value2: 8, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfchexbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhesb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhesbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 4, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhedb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 4, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "vfkhedbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhesb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 2, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhesbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhedb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 3, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhedbs"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 4, Value2: 12, Value3: 0, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhexb"}, + typ5ExtndMnics{BaseOpStr: "vfche", Value1: 4, Value2: 12, Value3: 1, Offset1: 3, Offset2: 4, Offset3: 5, ExtnOpStr: "wfkhexbs"}, + + // VFPSO - VECTOR FP PERFORM SIGN OPERATION + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 0, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflcsb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 8, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflcsb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 0, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflnsb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 8, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflnsb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 0, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflpsb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 2, Value2: 8, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflpsb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 0, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflcdb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 8, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflcdb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 0, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflndb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 8, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflndb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 0, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "vflpdb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 3, Value2: 8, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflpdb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 4, Value2: 8, Value3: 0, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflcxb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 4, Value2: 8, Value3: 1, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflnxb"}, + typ5ExtndMnics{BaseOpStr: "vfpso", Value1: 4, Value2: 8, Value3: 2, Offset1: 2, Offset2: 3, Offset3: 4, ExtnOpStr: "wflpxb"}, + } + + vec7InstrExtndMnics := []typ4ExtndMnics{ + // VFMA - VECTOR FP MULTIPLY AND ADD + typ4ExtndMnics{BaseOpStr: "vfma", Value1: 0, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "vfmasb"}, + typ4ExtndMnics{BaseOpStr: "vfma", Value1: 0, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "vfmadb"}, + typ4ExtndMnics{BaseOpStr: "vfma", Value1: 8, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmasb"}, + typ4ExtndMnics{BaseOpStr: "vfma", Value1: 8, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmadb"}, + typ4ExtndMnics{BaseOpStr: "vfma", Value1: 8, Value2: 4, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmaxb"}, + + // VFMS - VECTOR FP MULTIPLY AND SUBTRACT + typ4ExtndMnics{BaseOpStr: "vfms", Value1: 0, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "vfmssb"}, + typ4ExtndMnics{BaseOpStr: "vfms", Value1: 0, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "vfmsdb"}, + typ4ExtndMnics{BaseOpStr: "vfms", Value1: 8, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmssb"}, + typ4ExtndMnics{BaseOpStr: "vfms", Value1: 8, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmsdb"}, + typ4ExtndMnics{BaseOpStr: "vfms", Value1: 8, Value2: 4, Offset1: 4, Offset2: 5, ExtnOpStr: "wfmsxb"}, + + // VFNMA - VECTOR FP NEGATIVE MULTIPLY AND ADD + typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 0, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "vfnmasb"}, + typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 0, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "vfnmadb"}, + typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 8, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmasb"}, + typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 8, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmadb"}, + typ4ExtndMnics{BaseOpStr: "vfnma", Value1: 8, Value2: 4, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmaxb"}, + + // VFNMS - VECTOR FP NEGATIVE MULTIPLY AND SUBTRACT + typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 0, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "vfnmssb"}, + typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 0, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "vfnmsdb"}, + typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 8, Value2: 2, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmssb"}, + typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 8, Value2: 3, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmsdb"}, + typ4ExtndMnics{BaseOpStr: "vfnms", Value1: 8, Value2: 4, Offset1: 4, Offset2: 5, ExtnOpStr: "wfnmsxb"}, + } + + opString := inst.Op.String() + newOpStr := opString + + if inst.Enc == 0 { + return ".long 0x0" + } else if inst.Op == 0 { + return "error: unknown instruction" + } + + switch opString { + // Case to handle all "branch" instructions with one M-field operand + case "bic", "bcr", "bc", "brc", "brcl": + + for i := 0; i < len(brnchInstrExtndMnics); i++ { + if opString == brnchInstrExtndMnics[i].BaseOpStr && + uint8(inst.Args[brnchInstrExtndMnics[i].Offset].(Mask)) == brnchInstrExtndMnics[i].Value { + newOpStr = brnchInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(brnchInstrExtndMnics[i].Offset)) + break + } + } + + // Case to handle all "compare" instructions with one M-field operand + case "crb", "cgrb", "crj", "cgrj", "crt", "cgrt", "cib", "cgib", "cij", "cgij", "cit", "cgit", "clrb", "clgrb", + "clrj", "clgrj", "clrt", "clgrt", "clt", "clgt", "clib", "clgib", "clij", "clgij", "clfit", "clgit": + + for i := 0; i < len(cmpInstrExtndMnics); i++ { + //For CLT and CLGT instructions, M-value is the second operand. + //Hence, set the offset to "1" + if opString == "clt" || opString == "clgt" { + cmpInstrExtndMnics[i].Offset = 1 + } + + if uint8(inst.Args[cmpInstrExtndMnics[i].Offset].(Mask)) == cmpInstrExtndMnics[i].Value { + newOpStr = opString + cmpInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(cmpInstrExtndMnics[i].Offset)) + break + } + } + + // Case to handle all "load" and "store" instructions with one M-field operand + case "lochhi", "lochi", "locghi", "locfhr", "locfh", "locr", "locgr", "loc", + "locg", "selr", "selgr", "selfhr", "stocfh", "stoc", "stocg": + + for i := 0; i < len(ldSt_InstrExtndMnics); i++ { + + //For LOCFH, LOC, LOCG, SELR, SELGR, SELFHR, STOCFH, STOC, STOCG instructions, + //M-value is the forth operand. Hence, set the offset to "3" + if opString == "locfh" || opString == "loc" || opString == "locg" || opString == "selr" || opString == "selgr" || + opString == "selfhr" || opString == "stocfh" || opString == "stoc" || opString == "stocg" { + ldSt_InstrExtndMnics[i].Offset = 3 + } + + if uint8(inst.Args[ldSt_InstrExtndMnics[i].Offset].(Mask)) == ldSt_InstrExtndMnics[i].Value { + newOpStr = opString + ldSt_InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(ldSt_InstrExtndMnics[i].Offset)) + break + } + } + + // Case to handle all "vector" instructions with one M-field operand + case "vavg", "vavgl", "verllv", "veslv", "vesrav", "vesrlv", "vgfm", "vgm", "vmx", "vmxl", "vmrh", "vmrl", "vmn", "vmnl", "vrep", + "vclz", "vctz", "vec", "vecl", "vlc", "vlp", "vpopct", "vrepi", "verim", "verll", "vesl", "vesra", "vesrl", "vgfma", "vlrep", + "vlgv", "vlvg", "vlbrrep", "vler", "vlbr", "vstbr", "vster", "vpk", "vme", "vmh", "vmle", "vmlh", "vmlo", "vml", "vmo", "vmae", + "vmale", "vmalo", "vmal", "vmah", "vmalh", "vmao", "vmph", "vmplh", "vupl", "vupll", "vscbi", "vs", "vsum", "vsumg", "vsumq", "va", "vacc": + + switch opString { + + case "vavg", "vavgl", "verllv", "veslv", "vesrav", "vesrlv", "vgfm", "vgm", "vmx", "vmxl", "vmrh", "vmrl", "vmn", "vmnl", "vrep": + //M-field is 3rd arg for all these instructions. Hence, set the offset to "2" + for i := 0; i < len(vecInstrExtndMnics)-2; i++ { // 0,1,2,3 + if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset)) + break + } + } + + case "vclz", "vctz", "vec", "vecl", "vlc", "vlp", "vpopct", "vrepi": + for i := 0; i < len(vecInstrExtndMnics)-2; i++ { //0,1,2,3 + if uint8(inst.Args[vecInstrExtndMnics[i].Offset-1].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset-1)) + break + } + } + + case "verim", "verll", "vesl", "vesra", "vesrl", "vgfma", "vlrep": + for i := 0; i < len(vecInstrExtndMnics)-2; i++ { //0,1,2,3 + if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1)) + break + } + } + + case "vlgv", "vlvg": + for i := 0; i < len(vecInstrExtndMnics)-2; i++ { + if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1)) + break + } + } + + case "vlbrrep", "vler", "vster": + for i := 1; i < len(vecInstrExtndMnics)-2; i++ { + if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1)) + break + } + } + + case "vpk": + for i := 1; i < len(vecInstrExtndMnics)-2; i++ { + if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset)) + break + } + } + + case "vlbr", "vstbr": + for i := 1; i < len(vecInstrExtndMnics)-1; i++ { + if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1)) + break + } + } + case "vme", "vmh", "vmle", "vmlh", "vmlo", "vmo": + for i := 0; i < len(vecInstrExtndMnics)-3; i++ { //0,1,2 + if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset)) + break + } + } + + case "vml": + for i := 0; i < len(vecInstrExtndMnics)-3; i++ { //0,1,2 + if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value { + if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == 1 { + newOpStr = opString + string("hw") + } else { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + } + removeArg(inst, int8(vecInstrExtndMnics[i].Offset)) + break + } + } + + case "vmae", "vmale", "vmalo", "vmal", "vmah", "vmalh", "vmao": + for i := 0; i < len(vecInstrExtndMnics)-3; i++ { //0,1,2 + if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1)) + break + } + } + + case "vmph", "vmplh", "vupl", "vupll": //0,1,2 + for i := 0; i < len(vecInstrExtndMnics)-3; i++ { + if uint8(inst.Args[vecInstrExtndMnics[i].Offset-1].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset-1)) + break + } + } + + case "vscbi", "vs", "va", "vacc": // 0,1,2,3,4 + for i := 0; i < len(vecInstrExtndMnics)-1; i++ { + if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset)) + break + } + } + case "vsum", "vsumg", "vsumq": + var off int + switch opString { + case "vsum": + off = 0 + case "vsumg": + off = 1 + case "vsumq": + off = 2 + + } + for i := off; i < len(vecInstrExtndMnics)-4+off; i++ { + if uint8(inst.Args[vecInstrExtndMnics[i].Offset].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset)) + break + } + } + } + + case "vllez": + for i := 0; i < len(vecInstrExtndMnics); i++ { + if i == 4 { + continue + } + if uint8(inst.Args[vecInstrExtndMnics[i].Offset+1].(Mask)) == vecInstrExtndMnics[i].Value { + newOpStr = opString + vecInstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vecInstrExtndMnics[i].Offset+1)) + break + } + } + + case "vgbm": + if uint16(inst.Args[1].(Imm)) == uint16(0) { + newOpStr = "vzeo" + removeArg(inst, int8(1)) + } else if uint16(inst.Args[1].(Imm)) == uint16(0xFFFF) { + newOpStr = "vone" + removeArg(inst, int8(1)) + } + case "vno": + if uint8(inst.Args[1].(VReg)) == uint8(inst.Args[2].(VReg)) { //Bitwise Not instruction(VNOT) if V2 equal to v3 + newOpStr = opString + "t" + removeArg(inst, int8(2)) + } + + case "vmsl": + if uint8(inst.Args[4].(Mask)) == uint8(3) { + newOpStr = opString + "g" + removeArg(inst, int8(4)) + } + + case "vflr": + if uint8(inst.Args[2].(Mask)) == uint8(3) && ((inst.Args[3].(Mask)>>3)&0x1 == 0x1) { + inst.Args[3] = (inst.Args[3].(Mask) ^ 0x8) + newOpStr = "wflrd" + removeArg(inst, int8(2)) + } else if uint8(inst.Args[2].(Mask)) == uint8(4) && ((inst.Args[3].(Mask)>>3)&0x1 == 0x1) { + inst.Args[3] = (inst.Args[3].(Mask) ^ 0x8) + newOpStr = "wflrx" + removeArg(inst, int8(2)) + } else if uint8(inst.Args[2].(Mask)) == uint8(3) { + newOpStr = "vflrd" + removeArg(inst, int8(2)) + } + + case "vllebrz": + if uint8(inst.Args[4].(Mask)) == uint8(1) { + newOpStr = opString + "h" + removeArg(inst, int8(4)) + } else if uint8(inst.Args[4].(Mask)) == uint8(2) { + newOpStr = opString + "f" + removeArg(inst, int8(4)) + } else if uint8(inst.Args[4].(Mask)) == uint8(3) { + newOpStr = "ldrv" + removeArg(inst, int8(4)) + } else if uint8(inst.Args[4].(Mask)) == uint8(6) { + newOpStr = "lerv" + removeArg(inst, int8(4)) + } + + case "vschp": + if uint8(inst.Args[3].(Mask)) == uint8(2) { + newOpStr = "vschsp" + removeArg(inst, int8(3)) + } else if uint8(inst.Args[3].(Mask)) == uint8(3) { + newOpStr = "vschdp" + removeArg(inst, int8(3)) + } else if uint8(inst.Args[3].(Mask)) == uint8(4) { + newOpStr = "vschxp" + removeArg(inst, int8(3)) + } + + case "vsbcbi", "vsbi": + if uint8(inst.Args[4].(Mask)) == uint8(4) { + newOpStr = opString + vecInstrExtndMnics[4].ExtnOpStr + removeArg(inst, int8(4)) + } + + case "vac", "vaccc": + if uint8(inst.Args[4].(Mask)) == uint8(4) { + newOpStr = opString + vecInstrExtndMnics[4].ExtnOpStr + removeArg(inst, int8(4)) + } + + case "vceq", "vch", "vchl": + for i := 0; i < len(vec2InstrExtndMnics)-6; i++ { + if uint8(inst.Args[vec2InstrExtndMnics[i].Offset1].(Mask)) == vec2InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec2InstrExtndMnics[i].Offset2].(Mask)) == vec2InstrExtndMnics[i].Value2 { + newOpStr = opString + vec2InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec2InstrExtndMnics[i].Offset1)) + removeArg(inst, int8(vec2InstrExtndMnics[i].Offset2-1)) + break + } + } + + case "vpks", "vpkls": + for i := 1; i < len(vec2InstrExtndMnics)-6; i++ { + if i == 4 { + continue + } + if uint8(inst.Args[vec2InstrExtndMnics[i].Offset1].(Mask)) == vec2InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec2InstrExtndMnics[i].Offset2].(Mask)) == vec2InstrExtndMnics[i].Value2 { + newOpStr = opString + vec2InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec2InstrExtndMnics[i].Offset1)) + removeArg(inst, int8(vec2InstrExtndMnics[i].Offset2-1)) + break + } + } + case "vfee", "vfene": + var check bool + for i := 0; i < len(vec21InstrExtndMnics); i++ { + if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1].(Mask)) == vec21InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec21InstrExtndMnics[i].Offset2].(Mask)) == vec21InstrExtndMnics[i].Value2 { + newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1)) + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2-1)) + check = true + break + } + } + if !check { + if uint8(inst.Args[3].(Mask)) == 0 && (uint8(inst.Args[4].(Mask)) != uint8(0)) { + newOpStr = opString + vec21InstrExtndMnics[0].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[0].Offset1)) + } else if uint8(inst.Args[3].(Mask)) == 1 && (uint8(inst.Args[4].(Mask)) != uint8(0)) { + newOpStr = opString + vec21InstrExtndMnics[1].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[1].Offset1)) + } else if uint8(inst.Args[3].(Mask)) == 2 && (uint8(inst.Args[4].(Mask)) != uint8(0)) { + newOpStr = opString + vec21InstrExtndMnics[2].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[2].Offset1)) + } else if uint8(inst.Args[4].(Mask)) == 0 { + removeArg(inst, int8(vec21InstrExtndMnics[2].Offset2)) + } + } + + case "vfae", "vstrc": + off := uint8(0) + var check bool + if opString == "vstrc" { + off = uint8(1) + } + for i := 0; i < len(vec21InstrExtndMnics)-9; i++ { + if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+off].(Mask)) == vec21InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+off].(Mask)) == vec21InstrExtndMnics[i].Value2 { + newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+off)) + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2+off-1)) + check = true + break + } + } + + for i := 0; !(check) && (i < len(vec21InstrExtndMnics)-9); i++ { + if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+off].(Mask)) == vec21InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+off].(Mask)) == vec21InstrExtndMnics[i].Value2 { + newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+off)) + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2+off-1)) + check = true + break + } + } + //for i := 3; !(check) && (i < len(vec21InstrExtndMnics)); i++ { + for i := len(vec21InstrExtndMnics) - 1; !(check) && (i > 2); i-- { + if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+off].(Mask)) == vec21InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+off].(Mask))&(vec21InstrExtndMnics[i].Value2) == vec21InstrExtndMnics[i].Value2 { + x := uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+off].(Mask)) ^ (vec21InstrExtndMnics[i].Value2) + newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr + if x != 0 { + inst.Args[vec21InstrExtndMnics[i].Offset2+off] = Mask(x) + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+off)) + check = true + break + } else { + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+off)) + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2+off-1)) + check = true + break + } + } + } + if !check && inst.Args[4+off].(Mask) == Mask(0) { + removeArg(inst, int8(4+off)) + break + } + + case "vstrs": + var check bool + for i := 0; i < len(vec21InstrExtndMnics)-3; i++ { + if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+1].(Mask)) == vec21InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+1].(Mask)) == vec21InstrExtndMnics[i].Value2 { + newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+1)) + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2)) + check = true + break + } + if i == 2 { + i = i + 3 + } + } + + for i := 0; !(check) && (i < len(vec21InstrExtndMnics)-9); i++ { + if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1+1].(Mask)) == vec21InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec21InstrExtndMnics[i].Offset2+1].(Mask)) != 0 { + newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1+1)) + break + } + } + + case "vistr": + var check bool + for i := 0; i < len(vec21InstrExtndMnics)-6; i++ { + if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1-1].(Mask)) == vec21InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec21InstrExtndMnics[i].Offset2-1].(Mask)) == vec21InstrExtndMnics[i].Value2 { + newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1-1)) + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset2-2)) + check = true + break + } + } + + for i := 0; !(check) && (i < len(vec21InstrExtndMnics)-9); i++ { + if uint8(inst.Args[vec21InstrExtndMnics[i].Offset1-1].(Mask)) == vec21InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec21InstrExtndMnics[i].Offset2-1].(Mask)) != 0 { + newOpStr = opString + vec21InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec21InstrExtndMnics[i].Offset1-1)) + break + } + } + + if uint8(inst.Args[3].(Mask)) == 0 { + removeArg(inst, int8(3)) + break + } + + case "vcfps": + if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8)) + newOpStr = "wcefb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8)) + newOpStr = "wcdgb" + removeArg(inst, int8(2)) + break + } else if uint8(inst.Args[2].(Mask)) == uint8(2) { + newOpStr = "vcefb" + removeArg(inst, int8(2)) + break + } else if uint8(inst.Args[2].(Mask)) == uint8(3) { + newOpStr = "vcdgb" + removeArg(inst, int8(2)) + break + } + + case "vcfpl": + if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8)) + newOpStr = "wcelfb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8)) + newOpStr = "wcdlgb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(2) { + newOpStr = "vcelfb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(3) { + newOpStr = "vcdlgb" + removeArg(inst, int8(2)) + break + } + + case "vcsfp": + if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8)) + newOpStr = "wcfeb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8)) + newOpStr = "wcgdb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(2) { + newOpStr = "vcfeb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(3) { + newOpStr = "vcgdb" + removeArg(inst, int8(2)) + break + } + + case "vclfp": + if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8)) + newOpStr = "wclfeb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + inst.Args[3] = Mask((inst.Args[3].(Mask)) ^ (0x8)) + newOpStr = "wclgdb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(2) { + newOpStr = "vclfeb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(3) { + newOpStr = "vclgdb" + removeArg(inst, int8(2)) + break + } + + case "vfi": + if inst.Args[2].(Mask) == Mask(2) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + newOpStr = "wfisb" + removeArg(inst, int8(2)) + inst.Args[2] = Mask((inst.Args[2].(Mask)) ^ (0x8)) + break + } else if inst.Args[2].(Mask) == Mask(3) && ((inst.Args[3].(Mask)>>3)&(0x3) == 1) { + newOpStr = "wfidb" + removeArg(inst, int8(2)) + inst.Args[2] = Mask((inst.Args[2].(Mask)) ^ (0x8)) + break + } else if inst.Args[2].(Mask) == Mask(4) && ((inst.Args[3].(Mask)>>3)&(0x1) == 1) { + newOpStr = "wfixb" + removeArg(inst, int8(2)) + inst.Args[2] = Mask((inst.Args[2].(Mask)) ^ (0x8)) + break + } else if inst.Args[2].(Mask) == Mask(2) { + newOpStr = "vfisb" + removeArg(inst, int8(2)) + break + } else if inst.Args[2].(Mask) == Mask(3) { + newOpStr = "vfidb" + removeArg(inst, int8(2)) + break + } + + // Case to handle few vector instructions with 2 M-field operands + case "vfa", "vfd", "vfll", "vfmax", "vfmin", "vfm": + for i := 0; i < len(vec4InstrExtndMnics); i++ { + if opString == vec4InstrExtndMnics[i].BaseOpStr && + uint8(inst.Args[vec4InstrExtndMnics[i].Offset1].(Mask)) == vec4InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec4InstrExtndMnics[i].Offset2].(Mask)) == vec4InstrExtndMnics[i].Value2 { + newOpStr = vec4InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec4InstrExtndMnics[i].Offset1)) + removeArg(inst, int8(vec4InstrExtndMnics[i].Offset2-1)) + break + } + } + + // Case to handle few special "vector" instructions with 2 M-field operands + case "wfc", "wfk": + for i := 0; i < len(vec3InstrExtndMnics); i++ { + if uint8(inst.Args[vec3InstrExtndMnics[i].Offset1].(Mask)) == vec3InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec3InstrExtndMnics[i].Offset2].(Mask)) == vec3InstrExtndMnics[i].Value2 { + newOpStr = opString + vec3InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec3InstrExtndMnics[i].Offset1)) + removeArg(inst, int8(vec3InstrExtndMnics[i].Offset2-1)) + break + } + } + + // Case to handle few vector instructions with 2 M-field operands + case "vfma", "vfms", "vfnma", "vfnms": + for i := 0; i < len(vec7InstrExtndMnics); i++ { + if opString == vec7InstrExtndMnics[i].BaseOpStr && + uint8(inst.Args[vec7InstrExtndMnics[i].Offset1].(Mask)) == vec7InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec7InstrExtndMnics[i].Offset2].(Mask)) == vec7InstrExtndMnics[i].Value2 { + newOpStr = vec7InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec7InstrExtndMnics[i].Offset1)) + removeArg(inst, int8(vec7InstrExtndMnics[i].Offset2-1)) + break + } + } + + // List of instructions with 3 M-field operands. + case "vfce", "vfch", "vfche", "vfpso": + for i := 0; i < len(vec6InstrExtndMnics); i++ { + if opString == vec6InstrExtndMnics[i].BaseOpStr && + uint8(inst.Args[vec6InstrExtndMnics[i].Offset1].(Mask)) == vec6InstrExtndMnics[i].Value1 && + uint8(inst.Args[vec6InstrExtndMnics[i].Offset2].(Mask)) == vec6InstrExtndMnics[i].Value2 && + uint8(inst.Args[vec6InstrExtndMnics[i].Offset3].(Mask)) == vec6InstrExtndMnics[i].Value3 { + newOpStr = vec6InstrExtndMnics[i].ExtnOpStr + removeArg(inst, int8(vec6InstrExtndMnics[i].Offset1)) + removeArg(inst, int8(vec6InstrExtndMnics[i].Offset2-1)) + removeArg(inst, int8(vec6InstrExtndMnics[i].Offset3-2)) + break + } + } + + default: + return opString + } + return newOpStr +} + +// This is the function that is called to print the disassembled instruction +// in the GNU (AT&T) syntax form. +func GNUSyntax(inst Inst, pc uint64) string { + if inst.Enc == 0 { + return ".long 0x0" + } else if inst.Op == 0 { + return "error: unknown instruction" + } + return inst.String(pc) +} + +// removeArg removes the arg in inst.Args[index]. +func removeArg(inst *Inst, index int8) { + for i := int(index); i < len(inst.Args); i++ { + if i+1 < len(inst.Args) { + inst.Args[i] = inst.Args[i+1] + } else { + inst.Args[i] = nil + } + } +} diff --git a/s390x/s390xasm/inst.go b/s390x/s390xasm/inst.go new file mode 100644 index 00000000..e1fde847 --- /dev/null +++ b/s390x/s390xasm/inst.go @@ -0,0 +1,433 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package s390xasm + +import ( + "bytes" + "fmt" + "strings" +) + +type Inst struct { + Op Op // Opcode mnemonic + Enc uint64 // Raw encoding bits + Len int // Length of encoding in bytes. + Args Args // Instruction arguments, in s390x ISA manual order. +} + +func (i Inst) String(pc uint64) string { + var buf bytes.Buffer + var rxb_check bool + m := i.Op.String() + if strings.HasPrefix(m, "v") || strings.Contains(m, "wfc") || strings.Contains(m, "wfk") { + rxb_check = true + } + mnemonic := HandleExtndMnemonic(&i) + buf.WriteString(fmt.Sprintf("%s", mnemonic)) + for j := 0; j < len(i.Args); j++ { + if i.Args[j] == nil { + break + } + str := i.Args[j].String(pc) + if j == 0 { + buf.WriteString(" ") + } else { + switch i.Args[j].(type) { + case VReg: + if _, ok := i.Args[j-1].(Disp12); ok { + buf.WriteString("(") + } else if _, ok := i.Args[j-1].(Disp20); ok { + buf.WriteString("(") + } else { + buf.WriteString(",") + } + case Reg: + if _, ok := i.Args[j-1].(Disp12); ok { + if str != "" { + buf.WriteString("(") + } + } else if _, ok := i.Args[j-1].(Disp20); ok { + if str != "" { + buf.WriteString("(") + } + } else { + buf.WriteString(",") + } + case Base: + if _, ok := i.Args[j-1].(VReg); ok { + buf.WriteString(",") + } else if _, ok := i.Args[j-1].(Reg); ok { + buf.WriteString(",") + } else if _, ok := i.Args[j-1].(Disp12); ok { + if str != "" { + buf.WriteString("(") + } + } else if _, ok := i.Args[j-1].(Disp20); ok { + if str != "" { + buf.WriteString("(") + } + } else if _, ok := i.Args[j-1].(Len); ok { + buf.WriteString(",") + } else if _, ok := i.Args[j-1].(Index); ok { + if ((i.Args[j-1].String(pc)) != "") && str != "" { + str = "," + str + } else if str == "" { + str = ")" + } + } + case Index, Len: + if str != "" || (i.Args[j+1].String(pc)) != "" { + buf.WriteString("(") + } else { + j = j + 1 + } + default: + buf.WriteString(",") + } + } + buf.WriteString(str) + if rxb_check && i.Args[j+2] == nil { + break + } + } + return buf.String() +} + +// An Op is an instruction operation. +type Op uint16 + +func (o Op) String() string { + if int(o) >= len(opstr) || opstr[o] == "" { + return fmt.Sprintf("Op(%d)", int(o)) + } + return opstr[o] +} + +// An Arg is a single instruction argument. +// One of these types: Reg, Base, Index, Disp20, Disp12, Len, Mask, Sign8, Sign16, Sign32, RegIm12, RegIm16, RegIm24, RegIm32. +type Arg interface { + IsArg() + String(pc uint64) string +} + +// An Args holds the instruction arguments. +// If an instruction has fewer than 6 arguments, +// the final elements in the array are nil. +type Args [8]Arg + +// Base represents an 4-bit Base Register field +type Base uint8 + +const ( + B0 Base = iota + B1 + B2 + B3 + B4 + B5 + B6 + B7 + B8 + B9 + B10 + B11 + B12 + B13 + B14 + B15 +) + +func (Base) IsArg() {} +func (r Base) String(pc uint64) string { + switch { + case B1 <= r && r <= B15: + s := "%" + return fmt.Sprintf("%sr%d)", s, int(r-B0)) + case B0 == r: + return fmt.Sprintf("") + default: + return fmt.Sprintf("Base(%d)", int(r)) + } +} + +// Index represents an 4-bit Index Register field +type Index uint8 + +const ( + X0 Index = iota + X1 + X2 + X3 + X4 + X5 + X6 + X7 + X8 + X9 + X10 + X11 + X12 + X13 + X14 + X15 +) + +func (Index) IsArg() {} +func (r Index) String(pc uint64) string { + switch { + case X1 <= r && r <= X15: + s := "%" + return fmt.Sprintf("%sr%d", s, int(r-X0)) + case X0 == r: + return fmt.Sprintf("") + default: + return fmt.Sprintf("Base(%d)", int(r)) + } +} + +// Disp20 represents an 20-bit Unsigned Displacement +type Disp20 uint32 + +func (Disp20) IsArg() {} +func (r Disp20) String(pc uint64) string { + if (r>>19)&0x01 == 1 { + return fmt.Sprintf("%d", int32(r|0xfff<<20)) + } else { + return fmt.Sprintf("%d", int32(r)) + } +} + +// Disp12 represents an 12-bit Unsigned Displacement +type Disp12 uint16 + +func (Disp12) IsArg() {} +func (r Disp12) String(pc uint64) string { + return fmt.Sprintf("%d", r) +} + +// RegIm12 represents an 12-bit Register immediate number. +type RegIm12 uint16 + +func (RegIm12) IsArg() {} +func (r RegIm12) String(pc uint64) string { + if (r>>11)&0x01 == 1 { + return fmt.Sprintf("%#x", pc+(2*uint64(int16(r|0xf<<12)))) + } else { + return fmt.Sprintf("%#x", pc+(2*uint64(int16(r)))) + } +} + +// RegIm16 represents an 16-bit Register immediate number. +type RegIm16 uint16 + +func (RegIm16) IsArg() {} +func (r RegIm16) String(pc uint64) string { + return fmt.Sprintf("%#x", pc+(2*uint64(int16(r)))) +} + +// RegIm24 represents an 24-bit Register immediate number. +type RegIm24 uint32 + +func (RegIm24) IsArg() {} +func (r RegIm24) String(pc uint64) string { + if (r>>23)&0x01 == 1 { + return fmt.Sprintf("%#x", pc+(2*uint64(int32(r|0xff<<24)))) + } else { + return fmt.Sprintf("%#x", pc+(2*uint64(int32(r)))) + } +} + +// RegIm32 represents an 32-bit Register immediate number. +type RegIm32 uint32 + +func (RegIm32) IsArg() {} +func (r RegIm32) String(pc uint64) string { + return fmt.Sprintf("%#x", pc+(2*uint64(int32(r)))) +} + +// A Reg is a single register. The zero value means R0, not the absence of a register. +// It also includes special registers. +type Reg uint16 + +const ( + R0 Reg = iota + R1 + R2 + R3 + R4 + R5 + R6 + R7 + R8 + R9 + R10 + R11 + R12 + R13 + R14 + R15 + F0 + F1 + F2 + F3 + F4 + F5 + F6 + F7 + F8 + F9 + F10 + F11 + F12 + F13 + F14 + F15 + A0 + A1 + A2 + A3 + A4 + A5 + A6 + A7 + A8 + A9 + A10 + A11 + A12 + A13 + A14 + A15 + C0 + C1 + C2 + C3 + C4 + C5 + C6 + C7 + C8 + C9 + C10 + C11 + C12 + C13 + C14 + C15 +) + +func (Reg) IsArg() {} +func (r Reg) String(pc uint64) string { + s := "%" + switch { + case R0 <= r && r <= R15: + return fmt.Sprintf("%sr%d", s, int(r-R0)) + case F0 <= r && r <= F15: + return fmt.Sprintf("%sf%d", s, int(r-F0)) + case A0 <= r && r <= A15: + return fmt.Sprintf("%sa%d", s, int(r-A0)) + case C0 <= r && r <= C15: + return fmt.Sprintf("%sc%d", s, int(r-C0)) + default: + return fmt.Sprintf("Reg(%d)", int(r)) + } +} + +// VReg is a vector register. The zero value means V0, not the absence of a register. + +type VReg uint8 + +const ( + V0 VReg = iota + V1 + V2 + V3 + V4 + V5 + V6 + V7 + V8 + V9 + V10 + V11 + V12 + V13 + V14 + V15 + V16 + V17 + V18 + V19 + V20 + V21 + V22 + V23 + V24 + V25 + V26 + V27 + V28 + V29 + V30 + V31 +) + +func (VReg) IsArg() {} +func (r VReg) String(pc uint64) string { + s := "%" + if V0 <= r && r <= V31 { + return fmt.Sprintf("%sv%d", s, int(r-V0)) + } else { + return fmt.Sprintf("VReg(%d)", int(r)) + } +} + +// Imm represents an immediate number. +type Imm uint32 + +func (Imm) IsArg() {} +func (i Imm) String(pc uint64) string { + return fmt.Sprintf("%d", uint32(i)) +} + +// Sign8 represents an 8-bit signed immediate number. +type Sign8 int8 + +func (Sign8) IsArg() {} +func (i Sign8) String(pc uint64) string { + return fmt.Sprintf("%d", i) +} + +// Sign16 represents an 16-bit signed immediate number. +type Sign16 int16 + +func (Sign16) IsArg() {} +func (i Sign16) String(pc uint64) string { + return fmt.Sprintf("%d", i) +} + +// Sign32 represents an 32-bit signed immediate number. +type Sign32 int32 + +func (Sign32) IsArg() {} +func (i Sign32) String(pc uint64) string { + return fmt.Sprintf("%d", i) +} + +// Mask represents an 4-bit mask value +type Mask uint8 + +func (Mask) IsArg() {} +func (i Mask) String(pc uint64) string { + return fmt.Sprintf("%d", i) +} + +// Len represents an 8-bit type holds 4/8-bit Len argument +type Len uint8 + +func (Len) IsArg() {} +func (i Len) String(pc uint64) string { + return fmt.Sprintf("%d", uint16(i)+1) +} diff --git a/s390x/s390xasm/plan9.go b/s390x/s390xasm/plan9.go new file mode 100644 index 00000000..fa5e3362 --- /dev/null +++ b/s390x/s390xasm/plan9.go @@ -0,0 +1,1295 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package s390xasm + +import ( + "fmt" + "strconv" + "strings" +) + +var vectorSize = map[int]string{0: "B", 1: "H", 2: "F", 3: "G", 4: "Q"} +var vectorCS = map[int]string{0: "BS", 1: "HS", 2: "FS", 3: "GS"} + +// GoSyntax returns the Go assembler syntax for the instruction. +// The syntax was originally defined by Plan 9. +// The inst relates to single instruction. +// The pc is the program counter of the instruction, used for +// expanding PC-relative addresses into absolute ones. +// The symname function queries the symbol table for the program +// being disassembled. Given a target address it returns the name +// and base address of the symbol containing the target, if any; +// otherwise it returns "", 0. +func GoSyntax(inst Inst, pc uint64, symname func(uint64) (string, uint64)) string { + if symname == nil { + symname = func(uint64) (string, uint64) { return "", 0 } + } + + var args []string + opString := inst.Op.String() + op := strings.ToUpper(opString) + for i := 0; i < len(inst.Args); i++ { + if inst.Args[i] == nil { + break + } + switch inst.Args[i].(type) { + case Disp12, Disp20: + var temp []string + switch inst.Args[i+1].(type) { + case Index: // D(X,B) + for j := 0; j < 3; j++ { + temp = append(temp, plan9Arg(&inst, pc, symname, inst.Args[i+j])) + } + args = append(args, mem_operandx(temp)) + i = i + 2 + case Base: // D(B) + for j := 0; j < 2; j++ { + temp = append(temp, plan9Arg(&inst, pc, symname, inst.Args[i+j])) + } + args = append(args, mem_operand(temp)) + i = i + 1 + case VReg: // D(B) + for j := 0; j < 3; j++ { + temp = append(temp, plan9Arg(&inst, pc, symname, inst.Args[i+j])) + } + args = append(args, mem_operandv(temp)) + i = i + 2 + case Len: // D(L,B) + for j := 0; j < 3; j++ { + temp = append(temp, plan9Arg(&inst, pc, symname, inst.Args[i+j])) + } + ar1, ar2 := mem_operandl(temp) + args = append(args, ar1, ar2) + i = i + 2 + default: // D(R,B) + for j := 0; j < 3; j++ { + temp = append(temp, plan9Arg(&inst, pc, symname, inst.Args[i+j])) + } + args = append(args, mem_operandx(temp)) + i = i + 2 + } + default: + args = append(args, plan9Arg(&inst, pc, symname, inst.Args[i])) + } + } + if strings.HasPrefix(op, "V") || strings.Contains(op, "WFC") || strings.Contains(op, "WFK") { + args = args[:len(args)-1] + } + + switch inst.Op { + default: + switch len(args) { + case 0: + return op + case 1: + return fmt.Sprintf("%s %s", op, args[0]) + case 2: + if reverseOperandOrder(inst.Op) { + args[0], args[1] = args[1], args[0] + } + case 3: + if reverseOperandOrder(inst.Op) { + args[0], args[2] = args[2], args[0] + } else if reverseAllOperands(inst.Op) { + args[0], args[1], args[2] = args[1], args[2], args[0] + } + case 4: + if reverseOperandOrder(inst.Op) { + args[0], args[3] = args[3], args[0] + } else if reverseAllOperands(inst.Op) { + args[0], args[1], args[2], args[3] = args[1], args[2], args[3], args[0] + } + } + case LCGR, LCGFR: + switch inst.Op { + case LCGR: + op = "NEG" + case LCGFR: + op = "NEGW" + } + if args[0] == args[1] { + args = args[:1] + } else { + args[0], args[1] = args[1], args[0] + } + case LD, LE, LG, LGF, LLGF, LGH, LLGH, LGB, LLGC, LDY, LEY, LRVG, LRV, LRVH: + args[0], args[1] = args[1], args[0] + switch inst.Op { + case LG: + op = "MOVD" + case LGF: + op = "MOVW" + case LLGF: + op = "MOVWZ" + case LGH: + op = "MOVH" + case LLGH: + op = "MOVHZ" + case LGB: + op = "MOVB" + case LLGC: + op = "MOVBZ" + case LDY, LD: + op = "FMOVD" + case LEY, LE: + op = "FMOVS" + case LRVG: + op = "MOVDBR" + case LRV: + op = "MOVWBR" + case LRVH: + op = "MOVHBR" + } + case LA, LAY, LARL: + args[0], args[1] = args[1], args[0] + op = "MOVD" + + case LAA, LAAG, LAAL, LAALG, LAN, LANG, LAX, LAXG, LAO, LAOG: + args[0], args[1] = args[1], args[0] + case LM, LMY, LMG: // Load Multiple + switch inst.Op { + case LM, LMY: + op = "LMY" + } + args[0], args[1], args[2] = args[2], args[0], args[1] + + case STM, STMY, STMG: // Store Multiple + switch inst.Op { + case STM, STMY: + op = "STMY" + } + case ST, STY, STG, STHY, STCY, STRVG, STRV: + switch inst.Op { + case ST, STY: + op = "MOVW" + case STHY: + op = "MOVH" + case STCY: + op = "MOVB" + case STG: + op = "MOVD" + case STRVG: + op = "MOVDBR" + case STRV: + op = "MOVWBR" + } + case LGR, LGFR, LGHR, LGBR, LLGFR, LLGHR, LLGCR, LRVGR, LRVR, LDR: + switch inst.Op { + case LGR: + op = "MOVD" + case LGFR: + op = "MOVW" + case LGHR: + op = "MOVH" + case LGBR: + op = "MOVB" + case LLGFR: + op = "MOVWZ" + case LLGHR: + op = "MOVHZ" + case LLGCR: + op = "MOVBZ" + case LRVGR: + op = "MOVDBR" + case LRVR: + op = "MOVWBR" + case LDR: + op = "FMOVD" + } + args[0], args[1] = args[1], args[0] + case LZDR: + op = "FMOVD" + return op + " " + "$0" + ", " + args[0] + case LZER: + op = "FMOVS" + return op + " " + "$0" + ", " + args[0] + case STD, STDY, STE, STEY: + switch inst.Op { + case STD, STDY: + op = "FMOVD" + case STE, STEY: + op = "FMOVS" + } + + case LGHI, LLILH, LLIHL, LLIHH, LGFI, LLILF, LLIHF: + switch inst.Op { + case LGFI: + op = "MOVW" + case LGHI: + num, err := strconv.ParseInt(args[1][1:], 10, 16) + if err != nil { + return fmt.Sprintf("plan9Arg: error in converting ParseInt:%s", err) + } + if num == int64(int8(num)) { + op = "MOVB" + } else { + op = "MOVH" + } + default: + op = "MOVD" + } + args[0], args[1] = args[1], args[0] + case ARK, AGRK, ALGRK: + switch inst.Op { + case ARK: + op = "ADDW" + case AGRK: + op = "ADD" + case ALGRK: + op = "ADDC" + } + if args[0] == args[1] { + args[0], args[1] = args[2], args[0] + args = args[:2] + } else { + args[0], args[2] = args[2], args[0] + } + case AGHIK, AHIK, ALGHSIK: + num, err := strconv.ParseInt(args[2][1:], 10, 32) + if err != nil { + return fmt.Sprintf("plan9Arg: error in converting ParseInt:%s", err) + } + switch inst.Op { + case AGHIK: + if num < 0 { + op = "SUB" + args[2] = args[2][:1] + args[2][2:] + } else { + op = "ADD" + } + case AHIK: + op = "ADDW" + case ALGHSIK: + if num < 0 { + op = "SUBC" + args[2] = args[2][:1] + args[2][2:] + } else { + op = "ADDC" + } + } + args[0], args[2] = args[2], args[0] + case AGHI, AHI, AGFI, AFI, AR, ALCGR: + num, err := strconv.ParseInt(args[1][1:], 10, 32) + if err != nil { + return fmt.Sprintf("plan9Arg: error in converting ParseInt:%s", err) + } + switch inst.Op { + case AGHI, AGFI: + if num < 0 { + op = "SUB" + args[1] = args[1][:1] + args[1][2:] + } else { + op = "ADD" + } + case AHI, AFI, AR: + op = "ADDW" + case ALCGR: + op = "ADDE" + } + args[0], args[1] = args[1], args[0] + case AEBR, ADBR, DDBR, DEBR, MDBR, MEEBR, SDBR, SEBR, LPDBR, LNDBR, LPDFR, LNDFR, LCDFR, LCEBR, LEDBR, LDEBR, SQDBR, SQEBR: + switch inst.Op { + case AEBR: + op = "FADDS" + case ADBR: + op = "FADD" + case DDBR: + op = "FDIV" + case DEBR: + op = "FDIVS" + case MDBR: + op = "FMUL" + case MEEBR: + op = "FMULS" + case SDBR: + op = "FSUB" + case SEBR: + op = "FSUBS" + case LPDBR: + op = "FABS" + case LNDBR: + op = "FNABS" + case LCDFR: + op = "FNEG" + case LCEBR: + op = "FNEGS" + case SQDBR: + op = "FSQRT" + case SQEBR: + op = "FSQRTS" + } + args[0], args[1] = args[1], args[0] + case SR, SGR, SLGR, SLFI: + switch inst.Op { + case SR, SLFI: + op = "SUBW" + case SGR: + op = "SUB" + case SLGR: + op = "SUBC" + } + args[0], args[1] = args[1], args[0] + case SGRK, SLGRK, SRK: + switch inst.Op { + case SGRK: + op = "SUB" + case SLGRK: + op = "SUBC" + case SRK: + op = "SUBW" + } + if args[0] == args[1] { + args[0], args[1] = args[2], args[0] + args = args[:2] + } else { + args[0], args[2] = args[2], args[0] + } + case SLBGR: + op = "SUBE" + args[0], args[1] = args[1], args[0] + case MADBR: + op = "FMADD" + args[0], args[1], args[2] = args[1], args[2], args[0] + case VFM: + op = "WFMDB" + args[0], args[1], args[2] = args[1], args[2], args[0] + args = args[0:3] + case VFS: + op = "WFSDB" + args[0], args[2] = args[2], args[0] + args = args[0:3] + case MSGFR, MHI, MSFI, MSGFI: + switch inst.Op { + case MSGFR, MHI, MSFI: + op = "MULLW" + case MSGFI: + op = "MULLD" + } + args[0], args[1] = args[1], args[0] + + case NGR, NR, NILL, NILF, NILH, OGR, OR, OILL, OILF, OILH, XGR, XR, XILF: + op = bitwise_op(inst.Op) + args[0], args[1] = args[1], args[0] + switch inst.Op { + case NILL: + if int(inst.Args[1].(Sign16)) < 0 { + op = "ANDW" + } + + case NILF: + if int(inst.Args[1].(Sign32)) < 0 { + op = "AND" + } + case OILF: + if int(inst.Args[1].(Sign32)) < 0 { + op = "ORW" + } + case XILF: + if int(inst.Args[1].(Sign32)) < 0 { + op = "XORW" + } + } + + case NGRK, NRK, OGRK, ORK, XGRK, XRK: // opcode R1, R2, R3 + op = bitwise_op(inst.Op) + args[0], args[1], args[2] = args[1], args[2], args[0] + case SLLG, SRLG, SLLK, SRLK, RLL, RLLG, SRAK, SRAG: + switch inst.Op { + case SLLG: + op = "SLD" + case SRLG: + op = "SRD" + case SLLK: + op = "SLW" + case SRLK: + op = "SRW" + case SRAK: + op = "SRAW" + case SRAG: + op = "SRAD" + } + args[0], args[2] = args[2], args[0] + case TRAP2, SVC: + op = "SYSALL" + case CR, CLR, CGR, CLGR, KDBR, CDBR, CEBR, CGHI, CHI, CGFI, CLGFI, CFI, CLFI: + switch inst.Op { + case CGHI, CGFI, CGR: + op = "CMP" + case CHI, CFI, CR: + op = "CMPW" + case CLGFI, CLGR: + op = "CMPU" + case CLFI, CLR: + op = "CMPWU" + case CDBR: + op = "FCMPU" + case KDBR: + op = "FCMPO" + } + case CEFBRA, CDFBRA, CEGBRA, CDGBRA, CELFBR, CDLFBR, CELGBR, CDLGBR, CFEBRA, CFDBRA, CGEBRA, CGDBRA, CLFEBR, CLFDBR, CLGEBR, CLGDBR: + args[0], args[1] = args[2], args[0] + args = args[:2] + case CGRJ, CGIJ: + mask, err := strconv.Atoi(args[2][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + var check bool + switch mask & 0xf { + case 2: + op = "CMPBGT" + check = true + case 4: + op = "CMPBLT" + check = true + case 6: + op = "CMPBNE" + check = true + case 8: + op = "CMPBEQ" + check = true + case 10: + op = "CMPBGE" + check = true + case 12: + op = "CMPBLE" + check = true + } + if check { + args[2] = args[3] + args = args[:3] + } + case CLGRJ, CLGIJ: + mask, err := strconv.Atoi(args[2][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + var check bool + switch mask & 0xf { + case 2: + op = "CMPUBGT" + check = true + case 4: + op = "CMPUBLT" + check = true + case 7: + op = "CMPUBNE" + check = true + case 8: + op = "CMPUBEQ" + check = true + case 10: + op = "CMPUBGE" + check = true + case 12: + op = "CMPUBLE" + check = true + } + if check { + args[2] = args[3] + args = args[:3] + } + case CLRJ, CRJ, CIJ, CLIJ: + args[0], args[1], args[2] = args[2], args[0], args[1] + case BRC, BRCL: + mask, err := strconv.Atoi(args[0][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + opStr, check := branch_relative_op(mask, inst.Op) + if opStr != "" { + op = opStr + } + if check { + args[0] = args[1] + args = args[:1] + } + case BCR: + mask, err := strconv.Atoi(args[0][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + opStr := branchOnConditionOp(mask, inst.Op) + if opStr != "" { + op = opStr + } + if op == "SYNC" || op == "NOPH" { + return op + } + if op == "RET" { + args = args[:0] + return op + } + case LOCGR: + mask, err := strconv.Atoi(args[2][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + var check bool + switch mask & 0xf { + case 2: //Greaterthan (M=2) + op = "MOVDGT" + check = true + case 4: //Lessthan (M=4) + op = "MOVDLT" + check = true + case 7: // Not Equal (M=7) + op = "MOVDNE" + check = true + case 8: // Equal (M=8) + op = "MOVDEQ" + check = true + case 10: // Greaterthan or Equal (M=10) + op = "MOVDGE" + check = true + case 12: // Lessthan or Equal (M=12) + op = "MOVDLE" + check = true + } + if check { + args[0], args[1] = args[1], args[0] + args = args[:2] + } else { + args[0], args[2] = args[2], args[0] + } + case BRASL: + op = "CALL" // BL + args[0] = args[1] + args = args[:1] + case X, XY, XG: + switch inst.Op { + case X, XY: + op = "XORW" + case XG: + op = "XOR" + } + case N, NY, NG, O, OY, OG, XC, NC, OC, MVC, MVCIN, CLC: + switch inst.Op { + case N, NY: + op = "ANDW" + case NG: + op = "AND" + case O, OY: + op = "ORW" + case OG: + op = "OR" + } + args[0], args[1] = args[1], args[0] + case S, SY, SLBG, SLG, SG: + switch inst.Op { + case S, SY: + op = "SUBW" + case SLBG: + op = "SUBE" + case SLG: + op = "SUBC" + case SG: + op = "SUB" + } + args[0], args[1] = args[1], args[0] + case MSG, MSY, MS: + switch inst.Op { + case MSG: + op = "MULLD" + case MSY, MS: + op = "MULLW" + } + case A, AY, ALCG, ALG, AG: + switch inst.Op { + case A, AY: + op = "ADDW" + case ALCG: + op = "ADDE" + case ALG: + op = "ADDC" + case AG: + op = "ADD" + } + args[0], args[1] = args[1], args[0] + case RISBG, RISBGN, RISBHG, RISBLG, RNSBG, RXSBG, ROSBG: + switch inst.Op { + case RNSBG, RXSBG, ROSBG: + num, err := strconv.Atoi(args[2][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + if ((num >> 7) & 0x1) != 0 { + op = op + "T" + } + case RISBG, RISBGN, RISBHG, RISBLG: + num, err := strconv.Atoi(args[3][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + if ((num >> 7) & 0x1) != 0 { + op = op + "Z" + } + } + if len(args) == 5 { + args[0], args[1], args[2], args[3], args[4] = args[2], args[3], args[4], args[1], args[0] + } else { + args[0], args[1], args[2], args[3] = args[2], args[3], args[1], args[0] + } + + case VEC, VECL, VCLZ, VCTZ, VREPI, VPOPCT: //mnemonic V1, V2, M3 + mask, err := strconv.Atoi(args[2][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi for %q:%s", op, err) + } + val := mask & 0x7 + if val >= 0 && val < 4 { + op = op + vectorSize[val] + args = args[:2] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, mask) + } + switch inst.Op { + case VCLZ, VCTZ, VREPI, VPOPCT: + args[0], args[1] = args[1], args[0] + default: + } + //Mnemonic V1, V2, V3, M4 or Mnemonic V1, I2, I3, M4 or Mnemonic V1, V3, I2, M4 + case VA, VS, VACC, VAVG, VAVGL, VMX, VMXL, VMN, VMNL, VGFM, VGM, VREP, VERLLV, VESLV, VSCBI, VSUM, VSUMG, VSUMQ, VMH, VMLH, VML, VME, VMLE, VMO, VMLO: + mask, err := strconv.Atoi(args[3][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + val := mask & 0x7 + switch inst.Op { + case VA, VS, VACC, VSCBI: + if val >= 0 && val < 5 { + if args[0] == args[2] { + args[0], args[1] = args[1], args[0] + args = args[:2] + } else if inst.Op == VS { + if args[0] == args[1] { + args[0] = args[2] + args = args[:2] + } else { + args[0], args[2] = args[2], args[0] + args = args[:3] + } + } else { + args[0], args[1], args[2] = args[1], args[2], args[0] + args = args[:3] + } + op = op + vectorSize[val] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, mask) + } + case VAVG, VAVGL, VMX, VMXL, VMN, VMNL, VGFM, VGM: + if val >= 0 && val < 4 { + op = op + vectorSize[val] + args[0], args[1], args[2] = args[1], args[2], args[0] + args = args[:3] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, mask) + } + case VREP, VERLLV, VESLV: + if val >= 0 && val < 4 { + op = op + vectorSize[val] + args[0], args[2] = args[2], args[0] + args = args[:3] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, mask) + } + case VSUM, VSUMG, VSUMQ: + var off int + switch inst.Op { + case VSUM: + off = 0 + case VSUMG: + off = 1 + case VSUMQ: + off = 2 + } + if (val > (-1 + off)) && (val < (2 + off)) { + op = op + vectorSize[val] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, mask) + } + args = args[:3] + case VML, VMH, VMLH, VME, VMLE, VMO, VMLO: + if val >= 0 && val < 3 { + op = op + vectorSize[val] + } + if op == "VML" && val == 2 { + op = op + "W" + } + if args[0] == args[2] { + args[0], args[1] = args[1], args[0] + args = args[:2] + } else { + args[0], args[1], args[2] = args[1], args[2], args[0] + args = args[:3] + } + } + + case VGFMA, VERIM, VMAH, VMALH: // Mnemonic V1, V2, V3, V4/I4, M5 + mask, err := strconv.Atoi(args[4][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + val := mask & 0x7 + args = args[:4] + var off int + switch inst.Op { + case VMAH, VMALH: + off = -1 + } + + if val >= 0 && val < (4+off) { + op = op + vectorSize[val] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, mask) + } + switch inst.Op { + case VGFMA, VMAH, VMALH: + args[0], args[1], args[2], args[3] = args[1], args[2], args[3], args[0] + default: + args[0], args[3] = args[3], args[0] + } + case VSTRC, VFAE, VFEE, VFENE: + var off uint8 + switch inst.Op { + case VSTRC: + off = uint8(1) + default: + off = uint8(0) + } + m1, err := strconv.Atoi(args[3+off][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + m2, err := strconv.Atoi(args[4+off][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + index := m1 & 0x3 + if index < 0 || index > 2 { + return fmt.Sprintf("specification exception is recognized for %q with mask values: %v, %v \n", op, m1, m2) + } + switch m2 { + case 0: + op = op + vectorSize[index] + case 1: + op = op + vectorCS[index] + case 2: + op = op + "Z" + vectorSize[index] + case 3: + op = op + "Z" + vectorCS[index] + default: + return fmt.Sprintf("specification exception is recognized for %q with mask values: %v, %v \n", op, m1, m2) + } + switch inst.Op { + case VSTRC: + args[0], args[1], args[2], args[3] = args[1], args[2], args[3], args[0] + default: + args[0], args[1], args[2] = args[1], args[2], args[0] + } + args = args[:3+off] + + case VCEQ, VCH, VCHL: // Mnemonic V1, V2, V3, M4, M5 + m4, err := strconv.Atoi(args[3][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + m5, err := strconv.Atoi(args[4][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + val := (m4 & 0x7) + if m5 == 0 { + if val >= 0 && val < 4 { + op = op + vectorSize[val] + args[0], args[1], args[2] = args[1], args[2], args[0] + args = args[:3] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask(m4) value: %v \n", op, m4) + } + } else if m5 == 1 { + if val >= 0 && val < 4 { + op = op + vectorCS[val] + args[0], args[1], args[2] = args[1], args[2], args[0] + args = args[:3] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask(m4) value: %v \n", op, m4) + } + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask(m5) value: %v \n", op, m5) + } + case VFMA, VFMS, VMSL: //Mnemonic V1, V2, V3, V4, M5, M6 + m5, err := strconv.Atoi(args[4][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + m6, err := strconv.Atoi(args[5][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + switch inst.Op { + case VMSL: + if m5 == 3 && m6 == 8 { + op = op + "EG" + } else if m5 == 3 && m6 == 4 { + op = op + "OG" + } else if m5 == 3 && m6 == 12 { + op = op + "EOG" + } else if m5 == 3 { + op = op + "G" + } + default: + if m5 == 0 && m6 == 3 { + op = op + "DB" + } else if m5 == 8 && m6 == 3 { + op = "W" + op[1:] + "DB" + } else { + return fmt.Sprintf("specification exception is recognized for %q with m5: %v m6: %v \n", op, m5, m6) + } + } + args[0], args[1], args[2], args[3] = args[1], args[2], args[3], args[0] + args = args[:4] + + case VFCE, VFCH, VFCHE: //Mnemonic V1,V2,V3,M4,M5,M6 + m4, err := strconv.Atoi(args[3][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + m5, err := strconv.Atoi(args[4][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + m6, err := strconv.Atoi(args[5][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + if m5 == 0 { + if m4 == 3 && m6 == 0 { + op = op + "DB" + } else if m4 == 3 && m6 == 1 { + op = op + "DBS" + } else { + return fmt.Sprintf("specification exception is recognized for %q with m4: %v, m6: %v \n", op, m4, m6) + } + + } else if m5 == 8 { + if m4 == 3 && m6 == 0 { + op = "W" + op[1:] + "DB" + } else if m4 == 3 && m6 == 1 { + op = "W" + op[1:] + "DBS" + } else { + return fmt.Sprintf("specification exception is recognized for %q with m4: %v, m6: %v \n", op, m4, m6) + } + } else { + return fmt.Sprintf("specification exception is recognized for %q with m5: %v \n", op, m5) + } + args[0], args[1], args[2] = args[1], args[2], args[0] + args = args[:3] + + case VFTCI: + m4, err := strconv.Atoi(args[3][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + m5, err := strconv.Atoi(args[4][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: %q error in converting Atoi:%s", op, err) + } + val := (m4 & 0x7) + if m5 == 0 { + switch val { + case 2: + op = op + "SB" + case 3: + op = op + "DB" + default: + return fmt.Sprintf("specification exception is recognized for %q with mask(m4) value: %v \n", op, m4) + } + } else if m5 == 8 { + switch val { + case 2: + op = "W" + op[1:] + "SB" + case 3: + op = "W" + op[1:] + "DB" + case 4: + op = "W" + op[1:] + "XB" + default: + return fmt.Sprintf("specification exception is recognized for %q with mask(m4) value: %v \n", op, m4) + } + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask(m5) value: %v \n", op, m5) + } + args[0], args[2] = args[2], args[0] + args = args[:3] + case VAC, VACCC: + mask, err := strconv.Atoi(args[4][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + if mask&0x04 == 0 { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, mask) + } + op = op + "Q" + args[0], args[1], args[2], args[3] = args[1], args[2], args[3], args[0] + args = args[:4] + case VL, VLREP: + switch inst.Op { + case VL: + args[0], args[1] = args[1], args[0] + case VLREP: + args[0], args[1] = args[1], args[0] + mask, err := strconv.Atoi(args[2][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + if mask >= 0 && mask < 4 { + op = op + vectorSize[mask] + } + } + args = args[:2] + case VST, VSTEB, VSTEH, VSTEF, VSTEG, VLEB, VLEH, VLEF, VLEG: //Mnemonic V1, D2(X2,B2), M3 + m, err := strconv.Atoi(args[2][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + switch inst.Op { + case VST: + if m == 0 || (m > 2 && m < 5) { + args = args[:2] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, m) + } + case VLEB, VLEH, VLEF, VLEG: + args[0], args[2] = args[2], args[0] + default: + args[0], args[1], args[2] = args[2], args[0], args[1] + } + case VSTM, VSTL, VESL, VESRA, VLM, VERLL, VLVG: //Mnemonic V1, V3, D2(B2)[,M4] or V1, R3,D2(B2) + switch inst.Op { + case VSTM, VLM: + m, err := strconv.Atoi(args[3][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + if !(m == 0 || (m > 2 && m < 5)) { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, m) + } + if inst.Op == VLM { + args[0], args[1], args[2] = args[2], args[0], args[1] + } + args = args[:3] + case VESL, VESRA, VERLL, VLVG: + m, err := strconv.Atoi(args[3][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + if m >= 0 && m < 4 { + op = op + vectorSize[m] + } else { + return fmt.Sprintf("specification exception is recognized for %q with mask value: %v \n", op, m) + } + switch inst.Op { + case VLVG: + args[0], args[2] = args[2], args[0] + args = args[:3] + default: + if args[0] == args[1] { + args[0] = args[2] + args = args[:2] + break + } + args[0], args[2] = args[2], args[0] + args = args[:3] + } + case VSTL: + args[0], args[1] = args[1], args[0] + args = args[:3] + } + case VGBM: + val, err := strconv.Atoi(args[1][1:]) + if err != nil { + return fmt.Sprintf("GoSyntax: error in converting Atoi:%s", err) + } + if val == 0 { + op = "VZERO" + args = args[:1] + } else if val == 0xffff { + op = "VONE" + args = args[:1] + } else { + args[0], args[1] = args[1], args[0] + args = args[:2] + } + case VN, VNC, VO, VX, VNO: //mnemonic V1, V2, V3 + if args[0] == args[2] { + args = args[:2] + args[0], args[1] = args[1], args[0] + } else { + args[0], args[1], args[2] = args[1], args[2], args[0] + } + if op == "VNO" { + op = op + "T" + } + case VGEG, VGEF, VSCEG, VSCEF: //Mnemonic V1, D2(V2, B2), M3 + args[0], args[2] = args[2], args[0] + + } + if args != nil { + op += " " + strings.Join(args, ", ") + } + + return op +} + +// This function returns corresponding extended mnemonic for the given +// branch on relative mnemonic. +func branch_relative_op(mask int, opconst Op) (op string, check bool) { + switch mask & 0xf { + case 1: + op = "BVS" + check = true + case 2: + op = "BGT" + check = true + case 4: + op = "BLT" + check = true + case 5: + op = "BLTU" + check = true + case 7: + op = "BNE" + check = true + case 8: + op = "BEQ" + check = true + case 10: + op = "BGE" + check = true + case 12: + op = "BLE" + check = true + case 13: + op = "BLEU" + check = true + case 15: + op = "BR" + check = true + } + return op, check +} + +// This function returns corresponding extended mnemonic for the given +// brach on condition mnemonic. +func branchOnConditionOp(mask int, opconst Op) (op string) { + switch mask & 0xf { + case 0: + op = "NOPH" + case 14: + op = "SYNC" + case 15: + op = "RET" + } + return op +} + +// This function returns corresponding plan9 mnemonic for the native bitwise mnemonic. +func bitwise_op(op Op) string { + var ret string + switch op { + case NGR, NGRK, NILL: + ret = "AND" + case NR, NRK, NILH, NILF: + ret = "ANDW" + case OGR, OGRK, OILF: + ret = "OR" + case OR, ORK, OILH, OILL: + ret = "ORW" + case XGR, XGRK, XILF: + ret = "XOR" + case XR, XRK: + ret = "XORW" + } + return ret +} + +// This function parses memory operand of type D(B) +func mem_operand(args []string) string { + if args[0] != "" && args[1] != "" { + args[0] = fmt.Sprintf("%s(%s)", args[0], args[1]) + } else if args[0] != "" { + args[0] = fmt.Sprintf("$%s", args[0]) + } else if args[1] != "" { + args[0] = fmt.Sprintf("(%s)", args[1]) + } else { + args[0] = "" + } + return args[0] +} + +// This function parses memory operand of type D(X,B) +func mem_operandx(args []string) string { + if args[1] != "" && args[2] != "" { + args[1] = fmt.Sprintf("(%s)(%s*1)", args[2], args[1]) + } else if args[1] != "" { + args[1] = fmt.Sprintf("(%s)", args[1]) + } else if args[2] != "" { + args[1] = fmt.Sprintf("(%s)", args[2]) + } else if args[0] != "" { + args[1] = "" + } + if args[0] != "" && args[1] != "" { + args[0] = fmt.Sprintf("%s%s", args[0], args[1]) + } else if args[0] != "" { + args[0] = fmt.Sprintf("$%s", args[0]) + } else if args[1] != "" { + args[0] = fmt.Sprintf("%s", args[1]) + } else { + args[0] = "" + } + return args[0] +} + +// This function parses memory operand of type D(V,B) +func mem_operandv(args []string) string { + if args[1] != "" && args[2] != "" { + args[1] = fmt.Sprintf("(%s)(%s*1)", args[2], args[1]) + } else if args[1] != "" { + args[1] = fmt.Sprintf("(%s*1)", args[1]) + } else if args[2] != "" { + args[1] = fmt.Sprintf("(%s)", args[2]) + } else if args[0] != "" { + args[1] = "" + } + if args[0] != "" && args[1] != "" { + args[0] = fmt.Sprintf("%s%s", args[0], args[1]) + } else if args[0] != "" { + args[0] = fmt.Sprintf("$%s", args[0]) + } else if args[1] != "" { + args[0] = fmt.Sprintf("%s", args[1]) + } else { + args[0] = "" + } + return args[0] +} + +// This function parses memory operand of type D(L,B) +func mem_operandl(args []string) (string, string) { + if args[0] != "" && args[2] != "" { + args[0] = fmt.Sprintf("%s(%s)", args[0], args[2]) + } else if args[2] != "" { + args[0] = fmt.Sprintf("(%s)", args[2]) + } else { + args[0] = fmt.Sprintf("%s", args[0]) + } + return args[0], args[1] +} + +// plan9Arg formats arg (which is the argIndex's arg in inst) according to Plan 9 rules. +// NOTE: because Plan9Syntax is the only caller of this func, and it receives a copy +// of inst, it's ok to modify inst.Args here. +func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg Arg) string { + switch arg.(type) { + case Reg: + if arg == R13 { + return "g" + } + return strings.ToUpper(arg.String(pc)[1:]) + case Base: + if arg == R13 { + return "g" + } + s := arg.String(pc) + if s != "" { + return strings.ToUpper(s[1 : len(s)-1]) + } + return "R0" + case Index: + if arg == R13 { + return "g" + } + s := arg.String(pc) + if s != "" { + return strings.ToUpper(s[1:]) + } + return "" + case VReg: + return strings.ToUpper(arg.String(pc)[1:]) + case Disp20, Disp12: + numstr := arg.String(pc) + num, err := strconv.Atoi(numstr[:len(numstr)]) + if err != nil { + return fmt.Sprintf("plan9Arg: error in converting Atoi:%s", err) + } + if num == 0 { + return "" + } else { + return strconv.Itoa(num) + } + case RegIm12, RegIm16, RegIm24, RegIm32: + addr, err := strconv.ParseUint(arg.String(pc)[2:], 16, 64) + if err != nil { + return fmt.Sprintf("plan9Arg: error in converting ParseUint:%s", err) + } + off := int(addr - pc) + s, base := symname(addr) + if s != "" && addr == base { + return fmt.Sprintf("%s(SB)", s) + } + off = off / inst.Len + return fmt.Sprintf("%v(PC)", off) + case Imm, Sign8, Sign16, Sign32: + numImm := arg.String(pc) + switch arg.(type) { + case Sign32, Sign16, Imm: + num, err := strconv.ParseInt(numImm, 10, 64) + if err != nil { + return fmt.Sprintf("plan9Arg: error in converting ParseInt:%s", err) + } + switch inst.Op { + case LLIHF: + num = num << 32 + case LLILH: + num = num << 16 + case NILH: + num = (num << 16) | int64(0xFFFF) + case OILH: + num = num << 16 + } + numImm = fmt.Sprintf("%d", num) + } + return fmt.Sprintf("$%s", numImm) + case Mask, Len: + num := arg.String(pc) + return fmt.Sprintf("$%s", num) + } + return fmt.Sprintf("???(%v)", arg) +} + +// It checks any 2 args of given instructions to swap or not +func reverseOperandOrder(op Op) bool { + switch op { + case LOCR, MLGR: + return true + case LTEBR, LTDBR, LCDBR, LGDR: + return true + case VLEIB, VLEIH, VLEIF, VLEIG, VPDI: + return true + case VSLDB: + return true + } + return false +} + +// It checks whether to reverse all the args of given mnemonic or not +func reverseAllOperands(op Op) bool { + switch op { + case VLVGP: //3-operand list + return true + case VSEL, VPERM: //4-Operand list + return true + } + return false +} diff --git a/s390x/s390xasm/tables.go b/s390x/s390xasm/tables.go new file mode 100644 index 00000000..5a66c1fe --- /dev/null +++ b/s390x/s390xasm/tables.go @@ -0,0 +1,5047 @@ +// Code generated by s390xmap -fmt=decoder ../s390x.csv DO NOT EDIT. + +package s390xasm + +const ( + _ Op = iota + A + AR + ARK + AY + AG + AGR + AGRK + AGF + AGFR + AXBR + AXTR + AXTRA + ADB + ADBR + ADTR + ADTRA + AEB + AEBR + AP + AH + AHY + AGH + AHI + AGHI + AHHHR + AHHLR + AFI + AHIK + ASI + AGHIK + AGFI + AGSI + AIH + AL + ALR + ALRK + ALY + ALG + ALGR + ALGRK + ALGF + ALGFR + ALHHHR + ALHHLR + ALFI + ALGFI + ALC + ALCR + ALCG + ALCGR + ALHSIK + ALSI + ALGHSIK + ALGSI + ALSIH + ALSIHN + AXR + AD + ADR + AE + AER + AW + AWR + AU + AUR + N + NR + NRK + NY + NG + NGR + NGRK + NC + NI + NIY + NIHH + NIHL + NIHF + NILH + NILL + NILF + NCRK + NCGRK + BAL + BALR + BAS + BASR + BASSM + BSA + BSM + BAKR + BSG + BIC + BC + BCR + BCT + BCTR + BCTG + BCTGR + BXH + BXHG + BXLE + BXLEG + BPP + BPRP + BRAS + BRASL + BRC + BRCL + BRCT + BRCTG + BRCTH + BRXH + BRXHG + BRXLE + BRXLG + XSCH + CKSM + KM + KMA + KMC + KMF + KMCTR + KMO + CSCH + C + CR + CY + CG + CGR + CGF + CGFR + CXBR + CXTR + CXR + CDB + CDBR + CDTR + CD + CDR + CEB + CEBR + CE + CER + CRB + CGRB + CRJ + CGRJ + CFC + CRDTE + KXBR + KXTR + KDB + KDBR + KDTR + KEB + KEBR + CS + CSY + CSG + CSP + CSPG + CSST + CRT + CGRT + CEXTR + CEDTR + CP + CDS + CDSY + CDSG + CH + CHY + CGH + CHHSI + CHI + CHSI + CGHI + CGHSI + CHRL + CGHRL + CHF + CHHR + CHLR + CFI + CGFI + CIB + CGIB + CIJ + CGIJ + CIT + CGIT + CIH + CL + CLR + CLY + CLG + CLGR + CLGF + CLGFR + CLC + CLI + CLIY + CLRB + CLGRB + CLRJ + CLGRJ + CLRT + CLT + CLGRT + CLGT + CLMH + CLM + CLMY + CLHF + CLHHR + CLHLR + CLHHSI + CLFI + CLFHSI + CLGHSI + CLGFI + CLIB + CLGIB + CLIJ + CLGIJ + CLFIT + CLGIT + CLIH + CLCL + CLCLE + CLCLU + CLRL + CLHRL + CLGRL + CLGHRL + CLGFRL + CLST + CRL + CGRL + CGFRL + CUSE + CMPSC + KDSA + KIMD + KLMD + KMAC + THDR + THDER + CXFBR + CXFBRA + CXFTR + CXFR + CDFBR + CDFBRA + CDFTR + CDFR + CEFBR + CEFBRA + CEFR + CXGBR + CXGBRA + CXGTR + CXGTRA + CXGR + CDGBR + CDGBRA + CDGTR + CDGTRA + CDGR + CEGBR + CEGBRA + CEGR + CXLFBR + CXLFTR + CDLFBR + CDLFTR + CELFBR + CXLGBR + CXLGTR + CDLGBR + CDLGTR + CELGBR + CXPT + CDPT + CXSTR + CDSTR + CXUTR + CDUTR + CXZT + CDZT + TBEDR + TBDR + CVB + CVBY + CVBG + CVD + CVDY + CVDG + CFXBR + CFXBRA + CGXBR + CGXBRA + CFXTR + CGXTR + CGXTRA + CFXR + CGXR + CFDBR + CFDBRA + CGDBR + CGDBRA + CFDTR + CGDTR + CGDTRA + CFDR + CGDR + CFEBR + CFEBRA + CGEBR + CGEBRA + CFER + CGER + CLFXBR + CLGXBR + CLFXTR + CLGXTR + CLFDBR + CLGDBR + CLFDTR + CLGDTR + CLFEBR + CLGEBR + CPXT + CPDT + CSXTR + CSDTR + CUXTR + CUDTR + CZXT + CZDT + CU24 + CU21 + CU12 + CU14 + CU42 + CU41 + CPYA + CPSDR + VSCSHP + VSCHP + DFLTCC + D + DR + DXBR + DXTR + DXTRA + DXR + DDB + DDBR + DDTR + DDTRA + DD + DDR + DEB + DEBR + DE + DER + DP + DL + DLR + DLG + DLGR + DSG + DSGR + DSGF + DSGFR + DIDBR + DIEBR + ED + EDMK + X + XR + XRK + XY + XG + XGR + XGRK + XC + XI + XIY + XIHF + XILF + EX + EXRL + EAR + ESEA + EEXTR + EEDTR + ECAG + ECTG + EFPC + EPAR + EPAIR + EPSW + ESAR + ESAIR + ESXTR + ESDTR + EREG + EREGG + ESTA + ETND + FLOGR + HSCH + HDR + HER + IAC + IEXTR + IEDTR + IC + ICY + ICMH + ICM + ICMY + IIHH + IIHL + IIHF + IILH + IILL + IILF + IPM + IPK + IRBM + ISKE + IVSK + IDTE + IPTE + L + LR + LY + LG + LGR + LGF + LGFR + LXR + LD + LDR + LDY + LE + LER + LEY + LAM + LAMY + LA + LAY + LAE + LAEY + LARL + LASP + LAA + LAAG + LAAL + LAALG + LAN + LANG + LAX + LAXG + LAO + LAOG + LT + LTR + LTG + LTGR + LTGF + LTGFR + LTXBR + LTXTR + LTXR + LTDBR + LTDTR + LTDR + LTEBR + LTER + LAT + LGAT + LZRF + LZRG + LBEAR + LB + LBR + LGB + LGBR + LBH + LCR + LCGR + LCGFR + LCXBR + LCXR + LCDBR + LCDR + LCDFR + LCEBR + LCER + LCTL + LCTLG + LCBB + FIXBR + FIXBRA + FIXTR + FIXR + FIDBR + FIDBRA + FIDTR + FIDR + FIEBR + FIEBRA + FIER + LFPC + LFAS + LDGR + LGDR + LGG + LGSC + LH + LHR + LHY + LGH + LGHR + LHH + LOCHHI + LHI + LGHI + LOCHI + LOCGHI + LHRL + LGHRL + LFH + LFHAT + LOCFH + LOCFHR + LGFI + LXDB + LXDBR + LXDTR + LXD + LXDR + LXEB + LXEBR + LXE + LXER + LDEB + LDEBR + LDETR + LDE + LDER + LLGF + LLGFR + LLGFSG + LLGFAT + LLZRGF + LLC + LLCR + LLGC + LLGCR + LLCH + LLH + LLHR + LLGH + LLGHR + LLHH + LLHRL + LLGHRL + LLIHH + LLIHL + LLIHF + LLILH + LLILL + LLILF + LLGFRL + LLGT + LLGTR + LLGTAT + LM + LMY + LMG + LMD + LMH + LNR + LNGR + LNGFR + LNXBR + LNXR + LNDBR + LNDR + LNDFR + LNEBR + LNER + LOC + LOCR + LOCG + LOCGR + LPTEA + LPD + LPDG + LPQ + LPR + LPGR + LPGFR + LPXBR + LPXR + LPDBR + LPDR + LPDFR + LPEBR + LPER + LPSW + LPSWE + LPSWEY + LRA + LRAY + LRAG + LRL + LGRL + LGFRL + LRVH + LRV + LRVR + LRVG + LRVGR + LDXBR + LDXBRA + LDXTR + LDXR + LRDR + LEXBR + LEXBRA + LEXR + LEDBR + LEDBRA + LEDTR + LEDR + LRER + LURA + LURAG + LZXR + LZDR + LZER + MSTA + MSCH + MC + MVHHI + MVHI + MVGHI + MVC + MVI + MVIY + MVCIN + MVCL + MVCLE + MVCLU + MVN + MVPG + MVCRL + MVST + MVCP + MVCS + MVCDK + MVCK + MVO + MVCOS + MVCSK + MVZ + MG + MGRK + M + MFY + MR + MXBR + MXTR + MXTRA + MXR + MDB + MDBR + MDTR + MDTRA + MD + MDR + MXDB + MXDBR + MXD + MXDR + MEEB + MEEBR + MEE + MEER + MDEB + MDEBR + MDE + MDER + ME + MER + MAY + MAYR + MADB + MADBR + MAD + MADR + MAEB + MAEBR + MAE + MAER + MAYH + MAYHR + MAYL + MAYLR + MSDB + MSDBR + MSD + MSDR + MSEB + MSEBR + MSE + MSER + MP + MH + MHY + MGH + MHI + MGHI + MLG + MLGR + ML + MLR + MS + MSC + MSR + MSRKC + MSY + MSG + MSGC + MSGR + MSGRKC + MSGF + MSGFR + MSFI + MSGFI + MYH + MYHR + MYL + MYLR + MY + MYR + NNRK + NNGRK + NNPA + NIAI + NTSTG + NORK + NOGRK + NXRK + NXGRK + O + OR + ORK + OY + OG + OGR + OGRK + OC + OI + OIY + OIHH + OIHL + OIHF + OILH + OILL + OILF + OCRK + OCGRK + PACK + PKA + PKU + PGIN + PGOUT + PCC + PCKMO + PFPO + PFMF + PLO + PPA + PRNO + PTFF + PTF + POPCNT + PFD + PFDRL + PC + PR + PT + PTI + PALB + PTLB + QAXTR + QADTR + QPACI + RRXTR + RRDTR + RCHP + RDP + RRBE + RRBM + RP + RSCH + RLL + RLLG + RNSBG + RXSBG + RISBG + RISBGN + RISBHG + RISBLG + ROSBG + SRST + SRSTU + SELR + SELGR + SELFHR + SAR + SAL + SAC + SACF + SAM24 + SAM31 + SAM64 + SRNM + SRNMB + SCHM + SCK + SCKC + SCKPF + SPT + SRNMT + SFPC + SFASR + SPX + SPM + SPKA + SSAR + SSAIR + SSKE + SSM + SRP + SLDA + SLDL + SLA + SLAK + SLAG + SLL + SLLK + SLLG + SRDA + SRDL + SRA + SRAK + SRAG + SRL + SRLK + SRLG + SLXT + SLDT + SRXT + SRDT + SIGP + SORTL + SQXBR + SQXR + SQDB + SQDBR + SQD + SQDR + SQEB + SQEBR + SQE + SQER + SSCH + ST + STY + STG + STD + STDY + STE + STEY + STAM + STAMY + STBEAR + STCPS + STCRW + STC + STCY + STCH + STCMH + STCM + STCMY + STCK + STCKC + STCKE + STCKF + STCTL + STCTG + STAP + STIDP + STPT + STFL + STFLE + STFPC + STGSC + STH + STHY + STHH + STHRL + STFH + STOCFH + STM + STMY + STMG + STMH + STOC + STOCG + STPQ + STPX + STRAG + STRL + STGRL + STRVH + STRV + STRVG + STSCH + STSI + STNSM + STOSM + STURA + STURG + S + SR + SRK + SY + SG + SGR + SGRK + SGF + SGFR + SXBR + SXTR + SXTRA + SDB + SDBR + SDTR + SDTRA + SEB + SEBR + SP + SH + SHY + SGH + SHHHR + SHHLR + SL + SLR + SLRK + SLY + SLG + SLGR + SLGRK + SLGF + SLGFR + SLHHHR + SLHHLR + SLFI + SLGFI + SLB + SLBR + SLBG + SLBGR + SXR + SD + SDR + SE + SER + SW + SWR + SU + SUR + SVC + TAR + TAM + TS + TB + TCXB + TDCXT + TCDB + TDCDT + TCEB + TDCET + TDGXT + TDGDT + TDGET + TP + TPEI + TPI + TPROT + TSCH + TM + TMY + TMHH + TMHL + TMLH + TMLL + TMH + TML + TRACE + TRACG + TABORT + TBEGINC + TBEGIN + TEND + TR + TRT + TRTE + TRTR + TRTRE + TRE + TROO + TROT + TRTO + TRTT + TRAP2 + TRAP4 + UNPK + UNPKA + UNPKU + UPT + VA + VACC + VAP + VAC + VACCC + VN + VNC + VAVG + VAVGL + VBPERM + VCKSM + VCP + VCEQ + VCH + VCHL + VCSPH + VCVB + VCVBG + VCVD + VCVDG + VCLZDP + VCLZ + VCTZ + VDP + VEC + VECL + VERIM + VERLL + VERLLV + VESLV + VESL + VESRA + VESRAV + VESRL + VESRLV + VX + VFAE + VFEE + VFENE + VFA + WFK + VFCE + VFCH + VFCHE + WFC + VCLFNH + VCLFNL + VCRNF + VCFPS + VCDG + VCFPL + VCDLG + VCFN + VCSFP + VCGD + VCLFP + VCLGD + VCNF + VFD + VFLL + VFLR + VFMAX + VFMIN + VFM + VFMA + VFMS + VFNMA + VFNMS + VFPSO + VFSQ + VFS + VFTCI + VGFM + VGFMA + VGEF + VGEG + VGBM + VGM + VISTR + VL + VLR + VLREP + VLEBRH + VLEBRF + VLEBRG + VLBRREP + VLLEBRZ + VLBR + VLC + VLEH + VLEF + VLEG + VLEB + VLEIH + VLEIF + VLEIG + VLEIB + VLER + VFI + VLGV + VLIP + VLLEZ + VLM + VLP + VLRL + VLRLR + VLBB + VLVG + VLVGP + VLL + VMX + VMXL + VMRH + VMRL + VMN + VMNL + VMAE + VMAH + VMALE + VMALH + VMALO + VMAL + VMAO + VMSP + VMP + VME + VMH + VMLE + VMLH + VMLO + VML + VMO + VMSL + VNN + VNO + VNX + VO + VOC + VPK + VPKLS + VPKS + VPKZ + VPKZR + VPSOP + VPERM + VPDI + VPOPCT + VRP + VREP + VREPI + VSCEF + VSCEG + VSEL + VSDP + VSRP + VSRPR + VSL + VSLB + VSLD + VSLDB + VSRA + VSRAB + VSRD + VSRL + VSRLB + VSEG + VST + VSTEBRH + VSTEBRF + VSTEBRG + VSTBR + VSTEH + VSTEF + VSTEG + VSTEB + VSTER + VSTM + VSTRL + VSTRLR + VSTL + VSTRC + VSTRS + VS + VSCBI + VSP + VSBCBI + VSBI + VSUMG + VSUMQ + VSUM + VTP + VTM + VUPH + VUPLH + VUPLL + VUPL + VUPKZ + VUPKZH + VUPKZL + ZAP +) + +var opstr = [...]string{ + A: "a", + AR: "ar", + ARK: "ark", + AY: "ay", + AG: "ag", + AGR: "agr", + AGRK: "agrk", + AGF: "agf", + AGFR: "agfr", + AXBR: "axbr", + AXTR: "axtr", + AXTRA: "axtra", + ADB: "adb", + ADBR: "adbr", + ADTR: "adtr", + ADTRA: "adtra", + AEB: "aeb", + AEBR: "aebr", + AP: "ap", + AH: "ah", + AHY: "ahy", + AGH: "agh", + AHI: "ahi", + AGHI: "aghi", + AHHHR: "ahhhr", + AHHLR: "ahhlr", + AFI: "afi", + AHIK: "ahik", + ASI: "asi", + AGHIK: "aghik", + AGFI: "agfi", + AGSI: "agsi", + AIH: "aih", + AL: "al", + ALR: "alr", + ALRK: "alrk", + ALY: "aly", + ALG: "alg", + ALGR: "algr", + ALGRK: "algrk", + ALGF: "algf", + ALGFR: "algfr", + ALHHHR: "alhhhr", + ALHHLR: "alhhlr", + ALFI: "alfi", + ALGFI: "algfi", + ALC: "alc", + ALCR: "alcr", + ALCG: "alcg", + ALCGR: "alcgr", + ALHSIK: "alhsik", + ALSI: "alsi", + ALGHSIK: "alghsik", + ALGSI: "algsi", + ALSIH: "alsih", + ALSIHN: "alsihn", + AXR: "axr", + AD: "ad", + ADR: "adr", + AE: "ae", + AER: "aer", + AW: "aw", + AWR: "awr", + AU: "au", + AUR: "aur", + N: "n", + NR: "nr", + NRK: "nrk", + NY: "ny", + NG: "ng", + NGR: "ngr", + NGRK: "ngrk", + NC: "nc", + NI: "ni", + NIY: "niy", + NIHH: "nihh", + NIHL: "nihl", + NIHF: "nihf", + NILH: "nilh", + NILL: "nill", + NILF: "nilf", + NCRK: "ncrk", + NCGRK: "ncgrk", + BAL: "bal", + BALR: "balr", + BAS: "bas", + BASR: "basr", + BASSM: "bassm", + BSA: "bsa", + BSM: "bsm", + BAKR: "bakr", + BSG: "bsg", + BIC: "bic", + BC: "bc", + BCR: "bcr", + BCT: "bct", + BCTR: "bctr", + BCTG: "bctg", + BCTGR: "bctgr", + BXH: "bxh", + BXHG: "bxhg", + BXLE: "bxle", + BXLEG: "bxleg", + BPP: "bpp", + BPRP: "bprp", + BRAS: "bras", + BRASL: "brasl", + BRC: "brc", + BRCL: "brcl", + BRCT: "brct", + BRCTG: "brctg", + BRCTH: "brcth", + BRXH: "brxh", + BRXHG: "brxhg", + BRXLE: "brxle", + BRXLG: "brxlg", + XSCH: "xsch", + CKSM: "cksm", + KM: "km", + KMA: "kma", + KMC: "kmc", + KMF: "kmf", + KMCTR: "kmctr", + KMO: "kmo", + CSCH: "csch", + C: "c", + CR: "cr", + CY: "cy", + CG: "cg", + CGR: "cgr", + CGF: "cgf", + CGFR: "cgfr", + CXBR: "cxbr", + CXTR: "cxtr", + CXR: "cxr", + CDB: "cdb", + CDBR: "cdbr", + CDTR: "cdtr", + CD: "cd", + CDR: "cdr", + CEB: "ceb", + CEBR: "cebr", + CE: "ce", + CER: "cer", + CRB: "crb", + CGRB: "cgrb", + CRJ: "crj", + CGRJ: "cgrj", + CFC: "cfc", + CRDTE: "crdte", + KXBR: "kxbr", + KXTR: "kxtr", + KDB: "kdb", + KDBR: "kdbr", + KDTR: "kdtr", + KEB: "keb", + KEBR: "kebr", + CS: "cs", + CSY: "csy", + CSG: "csg", + CSP: "csp", + CSPG: "cspg", + CSST: "csst", + CRT: "crt", + CGRT: "cgrt", + CEXTR: "cextr", + CEDTR: "cedtr", + CP: "cp", + CDS: "cds", + CDSY: "cdsy", + CDSG: "cdsg", + CH: "ch", + CHY: "chy", + CGH: "cgh", + CHHSI: "chhsi", + CHI: "chi", + CHSI: "chsi", + CGHI: "cghi", + CGHSI: "cghsi", + CHRL: "chrl", + CGHRL: "cghrl", + CHF: "chf", + CHHR: "chhr", + CHLR: "chlr", + CFI: "cfi", + CGFI: "cgfi", + CIB: "cib", + CGIB: "cgib", + CIJ: "cij", + CGIJ: "cgij", + CIT: "cit", + CGIT: "cgit", + CIH: "cih", + CL: "cl", + CLR: "clr", + CLY: "cly", + CLG: "clg", + CLGR: "clgr", + CLGF: "clgf", + CLGFR: "clgfr", + CLC: "clc", + CLI: "cli", + CLIY: "cliy", + CLRB: "clrb", + CLGRB: "clgrb", + CLRJ: "clrj", + CLGRJ: "clgrj", + CLRT: "clrt", + CLT: "clt", + CLGRT: "clgrt", + CLGT: "clgt", + CLMH: "clmh", + CLM: "clm", + CLMY: "clmy", + CLHF: "clhf", + CLHHR: "clhhr", + CLHLR: "clhlr", + CLHHSI: "clhhsi", + CLFI: "clfi", + CLFHSI: "clfhsi", + CLGHSI: "clghsi", + CLGFI: "clgfi", + CLIB: "clib", + CLGIB: "clgib", + CLIJ: "clij", + CLGIJ: "clgij", + CLFIT: "clfit", + CLGIT: "clgit", + CLIH: "clih", + CLCL: "clcl", + CLCLE: "clcle", + CLCLU: "clclu", + CLRL: "clrl", + CLHRL: "clhrl", + CLGRL: "clgrl", + CLGHRL: "clghrl", + CLGFRL: "clgfrl", + CLST: "clst", + CRL: "crl", + CGRL: "cgrl", + CGFRL: "cgfrl", + CUSE: "cuse", + CMPSC: "cmpsc", + KDSA: "kdsa", + KIMD: "kimd", + KLMD: "klmd", + KMAC: "kmac", + THDR: "thdr", + THDER: "thder", + CXFBR: "cxfbr", + CXFBRA: "cxfbra", + CXFTR: "cxftr", + CXFR: "cxfr", + CDFBR: "cdfbr", + CDFBRA: "cdfbra", + CDFTR: "cdftr", + CDFR: "cdfr", + CEFBR: "cefbr", + CEFBRA: "cefbra", + CEFR: "cefr", + CXGBR: "cxgbr", + CXGBRA: "cxgbra", + CXGTR: "cxgtr", + CXGTRA: "cxgtra", + CXGR: "cxgr", + CDGBR: "cdgbr", + CDGBRA: "cdgbra", + CDGTR: "cdgtr", + CDGTRA: "cdgtra", + CDGR: "cdgr", + CEGBR: "cegbr", + CEGBRA: "cegbra", + CEGR: "cegr", + CXLFBR: "cxlfbr", + CXLFTR: "cxlftr", + CDLFBR: "cdlfbr", + CDLFTR: "cdlftr", + CELFBR: "celfbr", + CXLGBR: "cxlgbr", + CXLGTR: "cxlgtr", + CDLGBR: "cdlgbr", + CDLGTR: "cdlgtr", + CELGBR: "celgbr", + CXPT: "cxpt", + CDPT: "cdpt", + CXSTR: "cxstr", + CDSTR: "cdstr", + CXUTR: "cxutr", + CDUTR: "cdutr", + CXZT: "cxzt", + CDZT: "cdzt", + TBEDR: "tbedr", + TBDR: "tbdr", + CVB: "cvb", + CVBY: "cvby", + CVBG: "cvbg", + CVD: "cvd", + CVDY: "cvdy", + CVDG: "cvdg", + CFXBR: "cfxbr", + CFXBRA: "cfxbra", + CGXBR: "cgxbr", + CGXBRA: "cgxbra", + CFXTR: "cfxtr", + CGXTR: "cgxtr", + CGXTRA: "cgxtra", + CFXR: "cfxr", + CGXR: "cgxr", + CFDBR: "cfdbr", + CFDBRA: "cfdbra", + CGDBR: "cgdbr", + CGDBRA: "cgdbra", + CFDTR: "cfdtr", + CGDTR: "cgdtr", + CGDTRA: "cgdtra", + CFDR: "cfdr", + CGDR: "cgdr", + CFEBR: "cfebr", + CFEBRA: "cfebra", + CGEBR: "cgebr", + CGEBRA: "cgebra", + CFER: "cfer", + CGER: "cger", + CLFXBR: "clfxbr", + CLGXBR: "clgxbr", + CLFXTR: "clfxtr", + CLGXTR: "clgxtr", + CLFDBR: "clfdbr", + CLGDBR: "clgdbr", + CLFDTR: "clfdtr", + CLGDTR: "clgdtr", + CLFEBR: "clfebr", + CLGEBR: "clgebr", + CPXT: "cpxt", + CPDT: "cpdt", + CSXTR: "csxtr", + CSDTR: "csdtr", + CUXTR: "cuxtr", + CUDTR: "cudtr", + CZXT: "czxt", + CZDT: "czdt", + CU24: "cu24", + CU21: "cu21", + CU12: "cu12", + CU14: "cu14", + CU42: "cu42", + CU41: "cu41", + CPYA: "cpya", + CPSDR: "cpsdr", + VSCSHP: "vscshp", + VSCHP: "vschp", + DFLTCC: "dfltcc", + D: "d", + DR: "dr", + DXBR: "dxbr", + DXTR: "dxtr", + DXTRA: "dxtra", + DXR: "dxr", + DDB: "ddb", + DDBR: "ddbr", + DDTR: "ddtr", + DDTRA: "ddtra", + DD: "dd", + DDR: "ddr", + DEB: "deb", + DEBR: "debr", + DE: "de", + DER: "der", + DP: "dp", + DL: "dl", + DLR: "dlr", + DLG: "dlg", + DLGR: "dlgr", + DSG: "dsg", + DSGR: "dsgr", + DSGF: "dsgf", + DSGFR: "dsgfr", + DIDBR: "didbr", + DIEBR: "diebr", + ED: "ed", + EDMK: "edmk", + X: "x", + XR: "xr", + XRK: "xrk", + XY: "xy", + XG: "xg", + XGR: "xgr", + XGRK: "xgrk", + XC: "xc", + XI: "xi", + XIY: "xiy", + XIHF: "xihf", + XILF: "xilf", + EX: "ex", + EXRL: "exrl", + EAR: "ear", + ESEA: "esea", + EEXTR: "eextr", + EEDTR: "eedtr", + ECAG: "ecag", + ECTG: "ectg", + EFPC: "efpc", + EPAR: "epar", + EPAIR: "epair", + EPSW: "epsw", + ESAR: "esar", + ESAIR: "esair", + ESXTR: "esxtr", + ESDTR: "esdtr", + EREG: "ereg", + EREGG: "eregg", + ESTA: "esta", + ETND: "etnd", + FLOGR: "flogr", + HSCH: "hsch", + HDR: "hdr", + HER: "her", + IAC: "iac", + IEXTR: "iextr", + IEDTR: "iedtr", + IC: "ic", + ICY: "icy", + ICMH: "icmh", + ICM: "icm", + ICMY: "icmy", + IIHH: "iihh", + IIHL: "iihl", + IIHF: "iihf", + IILH: "iilh", + IILL: "iill", + IILF: "iilf", + IPM: "ipm", + IPK: "ipk", + IRBM: "irbm", + ISKE: "iske", + IVSK: "ivsk", + IDTE: "idte", + IPTE: "ipte", + L: "l", + LR: "lr", + LY: "ly", + LG: "lg", + LGR: "lgr", + LGF: "lgf", + LGFR: "lgfr", + LXR: "lxr", + LD: "ld", + LDR: "ldr", + LDY: "ldy", + LE: "le", + LER: "ler", + LEY: "ley", + LAM: "lam", + LAMY: "lamy", + LA: "la", + LAY: "lay", + LAE: "lae", + LAEY: "laey", + LARL: "larl", + LASP: "lasp", + LAA: "laa", + LAAG: "laag", + LAAL: "laal", + LAALG: "laalg", + LAN: "lan", + LANG: "lang", + LAX: "lax", + LAXG: "laxg", + LAO: "lao", + LAOG: "laog", + LT: "lt", + LTR: "ltr", + LTG: "ltg", + LTGR: "ltgr", + LTGF: "ltgf", + LTGFR: "ltgfr", + LTXBR: "ltxbr", + LTXTR: "ltxtr", + LTXR: "ltxr", + LTDBR: "ltdbr", + LTDTR: "ltdtr", + LTDR: "ltdr", + LTEBR: "ltebr", + LTER: "lter", + LAT: "lat", + LGAT: "lgat", + LZRF: "lzrf", + LZRG: "lzrg", + LBEAR: "lbear", + LB: "lb", + LBR: "lbr", + LGB: "lgb", + LGBR: "lgbr", + LBH: "lbh", + LCR: "lcr", + LCGR: "lcgr", + LCGFR: "lcgfr", + LCXBR: "lcxbr", + LCXR: "lcxr", + LCDBR: "lcdbr", + LCDR: "lcdr", + LCDFR: "lcdfr", + LCEBR: "lcebr", + LCER: "lcer", + LCTL: "lctl", + LCTLG: "lctlg", + LCBB: "lcbb", + FIXBR: "fixbr", + FIXBRA: "fixbra", + FIXTR: "fixtr", + FIXR: "fixr", + FIDBR: "fidbr", + FIDBRA: "fidbra", + FIDTR: "fidtr", + FIDR: "fidr", + FIEBR: "fiebr", + FIEBRA: "fiebra", + FIER: "fier", + LFPC: "lfpc", + LFAS: "lfas", + LDGR: "ldgr", + LGDR: "lgdr", + LGG: "lgg", + LGSC: "lgsc", + LH: "lh", + LHR: "lhr", + LHY: "lhy", + LGH: "lgh", + LGHR: "lghr", + LHH: "lhh", + LOCHHI: "lochhi", + LHI: "lhi", + LGHI: "lghi", + LOCHI: "lochi", + LOCGHI: "locghi", + LHRL: "lhrl", + LGHRL: "lghrl", + LFH: "lfh", + LFHAT: "lfhat", + LOCFH: "locfh", + LOCFHR: "locfhr", + LGFI: "lgfi", + LXDB: "lxdb", + LXDBR: "lxdbr", + LXDTR: "lxdtr", + LXD: "lxd", + LXDR: "lxdr", + LXEB: "lxeb", + LXEBR: "lxebr", + LXE: "lxe", + LXER: "lxer", + LDEB: "ldeb", + LDEBR: "ldebr", + LDETR: "ldetr", + LDE: "lde", + LDER: "lder", + LLGF: "llgf", + LLGFR: "llgfr", + LLGFSG: "llgfsg", + LLGFAT: "llgfat", + LLZRGF: "llzrgf", + LLC: "llc", + LLCR: "llcr", + LLGC: "llgc", + LLGCR: "llgcr", + LLCH: "llch", + LLH: "llh", + LLHR: "llhr", + LLGH: "llgh", + LLGHR: "llghr", + LLHH: "llhh", + LLHRL: "llhrl", + LLGHRL: "llghrl", + LLIHH: "llihh", + LLIHL: "llihl", + LLIHF: "llihf", + LLILH: "llilh", + LLILL: "llill", + LLILF: "llilf", + LLGFRL: "llgfrl", + LLGT: "llgt", + LLGTR: "llgtr", + LLGTAT: "llgtat", + LM: "lm", + LMY: "lmy", + LMG: "lmg", + LMD: "lmd", + LMH: "lmh", + LNR: "lnr", + LNGR: "lngr", + LNGFR: "lngfr", + LNXBR: "lnxbr", + LNXR: "lnxr", + LNDBR: "lndbr", + LNDR: "lndr", + LNDFR: "lndfr", + LNEBR: "lnebr", + LNER: "lner", + LOC: "loc", + LOCR: "locr", + LOCG: "locg", + LOCGR: "locgr", + LPTEA: "lptea", + LPD: "lpd", + LPDG: "lpdg", + LPQ: "lpq", + LPR: "lpr", + LPGR: "lpgr", + LPGFR: "lpgfr", + LPXBR: "lpxbr", + LPXR: "lpxr", + LPDBR: "lpdbr", + LPDR: "lpdr", + LPDFR: "lpdfr", + LPEBR: "lpebr", + LPER: "lper", + LPSW: "lpsw", + LPSWE: "lpswe", + LPSWEY: "lpswey", + LRA: "lra", + LRAY: "lray", + LRAG: "lrag", + LRL: "lrl", + LGRL: "lgrl", + LGFRL: "lgfrl", + LRVH: "lrvh", + LRV: "lrv", + LRVR: "lrvr", + LRVG: "lrvg", + LRVGR: "lrvgr", + LDXBR: "ldxbr", + LDXBRA: "ldxbra", + LDXTR: "ldxtr", + LDXR: "ldxr", + LRDR: "lrdr", + LEXBR: "lexbr", + LEXBRA: "lexbra", + LEXR: "lexr", + LEDBR: "ledbr", + LEDBRA: "ledbra", + LEDTR: "ledtr", + LEDR: "ledr", + LRER: "lrer", + LURA: "lura", + LURAG: "lurag", + LZXR: "lzxr", + LZDR: "lzdr", + LZER: "lzer", + MSTA: "msta", + MSCH: "msch", + MC: "mc", + MVHHI: "mvhhi", + MVHI: "mvhi", + MVGHI: "mvghi", + MVC: "mvc", + MVI: "mvi", + MVIY: "mviy", + MVCIN: "mvcin", + MVCL: "mvcl", + MVCLE: "mvcle", + MVCLU: "mvclu", + MVN: "mvn", + MVPG: "mvpg", + MVCRL: "mvcrl", + MVST: "mvst", + MVCP: "mvcp", + MVCS: "mvcs", + MVCDK: "mvcdk", + MVCK: "mvck", + MVO: "mvo", + MVCOS: "mvcos", + MVCSK: "mvcsk", + MVZ: "mvz", + MG: "mg", + MGRK: "mgrk", + M: "m", + MFY: "mfy", + MR: "mr", + MXBR: "mxbr", + MXTR: "mxtr", + MXTRA: "mxtra", + MXR: "mxr", + MDB: "mdb", + MDBR: "mdbr", + MDTR: "mdtr", + MDTRA: "mdtra", + MD: "md", + MDR: "mdr", + MXDB: "mxdb", + MXDBR: "mxdbr", + MXD: "mxd", + MXDR: "mxdr", + MEEB: "meeb", + MEEBR: "meebr", + MEE: "mee", + MEER: "meer", + MDEB: "mdeb", + MDEBR: "mdebr", + MDE: "mde", + MDER: "mder", + ME: "me", + MER: "mer", + MAY: "may", + MAYR: "mayr", + MADB: "madb", + MADBR: "madbr", + MAD: "mad", + MADR: "madr", + MAEB: "maeb", + MAEBR: "maebr", + MAE: "mae", + MAER: "maer", + MAYH: "mayh", + MAYHR: "mayhr", + MAYL: "mayl", + MAYLR: "maylr", + MSDB: "msdb", + MSDBR: "msdbr", + MSD: "msd", + MSDR: "msdr", + MSEB: "mseb", + MSEBR: "msebr", + MSE: "mse", + MSER: "mser", + MP: "mp", + MH: "mh", + MHY: "mhy", + MGH: "mgh", + MHI: "mhi", + MGHI: "mghi", + MLG: "mlg", + MLGR: "mlgr", + ML: "ml", + MLR: "mlr", + MS: "ms", + MSC: "msc", + MSR: "msr", + MSRKC: "msrkc", + MSY: "msy", + MSG: "msg", + MSGC: "msgc", + MSGR: "msgr", + MSGRKC: "msgrkc", + MSGF: "msgf", + MSGFR: "msgfr", + MSFI: "msfi", + MSGFI: "msgfi", + MYH: "myh", + MYHR: "myhr", + MYL: "myl", + MYLR: "mylr", + MY: "my", + MYR: "myr", + NNRK: "nnrk", + NNGRK: "nngrk", + NNPA: "nnpa", + NIAI: "niai", + NTSTG: "ntstg", + NORK: "nork", + NOGRK: "nogrk", + NXRK: "nxrk", + NXGRK: "nxgrk", + O: "o", + OR: "or", + ORK: "ork", + OY: "oy", + OG: "og", + OGR: "ogr", + OGRK: "ogrk", + OC: "oc", + OI: "oi", + OIY: "oiy", + OIHH: "oihh", + OIHL: "oihl", + OIHF: "oihf", + OILH: "oilh", + OILL: "oill", + OILF: "oilf", + OCRK: "ocrk", + OCGRK: "ocgrk", + PACK: "pack", + PKA: "pka", + PKU: "pku", + PGIN: "pgin", + PGOUT: "pgout", + PCC: "pcc", + PCKMO: "pckmo", + PFPO: "pfpo", + PFMF: "pfmf", + PLO: "plo", + PPA: "ppa", + PRNO: "prno", + PTFF: "ptff", + PTF: "ptf", + POPCNT: "popcnt", + PFD: "pfd", + PFDRL: "pfdrl", + PC: "pc", + PR: "pr", + PT: "pt", + PTI: "pti", + PALB: "palb", + PTLB: "ptlb", + QAXTR: "qaxtr", + QADTR: "qadtr", + QPACI: "qpaci", + RRXTR: "rrxtr", + RRDTR: "rrdtr", + RCHP: "rchp", + RDP: "rdp", + RRBE: "rrbe", + RRBM: "rrbm", + RP: "rp", + RSCH: "rsch", + RLL: "rll", + RLLG: "rllg", + RNSBG: "rnsbg", + RXSBG: "rxsbg", + RISBG: "risbg", + RISBGN: "risbgn", + RISBHG: "risbhg", + RISBLG: "risblg", + ROSBG: "rosbg", + SRST: "srst", + SRSTU: "srstu", + SELR: "selr", + SELGR: "selgr", + SELFHR: "selfhr", + SAR: "sar", + SAL: "sal", + SAC: "sac", + SACF: "sacf", + SAM24: "sam24", + SAM31: "sam31", + SAM64: "sam64", + SRNM: "srnm", + SRNMB: "srnmb", + SCHM: "schm", + SCK: "sck", + SCKC: "sckc", + SCKPF: "sckpf", + SPT: "spt", + SRNMT: "srnmt", + SFPC: "sfpc", + SFASR: "sfasr", + SPX: "spx", + SPM: "spm", + SPKA: "spka", + SSAR: "ssar", + SSAIR: "ssair", + SSKE: "sske", + SSM: "ssm", + SRP: "srp", + SLDA: "slda", + SLDL: "sldl", + SLA: "sla", + SLAK: "slak", + SLAG: "slag", + SLL: "sll", + SLLK: "sllk", + SLLG: "sllg", + SRDA: "srda", + SRDL: "srdl", + SRA: "sra", + SRAK: "srak", + SRAG: "srag", + SRL: "srl", + SRLK: "srlk", + SRLG: "srlg", + SLXT: "slxt", + SLDT: "sldt", + SRXT: "srxt", + SRDT: "srdt", + SIGP: "sigp", + SORTL: "sortl", + SQXBR: "sqxbr", + SQXR: "sqxr", + SQDB: "sqdb", + SQDBR: "sqdbr", + SQD: "sqd", + SQDR: "sqdr", + SQEB: "sqeb", + SQEBR: "sqebr", + SQE: "sqe", + SQER: "sqer", + SSCH: "ssch", + ST: "st", + STY: "sty", + STG: "stg", + STD: "std", + STDY: "stdy", + STE: "ste", + STEY: "stey", + STAM: "stam", + STAMY: "stamy", + STBEAR: "stbear", + STCPS: "stcps", + STCRW: "stcrw", + STC: "stc", + STCY: "stcy", + STCH: "stch", + STCMH: "stcmh", + STCM: "stcm", + STCMY: "stcmy", + STCK: "stck", + STCKC: "stckc", + STCKE: "stcke", + STCKF: "stckf", + STCTL: "stctl", + STCTG: "stctg", + STAP: "stap", + STIDP: "stidp", + STPT: "stpt", + STFL: "stfl", + STFLE: "stfle", + STFPC: "stfpc", + STGSC: "stgsc", + STH: "sth", + STHY: "sthy", + STHH: "sthh", + STHRL: "sthrl", + STFH: "stfh", + STOCFH: "stocfh", + STM: "stm", + STMY: "stmy", + STMG: "stmg", + STMH: "stmh", + STOC: "stoc", + STOCG: "stocg", + STPQ: "stpq", + STPX: "stpx", + STRAG: "strag", + STRL: "strl", + STGRL: "stgrl", + STRVH: "strvh", + STRV: "strv", + STRVG: "strvg", + STSCH: "stsch", + STSI: "stsi", + STNSM: "stnsm", + STOSM: "stosm", + STURA: "stura", + STURG: "sturg", + S: "s", + SR: "sr", + SRK: "srk", + SY: "sy", + SG: "sg", + SGR: "sgr", + SGRK: "sgrk", + SGF: "sgf", + SGFR: "sgfr", + SXBR: "sxbr", + SXTR: "sxtr", + SXTRA: "sxtra", + SDB: "sdb", + SDBR: "sdbr", + SDTR: "sdtr", + SDTRA: "sdtra", + SEB: "seb", + SEBR: "sebr", + SP: "sp", + SH: "sh", + SHY: "shy", + SGH: "sgh", + SHHHR: "shhhr", + SHHLR: "shhlr", + SL: "sl", + SLR: "slr", + SLRK: "slrk", + SLY: "sly", + SLG: "slg", + SLGR: "slgr", + SLGRK: "slgrk", + SLGF: "slgf", + SLGFR: "slgfr", + SLHHHR: "slhhhr", + SLHHLR: "slhhlr", + SLFI: "slfi", + SLGFI: "slgfi", + SLB: "slb", + SLBR: "slbr", + SLBG: "slbg", + SLBGR: "slbgr", + SXR: "sxr", + SD: "sd", + SDR: "sdr", + SE: "se", + SER: "ser", + SW: "sw", + SWR: "swr", + SU: "su", + SUR: "sur", + SVC: "svc", + TAR: "tar", + TAM: "tam", + TS: "ts", + TB: "tb", + TCXB: "tcxb", + TDCXT: "tdcxt", + TCDB: "tcdb", + TDCDT: "tdcdt", + TCEB: "tceb", + TDCET: "tdcet", + TDGXT: "tdgxt", + TDGDT: "tdgdt", + TDGET: "tdget", + TP: "tp", + TPEI: "tpei", + TPI: "tpi", + TPROT: "tprot", + TSCH: "tsch", + TM: "tm", + TMY: "tmy", + TMHH: "tmhh", + TMHL: "tmhl", + TMLH: "tmlh", + TMLL: "tmll", + TMH: "tmh", + TML: "tml", + TRACE: "trace", + TRACG: "tracg", + TABORT: "tabort", + TBEGINC: "tbeginc", + TBEGIN: "tbegin", + TEND: "tend", + TR: "tr", + TRT: "trt", + TRTE: "trte", + TRTR: "trtr", + TRTRE: "trtre", + TRE: "tre", + TROO: "troo", + TROT: "trot", + TRTO: "trto", + TRTT: "trtt", + TRAP2: "trap2", + TRAP4: "trap4", + UNPK: "unpk", + UNPKA: "unpka", + UNPKU: "unpku", + UPT: "upt", + VA: "va", + VACC: "vacc", + VAP: "vap", + VAC: "vac", + VACCC: "vaccc", + VN: "vn", + VNC: "vnc", + VAVG: "vavg", + VAVGL: "vavgl", + VBPERM: "vbperm", + VCKSM: "vcksm", + VCP: "vcp", + VCEQ: "vceq", + VCH: "vch", + VCHL: "vchl", + VCSPH: "vcsph", + VCVB: "vcvb", + VCVBG: "vcvbg", + VCVD: "vcvd", + VCVDG: "vcvdg", + VCLZDP: "vclzdp", + VCLZ: "vclz", + VCTZ: "vctz", + VDP: "vdp", + VEC: "vec", + VECL: "vecl", + VERIM: "verim", + VERLL: "verll", + VERLLV: "verllv", + VESLV: "veslv", + VESL: "vesl", + VESRA: "vesra", + VESRAV: "vesrav", + VESRL: "vesrl", + VESRLV: "vesrlv", + VX: "vx", + VFAE: "vfae", + VFEE: "vfee", + VFENE: "vfene", + VFA: "vfa", + WFK: "wfk", + VFCE: "vfce", + VFCH: "vfch", + VFCHE: "vfche", + WFC: "wfc", + VCLFNH: "vclfnh", + VCLFNL: "vclfnl", + VCRNF: "vcrnf", + VCFPS: "vcfps", + VCDG: "vcdg", + VCFPL: "vcfpl", + VCDLG: "vcdlg", + VCFN: "vcfn", + VCSFP: "vcsfp", + VCGD: "vcgd", + VCLFP: "vclfp", + VCLGD: "vclgd", + VCNF: "vcnf", + VFD: "vfd", + VFLL: "vfll", + VFLR: "vflr", + VFMAX: "vfmax", + VFMIN: "vfmin", + VFM: "vfm", + VFMA: "vfma", + VFMS: "vfms", + VFNMA: "vfnma", + VFNMS: "vfnms", + VFPSO: "vfpso", + VFSQ: "vfsq", + VFS: "vfs", + VFTCI: "vftci", + VGFM: "vgfm", + VGFMA: "vgfma", + VGEF: "vgef", + VGEG: "vgeg", + VGBM: "vgbm", + VGM: "vgm", + VISTR: "vistr", + VL: "vl", + VLR: "vlr", + VLREP: "vlrep", + VLEBRH: "vlebrh", + VLEBRF: "vlebrf", + VLEBRG: "vlebrg", + VLBRREP: "vlbrrep", + VLLEBRZ: "vllebrz", + VLBR: "vlbr", + VLC: "vlc", + VLEH: "vleh", + VLEF: "vlef", + VLEG: "vleg", + VLEB: "vleb", + VLEIH: "vleih", + VLEIF: "vleif", + VLEIG: "vleig", + VLEIB: "vleib", + VLER: "vler", + VFI: "vfi", + VLGV: "vlgv", + VLIP: "vlip", + VLLEZ: "vllez", + VLM: "vlm", + VLP: "vlp", + VLRL: "vlrl", + VLRLR: "vlrlr", + VLBB: "vlbb", + VLVG: "vlvg", + VLVGP: "vlvgp", + VLL: "vll", + VMX: "vmx", + VMXL: "vmxl", + VMRH: "vmrh", + VMRL: "vmrl", + VMN: "vmn", + VMNL: "vmnl", + VMAE: "vmae", + VMAH: "vmah", + VMALE: "vmale", + VMALH: "vmalh", + VMALO: "vmalo", + VMAL: "vmal", + VMAO: "vmao", + VMSP: "vmsp", + VMP: "vmp", + VME: "vme", + VMH: "vmh", + VMLE: "vmle", + VMLH: "vmlh", + VMLO: "vmlo", + VML: "vml", + VMO: "vmo", + VMSL: "vmsl", + VNN: "vnn", + VNO: "vno", + VNX: "vnx", + VO: "vo", + VOC: "voc", + VPK: "vpk", + VPKLS: "vpkls", + VPKS: "vpks", + VPKZ: "vpkz", + VPKZR: "vpkzr", + VPSOP: "vpsop", + VPERM: "vperm", + VPDI: "vpdi", + VPOPCT: "vpopct", + VRP: "vrp", + VREP: "vrep", + VREPI: "vrepi", + VSCEF: "vscef", + VSCEG: "vsceg", + VSEL: "vsel", + VSDP: "vsdp", + VSRP: "vsrp", + VSRPR: "vsrpr", + VSL: "vsl", + VSLB: "vslb", + VSLD: "vsld", + VSLDB: "vsldb", + VSRA: "vsra", + VSRAB: "vsrab", + VSRD: "vsrd", + VSRL: "vsrl", + VSRLB: "vsrlb", + VSEG: "vseg", + VST: "vst", + VSTEBRH: "vstebrh", + VSTEBRF: "vstebrf", + VSTEBRG: "vstebrg", + VSTBR: "vstbr", + VSTEH: "vsteh", + VSTEF: "vstef", + VSTEG: "vsteg", + VSTEB: "vsteb", + VSTER: "vster", + VSTM: "vstm", + VSTRL: "vstrl", + VSTRLR: "vstrlr", + VSTL: "vstl", + VSTRC: "vstrc", + VSTRS: "vstrs", + VS: "vs", + VSCBI: "vscbi", + VSP: "vsp", + VSBCBI: "vsbcbi", + VSBI: "vsbi", + VSUMG: "vsumg", + VSUMQ: "vsumq", + VSUM: "vsum", + VTP: "vtp", + VTM: "vtm", + VUPH: "vuph", + VUPLH: "vuplh", + VUPLL: "vupll", + VUPL: "vupl", + VUPKZ: "vupkz", + VUPKZH: "vupkzh", + VUPKZL: "vupkzl", + ZAP: "zap", +} + +var ( + ap_Reg_8_11 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{8, 4}} + ap_DispUnsigned_20_31 = &argField{Type: TypeDispUnsigned, flags: 0x10, BitField: BitField{20, 12}} + ap_IndexReg_12_15 = &argField{Type: TypeIndexReg, flags: 0x41, BitField: BitField{12, 4}} + ap_BaseReg_16_19 = &argField{Type: TypeBaseReg, flags: 0x21, BitField: BitField{16, 4}} + ap_Reg_12_15 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{12, 4}} + ap_Reg_24_27 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{24, 4}} + ap_Reg_28_31 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{28, 4}} + ap_Reg_16_19 = &argField{Type: TypeReg, flags: 0x1, BitField: BitField{16, 4}} + ap_DispSigned20_20_39 = &argField{Type: TypeDispSigned20, flags: 0x10, BitField: BitField{20, 20}} + ap_FPReg_24_27 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{24, 4}} + ap_FPReg_28_31 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{28, 4}} + ap_FPReg_16_19 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{16, 4}} + ap_Mask_20_23 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{20, 4}} + ap_FPReg_8_11 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{8, 4}} + ap_Len_8_11 = &argField{Type: TypeLen, flags: 0x10, BitField: BitField{8, 4}} + ap_DispUnsigned_36_47 = &argField{Type: TypeDispUnsigned, flags: 0x10, BitField: BitField{36, 12}} + ap_Len_12_15 = &argField{Type: TypeLen, flags: 0x10, BitField: BitField{12, 4}} + ap_BaseReg_32_35 = &argField{Type: TypeBaseReg, flags: 0x21, BitField: BitField{32, 4}} + ap_ImmSigned16_16_31 = &argField{Type: TypeImmSigned16, flags: 0x0, BitField: BitField{16, 16}} + ap_ImmSigned32_16_47 = &argField{Type: TypeImmSigned32, flags: 0x0, BitField: BitField{16, 32}} + ap_ImmSigned8_8_15 = &argField{Type: TypeImmSigned8, flags: 0x0, BitField: BitField{8, 8}} + ap_ImmUnsigned_16_47 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 32}} + ap_FPReg_12_15 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{12, 4}} + ap_Len_8_15 = &argField{Type: TypeLen, flags: 0x10, BitField: BitField{8, 8}} + ap_Mask_8_11 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{8, 4}} + ap_RegImSigned16_32_47 = &argField{Type: TypeRegImSigned16, flags: 0x80, BitField: BitField{32, 16}} + ap_RegImSigned12_12_23 = &argField{Type: TypeRegImSigned12, flags: 0x80, BitField: BitField{12, 12}} + ap_RegImSigned24_24_47 = &argField{Type: TypeRegImSigned24, flags: 0x80, BitField: BitField{24, 24}} + ap_RegImSigned16_16_31 = &argField{Type: TypeRegImSigned16, flags: 0x80, BitField: BitField{16, 16}} + ap_RegImSigned32_16_47 = &argField{Type: TypeRegImSigned32, flags: 0x80, BitField: BitField{16, 32}} + ap_Mask_32_35 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{32, 4}} + ap_Mask_16_19 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{16, 4}} + ap_ImmSigned16_32_47 = &argField{Type: TypeImmSigned16, flags: 0x0, BitField: BitField{32, 16}} + ap_ImmSigned8_32_39 = &argField{Type: TypeImmSigned8, flags: 0x0, BitField: BitField{32, 8}} + ap_Mask_12_15 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{12, 4}} + ap_ImmUnsigned_8_15 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{8, 8}} + ap_ImmUnsigned_32_47 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{32, 16}} + ap_ImmUnsigned_32_39 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{32, 8}} + ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 16}} + ap_FPReg_32_35 = &argField{Type: TypeFPReg, flags: 0x2, BitField: BitField{32, 4}} + ap_Mask_36_39 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{36, 4}} + ap_ACReg_24_27 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{24, 4}} + ap_ACReg_28_31 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{28, 4}} + ap_VecReg_8_11 = &argField{Type: TypeVecReg, flags: 0x8, BitField: BitField{8, 4}} + ap_VecReg_12_15 = &argField{Type: TypeVecReg, flags: 0x8, BitField: BitField{12, 4}} + ap_VecReg_16_19 = &argField{Type: TypeVecReg, flags: 0x8, BitField: BitField{16, 4}} + ap_ImmUnsigned_36_39 = &argField{Type: TypeImmUnsigned, flags: 0xc00, BitField: BitField{36, 4}} + ap_Mask_24_27 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{24, 4}} + ap_ACReg_8_11 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{8, 4}} + ap_ACReg_12_15 = &argField{Type: TypeACReg, flags: 0x3, BitField: BitField{12, 4}} + ap_CReg_8_11 = &argField{Type: TypeCReg, flags: 0x4, BitField: BitField{8, 4}} + ap_CReg_12_15 = &argField{Type: TypeCReg, flags: 0x4, BitField: BitField{12, 4}} + ap_ImmSigned32_16_31 = &argField{Type: TypeImmSigned32, flags: 0x0, BitField: BitField{16, 16}} + ap_ImmUnsigned_24_27 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{24, 4}} + ap_ImmUnsigned_28_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{28, 4}} + ap_ImmUnsigned_16_23 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 8}} + ap_ImmUnsigned_24_31 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{24, 8}} + ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{12, 4}} + ap_ImmUnsigned_28_35 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{28, 8}} + ap_VecReg_32_35 = &argField{Type: TypeVecReg, flags: 0x8, BitField: BitField{32, 4}} + ap_Mask_28_31 = &argField{Type: TypeMask, flags: 0x800, BitField: BitField{28, 4}} + ap_ImmUnsigned_16_27 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{16, 12}} + ap_ImmUnsigned_32_35 = &argField{Type: TypeImmUnsigned, flags: 0x0, BitField: BitField{32, 4}} +) + +var instFormats = [...]instFormat{ + {A, 0xff00000000000000, 0x5a00000000000000, 0x0, // ADD (32) (A R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AR, 0xff00000000000000, 0x1a00000000000000, 0x0, // ADD (32) (AR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {ARK, 0xffff000000000000, 0xb9f8000000000000, 0xf0000000000, // ADD (32) (ARK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {AY, 0xff00000000ff0000, 0xe3000000005a0000, 0x0, // ADD (32) (AY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AG, 0xff00000000ff0000, 0xe300000000080000, 0x0, // ADD (64) (AG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AGR, 0xffff000000000000, 0xb908000000000000, 0xff0000000000, // ADD (64) (AGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {AGRK, 0xffff000000000000, 0xb9e8000000000000, 0xf0000000000, // ADD (64) (AGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {AGF, 0xff00000000ff0000, 0xe300000000180000, 0x0, // ADD (64←32) (AGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AGFR, 0xffff000000000000, 0xb918000000000000, 0xff0000000000, // ADD (64←32) (AGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {AXBR, 0xffff000000000000, 0xb34a000000000000, 0xff0000000000, // ADD (extended BFP) (AXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {AXTR, 0xffff000000000000, 0xb3da000000000000, 0xf0000000000, // ADD (extended DFP) (AXTR R1,R2,R3) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}}, + {AXTRA, 0xffff000000000000, 0xb3da000000000000, 0x0, // ADD (extended DFP) (AXTRA R1,R2,R3,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}}, + {ADB, 0xff00000000ff0000, 0xed000000001a0000, 0xff000000, // ADD (long BFP) (ADB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ADBR, 0xffff000000000000, 0xb31a000000000000, 0xff0000000000, // ADD (long BFP) (ADBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {ADTR, 0xffff000000000000, 0xb3d2000000000000, 0xf0000000000, // ADD (long DFP) (ADTR R1,R2,R3) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}}, + {ADTRA, 0xffff000000000000, 0xb3d2000000000000, 0x0, // ADD (long DFP) (ADTRA R1,R2,R3,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}}, + {AEB, 0xff00000000ff0000, 0xed000000000a0000, 0xff000000, // ADD (short BFP) (AEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AEBR, 0xffff000000000000, 0xb30a000000000000, 0xff0000000000, // ADD (short BFP) (AEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {AP, 0xff00000000000000, 0xfa00000000000000, 0x0, // ADD DECIMAL (AP D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, + {AH, 0xff00000000000000, 0x4a00000000000000, 0x0, // ADD HALFWORD (32←16) (AH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AHY, 0xff00000000ff0000, 0xe3000000007a0000, 0x0, // ADD HALFWORD (32←16) (AHY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AGH, 0xff00000000ff0000, 0xe300000000380000, 0x0, // ADD HALFWORD (64→16) (AGH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AHI, 0xff0f000000000000, 0xa70a000000000000, 0x0, // ADD HALFWORD IMMEDIATE (32←16) (AHI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {AGHI, 0xff0f000000000000, 0xa70b000000000000, 0x0, // ADD HALFWORD IMMEDIATE (64←16) (AGHI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {AHHHR, 0xffff000000000000, 0xb9c8000000000000, 0xf0000000000, // ADD HIGH (32) (AHHHR R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {AHHLR, 0xffff000000000000, 0xb9d8000000000000, 0xf0000000000, // ADD HIGH (32) (AHHLR R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {AFI, 0xff0f000000000000, 0xc209000000000000, 0x0, // ADD IMMEDIATE (32) (AFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {AHIK, 0xff00000000ff0000, 0xec00000000d80000, 0xff000000, // ADD IMMEDIATE (32←16) (AHIK R1,R3,I2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmSigned16_16_31}}, + {ASI, 0xff00000000ff0000, 0xeb000000006a0000, 0x0, // ADD IMMEDIATE (32←8) (ASI D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {AGHIK, 0xff00000000ff0000, 0xec00000000d90000, 0xff000000, // ADD IMMEDIATE (64←16) (AGHIK R1,R3,I2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmSigned16_16_31}}, + {AGFI, 0xff0f000000000000, 0xc208000000000000, 0x0, // ADD IMMEDIATE (64←32) (AGFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {AGSI, 0xff00000000ff0000, 0xeb000000007a0000, 0x0, // ADD IMMEDIATE (64←8) (AGSI D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {AIH, 0xff0f000000000000, 0xcc08000000000000, 0x0, // ADD IMMEDIATE HIGH (32) (AIH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {AL, 0xff00000000000000, 0x5e00000000000000, 0x0, // ADD LOGICAL (32) (AL R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ALR, 0xff00000000000000, 0x1e00000000000000, 0x0, // ADD LOGICAL (32) (ALR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {ALRK, 0xffff000000000000, 0xb9fa000000000000, 0xf0000000000, // ADD LOGICAL (32) (ALRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {ALY, 0xff00000000ff0000, 0xe3000000005e0000, 0x0, // ADD LOGICAL (32) (ALY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ALG, 0xff00000000ff0000, 0xe3000000000a0000, 0x0, // ADD LOGICAL (64) (ALG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ALGR, 0xffff000000000000, 0xb90a000000000000, 0xff0000000000, // ADD LOGICAL (64) (ALGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ALGRK, 0xffff000000000000, 0xb9ea000000000000, 0xf0000000000, // ADD LOGICAL (64) (ALGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {ALGF, 0xff00000000ff0000, 0xe3000000001a0000, 0x0, // ADD LOGICAL (64←32) (ALGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ALGFR, 0xffff000000000000, 0xb91a000000000000, 0xff0000000000, // ADD LOGICAL (64←32) (ALGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ALHHHR, 0xffff000000000000, 0xb9ca000000000000, 0xf0000000000, // ADD LOGICAL HIGH (32) (ALHHHR R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {ALHHLR, 0xffff000000000000, 0xb9da000000000000, 0xf0000000000, // ADD LOGICAL HIGH (32) (ALHHLR R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {ALFI, 0xff0f000000000000, 0xc20b000000000000, 0x0, // ADD LOGICAL IMMEDIATE (32) (ALFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {ALGFI, 0xff0f000000000000, 0xc20a000000000000, 0x0, // ADD LOGICAL IMMEDIATE (64←32) (ALGFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {ALC, 0xff00000000ff0000, 0xe300000000980000, 0x0, // ADD LOGICAL WITH CARRY (32) (ALC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ALCR, 0xffff000000000000, 0xb998000000000000, 0xff0000000000, // ADD LOGICAL WITH CARRY (32) (ALCR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ALCG, 0xff00000000ff0000, 0xe300000000880000, 0x0, // ADD LOGICAL WITH CARRY (64) (ALCG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ALCGR, 0xffff000000000000, 0xb988000000000000, 0xff0000000000, // ADD LOGICAL WITH CARRY (64) (ALCGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ALHSIK, 0xff00000000ff0000, 0xec00000000da0000, 0xff000000, // ADD LOGICAL WITH SIGNED IMMEDIATE(32→16) (ALHSIK R1,R3,I2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmSigned16_16_31}}, + {ALSI, 0xff00000000ff0000, 0xeb000000006e0000, 0x0, // ADD LOGICAL WITH SIGNED IMMEDIATE (32←8) (ALSI D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {ALGHSIK, 0xff00000000ff0000, 0xec00000000db0000, 0xff000000, // ADD LOGICAL WITH SIGNED IMMEDIATE(64→16) (ALGHSIK R1,R3,I2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmSigned16_16_31}}, + {ALGSI, 0xff00000000ff0000, 0xeb000000007e0000, 0x0, // ADD LOGICAL WITH SIGNED IMMEDIATE (64→8) (ALGSI D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {ALSIH, 0xff0f000000000000, 0xcc0a000000000000, 0x0, // ADD LOGICAL WITH SIGNED IMMEDIATE HIGH(32) (ALSIH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {ALSIHN, 0xff0f000000000000, 0xcc0b000000000000, 0x0, // ADD LOGICAL WITH SIGNED IMMEDIATE HIGH(32) (ALSIHN R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {AXR, 0xff00000000000000, 0x3600000000000000, 0x0, // ADD NORMALIZED (extended HFP) (AXR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {AD, 0xff00000000000000, 0x6a00000000000000, 0x0, // ADD NORMALIZED (long HFP) (AD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ADR, 0xff00000000000000, 0x2a00000000000000, 0x0, // ADD NORMALIZED (long HFP) (ADR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {AE, 0xff00000000000000, 0x7a00000000000000, 0x0, // ADD NORMALIZED (short HFP) (AE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AER, 0xff00000000000000, 0x3a00000000000000, 0x0, // ADD NORMALIZED (short HFP) (AER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {AW, 0xff00000000000000, 0x6e00000000000000, 0x0, // ADD UNNORMALIZED (long HFP) (AW R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AWR, 0xff00000000000000, 0x2e00000000000000, 0x0, // ADD UNNORMALIZED (long HFP) (AWR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {AU, 0xff00000000000000, 0x7e00000000000000, 0x0, // ADD UNNORMALIZED (short HFP) (AU R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {AUR, 0xff00000000000000, 0x3e00000000000000, 0x0, // ADD UNNORMALIZED (short HFP) (AUR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {N, 0xff00000000000000, 0x5400000000000000, 0x0, // AND (32) (N R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {NR, 0xff00000000000000, 0x1400000000000000, 0x0, // AND (32) (NR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {NRK, 0xffff000000000000, 0xb9f4000000000000, 0xf0000000000, // AND (32) (NRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {NY, 0xff00000000ff0000, 0xe300000000540000, 0x0, // AND (32) (NY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {NG, 0xff00000000ff0000, 0xe300000000800000, 0x0, // AND (64) (NG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {NGR, 0xffff000000000000, 0xb980000000000000, 0xff0000000000, // AND (64) (NGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {NGRK, 0xffff000000000000, 0xb9e4000000000000, 0xf0000000000, // AND (64) (NGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {NC, 0xff00000000000000, 0xd400000000000000, 0x0, // AND (character) (NC D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {NI, 0xff00000000000000, 0x9400000000000000, 0x0, // AND (immediate) (NI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {NIY, 0xff00000000ff0000, 0xeb00000000540000, 0x0, // AND (immediate) (NIY D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {NIHH, 0xff0f000000000000, 0xa504000000000000, 0x0, // AND IMMEDIATE (high high) (NIHH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {NIHL, 0xff0f000000000000, 0xa505000000000000, 0x0, // AND IMMEDIATE (high low) (NIHL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {NIHF, 0xff0f000000000000, 0xc00a000000000000, 0x0, // AND IMMEDIATE (high) (NIHF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {NILH, 0xff0f000000000000, 0xa506000000000000, 0x0, // AND IMMEDIATE (low high) (NILH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {NILL, 0xff0f000000000000, 0xa507000000000000, 0x0, // AND IMMEDIATE (low low) (NILL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {NILF, 0xff0f000000000000, 0xc00b000000000000, 0x0, // AND IMMEDIATE (low) (NILF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {NCRK, 0xffff000000000000, 0xb9f5000000000000, 0xf0000000000, // AND WITH COMPLEMENT(32) (NCRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {NCGRK, 0xffff000000000000, 0xb9e5000000000000, 0xf0000000000, // AND WITH COMPLEMENT(64) (NCGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {BAL, 0xff00000000000000, 0x4500000000000000, 0x0, // BRANCH AND LINK (BAL R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {BALR, 0xff00000000000000, 0x500000000000000, 0x0, // BRANCH AND LINK (BALR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {BAS, 0xff00000000000000, 0x4d00000000000000, 0x0, // BRANCH AND SAVE (BAS R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {BASR, 0xff00000000000000, 0xd00000000000000, 0x0, // BRANCH AND SAVE (BASR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {BASSM, 0xff00000000000000, 0xc00000000000000, 0x0, // BRANCH AND SAVE AND SET MODE (BASSM R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {BSA, 0xffff000000000000, 0xb25a000000000000, 0xff0000000000, // BRANCH AND SET AUTHORITY (BSA R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {BSM, 0xff00000000000000, 0xb00000000000000, 0x0, // BRANCH AND SET MODE (BSM R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {BAKR, 0xffff000000000000, 0xb240000000000000, 0xff0000000000, // BRANCH AND STACK (BAKR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {BSG, 0xffff000000000000, 0xb258000000000000, 0xff0000000000, // BRANCH IN SUBSPACE GROUP (BSG R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {BIC, 0xff00000000ff0000, 0xe300000000470000, 0x0, // BRANCH INDIRECT ON CONDITION (BIC M1,D2(X2,B2)) + [8]*argField{ap_Mask_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {BC, 0xff00000000000000, 0x4700000000000000, 0x0, // BRANCH ON CONDITION (BC M1,D2(X2,B2)) + [8]*argField{ap_Mask_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {BCR, 0xff00000000000000, 0x700000000000000, 0x0, // BRANCH ON CONDITION (BCR M1,R2) + [8]*argField{ap_Mask_8_11, ap_Reg_12_15}}, + {BCT, 0xff00000000000000, 0x4600000000000000, 0x0, // BRANCH ON COUNT (32) (BCT R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {BCTR, 0xff00000000000000, 0x600000000000000, 0x0, // BRANCH ON COUNT (32) (BCTR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {BCTG, 0xff00000000ff0000, 0xe300000000460000, 0x0, // BRANCH ON COUNT (64) (BCTG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {BCTGR, 0xffff000000000000, 0xb946000000000000, 0xff0000000000, // BRANCH ON COUNT (64) (BCTGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {BXH, 0xff00000000000000, 0x8600000000000000, 0x0, // BRANCH ON INDEX HIGH (32) (BXH R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {BXHG, 0xff00000000ff0000, 0xeb00000000440000, 0x0, // BRANCH ON INDEX HIGH (64) (BXHG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {BXLE, 0xff00000000000000, 0x8700000000000000, 0x0, // BRANCH ON INDEX LOW OR EQUAL (32) (BXLE R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {BXLEG, 0xff00000000ff0000, 0xeb00000000450000, 0x0, // BRANCH ON INDEX LOW OR EQUAL (64) (BXLEG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {BPP, 0xff00000000000000, 0xc700000000000000, 0xf000000000000, // BRANCH PREDICTION PRELOAD (BPP M1,RI2,D3(B3)) + [8]*argField{ap_Mask_8_11, ap_RegImSigned16_32_47, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {BPRP, 0xff00000000000000, 0xc500000000000000, 0x0, // BRANCH PREDICTION RELATIVE PRELOAD (BPRP M1,RI2,RI3) + [8]*argField{ap_Mask_8_11, ap_RegImSigned12_12_23, ap_RegImSigned24_24_47}}, + {BRAS, 0xff0f000000000000, 0xa705000000000000, 0x0, // BRANCH RELATIVE AND SAVE (BRAS R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned16_16_31}}, + {BRASL, 0xff0f000000000000, 0xc005000000000000, 0x0, // BRANCH RELATIVE AND SAVE LONG (BRASL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {BRC, 0xff0f000000000000, 0xa704000000000000, 0x0, // BRANCH RELATIVE ON CONDITION (BRC M1,RI2) + [8]*argField{ap_Mask_8_11, ap_RegImSigned16_16_31}}, + {BRCL, 0xff0f000000000000, 0xc004000000000000, 0x0, // BRANCH RELATIVE ON CONDITION LONG (BRCL M1,RI2) + [8]*argField{ap_Mask_8_11, ap_RegImSigned32_16_47}}, + {BRCT, 0xff0f000000000000, 0xa706000000000000, 0x0, // BRANCH RELATIVE ON COUNT (32) (BRCT R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned16_16_31}}, + {BRCTG, 0xff0f000000000000, 0xa707000000000000, 0x0, // BRANCH RELATIVE ON COUNT (64) (BRCTG R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned16_16_31}}, + {BRCTH, 0xff0f000000000000, 0xcc06000000000000, 0x0, // BRANCH RELATIVE ON COUNT HIGH (32) (BRCTH R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {BRXH, 0xff00000000000000, 0x8400000000000000, 0x0, // BRANCH RELATIVE ON INDEX HIGH (32) (BRXH R1,R3,RI2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_RegImSigned16_16_31}}, + {BRXHG, 0xff00000000ff0000, 0xec00000000440000, 0xff000000, // BRANCH RELATIVE ON INDEX HIGH (64) (BRXHG R1,R3,RI2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_RegImSigned16_16_31}}, + {BRXLE, 0xff00000000000000, 0x8500000000000000, 0x0, // BRANCH RELATIVE ON INDEX LOW OR EQ. (32) (BRXLE R1,R3,RI2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_RegImSigned16_16_31}}, + {BRXLG, 0xff00000000ff0000, 0xec00000000450000, 0xff000000, // BRANCH RELATIVE ON INDEX LOW OR EQ. (64) (BRXLG R1,R3,RI2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_RegImSigned16_16_31}}, + {XSCH, 0xffff000000000000, 0xb276000000000000, 0xffff00000000, // CANCEL SUBCHANNEL (XSCH) + [8]*argField{}}, + {CKSM, 0xffff000000000000, 0xb241000000000000, 0xff0000000000, // CHECKSUM (CKSM R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {KM, 0xffff000000000000, 0xb92e000000000000, 0xff0000000000, // CIPHER MESSAGE (KM R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {KMA, 0xffff000000000000, 0xb929000000000000, 0xf0000000000, // CIPHER MESSAGE WITH AUTHENTICATION (KMA R1,R3,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31}}, + {KMC, 0xffff000000000000, 0xb92f000000000000, 0xff0000000000, // CIPHER MESSAGE WITH CHAINING (KMC R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {KMF, 0xffff000000000000, 0xb92a000000000000, 0xff0000000000, // CIPHER MESSAGE WITH CIPHER FEEDBACK (KMF R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {KMCTR, 0xffff000000000000, 0xb92d000000000000, 0xf0000000000, // CIPHER MESSAGE WITH COUNTER (KMCTR R1,R3,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31}}, + {KMO, 0xffff000000000000, 0xb92b000000000000, 0xff0000000000, // CIPHER MESSAGE WITH OUTPUT FEEDBACK (KMO R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CSCH, 0xffff000000000000, 0xb230000000000000, 0xffff00000000, // CLEAR SUBCHANNEL (CSCH) + [8]*argField{}}, + {C, 0xff00000000000000, 0x5900000000000000, 0x0, // COMPARE (32) (C R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CR, 0xff00000000000000, 0x1900000000000000, 0x0, // COMPARE (32) (CR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {CY, 0xff00000000ff0000, 0xe300000000590000, 0x0, // COMPARE (32) (CY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CG, 0xff00000000ff0000, 0xe300000000200000, 0x0, // COMPARE (64) (CG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CGR, 0xffff000000000000, 0xb920000000000000, 0xff0000000000, // COMPARE (64) (CGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CGF, 0xff00000000ff0000, 0xe300000000300000, 0x0, // COMPARE (64←32) (CGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CGFR, 0xffff000000000000, 0xb930000000000000, 0xff0000000000, // COMPARE (64←32) (CGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CXBR, 0xffff000000000000, 0xb349000000000000, 0xff0000000000, // COMPARE (extended BFP) (CXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CXTR, 0xffff000000000000, 0xb3ec000000000000, 0xff0000000000, // COMPARE (extended DFP) (CXTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CXR, 0xffff000000000000, 0xb369000000000000, 0xff0000000000, // COMPARE (extended HFP) (CXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CDB, 0xff00000000ff0000, 0xed00000000190000, 0xff000000, // COMPARE (long BFP) (CDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CDBR, 0xffff000000000000, 0xb319000000000000, 0xff0000000000, // COMPARE (long BFP) (CDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CDTR, 0xffff000000000000, 0xb3e4000000000000, 0xff0000000000, // COMPARE (long DFP) (CDTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CD, 0xff00000000000000, 0x6900000000000000, 0x0, // COMPARE (long HFP) (CD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CDR, 0xff00000000000000, 0x2900000000000000, 0x0, // COMPARE (long HFP) (CDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {CEB, 0xff00000000ff0000, 0xed00000000090000, 0xff000000, // COMPARE (short BFP) (CEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CEBR, 0xffff000000000000, 0xb309000000000000, 0xff0000000000, // COMPARE (short BFP) (CEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CE, 0xff00000000000000, 0x7900000000000000, 0x0, // COMPARE (short HFP) (CE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CER, 0xff00000000000000, 0x3900000000000000, 0x0, // COMPARE (short HFP) (CER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {CRB, 0xff00000000ff0000, 0xec00000000f60000, 0xf000000, // COMPARE AND BRANCH (32) (CRB R1,R2,M3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CGRB, 0xff00000000ff0000, 0xec00000000e40000, 0xf000000, // COMPARE AND BRANCH (64) (CGRB R1,R2,M3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CRJ, 0xff00000000ff0000, 0xec00000000760000, 0xf000000, // COMPARE AND BRANCH RELATIVE (32) (CRJ R1,R2,M3,RI4) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_RegImSigned16_16_31}}, + {CGRJ, 0xff00000000ff0000, 0xec00000000640000, 0xf000000, // COMPARE AND BRANCH RELATIVE (64) (CGRJ R1,R2,M3,RI4) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_RegImSigned16_16_31}}, + {CFC, 0xffff000000000000, 0xb21a000000000000, 0x0, // COMPARE AND FORM CODEWORD (CFC D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CRDTE, 0xffff000000000000, 0xb98f000000000000, 0x0, // COMPARE AND REPLACE DAT TABLE ENTRY (CRDTE R1,R3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {KXBR, 0xffff000000000000, 0xb348000000000000, 0xff0000000000, // COMPARE AND SIGNAL (extended BFP) (KXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {KXTR, 0xffff000000000000, 0xb3e8000000000000, 0xff0000000000, // COMPARE AND SIGNAL (extended DFP) (KXTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {KDB, 0xff00000000ff0000, 0xed00000000180000, 0xff000000, // COMPARE AND SIGNAL (long BFP) (KDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {KDBR, 0xffff000000000000, 0xb318000000000000, 0xff0000000000, // COMPARE AND SIGNAL (long BFP) (KDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {KDTR, 0xffff000000000000, 0xb3e0000000000000, 0xff0000000000, // COMPARE AND SIGNAL (long DFP) (KDTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {KEB, 0xff00000000ff0000, 0xed00000000080000, 0xff000000, // COMPARE AND SIGNAL (short BFP) (KEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {KEBR, 0xffff000000000000, 0xb308000000000000, 0xff0000000000, // COMPARE AND SIGNAL (short BFP) (KEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CS, 0xff00000000000000, 0xba00000000000000, 0x0, // COMPARE AND SWAP (32) (CS R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CSY, 0xff00000000ff0000, 0xeb00000000140000, 0x0, // COMPARE AND SWAP (32) (CSY R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CSG, 0xff00000000ff0000, 0xeb00000000300000, 0x0, // COMPARE AND SWAP (64) (CSG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CSP, 0xffff000000000000, 0xb250000000000000, 0xff0000000000, // COMPARE AND SWAP AND PURGE (32) (CSP R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CSPG, 0xffff000000000000, 0xb98a000000000000, 0xff0000000000, // COMPARE AND SWAP AND PURGE (64) (CSPG R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CSST, 0xff0f000000000000, 0xc802000000000000, 0x0, // COMPARE AND SWAP AND STORE (CSST D1(B1),D2(B2),R3) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_8_11}}, + {CRT, 0xffff000000000000, 0xb972000000000000, 0xf0000000000, // COMPARE AND TRAP (32) (CRT R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {CGRT, 0xffff000000000000, 0xb960000000000000, 0xf0000000000, // COMPARE AND TRAP (64) (CGRT R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {CEXTR, 0xffff000000000000, 0xb3fc000000000000, 0xff0000000000, // COMPARE BIASED EXPONENT (extended DFP) (CEXTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CEDTR, 0xffff000000000000, 0xb3f4000000000000, 0xff0000000000, // COMPARE BIASED EXPONENT (long DFP) (CEDTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CP, 0xff00000000000000, 0xf900000000000000, 0x0, // COMPARE DECIMAL (CP D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, + {CDS, 0xff00000000000000, 0xbb00000000000000, 0x0, // COMPARE DOUBLE AND SWAP (32) (CDS R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CDSY, 0xff00000000ff0000, 0xeb00000000310000, 0x0, // COMPARE DOUBLE AND SWAP (32) (CDSY R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CDSG, 0xff00000000ff0000, 0xeb000000003e0000, 0x0, // COMPARE DOUBLE AND SWAP (64) (CDSG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CH, 0xff00000000000000, 0x4900000000000000, 0x0, // COMPARE HALFWORD (32→16) (CH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CHY, 0xff00000000ff0000, 0xe300000000790000, 0x0, // COMPARE HALFWORD (32→16) (CHY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CGH, 0xff00000000ff0000, 0xe300000000340000, 0x0, // COMPARE HALFWORD (64←16) (CGH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CHHSI, 0xffff000000000000, 0xe554000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (16→16) (CHHSI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned16_32_47}}, + {CHI, 0xff0f000000000000, 0xa70e000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (32←16) (CHI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {CHSI, 0xffff000000000000, 0xe55c000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (32←16) (CHSI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned16_32_47}}, + {CGHI, 0xff0f000000000000, 0xa70f000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (64←16) (CGHI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {CGHSI, 0xffff000000000000, 0xe558000000000000, 0x0, // COMPARE HALFWORD IMMEDIATE (64←16) (CGHSI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned16_32_47}}, + {CHRL, 0xff0f000000000000, 0xc605000000000000, 0x0, // COMPAREHALFWORDRELATIVE LONG (32→16) (CHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CGHRL, 0xff0f000000000000, 0xc604000000000000, 0x0, // COMPAREHALFWORDRELATIVE LONG (64←16) (CGHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CHF, 0xff00000000ff0000, 0xe300000000cd0000, 0x0, // COMPARE HIGH (32) (CHF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CHHR, 0xffff000000000000, 0xb9cd000000000000, 0xff0000000000, // COMPARE HIGH (32) (CHHR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CHLR, 0xffff000000000000, 0xb9dd000000000000, 0xff0000000000, // COMPARE HIGH (32) (CHLR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CFI, 0xff0f000000000000, 0xc20d000000000000, 0x0, // COMPARE IMMEDIATE (32) (CFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {CGFI, 0xff0f000000000000, 0xc20c000000000000, 0x0, // COMPARE IMMEDIATE (64←32) (CGFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {CIB, 0xff00000000ff0000, 0xec00000000fe0000, 0x0, // COMPARE IMMEDIATE AND BRANCH (32←8) (CIB R1,I2,M3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_ImmSigned8_32_39, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CGIB, 0xff00000000ff0000, 0xec00000000fc0000, 0x0, // COMPARE IMMEDIATE AND BRANCH (64←8) (CGIB R1,I2,M3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_ImmSigned8_32_39, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CIJ, 0xff00000000ff0000, 0xec000000007e0000, 0x0, // COMPARE IMMEDIATE AND BRANCH RELATIVE(32→8) (CIJ R1,I2,M3,RI4) + [8]*argField{ap_Reg_8_11, ap_ImmSigned8_32_39, ap_Mask_12_15, ap_RegImSigned16_16_31}}, + {CGIJ, 0xff00000000ff0000, 0xec000000007c0000, 0x0, // COMPARE IMMEDIATE AND BRANCH RELATIVE(64→8) (CGIJ R1,I2,M3,RI4) + [8]*argField{ap_Reg_8_11, ap_ImmSigned8_32_39, ap_Mask_12_15, ap_RegImSigned16_16_31}}, + {CIT, 0xff00000000ff0000, 0xec00000000720000, 0xf00000f000000, // COMPARE IMMEDIATE AND TRAP (32→16) (CIT R1,I2,M3) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35}}, + {CGIT, 0xff00000000ff0000, 0xec00000000700000, 0xf00000f000000, // COMPARE IMMEDIATE AND TRAP (64←16) (CGIT R1,I2,M3) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35}}, + {CIH, 0xff0f000000000000, 0xcc0d000000000000, 0x0, // COMPARE IMMEDIATE HIGH (32) (CIH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {CL, 0xff00000000000000, 0x5500000000000000, 0x0, // COMPARE LOGICAL (32) (CL R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CLR, 0xff00000000000000, 0x1500000000000000, 0x0, // COMPARE LOGICAL (32) (CLR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {CLY, 0xff00000000ff0000, 0xe300000000550000, 0x0, // COMPARE LOGICAL (32) (CLY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CLG, 0xff00000000ff0000, 0xe300000000210000, 0x0, // COMPARE LOGICAL (64) (CLG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CLGR, 0xffff000000000000, 0xb921000000000000, 0xff0000000000, // COMPARE LOGICAL (64) (CLGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CLGF, 0xff00000000ff0000, 0xe300000000310000, 0x0, // COMPARE LOGICAL (64→32) (CLGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CLGFR, 0xffff000000000000, 0xb931000000000000, 0xff0000000000, // COMPARE LOGICAL (64→32) (CLGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CLC, 0xff00000000000000, 0xd500000000000000, 0x0, // COMPARE LOGICAL (character) (CLC D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {CLI, 0xff00000000000000, 0x9500000000000000, 0x0, // COMPARE LOGICAL (immediate) (CLI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {CLIY, 0xff00000000ff0000, 0xeb00000000550000, 0x0, // COMPARE LOGICAL (immediate) (CLIY D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {CLRB, 0xff00000000ff0000, 0xec00000000f70000, 0xf000000, // COMPARE LOGICAL AND BRANCH (32) (CLRB R1,R2,M3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CLGRB, 0xff00000000ff0000, 0xec00000000e50000, 0xf000000, // COMPARE LOGICAL AND BRANCH (64) (CLGRB R1,R2,M3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CLRJ, 0xff00000000ff0000, 0xec00000000770000, 0xf000000, // COMPARE LOGICAL AND BRANCH RELATIVE(32) (CLRJ R1,R2,M3,RI4) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_RegImSigned16_16_31}}, + {CLGRJ, 0xff00000000ff0000, 0xec00000000650000, 0xf000000, // COMPARE LOGICAL AND BRANCH RELATIVE(64) (CLGRJ R1,R2,M3,RI4) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_Mask_32_35, ap_RegImSigned16_16_31}}, + {CLRT, 0xffff000000000000, 0xb973000000000000, 0xf0000000000, // COMPARE LOGICAL AND TRAP (32) (CLRT R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {CLT, 0xff00000000ff0000, 0xeb00000000230000, 0x0, // COMPARE LOGICAL AND TRAP (32) (CLT R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CLGRT, 0xffff000000000000, 0xb961000000000000, 0xf0000000000, // COMPARE LOGICAL AND TRAP (64) (CLGRT R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {CLGT, 0xff00000000ff0000, 0xeb000000002b0000, 0x0, // COMPARE LOGICAL AND TRAP (64) (CLGT R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CLMH, 0xff00000000ff0000, 0xeb00000000200000, 0x0, // COMPARE LOGICAL CHAR. UNDER MASK (high) (CLMH R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CLM, 0xff00000000000000, 0xbd00000000000000, 0x0, // COMPARE LOGICAL CHAR. UNDER MASK (low) (CLM R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CLMY, 0xff00000000ff0000, 0xeb00000000210000, 0x0, // COMPARE LOGICAL CHAR. UNDER MASK (low) (CLMY R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CLHF, 0xff00000000ff0000, 0xe300000000cf0000, 0x0, // COMPARE LOGICAL HIGH (32) (CLHF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CLHHR, 0xffff000000000000, 0xb9cf000000000000, 0xff0000000000, // COMPARE LOGICAL HIGH (32) (CLHHR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CLHLR, 0xffff000000000000, 0xb9df000000000000, 0xff0000000000, // COMPARE LOGICAL HIGH (32) (CLHLR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CLHHSI, 0xffff000000000000, 0xe555000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (16←16) (CLHHSI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}}, + {CLFI, 0xff0f000000000000, 0xc20f000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (32) (CLFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {CLFHSI, 0xffff000000000000, 0xe55d000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (32←16) (CLFHSI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}}, + {CLGHSI, 0xffff000000000000, 0xe559000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (64←16) (CLGHSI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}}, + {CLGFI, 0xff0f000000000000, 0xc20e000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE (64←32) (CLGFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {CLIB, 0xff00000000ff0000, 0xec00000000ff0000, 0x0, // COMPARE LOGICAL IMMEDIATE AND BRANCH(32←8) (CLIB R1,I2,M3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_32_39, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CLGIB, 0xff00000000ff0000, 0xec00000000fd0000, 0x0, // COMPARE LOGICAL IMMEDIATE AND BRANCH(64→8) (CLGIB R1,I2,M3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_32_39, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CLIJ, 0xff00000000ff0000, 0xec000000007f0000, 0x0, // COMPARE LOGICAL IMMEDIATE AND BRANCH (CLIJ R1,I2,M3,RI4) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_32_39, ap_Mask_12_15, ap_RegImSigned16_16_31}}, + {CLGIJ, 0xff00000000ff0000, 0xec000000007d0000, 0x0, // RELATIVE (32→8)10COMPARE LOGICAL IMMEDIATE AND BRANCH (CLGIJ R1,I2,M3,RI4) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_32_39, ap_Mask_12_15, ap_RegImSigned16_16_31}}, + {CLFIT, 0xff00000000ff0000, 0xec00000000730000, 0xf00000f000000, // RELATIVE (64→8)COMPARE LOGICAL IMMEDIATE AND TRAP(32→16) (CLFIT R1,I2,M3) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35}}, + {CLGIT, 0xff00000000ff0000, 0xec00000000710000, 0xf00000f000000, // COMPARE LOGICAL IMMEDIATE AND TRAP(64←16) (CLGIT R1,I2,M3) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35}}, + {CLIH, 0xff0f000000000000, 0xcc0f000000000000, 0x0, // COMPARE LOGICAL IMMEDIATE HIGH (32) (CLIH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {CLCL, 0xff00000000000000, 0xf00000000000000, 0x0, // COMPARE LOGICAL LONG (CLCL R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {CLCLE, 0xff00000000000000, 0xa900000000000000, 0x0, // COMPARE LOGICAL LONG EXTENDED (CLCLE R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {CLCLU, 0xff00000000ff0000, 0xeb000000008f0000, 0x0, // COMPARE LOGICAL LONG UNICODE (CLCLU R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {CLRL, 0xff0f000000000000, 0xc60f000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (32) (CLRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CLHRL, 0xff0f000000000000, 0xc607000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (32→16) (CLHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CLGRL, 0xff0f000000000000, 0xc60a000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (64) (CLGRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CLGHRL, 0xff0f000000000000, 0xc606000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (64→16) (CLGHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CLGFRL, 0xff0f000000000000, 0xc60e000000000000, 0x0, // COMPARE LOGICAL RELATIVE LONG (64→32) (CLGFRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CLST, 0xffff000000000000, 0xb25d000000000000, 0xff0000000000, // COMPARE LOGICAL STRING (CLST R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CRL, 0xff0f000000000000, 0xc60d000000000000, 0x0, // COMPARE RELATIVE LONG (32) (CRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CGRL, 0xff0f000000000000, 0xc608000000000000, 0x0, // COMPARE RELATIVE LONG (64) (CGRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CGFRL, 0xff0f000000000000, 0xc60c000000000000, 0x0, // COMPARE RELATIVE LONG (64←32) (CGFRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {CUSE, 0xffff000000000000, 0xb257000000000000, 0xff0000000000, // COMPARE UNTIL SUBSTRING EQUAL (CUSE R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CMPSC, 0xffff000000000000, 0xb263000000000000, 0xff0000000000, // COMPRESSION CALL (CMPSC R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {KDSA, 0xffff000000000000, 0xb93a000000000000, 0xff0000000000, // COMPUTE DIGITAL SIGNATURE AUTHENTICATION (KDSA R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {KIMD, 0xffff000000000000, 0xb93e000000000000, 0xff0000000000, // COMPUTE INTERMEDIATE MESSAGE DIGEST (KIMD R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {KLMD, 0xffff000000000000, 0xb93f000000000000, 0xff0000000000, // COMPUTE LAST MESSAGE DIGEST (KLMD R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {KMAC, 0xffff000000000000, 0xb91e000000000000, 0xff0000000000, // COMPUTE MESSAGE AUTHENTICATION CODE (KMAC R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {THDR, 0xffff000000000000, 0xb359000000000000, 0xff0000000000, // CONVERT BFP TO HFP (long) (THDR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {THDER, 0xffff000000000000, 0xb358000000000000, 0xff0000000000, // CONVERT BFP TO HFP (short to long) (THDER R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {CXFBR, 0xffff000000000000, 0xb396000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to extended BFP) (CXFBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CXFBRA, 0xffff000000000000, 0xb396000000000000, 0x0, // CONVERT FROM FIXED (32 to extended BFP) (CXFBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CXFTR, 0xffff000000000000, 0xb959000000000000, 0x0, // CONVERT FROM FIXED (32 to extended DFP) (CXFTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CXFR, 0xffff000000000000, 0xb3b6000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to extended HFP) (CXFR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CDFBR, 0xffff000000000000, 0xb395000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to long BFP) (CDFBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CDFBRA, 0xffff000000000000, 0xb395000000000000, 0x0, // CONVERT FROM FIXED (32 to long BFP) (CDFBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CDFTR, 0xffff000000000000, 0xb951000000000000, 0x0, // CONVERT FROM FIXED (32 to long DFP) (CDFTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CDFR, 0xffff000000000000, 0xb3b5000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to long HFP) (CDFR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CEFBR, 0xffff000000000000, 0xb394000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to short BFP) (CEFBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CEFBRA, 0xffff000000000000, 0xb394000000000000, 0x0, // CONVERT FROM FIXED (32 to short BFP) (CEFBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CEFR, 0xffff000000000000, 0xb3b4000000000000, 0xff0000000000, // CONVERT FROM FIXED (32 to short HFP) (CEFR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CXGBR, 0xffff000000000000, 0xb3a6000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to extended BFP) (CXGBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CXGBRA, 0xffff000000000000, 0xb3a6000000000000, 0x0, // CONVERT FROM FIXED (64 to extended BFP) (CXGBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CXGTR, 0xffff000000000000, 0xb3f9000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to extended DFP) (CXGTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CXGTRA, 0xffff000000000000, 0xb3f9000000000000, 0x0, // CONVERT FROM FIXED (64 to extended DFP) (CXGTRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CXGR, 0xffff000000000000, 0xb3c6000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to extended HFP) (CXGR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CDGBR, 0xffff000000000000, 0xb3a5000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to long BFP) (CDGBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CDGBRA, 0xffff000000000000, 0xb3a5000000000000, 0x0, // CONVERT FROM FIXED (64 to long BFP) (CDGBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CDGTR, 0xffff000000000000, 0xb3f1000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to long DFP) (CDGTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CDGTRA, 0xffff000000000000, 0xb3f1000000000000, 0x0, // CONVERT FROM FIXED (64 to long DFP) (CDGTRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CDGR, 0xffff000000000000, 0xb3c5000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to long HFP) (CDGR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CEGBR, 0xffff000000000000, 0xb3a4000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to short BFP) (CEGBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CEGBRA, 0xffff000000000000, 0xb3a4000000000000, 0x0, // CONVERT FROM FIXED (64 to short BFP) (CEGBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CEGR, 0xffff000000000000, 0xb3c4000000000000, 0xff0000000000, // CONVERT FROM FIXED (64 to short HFP) (CEGR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CXLFBR, 0xffff000000000000, 0xb392000000000000, 0x0, // CONVERT FROM LOGICAL (32 to extended BFP) (CXLFBR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CXLFTR, 0xffff000000000000, 0xb95b000000000000, 0x0, // CONVERT FROM LOGICAL (32 to extended DFP) (CXLFTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CDLFBR, 0xffff000000000000, 0xb391000000000000, 0x0, // CONVERT FROM LOGICAL (32 to long BFP) (CDLFBR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CDLFTR, 0xffff000000000000, 0xb953000000000000, 0x0, // CONVERT FROM LOGICAL (32 to long DFP) (CDLFTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CELFBR, 0xffff000000000000, 0xb390000000000000, 0x0, // CONVERT FROM LOGICAL (32 to short BFP) (CELFBR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CXLGBR, 0xffff000000000000, 0xb3a2000000000000, 0x0, // CONVERT FROM LOGICAL (64 to extended BFP) (CXLGBR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CXLGTR, 0xffff000000000000, 0xb95a000000000000, 0x0, // CONVERT FROM LOGICAL (64 to extended DFP) (CXLGTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CDLGBR, 0xffff000000000000, 0xb3a1000000000000, 0x0, // CONVERT FROM LOGICAL (64 to long BFP) (CDLGBR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CDLGTR, 0xffff000000000000, 0xb952000000000000, 0x0, // CONVERT FROM LOGICAL (64 to long DFP) (CDLGTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CELGBR, 0xffff000000000000, 0xb3a0000000000000, 0x0, // CONVERT FROM LOGICAL (64 to short BFP) (CELGBR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {CXPT, 0xff00000000ff0000, 0xed00000000af0000, 0x0, // CONVERT FROM PACKED (to extended DFP) (CXPT R1,D2(L2,B2),M3) + [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}}, + {CDPT, 0xff00000000ff0000, 0xed00000000ae0000, 0x0, // CONVERT FROM PACKED (to long DFP) (CDPT R1,D2(L2,B2),M3) + [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}}, + {CXSTR, 0xffff000000000000, 0xb3fb000000000000, 0xff0000000000, // CONVERT FROM SIGNED PACKED (128 to extended DFP) (CXSTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CDSTR, 0xffff000000000000, 0xb3f3000000000000, 0xff0000000000, // CONVERT FROM SIGNED PACKED (64 to long DFP) (CDSTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CXUTR, 0xffff000000000000, 0xb3fa000000000000, 0xff0000000000, // CONVERT FROM UNSIGNED PACKED (128 to ext. DFP) (CXUTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CDUTR, 0xffff000000000000, 0xb3f2000000000000, 0xff0000000000, // CONVERT FROM UNSIGNED PACKED (64 to long DFP) (CDUTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {CXZT, 0xff00000000ff0000, 0xed00000000ab0000, 0x0, // CONVERT FROM ZONED (to extended DFP) (CXZT R1,D2(L2,B2),M3) + [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}}, + {CDZT, 0xff00000000ff0000, 0xed00000000aa0000, 0x0, // CONVERT FROM ZONED (to long DFP) (CDZT R1,D2(L2,B2),M3) + [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}}, + {TBEDR, 0xffff000000000000, 0xb350000000000000, 0xf0000000000, // CONVERT HFP TO BFP (long to short) (TBEDR R1,M3,R2) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {TBDR, 0xffff000000000000, 0xb351000000000000, 0xf0000000000, // CONVERT HFP TO BFP (long) (TBDR R1,M3,R2) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CVB, 0xff00000000000000, 0x4f00000000000000, 0x0, // CONVERT TO BINARY (32) (CVB R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CVBY, 0xff00000000ff0000, 0xe300000000060000, 0x0, // CONVERT TO BINARY (32) (CVBY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CVBG, 0xff00000000ff0000, 0xe3000000000e0000, 0x0, // CONVERT TO BINARY (64) (CVBG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CVD, 0xff00000000000000, 0x4e00000000000000, 0x0, // CONVERT TO DECIMAL (32) (CVD R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CVDY, 0xff00000000ff0000, 0xe300000000260000, 0x0, // CONVERT TO DECIMAL (32) (CVDY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CVDG, 0xff00000000ff0000, 0xe3000000002e0000, 0x0, // CONVERT TO DECIMAL (64) (CVDG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {CFXBR, 0xffff000000000000, 0xb39a000000000000, 0xf0000000000, // CONVERT TO FIXED (extended BFP to 32) (CFXBR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CFXBRA, 0xffff000000000000, 0xb39a000000000000, 0x0, // CONVERT TO FIXED (extended BFP to 32) (CFXBRA R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CGXBR, 0xffff000000000000, 0xb3aa000000000000, 0xf0000000000, // CONVERT TO FIXED (extended BFP to 64) (CGXBR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CGXBRA, 0xffff000000000000, 0xb3aa000000000000, 0x0, // CONVERT TO FIXED (extended BFP to 64) (CGXBRA R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CFXTR, 0xffff000000000000, 0xb949000000000000, 0x0, // CONVERT TO FIXED (extended DFP to 32) (CFXTR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CGXTR, 0xffff000000000000, 0xb3e9000000000000, 0xf0000000000, // CONVERT TO FIXED (extended DFP to 64) (CGXTR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CGXTRA, 0xffff000000000000, 0xb3e9000000000000, 0x0, // CONVERT TO FIXED (extended DFP to 64) (CGXTRA R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CFXR, 0xffff000000000000, 0xb3ba000000000000, 0xf0000000000, // CONVERT TO FIXED (extended HFP to 32) (CFXR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CGXR, 0xffff000000000000, 0xb3ca000000000000, 0xf0000000000, // CONVERT TO FIXED (extended HFP to 64) (CGXR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CFDBR, 0xffff000000000000, 0xb399000000000000, 0xf0000000000, // CONVERT TO FIXED (long BFP to 32) (CFDBR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CFDBRA, 0xffff000000000000, 0xb399000000000000, 0x0, // CONVERT TO FIXED (long BFP to 32) (CFDBRA R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CGDBR, 0xffff000000000000, 0xb3a9000000000000, 0xf0000000000, // CONVERT TO FIXED (long BFP to 64) (CGDBR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CGDBRA, 0xffff000000000000, 0xb3a9000000000000, 0x0, // CONVERT TO FIXED (long BFP to 64) (CGDBRA R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CFDTR, 0xffff000000000000, 0xb941000000000000, 0x0, // CONVERT TO FIXED (long DFP to 32) (CFDTR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CGDTR, 0xffff000000000000, 0xb3e1000000000000, 0xf0000000000, // CONVERT TO FIXED (long DFP to 64) (CGDTR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CGDTRA, 0xffff000000000000, 0xb3e1000000000000, 0x0, // CONVERT TO FIXED (long DFP to 64) (CGDTRA R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CFDR, 0xffff000000000000, 0xb3b9000000000000, 0xf0000000000, // CONVERT TO FIXED (long HFP to 32) (CFDR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CGDR, 0xffff000000000000, 0xb3c9000000000000, 0xf0000000000, // CONVERT TO FIXED (long HFP to 64) (CGDR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CFEBR, 0xffff000000000000, 0xb398000000000000, 0xf0000000000, // CONVERT TO FIXED (short BFP to 32) (CFEBR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CFEBRA, 0xffff000000000000, 0xb398000000000000, 0x0, // CONVERT TO FIXED (short BFP to 32) (CFEBRA R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CGEBR, 0xffff000000000000, 0xb3a8000000000000, 0xf0000000000, // CONVERT TO FIXED (short BFP to 64) (CGEBR R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CGEBRA, 0xffff000000000000, 0xb3a8000000000000, 0x0, // CONVERT TO FIXED (short BFP to 64) (CGEBRA R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CFER, 0xffff000000000000, 0xb3b8000000000000, 0xf0000000000, // CONVERT TO FIXED (short HFP to 32) (CFER R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CGER, 0xffff000000000000, 0xb3c8000000000000, 0xf0000000000, // CONVERT TO FIXED (short HFP to 64) (CGER R1,M3,R2) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {CLFXBR, 0xffff000000000000, 0xb39e000000000000, 0x0, // CONVERT TO LOGICAL (extended BFP to 32) (CLFXBR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLGXBR, 0xffff000000000000, 0xb3ae000000000000, 0x0, // CONVERT TO LOGICAL (extended BFP to 64) (CLGXBR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLFXTR, 0xffff000000000000, 0xb94b000000000000, 0x0, // CONVERT TO LOGICAL (extended DFP to 32) (CLFXTR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLGXTR, 0xffff000000000000, 0xb94a000000000000, 0x0, // CONVERT TO LOGICAL (extended DFP to 64) (CLGXTR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLFDBR, 0xffff000000000000, 0xb39d000000000000, 0x0, // CONVERT TO LOGICAL (long BFP to 32) (CLFDBR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLGDBR, 0xffff000000000000, 0xb3ad000000000000, 0x0, // CONVERT TO LOGICAL (long BFP to 64) (CLGDBR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLFDTR, 0xffff000000000000, 0xb943000000000000, 0x0, // CONVERT TO LOGICAL (long DFP to 32) (CLFDTR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLGDTR, 0xffff000000000000, 0xb942000000000000, 0x0, // CONVERT TO LOGICAL (long DFP to 64) (CLGDTR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLFEBR, 0xffff000000000000, 0xb39c000000000000, 0x0, // CONVERT TO LOGICAL (short BFP to 32) (CLFEBR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CLGEBR, 0xffff000000000000, 0xb3ac000000000000, 0x0, // CONVERT TO LOGICAL (short BFP to 64) (CLGEBR R1,M3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {CPXT, 0xff00000000ff0000, 0xed00000000ad0000, 0x0, // CONVERT TO PACKED (from extended DFP) (CPXT R1,D2(L2,B2),M3) + [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}}, + {CPDT, 0xff00000000ff0000, 0xed00000000ac0000, 0x0, // CONVERT TO PACKED (from long DFP) (CPDT R1,D2(L2,B2),M3) + [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}}, + {CSXTR, 0xffff000000000000, 0xb3eb000000000000, 0xf00000000000, // CONVERT TO SIGNED PACKED (extended DFP to 128) (CSXTR R1,R2,M4) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31, ap_Mask_20_23}}, + {CSDTR, 0xffff000000000000, 0xb3e3000000000000, 0xf00000000000, // CONVERT TO SIGNED PACKED (long DFP to 64) (CSDTR R1,R2,M4) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31, ap_Mask_20_23}}, + {CUXTR, 0xffff000000000000, 0xb3ea000000000000, 0xff0000000000, // CONVERTTOUNSIGNEDPACKED(extendedDFP to 128) (CUXTR R1,R2) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}}, + {CUDTR, 0xffff000000000000, 0xb3e2000000000000, 0xff0000000000, // CONVERT TO UNSIGNED PACKED (long DFP to 64) (CUDTR R1,R2) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}}, + {CZXT, 0xff00000000ff0000, 0xed00000000a90000, 0x0, // CONVERT TO ZONED (from extended DFP) (CZXT R1,D2(L2,B2),M3) + [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}}, + {CZDT, 0xff00000000ff0000, 0xed00000000a80000, 0x0, // CONVERT TO ZONED (from long DFP) (CZDT R1,D2(L2,B2),M3) + [8]*argField{ap_FPReg_32_35, ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_Mask_36_39}}, + {CU24, 0xffff000000000000, 0xb9b1000000000000, 0xf0000000000, // CONVERT UTF-16 TO UTF-32 (CU24 R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {CU21, 0xffff000000000000, 0xb2a6000000000000, 0xf0000000000, // CONVERT UTF-16 TO UTF-8 (CU21 R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {CU12, 0xffff000000000000, 0xb2a7000000000000, 0xf0000000000, // CONVERT UTF-8 TO UTF-16 (CU12 R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {CU14, 0xffff000000000000, 0xb9b0000000000000, 0xf0000000000, // CONVERT UTF-8 TO UTF-32 (CU14 R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {CU42, 0xffff000000000000, 0xb9b3000000000000, 0xff0000000000, // CONVERT UTF-32 TO UTF-16 (CU42 R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CU41, 0xffff000000000000, 0xb9b2000000000000, 0xff0000000000, // CONVERT UTF-32 TO UTF-8 (CU41 R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {CPYA, 0xffff000000000000, 0xb24d000000000000, 0xff0000000000, // COPY ACCESS (CPYA R1,R2) + [8]*argField{ap_ACReg_24_27, ap_ACReg_28_31}}, + {CPSDR, 0xffff000000000000, 0xb372000000000000, 0xf0000000000, // COPY SIGN (long) (CPSDR R1,R3,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31}}, + {VSCSHP, 0xff00000000ff0000, 0xe6000000007c0000, 0xffff0000000, // DECIMAL SCALE AND CONVERT AND SPLIT TO HFP (VSCSHP V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VSCHP, 0xff00000000ff0000, 0xe600000000740000, 0xf0f00000000, // DECIMAL SCALE AND CONVERT TO HFP (VSCHP V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {DFLTCC, 0xffff000000000000, 0xb939000000000000, 0xf0000000000, // DEFLATE CONVERSION CALL (DFLTCC R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {D, 0xff00000000000000, 0x5d00000000000000, 0x0, // DIVIDE (32→64) (D R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DR, 0xff00000000000000, 0x1d00000000000000, 0x0, // DIVIDE (32←64) (DR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {DXBR, 0xffff000000000000, 0xb34d000000000000, 0xff0000000000, // DIVIDE (extended BFP) (DXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {DXTR, 0xffff000000000000, 0xb3d9000000000000, 0xf0000000000, // DIVIDE (extended DFP) (DXTR R1,R2,R3) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}}, + {DXTRA, 0xffff000000000000, 0xb3d9000000000000, 0x0, // DIVIDE (extended DFP) (DXTRA R1,R2,R3,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}}, + {DXR, 0xffff000000000000, 0xb22d000000000000, 0xff0000000000, // DIVIDE (extended HFP) (DXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {DDB, 0xff00000000ff0000, 0xed000000001d0000, 0xff000000, // DIVIDE (long BFP) (DDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DDBR, 0xffff000000000000, 0xb31d000000000000, 0xff0000000000, // DIVIDE (long BFP) (DDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {DDTR, 0xffff000000000000, 0xb3d1000000000000, 0xf0000000000, // DIVIDE (long DFP) (DDTR R1,R2,R3) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}}, + {DDTRA, 0xffff000000000000, 0xb3d1000000000000, 0x0, // DIVIDE (long DFP) (DDTRA R1,R2,R3,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}}, + {DD, 0xff00000000000000, 0x6d00000000000000, 0x0, // DIVIDE (long HFP) (DD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DDR, 0xff00000000000000, 0x2d00000000000000, 0x0, // DIVIDE (long HFP) (DDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {DEB, 0xff00000000ff0000, 0xed000000000d0000, 0xff000000, // DIVIDE (short BFP) (DEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DEBR, 0xffff000000000000, 0xb30d000000000000, 0xff0000000000, // DIVIDE (short BFP) (DEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {DE, 0xff00000000000000, 0x7d00000000000000, 0x0, // DIVIDE (short HFP) (DE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DER, 0xff00000000000000, 0x3d00000000000000, 0x0, // DIVIDE (short HFP) (DER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {DP, 0xff00000000000000, 0xfd00000000000000, 0x0, // DIVIDE DECIMAL (DP D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, + {DL, 0xff00000000ff0000, 0xe300000000970000, 0x0, // DIVIDE LOGICAL (32→64) (DL R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DLR, 0xffff000000000000, 0xb997000000000000, 0xff0000000000, // DIVIDE LOGICAL (32←64) (DLR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {DLG, 0xff00000000ff0000, 0xe300000000870000, 0x0, // DIVIDE LOGICAL (64←128) (DLG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DLGR, 0xffff000000000000, 0xb987000000000000, 0xff0000000000, // DIVIDE LOGICAL (64→128) (DLGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {DSG, 0xff00000000ff0000, 0xe3000000000d0000, 0x0, // DIVIDE SINGLE (64) (DSG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DSGR, 0xffff000000000000, 0xb90d000000000000, 0xff0000000000, // DIVIDE SINGLE (64) (DSGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {DSGF, 0xff00000000ff0000, 0xe3000000001d0000, 0x0, // DIVIDE SINGLE (64←32) (DSGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {DSGFR, 0xffff000000000000, 0xb91d000000000000, 0xff0000000000, // DIVIDE SINGLE (64→32) (DSGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {DIDBR, 0xffff000000000000, 0xb35b000000000000, 0x0, // DIVIDE TO INTEGER (long BFP) (DIDBR R1,R3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {DIEBR, 0xffff000000000000, 0xb353000000000000, 0x0, // DIVIDE TO INTEGER (short BFP) (DIEBR R1,R3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {ED, 0xff00000000000000, 0xde00000000000000, 0x0, // EDIT (ED D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {EDMK, 0xff00000000000000, 0xdf00000000000000, 0x0, // EDIT AND MARK (EDMK D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {X, 0xff00000000000000, 0x5700000000000000, 0x0, // EXCLUSIVE OR (32) (X R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {XR, 0xff00000000000000, 0x1700000000000000, 0x0, // EXCLUSIVE OR (32) (XR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {XRK, 0xffff000000000000, 0xb9f7000000000000, 0xf0000000000, // EXCLUSIVE OR (32) (XRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {XY, 0xff00000000ff0000, 0xe300000000570000, 0x0, // EXCLUSIVE OR (32) (XY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {XG, 0xff00000000ff0000, 0xe300000000820000, 0x0, // EXCLUSIVE OR (64) (XG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {XGR, 0xffff000000000000, 0xb982000000000000, 0xff0000000000, // EXCLUSIVE OR (64) (XGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {XGRK, 0xffff000000000000, 0xb9e7000000000000, 0xf0000000000, // EXCLUSIVE OR (64) (XGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {XC, 0xff00000000000000, 0xd700000000000000, 0x0, // EXCLUSIVE OR (character) (XC D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {XI, 0xff00000000000000, 0x9700000000000000, 0x0, // EXCLUSIVE OR (immediate) (XI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {XIY, 0xff00000000ff0000, 0xeb00000000570000, 0x0, // EXCLUSIVE OR (immediate) (XIY D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {XIHF, 0xff0f000000000000, 0xc006000000000000, 0x0, // EXCLUSIVE OR IMMEDIATE (high) (XIHF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {XILF, 0xff0f000000000000, 0xc007000000000000, 0x0, // EXCLUSIVE OR IMMEDIATE (low) (XILF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {EX, 0xff00000000000000, 0x4400000000000000, 0x0, // EXECUTE (EX R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {EXRL, 0xff0f000000000000, 0xc600000000000000, 0x0, // EXECUTE RELATIVE LONG (EXRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {EAR, 0xffff000000000000, 0xb24f000000000000, 0xff0000000000, // EXTRACT ACCESS (EAR R1,R2) + [8]*argField{ap_Reg_24_27, ap_ACReg_28_31}}, + {ESEA, 0xffff000000000000, 0xb99d000000000000, 0xff0f00000000, // EXTRACT AND SET EXTENDED AUTHORITY (ESEA R1) + [8]*argField{ap_Reg_24_27}}, + {EEXTR, 0xffff000000000000, 0xb3ed000000000000, 0xff0000000000, // EXTRACT BIASED EXPONENT (extended DFP to 64) (EEXTR R1,R2) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}}, + {EEDTR, 0xffff000000000000, 0xb3e5000000000000, 0xff0000000000, // EXTRACT BIASED EXPONENT (long DFP to 64) (EEDTR R1,R2) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}}, + {ECAG, 0xff00000000ff0000, 0xeb000000004c0000, 0x0, // EXTRACT CPU ATTRIBUTE (ECAG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {ECTG, 0xff0f000000000000, 0xc801000000000000, 0x0, // EXTRACT CPU TIME (ECTG D1(B1),D2(B2),R3) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_8_11}}, + {EFPC, 0xffff000000000000, 0xb38c000000000000, 0xff0f00000000, // EXTRACT FPC (EFPC R1) + [8]*argField{ap_Reg_24_27}}, + {EPAR, 0xffff000000000000, 0xb226000000000000, 0xff0f00000000, // EXTRACT PRIMARY ASN (EPAR R1) + [8]*argField{ap_Reg_24_27}}, + {EPAIR, 0xffff000000000000, 0xb99a000000000000, 0xff0f00000000, // EXTRACT PRIMARY ASN AND INSTANCE (EPAIR R1) + [8]*argField{ap_Reg_24_27}}, + {EPSW, 0xffff000000000000, 0xb98d000000000000, 0xff0000000000, // EXTRACT PSW (EPSW R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ESAR, 0xffff000000000000, 0xb227000000000000, 0xff0f00000000, // EXTRACT SECONDARY ASN (ESAR R1) + [8]*argField{ap_Reg_24_27}}, + {ESAIR, 0xffff000000000000, 0xb99b000000000000, 0xff0f00000000, // EXTRACT SECONDARY ASN AND INSTANCE (ESAIR R1) + [8]*argField{ap_Reg_24_27}}, + {ESXTR, 0xffff000000000000, 0xb3ef000000000000, 0xff0000000000, // EXTRACT SIGNIFICANCE (extended DFP to 64) (ESXTR R1,R2) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}}, + {ESDTR, 0xffff000000000000, 0xb3e7000000000000, 0xff0000000000, // EXTRACT SIGNIFICANCE (long DFP to 64) (ESDTR R1,R2) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}}, + {EREG, 0xffff000000000000, 0xb249000000000000, 0xff0000000000, // EXTRACT STACKED REGISTERS (32) (EREG R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {EREGG, 0xffff000000000000, 0xb90e000000000000, 0xff0000000000, // EXTRACT STACKED REGISTERS (64) (EREGG R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ESTA, 0xffff000000000000, 0xb24a000000000000, 0xff0000000000, // EXTRACT STACKED STATE (ESTA R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ETND, 0xffff000000000000, 0xb2ec000000000000, 0xff0f00000000, // EXTRACT TRANSACTION NESTING DEPTH (ETND R1) + [8]*argField{ap_Reg_24_27}}, + {FLOGR, 0xffff000000000000, 0xb983000000000000, 0xff0000000000, // FIND LEFTMOST ONE (FLOGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {HSCH, 0xffff000000000000, 0xb231000000000000, 0xffff00000000, // HALT SUBCHANNEL (HSCH) + [8]*argField{}}, + {HDR, 0xff00000000000000, 0x2400000000000000, 0x0, // HALVE (long HFP) (HDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {HER, 0xff00000000000000, 0x3400000000000000, 0x0, // HALVE (short HFP) (HER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {IAC, 0xffff000000000000, 0xb224000000000000, 0xff0f00000000, // INSERT ADDRESS SPACE CONTROL (IAC R1) + [8]*argField{ap_Reg_24_27}}, + {IEXTR, 0xffff000000000000, 0xb3fe000000000000, 0xf0000000000, // INSERT BIASED EXPONENT (64 to extended DFP) (IEXTR R1,R3,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_Reg_28_31}}, + {IEDTR, 0xffff000000000000, 0xb3f6000000000000, 0xf0000000000, // INSERT BIASED EXPONENT (64 to long DFP) (IEDTR R1,R3,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_Reg_28_31}}, + {IC, 0xff00000000000000, 0x4300000000000000, 0x0, // INSERT CHARACTER (IC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ICY, 0xff00000000ff0000, 0xe300000000730000, 0x0, // INSERT CHARACTER (ICY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {ICMH, 0xff00000000ff0000, 0xeb00000000800000, 0x0, // INSERT CHARACTERS UNDER MASK (high) (ICMH R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {ICM, 0xff00000000000000, 0xbf00000000000000, 0x0, // INSERT CHARACTERS UNDER MASK (low) (ICM R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {ICMY, 0xff00000000ff0000, 0xeb00000000810000, 0x0, // INSERT CHARACTERS UNDER MASK (low) (ICMY R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {IIHH, 0xff0f000000000000, 0xa500000000000000, 0x0, // INSERT IMMEDIATE (high high) (IIHH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {IIHL, 0xff0f000000000000, 0xa501000000000000, 0x0, // INSERT IMMEDIATE (high low) (IIHL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {IIHF, 0xff0f000000000000, 0xc008000000000000, 0x0, // INSERT IMMEDIATE (high) (IIHF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {IILH, 0xff0f000000000000, 0xa502000000000000, 0x0, // INSERT IMMEDIATE (low high) (IILH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {IILL, 0xff0f000000000000, 0xa503000000000000, 0x0, // INSERT IMMEDIATE (low low) (IILL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {IILF, 0xff0f000000000000, 0xc009000000000000, 0x0, // INSERT IMMEDIATE (low) (IILF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {IPM, 0xffff000000000000, 0xb222000000000000, 0xff0f00000000, // INSERT PROGRAM MASK (IPM R1) + [8]*argField{ap_Reg_24_27}}, + {IPK, 0xffff000000000000, 0xb20b000000000000, 0xffff00000000, // INSERT PSW KEY (IPK) + [8]*argField{}}, + {IRBM, 0xffff000000000000, 0xb9ac000000000000, 0xff0000000000, // INSERT REFERENCE BITS MULTIPLE (IRBM R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ISKE, 0xffff000000000000, 0xb229000000000000, 0xff0000000000, // INSERT STORAGE KEY EXTENDED (ISKE R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {IVSK, 0xffff000000000000, 0xb223000000000000, 0xff0000000000, // INSERT VIRTUAL STORAGE KEY (IVSK R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {IDTE, 0xffff000000000000, 0xb98e000000000000, 0x0, // INVALIDATE DAT TABLE ENTRY (IDTE R1,R3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {IPTE, 0xffff000000000000, 0xb221000000000000, 0x0, // INVALIDATE PAGE TABLE ENTRY (IPTE R1,R2,R3,M4) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19, ap_Mask_20_23}}, + {L, 0xff00000000000000, 0x5800000000000000, 0x0, // LOAD (32) (L R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LR, 0xff00000000000000, 0x1800000000000000, 0x0, // LOAD (32) (LR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {LY, 0xff00000000ff0000, 0xe300000000580000, 0x0, // LOAD (32) (LY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LG, 0xff00000000ff0000, 0xe300000000040000, 0x0, // LOAD (64) (LG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LGR, 0xffff000000000000, 0xb904000000000000, 0xff0000000000, // LOAD (64) (LGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LGF, 0xff00000000ff0000, 0xe300000000140000, 0x0, // LOAD (64←32) (LGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LGFR, 0xffff000000000000, 0xb914000000000000, 0xff0000000000, // LOAD (64←32) (LGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LXR, 0xffff000000000000, 0xb365000000000000, 0xff0000000000, // LOAD (extended) (LXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LD, 0xff00000000000000, 0x6800000000000000, 0x0, // LOAD (long) (LD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LDR, 0xff00000000000000, 0x2800000000000000, 0x0, // LOAD (long) (LDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LDY, 0xff00000000ff0000, 0xed00000000650000, 0x0, // LOAD (long) (LDY R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LE, 0xff00000000000000, 0x7800000000000000, 0x0, // LOAD (short) (LE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LER, 0xff00000000000000, 0x3800000000000000, 0x0, // LOAD (short) (LER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LEY, 0xff00000000ff0000, 0xed00000000640000, 0x0, // LOAD (short) (LEY R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LAM, 0xff00000000000000, 0x9a00000000000000, 0x0, // LOAD ACCESS MULTIPLE 7-268 (LAM R1,R3,D2(B2)) + [8]*argField{ap_ACReg_8_11, ap_ACReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {LAMY, 0xff00000000ff0000, 0xeb000000009a0000, 0x0, // LOAD ACCESS MULTIPLE 7-268 (LAMY R1,R3,D2(B2)) + [8]*argField{ap_ACReg_8_11, ap_ACReg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LA, 0xff00000000000000, 0x4100000000000000, 0x0, // LOAD ADDRESS (LA R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LAY, 0xff00000000ff0000, 0xe300000000710000, 0x0, // LOAD ADDRESS (LAY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LAE, 0xff00000000000000, 0x5100000000000000, 0x0, // LOAD ADDRESS EXTENDED (LAE R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LAEY, 0xff00000000ff0000, 0xe300000000750000, 0x0, // LOAD ADDRESS EXTENDED (LAEY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LARL, 0xff0f000000000000, 0xc000000000000000, 0x0, // LOAD ADDRESS RELATIVE LONG (LARL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LASP, 0xffff000000000000, 0xe500000000000000, 0x0, // LOAD ADDRESS SPACE PARAMETERS (LASP D1(B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {LAA, 0xff00000000ff0000, 0xeb00000000f80000, 0x0, // LOAD AND ADD (32) (LAA R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LAAG, 0xff00000000ff0000, 0xeb00000000e80000, 0x0, // LOAD AND ADD (64) (LAAG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LAAL, 0xff00000000ff0000, 0xeb00000000fa0000, 0x0, // LOAD AND ADD LOGICAL (32) (LAAL R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LAALG, 0xff00000000ff0000, 0xeb00000000ea0000, 0x0, // LOAD AND ADD LOGICAL (64) (LAALG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LAN, 0xff00000000ff0000, 0xeb00000000f40000, 0x0, // LOAD AND AND (32) (LAN R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LANG, 0xff00000000ff0000, 0xeb00000000e40000, 0x0, // LOAD AND AND (64) (LANG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LAX, 0xff00000000ff0000, 0xeb00000000f70000, 0x0, // LOAD AND EXCLUSIVE OR (32) (LAX R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LAXG, 0xff00000000ff0000, 0xeb00000000e70000, 0x0, // LOAD AND EXCLUSIVE OR (64) (LAXG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LAO, 0xff00000000ff0000, 0xeb00000000f60000, 0x0, // LOAD AND OR (32) (LAO R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LAOG, 0xff00000000ff0000, 0xeb00000000e60000, 0x0, // LOAD AND OR (64) (LAOG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LT, 0xff00000000ff0000, 0xe300000000120000, 0x0, // LOAD AND TEST (32) (LT R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LTR, 0xff00000000000000, 0x1200000000000000, 0x0, // LOAD AND TEST (32) (LTR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {LTG, 0xff00000000ff0000, 0xe300000000020000, 0x0, // LOAD AND TEST (64) (LTG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LTGR, 0xffff000000000000, 0xb902000000000000, 0xff0000000000, // LOAD AND TEST (64) (LTGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LTGF, 0xff00000000ff0000, 0xe300000000320000, 0x0, // LOAD AND TEST (64→32) (LTGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LTGFR, 0xffff000000000000, 0xb912000000000000, 0xff0000000000, // LOAD AND TEST (64→32) (LTGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LTXBR, 0xffff000000000000, 0xb342000000000000, 0xff0000000000, // LOAD AND TEST (extended BFP) (LTXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LTXTR, 0xffff000000000000, 0xb3de000000000000, 0xff0000000000, // LOAD AND TEST (extended DFP) (LTXTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LTXR, 0xffff000000000000, 0xb362000000000000, 0xff0000000000, // LOAD AND TEST (extended HFP) (LTXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LTDBR, 0xffff000000000000, 0xb312000000000000, 0xff0000000000, // LOAD AND TEST (long BFP) (LTDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LTDTR, 0xffff000000000000, 0xb3d6000000000000, 0xff0000000000, // LOAD AND TEST (long DFP) (LTDTR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LTDR, 0xff00000000000000, 0x2200000000000000, 0x0, // LOAD AND TEST (long HFP) (LTDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LTEBR, 0xffff000000000000, 0xb302000000000000, 0xff0000000000, // LOAD AND TEST (short BFP) (LTEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LTER, 0xff00000000000000, 0x3200000000000000, 0x0, // LOAD AND TEST (short HFP) (LTER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LAT, 0xff00000000ff0000, 0xe3000000009f0000, 0x0, // LOAD AND TRAP (32L→32) (LAT R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LGAT, 0xff00000000ff0000, 0xe300000000850000, 0x0, // LOAD AND TRAP (64) (LGAT R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LZRF, 0xff00000000ff0000, 0xe3000000003b0000, 0x0, // LOAD AND ZERO RIGHTMOST BYTE (32) (LZRF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LZRG, 0xff00000000ff0000, 0xe3000000002a0000, 0x0, // LOAD AND ZERO RIGHTMOST BYTE (64) (LZRG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LBEAR, 0xffff000000000000, 0xb200000000000000, 0x0, // LOAD BEAR (LBEAR D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {LB, 0xff00000000ff0000, 0xe300000000760000, 0x0, // LOAD BYTE (32→8) (LB R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LBR, 0xffff000000000000, 0xb926000000000000, 0xff0000000000, // LOAD BYTE (32←8) (LBR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LGB, 0xff00000000ff0000, 0xe300000000770000, 0x0, // LOAD BYTE (64→8) (LGB R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LGBR, 0xffff000000000000, 0xb906000000000000, 0xff0000000000, // LOAD BYTE (64←8) (LGBR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LBH, 0xff00000000ff0000, 0xe300000000c00000, 0x0, // LOAD BYTE HIGH (32←8) (LBH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LCR, 0xff00000000000000, 0x1300000000000000, 0x0, // LOAD COMPLEMENT (32) (LCR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {LCGR, 0xffff000000000000, 0xb903000000000000, 0xff0000000000, // LOAD COMPLEMENT (64) (LCGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LCGFR, 0xffff000000000000, 0xb913000000000000, 0xff0000000000, // LOAD COMPLEMENT (64←32) (LCGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LCXBR, 0xffff000000000000, 0xb343000000000000, 0xff0000000000, // LOAD COMPLEMENT (extended BFP) (LCXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LCXR, 0xffff000000000000, 0xb363000000000000, 0xff0000000000, // LOAD COMPLEMENT (extended HFP) (LCXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LCDBR, 0xffff000000000000, 0xb313000000000000, 0xff0000000000, // LOAD COMPLEMENT (long BFP) (LCDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LCDR, 0xff00000000000000, 0x2300000000000000, 0x0, // LOAD COMPLEMENT (long HFP) (LCDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LCDFR, 0xffff000000000000, 0xb373000000000000, 0xff0000000000, // LOAD COMPLEMENT (long) (LCDFR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LCEBR, 0xffff000000000000, 0xb303000000000000, 0xff0000000000, // LOAD COMPLEMENT (short BFP) (LCEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LCER, 0xff00000000000000, 0x3300000000000000, 0x0, // LOAD COMPLEMENT (short HFP) (LCER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LCTL, 0xff00000000000000, 0xb700000000000000, 0x0, // LOAD CONTROL (32) (LCTL R1,R3,D2(B2)) + [8]*argField{ap_CReg_8_11, ap_CReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {LCTLG, 0xff00000000ff0000, 0xeb000000002f0000, 0x0, // LOAD CONTROL (64) (LCTLG R1,R3,D2(B2)) + [8]*argField{ap_CReg_8_11, ap_CReg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LCBB, 0xff00000000ff0000, 0xe700000000270000, 0xf000000, // LOAD COUNT TO BLOCK BOUNDARY (LCBB R1,D2(X2,B2),M3) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35}}, + {FIXBR, 0xffff000000000000, 0xb347000000000000, 0xf0000000000, // LOAD FP INTEGER (extended BFP) (FIXBR R1,M3,R2) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {FIXBRA, 0xffff000000000000, 0xb347000000000000, 0x0, // LOAD FP INTEGER (extended BFP) (FIXBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {FIXTR, 0xffff000000000000, 0xb3df000000000000, 0x0, // LOAD FP INTEGER (extended DFP) (FIXTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {FIXR, 0xffff000000000000, 0xb367000000000000, 0xff0000000000, // LOAD FP INTEGER (extended HFP) (FIXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {FIDBR, 0xffff000000000000, 0xb35f000000000000, 0xf0000000000, // LOAD FP INTEGER (long BFP) (FIDBR R1,M3,R2) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {FIDBRA, 0xffff000000000000, 0xb35f000000000000, 0x0, // LOAD FP INTEGER (long BFP) (FIDBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {FIDTR, 0xffff000000000000, 0xb3d7000000000000, 0x0, // LOAD FP INTEGER (long DFP) (FIDTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {FIDR, 0xffff000000000000, 0xb37f000000000000, 0xff0000000000, // LOAD FP INTEGER (long HFP) (FIDR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {FIEBR, 0xffff000000000000, 0xb357000000000000, 0xf0000000000, // LOAD FP INTEGER (short BFP) (FIEBR R1,M3,R2) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31}}, + {FIEBRA, 0xffff000000000000, 0xb357000000000000, 0x0, // LOAD FP INTEGER (short BFP) (FIEBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {FIER, 0xffff000000000000, 0xb377000000000000, 0xff0000000000, // LOAD FP INTEGER (short HFP) (FIER R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LFPC, 0xffff000000000000, 0xb29d000000000000, 0x0, // LOAD FPC (LFPC D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {LFAS, 0xffff000000000000, 0xb2bd000000000000, 0x0, // LOAD FPC AND SIGNAL (LFAS D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {LDGR, 0xffff000000000000, 0xb3c1000000000000, 0xff0000000000, // LOAD FPR FROM GR (64 to long) (LDGR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_Reg_28_31}}, + {LGDR, 0xffff000000000000, 0xb3cd000000000000, 0xff0000000000, // LOAD GR FROM FPR (long to 64) (LGDR R1,R2) + [8]*argField{ap_Reg_24_27, ap_FPReg_28_31}}, + {LGG, 0xff00000000ff0000, 0xe3000000004c0000, 0x0, // LOAD GUARDED (64) (LGG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LGSC, 0xff00000000ff0000, 0xe3000000004d0000, 0x0, // LOAD GUARDED STORAGE CONTROLS (LGSC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LH, 0xff00000000000000, 0x4800000000000000, 0x0, // LOAD HALFWORD (32→16) (LH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LHR, 0xffff000000000000, 0xb927000000000000, 0xff0000000000, // LOAD HALFWORD (32←16) (LHR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LHY, 0xff00000000ff0000, 0xe300000000780000, 0x0, // LOAD HALFWORD (32←16) (LHY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LGH, 0xff00000000ff0000, 0xe300000000150000, 0x0, // LOAD HALFWORD (64←16) (LGH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LGHR, 0xffff000000000000, 0xb907000000000000, 0xff0000000000, // LOAD HALFWORD (64←16) (LGHR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LHH, 0xff00000000ff0000, 0xe300000000c40000, 0x0, // LOAD HALFWORD HIGH (32→16) (LHH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LOCHHI, 0xff00000000ff0000, 0xec000000004e0000, 0xff000000, // LOAD HALFWORD HIGH IMMEDIATE ON (LOCHHI R1,I2,M3) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_12_15}}, + {LHI, 0xff0f000000000000, 0xa708000000000000, 0x0, // CONDITION (32←16)LOAD HALFWORD IMMEDIATE (32)←16 (LHI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {LGHI, 0xff0f000000000000, 0xa709000000000000, 0x0, // LOAD HALFWORD IMMEDIATE (64→16) (LGHI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {LOCHI, 0xff00000000ff0000, 0xec00000000420000, 0xff000000, // LOAD HALFWORD IMMEDIATE ON CONDITION(32←16) (LOCHI R1,I2,M3) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_12_15}}, + {LOCGHI, 0xff00000000ff0000, 0xec00000000460000, 0xff000000, // LOAD HALFWORD IMMEDIATE ON CONDITION(64→16) (LOCGHI R1,I2,M3) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31, ap_Mask_12_15}}, + {LHRL, 0xff0f000000000000, 0xc405000000000000, 0x0, // LOAD HALFWORD RELATIVE LONG (32←16) (LHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LGHRL, 0xff0f000000000000, 0xc404000000000000, 0x0, // LOAD HALFWORD RELATIVE LONG (64←16) (LGHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LFH, 0xff00000000ff0000, 0xe300000000ca0000, 0x0, // LOAD HIGH (32) (LFH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LFHAT, 0xff00000000ff0000, 0xe300000000c80000, 0x0, // LOAD HIGH AND TRAP (32H←32) (LFHAT R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LOCFH, 0xff00000000ff0000, 0xeb00000000e00000, 0x0, // LOAD HIGH ON CONDITION (32) (LOCFH R1,D2(B2),M3) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}}, + {LOCFHR, 0xffff000000000000, 0xb9e0000000000000, 0xf0000000000, // LOAD HIGH ON CONDITION (32) (LOCFHR R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {LGFI, 0xff0f000000000000, 0xc001000000000000, 0x0, // LOAD IMMEDIATE (64→32) (LGFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {LXDB, 0xff00000000ff0000, 0xed00000000050000, 0xff000000, // LOAD LENGTHENED (long to extended BFP) (LXDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LXDBR, 0xffff000000000000, 0xb305000000000000, 0xff0000000000, // LOAD LENGTHENED (long to extended BFP) (LXDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LXDTR, 0xffff000000000000, 0xb3dc000000000000, 0xf00000000000, // LOAD LENGTHENED (long to extended DFP) (LXDTR R1,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_Mask_20_23}}, + {LXD, 0xff00000000ff0000, 0xed00000000250000, 0xff000000, // LOAD LENGTHENED (long to extended HFP) (LXD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LXDR, 0xffff000000000000, 0xb325000000000000, 0xff0000000000, // LOAD LENGTHENED (long to extended HFP) (LXDR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LXEB, 0xff00000000ff0000, 0xed00000000060000, 0xff000000, // LOAD LENGTHENED (short to extended BFP) (LXEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LXEBR, 0xffff000000000000, 0xb306000000000000, 0xff0000000000, // LOAD LENGTHENED (short to extended BFP) (LXEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LXE, 0xff00000000ff0000, 0xed00000000260000, 0xff000000, // LOAD LENGTHENED (short to extended HFP) (LXE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LXER, 0xffff000000000000, 0xb326000000000000, 0xff0000000000, // LOAD LENGTHENED (short to extended HFP) (LXER R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LDEB, 0xff00000000ff0000, 0xed00000000040000, 0xff000000, // LOAD LENGTHENED (short to long BFP) (LDEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LDEBR, 0xffff000000000000, 0xb304000000000000, 0xff0000000000, // LOAD LENGTHENED (short to long BFP) (LDEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LDETR, 0xffff000000000000, 0xb3d4000000000000, 0xf00000000000, // LOAD LENGTHENED (short to long DFP) (LDETR R1,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_Mask_20_23}}, + {LDE, 0xff00000000ff0000, 0xed00000000240000, 0xff000000, // LOAD LENGTHENED (short to long HFP) (LDE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LDER, 0xffff000000000000, 0xb324000000000000, 0xff0000000000, // LOAD LENGTHENED (short to long HFP) (LDER R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LLGF, 0xff00000000ff0000, 0xe300000000160000, 0x0, // LOAD LOGICAL (64←32) (LLGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLGFR, 0xffff000000000000, 0xb916000000000000, 0xff0000000000, // LOAD LOGICAL (64←32) (LLGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LLGFSG, 0xff00000000ff0000, 0xe300000000480000, 0x0, // LOAD LOGICAL AND SHIFT GUARDED (64←32) (LLGFSG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLGFAT, 0xff00000000ff0000, 0xe3000000009d0000, 0x0, // LOAD LOGICAL AND TRAP (64→32) (LLGFAT R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLZRGF, 0xff00000000ff0000, 0xe3000000003a0000, 0x0, // LOAD LOGICAL AND ZERO RIGHTMOST BYTE(64→32) (LLZRGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLC, 0xff00000000ff0000, 0xe300000000940000, 0x0, // LOAD LOGICAL CHARACTER (32→8) (LLC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLCR, 0xffff000000000000, 0xb994000000000000, 0xff0000000000, // LOAD LOGICAL CHARACTER (32←8) (LLCR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LLGC, 0xff00000000ff0000, 0xe300000000900000, 0x0, // LOAD LOGICAL CHARACTER (64←8) (LLGC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLGCR, 0xffff000000000000, 0xb984000000000000, 0xff0000000000, // LOAD LOGICAL CHARACTER (64←8) (LLGCR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LLCH, 0xff00000000ff0000, 0xe300000000c20000, 0x0, // LOAD LOGICAL CHARACTER HIGH (32←8) (LLCH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLH, 0xff00000000ff0000, 0xe300000000950000, 0x0, // LOAD LOGICAL HALFWORD (32←16) (LLH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLHR, 0xffff000000000000, 0xb995000000000000, 0xff0000000000, // LOAD LOGICAL HALFWORD (32←16) (LLHR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LLGH, 0xff00000000ff0000, 0xe300000000910000, 0x0, // LOAD LOGICAL HALFWORD (64→16) (LLGH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLGHR, 0xffff000000000000, 0xb985000000000000, 0xff0000000000, // LOAD LOGICAL HALFWORD (64←16) (LLGHR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LLHH, 0xff00000000ff0000, 0xe300000000c60000, 0x0, // LOAD LOGICAL HALFWORD HIGH (32→16) (LLHH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLHRL, 0xff0f000000000000, 0xc402000000000000, 0x0, // LOAD LOGICAL HALFWORD RELATIVE LONG(32←16) (LLHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LLGHRL, 0xff0f000000000000, 0xc406000000000000, 0x0, // LOAD LOGICAL HALFWORD RELATIVE LONG(64→16) (LLGHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LLIHH, 0xff0f000000000000, 0xa50c000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high high) (LLIHH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {LLIHL, 0xff0f000000000000, 0xa50d000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high low) (LLIHL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {LLIHF, 0xff0f000000000000, 0xc00e000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (high) (LLIHF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {LLILH, 0xff0f000000000000, 0xa50e000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low high) (LLILH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {LLILL, 0xff0f000000000000, 0xa50f000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low low) (LLILL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {LLILF, 0xff0f000000000000, 0xc00f000000000000, 0x0, // LOAD LOGICAL IMMEDIATE (low) (LLILF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {LLGFRL, 0xff0f000000000000, 0xc40e000000000000, 0x0, // LOAD LOGICAL RELATIVE LONG (64→32) (LLGFRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LLGT, 0xff00000000ff0000, 0xe300000000170000, 0x0, // LOAD LOGICAL THIRTY ONE BITS (64→31) (LLGT R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LLGTR, 0xffff000000000000, 0xb917000000000000, 0xff0000000000, // LOAD LOGICAL THIRTY ONE BITS (64→31) (LLGTR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LLGTAT, 0xff00000000ff0000, 0xe3000000009c0000, 0x0, // LOAD LOGICAL THIRTY ONE BITS AND TRAP(64←31) (LLGTAT R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LM, 0xff00000000000000, 0x9800000000000000, 0x0, // LOAD MULTIPLE (32) (LM R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {LMY, 0xff00000000ff0000, 0xeb00000000980000, 0x0, // LOAD MULTIPLE (32) (LMY R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LMG, 0xff00000000ff0000, 0xeb00000000040000, 0x0, // LOAD MULTIPLE (64) (LMG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LMD, 0xff00000000000000, 0xef00000000000000, 0x0, // LOAD MULTIPLE DISJOINT (64→32&32) (LMD R1,R3,D2(B2),D4(B4)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {LMH, 0xff00000000ff0000, 0xeb00000000960000, 0x0, // LOAD MULTIPLE HIGH (32) (LMH R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LNR, 0xff00000000000000, 0x1100000000000000, 0x0, // LOAD NEGATIVE (32) (LNR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {LNGR, 0xffff000000000000, 0xb901000000000000, 0xff0000000000, // LOAD NEGATIVE (64) (LNGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LNGFR, 0xffff000000000000, 0xb911000000000000, 0xff0000000000, // LOAD NEGATIVE (64→32) (LNGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LNXBR, 0xffff000000000000, 0xb341000000000000, 0xff0000000000, // LOAD NEGATIVE (extended BFP) (LNXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LNXR, 0xffff000000000000, 0xb361000000000000, 0xff0000000000, // LOAD NEGATIVE (extended HFP) (LNXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LNDBR, 0xffff000000000000, 0xb311000000000000, 0xff0000000000, // LOAD NEGATIVE (long BFP) (LNDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LNDR, 0xff00000000000000, 0x2100000000000000, 0x0, // LOAD NEGATIVE (long HFP) (LNDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LNDFR, 0xffff000000000000, 0xb371000000000000, 0xff0000000000, // LOAD NEGATIVE (long) (LNDFR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LNEBR, 0xffff000000000000, 0xb301000000000000, 0xff0000000000, // LOAD NEGATIVE (short BFP) (LNEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LNER, 0xff00000000000000, 0x3100000000000000, 0x0, // LOAD NEGATIVE (short HFP) (LNER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LOC, 0xff00000000ff0000, 0xeb00000000f20000, 0x0, // LOAD ON CONDITION (32) (LOC R1,D2(B2),M3) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}}, + {LOCR, 0xffff000000000000, 0xb9f2000000000000, 0xf0000000000, // LOAD ON CONDITION (32) (LOCR R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {LOCG, 0xff00000000ff0000, 0xeb00000000e20000, 0x0, // LOAD ON CONDITION (64) (LOCG R1,D2(B2),M3) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}}, + {LOCGR, 0xffff000000000000, 0xb9e2000000000000, 0xf0000000000, // LOAD ON CONDITION (64) (LOCGR R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {LPTEA, 0xffff000000000000, 0xb9aa000000000000, 0x0, // LOAD PAGE TABLE ENTRY ADDRESS (LPTEA R1,R3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {LPD, 0xff0f000000000000, 0xc804000000000000, 0x0, // LOAD PAIR DISJOINT (32) (LPD R3,D1(B1),D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {LPDG, 0xff0f000000000000, 0xc805000000000000, 0x0, // LOAD PAIR DISJOINT (64) (LPDG R3,D1(B1),D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {LPQ, 0xff00000000ff0000, 0xe3000000008f0000, 0x0, // LOAD PAIR FROM QUADWORD (64&64←128) (LPQ R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LPR, 0xff00000000000000, 0x1000000000000000, 0x0, // LOAD POSITIVE (32) (LPR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {LPGR, 0xffff000000000000, 0xb900000000000000, 0xff0000000000, // LOAD POSITIVE (64) (LPGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LPGFR, 0xffff000000000000, 0xb910000000000000, 0xff0000000000, // LOAD POSITIVE (64→32) (LPGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LPXBR, 0xffff000000000000, 0xb340000000000000, 0xff0000000000, // LOAD POSITIVE (extended BFP) (LPXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LPXR, 0xffff000000000000, 0xb360000000000000, 0xff0000000000, // LOAD POSITIVE (extended HFP) (LPXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LPDBR, 0xffff000000000000, 0xb310000000000000, 0xff0000000000, // LOAD POSITIVE (long BFP) (LPDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LPDR, 0xff00000000000000, 0x2000000000000000, 0x0, // LOAD POSITIVE (long HFP) (LPDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LPDFR, 0xffff000000000000, 0xb370000000000000, 0xff0000000000, // LOAD POSITIVE (long) (LPDFR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LPEBR, 0xffff000000000000, 0xb300000000000000, 0xff0000000000, // LOAD POSITIVE (short BFP) (LPEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LPER, 0xff00000000000000, 0x3000000000000000, 0x0, // LOAD POSITIVE (short HFP) (LPER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LPSW, 0xff00000000000000, 0x8200000000000000, 0x0, // LOAD PSW (LPSW D1(B1)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {LPSWE, 0xffff000000000000, 0xb2b2000000000000, 0x0, // LOAD PSW EXTENDED (LPSWE D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {LPSWEY, 0xff00000000ff0000, 0xeb00000000710000, 0xff000000000000, // LOAD PSW EXTENDED (LPSWEY D1(B1)) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {LRA, 0xff00000000000000, 0xb100000000000000, 0x0, // LOAD REAL ADDRESS (32) (LRA R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LRAY, 0xff00000000ff0000, 0xe300000000130000, 0x0, // LOAD REAL ADDRESS (32) (LRAY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LRAG, 0xff00000000ff0000, 0xe300000000030000, 0x0, // LOAD REAL ADDRESS (64) (LRAG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LRL, 0xff0f000000000000, 0xc40d000000000000, 0x0, // LOAD RELATIVE LONG (32) (LRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LGRL, 0xff0f000000000000, 0xc408000000000000, 0x0, // LOAD RELATIVE LONG (64) (LGRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LGFRL, 0xff0f000000000000, 0xc40c000000000000, 0x0, // LOAD RELATIVE LONG (64→32) (LGFRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {LRVH, 0xff00000000ff0000, 0xe3000000001f0000, 0x0, // LOAD REVERSED (16) (LRVH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LRV, 0xff00000000ff0000, 0xe3000000001e0000, 0x0, // LOAD REVERSED (32) (LRV R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LRVR, 0xffff000000000000, 0xb91f000000000000, 0xff0000000000, // LOAD REVERSED (32) (LRVR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LRVG, 0xff00000000ff0000, 0xe3000000000f0000, 0x0, // LOAD REVERSED (64) (LRVG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {LRVGR, 0xffff000000000000, 0xb90f000000000000, 0xff0000000000, // LOAD REVERSED (64) (LRVGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LDXBR, 0xffff000000000000, 0xb345000000000000, 0xff0000000000, // LOAD ROUNDED (extended to long BFP) (LDXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LDXBRA, 0xffff000000000000, 0xb345000000000000, 0x0, // LOAD ROUNDED (extended to long BFP) (LDXBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {LDXTR, 0xffff000000000000, 0xb3dd000000000000, 0x0, // LOAD ROUNDED (extended to long DFP) (LDXTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {LDXR, 0xff00000000000000, 0x2500000000000000, 0x0, // LOAD ROUNDED (extended to long HFP) (LDXR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LRDR, 0xff00000000000000, 0x2500000000000000, 0x0, // LOAD ROUNDED (extended to long HFP) (LRDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LEXBR, 0xffff000000000000, 0xb346000000000000, 0xff0000000000, // LOAD ROUNDED (extended to short BFP) (LEXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LEXBRA, 0xffff000000000000, 0xb346000000000000, 0x0, // LOAD ROUNDED (extended to short BFP) (LEXBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {LEXR, 0xffff000000000000, 0xb366000000000000, 0xff0000000000, // LOAD ROUNDED (extended to short HFP) (LEXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LEDBR, 0xffff000000000000, 0xb344000000000000, 0xff0000000000, // LOAD ROUNDED (long to short BFP) (LEDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {LEDBRA, 0xffff000000000000, 0xb344000000000000, 0x0, // LOAD ROUNDED (long to short BFP) (LEDBRA R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {LEDTR, 0xffff000000000000, 0xb3d5000000000000, 0x0, // LOAD ROUNDED (long to short DFP) (LEDTR R1,M3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_Mask_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {LEDR, 0xff00000000000000, 0x3500000000000000, 0x0, // LOAD ROUNDED (long to short HFP) (LEDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LRER, 0xff00000000000000, 0x3500000000000000, 0x0, // LOAD ROUNDED (long to short HFP) (LRER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {LURA, 0xffff000000000000, 0xb24b000000000000, 0xff0000000000, // LOAD USING REAL ADDRESS (32) (LURA R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LURAG, 0xffff000000000000, 0xb905000000000000, 0xff0000000000, // LOAD USING REAL ADDRESS (64) (LURAG R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {LZXR, 0xffff000000000000, 0xb376000000000000, 0xff0f00000000, // LOAD ZERO (extended) (LZXR R1) + [8]*argField{ap_FPReg_24_27}}, + {LZDR, 0xffff000000000000, 0xb375000000000000, 0xff0f00000000, // LOAD ZERO (long) (LZDR R1) + [8]*argField{ap_FPReg_24_27}}, + {LZER, 0xffff000000000000, 0xb374000000000000, 0xff0f00000000, // LOAD ZERO (short) (LZER R1) + [8]*argField{ap_FPReg_24_27}}, + {MSTA, 0xffff000000000000, 0xb247000000000000, 0xff0f00000000, // MODIFY STACKED STATE (MSTA R1) + [8]*argField{ap_Reg_24_27}}, + {MSCH, 0xffff000000000000, 0xb232000000000000, 0x0, // MODIFY SUBCHANNEL (MSCH D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {MC, 0xff00000000000000, 0xaf00000000000000, 0x0, // MONITOR CALL (MC D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {MVHHI, 0xffff000000000000, 0xe544000000000000, 0x0, // MOVE (16←16) (MVHHI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}}, + {MVHI, 0xffff000000000000, 0xe54c000000000000, 0x0, // MOVE (32→16) (MVHI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}}, + {MVGHI, 0xffff000000000000, 0xe548000000000000, 0x0, // MOVE (64←16) (MVGHI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned16_32_47}}, + {MVC, 0xff00000000000000, 0xd200000000000000, 0x0, // MOVE (character) (MVC D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {MVI, 0xff00000000000000, 0x9200000000000000, 0x0, // MOVE (immediate) (MVI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {MVIY, 0xff00000000ff0000, 0xeb00000000520000, 0x0, // MOVE (immediate) (MVIY D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {MVCIN, 0xff00000000000000, 0xe800000000000000, 0x0, // MOVE INVERSE (MVCIN D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {MVCL, 0xff00000000000000, 0xe00000000000000, 0x0, // MOVE LONG (MVCL R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {MVCLE, 0xff00000000000000, 0xa800000000000000, 0x0, // MOVE LONG EXTENDED (MVCLE R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {MVCLU, 0xff00000000ff0000, 0xeb000000008e0000, 0x0, // MOVE LONG UNICODE (MVCLU R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {MVN, 0xff00000000000000, 0xd100000000000000, 0x0, // MOVE NUMERICS (MVN D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {MVPG, 0xffff000000000000, 0xb254000000000000, 0xff0000000000, // MOVE PAGE (MVPG R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {MVCRL, 0xffff000000000000, 0xe50a000000000000, 0x0, // MOVE RIGHT TO LEFT (MVCRL D1(B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {MVST, 0xffff000000000000, 0xb255000000000000, 0xff0000000000, // MOVE STRING (MVST R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {MVCP, 0xff00000000000000, 0xda00000000000000, 0x0, // MOVE TO PRIMARY (MVCP D1(R1,B1),D2(B2),R3) + [8]*argField{ap_DispUnsigned_20_31, ap_Reg_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_12_15}}, + {MVCS, 0xff00000000000000, 0xdb00000000000000, 0x0, // MOVE TO SECONDARY (MVCS D1(R1,B1),D2(B2),R3) + [8]*argField{ap_DispUnsigned_20_31, ap_Reg_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_12_15}}, + {MVCDK, 0xffff000000000000, 0xe50f000000000000, 0x0, // MOVE WITH DESTINATION KEY (MVCDK D1(B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {MVCK, 0xff00000000000000, 0xd900000000000000, 0x0, // MOVE WITH KEY (MVCK D1(R1,B1),D2(B2),R3) + [8]*argField{ap_DispUnsigned_20_31, ap_Reg_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_12_15}}, + {MVO, 0xff00000000000000, 0xf100000000000000, 0x0, // MOVE WITH OFFSET (MVO D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, + {MVCOS, 0xff0f000000000000, 0xc800000000000000, 0x0, // MOVE WITH OPTIONAL SPECIFICATIONS (MVCOS D1(B1),D2(B2),R3) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_Reg_8_11}}, + {MVCSK, 0xffff000000000000, 0xe50e000000000000, 0x0, // MOVE WITH SOURCE KEY (MVCSK D1(B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {MVZ, 0xff00000000000000, 0xd300000000000000, 0x0, // MOVE ZONES (MVZ D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {MG, 0xff00000000ff0000, 0xe300000000840000, 0x0, // MULTIPLY (128←64) (MG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MGRK, 0xffff000000000000, 0xb9ec000000000000, 0xf0000000000, // MULTIPLY (128←64) (MGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {M, 0xff00000000000000, 0x5c00000000000000, 0x0, // MULTIPLY (64←32) (M R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MFY, 0xff00000000ff0000, 0xe3000000005c0000, 0x0, // MULTIPLY (64←32) (MFY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MR, 0xff00000000000000, 0x1c00000000000000, 0x0, // MULTIPLY (64←32) (MR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {MXBR, 0xffff000000000000, 0xb34c000000000000, 0xff0000000000, // MULTIPLY (extended BFP) (MXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {MXTR, 0xffff000000000000, 0xb3d8000000000000, 0xf0000000000, // MULTIPLY (extended DFP) (MXTR R1,R2,R3) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}}, + {MXTRA, 0xffff000000000000, 0xb3d8000000000000, 0x0, // MULTIPLY (extended DFP) (MXTRA R1,R2,R3,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}}, + {MXR, 0xff00000000000000, 0x2600000000000000, 0x0, // MULTIPLY (extended HFP) (MXR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {MDB, 0xff00000000ff0000, 0xed000000001c0000, 0xff000000, // MULTIPLY (long BFP) (MDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MDBR, 0xffff000000000000, 0xb31c000000000000, 0xff0000000000, // MULTIPLY (long BFP) (MDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {MDTR, 0xffff000000000000, 0xb3d0000000000000, 0xf0000000000, // MULTIPLY (long DFP) (MDTR R1,R2,R3) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}}, + {MDTRA, 0xffff000000000000, 0xb3d0000000000000, 0x0, // MULTIPLY (long DFP) (MDTRA R1,R2,R3,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}}, + {MD, 0xff00000000000000, 0x6c00000000000000, 0x0, // MULTIPLY (long HFP) (MD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MDR, 0xff00000000000000, 0x2c00000000000000, 0x0, // MULTIPLY (long HFP) (MDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {MXDB, 0xff00000000ff0000, 0xed00000000070000, 0xff000000, // MULTIPLY (long to extended BFP) (MXDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MXDBR, 0xffff000000000000, 0xb307000000000000, 0xff0000000000, // MULTIPLY (long to extended BFP) (MXDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {MXD, 0xff00000000000000, 0x6700000000000000, 0x0, // MULTIPLY (long to extended HFP) (MXD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MXDR, 0xff00000000000000, 0x2700000000000000, 0x0, // MULTIPLY (long to extended HFP) (MXDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {MEEB, 0xff00000000ff0000, 0xed00000000170000, 0xff000000, // MULTIPLY (short BFP) (MEEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MEEBR, 0xffff000000000000, 0xb317000000000000, 0xff0000000000, // MULTIPLY (short BFP) (MEEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {MEE, 0xff00000000ff0000, 0xed00000000370000, 0xff000000, // MULTIPLY (short HFP) (MEE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MEER, 0xffff000000000000, 0xb337000000000000, 0xff0000000000, // MULTIPLY (short HFP) (MEER R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {MDEB, 0xff00000000ff0000, 0xed000000000c0000, 0xff000000, // MULTIPLY (short to long BFP) (MDEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MDEBR, 0xffff000000000000, 0xb30c000000000000, 0xff0000000000, // MULTIPLY (short to long BFP) (MDEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {MDE, 0xff00000000000000, 0x7c00000000000000, 0x0, // MULTIPLY (short to long HFP) (MDE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MDER, 0xff00000000000000, 0x3c00000000000000, 0x0, // MULTIPLY (short to long HFP) (MDER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {ME, 0xff00000000000000, 0x7c00000000000000, 0x0, // MULTIPLY (short to long HFP) (ME R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MER, 0xff00000000000000, 0x3c00000000000000, 0x0, // MULTIPLY (short to long HFP) (MER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {MAY, 0xff00000000ff0000, 0xed000000003a0000, 0xf000000, // MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) (MAY R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MAYR, 0xffff000000000000, 0xb33a000000000000, 0xf0000000000, // MULTIPLY & ADD UNNORMALIZED (long to ext. HFP) (MAYR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MADB, 0xff00000000ff0000, 0xed000000001e0000, 0xf000000, // MULTIPLY AND ADD (long BFP) (MADB R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MADBR, 0xffff000000000000, 0xb31e000000000000, 0xf0000000000, // MULTIPLY AND ADD (long BFP) (MADBR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MAD, 0xff00000000ff0000, 0xed000000003e0000, 0xf000000, // MULTIPLY AND ADD (long HFP) (MAD R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MADR, 0xffff000000000000, 0xb33e000000000000, 0xf0000000000, // MULTIPLY AND ADD (long HFP) (MADR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MAEB, 0xff00000000ff0000, 0xed000000000e0000, 0xf000000, // MULTIPLY AND ADD (short BFP) (MAEB R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MAEBR, 0xffff000000000000, 0xb30e000000000000, 0xf0000000000, // MULTIPLY AND ADD (short BFP) (MAEBR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MAE, 0xff00000000ff0000, 0xed000000002e0000, 0xf000000, // MULTIPLY AND ADD (short HFP) (MAE R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MAER, 0xffff000000000000, 0xb32e000000000000, 0xf0000000000, // MULTIPLY AND ADD (short HFP) (MAER R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MAYH, 0xff00000000ff0000, 0xed000000003c0000, 0xf000000, // MULTIPLY AND ADD UNNRM. (long to ext. high HFP) (MAYH R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MAYHR, 0xffff000000000000, 0xb33c000000000000, 0xf0000000000, // MULTIPLY AND ADD UNNRM. (long to ext. high HFP) (MAYHR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MAYL, 0xff00000000ff0000, 0xed00000000380000, 0xf000000, // MULTIPLY AND ADD UNNRM. (long to ext. low HFP) (MAYL R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MAYLR, 0xffff000000000000, 0xb338000000000000, 0xf0000000000, // MULTIPLY AND ADD UNNRM. (long to ext. low HFP) (MAYLR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MSDB, 0xff00000000ff0000, 0xed000000001f0000, 0xf000000, // MULTIPLY AND SUBTRACT (long BFP) (MSDB R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSDBR, 0xffff000000000000, 0xb31f000000000000, 0xf0000000000, // MULTIPLY AND SUBTRACT (long BFP) (MSDBR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MSD, 0xff00000000ff0000, 0xed000000003f0000, 0xf000000, // MULTIPLY AND SUBTRACT (long HFP) (MSD R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSDR, 0xffff000000000000, 0xb33f000000000000, 0xf0000000000, // MULTIPLY AND SUBTRACT (long HFP) (MSDR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MSEB, 0xff00000000ff0000, 0xed000000000f0000, 0xf000000, // MULTIPLY AND SUBTRACT (short BFP) (MSEB R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSEBR, 0xffff000000000000, 0xb30f000000000000, 0xf0000000000, // MULTIPLY AND SUBTRACT (short BFP) (MSEBR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MSE, 0xff00000000ff0000, 0xed000000002f0000, 0xf000000, // MULTIPLY AND SUBTRACT (short HFP) (MSE R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSER, 0xffff000000000000, 0xb32f000000000000, 0xf0000000000, // MULTIPLY AND SUBTRACT (short HFP) (MSER R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MP, 0xff00000000000000, 0xfc00000000000000, 0x0, // MULTIPLY DECIMAL (MP D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, + {MH, 0xff00000000000000, 0x4c00000000000000, 0x0, // MULTIPLY HALFWORD (32←16) (MH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MHY, 0xff00000000ff0000, 0xe3000000007c0000, 0x0, // MULTIPLY HALFWORD (32←16) (MHY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MGH, 0xff00000000ff0000, 0xe3000000003c0000, 0x0, // MULTIPLY HALFWORD (64→16) (MGH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MHI, 0xff0f000000000000, 0xa70c000000000000, 0x0, // MULTIPLY HALFWORD IMMEDIATE (32→16) (MHI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_31}}, + {MGHI, 0xff0f000000000000, 0xa70d000000000000, 0x0, // MULTIPLY HALFWORD IMMEDIATE (64→16) (MGHI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_31}}, + {MLG, 0xff00000000ff0000, 0xe300000000860000, 0x0, // MULTIPLY LOGICAL (128→64) (MLG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MLGR, 0xffff000000000000, 0xb986000000000000, 0xff0000000000, // MULTIPLY LOGICAL (128→64) (MLGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {ML, 0xff00000000ff0000, 0xe300000000960000, 0x0, // MULTIPLY LOGICAL (64←32) (ML R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MLR, 0xffff000000000000, 0xb996000000000000, 0xff0000000000, // MULTIPLY LOGICAL (64←32) (MLR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {MS, 0xff00000000000000, 0x7100000000000000, 0x0, // MULTIPLY SINGLE (32) (MS R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSC, 0xff00000000ff0000, 0xe300000000530000, 0x0, // MULTIPLY SINGLE (32) (MSC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSR, 0xffff000000000000, 0xb252000000000000, 0xff0000000000, // MULTIPLY SINGLE (32) (MSR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {MSRKC, 0xffff000000000000, 0xb9fd000000000000, 0xf0000000000, // MULTIPLY SINGLE (32) (MSRKC R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {MSY, 0xff00000000ff0000, 0xe300000000510000, 0x0, // MULTIPLY SINGLE (32) (MSY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSG, 0xff00000000ff0000, 0xe3000000000c0000, 0x0, // MULTIPLY SINGLE (64) (MSG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSGC, 0xff00000000ff0000, 0xe300000000830000, 0x0, // MULTIPLY SINGLE (64) (MSGC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSGR, 0xffff000000000000, 0xb90c000000000000, 0xff0000000000, // MULTIPLY SINGLE (64) (MSGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {MSGRKC, 0xffff000000000000, 0xb9ed000000000000, 0xf0000000000, // MULTIPLY SINGLE (64) (MSGRKC R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {MSGF, 0xff00000000ff0000, 0xe3000000001c0000, 0x0, // MULTIPLY SINGLE (64←32) (MSGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MSGFR, 0xffff000000000000, 0xb91c000000000000, 0xff0000000000, // MULTIPLY SINGLE (64←32) (MSGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {MSFI, 0xff0f000000000000, 0xc201000000000000, 0x0, // MULTIPLY SINGLE IMMEDIATE (32) (MSFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {MSGFI, 0xff0f000000000000, 0xc200000000000000, 0x0, // MULTIPLY SINGLE IMMEDIATE (64←32) (MSGFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {MYH, 0xff00000000ff0000, 0xed000000003d0000, 0xf000000, // MULTIPLY UNNORM. (long to ext. high HFP) (MYH R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MYHR, 0xffff000000000000, 0xb33d000000000000, 0xf0000000000, // MULTIPLY UNNORM. (long to ext. high HFP) (MYHR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MYL, 0xff00000000ff0000, 0xed00000000390000, 0xf000000, // MULTIPLY UNNORM. (long to ext. low HFP) (MYL R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MYLR, 0xffff000000000000, 0xb339000000000000, 0xf0000000000, // MULTIPLY UNNORM. (long to ext. low HFP) (MYLR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {MY, 0xff00000000ff0000, 0xed000000003b0000, 0xf000000, // MULTIPLY UNNORMALIZED (long to ext. HFP) (MY R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {MYR, 0xffff000000000000, 0xb33b000000000000, 0xf0000000000, // MULTIPLY UNNORMALIZED (long to ext. HFP) (MYR R1,R3,R2) + [8]*argField{ap_FPReg_16_19, ap_FPReg_24_27, ap_FPReg_28_31}}, + {NNRK, 0xffff000000000000, 0xb974000000000000, 0xf0000000000, // NAND (32) (NNRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {NNGRK, 0xffff000000000000, 0xb964000000000000, 0xf0000000000, // NAND (64) (NNGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {NNPA, 0xffff000000000000, 0xb93b000000000000, 0xffff00000000, // NEURAL NETWORK PROCESSING ASSIST (NNPA) + [8]*argField{}}, + {NIAI, 0xffff000000000000, 0xb2fa000000000000, 0xff0000000000, // NEXT INSTRUCTION ACCESS INTENT (NIAI I1,I2) + [8]*argField{ap_ImmUnsigned_24_27, ap_ImmUnsigned_28_31}}, + {NTSTG, 0xff00000000ff0000, 0xe300000000250000, 0x0, // NONTRANSACTIONAL STORE (64) (NTSTG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {NORK, 0xffff000000000000, 0xb976000000000000, 0xf0000000000, // NOR (32) (NORK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {NOGRK, 0xffff000000000000, 0xb966000000000000, 0xf0000000000, // NOR (64) (NOGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {NXRK, 0xffff000000000000, 0xb977000000000000, 0xf0000000000, // NOT EXCLUSIVE OR (32) (NXRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {NXGRK, 0xffff000000000000, 0xb967000000000000, 0xf0000000000, // NOT EXCLUSIVE OR (64) (NXGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {O, 0xff00000000000000, 0x5600000000000000, 0x0, // OR (32) (O R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {OR, 0xff00000000000000, 0x1600000000000000, 0x0, // OR (32) (OR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {ORK, 0xffff000000000000, 0xb9f6000000000000, 0xf0000000000, // OR (32) (ORK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {OY, 0xff00000000ff0000, 0xe300000000560000, 0x0, // OR (32) (OY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {OG, 0xff00000000ff0000, 0xe300000000810000, 0x0, // OR (64) (OG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {OGR, 0xffff000000000000, 0xb981000000000000, 0xff0000000000, // OR (64) (OGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {OGRK, 0xffff000000000000, 0xb9e6000000000000, 0xf0000000000, // OR (64) (OGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {OC, 0xff00000000000000, 0xd600000000000000, 0x0, // OR (character) (OC D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {OI, 0xff00000000000000, 0x9600000000000000, 0x0, // OR (immediate) (OI D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {OIY, 0xff00000000ff0000, 0xeb00000000560000, 0x0, // OR (immediate) (OIY D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmSigned8_8_15}}, + {OIHH, 0xff0f000000000000, 0xa508000000000000, 0x0, // OR IMMEDIATE (high high) (OIHH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {OIHL, 0xff0f000000000000, 0xa509000000000000, 0x0, // OR IMMEDIATE (high low) (OIHL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {OIHF, 0xff0f000000000000, 0xc00c000000000000, 0x0, // OR IMMEDIATE (high) (OIHF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {OILH, 0xff0f000000000000, 0xa50a000000000000, 0x0, // OR IMMEDIATE (low high) (OILH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {OILL, 0xff0f000000000000, 0xa50b000000000000, 0x0, // OR IMMEDIATE (low low) (OILL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned16_16_31}}, + {OILF, 0xff0f000000000000, 0xc00d000000000000, 0x0, // OR IMMEDIATE (low) (OILF R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmSigned32_16_47}}, + {OCRK, 0xffff000000000000, 0xb975000000000000, 0xf0000000000, // OR WITH COMPLEMENT (32) (OCRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {OCGRK, 0xffff000000000000, 0xb965000000000000, 0xf0000000000, // OR WITH COMPLEMENT (64) (OCGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {PACK, 0xff00000000000000, 0xf200000000000000, 0x0, // PACK (PACK D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, + {PKA, 0xff00000000000000, 0xe900000000000000, 0x0, // PACK ASCII (PKA D1(B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_8_15, ap_BaseReg_32_35}}, + {PKU, 0xff00000000000000, 0xe100000000000000, 0x0, // PACK UNICODE (PKU D1(B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_8_15, ap_BaseReg_32_35}}, + {PGIN, 0xffff000000000000, 0xb22e000000000000, 0xff0000000000, // PAGE IN (PGIN R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {PGOUT, 0xffff000000000000, 0xb22f000000000000, 0xff0000000000, // PAGE OUT (PGOUT R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {PCC, 0xffff000000000000, 0xb92c000000000000, 0xffff00000000, // PERFORM CRYPTOGRAPHIC COMPUTATION (PCC) + [8]*argField{}}, + {PCKMO, 0xffff000000000000, 0xb928000000000000, 0xffff00000000, // PERFORM CRYPTOGRAPHIC KEY MGMT. OPERATIONS (PCKMO) + [8]*argField{}}, + {PFPO, 0xffff000000000000, 0x10a000000000000, 0x0, // PERFORM FLOATING-POINT OPERATION (PFPO) + [8]*argField{}}, + {PFMF, 0xffff000000000000, 0xb9af000000000000, 0xff0000000000, // PERFORM FRAME MANAGEMENT FUNCTION (PFMF R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {PLO, 0xff00000000000000, 0xee00000000000000, 0x0, // PERFORM LOCKED OPERATION (PLO R1,D2(B2),R3,D4(B4)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Reg_12_15, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {PPA, 0xffff000000000000, 0xb2e8000000000000, 0xf0000000000, // PERFORM PROCESSOR ASSIST (PPA R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {PRNO, 0xffff000000000000, 0xb93c000000000000, 0xff0000000000, // PERFORM RANDOM NUMBER OPERATION (PRNO R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {PTFF, 0xffff000000000000, 0x104000000000000, 0x0, // PERFORM TIMING FACILITY FUNCTION (PTFF) + [8]*argField{}}, + {PTF, 0xffff000000000000, 0xb9a2000000000000, 0xff0f00000000, // PERFORM TOPOLOGY FUNCTION (PTF R1) + [8]*argField{ap_Reg_24_27}}, + {POPCNT, 0xffff000000000000, 0xb9e1000000000000, 0xf0000000000, // POPULATION COUNT (POPCNT R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {PFD, 0xff00000000ff0000, 0xe300000000360000, 0x0, // PREFETCH DATA (PFD M1,D2(X2,B2)) + [8]*argField{ap_Mask_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {PFDRL, 0xff0f000000000000, 0xc602000000000000, 0x0, // PREFETCH DATA RELATIVE LONG (PFDRL M1,RI2) + [8]*argField{ap_Mask_8_11, ap_RegImSigned32_16_47}}, + {PC, 0xffff000000000000, 0xb218000000000000, 0x0, // PROGRAM CALL (PC D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {PR, 0xffff000000000000, 0x101000000000000, 0x0, // PROGRAM RETURN (PR) + [8]*argField{}}, + {PT, 0xffff000000000000, 0xb228000000000000, 0xff0000000000, // PROGRAM TRANSFER (PT R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {PTI, 0xffff000000000000, 0xb99e000000000000, 0xff0000000000, // PROGRAM TRANSFER WITH INSTANCE (PTI R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {PALB, 0xffff000000000000, 0xb248000000000000, 0xffff00000000, // PURGE ALB (PALB) + [8]*argField{}}, + {PTLB, 0xffff000000000000, 0xb20d000000000000, 0xffff00000000, // PURGE TLB (PTLB) + [8]*argField{}}, + {QAXTR, 0xffff000000000000, 0xb3fd000000000000, 0x0, // QUANTIZE (extended DFP) (QAXTR R1,R3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {QADTR, 0xffff000000000000, 0xb3f5000000000000, 0x0, // QUANTIZE (long DFP) (QADTR R1,R3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_FPReg_28_31, ap_Mask_20_23}}, + {QPACI, 0xffff000000000000, 0xb28f000000000000, 0x0, // QUERY PROCESSOR ACTIVITY COUNTER INFORMATION (QPACI D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {RRXTR, 0xffff000000000000, 0xb3ff000000000000, 0x0, // REROUND (extended DFP) (RRXTR R1,R3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {RRDTR, 0xffff000000000000, 0xb3f7000000000000, 0x0, // REROUND (long DFP) (RRDTR R1,R3,R2,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {RCHP, 0xffff000000000000, 0xb23b000000000000, 0xffff00000000, // RESET CHANNEL PATH (RCHP) + [8]*argField{}}, + {RDP, 0xffff000000000000, 0xb98b000000000000, 0x0, // RESET DAT PROTECTION (RDP R1,R3,R2,M4) + [8]*argField{ap_Reg_24_27, ap_Reg_16_19, ap_Reg_28_31, ap_Mask_20_23}}, + {RRBE, 0xffff000000000000, 0xb22a000000000000, 0xff0000000000, // RESET REFERENCE BIT EXTENDED (RRBE R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {RRBM, 0xffff000000000000, 0xb9ae000000000000, 0xff0000000000, // RESET REFERENCE BITS MULTIPLE (RRBM R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {RP, 0xffff000000000000, 0xb277000000000000, 0x0, // RESUME PROGRAM (RP D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {RSCH, 0xffff000000000000, 0xb238000000000000, 0xffff00000000, // RESUME SUBCHANNEL (RSCH) + [8]*argField{}}, + {RLL, 0xff00000000ff0000, 0xeb000000001d0000, 0x0, // ROTATE LEFT SINGLE LOGICAL (32) (RLL R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {RLLG, 0xff00000000ff0000, 0xeb000000001c0000, 0x0, // ROTATE LEFT SINGLE LOGICAL (64) (RLLG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {RNSBG, 0xff00000000ff0000, 0xec00000000540000, 0x0, // ROTATE THEN AND SELECTED BITS (64) (RNSBG R1,R2,I3,I4,I5) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}}, + {RXSBG, 0xff00000000ff0000, 0xec00000000570000, 0x0, // ROTATETHENEXCLUSIVEORSELECT.BITS(64) (RXSBG R1,R2,I3,I4,I5) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}}, + {RISBG, 0xff00000000ff0000, 0xec00000000550000, 0x0, // ROTATE THEN INSERT SELECTED BITS (64) (RISBG R1,R2,I3,I4,I5) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}}, + {RISBGN, 0xff00000000ff0000, 0xec00000000590000, 0x0, // ROTATE THEN INSERT SELECTED BITS (64) (RISBGN R1,R2,I3,I4,I5) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}}, + {RISBHG, 0xff00000000ff0000, 0xec000000005d0000, 0x0, // ROTATE THEN INSERT SELECTED BITS HIGH(64) (RISBHG R1,R2,I3,I4,I5) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}}, + {RISBLG, 0xff00000000ff0000, 0xec00000000510000, 0x0, // ROTATE THEN INSERT SELECTED BITS LOW (64) (RISBLG R1,R2,I3,I4,I5) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}}, + {ROSBG, 0xff00000000ff0000, 0xec00000000560000, 0x0, // ROTATE THEN OR SELECTED BITS (64) (ROSBG R1,R2,I3,I4,I5) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_ImmUnsigned_32_39}}, + {SRST, 0xffff000000000000, 0xb25e000000000000, 0xff0000000000, // SEARCH STRING (SRST R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SRSTU, 0xffff000000000000, 0xb9be000000000000, 0xff0000000000, // SEARCH STRING UNICODE (SRSTU R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SELR, 0xffff000000000000, 0xb9f0000000000000, 0x0, // SELECT (32) (SELR R1,R2,R3,M4) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19, ap_Mask_20_23}}, + {SELGR, 0xffff000000000000, 0xb9e3000000000000, 0x0, // SELECT (64) (SELGR R1,R2,R3,M4) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19, ap_Mask_20_23}}, + {SELFHR, 0xffff000000000000, 0xb9c0000000000000, 0x0, // SELECT HIGH (32) (SELFHR R1,R2,R3,M4) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19, ap_Mask_20_23}}, + {SAR, 0xffff000000000000, 0xb24e000000000000, 0xff0000000000, // SET ACCESS (SAR R1,R2) + [8]*argField{ap_ACReg_24_27, ap_Reg_28_31}}, + {SAL, 0xffff000000000000, 0xb237000000000000, 0xffff00000000, // SET ADDRESS LIMIT (SAL) + [8]*argField{}}, + {SAC, 0xffff000000000000, 0xb219000000000000, 0x0, // SET ADDRESS SPACE CONTROL (SAC D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SACF, 0xffff000000000000, 0xb279000000000000, 0x0, // SET ADDRESS SPACE CONTROL FAST (SACF D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SAM24, 0xffff000000000000, 0x10c000000000000, 0x0, // SET ADDRESSING MODE (24) (SAM24) + [8]*argField{}}, + {SAM31, 0xffff000000000000, 0x10d000000000000, 0x0, // SET ADDRESSING MODE (31) (SAM31) + [8]*argField{}}, + {SAM64, 0xffff000000000000, 0x10e000000000000, 0x0, // SET ADDRESSING MODE (64) (SAM64) + [8]*argField{}}, + {SRNM, 0xffff000000000000, 0xb299000000000000, 0x0, // SET BFP ROUNDING MODE (2 bit) (SRNM D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SRNMB, 0xffff000000000000, 0xb2b8000000000000, 0x0, // SET BFP ROUNDING MODE (3 bit) (SRNMB D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SCHM, 0xffff000000000000, 0xb23c000000000000, 0xffff00000000, // SET CHANNEL MONITOR (SCHM) + [8]*argField{}}, + {SCK, 0xffff000000000000, 0xb204000000000000, 0x0, // SET CLOCK (SCK D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SCKC, 0xffff000000000000, 0xb206000000000000, 0x0, // SET CLOCK COMPARATOR (SCKC D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SCKPF, 0xffff000000000000, 0x107000000000000, 0x0, // SET CLOCK PROGRAMMABLE FIELD (SCKPF) + [8]*argField{}}, + {SPT, 0xffff000000000000, 0xb208000000000000, 0x0, // SET CPU TIMER (SPT D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SRNMT, 0xffff000000000000, 0xb2b9000000000000, 0x0, // SET DFP ROUNDING MODE (SRNMT D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SFPC, 0xffff000000000000, 0xb384000000000000, 0xff0f00000000, // SET FPC (SFPC R1) + [8]*argField{ap_Reg_24_27}}, + {SFASR, 0xffff000000000000, 0xb385000000000000, 0xff0f00000000, // SET FPC AND SIGNAL (SFASR R1) + [8]*argField{ap_Reg_24_27}}, + {SPX, 0xffff000000000000, 0xb210000000000000, 0x0, // SET PREFIX (SPX D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SPM, 0xff00000000000000, 0x400000000000000, 0xf000000000000, // SET PROGRAM MASK (SPM R1) + [8]*argField{ap_Reg_8_11}}, + {SPKA, 0xffff000000000000, 0xb20a000000000000, 0x0, // SET PSW KEY FROM ADDRESS (SPKA D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SSAR, 0xffff000000000000, 0xb225000000000000, 0xff0f00000000, // SET SECONDARY ASN (SSAR R1) + [8]*argField{ap_Reg_24_27}}, + {SSAIR, 0xffff000000000000, 0xb99f000000000000, 0xff0f00000000, // SET SECONDARY ASN WITH INSTANCE (SSAIR R1) + [8]*argField{ap_Reg_24_27}}, + {SSKE, 0xffff000000000000, 0xb22b000000000000, 0xf0000000000, // SET STORAGE KEY EXTENDED (SSKE R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {SSM, 0xff00000000000000, 0x8000000000000000, 0x0, // SET SYSTEM MASK (SSM D1(B1)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SRP, 0xff00000000000000, 0xf000000000000000, 0x0, // SHIFT AND ROUND DECIMAL (SRP D1(L1,B1),D2(B2),I3) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35, ap_ImmUnsigned_12_15}}, + {SLDA, 0xff00000000000000, 0x8f00000000000000, 0xf000000000000, // SHIFT LEFT DOUBLE (64) (SLDA R1,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SLDL, 0xff00000000000000, 0x8d00000000000000, 0xf000000000000, // SHIFT LEFT DOUBLE LOGICAL (64) (SLDL R1,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SLA, 0xff00000000000000, 0x8b00000000000000, 0xf000000000000, // SHIFT LEFT SINGLE (32) (SLA R1,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SLAK, 0xff00000000ff0000, 0xeb00000000dd0000, 0x0, // SHIFT LEFT SINGLE (32) (SLAK R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {SLAG, 0xff00000000ff0000, 0xeb000000000b0000, 0x0, // SHIFT LEFT SINGLE (64) (SLAG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {SLL, 0xff00000000000000, 0x8900000000000000, 0xf000000000000, // SHIFT LEFT SINGLE LOGICAL (32) (SLL R1,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SLLK, 0xff00000000ff0000, 0xeb00000000df0000, 0x0, // SHIFT LEFT SINGLE LOGICAL (32) (SLLK R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {SLLG, 0xff00000000ff0000, 0xeb000000000d0000, 0x0, // SHIFT LEFT SINGLE LOGICAL (64) (SLLG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {SRDA, 0xff00000000000000, 0x8e00000000000000, 0xf000000000000, // SHIFT RIGHT DOUBLE (64) (SRDA R1,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SRDL, 0xff00000000000000, 0x8c00000000000000, 0xf000000000000, // SHIFT RIGHT DOUBLE LOGICAL (64) (SRDL R1,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SRA, 0xff00000000000000, 0x8a00000000000000, 0xf000000000000, // SHIFT RIGHT SINGLE (32) (SRA R1,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SRAK, 0xff00000000ff0000, 0xeb00000000dc0000, 0x0, // SHIFT RIGHT SINGLE (32) (SRAK R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {SRAG, 0xff00000000ff0000, 0xeb000000000a0000, 0x0, // SHIFT RIGHT SINGLE (64) (SRAG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {SRL, 0xff00000000000000, 0x8800000000000000, 0xf000000000000, // SHIFT RIGHT SINGLE LOGICAL (32) (SRL R1,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SRLK, 0xff00000000ff0000, 0xeb00000000de0000, 0x0, // SHIFT RIGHT SINGLE LOGICAL (32) (SRLK R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {SRLG, 0xff00000000ff0000, 0xeb000000000c0000, 0x0, // SHIFT RIGHT SINGLE LOGICAL (64) (SRLG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {SLXT, 0xff00000000ff0000, 0xed00000000480000, 0xf000000, // SHIFT SIGNIFICAND LEFT (extended DFP) (SLXT R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SLDT, 0xff00000000ff0000, 0xed00000000400000, 0xf000000, // SHIFT SIGNIFICAND LEFT (long DFP) (SLDT R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SRXT, 0xff00000000ff0000, 0xed00000000490000, 0xf000000, // SHIFT SIGNIFICAND RIGHT (extended DFP) (SRXT R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SRDT, 0xff00000000ff0000, 0xed00000000410000, 0xf000000, // SHIFT SIGNIFICAND RIGHT (long DFP) (SRDT R1,R3,D2(X2,B2)) + [8]*argField{ap_FPReg_32_35, ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SIGP, 0xff00000000000000, 0xae00000000000000, 0x0, // SIGNAL PROCESSOR (SIGP R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {SORTL, 0xffff000000000000, 0xb938000000000000, 0xff0000000000, // SORT LISTS (SORTL R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SQXBR, 0xffff000000000000, 0xb316000000000000, 0xff0000000000, // SQUARE ROOT (extended BFP) (SQXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SQXR, 0xffff000000000000, 0xb336000000000000, 0xff0000000000, // SQUARE ROOT (extended HFP) (SQXR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SQDB, 0xff00000000ff0000, 0xed00000000150000, 0xff000000, // SQUARE ROOT (long BFP) (SQDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SQDBR, 0xffff000000000000, 0xb315000000000000, 0xff0000000000, // SQUARE ROOT (long BFP) (SQDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SQD, 0xff00000000ff0000, 0xed00000000350000, 0xff000000, // SQUARE ROOT (long HFP) (SQD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SQDR, 0xffff000000000000, 0xb244000000000000, 0xff0000000000, // SQUARE ROOT (long HFP) (SQDR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SQEB, 0xff00000000ff0000, 0xed00000000140000, 0xff000000, // SQUARE ROOT (short BFP) (SQEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SQEBR, 0xffff000000000000, 0xb314000000000000, 0xff0000000000, // SQUARE ROOT (short BFP) (SQEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SQE, 0xff00000000ff0000, 0xed00000000340000, 0xff000000, // SQUARE ROOT (short HFP) (SQE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SQER, 0xffff000000000000, 0xb245000000000000, 0xff0000000000, // SQUARE ROOT (short HFP) (SQER R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SSCH, 0xffff000000000000, 0xb233000000000000, 0x0, // START SUBCHANNEL (SSCH D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {ST, 0xff00000000000000, 0x5000000000000000, 0x0, // STORE (32) (ST R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STY, 0xff00000000ff0000, 0xe300000000500000, 0x0, // STORE (32) (STY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STG, 0xff00000000ff0000, 0xe300000000240000, 0x0, // STORE (64) (STG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STD, 0xff00000000000000, 0x6000000000000000, 0x0, // STORE (long) (STD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STDY, 0xff00000000ff0000, 0xed00000000670000, 0x0, // STORE (long) (STDY R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STE, 0xff00000000000000, 0x7000000000000000, 0x0, // STORE (short) (STE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STEY, 0xff00000000ff0000, 0xed00000000660000, 0x0, // STORE (short) (STEY R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STAM, 0xff00000000000000, 0x9b00000000000000, 0x0, // STORE ACCESS MULTIPLE 7-389 (STAM R1,R3,D2(B2)) + [8]*argField{ap_ACReg_8_11, ap_ACReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STAMY, 0xff00000000ff0000, 0xeb000000009b0000, 0x0, // STORE ACCESS MULTIPLE 7-389 (STAMY R1,R3,D2(B2)) + [8]*argField{ap_ACReg_8_11, ap_ACReg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {STBEAR, 0xffff000000000000, 0xb201000000000000, 0x0, // STORE BEAR (STBEAR D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STCPS, 0xffff000000000000, 0xb23a000000000000, 0x0, // STORE CHANNEL PATH STATUS (STCPS D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STCRW, 0xffff000000000000, 0xb239000000000000, 0x0, // STORE CHANNEL REPORT WORD (STCRW D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STC, 0xff00000000000000, 0x4200000000000000, 0x0, // STORE CHARACTER (STC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STCY, 0xff00000000ff0000, 0xe300000000720000, 0x0, // STORE CHARACTER (STCY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STCH, 0xff00000000ff0000, 0xe300000000c30000, 0x0, // STORE CHARACTER HIGH (8) (STCH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STCMH, 0xff00000000ff0000, 0xeb000000002c0000, 0x0, // STORE CHARACTERS UNDER MASK (high) (STCMH R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {STCM, 0xff00000000000000, 0xbe00000000000000, 0x0, // STORE CHARACTERS UNDER MASK (low) (STCM R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STCMY, 0xff00000000ff0000, 0xeb000000002d0000, 0x0, // STORE CHARACTERS UNDER MASK (low) (STCMY R1,M3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Mask_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {STCK, 0xffff000000000000, 0xb205000000000000, 0x0, // STORE CLOCK (STCK D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STCKC, 0xffff000000000000, 0xb207000000000000, 0x0, // STORE CLOCK COMPARATOR (STCKC D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STCKE, 0xffff000000000000, 0xb278000000000000, 0x0, // STORE CLOCK EXTENDED (STCKE D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STCKF, 0xffff000000000000, 0xb27c000000000000, 0x0, // STORE CLOCK FAST (STCKF D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STCTL, 0xff00000000000000, 0xb600000000000000, 0x0, // STORE CONTROL (32) (STCTL R1,R3,D2(B2)) + [8]*argField{ap_CReg_8_11, ap_CReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STCTG, 0xff00000000ff0000, 0xeb00000000250000, 0x0, // STORE CONTROL (64) (STCTG R1,R3,D2(B2)) + [8]*argField{ap_CReg_8_11, ap_CReg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {STAP, 0xffff000000000000, 0xb212000000000000, 0x0, // STORE CPU ADDRESS (STAP D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STIDP, 0xffff000000000000, 0xb202000000000000, 0x0, // STORE CPU ID (STIDP D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STPT, 0xffff000000000000, 0xb209000000000000, 0x0, // STORE CPU TIMER (STPT D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STFL, 0xffff000000000000, 0xb2b1000000000000, 0x0, // STORE FACILITY LIST (STFL D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STFLE, 0xffff000000000000, 0xb2b0000000000000, 0x0, // STORE FACILITY LIST EXTENDED (STFLE D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STFPC, 0xffff000000000000, 0xb29c000000000000, 0x0, // STORE FPC (STFPC D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STGSC, 0xff00000000ff0000, 0xe300000000490000, 0x0, // STORE GUARDED STORAGE CONTROLS (STGSC R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STH, 0xff00000000000000, 0x4000000000000000, 0x0, // STORE HALFWORD (16) (STH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STHY, 0xff00000000ff0000, 0xe300000000700000, 0x0, // STORE HALFWORD (16) (STHY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STHH, 0xff00000000ff0000, 0xe300000000c70000, 0x0, // STORE HALFWORD HIGH (16) (STHH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STHRL, 0xff0f000000000000, 0xc407000000000000, 0x0, // STORE HALFWORD RELATIVE LONG (16) (STHRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {STFH, 0xff00000000ff0000, 0xe300000000cb0000, 0x0, // STORE HIGH (32) (STFH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STOCFH, 0xff00000000ff0000, 0xeb00000000e10000, 0x0, // STORE HIGH ON CONDITION (STOCFH R1,D2(B2),M3) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}}, + {STM, 0xff00000000000000, 0x9000000000000000, 0x0, // STORE MULTIPLE (32) (STM R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STMY, 0xff00000000ff0000, 0xeb00000000900000, 0x0, // STORE MULTIPLE (32) (STMY R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {STMG, 0xff00000000ff0000, 0xeb00000000240000, 0x0, // STORE MULTIPLE (64) (STMG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {STMH, 0xff00000000ff0000, 0xeb00000000260000, 0x0, // STORE MULTIPLE HIGH (32) (STMH R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {STOC, 0xff00000000ff0000, 0xeb00000000f30000, 0x0, // STORE ON CONDITION (32) (STOC R1,D2(B2),M3) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}}, + {STOCG, 0xff00000000ff0000, 0xeb00000000e30000, 0x0, // STORE ON CONDITION (64) (STOCG R1,D2(B2),M3) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_Mask_12_15}}, + {STPQ, 0xff00000000ff0000, 0xe3000000008e0000, 0x0, // STORE PAIR TO QUADWORD (STPQ R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STPX, 0xffff000000000000, 0xb211000000000000, 0x0, // STORE PREFIX (STPX D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STRAG, 0xffff000000000000, 0xe502000000000000, 0x0, // STORE REAL ADDRESS (STRAG D1(B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {STRL, 0xff0f000000000000, 0xc40f000000000000, 0x0, // STORE RELATIVE LONG (32) (STRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {STGRL, 0xff0f000000000000, 0xc40b000000000000, 0x0, // STORE RELATIVE LONG (64) (STGRL R1,RI2) + [8]*argField{ap_Reg_8_11, ap_RegImSigned32_16_47}}, + {STRVH, 0xff00000000ff0000, 0xe3000000003f0000, 0x0, // STORE REVERSED (16) (STRVH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STRV, 0xff00000000ff0000, 0xe3000000003e0000, 0x0, // STORE REVERSED (32) (STRV R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STRVG, 0xff00000000ff0000, 0xe3000000002f0000, 0x0, // STORE REVERSED (64) (STRVG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {STSCH, 0xffff000000000000, 0xb234000000000000, 0x0, // STORE SUBCHANNEL (STSCH D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STSI, 0xffff000000000000, 0xb27d000000000000, 0x0, // STORE SYSTEM INFORMATION (STSI D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {STNSM, 0xff00000000000000, 0xac00000000000000, 0x0, // STORE THEN AND SYSTEM MASK (STNSM D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {STOSM, 0xff00000000000000, 0xad00000000000000, 0x0, // STORE THEN OR SYSTEM MASK (STOSM D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {STURA, 0xffff000000000000, 0xb246000000000000, 0xff0000000000, // STORE USING REAL ADDRESS (32) (STURA R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {STURG, 0xffff000000000000, 0xb925000000000000, 0xff0000000000, // STORE USING REAL ADDRESS (64) (STURG R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {S, 0xff00000000000000, 0x5b00000000000000, 0x0, // SUBTRACT (32) (S R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SR, 0xff00000000000000, 0x1b00000000000000, 0x0, // SUBTRACT (32) (SR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {SRK, 0xffff000000000000, 0xb9f9000000000000, 0xf0000000000, // SUBTRACT (32) (SRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {SY, 0xff00000000ff0000, 0xe3000000005b0000, 0x0, // SUBTRACT (32) (SY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SG, 0xff00000000ff0000, 0xe300000000090000, 0x0, // SUBTRACT (64) (SG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SGR, 0xffff000000000000, 0xb909000000000000, 0xff0000000000, // SUBTRACT (64) (SGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SGRK, 0xffff000000000000, 0xb9e9000000000000, 0xf0000000000, // SUBTRACT (64) (SGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {SGF, 0xff00000000ff0000, 0xe300000000190000, 0x0, // SUBTRACT (64←32) (SGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SGFR, 0xffff000000000000, 0xb919000000000000, 0xff0000000000, // SUBTRACT (64→32) (SGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SXBR, 0xffff000000000000, 0xb34b000000000000, 0xff0000000000, // SUBTRACT (extended BFP) (SXBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SXTR, 0xffff000000000000, 0xb3db000000000000, 0xf0000000000, // SUBTRACT (extended DFP) (SXTR R1,R2,R3) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}}, + {SXTRA, 0xffff000000000000, 0xb3db000000000000, 0x0, // SUBTRACT (extended DFP) (SXTRA R1,R2,R3,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}}, + {SDB, 0xff00000000ff0000, 0xed000000001b0000, 0xff000000, // SUBTRACT (long BFP) (SDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SDBR, 0xffff000000000000, 0xb31b000000000000, 0xff0000000000, // SUBTRACT (long BFP) (SDBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SDTR, 0xffff000000000000, 0xb3d3000000000000, 0xf0000000000, // SUBTRACT (long DFP) (SDTR R1,R2,R3) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19}}, + {SDTRA, 0xffff000000000000, 0xb3d3000000000000, 0x0, // SUBTRACT (long DFP) (SDTRA R1,R2,R3,M4) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31, ap_FPReg_16_19, ap_Mask_20_23}}, + {SEB, 0xff00000000ff0000, 0xed000000000b0000, 0xff000000, // SUBTRACT (short BFP) (SEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SEBR, 0xffff000000000000, 0xb30b000000000000, 0xff0000000000, // SUBTRACT (short BFP) (SEBR R1,R2) + [8]*argField{ap_FPReg_24_27, ap_FPReg_28_31}}, + {SP, 0xff00000000000000, 0xfb00000000000000, 0x0, // SUBTRACT DECIMAL (SP D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, + {SH, 0xff00000000000000, 0x4b00000000000000, 0x0, // SUBTRACT HALFWORD (32←16) (SH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SHY, 0xff00000000ff0000, 0xe3000000007b0000, 0x0, // SUBTRACT HALFWORD (32→16) (SHY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SGH, 0xff00000000ff0000, 0xe300000000390000, 0x0, // SUBTRACT HALFWORD (64→16) (SGH R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SHHHR, 0xffff000000000000, 0xb9c9000000000000, 0xf0000000000, // SUBTRACT HIGH (32) (SHHHR R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {SHHLR, 0xffff000000000000, 0xb9d9000000000000, 0xf0000000000, // SUBTRACT HIGH (32) (SHHLR R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {SL, 0xff00000000000000, 0x5f00000000000000, 0x0, // SUBTRACT LOGICAL (32) (SL R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SLR, 0xff00000000000000, 0x1f00000000000000, 0x0, // SUBTRACT LOGICAL (32) (SLR R1,R2) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15}}, + {SLRK, 0xffff000000000000, 0xb9fb000000000000, 0xf0000000000, // SUBTRACT LOGICAL (32) (SLRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {SLY, 0xff00000000ff0000, 0xe3000000005f0000, 0x0, // SUBTRACT LOGICAL (32) (SLY R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SLG, 0xff00000000ff0000, 0xe3000000000b0000, 0x0, // SUBTRACT LOGICAL (64) (SLG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SLGR, 0xffff000000000000, 0xb90b000000000000, 0xff0000000000, // SUBTRACT LOGICAL (64) (SLGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SLGRK, 0xffff000000000000, 0xb9eb000000000000, 0xf0000000000, // SUBTRACT LOGICAL (64) (SLGRK R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {SLGF, 0xff00000000ff0000, 0xe3000000001b0000, 0x0, // SUBTRACT LOGICAL (64←32) (SLGF R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SLGFR, 0xffff000000000000, 0xb91b000000000000, 0xff0000000000, // SUBTRACT LOGICAL (64←32) (SLGFR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SLHHHR, 0xffff000000000000, 0xb9cb000000000000, 0xf0000000000, // SUBTRACT LOGICAL HIGH (32) (SLHHHR R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {SLHHLR, 0xffff000000000000, 0xb9db000000000000, 0xf0000000000, // SUBTRACT LOGICAL HIGH (32) (SLHHLR R1,R2,R3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Reg_16_19}}, + {SLFI, 0xff0f000000000000, 0xc205000000000000, 0x0, // SUBTRACT LOGICAL IMMEDIATE (32) (SLFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {SLGFI, 0xff0f000000000000, 0xc204000000000000, 0x0, // SUBTRACT LOGICAL IMMEDIATE (64→32) (SLGFI R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_47}}, + {SLB, 0xff00000000ff0000, 0xe300000000990000, 0x0, // SUBTRACT LOGICAL WITH BORROW (32) (SLB R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SLBR, 0xffff000000000000, 0xb999000000000000, 0xff0000000000, // SUBTRACT LOGICAL WITH BORROW (32) (SLBR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SLBG, 0xff00000000ff0000, 0xe300000000890000, 0x0, // SUBTRACT LOGICAL WITH BORROW (64) (SLBG R1,D2(X2,B2)) + [8]*argField{ap_Reg_8_11, ap_DispSigned20_20_39, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SLBGR, 0xffff000000000000, 0xb989000000000000, 0xff0000000000, // SUBTRACT LOGICAL WITH BORROW (64) (SLBGR R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {SXR, 0xff00000000000000, 0x3700000000000000, 0x0, // SUBTRACT NORMALIZED (extended HFP) (SXR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {SD, 0xff00000000000000, 0x6b00000000000000, 0x0, // SUBTRACT NORMALIZED (long HFP) (SD R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SDR, 0xff00000000000000, 0x2b00000000000000, 0x0, // SUBTRACT NORMALIZED (long HFP) (SDR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {SE, 0xff00000000000000, 0x7b00000000000000, 0x0, // SUBTRACT NORMALIZED (short HFP) (SE R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SER, 0xff00000000000000, 0x3b00000000000000, 0x0, // SUBTRACT NORMALIZED (short HFP) (SER R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {SW, 0xff00000000000000, 0x6f00000000000000, 0x0, // SUBTRACT UNNORMALIZED (long HFP) (SW R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SWR, 0xff00000000000000, 0x2f00000000000000, 0x0, // SUBTRACT UNNORMALIZED (long HFP) (SWR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {SU, 0xff00000000000000, 0x7f00000000000000, 0x0, // SUBTRACT UNNORMALIZED (short HFP) (SU R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {SUR, 0xff00000000000000, 0x3f00000000000000, 0x0, // SUBTRACT UNNORMALIZED (short HFP) (SUR R1,R2) + [8]*argField{ap_FPReg_8_11, ap_FPReg_12_15}}, + {SVC, 0xff00000000000000, 0xa00000000000000, 0x0, // SUPERVISOR CALL (SVC I) + [8]*argField{ap_ImmUnsigned_8_15}}, + {TAR, 0xffff000000000000, 0xb24c000000000000, 0xff0000000000, // TEST ACCESS (TAR R1,R2) + [8]*argField{ap_ACReg_24_27, ap_Reg_28_31}}, + {TAM, 0xffff000000000000, 0x10b000000000000, 0x0, // TEST ADDRESSING MODE (TAM) + [8]*argField{}}, + {TS, 0xff00000000000000, 0x9300000000000000, 0x0, // TEST AND SET (TS D1(B1)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {TB, 0xffff000000000000, 0xb22c000000000000, 0xff0000000000, // TEST BLOCK (TB R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {TCXB, 0xff00000000ff0000, 0xed00000000120000, 0xff000000, // TEST DATA CLASS (extended BFP) (TCXB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TDCXT, 0xff00000000ff0000, 0xed00000000580000, 0xff000000, // TEST DATA CLASS (extended DFP) (TDCXT R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TCDB, 0xff00000000ff0000, 0xed00000000110000, 0xff000000, // TEST DATA CLASS (long BFP) (TCDB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TDCDT, 0xff00000000ff0000, 0xed00000000540000, 0xff000000, // TEST DATA CLASS (long DFP) (TDCDT R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TCEB, 0xff00000000ff0000, 0xed00000000100000, 0xff000000, // TEST DATA CLASS (short BFP) (TCEB R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TDCET, 0xff00000000ff0000, 0xed00000000500000, 0xff000000, // TEST DATA CLASS (short DFP) (TDCET R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TDGXT, 0xff00000000ff0000, 0xed00000000590000, 0xff000000, // TEST DATA GROUP (extended DFP) (TDGXT R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TDGDT, 0xff00000000ff0000, 0xed00000000550000, 0xff000000, // TEST DATA GROUP (long DFP) (TDGDT R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TDGET, 0xff00000000ff0000, 0xed00000000510000, 0xff000000, // TEST DATA GROUP (short DFP) (TDGET R1,D2(X2,B2)) + [8]*argField{ap_FPReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19}}, + {TP, 0xff00000000ff0000, 0xeb00000000c00000, 0xf0000ff000000, // TEST DECIMAL (TP D1(L1,B1)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19}}, + {TPEI, 0xffff000000000000, 0xb9a1000000000000, 0xff0000000000, // TEST PENDING EXTERNAL INTERRUPTION (TPEI R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {TPI, 0xffff000000000000, 0xb236000000000000, 0x0, // TEST PENDING INTERRUPTION (TPI D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {TPROT, 0xffff000000000000, 0xe501000000000000, 0x0, // TEST PROTECTION (TPROT D1(B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {TSCH, 0xffff000000000000, 0xb235000000000000, 0x0, // TEST SUBCHANNEL (TSCH D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {TM, 0xff00000000000000, 0x9100000000000000, 0x0, // TEST UNDER MASK (TM D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {TMY, 0xff00000000ff0000, 0xeb00000000510000, 0x0, // TEST UNDER MASK (TMY D1(B1),I2) + [8]*argField{ap_DispSigned20_20_39, ap_BaseReg_16_19, ap_ImmUnsigned_8_15}}, + {TMHH, 0xff0f000000000000, 0xa702000000000000, 0x0, // TEST UNDER MASK (high high) (TMHH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {TMHL, 0xff0f000000000000, 0xa703000000000000, 0x0, // TEST UNDER MASK (high low) (TMHL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {TMLH, 0xff0f000000000000, 0xa700000000000000, 0x0, // TEST UNDER MASK (low high) (TMLH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {TMLL, 0xff0f000000000000, 0xa701000000000000, 0x0, // TEST UNDER MASK (low low) (TMLL R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {TMH, 0xff0f000000000000, 0xa700000000000000, 0x0, // TEST UNDER MASK HIGH (TMH R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {TML, 0xff0f000000000000, 0xa701000000000000, 0x0, // TEST UNDER MASK LOW (TML R1,I2) + [8]*argField{ap_Reg_8_11, ap_ImmUnsigned_16_31}}, + {TRACE, 0xff00000000000000, 0x9900000000000000, 0x0, // TRACE (32) (TRACE R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {TRACG, 0xff00000000ff0000, 0xeb000000000f0000, 0x0, // TRACE (64) (TRACG R1,R3,D2(B2)) + [8]*argField{ap_Reg_8_11, ap_Reg_12_15, ap_DispSigned20_20_39, ap_BaseReg_16_19}}, + {TABORT, 0xffff000000000000, 0xb2fc000000000000, 0x0, // TRANSACTION ABORT (TABORT D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {TBEGINC, 0xffff000000000000, 0xe561000000000000, 0x0, // TRANSACTION BEGIN (constrained) (TBEGINC D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}}, + {TBEGIN, 0xffff000000000000, 0xe560000000000000, 0x0, // TRANSACTION BEGIN (nonconstrained) (TBEGIN D1(B1),I2) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_32_47}}, + {TEND, 0xffff000000000000, 0xb2f8000000000000, 0xffff00000000, // TRANSACTION END (TEND) + [8]*argField{}}, + {TR, 0xff00000000000000, 0xdc00000000000000, 0x0, // TRANSLATE (TR D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {TRT, 0xff00000000000000, 0xdd00000000000000, 0x0, // TRANSLATE AND TEST (TRT D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {TRTE, 0xffff000000000000, 0xb9bf000000000000, 0xf0000000000, // TRANSLATE AND TEST EXTENDED (TRTE R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {TRTR, 0xff00000000000000, 0xd000000000000000, 0x0, // TRANSLATE AND TEST REVERSE (TRTR D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {TRTRE, 0xffff000000000000, 0xb9bd000000000000, 0xf0000000000, // TRANSLATE AND TEST REVERSE EXTENDED (TRTRE R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {TRE, 0xffff000000000000, 0xb2a5000000000000, 0xff0000000000, // TRANSLATE EXTENDED (TRE R1,R2) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31}}, + {TROO, 0xffff000000000000, 0xb993000000000000, 0xf0000000000, // TRANSLATE ONE TO ONE (TROO R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {TROT, 0xffff000000000000, 0xb992000000000000, 0xf0000000000, // TRANSLATE ONE TO TWO (TROT R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {TRTO, 0xffff000000000000, 0xb991000000000000, 0xf0000000000, // TRANSLATE TWO TO ONE (TRTO R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {TRTT, 0xffff000000000000, 0xb990000000000000, 0xf0000000000, // TRANSLATE TWO TO TWO (TRTT R1,R2,M3) + [8]*argField{ap_Reg_24_27, ap_Reg_28_31, ap_Mask_16_19}}, + {TRAP2, 0xffff000000000000, 0x1ff000000000000, 0x0, // TRAP (TRAP2) + [8]*argField{}}, + {TRAP4, 0xffff000000000000, 0xb2ff000000000000, 0x0, // TRAP (TRAP4 D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_BaseReg_16_19}}, + {UNPK, 0xff00000000000000, 0xf300000000000000, 0x0, // UNPACK (UNPK D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, + {UNPKA, 0xff00000000000000, 0xea00000000000000, 0x0, // UNPACK ASCII (UNPKA D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {UNPKU, 0xff00000000000000, 0xe200000000000000, 0x0, // UNPACK UNICODE (UNPKU D1(L1,B1),D2(B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_15, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_BaseReg_32_35}}, + {UPT, 0xffff000000000000, 0x102000000000000, 0x0, // UPDATE TREE (UPT) + [8]*argField{}}, + {VA, 0xff00000000ff0000, 0xe700000000f30000, 0xfff00000000, // VECTOR ADD (VA V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VACC, 0xff00000000ff0000, 0xe700000000f10000, 0xfff00000000, // VECTOR ADD COMPUTE CARRY (VACC V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VAP, 0xff00000000ff0000, 0xe600000000710000, 0xf0000000000, // VECTOR ADD DECIMAL (VAP V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VAC, 0xff00000000ff0000, 0xe700000000bb0000, 0xff00000000, // VECTOR ADD WITH CARRY (VAC V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VACCC, 0xff00000000ff0000, 0xe700000000b90000, 0xff00000000, // VECTOR ADD WITH CARRY COMPUTE CARRY (VACCC V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VN, 0xff00000000ff0000, 0xe700000000680000, 0xffff0000000, // VECTOR AND (VN V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VNC, 0xff00000000ff0000, 0xe700000000690000, 0xffff0000000, // VECTOR AND WITH COMPLEMENT (VNC V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VAVG, 0xff00000000ff0000, 0xe700000000f20000, 0xfff00000000, // VECTOR AVERAGE (VAVG V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VAVGL, 0xff00000000ff0000, 0xe700000000f00000, 0xfff00000000, // VECTOR AVERAGE LOGICAL (VAVGL V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VBPERM, 0xff00000000ff0000, 0xe700000000850000, 0xffff0000000, // VECTOR BIT PERMUTE (VBPERM V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VCKSM, 0xff00000000ff0000, 0xe700000000660000, 0xffff0000000, // VECTOR CHECKSUM (VCKSM V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VCP, 0xff00000000ff0000, 0xe600000000770000, 0xf00f0ff0000000, // VECTOR COMPARE DECIMAL (VCP V1,V2,M3) + [8]*argField{ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCEQ, 0xff00000000ff0000, 0xe700000000f80000, 0xf0f00000000, // VECTOR COMPARE EQUAL (VCEQ V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCH, 0xff00000000ff0000, 0xe700000000fb0000, 0xf0f00000000, // VECTOR COMPARE HIGH (VCH V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCHL, 0xff00000000ff0000, 0xe700000000f90000, 0xf0f00000000, // VECTOR COMPARE HIGH LOGICAL (VCHL V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCSPH, 0xff00000000ff0000, 0xe6000000007d0000, 0xf0ff0000000, // VECTOR CONVERT HFP TO SCALED DECIMAL (VCSPH V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCVB, 0xff00000000ff0000, 0xe600000000500000, 0xff00f0000000, // VECTOR CONVERT TO BINARY (VCVB R1,V2,M3,M4) + [8]*argField{ap_Reg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VCVBG, 0xff00000000ff0000, 0xe600000000520000, 0xff00f0000000, // VECTOR CONVERT TO BINARY (VCVBG R1,V2,M3,M4) + [8]*argField{ap_Reg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VCVD, 0xff00000000ff0000, 0xe600000000580000, 0xff0000000000, // VECTOR CONVERT TO DECIMAL (VCVD V1,R2,I3,M4) + [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCVDG, 0xff00000000ff0000, 0xe6000000005a0000, 0xff0000000000, // VECTOR CONVERT TO DECIMAL (VCVDG V1,R2,I3,M4) + [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCLZDP, 0xff00000000ff0000, 0xe600000000510000, 0xff0ff0000000, // VECTOR COUNT LEADING ZERO DIGITS (VCLZDP V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCLZ, 0xff00000000ff0000, 0xe700000000530000, 0xffff00000000, // VECTOR COUNT LEADING ZEROS (VCLZ V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VCTZ, 0xff00000000ff0000, 0xe700000000520000, 0xffff00000000, // VECTOR COUNT TRAILING ZEROS (VCTZ V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VDP, 0xff00000000ff0000, 0xe6000000007a0000, 0xf0000000000, // VECTOR DIVIDE DECIMAL (VDP V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VEC, 0xff00000000ff0000, 0xe700000000db0000, 0xffff00000000, // VECTOR ELEMENT COMPARE (VEC V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VECL, 0xff00000000ff0000, 0xe700000000d90000, 0xffff00000000, // VECTOR ELEMENT COMPARE LOGICAL (VECL V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VERIM, 0xff00000000ff0000, 0xe700000000720000, 0xf0000000000, // VECTORELEMENTROTATEANDINSERTUNDER MASK (VERIM V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_24_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VERLL, 0xff00000000ff0000, 0xe700000000330000, 0x0, // VECTOR ELEMENT ROTATE LEFT LOGICAL (VERLL V1,V3,D2(B2),M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VERLLV, 0xff00000000ff0000, 0xe700000000730000, 0xfff00000000, // VECTOR ELEMENT ROTATE LEFT LOGICAL (VERLLV V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VESLV, 0xff00000000ff0000, 0xe700000000700000, 0xfff00000000, // VECTOR ELEMENT SHIFT LEFT (VESLV V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VESL, 0xff00000000ff0000, 0xe700000000300000, 0x0, // VECTOR ELEMENT SHIFT LEFT (VESL V1,V3,D2(B2),M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VESRA, 0xff00000000ff0000, 0xe7000000003a0000, 0x0, // VECTOR ELEMENT SHIFT RIGHT ARITHMETIC (VESRA V1,V3,D2(B2),M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VESRAV, 0xff00000000ff0000, 0xe7000000007a0000, 0xfff00000000, // VECTOR ELEMENT SHIFT RIGHT ARITHMETIC (VESRAV V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VESRL, 0xff00000000ff0000, 0xe700000000380000, 0x0, // VECTOR ELEMENT SHIFT RIGHT LOGICAL (VESRL V1,V3,D2(B2),M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VESRLV, 0xff00000000ff0000, 0xe700000000780000, 0xfff00000000, // VECTOR ELEMENT SHIFT RIGHT LOGICAL (VESRLV V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VX, 0xff00000000ff0000, 0xe7000000006d0000, 0xffff0000000, // VECTOR EXCLUSIVE OR (VX V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VFAE, 0xff00000000ff0000, 0xe700000000820000, 0xf0f00000000, // VECTOR FIND ANY ELEMENT EQUAL (VFAE V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFEE, 0xff00000000ff0000, 0xe700000000800000, 0xf0f00000000, // VECTOR FIND ELEMENT EQUAL (VFEE V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFENE, 0xff00000000ff0000, 0xe700000000810000, 0xf0f00000000, // VECTOR FIND ELEMENT NOT EQUAL (VFENE V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFA, 0xff00000000ff0000, 0xe700000000e30000, 0xff000000000, // VECTOR FP ADD (VFA V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {WFK, 0xff00000000ff0000, 0xe700000000ca0000, 0xfff000000000, // VECTOR FP COMPARE AND SIGNAL SCALAR (WFK V1,V2,M3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VFCE, 0xff00000000ff0000, 0xe700000000e80000, 0xf0000000000, // VECTOR FP COMPARE EQUAL (VFCE V1,V2,V3,M4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFCH, 0xff00000000ff0000, 0xe700000000eb0000, 0xf0000000000, // VECTOR FP COMPARE HIGH (VFCH V1,V2,V3,M4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFCHE, 0xff00000000ff0000, 0xe700000000ea0000, 0xf0000000000, // VECTOR FP COMPARE HIGH OR EQUAL (VFCHE V1,V2,V3,M4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {WFC, 0xff00000000ff0000, 0xe700000000cb0000, 0xfff000000000, // VECTOR FP COMPARE SCALAR (WFC V1,V2,M3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VCLFNH, 0xff00000000ff0000, 0xe600000000560000, 0xfff000000000, // VECTOR FP CONVERT AND LENGTHEN FROM NNP HIGH (VCLFNH V1,V2,M3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VCLFNL, 0xff00000000ff0000, 0xe6000000005e0000, 0xfff000000000, // VECTOR FP CONVERT AND LENGTHEN FROM NNP LOW (VCLFNL V1,V2,M3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VCRNF, 0xff00000000ff0000, 0xe600000000750000, 0xff000000000, // VECTOR FP CONVERT AND ROUND TO NNP (VCRNF V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VCFPS, 0xff00000000ff0000, 0xe700000000c30000, 0xff0000000000, // VECTOR FP CONVERT FROM FIXED (VCFPS V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCDG, 0xff00000000ff0000, 0xe700000000c30000, 0xff0000000000, // VECTOR FP CONVERT FROM FIXED 64-BIT (VCDG V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCFPL, 0xff00000000ff0000, 0xe700000000c10000, 0xff0000000000, // VECTOR FP CONVERT FROM LOGICAL (VCFPL V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCDLG, 0xff00000000ff0000, 0xe700000000c10000, 0xff0000000000, // VECTOR FP CONVERT FROM LOGICAL 64-BIT (VCDLG V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCFN, 0xff00000000ff0000, 0xe6000000005d0000, 0xfff000000000, // VECTOR FP CONVERT FROM NNP (VCFN V1,V2,M3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VCSFP, 0xff00000000ff0000, 0xe700000000c20000, 0xff0000000000, // VECTOR FP CONVERT TO FIXED (VCSFP V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCGD, 0xff00000000ff0000, 0xe700000000c20000, 0xff0000000000, // VECTOR FP CONVERT TO FIXED 64-BIT (VCGD V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCLFP, 0xff00000000ff0000, 0xe700000000c00000, 0xff0000000000, // VECTOR FP CONVERT TO LOGICAL (VCLFP V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCLGD, 0xff00000000ff0000, 0xe700000000c00000, 0xff0000000000, // VECTOR FP CONVERT TO LOGICAL 64-BIT (VCLGD V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VCNF, 0xff00000000ff0000, 0xe600000000550000, 0xfff000000000, // VECTOR FP CONVERT TO NNP (VCNF V1,V2,M3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VFD, 0xff00000000ff0000, 0xe700000000e50000, 0xff000000000, // VECTOR FP DIVIDE (VFD V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VFLL, 0xff00000000ff0000, 0xe700000000c40000, 0xfff000000000, // VECTOR FP LOAD LENGTHENED (VFLL V1,V2,M3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VFLR, 0xff00000000ff0000, 0xe700000000c50000, 0xff0000000000, // VECTOR FP LOAD ROUNDED (VFLR V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFMAX, 0xff00000000ff0000, 0xe700000000ef0000, 0xf0000000000, // VECTOR FP MAXIMUM (VFMAX V1,V2,V3,M4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFMIN, 0xff00000000ff0000, 0xe700000000ee0000, 0xf0000000000, // VECTOR FP MINIMUM (VFMIN V1,V2,V3,M4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFM, 0xff00000000ff0000, 0xe700000000e70000, 0xff000000000, // VECTOR FP MULTIPLY (VFM V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VFMA, 0xff00000000ff0000, 0xe7000000008f0000, 0xf000000000, // VECTOR FP MULTIPLY AND ADD (VFMA V1,V2,V3,V4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_28_31, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VFMS, 0xff00000000ff0000, 0xe7000000008e0000, 0xf000000000, // VECTOR FP MULTIPLY AND SUBTRACT (VFMS V1,V2,V3,V4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_28_31, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VFNMA, 0xff00000000ff0000, 0xe7000000009f0000, 0xf000000000, // VECTOR FP NEGATIVE MULTIPLY AND ADD (VFNMA V1,V2,V3,V4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_28_31, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VFNMS, 0xff00000000ff0000, 0xe7000000009e0000, 0xf000000000, // VECTOR FP NEGATIVE MULTIPLY AND SUBTRACT (VFNMS V1,V2,V3,V4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_28_31, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VFPSO, 0xff00000000ff0000, 0xe700000000cc0000, 0xff0000000000, // VECTOR FP PERFORM SIGN OPERATION (VFPSO V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VFSQ, 0xff00000000ff0000, 0xe700000000ce0000, 0xfff000000000, // VECTOR FP SQUARE ROOT (VFSQ V1,V2,M3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VFS, 0xff00000000ff0000, 0xe700000000e20000, 0xff000000000, // VECTOR FP SUBTRACT (VFS V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VFTCI, 0xff00000000ff0000, 0xe7000000004a0000, 0x0, // VECTOR FP TEST DATA CLASS IMMEDIATE (VFTCI V1,V2,I3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_16_27, ap_Mask_32_35, ap_Mask_28_31, ap_ImmUnsigned_36_39}}, + {VGFM, 0xff00000000ff0000, 0xe700000000b40000, 0xfff00000000, // VECTOR GALOIS FIELD MULTIPLY SUM (VGFM V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VGFMA, 0xff00000000ff0000, 0xe700000000bc0000, 0xff00000000, // VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE (VGFMA V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VGEF, 0xff00000000ff0000, 0xe700000000130000, 0x0, // VECTOR GATHER ELEMENT (32) (VGEF V1,D2(V2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_VecReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VGEG, 0xff00000000ff0000, 0xe700000000120000, 0x0, // VECTOR GATHER ELEMENT (64) (VGEG V1,D2(V2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_VecReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VGBM, 0xff00000000ff0000, 0xe700000000440000, 0xf0000f0000000, // VECTOR GENERATE BYTE MASK (VGBM V1,I2) + [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_ImmUnsigned_36_39}}, + {VGM, 0xff00000000ff0000, 0xe700000000460000, 0xf000000000000, // VECTOR GENERATE MASK (VGM V1,I2,I3,M4) + [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_23, ap_ImmUnsigned_24_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VISTR, 0xff00000000ff0000, 0xe7000000005c0000, 0xff0f00000000, // VECTOR ISOLATE STRING (VISTR V1,V2,M3,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VL, 0xff00000000ff0000, 0xe700000000060000, 0x0, // VECTOR LOAD (VL V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLR, 0xff00000000ff0000, 0xe700000000560000, 0xfffff0000000, // VECTOR LOAD (VLR V1,V2) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_36_39}}, + {VLREP, 0xff00000000ff0000, 0xe700000000050000, 0x0, // VECTOR LOAD AND REPLICATE (VLREP V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEBRH, 0xff00000000ff0000, 0xe600000000010000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT (16) (VLEBRH V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEBRF, 0xff00000000ff0000, 0xe600000000030000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT (32) (VLEBRF V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEBRG, 0xff00000000ff0000, 0xe600000000020000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT (64) (VLEBRG V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLBRREP, 0xff00000000ff0000, 0xe600000000050000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT AND REPLICATE (VLBRREP V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLLEBRZ, 0xff00000000ff0000, 0xe600000000040000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENT AND ZERO (VLLEBRZ V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLBR, 0xff00000000ff0000, 0xe600000000060000, 0x0, // VECTOR LOAD BYTE REVERSED ELEMENTS (VLBR V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLC, 0xff00000000ff0000, 0xe700000000de0000, 0xffff00000000, // VECTOR LOAD COMPLEMENT (VLC V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEH, 0xff00000000ff0000, 0xe700000000010000, 0x0, // VECTOR LOAD ELEMENT (16) (VLEH V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEF, 0xff00000000ff0000, 0xe700000000030000, 0x0, // VECTOR LOAD ELEMENT (32) (VLEF V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEG, 0xff00000000ff0000, 0xe700000000020000, 0x0, // VECTOR LOAD ELEMENT (64) (VLEG V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEB, 0xff00000000ff0000, 0xe700000000000000, 0x0, // VECTOR LOAD ELEMENT (8) (VLEB V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEIH, 0xff00000000ff0000, 0xe700000000410000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (16) (VLEIH V1,I2,M3) + [8]*argField{ap_VecReg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEIF, 0xff00000000ff0000, 0xe700000000430000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (32) (VLEIF V1,I2,M3) + [8]*argField{ap_VecReg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEIG, 0xff00000000ff0000, 0xe700000000420000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (64) (VLEIG V1,I2,M3) + [8]*argField{ap_VecReg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLEIB, 0xff00000000ff0000, 0xe700000000400000, 0xf000000000000, // VECTOR LOAD ELEMENT IMMEDIATE (8) (VLEIB V1,I2,M3) + [8]*argField{ap_VecReg_8_11, ap_ImmSigned16_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLER, 0xff00000000ff0000, 0xe600000000070000, 0x0, // VECTOR LOAD ELEMENTS REVERSED (VLER V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VFI, 0xff00000000ff0000, 0xe700000000c70000, 0xff0000000000, // VECTOR LOAD FP INTEGER (VFI V1,V2,M3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_Mask_28_31, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VLGV, 0xff00000000ff0000, 0xe700000000210000, 0x0, // VECTOR LOAD GR FROM VR ELEMENT (VLGV R1,V3,D2(B2),M4) + [8]*argField{ap_Reg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLIP, 0xff00000000ff0000, 0xe600000000490000, 0xf000000000000, // VECTOR LOAD IMMEDIATE DECIMAL (VLIP V1,I2,I3) + [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_ImmUnsigned_32_35, ap_ImmUnsigned_36_39}}, + {VLLEZ, 0xff00000000ff0000, 0xe700000000040000, 0x0, // VECTOR LOAD LOGICAL ELEMENT AND ZERO (VLLEZ V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLM, 0xff00000000ff0000, 0xe700000000360000, 0x0, // VECTOR LOAD MULTIPLE (VLM V1,V3,D2(B2),M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLP, 0xff00000000ff0000, 0xe700000000df0000, 0xffff00000000, // VECTOR LOAD POSITIVE (VLP V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLRL, 0xff00000000ff0000, 0xe600000000350000, 0x0, // VECTOR LOAD RIGHTMOST WITH LENGTH (VLRL V1,D2(B2),I3) + [8]*argField{ap_VecReg_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15, ap_ImmUnsigned_36_39}}, + {VLRLR, 0xff00000000ff0000, 0xe600000000370000, 0xf0000000000000, // VECTOR LOAD RIGHTMOST WITH LENGTH (VLRLR V1,R3,D2(B2)) + [8]*argField{ap_VecReg_32_35, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_36_39}}, + {VLBB, 0xff00000000ff0000, 0xe700000000070000, 0x0, // VECTOR LOAD TO BLOCK BOUNDARY (VLBB V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLVG, 0xff00000000ff0000, 0xe700000000220000, 0x0, // VECTOR LOAD VR ELEMENT FROM GR (VLVG V1,R3,D2(B2),M4) + [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VLVGP, 0xff00000000ff0000, 0xe700000000620000, 0xffff0000000, // VECTOR LOAD VR FROM GRS DISJOINT (VLVGP V1,R2,R3) + [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_Reg_16_19, ap_ImmUnsigned_36_39}}, + {VLL, 0xff00000000ff0000, 0xe700000000370000, 0xf0000000, // VECTOR LOAD WITH LENGTH (VLL V1,R3,D2(B2)) + [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_36_39}}, + {VMX, 0xff00000000ff0000, 0xe700000000ff0000, 0xfff00000000, // VECTOR MAXIMUM (VMX V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMXL, 0xff00000000ff0000, 0xe700000000fd0000, 0xfff00000000, // VECTOR MAXIMUM LOGICAL (VMXL V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMRH, 0xff00000000ff0000, 0xe700000000610000, 0xfff00000000, // VECTOR MERGE HIGH (VMRH V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMRL, 0xff00000000ff0000, 0xe700000000600000, 0xfff00000000, // VECTOR MERGE LOW (VMRL V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMN, 0xff00000000ff0000, 0xe700000000fe0000, 0xfff00000000, // VECTOR MINIMUM (VMN V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMNL, 0xff00000000ff0000, 0xe700000000fc0000, 0xfff00000000, // VECTOR MINIMUM LOGICAL (VMNL V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMAE, 0xff00000000ff0000, 0xe700000000ae0000, 0xff00000000, // VECTOR MULTIPLY AND ADD EVEN (VMAE V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VMAH, 0xff00000000ff0000, 0xe700000000ab0000, 0xff00000000, // VECTOR MULTIPLY AND ADD HIGH (VMAH V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VMALE, 0xff00000000ff0000, 0xe700000000ac0000, 0xff00000000, // VECTOR MULTIPLY AND ADD LOGICAL EVEN (VMALE V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VMALH, 0xff00000000ff0000, 0xe700000000a90000, 0xff00000000, // VECTOR MULTIPLY AND ADD LOGICAL HIGH (VMALH V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VMALO, 0xff00000000ff0000, 0xe700000000ad0000, 0xff00000000, // VECTOR MULTIPLY AND ADD LOGICAL ODD (VMALO V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VMAL, 0xff00000000ff0000, 0xe700000000aa0000, 0xff00000000, // VECTOR MULTIPLY AND ADD LOW (VMAL V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VMAO, 0xff00000000ff0000, 0xe700000000af0000, 0xff00000000, // VECTOR MULTIPLY AND ADD ODD (VMAO V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VMSP, 0xff00000000ff0000, 0xe600000000790000, 0xf0000000000, // VECTOR MULTIPLY AND SHIFT DECIMAL (VMSP V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VMP, 0xff00000000ff0000, 0xe600000000780000, 0xf0000000000, // VECTOR MULTIPLY DECIMAL (VMP V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VME, 0xff00000000ff0000, 0xe700000000a60000, 0xfff00000000, // VECTOR MULTIPLY EVEN (VME V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMH, 0xff00000000ff0000, 0xe700000000a30000, 0xfff00000000, // VECTOR MULTIPLY HIGH (VMH V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMLE, 0xff00000000ff0000, 0xe700000000a40000, 0xfff00000000, // VECTOR MULTIPLY LOGICAL EVEN (VMLE V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMLH, 0xff00000000ff0000, 0xe700000000a10000, 0xfff00000000, // VECTOR MULTIPLY LOGICAL HIGH (VMLH V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMLO, 0xff00000000ff0000, 0xe700000000a50000, 0xfff00000000, // VECTOR MULTIPLY LOGICAL ODD (VMLO V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VML, 0xff00000000ff0000, 0xe700000000a20000, 0xfff00000000, // VECTOR MULTIPLY LOW (VML V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMO, 0xff00000000ff0000, 0xe700000000a70000, 0xfff00000000, // VECTOR MULTIPLY ODD (VMO V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VMSL, 0xff00000000ff0000, 0xe700000000b80000, 0xf00000000, // VECTOR MULTIPLY SUM LOGICAL (VMSL V1,V2,V3,V4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VNN, 0xff00000000ff0000, 0xe7000000006e0000, 0xffff0000000, // VECTOR NAND (VNN V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VNO, 0xff00000000ff0000, 0xe7000000006b0000, 0xffff0000000, // VECTOR NOR (VNO V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VNX, 0xff00000000ff0000, 0xe7000000006c0000, 0xffff0000000, // VECTOR NOT EXCLUSIVE OR (VNX V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VO, 0xff00000000ff0000, 0xe7000000006a0000, 0xffff0000000, // VECTOR OR (VO V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VOC, 0xff00000000ff0000, 0xe7000000006f0000, 0xffff0000000, // VECTOR OR WITH COMPLEMENT (VOC V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VPK, 0xff00000000ff0000, 0xe700000000940000, 0xfff00000000, // VECTOR PACK (VPK V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VPKLS, 0xff00000000ff0000, 0xe700000000950000, 0xf0f00000000, // VECTOR PACK LOGICAL SATURATE (VPKLS V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VPKS, 0xff00000000ff0000, 0xe700000000970000, 0xf0f00000000, // VECTOR PACK SATURATE (VPKS V1,V2,V3,M4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VPKZ, 0xff00000000ff0000, 0xe600000000340000, 0x0, // VECTOR PACK ZONED (VPKZ V1,D2(B2),I3) + [8]*argField{ap_VecReg_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15, ap_ImmUnsigned_36_39}}, + {VPKZR, 0xff00000000ff0000, 0xe600000000700000, 0xf0000000000, // VECTOR PACK ZONED REGISTER (VPKZR V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VPSOP, 0xff00000000ff0000, 0xe6000000005b0000, 0x0, // VECTOR PERFORM SIGN OPERATION DECIMAL (VPSOP V1,V2,I3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_28_35, ap_ImmUnsigned_16_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VPERM, 0xff00000000ff0000, 0xe7000000008c0000, 0xfff00000000, // VECTOR PERMUTE (VPERM V1,V2,V3,V4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_ImmUnsigned_36_39}}, + {VPDI, 0xff00000000ff0000, 0xe700000000840000, 0xfff00000000, // VECTOR PERMUTE DOUBLEWORD IMMEDIATE (VPDI V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VPOPCT, 0xff00000000ff0000, 0xe700000000500000, 0xffff00000000, // VECTOR POPULATION COUNT (VPOPCT V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VRP, 0xff00000000ff0000, 0xe6000000007b0000, 0xf0000000000, // VECTOR REMAINDER DECIMAL (VRP V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VREP, 0xff00000000ff0000, 0xe7000000004d0000, 0x0, // VECTOR REPLICATE (VREP V1,V3,I2,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VREPI, 0xff00000000ff0000, 0xe700000000450000, 0xf000000000000, // VECTOR REPLICATE IMMEDIATE (VREPI V1,I2,M3) + [8]*argField{ap_VecReg_8_11, ap_ImmUnsigned_16_31, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSCEF, 0xff00000000ff0000, 0xe7000000001b0000, 0x0, // VECTOR SCATTER ELEMENT (32) (VSCEF V1,D2(V2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_VecReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSCEG, 0xff00000000ff0000, 0xe7000000001a0000, 0x0, // VECTOR SCATTER ELEMENT (64) (VSCEG V1,D2(V2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_VecReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSEL, 0xff00000000ff0000, 0xe7000000008d0000, 0xfff00000000, // VECTOR SELECT (VSEL V1,V2,V3,V4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_ImmUnsigned_36_39}}, + {VSDP, 0xff00000000ff0000, 0xe6000000007e0000, 0xf0000000000, // VECTOR SHIFT AND DIVIDE DECIMAL (VSDP V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VSRP, 0xff00000000ff0000, 0xe600000000590000, 0x0, // VECTOR SHIFT AND ROUND DECIMAL (VSRP V1,V2,I3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_28_35, ap_ImmUnsigned_16_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VSRPR, 0xff00000000ff0000, 0xe600000000720000, 0xf0000000000, // VECTOR SHIFT AND ROUND DECIMAL REGISTER (VSRPR V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VSL, 0xff00000000ff0000, 0xe700000000740000, 0xffff0000000, // VECTOR SHIFT LEFT (VSL V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VSLB, 0xff00000000ff0000, 0xe700000000750000, 0xffff0000000, // VECTOR SHIFT LEFT BY BYTE (VSLB V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VSLD, 0xff00000000ff0000, 0xe700000000860000, 0xf00f0000000, // VECTOR SHIFT LEFT DOUBLE BY BIT (VSLD V1,V2,V3,I4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_24_31, ap_ImmUnsigned_36_39}}, + {VSLDB, 0xff00000000ff0000, 0xe700000000770000, 0xf00f0000000, // VECTOR SHIFT LEFT DOUBLE BY BYTE (VSLDB V1,V2,V3,I4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_24_31, ap_ImmUnsigned_36_39}}, + {VSRA, 0xff00000000ff0000, 0xe7000000007e0000, 0xffff0000000, // VECTOR SHIFT RIGHT ARITHMETIC (VSRA V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VSRAB, 0xff00000000ff0000, 0xe7000000007f0000, 0xffff0000000, // VECTOR SHIFT RIGHT ARITHMETIC BY BYTE (VSRAB V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VSRD, 0xff00000000ff0000, 0xe700000000870000, 0xf00f0000000, // VECTOR SHIFT RIGHT DOUBLE BY BIT (VSRD V1,V2,V3,I4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_24_31, ap_ImmUnsigned_36_39}}, + {VSRL, 0xff00000000ff0000, 0xe7000000007c0000, 0xffff0000000, // VECTOR SHIFT RIGHT LOGICAL (VSRL V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VSRLB, 0xff00000000ff0000, 0xe7000000007d0000, 0xffff0000000, // VECTOR SHIFT RIGHT LOGICAL BY BYTE (VSRLB V1,V2,V3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_36_39}}, + {VSEG, 0xff00000000ff0000, 0xe7000000005f0000, 0xffff00000000, // VECTOR SIGN EXTEND TO DOUBLEWORD (VSEG V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VST, 0xff00000000ff0000, 0xe7000000000e0000, 0x0, // VECTOR STORE (VST V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTEBRH, 0xff00000000ff0000, 0xe600000000090000, 0x0, // VECTOR STORE BYTE REVERSED ELEMENT(16) (VSTEBRH V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTEBRF, 0xff00000000ff0000, 0xe6000000000b0000, 0x0, // VECTOR STORE BYTE REVERSED ELEMENT(32) (VSTEBRF V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTEBRG, 0xff00000000ff0000, 0xe6000000000a0000, 0x0, // VECTOR STORE BYTE REVERSED ELEMENT(64) (VSTEBRG V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTBR, 0xff00000000ff0000, 0xe6000000000e0000, 0x0, // VECTOR STORE BYTE REVERSED ELEMENTS (VSTBR V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTEH, 0xff00000000ff0000, 0xe700000000090000, 0x0, // VECTOR STORE ELEMENT (16) (VSTEH V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTEF, 0xff00000000ff0000, 0xe7000000000b0000, 0x0, // VECTOR STORE ELEMENT (32) (VSTEF V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTEG, 0xff00000000ff0000, 0xe7000000000a0000, 0x0, // VECTOR STORE ELEMENT (64) (VSTEG V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTEB, 0xff00000000ff0000, 0xe700000000080000, 0x0, // VECTOR STORE ELEMENT (8) (VSTEB V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTER, 0xff00000000ff0000, 0xe6000000000f0000, 0x0, // VECTOR STORE ELEMENTS REVERSED (VSTER V1,D2(X2,B2),M3) + [8]*argField{ap_VecReg_8_11, ap_DispUnsigned_20_31, ap_IndexReg_12_15, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTM, 0xff00000000ff0000, 0xe7000000003e0000, 0x0, // VECTOR STORE MULTIPLE (VSTM V1,V3,D2(B2),M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSTRL, 0xff00000000ff0000, 0xe6000000003d0000, 0x0, // VECTOR STORE RIGHTMOST WITH LENGTH (VSTRL V1,D2(B2),I3) + [8]*argField{ap_VecReg_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15, ap_ImmUnsigned_36_39}}, + {VSTRLR, 0xff00000000ff0000, 0xe6000000003f0000, 0xf0000000000000, // VECTOR STORE RIGHTMOST WITH LENGTH (VSTRLR V1,R3,D2(B2)) + [8]*argField{ap_VecReg_32_35, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_36_39}}, + {VSTL, 0xff00000000ff0000, 0xe7000000003f0000, 0xf0000000, // VECTOR STORE WITH LENGTH (VSTL V1,R3,D2(B2)) + [8]*argField{ap_VecReg_8_11, ap_Reg_12_15, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_36_39}}, + {VSTRC, 0xff00000000ff0000, 0xe7000000008a0000, 0xf00000000, // VECTOR STRING RANGE COMPARE (VSTRC V1,V2,V3,V4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VSTRS, 0xff00000000ff0000, 0xe7000000008b0000, 0xf00000000, // VECTOR STRING SEARCH (VSTRS V1,V2,V3,V4,M5,M6) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VS, 0xff00000000ff0000, 0xe700000000f70000, 0xfff00000000, // VECTOR SUBTRACT (VS V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSCBI, 0xff00000000ff0000, 0xe700000000f50000, 0xfff00000000, // VECTOR SUBTRACT COMPUTE BORROW INDICATION (VSCBI V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSP, 0xff00000000ff0000, 0xe600000000730000, 0xf0000000000, // VECTOR SUBTRACT DECIMAL (VSP V1,V2,V3,I4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_ImmUnsigned_28_35, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VSBCBI, 0xff00000000ff0000, 0xe700000000bd0000, 0xff00000000, // VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION (VSBCBI V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VSBI, 0xff00000000ff0000, 0xe700000000bf0000, 0xff00000000, // VECTOR SUBTRACT WITH BORROW INDICATION (VSBI V1,V2,V3,V4,M5) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_VecReg_32_35, ap_Mask_20_23, ap_ImmUnsigned_36_39}}, + {VSUMG, 0xff00000000ff0000, 0xe700000000650000, 0xfff00000000, // VECTOR SUM ACROSS DOUBLEWORD (VSUMG V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSUMQ, 0xff00000000ff0000, 0xe700000000670000, 0xfff00000000, // VECTOR SUM ACROSS QUADWORD (VSUMQ V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VSUM, 0xff00000000ff0000, 0xe700000000640000, 0xfff00000000, // VECTOR SUM ACROSS WORD (VSUM V1,V2,V3,M4) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_VecReg_16_19, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VTP, 0xff00000000ff0000, 0xe6000000005f0000, 0xf0fffff0000000, // VECTOR TEST DECIMAL (VTP V1) + [8]*argField{ap_VecReg_12_15, ap_ImmUnsigned_36_39}}, + {VTM, 0xff00000000ff0000, 0xe700000000d80000, 0xfffff0000000, // VECTOR TEST UNDER MASK (VTM V1,V2) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_ImmUnsigned_36_39}}, + {VUPH, 0xff00000000ff0000, 0xe700000000d70000, 0xffff00000000, // VECTOR UNPACK HIGH (VUPH V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VUPLH, 0xff00000000ff0000, 0xe700000000d50000, 0xffff00000000, // VECTOR UNPACK LOGICAL HIGH (VUPLH V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VUPLL, 0xff00000000ff0000, 0xe700000000d40000, 0xffff00000000, // VECTOR UNPACK LOGICAL LOW (VUPLL V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VUPL, 0xff00000000ff0000, 0xe700000000d60000, 0xffff00000000, // VECTOR UNPACK LOW (VUPL V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_32_35, ap_ImmUnsigned_36_39}}, + {VUPKZ, 0xff00000000ff0000, 0xe6000000003c0000, 0x0, // VECTOR UNPACK ZONED (VUPKZ V1,D2(B2),I3) + [8]*argField{ap_VecReg_32_35, ap_DispUnsigned_20_31, ap_BaseReg_16_19, ap_ImmUnsigned_8_15, ap_ImmUnsigned_36_39}}, + {VUPKZH, 0xff00000000ff0000, 0xe600000000540000, 0xff0ff0000000, // VECTOR UNPACK ZONED HIGH (VUPKZH V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {VUPKZL, 0xff00000000ff0000, 0xe6000000005c0000, 0xff0ff0000000, // VECTOR UNPACK ZONED LOW (VUPKZL V1,V2,M3) + [8]*argField{ap_VecReg_8_11, ap_VecReg_12_15, ap_Mask_24_27, ap_ImmUnsigned_36_39}}, + {ZAP, 0xff00000000000000, 0xf800000000000000, 0x0, // ZERO AND ADD (ZAP D1(L1,B1),D2(L2,B2)) + [8]*argField{ap_DispUnsigned_20_31, ap_Len_8_11, ap_BaseReg_16_19, ap_DispUnsigned_36_47, ap_Len_12_15, ap_BaseReg_32_35}}, +} diff --git a/s390x/s390xasm/testdata/decode.txt b/s390x/s390xasm/testdata/decode.txt new file mode 100644 index 00000000..29a5e699 --- /dev/null +++ b/s390x/s390xasm/testdata/decode.txt @@ -0,0 +1,170 @@ + b9040021| plan9 MOVD R1, R2 + b9140043| plan9 MOVW R3, R4 + b9070065| plan9 MOVH R5, R6 + b9060087| plan9 MOVB R7, R8 + b9160021| plan9 MOVWZ R1, R2 + b9850032| plan9 MOVHZ R2, R3 + b9840054| plan9 MOVBZ R4, R5 + b90f0021| plan9 MOVDBR R1, R2 + b91f0043| plan9 MOVWBR R3, R4 + b9e28010| plan9 MOVDEQ R0, R1 + b9e2a032| plan9 MOVDGE R2, R3 + b9e22054| plan9 MOVDGT R4, R5 + b9e2c076| plan9 MOVDLE R6, R7 + b9e24098| plan9 MOVDLT R8, R9 + b9e270ba| plan9 MOVDNE R10, R11 + b9f23012| plan9 LOCR $3, R2, R1 + b3130020| plan9 LCDBR F0, F2 + b9e27065| plan9 MOVDNE R5, R6 +e310f0000004| plan9 MOVD (R15), R1 +e320f0000014| plan9 MOVW (R15), R2 +e330f0000015| plan9 MOVH (R15), R3 +e340f0000077| plan9 MOVB (R15), R4 +e350f0000016| plan9 MOVWZ (R15), R5 +e360f0000091| plan9 MOVHZ (R15), R6 +e370f0000090| plan9 MOVBZ (R15), R7 +e380f000000f| plan9 MOVDBR (R15), R8 +e390f000001e| plan9 MOVWBR (R15), R9 +e310fff8ff24| plan9 MOVD R1, -8(R15) +e320fff8ff50| plan9 MOVW R2, -8(R15) +e330fff8ff70| plan9 MOVH R3, -8(R15) +e340fff8ff72| plan9 MOVB R4, -8(R15) +e350fff8ff2f| plan9 MOVDBR R5, -8(R15) +e360fff8ff3e| plan9 MOVWBR R6, -8(R15) +c01efffffffe| plan9 MOVD $-8589934592, R1 +c021fffe0000| plan9 MOVW $-131072, R2 + a739fe00| plan9 MOVH $-512, R3 + a749ffff| plan9 MOVB $-1, R4 + b9e81022| plan9 ADD R1, R2 + b9e81032| plan9 ADD R1, R2, R3 + a71b2000| plan9 ADD $8192, R1 +ec21200000d9| plan9 ADD $8192, R1, R2 +c21800008000| plan9 ADD $32768, R1 + b9ea1022| plan9 ADDC R1, R2 + b9ea1032| plan9 ADDC R1, R2, R3 +ec21000100db| plan9 ADDC $1, R1, R2 +ec21ffff00db| plan9 SUBC $1, R1, R2 + 1a21| plan9 ADDW R1, R2 + b9f81032| plan9 ADDW R1, R2, R3 + a71a2000| plan9 ADDW $8192, R1 +ec21200000d8| plan9 ADDW $8192, R1, R2 + b9880021| plan9 ADDE R1, R2 +e3201000000a| plan9 ADDC (R1), R2 + 5a605000| plan9 ADDW (R5), R6 + 5a807fff| plan9 ADDW 4095(R7), R8 +e3201fffff5a| plan9 ADDW -1(R1), R2 +e34030000188| plan9 ADDE 4096(R3), R4 +e34230000188| plan9 ADDE 4096(R3)(R2*1), R4 + b9090043| plan9 SUB R3, R4 + b9e93054| plan9 SUB R3, R4, R5 + a73be000| plan9 SUB $8192, R3 +ec43e00000d9| plan9 SUB $8192, R3, R4 + b90b0021| plan9 SUBC R1, R2 +ec43ffff00db| plan9 SUBC $1, R3, R4 + b9eb2043| plan9 SUBC R2, R3, R4 + 1b43| plan9 SUBW R3, R4 + b9f93054| plan9 SUBW R3, R4, R5 +c21500002000| plan9 SUBW $8192, R1 +e320400f0089| plan9 SUBE 15(R4), R2 +e32040080009| plan9 SUB 8(R4), R2 + 5b204000| plan9 SUBW (R4), R2 +e3204fffff5b| plan9 SUBW -1(R4), R2 + b91c0076| plan9 MULLW R6, R7 + a76c2000| plan9 MULLW $8192, R6 +c2810000000f| plan9 MULLW $15, R8 +c281ffff7fff| plan9 MULLW $-32769, R8 +c21080000000| plan9 MULLD $-2147483648, R1 + b9860021| plan9 MLGR R1, R2 + b9030011| plan9 NEG R1 + b9030021| plan9 NEG R1, R2 + b9130011| plan9 NEGW R1 + b9130021| plan9 NEGW R1, R2 + b9830022| plan9 FLOGR R2, R2 + b9800021| plan9 AND R1, R2 + b9e42031| plan9 AND R1, R2, R3 + a517ffff| plan9 ANDW $-1, R1 +c01bffff0000| plan9 AND $-65536, R1 + 1421| plan9 ANDW R1, R2 + b9f42031| plan9 ANDW R1, R2, R3 +c01b00000001| plan9 ANDW $1, R1 + a5160001| plan9 ANDW $131071, R1 +c01b00010000| plan9 ANDW $65536, R1 + a517fffe| plan9 ANDW $-2, R1 + a517000f| plan9 AND $15, R1 +e32010000080| plan9 AND (R1), R2 + 54201000| plan9 ANDW (R1), R2 +e32010000154| plan9 ANDW 4096(R1), R2 + b9810021| plan9 OR R1, R2 + b9e62031| plan9 OR R1, R2, R3 + a51a0001| plan9 ORW $65536, R1 + a51bffff| plan9 ORW $-1, R1 + a51b0001| plan9 ORW $1, R1 + 1621| plan9 ORW R1, R2 +c01d0001ffff| plan9 OR $131071, R1 +c01dffffffff| plan9 ORW $-1, R1 + b9f62031| plan9 ORW R1, R2, R3 +e32010000081| plan9 OR (R1), R2 + 56201000| plan9 ORW (R1), R2 +e3201fffff56| plan9 ORW -1(R1), R2 + b9820021| plan9 XOR R1, R2 + b9e72031| plan9 XOR R1, R2, R3 +c01700000001| plan9 XOR $1, R1 +c0170001ffff| plan9 XOR $131071, R1 +c01700010000| plan9 XOR $65536, R1 + 1721| plan9 XORW R1, R2 + b9f72031| plan9 XORW R1, R2, R3 +c017fffffffe| plan9 XORW $-2, R1 + 0700| plan9 NOPH + 07e0| plan9 SYNC + b92e0024| plan9 KM R2, R4 + b92f0026| plan9 KMC R2, R6 + b93f0028| plan9 KLMD R2, R8 + b93e0004| plan9 KIMD R0, R4 + b93a0008| plan9 KDSA R0, R8 + b9296024| plan9 KMA R2, R6, R4 + b92d6024| plan9 KMCTR R2, R6, R4 + b31e0042| plan9 FMADD F4, F2, F0 +e748a00830e7| plan9 WFMDB V8, V10, V4 +e743000830e2| plan9 WFSDB V0, V3, V4 + b3cd0026| plan9 LGDR F6, R2 + a7f4008c| plan9 BR 70(PC) + a7140005| plan9 BVS 2(PC) + 07fe| plan9 RET +e743400000f3| plan9 VAB V3, V4 +e743600000f3| plan9 VAB V3, V6, V4 +e743400010f3| plan9 VAH V3, V4 +e743600010f3| plan9 VAH V3, V6, V4 +e743400020f3| plan9 VAF V3, V4 +e743600020f3| plan9 VAF V3, V6, V4 +e743400030f3| plan9 VAG V3, V4 +e743600030f3| plan9 VAG V3, V6, V4 +e743400040f3| plan9 VAQ V3, V4 +e743600040f3| plan9 VAQ V3, V6, V4 +e734600000f7| plan9 VSB V6, V4, V3 +e722100000f7| plan9 VSB V1, V2 +e734600010f7| plan9 VSH V6, V4, V3 +e722100010f7| plan9 VSH V1, V2 +e734600020f7| plan9 VSF V6, V4, V3 +e722100020f7| plan9 VSF V1, V2 +e734600030f7| plan9 VSG V6, V4, V3 +e722100030f7| plan9 VSG V1, V2 +e734600040f7| plan9 VSQ V6, V4, V3 +e722100040f7| plan9 VSQ V1, V2 +e7824000608a| plan9 VSTRCB V2, V4, V6, V8 +e7824100608a| plan9 VSTRCH V2, V4, V6, V8 +e7824200608a| plan9 VSTRCF V2, V4, V6, V8 +e7824010608a| plan9 VSTRCBS V2, V4, V6, V8 +e7824110608a| plan9 VSTRCHS V2, V4, V6, V8 +e7824210608a| plan9 VSTRCFS V2, V4, V6, V8 +e710ffff0044| plan9 VONE V1 +e70000000844| plan9 VZERO V16 +e70210000068| plan9 VN V2, V1, V0 +e71010000468| plan9 VN V16, V1 +e70210000069| plan9 VNC V2, V1, V0 +e71010000469| plan9 VNC V16, V1 +e7021000006a| plan9 VO V2, V1, V0 +e7101000046a| plan9 VO V16, V1 +e7021000006d| plan9 VX V2, V1, V0 +e7101000046d| plan9 VX V16, V1 +e7101000046b| plan9 VNOT V16, V1 +e78340000062| plan9 VLVGP R3, R4, V8 diff --git a/s390x/s390xasm/testdata/decode_generated.txt b/s390x/s390xasm/testdata/decode_generated.txt new file mode 100644 index 00000000..738a76e0 --- /dev/null +++ b/s390x/s390xasm/testdata/decode_generated.txt @@ -0,0 +1,1245 @@ + 5a82100b| gnu a %r8,11(%r2,%r1) + 1a80| gnu ar %r8,%r0 + b9f80080| gnu ark %r8,%r0,%r0 +e382100b005a| gnu ay %r8,11(%r2,%r1) +e382100b0008| gnu ag %r8,11(%r2,%r1) + b9080080| gnu agr %r8,%r0 + b9e80080| gnu agrk %r8,%r0,%r0 +e382100b0018| gnu agf %r8,11(%r2,%r1) + b9180080| gnu agfr %r8,%r0 + b34a0080| gnu axbr %f8,%f0 + b3da0080| gnu axtr %f8,%f0,%f0 + b3da0180| gnu axtra %f8,%f0,%f0,1 +ed82100b001a| gnu adb %f8,11(%r2,%r1) + b31a0080| gnu adbr %f8,%f0 + b3d20080| gnu adtr %f8,%f0,%f0 + b3d20180| gnu adtra %f8,%f0,%f0,1 +ed82100b000a| gnu aeb %f8,11(%r2,%r1) + b30a0080| gnu aebr %f8,%f0 +fa332006100b| gnu ap 6(4,%r2),11(4,%r1) + 4a82100b| gnu ah %r8,11(%r2,%r1) +e382100b007a| gnu ahy %r8,11(%r2,%r1) +e382100b0038| gnu agh %r8,11(%r2,%r1) + a78a0008| gnu ahi %r8,8 + a78b0008| gnu aghi %r8,8 + b9c80080| gnu ahhhr %r8,%r0,%r0 + b9d80080| gnu ahhlr %r8,%r0,%r0 +c28900000008| gnu afi %r8,8 +ec80000800d8| gnu ahik %r8,%r0,8 +eb082006006a| gnu asi 6(%r2),8 +ec80000800d9| gnu aghik %r8,%r0,8 +c28800000008| gnu agfi %r8,8 +eb082006007a| gnu agsi 6(%r2),8 +cc8800000008| gnu aih %r8,8 + 5e82100b| gnu al %r8,11(%r2,%r1) + 1e80| gnu alr %r8,%r0 + b9fa0080| gnu alrk %r8,%r0,%r0 +e382100b005e| gnu aly %r8,11(%r2,%r1) +e382100b000a| gnu alg %r8,11(%r2,%r1) + b90a0080| gnu algr %r8,%r0 + b9ea0080| gnu algrk %r8,%r0,%r0 +e382100b001a| gnu algf %r8,11(%r2,%r1) + b91a0080| gnu algfr %r8,%r0 + b9ca0080| gnu alhhhr %r8,%r0,%r0 + b9da0080| gnu alhhlr %r8,%r0,%r0 +c28b00000008| gnu alfi %r8,8 +c28a00000008| gnu algfi %r8,8 +e382100b0098| gnu alc %r8,11(%r2,%r1) + b9980080| gnu alcr %r8,%r0 +e382100b0088| gnu alcg %r8,11(%r2,%r1) + b9880080| gnu alcgr %r8,%r0 +ec80000800da| gnu alhsik %r8,%r0,8 +eb082006006e| gnu alsi 6(%r2),8 +ec80000800db| gnu alghsik %r8,%r0,8 +eb082006007e| gnu algsi 6(%r2),8 +cc8a00000008| gnu alsih %r8,8 +cc8b00000008| gnu alsihn %r8,8 + 3680| gnu axr %f8,%f0 + 6a82100b| gnu ad %f8,11(%r2,%r1) + 2a80| gnu adr %f8,%f0 + 7a82100b| gnu ae %f8,11(%r2,%r1) + 3a80| gnu aer %f8,%f0 + 6e82100b| gnu aw %f8,11(%r2,%r1) + 2e80| gnu awr %f8,%f0 + 7e82100b| gnu au %f8,11(%r2,%r1) + 3e80| gnu aur %f8,%f0 + 5482100b| gnu n %r8,11(%r2,%r1) + 1480| gnu nr %r8,%r0 + b9f40080| gnu nrk %r8,%r0,%r0 +e382100b0054| gnu ny %r8,11(%r2,%r1) +e382100b0080| gnu ng %r8,11(%r2,%r1) + b9800080| gnu ngr %r8,%r0 + b9e40080| gnu ngrk %r8,%r0,%r0 +d4032006100b| gnu nc 6(4,%r2),11(%r1) + 94ff2006| gnu ni 6(%r2),-1 +ebff20060054| gnu niy 6(%r2),-1 + a584fffe| gnu nihh %r8,-2 + a585fffe| gnu nihl %r8,-2 +c08afffffffe| gnu nihf %r8,-2 + a586fffe| gnu nilh %r8,-2 + a587fffe| gnu nill %r8,-2 +c08bfffffffe| gnu nilf %r8,-2 + b9f50080| gnu ncrk %r8,%r0,%r0 + b9e50080| gnu ncgrk %r8,%r0,%r0 + 4582100b| gnu bal %r8,11(%r2,%r1) + 0580| gnu balr %r8,%r0 + 4d82100b| gnu bas %r8,11(%r2,%r1) + 0d80| gnu basr %r8,%r0 + 0c80| gnu bassm %r8,%r0 + b25a0080| gnu bsa %r8,%r0 + 0b80| gnu bsm %r8,%r0 + b2400080| gnu bakr %r8,%r0 + b2580080| gnu bsg %r8,%r0 +e372100b0047| gnu bine 11(%r2,%r1) + 4772100b| gnu bne 11(%r2,%r1) + 0770| gnu bner %r0 + 4682100b| gnu bct %r8,11(%r2,%r1) + 0680| gnu bctr %r8,%r0 +e382100b0046| gnu bctg %r8,11(%r2,%r1) + b9460080| gnu bctgr %r8,%r0 + 8680100b| gnu bxh %r8,%r0,11(%r1) +eb80100b0044| gnu bxhg %r8,%r0,11(%r1) + 8780100b| gnu bxle %r8,%r0,11(%r1) +eb80100b0045| gnu bxleg %r8,%r0,11(%r1) +c77060b60000| gnu bpp 7,0x1cc,182(%r6) +c57000000093| gnu bprp 7,0x1d2,0x2f8 + a7850000| gnu bras %r8,0x1d8 +c08500000000| gnu brasl %r8,0x1dc + a7740000| gnu jne 0x1e2 +c07400000000| gnu jgne 0x1e6 + a7860000| gnu brct %r8,0x1ec + a7870000| gnu brctg %r8,0x1f0 +cc8600000000| gnu brcth %r8,0x1f4 + 84800000| gnu brxh %r8,%r0,0x1fa +ec8000000044| gnu brxhg %r8,%r0,0x1fe + 85800000| gnu brxle %r8,%r0,0x204 +ec8000000045| gnu brxlg %r8,%r0,0x208 + b2760000| gnu xsch + b2410080| gnu cksm %r8,%r0 + b92e0080| gnu km %r8,%r0 + b9290080| gnu kma %r8,%r0,%r0 + b92f0080| gnu kmc %r8,%r0 + b92a0080| gnu kmf %r8,%r0 + b92d0080| gnu kmctr %r8,%r0,%r0 + b92b0080| gnu kmo %r8,%r0 + b2300000| gnu csch + 5982100b| gnu c %r8,11(%r2,%r1) + 1980| gnu cr %r8,%r0 +e382100b0059| gnu cy %r8,11(%r2,%r1) +e382100b0020| gnu cg %r8,11(%r2,%r1) + b9200080| gnu cgr %r8,%r0 +e382100b0030| gnu cgf %r8,11(%r2,%r1) + b9300080| gnu cgfr %r8,%r0 + b3490080| gnu cxbr %f8,%f0 + b3ec0080| gnu cxtr %f8,%f0 + b3690080| gnu cxr %f8,%f0 +ed82100b0019| gnu cdb %f8,11(%r2,%r1) + b3190080| gnu cdbr %f8,%f0 + b3e40080| gnu cdtr %f8,%f0 + 6982100b| gnu cd %f8,11(%r2,%r1) + 2980| gnu cdr %f8,%f0 +ed82100b0009| gnu ceb %f8,11(%r2,%r1) + b3090080| gnu cebr %f8,%f0 + 7982100b| gnu ce %f8,11(%r2,%r1) + 3980| gnu cer %f8,%f0 +ec8080cd30f6| gnu crb %r8,%r0,3,205(%r8) +ec8080cd30e4| gnu cgrb %r8,%r0,3,205(%r8) +ec80ffac3076| gnu crj %r8,%r0,3,0x1e6 +ec80ffac3064| gnu cgrj %r8,%r0,3,0x1ec + b21a100b| gnu cfc 11(%r1) + b98f0180| gnu crdte %r8,%r0,%r0,1 + b3480080| gnu kxbr %f8,%f0 + b3e80080| gnu kxtr %f8,%f0 +ed82100b0018| gnu kdb %f8,11(%r2,%r1) + b3180080| gnu kdbr %f8,%f0 + b3e00080| gnu kdtr %f8,%f0 +ed82100b0008| gnu keb %f8,11(%r2,%r1) + b3080080| gnu kebr %f8,%f0 + ba80100b| gnu cs %r8,%r0,11(%r1) +eb80100b0014| gnu csy %r8,%r0,11(%r1) +eb80100b0030| gnu csg %r8,%r0,11(%r1) + b2500080| gnu csp %r8,%r0 + b98a0080| gnu cspg %r8,%r0 +c8022006100b| gnu csst 6(%r2),11(%r1),%r0 + b9723080| gnu crt %r8,%r0,3 + b9603080| gnu cgrt %r8,%r0,3 + b3fc0080| gnu cextr %f8,%f0 + b3f40080| gnu cedtr %f8,%f0 +f9332006100b| gnu cp 6(4,%r2),11(4,%r1) + bb80100b| gnu cds %r8,%r0,11(%r1) +eb80100b0031| gnu cdsy %r8,%r0,11(%r1) +eb80100b003e| gnu cdsg %r8,%r0,11(%r1) + 4982100b| gnu ch %r8,11(%r2,%r1) +e382100b0079| gnu chy %r8,11(%r2,%r1) +e382100b0034| gnu cgh %r8,11(%r2,%r1) +e55420060008| gnu chhsi 6(%r2),8 + a78e0008| gnu chi %r8,8 +e55c20060008| gnu chsi 6(%r2),8 + a78f0008| gnu cghi %r8,8 +e55820060008| gnu cghsi 6(%r2),8 +c68500000000| gnu chrl %r8,0x330 +c68400000000| gnu cghrl %r8,0x336 +e382100b00cd| gnu chf %r8,11(%r2,%r1) + b9cd0080| gnu chhr %r8,%r0 + b9dd0080| gnu chlr %r8,%r0 +c28d00000008| gnu cfi %r8,8 +c28c00000008| gnu cgfi %r8,8 +ec8380cd08fe| gnu cib %r8,8,3,205(%r8) +ec8380cd08fc| gnu cgib %r8,8,3,205(%r8) +ec83ffac087e| gnu cij %r8,8,3,0x2ba +ec83ffac087c| gnu cgij %r8,8,3,0x2c0 +ec8000083072| gnu cit %r8,8,3 +ec8000083070| gnu cgit %r8,8,3 +cc8d00000008| gnu cih %r8,8 + 5582100b| gnu cl %r8,11(%r2,%r1) + 1580| gnu clr %r8,%r0 +e382100b0055| gnu cly %r8,11(%r2,%r1) +e382100b0021| gnu clg %r8,11(%r2,%r1) + b9210080| gnu clgr %r8,%r0 +e382100b0031| gnu clgf %r8,11(%r2,%r1) + b9310080| gnu clgfr %r8,%r0 +d5032006100b| gnu clc 6(4,%r2),11(%r1) + 95082006| gnu cli 6(%r2),8 +eb0820060055| gnu cliy 6(%r2),8 +ec8080cd30f7| gnu clrb %r8,%r0,3,205(%r8) +ec8080cd30e5| gnu clgrb %r8,%r0,3,205(%r8) +ec80ffac3077| gnu clrj %r8,%r0,3,0x314 +ec80ffac3065| gnu clgrj %r8,%r0,3,0x31a + b9733080| gnu clrt %r8,%r0,3 +eb83100b0023| gnu clt %r8,3,11(%r1) + b9613080| gnu clgrt %r8,%r0,3 +eb83100b002b| gnu clgt %r8,3,11(%r1) +eb83100b0020| gnu clmh %r8,3,11(%r1) + bd83100b| gnu clm %r8,3,11(%r1) +eb83100b0021| gnu clmy %r8,3,11(%r1) +e382100b00cf| gnu clhf %r8,11(%r2,%r1) + b9cf0080| gnu clhhr %r8,%r0 + b9df0080| gnu clhlr %r8,%r0 +e55520060008| gnu clhhsi 6(%r2),8 +c28f00000008| gnu clfi %r8,8 +e55d20060008| gnu clfhsi 6(%r2),8 +e55920060008| gnu clghsi 6(%r2),8 +c28e00000008| gnu clgfi %r8,8 +ec8380cd08ff| gnu clib %r8,8,3,205(%r8) +ec8380cd08fd| gnu clgib %r8,8,3,205(%r8) +ec83ffac087f| gnu clij %r8,8,3,0x37c +ec83ffac087d| gnu clgij %r8,8,3,0x382 +ec8000083073| gnu clfit %r8,8,3 +ec8000083071| gnu clgit %r8,8,3 +cc8f00000008| gnu clih %r8,8 + 0f80| gnu clcl %r8,%r0 + a980100b| gnu clcle %r8,%r0,11(%r1) +eb80100b008f| gnu clclu %r8,%r0,11(%r1) +c68f00000000| gnu clrl %r8,0x44e +c68700000000| gnu clhrl %r8,0x454 +c68a00000000| gnu clgrl %r8,0x45a +c68600000000| gnu clghrl %r8,0x460 +c68e00000000| gnu clgfrl %r8,0x466 + b25d0080| gnu clst %r8,%r0 +c68d00000000| gnu crl %r8,0x470 +c68800000000| gnu cgrl %r8,0x476 +c68c00000000| gnu cgfrl %r8,0x47c + b2570080| gnu cuse %r8,%r0 + b2630080| gnu cmpsc %r8,%r0 + b93a0080| gnu kdsa %r8,%r0 + b93e0080| gnu kimd %r8,%r0 + b93f0080| gnu klmd %r8,%r0 + b91e0080| gnu kmac %r8,%r0 + b3590080| gnu thdr %f8,%f0 + b3580080| gnu thder %f8,%f0 + b3960080| gnu cxfbr %f8,%r0 + b3963180| gnu cxfbra %f8,3,%r0,1 + b9593180| gnu cxftr %f8,3,%r0,1 + b3b60080| gnu cxfr %f8,%r0 + b3950080| gnu cdfbr %f8,%r0 + b3953180| gnu cdfbra %f8,3,%r0,1 + b9513180| gnu cdftr %f8,3,%r0,1 + b3b50080| gnu cdfr %f8,%r0 + b3940080| gnu cefbr %f8,%r0 + b3943180| gnu cefbra %f8,3,%r0,1 + b3b40080| gnu cefr %f8,%r0 + b3a60080| gnu cxgbr %f8,%r0 + b3a63180| gnu cxgbra %f8,3,%r0,1 + b3f90080| gnu cxgtr %f8,%r0 + b3f93180| gnu cxgtra %f8,3,%r0,1 + b3c60080| gnu cxgr %f8,%r0 + b3a50080| gnu cdgbr %f8,%r0 + b3a53180| gnu cdgbra %f8,3,%r0,1 + b3f10080| gnu cdgtr %f8,%r0 + b3f13180| gnu cdgtra %f8,3,%r0,1 + b3c50080| gnu cdgr %f8,%r0 + b3a40080| gnu cegbr %f8,%r0 + b3a43180| gnu cegbra %f8,3,%r0,1 + b3c40080| gnu cegr %f8,%r0 + b3923180| gnu cxlfbr %f8,3,%r0,1 + b95b3180| gnu cxlftr %f8,3,%r0,1 + b3913180| gnu cdlfbr %f8,3,%r0,1 + b9533180| gnu cdlftr %f8,3,%r0,1 + b3903180| gnu celfbr %f8,3,%r0,1 + b3a23180| gnu cxlgbr %f8,3,%r0,1 + b95a3180| gnu cxlgtr %f8,3,%r0,1 + b3a13180| gnu cdlgbr %f8,3,%r0,1 + b9523180| gnu cdlgtr %f8,3,%r0,1 + b3a03180| gnu celgbr %f8,3,%r0,1 +ed03100b83af| gnu cxpt %f8,11(4,%r1),3 +ed03100b83ae| gnu cdpt %f8,11(4,%r1),3 + b3fb0080| gnu cxstr %f8,%r0 + b3f30080| gnu cdstr %f8,%r0 + b3fa0080| gnu cxutr %f8,%r0 + b3f20080| gnu cdutr %f8,%r0 +ed03100b83ab| gnu cxzt %f8,11(4,%r1),3 +ed03100b83aa| gnu cdzt %f8,11(4,%r1),3 + b3503080| gnu tbedr %f8,3,%f0 + b3513080| gnu tbdr %f8,3,%f0 + 4f82100b| gnu cvb %r8,11(%r2,%r1) +e382100b0006| gnu cvby %r8,11(%r2,%r1) +e382100b000e| gnu cvbg %r8,11(%r2,%r1) + 4e82100b| gnu cvd %r8,11(%r2,%r1) +e382100b0026| gnu cvdy %r8,11(%r2,%r1) +e382100b002e| gnu cvdg %r8,11(%r2,%r1) + b39a3080| gnu cfxbr %r8,3,%f0 + b39a3180| gnu cfxbra %r8,3,%f0,1 + b3aa3080| gnu cgxbr %r8,3,%f0 + b3aa3180| gnu cgxbra %r8,3,%f0,1 + b9493180| gnu cfxtr %r8,3,%f0,1 + b3e93080| gnu cgxtr %r8,3,%f0 + b3e93180| gnu cgxtra %r8,3,%f0,1 + b3ba3080| gnu cfxr %r8,3,%f0 + b3ca3080| gnu cgxr %r8,3,%f0 + b3993080| gnu cfdbr %r8,3,%f0 + b3993180| gnu cfdbra %r8,3,%f0,1 + b3a93080| gnu cgdbr %r8,3,%f0 + b3a93180| gnu cgdbra %r8,3,%f0,1 + b9413180| gnu cfdtr %r8,3,%f0,1 + b3e13080| gnu cgdtr %r8,3,%f0 + b3e13180| gnu cgdtra %r8,3,%f0,1 + b3b93080| gnu cfdr %r8,3,%f0 + b3c93080| gnu cgdr %r8,3,%f0 + b3983080| gnu cfebr %r8,3,%f0 + b3983180| gnu cfebra %r8,3,%f0,1 + b3a83080| gnu cgebr %r8,3,%f0 + b3a83180| gnu cgebra %r8,3,%f0,1 + b3b83080| gnu cfer %r8,3,%f0 + b3c83080| gnu cger %r8,3,%f0 + b39e3180| gnu clfxbr %r8,3,%f0,1 + b3ae3180| gnu clgxbr %r8,3,%f0,1 + b94b3180| gnu clfxtr %r8,3,%f0,1 + b94a3180| gnu clgxtr %r8,3,%f0,1 + b39d3180| gnu clfdbr %r8,3,%f0,1 + b3ad3180| gnu clgdbr %r8,3,%f0,1 + b9433180| gnu clfdtr %r8,3,%f0,1 + b9423180| gnu clgdtr %r8,3,%f0,1 + b39c3180| gnu clfebr %r8,3,%f0,1 + b3ac3180| gnu clgebr %r8,3,%f0,1 +ed03100b83ad| gnu cpxt %f8,11(4,%r1),3 +ed03100b83ac| gnu cpdt %f8,11(4,%r1),3 + b3eb0180| gnu csxtr %r8,%f0,1 + b3e30180| gnu csdtr %r8,%f0,1 + b3ea0080| gnu cuxtr %r8,%f0 + b3e20080| gnu cudtr %r8,%f0 +ed03100b83a9| gnu czxt %f8,11(4,%r1),3 +ed03100b83a8| gnu czdt %f8,11(4,%r1),3 + b2a63080| gnu cu21 %r8,%r0,3 + b9b13080| gnu cu24 %r8,%r0,3 + b2a63080| gnu cu21 %r8,%r0,3 + b2a73080| gnu cu12 %r8,%r0,3 + b2a73080| gnu cu12 %r8,%r0,3 + b9b03080| gnu cu14 %r8,%r0,3 + b9b30080| gnu cu42 %r8,%r0 + b9b20080| gnu cu41 %r8,%r0 + b24d0080| gnu cpya %a8,%a0 + b3720080| gnu cpsdr %f8,%f0,%f0 +e6235000087c| gnu vscshp %v18,%v3,%v5 +e62350901874| gnu vschp %v18,%v3,%v5,1,9 + b9390080| gnu dfltcc %r8,%r0,%r0 + 5d82100b| gnu d %r8,11(%r2,%r1) + 1d80| gnu dr %r8,%r0 + b34d0080| gnu dxbr %f8,%f0 + b3d90080| gnu dxtr %f8,%f0,%f0 + b3d90180| gnu dxtra %f8,%f0,%f0,1 + b22d0080| gnu dxr %f8,%f0 +ed82100b001d| gnu ddb %f8,11(%r2,%r1) + b31d0080| gnu ddbr %f8,%f0 + b3d10080| gnu ddtr %f8,%f0,%f0 + b3d10180| gnu ddtra %f8,%f0,%f0,1 + 6d82100b| gnu dd %f8,11(%r2,%r1) + 2d80| gnu ddr %f8,%f0 +ed82100b000d| gnu deb %f8,11(%r2,%r1) + b30d0080| gnu debr %f8,%f0 + 7d82100b| gnu de %f8,11(%r2,%r1) + 3d80| gnu der %f8,%f0 +fd332006100b| gnu dp 6(4,%r2),11(4,%r1) +e382100b0097| gnu dl %r8,11(%r2,%r1) + b9970080| gnu dlr %r8,%r0 +e382100b0087| gnu dlg %r8,11(%r2,%r1) + b9870080| gnu dlgr %r8,%r0 +e382100b000d| gnu dsg %r8,11(%r2,%r1) + b90d0080| gnu dsgr %r8,%r0 +e382100b001d| gnu dsgf %r8,11(%r2,%r1) + b91d0080| gnu dsgfr %r8,%r0 + b35b0180| gnu didbr %f8,%f0,%f0,1 + b3530180| gnu diebr %f8,%f0,%f0,1 +de032006100b| gnu ed 6(4,%r2),11(%r1) +df032006100b| gnu edmk 6(4,%r2),11(%r1) + 5782100b| gnu x %r8,11(%r2,%r1) + 1780| gnu xr %r8,%r0 + b9f70080| gnu xrk %r8,%r0,%r0 +e382100b0057| gnu xy %r8,11(%r2,%r1) +e382100b0082| gnu xg %r8,11(%r2,%r1) + b9820080| gnu xgr %r8,%r0 + b9e70080| gnu xgrk %r8,%r0,%r0 +d7032006100b| gnu xc 6(4,%r2),11(%r1) + 97ff2006| gnu xi 6(%r2),-1 +ebff20060057| gnu xiy 6(%r2),-1 +c086ffffffff| gnu xihf %r8,-1 +c087ffffffff| gnu xilf %r8,-1 + 4482100b| gnu ex %r8,11(%r2,%r1) +c68000000000| gnu exrl %r8,0x720 + b24f0080| gnu ear %r8,%a0 + b99d0080| gnu esea %r8 + b3ed0080| gnu eextr %r8,%f0 + b3e50080| gnu eedtr %r8,%f0 +eb80100b004c| gnu ecag %r8,%r0,11(%r1) +c8012006100b| gnu ectg 6(%r2),11(%r1),%r0 + b38c0080| gnu efpc %r8 + b2260080| gnu epar %r8 + b99a0080| gnu epair %r8 + b98d0080| gnu epsw %r8,%r0 + b2270080| gnu esar %r8 + b99b0080| gnu esair %r8 + b3ef0080| gnu esxtr %r8,%f0 + b3e70080| gnu esdtr %r8,%f0 + b2490080| gnu ereg %r8,%r0 + b90e0080| gnu eregg %r8,%r0 + b24a0080| gnu esta %r8,%r0 + b2ec0080| gnu etnd %r8 + b9830080| gnu flogr %r8,%r0 + b2310000| gnu hsch + 2480| gnu hdr %f8,%f0 + 3480| gnu her %f8,%f0 + b2240080| gnu iac %r8 + b3fe0080| gnu iextr %f8,%f0,%r0 + b3f60080| gnu iedtr %f8,%f0,%r0 + 4382100b| gnu ic %r8,11(%r2,%r1) +e382100b0073| gnu icy %r8,11(%r2,%r1) +eb83100b0080| gnu icmh %r8,3,11(%r1) + bf83100b| gnu icm %r8,3,11(%r1) +eb83100b0081| gnu icmy %r8,3,11(%r1) + a5800008| gnu iihh %r8,8 + a5810008| gnu iihl %r8,8 +c08800000008| gnu iihf %r8,8 + a5820008| gnu iilh %r8,8 + a5830008| gnu iill %r8,8 +c08900000008| gnu iilf %r8,8 + b2220080| gnu ipm %r8 + b20b0000| gnu ipk + b9ac0080| gnu irbm %r8,%r0 + b2290080| gnu iske %r8,%r0 + b2230080| gnu ivsk %r8,%r0 + b98e0180| gnu idte %r8,%r0,%r0,1 + b2210180| gnu ipte %r8,%r0,%r0,1 + 5882100b| gnu l %r8,11(%r2,%r1) + 1880| gnu lr %r8,%r0 +e382100b0058| gnu ly %r8,11(%r2,%r1) +e382100b0004| gnu lg %r8,11(%r2,%r1) + b9040080| gnu lgr %r8,%r0 +e382100b0014| gnu lgf %r8,11(%r2,%r1) + b9140080| gnu lgfr %r8,%r0 + b3650080| gnu lxr %f8,%f0 + 6882100b| gnu ld %f8,11(%r2,%r1) + 2880| gnu ldr %f8,%f0 +ed82100b0065| gnu ldy %f8,11(%r2,%r1) + 7882100b| gnu le %f8,11(%r2,%r1) + 3880| gnu ler %f8,%f0 +ed82100b0064| gnu ley %f8,11(%r2,%r1) + 9a80100b| gnu lam %a8,%a0,11(%r1) +eb80100b009a| gnu lamy %a8,%a0,11(%r1) + 4182100b| gnu la %r8,11(%r2,%r1) +e382100b0071| gnu lay %r8,11(%r2,%r1) + 5182100b| gnu lae %r8,11(%r2,%r1) +e382100b0075| gnu laey %r8,11(%r2,%r1) +c08000000000| gnu larl %r8,0x836 +e5002006100b| gnu lasp 6(%r2),11(%r1) +eb80100b00f8| gnu laa %r8,%r0,11(%r1) +eb80100b00e8| gnu laag %r8,%r0,11(%r1) +eb80100b00fa| gnu laal %r8,%r0,11(%r1) +eb80100b00ea| gnu laalg %r8,%r0,11(%r1) +eb80100b00f4| gnu lan %r8,%r0,11(%r1) +eb80100b00e4| gnu lang %r8,%r0,11(%r1) +eb80100b00f7| gnu lax %r8,%r0,11(%r1) +eb80100b00e7| gnu laxg %r8,%r0,11(%r1) +eb80100b00f6| gnu lao %r8,%r0,11(%r1) +eb80100b00e6| gnu laog %r8,%r0,11(%r1) +e382100b0012| gnu lt %r8,11(%r2,%r1) + 1280| gnu ltr %r8,%r0 +e382100b0002| gnu ltg %r8,11(%r2,%r1) + b9020080| gnu ltgr %r8,%r0 +e382100b0032| gnu ltgf %r8,11(%r2,%r1) + b9120080| gnu ltgfr %r8,%r0 + b3420080| gnu ltxbr %f8,%f0 + b3de0080| gnu ltxtr %f8,%f0 + b3620080| gnu ltxr %f8,%f0 + b3120080| gnu ltdbr %f8,%f0 + b3d60080| gnu ltdtr %f8,%f0 + 2280| gnu ltdr %f8,%f0 + b3020080| gnu ltebr %f8,%f0 + 3280| gnu lter %f8,%f0 +e382100b009f| gnu lat %r8,11(%r2,%r1) +e382100b0085| gnu lgat %r8,11(%r2,%r1) +e382100b003b| gnu lzrf %r8,11(%r2,%r1) +e382100b002a| gnu lzrg %r8,11(%r2,%r1) + b200100b| gnu lbear 11(%r1) +e382100b0076| gnu lb %r8,11(%r2,%r1) + b9260080| gnu lbr %r8,%r0 +e382100b0077| gnu lgb %r8,11(%r2,%r1) + b9060080| gnu lgbr %r8,%r0 +e382100b00c0| gnu lbh %r8,11(%r2,%r1) + 1380| gnu lcr %r8,%r0 + b9030080| gnu lcgr %r8,%r0 + b9130080| gnu lcgfr %r8,%r0 + b3430080| gnu lcxbr %f8,%f0 + b3630080| gnu lcxr %f8,%f0 + b3130080| gnu lcdbr %f8,%f0 + 2380| gnu lcdr %f8,%f0 + b3730080| gnu lcdfr %f8,%f0 + b3030080| gnu lcebr %f8,%f0 + 3380| gnu lcer %f8,%f0 + b780100b| gnu lctl %c8,%c0,11(%r1) +eb80100b002f| gnu lctlg %c8,%c0,11(%r1) +e782100b3027| gnu lcbb %r8,11(%r2,%r1),3 + b3473080| gnu fixbr %f8,3,%f0 + b3473180| gnu fixbra %f8,3,%f0,1 + b3df3180| gnu fixtr %f8,3,%f0,1 + b3670080| gnu fixr %f8,%f0 + b35f3080| gnu fidbr %f8,3,%f0 + b35f3180| gnu fidbra %f8,3,%f0,1 + b3d73180| gnu fidtr %f8,3,%f0,1 + b37f0080| gnu fidr %f8,%f0 + b3573080| gnu fiebr %f8,3,%f0 + b3573180| gnu fiebra %f8,3,%f0,1 + b3770080| gnu fier %f8,%f0 + b29d100b| gnu lfpc 11(%r1) + b2bd100b| gnu lfas 11(%r1) + b3c10080| gnu ldgr %f8,%r0 + b3cd0080| gnu lgdr %r8,%f0 +e382100b004c| gnu lgg %r8,11(%r2,%r1) +e382100b004d| gnu lgsc %r8,11(%r2,%r1) + 4882100b| gnu lh %r8,11(%r2,%r1) + b9270080| gnu lhr %r8,%r0 +e382100b0078| gnu lhy %r8,11(%r2,%r1) +e382100b0015| gnu lgh %r8,11(%r2,%r1) + b9070080| gnu lghr %r8,%r0 +e382100b00c4| gnu lhh %r8,11(%r2,%r1) +ec830008004e| gnu lochhinle %r8,8 + a7880008| gnu lhi %r8,8 + a7890008| gnu lghi %r8,8 +ec8300080042| gnu lochinle %r8,8 +ec8300080046| gnu locghinle %r8,8 +c48500000000| gnu lhrl %r8,0x99e +c48400000000| gnu lghrl %r8,0x9a4 +e382100b00ca| gnu lfh %r8,11(%r2,%r1) +e382100b00c8| gnu lfhat %r8,11(%r2,%r1) +eb83100b00e0| gnu locfhnle %r8,11(%r1) + b9e03080| gnu locfhrnle %r8,%r0 +c081fffffffe| gnu lgfi %r8,-2 +ed82100b0005| gnu lxdb %f8,11(%r2,%r1) + b3050080| gnu lxdbr %f8,%f0 + b3dc0180| gnu lxdtr %f8,%f0,1 +ed82100b0025| gnu lxd %f8,11(%r2,%r1) + b3250080| gnu lxdr %f8,%f0 +ed82100b0006| gnu lxeb %f8,11(%r2,%r1) + b3060080| gnu lxebr %f8,%f0 +ed82100b0026| gnu lxe %f8,11(%r2,%r1) + b3260080| gnu lxer %f8,%f0 +ed82100b0004| gnu ldeb %f8,11(%r2,%r1) + b3040080| gnu ldebr %f8,%f0 + b3d40180| gnu ldetr %f8,%f0,1 +ed82100b0024| gnu lde %f8,11(%r2,%r1) + b3240080| gnu lder %f8,%f0 +e382100b0016| gnu llgf %r8,11(%r2,%r1) + b9160080| gnu llgfr %r8,%r0 +e382100b0048| gnu llgfsg %r8,11(%r2,%r1) +e382100b009d| gnu llgfat %r8,11(%r2,%r1) +e382100b003a| gnu llzrgf %r8,11(%r2,%r1) +e382100b0094| gnu llc %r8,11(%r2,%r1) + b9940080| gnu llcr %r8,%r0 +e382100b0090| gnu llgc %r8,11(%r2,%r1) + b9840080| gnu llgcr %r8,%r0 +e382100b00c2| gnu llch %r8,11(%r2,%r1) +e382100b0095| gnu llh %r8,11(%r2,%r1) + b9950080| gnu llhr %r8,%r0 +e382100b0091| gnu llgh %r8,11(%r2,%r1) + b9850080| gnu llghr %r8,%r0 +e382100b00c6| gnu llhh %r8,11(%r2,%r1) +c48200000000| gnu llhrl %r8,0xa5a +c48600000000| gnu llghrl %r8,0xa60 + a58cffff| gnu llihh %r8,-1 + a58dffff| gnu llihl %r8,-1 +c08efffffffe| gnu llihf %r8,-2 + a58effff| gnu llilh %r8,-1 + a58fffff| gnu llill %r8,-1 +c08ffffffffe| gnu llilf %r8,-2 +c48e00000000| gnu llgfrl %r8,0xa82 +e382100b0017| gnu llgt %r8,11(%r2,%r1) + b9170080| gnu llgtr %r8,%r0 +e382100b009c| gnu llgtat %r8,11(%r2,%r1) + 9880100b| gnu lm %r8,%r0,11(%r1) +eb80100b0098| gnu lmy %r8,%r0,11(%r1) +eb80100b0004| gnu lmg %r8,%r0,11(%r1) +ef80100b80cd| gnu lmd %r8,%r0,11(%r1),205(%r8) +eb80100b0096| gnu lmh %r8,%r0,11(%r1) + 1180| gnu lnr %r8,%r0 + b9010080| gnu lngr %r8,%r0 + b9110080| gnu lngfr %r8,%r0 + b3410080| gnu lnxbr %f8,%f0 + b3610080| gnu lnxr %f8,%f0 + b3110080| gnu lndbr %f8,%f0 + 2180| gnu lndr %f8,%f0 + b3710080| gnu lndfr %f8,%f0 + b3010080| gnu lnebr %f8,%f0 + 3180| gnu lner %f8,%f0 +eb83100b00f2| gnu locnle %r8,11(%r1) + b9f23080| gnu locrnle %r8,%r0 +eb83100b00e2| gnu locgnle %r8,11(%r1) + b9e23080| gnu locgrnle %r8,%r0 + b9aa0180| gnu lptea %r8,%r0,%r0,1 +c8042006100b| gnu lpd %r0,6(%r2),11(%r1) +c8052006100b| gnu lpdg %r0,6(%r2),11(%r1) +e382100b008f| gnu lpq %r8,11(%r2,%r1) + 1080| gnu lpr %r8,%r0 + b9000080| gnu lpgr %r8,%r0 + b9100080| gnu lpgfr %r8,%r0 + b3400080| gnu lpxbr %f8,%f0 + b3600080| gnu lpxr %f8,%f0 + b3100080| gnu lpdbr %f8,%f0 + 2080| gnu lpdr %f8,%f0 + b3700080| gnu lpdfr %f8,%f0 + b3000080| gnu lpebr %f8,%f0 + 3080| gnu lper %f8,%f0 + 82002006| gnu lpsw 6(%r2) + b2b2100b| gnu lpswe 11(%r1) +eb0020060071| gnu lpswey 6(%r2) + b182100b| gnu lra %r8,11(%r2,%r1) +e382100b0013| gnu lray %r8,11(%r2,%r1) +e382100b0003| gnu lrag %r8,11(%r2,%r1) +c48d00000000| gnu lrl %r8,0xb40 +c48800000000| gnu lgrl %r8,0xb46 +c48c00000000| gnu lgfrl %r8,0xb4c +e382100b001f| gnu lrvh %r8,11(%r2,%r1) +e382100b001e| gnu lrv %r8,11(%r2,%r1) + b91f0080| gnu lrvr %r8,%r0 +e382100b000f| gnu lrvg %r8,11(%r2,%r1) + b90f0080| gnu lrvgr %r8,%r0 + b3450080| gnu ldxbr %f8,%f0 + b3453180| gnu ldxbra %f8,3,%f0,1 + b3dd3180| gnu ldxtr %f8,3,%f0,1 + 2580| gnu ldxr %f8,%f0 + 2580| gnu ldxr %f8,%f0 + b3460080| gnu lexbr %f8,%f0 + b3463180| gnu lexbra %f8,3,%f0,1 + b3660080| gnu lexr %f8,%f0 + b3440080| gnu ledbr %f8,%f0 + b3443180| gnu ledbra %f8,3,%f0,1 + b3d53180| gnu ledtr %f8,3,%f0,1 + 3580| gnu ledr %f8,%f0 + 3580| gnu ledr %f8,%f0 + b24b0080| gnu lura %r8,%r0 + b9050080| gnu lurag %r8,%r0 + b3760080| gnu lzxr %f8 + b3750080| gnu lzdr %f8 + b3740080| gnu lzer %f8 + b2470080| gnu msta %r8 + b232100b| gnu msch 11(%r1) + af082006| gnu mc 6(%r2),8 +e54420060008| gnu mvhhi 6(%r2),8 +e54c20060008| gnu mvhi 6(%r2),8 +e54820060008| gnu mvghi 6(%r2),8 +d2032006100b| gnu mvc 6(4,%r2),11(%r1) + 92082006| gnu mvi 6(%r2),8 +eb0820060052| gnu mviy 6(%r2),8 +e8032006100b| gnu mvcin 6(4,%r2),11(%r1) + 0e80| gnu mvcl %r8,%r0 + a880100b| gnu mvcle %r8,%r0,11(%r1) +eb80100b008e| gnu mvclu %r8,%r0,11(%r1) +d1032006100b| gnu mvn 6(4,%r2),11(%r1) + b2540080| gnu mvpg %r8,%r0 +e50a2006100b| gnu mvcrl 6(%r2),11(%r1) + b2550080| gnu mvst %r8,%r0 +da802006100b| gnu mvcp 6(%r8,%r2),11(%r1),%r0 +db802006100b| gnu mvcs 6(%r8,%r2),11(%r1),%r0 +e50f2006100b| gnu mvcdk 6(%r2),11(%r1) +d9802006100b| gnu mvck 6(%r8,%r2),11(%r1),%r0 +f1332006100b| gnu mvo 6(4,%r2),11(4,%r1) +c8002006100b| gnu mvcos 6(%r2),11(%r1),%r0 +e50e2006100b| gnu mvcsk 6(%r2),11(%r1) +d3032006100b| gnu mvz 6(4,%r2),11(%r1) +e382100b0084| gnu mg %r8,11(%r2,%r1) + b9ec0080| gnu mgrk %r8,%r0,%r0 + 5c82100b| gnu m %r8,11(%r2,%r1) +e382100b005c| gnu mfy %r8,11(%r2,%r1) + 1c80| gnu mr %r8,%r0 + b34c0080| gnu mxbr %f8,%f0 + b3d80080| gnu mxtr %f8,%f0,%f0 + b3d80180| gnu mxtra %f8,%f0,%f0,1 + 2680| gnu mxr %f8,%f0 +ed82100b001c| gnu mdb %f8,11(%r2,%r1) + b31c0080| gnu mdbr %f8,%f0 + b3d00080| gnu mdtr %f8,%f0,%f0 + b3d00180| gnu mdtra %f8,%f0,%f0,1 + 6c82100b| gnu md %f8,11(%r2,%r1) + 2c80| gnu mdr %f8,%f0 +ed82100b0007| gnu mxdb %f8,11(%r2,%r1) + b3070080| gnu mxdbr %f8,%f0 + 6782100b| gnu mxd %f8,11(%r2,%r1) + 2780| gnu mxdr %f8,%f0 +ed82100b0017| gnu meeb %f8,11(%r2,%r1) + b3170080| gnu meebr %f8,%f0 +ed82100b0037| gnu mee %f8,11(%r2,%r1) + b3370080| gnu meer %f8,%f0 +ed82100b000c| gnu mdeb %f8,11(%r2,%r1) + b30c0080| gnu mdebr %f8,%f0 + 7c82100b| gnu mde %f8,11(%r2,%r1) + 3c80| gnu mder %f8,%f0 + 7c82100b| gnu mde %f8,11(%r2,%r1) + 3c80| gnu mder %f8,%f0 +ed02100b803a| gnu may %f8,%f0,11(%r2,%r1) + b33a8000| gnu mayr %f8,%f0,%f0 +ed02100b801e| gnu madb %f8,%f0,11(%r2,%r1) + b31e8000| gnu madbr %f8,%f0,%f0 +ed02100b803e| gnu mad %f8,%f0,11(%r2,%r1) + b33e8000| gnu madr %f8,%f0,%f0 +ed02100b800e| gnu maeb %f8,%f0,11(%r2,%r1) + b30e8000| gnu maebr %f8,%f0,%f0 +ed02100b802e| gnu mae %f8,%f0,11(%r2,%r1) + b32e8000| gnu maer %f8,%f0,%f0 +ed02100b803c| gnu mayh %f8,%f0,11(%r2,%r1) + b33c8000| gnu mayhr %f8,%f0,%f0 +ed02100b8038| gnu mayl %f8,%f0,11(%r2,%r1) + b3388000| gnu maylr %f8,%f0,%f0 +ed02100b801f| gnu msdb %f8,%f0,11(%r2,%r1) + b31f8000| gnu msdbr %f8,%f0,%f0 +ed02100b803f| gnu msd %f8,%f0,11(%r2,%r1) + b33f8000| gnu msdr %f8,%f0,%f0 +ed02100b800f| gnu mseb %f8,%f0,11(%r2,%r1) + b30f8000| gnu msebr %f8,%f0,%f0 +ed02100b802f| gnu mse %f8,%f0,11(%r2,%r1) + b32f8000| gnu mser %f8,%f0,%f0 +fc332006100b| gnu mp 6(4,%r2),11(4,%r1) + 4c82100b| gnu mh %r8,11(%r2,%r1) +e382100b007c| gnu mhy %r8,11(%r2,%r1) +e382100b003c| gnu mgh %r8,11(%r2,%r1) + a78cfffd| gnu mhi %r8,-3 + a78dfffd| gnu mghi %r8,-3 +e382100b0086| gnu mlg %r8,11(%r2,%r1) + b9860080| gnu mlgr %r8,%r0 +e382100b0096| gnu ml %r8,11(%r2,%r1) + b9960080| gnu mlr %r8,%r0 + 7182100b| gnu ms %r8,11(%r2,%r1) +e382100b0053| gnu msc %r8,11(%r2,%r1) + b2520080| gnu msr %r8,%r0 + b9fd0080| gnu msrkc %r8,%r0,%r0 +e382100b0051| gnu msy %r8,11(%r2,%r1) +e382100b000c| gnu msg %r8,11(%r2,%r1) +e382100b0083| gnu msgc %r8,11(%r2,%r1) + b90c0080| gnu msgr %r8,%r0 + b9ed0080| gnu msgrkc %r8,%r0,%r0 +e382100b001c| gnu msgf %r8,11(%r2,%r1) + b91c0080| gnu msgfr %r8,%r0 +c281ffffffff| gnu msfi %r8,-1 +c280ffffffff| gnu msgfi %r8,-1 +ed02100b803d| gnu myh %f8,%f0,11(%r2,%r1) + b33d8000| gnu myhr %f8,%f0,%f0 +ed02100b8039| gnu myl %f8,%f0,11(%r2,%r1) + b3398000| gnu mylr %f8,%f0,%f0 +ed02100b803b| gnu my %f8,%f0,11(%r2,%r1) + b33b8000| gnu myr %f8,%f0,%f0 + b9740080| gnu nnrk %r8,%r0,%r0 + b9640080| gnu nngrk %r8,%r0,%r0 + b93b0000| gnu nnpa + b2fa00c8| gnu niai 12,8 +e382100b0025| gnu ntstg %r8,11(%r2,%r1) + b9760080| gnu nork %r8,%r0,%r0 + b9660080| gnu nogrk %r8,%r0,%r0 + b9770080| gnu nxrk %r8,%r0,%r0 + b9670080| gnu nxgrk %r8,%r0,%r0 + 5682100b| gnu o %r8,11(%r2,%r1) + 1680| gnu or %r8,%r0 + b9f60080| gnu ork %r8,%r0,%r0 +e382100b0056| gnu oy %r8,11(%r2,%r1) +e382100b0081| gnu og %r8,11(%r2,%r1) + b9810080| gnu ogr %r8,%r0 + b9e60080| gnu ogrk %r8,%r0,%r0 +d6032006100b| gnu oc 6(4,%r2),11(%r1) + 96ff2006| gnu oi 6(%r2),-1 +ebff20060056| gnu oiy 6(%r2),-1 + a588ffff| gnu oihh %r8,-1 + a589ffff| gnu oihl %r8,-1 +c08cffffffff| gnu oihf %r8,-1 + a58affff| gnu oilh %r8,-1 + a58bffff| gnu oill %r8,-1 +c08dffffffff| gnu oilf %r8,-1 + b9750080| gnu ocrk %r8,%r0,%r0 + b9650080| gnu ocgrk %r8,%r0,%r0 +f2332006100b| gnu pack 6(4,%r2),11(4,%r1) +e9032006100b| gnu pka 6(%r2),11(4,%r1) +e1032006100b| gnu pku 6(%r2),11(4,%r1) + b22e0080| gnu pgin %r8,%r0 + b22f0080| gnu pgout %r8,%r0 + b92c0000| gnu pcc + b9280000| gnu pckmo + 010a| gnu pfpo + b9af0080| gnu pfmf %r8,%r0 +ee80100b80cd| gnu plo %r8,11(%r1),%r0,205(%r8) + b2e83080| gnu ppa %r8,%r0,3 + b93c0080| gnu prno %r8,%r0 + b93c0080| gnu prno %r8,%r0 + 0104| gnu ptff + b9a20080| gnu ptf %r8 + b9e13080| gnu popcnt %r8,%r0,3 +e372100b0036| gnu pfd 7,11(%r2,%r1) +c67200000000| gnu pfdrl 7,0xe68 + b218100b| gnu pc 11(%r1) + 0101| gnu pr + b2280080| gnu pt %r8,%r0 + b99e0080| gnu pti %r8,%r0 + b2480000| gnu palb + b20d0000| gnu ptlb + b3fd0180| gnu qaxtr %f8,%f0,%f0,1 + b3f50180| gnu qadtr %f8,%f0,%f0,1 + b28f100b| gnu qpaci 11(%r1) + b3ff0180| gnu rrxtr %f8,%f0,%r0,1 + b3f70180| gnu rrdtr %f8,%f0,%r0,1 + b23b0000| gnu rchp + b98b0180| gnu rdp %r8,%r0,%r0,1 + b22a0080| gnu rrbe %r8,%r0 + b9ae0080| gnu rrbm %r8,%r0 + b277100b| gnu rp 11(%r1) + b2380000| gnu rsch +eb80100b001d| gnu rll %r8,%r0,11(%r1) +eb80100b001c| gnu rllg %r8,%r0,11(%r1) +ec8009691254| gnu rnsbg %r8,%r0,9,105,18 +ec8009691257| gnu rxsbg %r8,%r0,9,105,18 +ec8009691255| gnu risbg %r8,%r0,9,105,18 +ec8009691259| gnu risbgn %r8,%r0,9,105,18 +ec800969125d| gnu risbhg %r8,%r0,9,105,18 +ec8009691251| gnu risblg %r8,%r0,9,105,18 +ec8009691256| gnu rosbg %r8,%r0,9,105,18 + b25e0080| gnu srst %r8,%r0 + b9be0080| gnu srstu %r8,%r0 + b9f00180| gnu selro %r8,%r0,%r0 + b9e30180| gnu selgro %r8,%r0,%r0 + b9c00180| gnu selfhro %r8,%r0,%r0 + b24e0080| gnu sar %a8,%r0 + b2370000| gnu sal + b219100b| gnu sac 11(%r1) + b279100b| gnu sacf 11(%r1) + 010c| gnu sam24 + 010d| gnu sam31 + 010e| gnu sam64 + b299100b| gnu srnm 11(%r1) + b2b8100b| gnu srnmb 11(%r1) + b23c0000| gnu schm + b204100b| gnu sck 11(%r1) + b206100b| gnu sckc 11(%r1) + 0107| gnu sckpf + b208100b| gnu spt 11(%r1) + b2b9100b| gnu srnmt 11(%r1) + b3840080| gnu sfpc %r8 + b3850080| gnu sfasr %r8 + b210100b| gnu spx 11(%r1) + 0480| gnu spm %r8 + b20a100b| gnu spka 11(%r1) + b2250080| gnu ssar %r8 + b99f0080| gnu ssair %r8 + b22b3080| gnu sske %r8,%r0,3 + 80002006| gnu ssm 6(%r2) +f0392006100b| gnu srp 6(4,%r2),11(%r1),9 + 8f80100b| gnu slda %r8,11(%r1) + 8d80100b| gnu sldl %r8,11(%r1) + 8b80100b| gnu sla %r8,11(%r1) +eb80100b00dd| gnu slak %r8,%r0,11(%r1) +eb80100b000b| gnu slag %r8,%r0,11(%r1) + 8980100b| gnu sll %r8,11(%r1) +eb80100b00df| gnu sllk %r8,%r0,11(%r1) +eb80100b000d| gnu sllg %r8,%r0,11(%r1) + 8e80100b| gnu srda %r8,11(%r1) + 8c80100b| gnu srdl %r8,11(%r1) + 8a80100b| gnu sra %r8,11(%r1) +eb80100b00dc| gnu srak %r8,%r0,11(%r1) +eb80100b000a| gnu srag %r8,%r0,11(%r1) + 8880100b| gnu srl %r8,11(%r1) +eb80100b00de| gnu srlk %r8,%r0,11(%r1) +eb80100b000c| gnu srlg %r8,%r0,11(%r1) +ed02100b8048| gnu slxt %f8,%f0,11(%r2,%r1) +ed02100b8040| gnu sldt %f8,%f0,11(%r2,%r1) +ed02100b8049| gnu srxt %f8,%f0,11(%r2,%r1) +ed02100b8041| gnu srdt %f8,%f0,11(%r2,%r1) + ae80100b| gnu sigp %r8,%r0,11(%r1) + b9380080| gnu sortl %r8,%r0 + b3160080| gnu sqxbr %f8,%f0 + b3360080| gnu sqxr %f8,%f0 +ed82100b0015| gnu sqdb %f8,11(%r2,%r1) + b3150080| gnu sqdbr %f8,%f0 +ed82100b0035| gnu sqd %f8,11(%r2,%r1) + b2440080| gnu sqdr %f8,%f0 +ed82100b0014| gnu sqeb %f8,11(%r2,%r1) + b3140080| gnu sqebr %f8,%f0 +ed82100b0034| gnu sqe %f8,11(%r2,%r1) + b2450080| gnu sqer %f8,%f0 + b233100b| gnu ssch 11(%r1) + 5082100b| gnu st %r8,11(%r2,%r1) +e382100b0050| gnu sty %r8,11(%r2,%r1) +e382100b0024| gnu stg %r8,11(%r2,%r1) + 6082100b| gnu std %f8,11(%r2,%r1) +ed82100b0067| gnu stdy %f8,11(%r2,%r1) + 7082100b| gnu ste %f8,11(%r2,%r1) +ed82100b0066| gnu stey %f8,11(%r2,%r1) + 9b80100b| gnu stam %a8,%a0,11(%r1) +eb80100b009b| gnu stamy %a8,%a0,11(%r1) + b201100b| gnu stbear 11(%r1) + b23a100b| gnu stcps 11(%r1) + b239100b| gnu stcrw 11(%r1) + 4282100b| gnu stc %r8,11(%r2,%r1) +e382100b0072| gnu stcy %r8,11(%r2,%r1) +e382100b00c3| gnu stch %r8,11(%r2,%r1) +eb83100b002c| gnu stcmh %r8,3,11(%r1) + be83100b| gnu stcm %r8,3,11(%r1) +eb83100b002d| gnu stcmy %r8,3,11(%r1) + b205100b| gnu stck 11(%r1) + b207100b| gnu stckc 11(%r1) + b278100b| gnu stcke 11(%r1) + b27c100b| gnu stckf 11(%r1) + b680100b| gnu stctl %c8,%c0,11(%r1) +eb80100b0025| gnu stctg %c8,%c0,11(%r1) + b212100b| gnu stap 11(%r1) + b202100b| gnu stidp 11(%r1) + b209100b| gnu stpt 11(%r1) + b2b1100b| gnu stfl 11(%r1) + b2b0100b| gnu stfle 11(%r1) + b29c100b| gnu stfpc 11(%r1) +e382100b0049| gnu stgsc %r8,11(%r2,%r1) + 4082100b| gnu sth %r8,11(%r2,%r1) +e382100b0070| gnu sthy %r8,11(%r2,%r1) +e382100b00c7| gnu sthh %r8,11(%r2,%r1) +c48700000000| gnu sthrl %r8,0x109c +e382100b00cb| gnu stfh %r8,11(%r2,%r1) +eb83100b00e1| gnu stocfhnle %r8,11(%r1) + 9080100b| gnu stm %r8,%r0,11(%r1) +eb80100b0090| gnu stmy %r8,%r0,11(%r1) +eb80100b0024| gnu stmg %r8,%r0,11(%r1) +eb80100b0026| gnu stmh %r8,%r0,11(%r1) +eb83100b00f3| gnu stocnle %r8,11(%r1) +eb83100b00e3| gnu stocgnle %r8,11(%r1) +e382100b008e| gnu stpq %r8,11(%r2,%r1) + b211100b| gnu stpx 11(%r1) +e5022006100b| gnu strag 6(%r2),11(%r1) +c48f00000000| gnu strl %r8,0x10e0 +c48b00000000| gnu stgrl %r8,0x10e6 +e382100b003f| gnu strvh %r8,11(%r2,%r1) +e382100b003e| gnu strv %r8,11(%r2,%r1) +e382100b002f| gnu strvg %r8,11(%r2,%r1) + b234100b| gnu stsch 11(%r1) + b27d100b| gnu stsi 11(%r1) + ac082006| gnu stnsm 6(%r2),8 + ad082006| gnu stosm 6(%r2),8 + b2460080| gnu stura %r8,%r0 + b9250080| gnu sturg %r8,%r0 + 5b82100b| gnu s %r8,11(%r2,%r1) + 1b80| gnu sr %r8,%r0 + b9f90080| gnu srk %r8,%r0,%r0 +e382100b005b| gnu sy %r8,11(%r2,%r1) +e382100b0009| gnu sg %r8,11(%r2,%r1) + b9090080| gnu sgr %r8,%r0 + b9e90080| gnu sgrk %r8,%r0,%r0 +e382100b0019| gnu sgf %r8,11(%r2,%r1) + b9190080| gnu sgfr %r8,%r0 + b34b0080| gnu sxbr %f8,%f0 + b3db0080| gnu sxtr %f8,%f0,%f0 + b3db0180| gnu sxtra %f8,%f0,%f0,1 +ed82100b001b| gnu sdb %f8,11(%r2,%r1) + b31b0080| gnu sdbr %f8,%f0 + b3d30080| gnu sdtr %f8,%f0,%f0 + b3d30180| gnu sdtra %f8,%f0,%f0,1 +ed82100b000b| gnu seb %f8,11(%r2,%r1) + b30b0080| gnu sebr %f8,%f0 +fb332006100b| gnu sp 6(4,%r2),11(4,%r1) + 4b82100b| gnu sh %r8,11(%r2,%r1) +e382100b007b| gnu shy %r8,11(%r2,%r1) +e382100b0039| gnu sgh %r8,11(%r2,%r1) + b9c90080| gnu shhhr %r8,%r0,%r0 + b9d90080| gnu shhlr %r8,%r0,%r0 + 5f82100b| gnu sl %r8,11(%r2,%r1) + 1f80| gnu slr %r8,%r0 + b9fb0080| gnu slrk %r8,%r0,%r0 +e382100b005f| gnu sly %r8,11(%r2,%r1) +e382100b000b| gnu slg %r8,11(%r2,%r1) + b90b0080| gnu slgr %r8,%r0 + b9eb0080| gnu slgrk %r8,%r0,%r0 +e382100b001b| gnu slgf %r8,11(%r2,%r1) + b91b0080| gnu slgfr %r8,%r0 + b9cb0080| gnu slhhhr %r8,%r0,%r0 + b9db0080| gnu slhhlr %r8,%r0,%r0 +c28500000008| gnu slfi %r8,8 +c28400000008| gnu slgfi %r8,8 +e382100b0099| gnu slb %r8,11(%r2,%r1) + b9990080| gnu slbr %r8,%r0 +e382100b0089| gnu slbg %r8,11(%r2,%r1) + b9890080| gnu slbgr %r8,%r0 + 3780| gnu sxr %f8,%f0 + 6b82100b| gnu sd %f8,11(%r2,%r1) + 2b80| gnu sdr %f8,%f0 + 7b82100b| gnu se %f8,11(%r2,%r1) + 3b80| gnu ser %f8,%f0 + 6f82100b| gnu sw %f8,11(%r2,%r1) + 2f80| gnu swr %f8,%f0 + 7f82100b| gnu su %f8,11(%r2,%r1) + 3f80| gnu sur %f8,%f0 + 0a7c| gnu svc 124 + b24c0080| gnu tar %a8,%r0 + 010b| gnu tam + 93002006| gnu ts 6(%r2) + b22c0080| gnu tb %r8,%r0 +ed82100b0012| gnu tcxb %f8,11(%r2,%r1) +ed82100b0058| gnu tdcxt %f8,11(%r2,%r1) +ed82100b0011| gnu tcdb %f8,11(%r2,%r1) +ed82100b0054| gnu tdcdt %f8,11(%r2,%r1) +ed82100b0010| gnu tceb %f8,11(%r2,%r1) +ed82100b0050| gnu tdcet %f8,11(%r2,%r1) +ed82100b0059| gnu tdgxt %f8,11(%r2,%r1) +ed82100b0055| gnu tdgdt %f8,11(%r2,%r1) +ed82100b0051| gnu tdget %f8,11(%r2,%r1) +eb30200600c0| gnu tp 6(4,%r2) + b9a10080| gnu tpei %r8,%r0 + b236100b| gnu tpi 11(%r1) +e5012006100b| gnu tprot 6(%r2),11(%r1) + b235100b| gnu tsch 11(%r1) + 91082006| gnu tm 6(%r2),8 +eb0820060051| gnu tmy 6(%r2),8 + a7820008| gnu tmhh %r8,8 + a7830008| gnu tmhl %r8,8 + a7800008| gnu tmlh %r8,8 + a7810008| gnu tmll %r8,8 + a7800008| gnu tmlh %r8,8 + a7810008| gnu tmll %r8,8 + 9980100b| gnu trace %r8,%r0,11(%r1) +eb80100b000f| gnu tracg %r8,%r0,11(%r1) + b2fc100b| gnu tabort 11(%r1) +e56120060008| gnu tbeginc 6(%r2),8 +e56020060008| gnu tbegin 6(%r2),8 + b2f80000| gnu tend +dc032006100b| gnu tr 6(4,%r2),11(%r1) +dd032006100b| gnu trt 6(4,%r2),11(%r1) + b9bf3080| gnu trte %r8,%r0,3 +d0032006100b| gnu trtr 6(4,%r2),11(%r1) + b9bd3080| gnu trtre %r8,%r0,3 + b2a50080| gnu tre %r8,%r0 + b9933080| gnu troo %r8,%r0,3 + b9923080| gnu trot %r8,%r0,3 + b9913080| gnu trto %r8,%r0,3 + b9903080| gnu trtt %r8,%r0,3 + 01ff| gnu trap2 + b2ff100b| gnu trap4 11(%r1) +f3332006100b| gnu unpk 6(4,%r2),11(4,%r1) +ea032006100b| gnu unpka 6(4,%r2),11(%r1) +e2032006100b| gnu unpku 6(4,%r2),11(%r1) + 0102| gnu upt +e723500018f3| gnu vah %v18,%v3,%v5 +e723500018f1| gnu vacch %v18,%v3,%v5 +e62350969871| gnu vap %v18,%v3,%v5,105,9 +e723590088bb| gnu vac %v18,%v3,%v5,%v8,9 +e723590088b9| gnu vaccc %v18,%v3,%v5,%v8,9 +e72350000868| gnu vn %v18,%v3,%v5 +e72350000869| gnu vnc %v18,%v3,%v5 +e723500018f2| gnu vavgh %v18,%v3,%v5 +e723500018f0| gnu vavglh %v18,%v3,%v5 +e72350000885| gnu vbperm %v18,%v3,%v5 +e72350000866| gnu vcksm %v18,%v3,%v5 +e60230300477| gnu vcp %v18,%v3,3 +e723509018f8| gnu vceq %v18,%v3,%v5,1,9 +e723509018fb| gnu vch %v18,%v3,%v5,1,9 +e723509018f9| gnu vchl %v18,%v3,%v5,1,9 +e6235010087d| gnu vcsph %v18,%v3,%v5,1 +e68300310050| gnu vcvb %r8,%v3,3,1 +e68300310052| gnu vcvbg %r8,%v3,3,1 +e62000109858| gnu vcvd %v18,%r0,9,1 +e6200010985a| gnu vcvdg %v18,%r0,9,1 +e62300300851| gnu vclzdp %v18,%v3,3 +e72300003853| gnu vclzg %v18,%v3 +e72300003852| gnu vctzg %v18,%v3 +e6235096987a| gnu vdp %v18,%v3,%v5,105,9 +e723000038db| gnu vecg %v18,%v3 +e723000038d9| gnu veclg %v18,%v3 +e72350699872| gnu verim %v18,%v3,%v5,105,9 +e725100b1833| gnu verllh %v18,%v5,11(%r1) +e72350001873| gnu verllvh %v18,%v3,%v5 +e72350001870| gnu veslvh %v18,%v3,%v5 +e725100b1830| gnu veslh %v18,%v5,11(%r1) +e725100b183a| gnu vesrah %v18,%v5,11(%r1) +e7235000187a| gnu vesravh %v18,%v3,%v5 +e725100b1838| gnu vesrlh %v18,%v5,11(%r1) +e72350001878| gnu vesrlvh %v18,%v3,%v5 +e7235000086d| gnu vx %v18,%v3,%v5 +e72350901882| gnu vfaehs %v18,%v3,%v5,8 +e72350901880| gnu vfeeh %v18,%v3,%v5,9 +e72350901881| gnu vfeneh %v18,%v3,%v5,9 +e723500918e3| gnu vfa %v18,%v3,%v5,1,9 +e723000138ca| gnu wfk %v18,%v3,3,1 +e72350b918e8| gnu vfce %v18,%v3,%v5,1,9,11 +e72350b918eb| gnu vfch %v18,%v3,%v5,1,9,11 +e72350b918ea| gnu vfche %v18,%v3,%v5,1,9,11 +e723000138cb| gnu wfc %v18,%v3,3,1 +e62300013856| gnu vclfnh %v18,%v3,3,1 +e6230001385e| gnu vclfnl %v18,%v3,3,1 +e62350091875| gnu vcrnf %v18,%v3,%v5,1,9 +e723009138c3| gnu vcdgb %v18,%v3,1,9 +e723009138c3| gnu vcdgb %v18,%v3,1,9 +e723009138c1| gnu vcdlgb %v18,%v3,1,9 +e723009138c1| gnu vcdlgb %v18,%v3,1,9 +e6230001385d| gnu vcfn %v18,%v3,3,1 +e723009138c2| gnu vcgdb %v18,%v3,1,9 +e723009138c2| gnu vcgdb %v18,%v3,1,9 +e723009138c0| gnu vclgdb %v18,%v3,1,9 +e723009138c0| gnu vclgdb %v18,%v3,1,9 +e62300013855| gnu vcnf %v18,%v3,3,1 +e723500918e5| gnu vfd %v18,%v3,%v5,1,9 +e723000138c4| gnu vfll %v18,%v3,3,1 +e723009138c5| gnu vflrd %v18,%v3,1,9 +e72350b918ef| gnu vfmax %v18,%v3,%v5,1,9,11 +e72350b918ee| gnu vfmin %v18,%v3,%v5,1,9,11 +e723500918e7| gnu vfm %v18,%v3,%v5,1,9 +e7235b09888f| gnu vfma %v18,%v3,%v5,%v8,9,11 +e7235b09888e| gnu vfms %v18,%v3,%v5,%v8,9,11 +e7235b09889f| gnu vfnma %v18,%v3,%v5,%v8,9,11 +e7235b09889e| gnu vfnms %v18,%v3,%v5,%v8,9,11 +e723009138cc| gnu vfpso %v18,%v3,3,1,9 +e723000138ce| gnu vfsq %v18,%v3,3,1 +e723500918e2| gnu vfs %v18,%v3,%v5,1,9 +e7230099184a| gnu vftci %v18,%v3,9,1,9 +e723500018b4| gnu vgfmh %v18,%v3,%v5 +e723590088bc| gnu vgfma %v18,%v3,%v5,%v8,9 +e723100b3813| gnu vgef %v18,11(%v3,%r1),3 +e723100b3812| gnu vgeg %v18,11(%v3,%r1),3 +e72000080844| gnu vgbm %v18,8 +e72008091846| gnu vgmh %v18,8,9 +e7230090385c| gnu vistr %v18,%v3,3,9 +e722100b3806| gnu vl %v18,11(%r2,%r1),3 +e72300000856| gnu vlr %v18,%v3 +e722100b3805| gnu vlrepg %v18,11(%r2,%r1) +e622100b3801| gnu vlebrh %v18,11(%r2,%r1),3 +e622100b3803| gnu vlebrf %v18,11(%r2,%r1),3 +e622100b3802| gnu vlebrg %v18,11(%r2,%r1),3 +e622100b3805| gnu vlbrrepg %v18,11(%r2,%r1) +e622100b3804| gnu ldrv %v18,11(%r2,%r1) +e622100b3806| gnu vlbrg %v18,11(%r2,%r1) +e723000038de| gnu vlcg %v18,%v3 +e722100b3801| gnu vleh %v18,11(%r2,%r1),3 +e722100b3803| gnu vlef %v18,11(%r2,%r1),3 +e722100b3802| gnu vleg %v18,11(%r2,%r1),3 +e722100b3800| gnu vleb %v18,11(%r2,%r1),3 +e720ffff3841| gnu vleih %v18,-1,3 +e720ffff3843| gnu vleif %v18,-1,3 +e720ffff3842| gnu vleig %v18,-1,3 +e720ffff3840| gnu vleib %v18,-1,3 +e622100b3807| gnu vlerg %v18,11(%r2,%r1) +e723009138c7| gnu vfidb %v18,%v3,1,9 +e785100b1021| gnu vlgvh %r8,%v5,11(%r1) +e62000089849| gnu vlip %v18,8,9 +e722100b3804| gnu vllezg %v18,11(%r2,%r1) +e725100b1836| gnu vlm %v18,%v5,11(%r1),1 +e723000038df| gnu vlpg %v18,%v3 +e609100b2135| gnu vlrl %v18,11(%r1),9 +e600100b2137| gnu vlrlr %v18,%r0,11(%r1) +e722100b3807| gnu vlbb %v18,11(%r2,%r1),3 +e720100b1822| gnu vlvgh %v18,%r0,11(%r1) +e72000000862| gnu vlvgp %v18,%r0,%r0 +e720100b0837| gnu vll %v18,%r0,11(%r1) +e723500018ff| gnu vmxh %v18,%v3,%v5 +e723500018fd| gnu vmxlh %v18,%v3,%v5 +e72350001861| gnu vmrhh %v18,%v3,%v5 +e72350001860| gnu vmrlh %v18,%v3,%v5 +e723500018fe| gnu vmnh %v18,%v3,%v5 +e723500018fc| gnu vmnlh %v18,%v3,%v5 +e723590088ae| gnu vmae %v18,%v3,%v5,%v8,9 +e723590088ab| gnu vmah %v18,%v3,%v5,%v8,9 +e723590088ac| gnu vmale %v18,%v3,%v5,%v8,9 +e723590088a9| gnu vmalh %v18,%v3,%v5,%v8,9 +e723590088ad| gnu vmalo %v18,%v3,%v5,%v8,9 +e723590088aa| gnu vmal %v18,%v3,%v5,%v8,9 +e723590088af| gnu vmao %v18,%v3,%v5,%v8,9 +e62350969879| gnu vmsp %v18,%v3,%v5,105,9 +e62350969878| gnu vmp %v18,%v3,%v5,105,9 +e723500018a6| gnu vmeh %v18,%v3,%v5 +e723500018a3| gnu vmhh %v18,%v3,%v5 +e723500018a4| gnu vmleh %v18,%v3,%v5 +e723500018a1| gnu vmlhh %v18,%v3,%v5 +e723500018a5| gnu vmloh %v18,%v3,%v5 +e723500018a2| gnu vmlhw %v18,%v3,%v5 +e723500018a7| gnu vmoh %v18,%v3,%v5 +e72359b088b8| gnu vmsl %v18,%v3,%v5,%v8,9,11 +e7235000086e| gnu vnn %v18,%v3,%v5 +e7235000086b| gnu vno %v18,%v3,%v5 +e7235000086c| gnu vnx %v18,%v3,%v5 +e7235000086a| gnu vo %v18,%v3,%v5 +e7235000086f| gnu voc %v18,%v3,%v5 +e72350001894| gnu vpkh %v18,%v3,%v5 +e72350901895| gnu vpkls %v18,%v3,%v5,1,9 +e72350901897| gnu vpks %v18,%v3,%v5,1,9 +e609100b2134| gnu vpkz %v18,11(%r1),9 +e62350969870| gnu vpkzr %v18,%v3,%v5,105,9 +e6236990985b| gnu vpsop %v18,%v3,9,105,9 +e7235000888c| gnu vperm %v18,%v3,%v5,%v8 +e72350001884| gnu vpdi %v18,%v3,%v5,1 +e72300003850| gnu vpopctg %v18,%v3 +e6235096987b| gnu vrp %v18,%v3,%v5,105,9 +e7250008184d| gnu vreph %v18,%v5,8 +e72000083845| gnu vrepig %v18,8 +e723100b381b| gnu vscef %v18,11(%v3,%r1),3 +e723100b381a| gnu vsceg %v18,11(%v3,%r1),3 +e7235000888d| gnu vsel %v18,%v3,%v5,%v8 +e6235096987e| gnu vsdp %v18,%v3,%v5,105,9 +e62369909859| gnu vsrp %v18,%v3,9,105,9 +e62350969872| gnu vsrpr %v18,%v3,%v5,105,9 +e72350000874| gnu vsl %v18,%v3,%v5 +e72350000875| gnu vslb %v18,%v3,%v5 +e72350690886| gnu vsld %v18,%v3,%v5,105 +e72350690877| gnu vsldb %v18,%v3,%v5,105 +e7235000087e| gnu vsra %v18,%v3,%v5 +e7235000087f| gnu vsrab %v18,%v3,%v5 +e72350690887| gnu vsrd %v18,%v3,%v5,105 +e7235000087c| gnu vsrl %v18,%v3,%v5 +e7235000087d| gnu vsrlb %v18,%v3,%v5 +e7230000385f| gnu vseg %v18,%v3,3 +e722100b380e| gnu vst %v18,11(%r2,%r1),3 +e622100b3809| gnu vstebrh %v18,11(%r2,%r1),3 +e622100b380b| gnu vstebrf %v18,11(%r2,%r1),3 +e622100b380a| gnu vstebrg %v18,11(%r2,%r1),3 +e622100b380e| gnu vstbrg %v18,11(%r2,%r1) +e722100b3809| gnu vsteh %v18,11(%r2,%r1),3 +e722100b380b| gnu vstef %v18,11(%r2,%r1),3 +e722100b380a| gnu vsteg %v18,11(%r2,%r1),3 +e722100b3808| gnu vsteb %v18,11(%r2,%r1),3 +e622100b380f| gnu vsterg %v18,11(%r2,%r1) +e725100b183e| gnu vstm %v18,%v5,11(%r1),1 +e609100b213d| gnu vstrl %v18,11(%r1),9 +e600100b213f| gnu vstrlr %v18,%r0,11(%r1) +e720100b083f| gnu vstl %v18,%r0,11(%r1) +e72359b0888a| gnu vstrc %v18,%v3,%v5,%v8,9,11 +e72359b0888b| gnu vstrs %v18,%v3,%v5,%v8,9,11 +e723500018f7| gnu vsh %v18,%v3,%v5 +e723500018f5| gnu vscbih %v18,%v3,%v5 +e62350969873| gnu vsp %v18,%v3,%v5,105,9 +e723590088bd| gnu vsbcbi %v18,%v3,%v5,%v8,9 +e723590088bf| gnu vsbi %v18,%v3,%v5,%v8,9 +e72350001865| gnu vsumgh %v18,%v3,%v5 +e72350001867| gnu vsumq %v18,%v3,%v5,1 +e72350001864| gnu vsumh %v18,%v3,%v5 +e6020000045f| gnu vtp %v18 +e723000008d8| gnu vtm %v18,%v3 +e723000038d7| gnu vuph %v18,%v3,3 +e723000038d5| gnu vuplh %v18,%v3,3 +e723000038d4| gnu vupll %v18,%v3,3 +e723000038d6| gnu vupl %v18,%v3,3 +e609100b213c| gnu vupkz %v18,11(%r1),9 +e62300300854| gnu vupkzh %v18,%v3,3 +e6230030085c| gnu vupkzl %v18,%v3,3 +f8332006100b| gnu zap 6(4,%r2),11(4,%r1) diff --git a/s390x/s390xmap/map.go b/s390x/s390xmap/map.go new file mode 100644 index 00000000..3fc89f11 --- /dev/null +++ b/s390x/s390xmap/map.go @@ -0,0 +1,634 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// s390xmap constructs the s390x opcode map from the instruction set CSV file. +// +// Usage: +// +// s390map [-fmt=format] s390x.csv +// +// The known output formats are: +// +// text (default) - print decoding tree in text form +// decoder - print decoding tables for the s390xasm package +// encoder - generate a self-contained file which can be used to encode +// go obj.Progs into machine code +// asm - generate a GNU asm file which can be compiled by gcc containing +// all opcodes discovered in s390x.csv using macro friendly arguments. +package main + +import ( + "bytes" + "encoding/csv" + "flag" + "fmt" + gofmt "go/format" + "log" + "os" + "regexp" + "strconv" + "strings" + + asm "golang.org/x/arch/s390x/s390xasm" +) + +var format = flag.String("fmt", "text", "output format: text, decoder, asm") +var debug = flag.Bool("debug", false, "enable debugging output") + +var inputFile string + +func usage() { + fmt.Fprintf(os.Stderr, "usage: s390xmap [-fmt=format] s390x.csv\n") + os.Exit(2) +} + +func main() { + log.SetFlags(0) + log.SetPrefix("s390xmap: ") + + flag.Usage = usage + flag.Parse() + if flag.NArg() != 1 { + usage() + } + + inputFile = flag.Arg(0) + + var printTyp func(*Prog) + switch *format { + default: + log.Fatalf("unknown output format %q", *format) + case "text": + printTyp = printText + case "decoder": + printTyp = printDecoder + case "asm": + printTyp = printASM + case "encoder": + printTyp = printEncoder + } + + p, err := readCSV(flag.Arg(0)) + if err != nil { + log.Fatal(err) + } + log.Printf("Parsed %d instruction forms.", len(p.Insts)) + printTyp(p) +} + +// readCSV reads the CSV file and returns the corresponding Prog. +// It may print details about problems to standard error using the log package. +func readCSV(file string) (*Prog, error) { + // Read input. + // Skip leading blank and # comment lines. + f, err := os.Open(file) + if err != nil { + return nil, err + } + csvReader := csv.NewReader(f) + csvReader.Comment = '#' + table, err := csvReader.ReadAll() + if err != nil { + return nil, fmt.Errorf("parsing %s: %v", file, err) + } + if len(table) == 0 { + return nil, fmt.Errorf("empty csv input") + } + if len(table[0]) < 3 { + return nil, fmt.Errorf("csv too narrow: need at least four columns") + } + + p := &Prog{} + for _, row := range table { + add(p, row[0], row[1], row[2], row[3]) + } + return p, nil +} + +type Prog struct { + Insts []Inst + OpRanges map[string]string + nextOrder int // Next position value (used for Insts[x].order) +} + +type Field struct { + Name string + BitField asm.BitField + Type asm.ArgType + flags uint16 +} + +func (f Field) String() string { + return fmt.Sprintf("%v(%s%v)", f.Type, f.Name, f.BitField) +} + +type Inst struct { + Text string + Encoding string + Op string + Mask uint64 + Value uint64 + DontCare uint64 + Len uint16 + Fields []Field +} + +func (i Inst) String() string { + return fmt.Sprintf("%s (%s) %08x/%08x %v (%s)", i.Op, i.Encoding, i.Value, i.Mask, i.Fields, i.Text) +} + +type Arg struct { + Name string + Bits int8 + Offs int8 +} + +func (a Arg) String() string { + return fmt.Sprintf("%s[%d:%d]", a.Name, a.Offs, a.Offs+a.Bits-1) +} + +func (a Arg) Maximum() int { + return 1< 0 { + args[len(args)-1].Bits += int8(off) + } + if name != "" && name != "??" { + arg := Arg{Name: name, Offs: int8(off), Bits: int8(-off)} + args.Append(arg) + } + } + return args +} + +// Compute the Mask (usually Opcode + secondary Opcode bitfields), +// the Value (the expected value under the mask), and +// reserved bits (i.e the // fields which should be set to 0) +func computeMaskValueReserved(args Args, text string) (mask, value, reserved uint64) { + for i := 0; i < len(args); i++ { + arg := args[i] + v, err := strconv.Atoi(arg.Name) + switch { + case err == nil && v >= 0: // is a numbered field + if v < 0 || v > arg.Maximum() { + fmt.Fprintf(os.Stderr, "%s: field %s value (%d) is out of range (%d-bit)\n", text, arg, v, arg.Bits) + } + mask |= arg.BitMask() + value |= uint64(v) << arg.Shift() + args.Delete(i) + i-- + case arg.Name[0] == '/': // don't care + if arg.Name != strings.Repeat("/", len(arg.Name)) { + log.Fatalf("%s: arg %v named like a don't care bit, but it's not", text, arg) + } + reserved |= arg.BitMask() + args.Delete(i) + i-- + default: + continue + } + } + // sanity checks + if mask&reserved != 0 { + log.Fatalf("%s: mask (%08x) and don't care (%08x) collide", text, mask, reserved) + } + if value&^mask != 0 { + log.Fatalf("%s: value (%08x) out of range of mask (%08x)", text, value, mask) + } + return +} + +func Imm_signed_8bit_check(op string) bool { + imm_8 := []string{"ASI", "AGSI", "ALSI", "ALGSI", "CIB", "CGIB", "CIJ", "CGIJ", "NI", "NIY", "OI", "OIY", "XI", "XIY"} + var ret bool + ret = false + for _, str := range imm_8 { + if strings.Compare(op, str) == 0 { + ret = true + break + } + } + return ret +} + +func Imm_signed_16bit_check(op string) bool { + imm_16 := []string{"AHI", "AGHI", "ALHSIK", "ALGHSIK", "AHIK", "AGHIK", "LHI", "LGHI", "MVGHI", "CIT", "CGIT", "CGHI", "CGHSI", "CHHSI", "CHI", "CHSI", "CRJ", "CGRJ", "NIHH", "NILL", "NIHL", "NILH", "LLIHH", "LLILL", "LLIHL", "LLILH", "OIHH", "OILL", "OIHL", "OILH", "VLEIB", "VLEIH", "VLEIF", "VLEIG"} + var ret bool + ret = false + for _, str := range imm_16 { + if strings.Compare(op, str) == 0 { + ret = true + break + } + } + return ret +} + +func Imm_signed_32bit_check(op string) bool { + imm_32 := []string{"AFI", "AGFI", "AIH", "CIH", "CFI", "CGFI", "CRL", "STRL", "STGRL", "LGFI", "LLIHF", "LLILF", "MSFI", "MSGFI", "MGHI", "MHI", "NIHF", "NILF", "OILF", "OIHF", "XILF", "XIHF"} + var ret bool + ret = false + for _, str := range imm_32 { + if strings.Compare(op, str) == 0 { + ret = true + break + } + } + return ret +} + +func check_flags(flags string) bool { + if strings.Contains(flags, "Da") { + return true + } else if strings.Contains(flags, "Db") { + return true + } else if strings.Contains(flags, "Dt") { + return true + } else { + return false + } +} + +// Parse a row from the CSV describing the instructions, and place the +// detected instructions into p. One entry may generate multiple intruction +// entries as each extended mnemonic listed in text is treated like a unique +// instruction. +func add(p *Prog, text, mnemonics, encoding, flags string) { + // Parse encoding, building size and offset of each field. + // The first field in the encoding is the smallest offset. + // And note the MSB is bit 0, not bit 31. + // Example: "31@0|RS@6|RA@11|///@16|26@21|Rc@31|" + var args Args + + args = parseFields(encoding, text) + mask, value, dontCare := computeMaskValueReserved(args, text) + + // split mnemonics into individual instructions + inst := Inst{Text: text, Encoding: mnemonics, Value: value, Mask: mask, DontCare: dontCare} + + // order inst.Args according to mnemonics order + for i, opr := range operandRe.FindAllString(mnemonics, -1) { + if i == 0 { // operation + inst.Op = opr + continue + } + field := Field{Name: opr} + typ := asm.TypeUnknown + flag := uint16(0) + switch opr { + case "R1", "R2", "R3": + s := strings.Split(mnemonics, " ") + switch opr { + case "R1": + switch s[0] { + case "CPDT", "CPXT", "CDXT", "CZXT", "CZDT": + typ = asm.TypeFPReg + flag = 0x2 + case "CUXTR", "EEXTR", "EEDTR", "EFPC", "ESXTR", "ESDTR", "LGDR", "SFPC", "SFASR": + typ = asm.TypeReg + flag = 0x1 + case "CPYA", "LAM", "LAMY", "STAM", "STAMY", "SAR", "TAR": + typ = asm.TypeACReg + flag = 0x3 + case "LCTL", "LCTLG", "STCTL", "STCTG": + typ = asm.TypeCReg + flag = 0x4 + default: + if check_flags(flags) { + if strings.Contains(text, "CONVERT TO") { + typ = asm.TypeReg + flag = 0x1 + } else { + typ = asm.TypeFPReg + flag = 0x2 + } + } else { + typ = asm.TypeReg + flag = 0x1 + } + } + case "R2": + switch s[0] { + case "IEXTR", "IEDTR", "LDGR", "RRXTR", "RRDTR": + typ = asm.TypeReg + flag = 0x1 + case "CPYA", "EAR": + typ = asm.TypeACReg + flag = 0x3 + default: + if check_flags(flags) { + if strings.Contains(text, "CONVERT FROM") { + typ = asm.TypeReg + flag = 0x1 + } else { + typ = asm.TypeFPReg + flag = 0x2 + } + } else { + typ = asm.TypeReg + flag = 0x1 + } + } + case "R3": + switch s[0] { + case "LAM", "LAMY", "STAM", "STAMY": + typ = asm.TypeACReg + flag = 0x3 + case "LCTL", "LCTLG", "STCTL", "STCTG": + typ = asm.TypeCReg + flag = 0x4 + default: + if check_flags(flags) { + typ = asm.TypeFPReg + flag = 0x2 + } else { + typ = asm.TypeReg + flag = 0x1 + } + } + } + + case "I", "I1", "I2", "I3", "I4", "I5": + flag = 0x0 + switch opr { + case "I", "I1": + typ = asm.TypeImmUnsigned + + case "I2": + if Imm_signed_8bit_check(inst.Op) { + typ = asm.TypeImmSigned8 + break + } else if Imm_signed_16bit_check(inst.Op) { // "ASI", "AGSI", "ALSI", "ALGSI" + typ = asm.TypeImmSigned16 + break + } else if Imm_signed_32bit_check(inst.Op) { // "AHI", "AGHI", "AHIK", "AGHIK", "LHI", "LGHI" + typ = asm.TypeImmSigned32 + break + } else { + typ = asm.TypeImmUnsigned + break + } + + case "I3", "I4", "I5": + typ = asm.TypeImmUnsigned + + } + + case "RI2", "RI3", "RI4": + flag = 0x80 + i := args.Find(opr) + count := uint8(args[i].Bits) + if count == 12 { + typ = asm.TypeRegImSigned12 + break + } else if count == 16 { + typ = asm.TypeRegImSigned16 + break + } else if count == 24 { + typ = asm.TypeRegImSigned24 + break + } else if count == 32 { + typ = asm.TypeRegImSigned32 + break + } + + case "M1", "M3", "M4", "M5", "M6": + flag = 0x800 + typ = asm.TypeMask + + case "B1", "B2", "B3", "B4": + typ = asm.TypeBaseReg + flag = 0x20 | 0x01 + + case "X2": + typ = asm.TypeIndexReg + flag = 0x40 | 0x01 + + case "D1", "D2", "D3", "D4": + flag = 0x10 + i := args.Find(opr) + if uint8(args[i].Bits) == 20 { + typ = asm.TypeDispSigned20 + break + } else { + typ = asm.TypeDispUnsigned + break + } + + case "L1", "L2": + typ = asm.TypeLen + flag = 0x10 + case "V1", "V2", "V3", "V4", "V5", "V6": + typ = asm.TypeVecReg + flag = 0x08 + } + + if typ == asm.TypeUnknown { + log.Fatalf("%s %s unknown type for opr %s", text, inst, opr) + } + field.Type = typ + field.flags = flag + var f1 asm.BitField + i := args.Find(opr) + if i < 0 { + log.Fatalf("%s: couldn't find %s in %s", text, opr, args) + } + f1.Offs, f1.Bits = uint8(args[i].Offs), uint8(args[i].Bits) + field.BitField = f1 + inst.Fields = append(inst.Fields, field) + } + if strings.HasPrefix(inst.Op, "V") || strings.Contains(inst.Op, "WFC") || strings.Contains(inst.Op, "WFK") { //Check Vector Instructions + Bits := asm.BitField{Offs: 36, Bits: 4} + field := Field{Name: "RXB", BitField: Bits, Type: asm.TypeImmUnsigned, flags: 0xC00} + inst.Fields = append(inst.Fields, field) + } + if *debug { + fmt.Printf("%v\n", inst) + } + p.Insts = append(p.Insts, inst) +} + +// operandRe matches each operand (including opcode) in instruction mnemonics +var operandRe = regexp.MustCompile(`([[:alpha:]][[:alnum:]_]*\.?)`) + +// printText implements the -fmt=text mode, which is not implemented (yet?). +func printText(p *Prog) { + log.Fatal("-fmt=text not implemented") +} + +// printEncoder implements the -fmt=encoder mode. which is not implemented (yet?). +func printEncoder(p *Prog) { + log.Fatal("-fmt=encoder not implemented") +} + +func printASM(p *Prog) { + fmt.Printf("#include \"hack.h\"\n") + fmt.Printf(".text\n") + for _, inst := range p.Insts { + fmt.Printf("\t%s\n", inst.Encoding) + } +} + +// argFieldName constructs a name for the argField +func argFieldName(f Field) string { + ns := []string{"ap", f.Type.String()} + b := f.BitField + ns = append(ns, fmt.Sprintf("%d_%d", b.Offs, b.Offs+b.Bits-1)) + return strings.Join(ns, "_") +} + +// printDecoder implements the -fmt=decoder mode. +// It emits the tables.go for package armasm's decoder. +func printDecoder(p *Prog) { + var buf bytes.Buffer + + fmt.Fprintf(&buf, "// Code generated by s390xmap -fmt=decoder %s DO NOT EDIT.\n", inputFile) + fmt.Fprintf(&buf, "\n") + + fmt.Fprintf(&buf, "package s390xasm\n\n") + + // Build list of opcodes, using the csv order (which corresponds to ISA docs order) + m := map[string]bool{} + fmt.Fprintf(&buf, "const (\n\t_ Op = iota\n") + for i := 0; i < len(p.Insts); i++ { + name := p.Insts[i].Op + switch name { + case "CUUTF", "CUTFU", "PPNO": + m[name] = false + p.Insts = append(p.Insts[:i], p.Insts[i+1:]...) + i-- + default: + m[name] = true + } + if ok := m[name]; !ok { + continue + } + fmt.Fprintf(&buf, "\t%s\n", name) + } + fmt.Fprint(&buf, ")\n\n\n") + + // Emit slice mapping opcode number to name string. + m = map[string]bool{} + fmt.Fprintf(&buf, "var opstr = [...]string{\n") + for _, inst := range p.Insts { + name := inst.Op + if ok := m[name]; ok { + continue + } + m[name] = true + fmt.Fprintf(&buf, "\t%s: %q,\n", inst.Op, strings.ToLower(inst.Op)) + } + fmt.Fprint(&buf, "}\n\n\n") + + // print out argFields + fmt.Fprintf(&buf, "var (\n") + m = map[string]bool{} + for _, inst := range p.Insts { + for _, f := range inst.Fields { + name := argFieldName(f) + if ok := m[name]; ok { + continue + } + m[name] = true + fmt.Fprintf(&buf, "\t%s = &argField{Type: %#v, flags: %#x, BitField: BitField", name, f.Type, f.flags) + b := f.BitField + fmt.Fprintf(&buf, "{%d, %d }", b.Offs, b.Bits) + fmt.Fprintf(&buf, "}\n") + } + } + fmt.Fprint(&buf, ")\n\n\n") + + // Emit decoding table. + fmt.Fprintf(&buf, "var instFormats = [...]instFormat{\n") + for _, inst := range p.Insts { + m, v, dc := inst.Mask, inst.Value, inst.DontCare + fmt.Fprintf(&buf, "\t{ %s, %#x, %#x, %#x,", inst.Op, m, v, dc) + fmt.Fprintf(&buf, " // %s (%s)\n\t\t[8]*argField{", inst.Text, inst.Encoding) + for _, f := range inst.Fields { + fmt.Fprintf(&buf, "%s, ", argFieldName(f)) + } + fmt.Fprintf(&buf, "}},\n") + } + fmt.Fprint(&buf, "}\n\n") + + out, err := gofmt.Source(buf.Bytes()) + if err != nil { + log.Fatalf("gofmt error: %v", err) + fmt.Printf("%s", buf.Bytes()) + } else { + fmt.Printf("%s", out) + } +} diff --git a/s390x/s390xspec/spec.go b/s390x/s390xspec/spec.go new file mode 100644 index 00000000..1b24be85 --- /dev/null +++ b/s390x/s390xspec/spec.go @@ -0,0 +1,1067 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +// S390xspec reads the Principles of Operation PDF Manual +// to collect instruction encoding details and writes those details to standard output +// in CSV format. +// +// Usage: +// +// s390xspec z_Architecture_Principles_of_Operation.pdf > s390x.csv +// +// Each CSV line contains three fields: +// +// instruction +// The instruction heading, such as "BRANCH AND LINK". +// mnemonic +// The instruction mnemonics, such as "BAL R1,D2(X2,B2)". +// encoding +// The instruction encoding, a sequence of opcode and operands encoding in respective bit positions +// such as operand@bitposition each separated by | +// Ex: "45@0|R1@8|X2@12|B2@16|D2@20|" +// +// For more on the exact meaning of these fields, see the Principle of Operations IBM-Z Architecture PDF Manual. +package main + +import ( + "bufio" + "fmt" + "log" + "math" + "os" + "sort" + "strconv" + "strings" + + "rsc.io/pdf" +) + +type Inst struct { + Name string + Text string + Enc string + Flags string +} + +var stdout *bufio.Writer + +func main() { + log.SetFlags(0) + log.SetPrefix("s390xspec: ") + + if len(os.Args) != 2 { + fmt.Fprintf(os.Stderr, "usage: s390xspec file.pdf\n") + os.Exit(2) + } + + f, err := pdf.Open(os.Args[1]) + if err != nil { + log.Fatal(err) + } + + // Split across multiple columns and pages! + var all = []Inst{} + + // Scan document looking for instructions. + // Must find exactly the ones in the outline. + n := f.NumPage() + for pageNum := 1; pageNum <= n; pageNum++ { + page := f.Page(pageNum) + t1 := getPageContent(page) + if len(t1) > 0 && match(t1[0], "Helvetica-Bold", 13.98, "Instructions Arranged by Name") { + for n := pageNum; n < pageNum+24; n++ { + page := f.Page(n) + table := parsePage(n, page) + all = append(all, table...) + } + break + } else { + continue + } + } + stdout = bufio.NewWriter(os.Stdout) + for _, inst := range all { + if strings.Contains(inst.Name, "\x00I") { + r := rune(0x2190) + inst.Name = strings.Replace(inst.Name, "\x00I", string(r), -1) + } else if strings.Contains(inst.Name, "I\x00") { + r := rune(0x2192) + inst.Name = strings.Replace(inst.Name, "I\x00", string(r), -1) + } + fmt.Fprintf(stdout, "%q,%q,%q,%q\n", inst.Name, inst.Text, inst.Enc, inst.Flags) + } + stdout.Flush() + +} + +// getPageContent gets the page content of a single PDF page +func getPageContent(p pdf.Page) []pdf.Text { + var text []pdf.Text + + content := p.Content() + for _, t := range content.Text { + text = append(text, t) + } + + text = findWords(text) + return text +} + +// parsePage parses single PDF page and returns the instructions content +func parsePage(num int, p pdf.Page) []Inst { + var insts []Inst + text := getPageContent(p) + + for { + var heading, mnemonic, format string + // The float numbers below are the horizontal X-coordinate values to be parsed out of the Z-ISA PDF book. + for len(text) > 0 && !(match(text[0], "Helvetica-Narrow", 8, "") && (matchXCord(text[0], 73.9) || matchXCord(text[0], 55.9))) { + text = text[1:] + } + if len(text) == 0 { + break + } + heading = text[0].S + text = text[1:] + // The float numbers below are the horizontal X-coordinate values to be parsed out of the Z-ISA PDF book. + for !(matchXCord(text[0], 212.2) || matchXCord(text[0], 230.1) || matchXCord(text[0], 246.2) || matchXCord(text[0], 264.2)) { + heading += text[0].S + if match(text[0], "Wingdings3", 0, "") { + heading += text[1].S + text = text[1:] + } + text = text[1:] + } + if strings.Compare(heading, "DIAGNOSE") == 0 { + text = text[1:] + continue + } + heading, check, m := checkHeading(heading) + if check { + mnemonic = m + } else { + mnemonic = text[0].S + text = text[1:] + } + index := strings.Index(mnemonic, " ") + if index != -1 { + format = mnemonic[index+1:] + mnemonic = mnemonic[:index] + } else { + format = text[0].S + } + text = text[1:] + if strings.Compare(format, "SS") == 0 { + format += text[0].S + } + before, _, _ := strings.Cut(format, " ") + format = before + // The float numbers below are the horizontal X-coordinate values to be parsed out of the Z-ISA PDF book. + for len(text) > 0 && !(match(text[0], "Helvetica-Narrow", 8, "") && (matchXCord(text[0], 350.82) || matchXCord(text[0], 363.84) || matchXCord(text[0], 332.82) || matchXCord(text[0], 345.84))) { + if text[0].X > 405.48 { + break + } + text = text[1:] + } + flags := text[0].S + // The float numbers below are the horizontal X-coordinate values to be parsed out of the Z-ISA PDF book. + for len(text) > 0 && !(match(text[0], "Helvetica-Narrow", 8, "") && ((matchXCord(text[0], 481.7) && (!matchXCord(text[1], 496.1))) || matchXCord(text[0], 496.1) || (matchXCord(text[0], 499.6) && (!matchXCord(text[1], 514))) || (matchXCord(text[0], 514)))) { + text = text[1:] + } + if len(text) == 0 { + break + } + opcode := text[0].S + b1, b2, _ := strings.Cut(opcode, " ") + if matchXCord(text[0], 481.7) || matchXCord(text[0], 499.6) { + opcode = b2 + } else { + opcode = b1 + } + if strings.Compare(text[0].S, b1) == 0 { + text = text[2:] + } else { + text = text[1:] + } + mnemonic1, encoding := frameMnemonic(mnemonic, format, opcode) + for match(text[0], "Helvetica-Narrow", 5.1, "") { + text = text[1:] + } + if match(text[0], "Helvetica-Oblique", 9, "") { + text = text[2:] + insts = append(insts, Inst{heading, mnemonic1, encoding, flags}) + continue + } + if strings.HasPrefix(text[0].S, "(") { + y123 := text[0].Y + for text[0].Y == y123 && !matchXCord(text[0], 5.1) { + heading += text[0].S + text = text[1:] + } + } else if !(math.Abs(text[0].Y-text[1].Y) < 0.3) { + heading += " " + text[0].S + text = text[1:] + } + insts = append(insts, Inst{heading, mnemonic1, encoding, flags}) + if match(text[0], "Helvetica-Oblique", 9, "") { + break + } + } + return insts +} + +func checkHeading(heading string) (string, bool, string) { + substr := []string{"ALSI", "ALGSI", "CHRL", "CGHRL", "CUXTR", "IEXTR", "RXSBG", "RISBLG", "VERIM", "VPSOP"} + b := false + for _, s := range substr { + r1 := strings.Index(heading, s) + if r1 != -1 { + heading = heading[:r1-1] + b = true + return heading, b, s + } + } + return heading, b, "" +} + +func frameMnemonic(mnemonic, format, opcode string) (string, string) { + + var mn, enc string + + switch format { + case "E": + mn, enc = mnemonic_E(mnemonic, opcode) + case "I": + mn, enc = mnemonic_I(mnemonic, opcode) + case "IE": + mn, enc = mnemonic_IE(mnemonic, opcode) + case "MII": + mn, enc = mnemonic_MII(mnemonic, opcode) + case "RI-a", "RI-b", "RI-c": + mn, enc = mnemonic_RI(mnemonic, format, opcode) + case "RIE-a", "RIE-b", "RIE-c", "RIE-d", "RIE-e", "RIE-f", "RIE-g": + mn, enc = mnemonic_RIE(mnemonic, format, opcode) + case "RIL-a", "RIL-b", "RIL-c": + mn, enc = mnemonic_RIL(mnemonic, format, opcode) + case "RIS": + mn, enc = mnemonic_RIS(mnemonic, opcode) + case "RR": + mn, enc = mnemonic_RR(mnemonic, opcode) + case "RRD": + mn, enc = mnemonic_RRD(mnemonic, opcode) + case "RRE": + mn, enc = mnemonic_RRE(mnemonic, opcode) + case "RRF-a", "RRF-b", "RRF-c", "RRF-d", "RRF-e": + mn, enc = mnemonic_RRF(mnemonic, format, opcode) + case "RRS": + mn, enc = mnemonic_RRS(mnemonic, opcode) + case "RS-a", "RS-b": + mn, enc = mnemonic_RS(mnemonic, format, opcode) + case "RSI": + mn, enc = mnemonic_RSI(mnemonic, opcode) + case "RSL-a", "RSL-b": + mn, enc = mnemonic_RSL(mnemonic, format, opcode) + case "RSY-a", "RSY-b": + mn, enc = mnemonic_RSY(mnemonic, format, opcode) + case "RX-a", "RX-b": + mn, enc = mnemonic_RX(mnemonic, format, opcode) + case "RXE": + mn, enc = mnemonic_RXE(mnemonic, opcode) + case "RXF": + mn, enc = mnemonic_RXF(mnemonic, opcode) + case "RXY-a", "RXY-b": + mn, enc = mnemonic_RXY(mnemonic, format, opcode) + case "S": + mn, enc = mnemonic_S(mnemonic, opcode) + case "SI": + mn, enc = mnemonic_SI(mnemonic, opcode) + case "SIL": + mn, enc = mnemonic_SIL(mnemonic, opcode) + case "SIY": + mn, enc = mnemonic_SIY(mnemonic, opcode) + case "SMI": + mn, enc = mnemonic_SMI(mnemonic, opcode) + case "SS-a", "SS-b", "SS-c", "SS-d", "SS-e", "SS-f": + mn, enc = mnemonic_SS(mnemonic, format, opcode) + case "SSE": + mn, enc = mnemonic_SSE(mnemonic, opcode) + case "SSF": + mn, enc = mnemonic_SSF(mnemonic, opcode) + case "VRI-a", "VRI-b", "VRI-c", "VRI-d", "VRI-e", "VRI-f", "VRI-g", "VRI-h", "VRI-i": + mn, enc = mnemonic_VRI(mnemonic, format, opcode) + case "VRR-a", "VRR-b", "VRR-c", "VRR-d", "VRR-e", "VRR-f", "VRR-g", "VRR-h", "VRR-i", "VRR-j", "VRR-k": + mn, enc = mnemonic_VRR(mnemonic, format, opcode) + case "VRS-a", "VRS-b", "VRS-c", "VRS-d": + mn, enc = mnemonic_VRS(mnemonic, format, opcode) + case "VRV": + mn, enc = mnemonic_VRV(mnemonic, opcode) + case "VRX": + mn, enc = mnemonic_VRX(mnemonic, opcode) + case "VSI": + mn, enc = mnemonic_VSI(mnemonic, opcode) + default: + mn = mnemonic + } + return mn, enc +} + +func mnemonic_E(mnemonic, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|??@16" + return mnemonic, enc +} + +func mnemonic_I(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " I" + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|I@8|??@16" + return mnemonic, enc +} + +func mnemonic_IE(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " I1,I2" + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|//@16|I1@24|I2@28|??@32" + return mnemonic, enc +} + +func mnemonic_MII(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " M1,RI2,RI3" + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|M1@8|RI2@12|RI3@24|??@48" + return mnemonic, enc +} + +func mnemonic_RI(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:3], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "RI-a": + mnemonic += " R1,I2" + enc = str1 + "@0|R1@8|" + str2 + "@12|I2@16|??@32" + case "RI-b": + mnemonic += " R1,RI2" + enc = str1 + "@0|R1@8|" + str2 + "@12|RI2@16|??@32" + case "RI-c": + mnemonic += " M1,RI2" + enc = str1 + "@0|M1@8|" + str2 + "@12|RI2@16|??@32" + } + return mnemonic, enc +} + +func mnemonic_RIE(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "RIE-a": + mnemonic += " R1,I2,M3" + enc = str1 + "@0|R1@8|//@12|I2@16|M3@32|//@36|" + str2 + "@40|??@48" + case "RIE-b": + mnemonic += " R1,R2,M3,RI4" + enc = str1 + "@0|R1@8|R2@12|RI4@16|M3@32|//@36|" + str2 + "@40|??@48" + case "RIE-c": + mnemonic += " R1,I2,M3,RI4" + enc = str1 + "@0|R1@8|M3@12|RI4@16|I2@32|" + str2 + "@40|??@48" + case "RIE-d": + mnemonic += " R1,R3,I2" + enc = str1 + "@0|R1@8|R3@12|I2@16|//@32|" + str2 + "@40|??@48" + case "RIE-e": + mnemonic += " R1,R3,RI2" + enc = str1 + "@0|R1@8|R3@12|RI2@16|//@32|" + str2 + "@40|??@48" + case "RIE-f": + mnemonic += " R1,R2,I3,I4,I5" + enc = str1 + "@0|R1@8|R2@12|I3@16|I4@24|I5@32|" + str2 + "@40|??@48" + case "RIE-g": + mnemonic += " R1,I2,M3" + enc = str1 + "@0|R1@8|M3@12|I2@16|//@32|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_RIL(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "RIL-a": + mnemonic += " R1,I2" + enc = str1 + "@0|R1@8|" + str2 + "@12|I2@16|??@48" + case "RIL-b": + mnemonic += " R1,RI2" + enc = str1 + "@0|R1@8|" + str2 + "@12|RI2@16|??@48" + case "RIL-c": + mnemonic += " M1,RI2" + enc = str1 + "@0|M1@8|" + str2 + "@12|RI2@16|??@48" + } + return mnemonic, enc +} + +func mnemonic_RIS(mnemonic, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + mnemonic += " R1,I2,M3,D4(B4)" + enc = str1 + "@0|R1@8|M3@12|B4@16|D4@20|I2@32|" + str2 + "@40|??@48" + return mnemonic, enc +} + +func mnemonic_RR(mnemonic, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + switch mnemonic { + case "BCR": + mnemonic += " M1,R2" + enc = str + "@0|M1@8|R2@12|??@16" + case "SPM": + mnemonic += " R1" + enc = str + "@0|R1@8|//@12|??@16" + default: + mnemonic += " R1,R2" + enc = str + "@0|R1@8|R2@12|??@16" + } + return mnemonic, enc +} + +func mnemonic_RRD(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " R1,R3,R2" + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|R1@16|//@20|R3@24|R2@28|??@32" + return mnemonic, enc +} + +func mnemonic_RRE(mnemonic, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + switch mnemonic { + case "LZER", "LZDR", "LZXR", "EFPC", "EPAR", "EPAIR", "ESEA", "ESAIR", "ESAR", "ETND", "IAC", "IPM", "MSTA", "PTF", "SFASR", "SFPC", "SSAR", "SSAIR": + mnemonic += " R1" + enc = str + "@0|//@16|R1@24|//@28|??@32" + case "NNPA", "PALB", "PCC", "PCKMO": + enc = str + "@0|//@16|??@32" + default: + mnemonic += " R1,R2" + enc = str + "@0|//@16|R1@24|R2@28|??@32" + } + return mnemonic, enc +} + +func mnemonic_RRF(mnemonic, format, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + switch format { + case "RRF-a": + switch mnemonic { + case "SELR", "SELGR", "SELFHR", "IPTE", "AXTRA", "ADTRA", + "DDTRA", "DXTRA", "MDTRA", "MXTRA", "SDTRA", "SXTRA": + mnemonic += " R1,R2,R3,M4" + enc = str + "@0|R3@16|M4@20|R1@24|R2@28|??@32" + default: + mnemonic += " R1,R2,R3" + enc = str + "@0|R3@16|//@20|R1@24|R2@28|??@32" + } + case "RRF-b": + switch mnemonic { + case "CRDTE", "IDTE", "LPTEA", "RDP", "DIEBR", "DIDBR", + "QADTR", "QAXTR", "RRDTR", "RRXTR": + mnemonic += " R1,R3,R2,M4" + enc = str + "@0|R3@16|M4@20|R1@24|R2@28|??@32" + default: + mnemonic += " R1,R3,R2" + enc = str + "@0|R3@16|//@20|R1@24|R2@28|??@32" + } + case "RRF-c": + mnemonic += " R1,R2,M3" + enc = str + "@0|M3@16|//@20|R1@24|R2@28|??@32" + case "RRF-d": + mnemonic += " R1,R2,M4" + enc = str + "@0|//@16|M4@20|R1@24|R2@28|??@32" + case "RRF-e": + switch mnemonic { + case "CXFBRA", "CXFTR", "CDFBRA", "CDFTR", "CEFBRA", "CXGBRA", "CXGTRA", "CDGBRA", "CDGTRA", "CEGBRA", "CXLFBR", "CXLFTR", "CDLFBR", "CDLFTR", "CELFBR", + "CXLGBR", "CXLGTR", "CDLGBR", "CDLGTR", "CELGBR", "CFXBRA", "CGXBRA", "CFXTR", "CGXTRA", "CFDBRA", "CGDBRA", "CFDTR", "CGDTRA", "CFEBRA", "CGEBRA", + "CLFEBR", "CLFDBR", "CLFXBR", "CLGEBR", "CLGDBR", "CLGXBR", "CLFXTR", "CLFDTR", "CLGXTR", "CLGDTR", "FIEBRA", "FIDBRA", "FIXBRA", "FIDTR", "FIXTR", + "LDXBRA", "LEDBRA", "LEXBRA", "LEDTR", "LDXTR": + mnemonic += " R1,M3,R2,M4" + enc = str + "@0|M3@16|M4@20|R1@24|R2@28|??@32" + default: + mnemonic += " R1,M3,R2" + enc = str + "@0|M3@16|//@20|R1@24|R2@28|??@32" + } + } + return mnemonic, enc +} + +func mnemonic_RRS(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " R1,R2,M3,D4(B4)" + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + enc = str1 + "@0|R1@8|R2@12|B4@16|D4@20|M3@32|//@36|" + str2 + "@40|??@48" + return mnemonic, enc +} + +func mnemonic_RS(mnemonic, format, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + switch format { + case "RS-a": + switch mnemonic { + case "SLDA", "SLDL", "SLA", "SLL", "SRA", "SRDA", "SRDL", "SRL": + mnemonic += " R1,D2(B2)" + enc = str + "@0|R1@8|//@12|B2@16|D2@20|??@32" + default: + mnemonic += " R1,R3,D2(B2)" + enc = str + "@0|R1@8|R3@12|B2@16|D2@20|??@32" + } + case "RS-b": + mnemonic += " R1,M3,D2(B2)" + enc = str + "@0|R1@8|M3@12|B2@16|D2@20|??@32" + } + return mnemonic, enc +} + +func mnemonic_RSI(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " R1,R3,RI2" + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|R1@8|R3@12|RI2@16|??@32" + return mnemonic, enc +} + +func mnemonic_RSL(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "RSL-a": + mnemonic += " D1(L1,B1)" + enc = str1 + "@0|L1@8|//@12|B1@16|D1@20|//@32|" + str2 + "@40|??@48" + case "RSL-b": + mnemonic += " R1,D2(L2,B2),M3" + enc = str1 + "@0|L2@8|B2@16|D2@20|R1@32|M3@36|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_RSY(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "RSY-a": + mnemonic += " R1,R3,D2(B2)" + enc = str1 + "@0|R1@8|R3@12|B2@16|D2@20|" + str2 + "@40|??@48" + case "RSY-b": + switch mnemonic { + case "LOC", "LOCFH", "LOCG", "STOCFH", "STOC", "STOCG": + mnemonic += " R1,D2(B2),M3" + default: + mnemonic += " R1,M3,D2(B2)" + } + enc = str1 + "@0|R1@8|M3@12|B2@16|D2@20|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_RX(mnemonic, format, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseInt(opcode, 16, 16) + str := strconv.Itoa(int(val)) + switch format { + case "RX-a": + mnemonic += " R1,D2(X2,B2)" + enc = str + "@0|R1@8|X2@12|B2@16|D2@20|??@32" + case "RX-b": + mnemonic += " M1,D2(X2,B2)" + enc = str + "@0|M1@8|X2@12|B2@16|D2@20|??@32" + } + return mnemonic, enc +} + +func mnemonic_RXE(mnemonic, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch mnemonic { + case "LCBB": + mnemonic += " R1,D2(X2,B2),M3" + enc = str1 + "@0|R1@8|X2@12|B2@16|D2@20|M3@32|//@36|" + str2 + "@40|??@48" + default: + mnemonic += " R1,D2(X2,B2)" + enc = str1 + "@0|R1@8|X2@12|B2@16|D2@20|//@32|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_RXF(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " R1,R3,D2(X2,B2)" + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + enc = str1 + "@0|R3@8|X2@12|B2@16|D2@20|R1@32|//@36|" + str2 + "@40|??@48" + return mnemonic, enc +} + +func mnemonic_RXY(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "RXY-a": + mnemonic += " R1,D2(X2,B2)" + enc = str1 + "@0|R1@8|X2@12|B2@16|D2@20|" + str2 + "@40|??@48" + case "RXY-b": + mnemonic += " M1,D2(X2,B2)" + enc = str1 + "@0|M1@8|X2@12|B2@16|D2@20|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_S(mnemonic, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + switch mnemonic { + case "PTLB", "TEND", "XSCH", "CSCH", "HSCH", "IPK", "RCHP", "RSCH", "SAL", "SCHM": + enc = str + "@0|//@16|??@32" + default: + mnemonic += " D2(B2)" + enc = str + "@0|B2@16|D2@20|??@32" + } + return mnemonic, enc +} + +func mnemonic_SI(mnemonic, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + switch mnemonic { + case "TS", "SSM", "LPSW": + mnemonic += " D1(B1)" + default: + mnemonic += " D1(B1),I2" + } + enc = str + "@0|I2@8|B1@16|D1@20|??@32" + return mnemonic, enc +} + +func mnemonic_SIL(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " D1(B1),I2" + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|B1@16|D1@20|I2@32|??@48" + return mnemonic, enc +} + +func mnemonic_SIY(mnemonic, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch mnemonic { + case "LPSWEY": + mnemonic += " D1(B1)" + enc = str1 + "@0|//@8|B1@16|D1@20|" + str2 + "@40|??@48" + default: + mnemonic += " D1(B1),I2" + enc = str1 + "@0|I2@8|B1@16|D1@20|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_SMI(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " M1,RI2,D3(B3)" + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|M1@8|//@12|B3@16|D3@20|RI2@32|??@48" + return mnemonic, enc +} + +func mnemonic_SS(mnemonic, format, opcode string) (string, string) { + var enc string + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + switch format { + case "SS-a": + mnemonic += " D1(L1,B1),D2(B2)" + enc = str + "@0|L1@8|B1@16|D1@20|B2@32|D2@36|??@48" + case "SS-b": + mnemonic += " D1(L1,B1),D2(L2,B2)" + enc = str + "@0|L1@8|L2@12|B1@16|D1@20|B2@32|D2@36|??@48" + case "SS-c": + mnemonic += " D1(L1,B1),D2(B2),I3" + enc = str + "@0|L1@8|I3@12|B1@16|D1@20|B2@32|D2@36|??@48" + case "SS-d": + mnemonic += " D1(R1,B1),D2(B2),R3" + enc = str + "@0|R1@8|R3@12|B1@16|D1@20|B2@32|D2@36|??@48" + case "SS-e": + switch mnemonic { + case "LMD": + mnemonic += " R1,R3,D2(B2),D4(B4)" + default: + mnemonic += " R1,D2(B2),R3,D4(B4)" + } + enc = str + "@0|R1@8|R3@12|B2@16|D2@20|B4@32|D4@36|??@48" + case "SS-f": + mnemonic += " D1(B1),D2(L2,B2)" + enc = str + "@0|L2@8|B1@16|D1@20|B2@32|D2@36|??@48" + } + return mnemonic, enc + +} + +func mnemonic_SSE(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " D1(B1),D2(B2)" + val, _ := strconv.ParseUint(opcode, 16, 16) + str := strconv.Itoa(int(val)) + enc = str + "@0|B1@16|D1@20|B2@32|D2@36|??@48" + return mnemonic, enc +} + +func mnemonic_SSF(mnemonic, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch mnemonic { + case "LPD", "LPDG": + mnemonic += " R3,D1(B1),D2(B2)" + default: + mnemonic += " D1(B1),D2(B2),R3" + } + enc = str1 + "@0|R3@8|" + str2 + "@12|B1@16|D1@20|B2@32|D2@36|??@48" + return mnemonic, enc +} + +func mnemonic_VRI(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "VRI-a": + if strings.Contains(mnemonic, "VGBM") { // Check for M3 field + mnemonic += " V1,I2" + enc = str1 + "@0|V1@8|//@12|I2@16|//@32|RXB@36|" + str2 + "@40|??@48" + } else { + mnemonic += " V1,I2,M3" + enc = str1 + "@0|V1@8|//@12|I2@16|M3@32|RXB@36|" + str2 + "@40|??@48" + } + case "VRI-b": + mnemonic += " V1,I2,I3,M4" + enc = str1 + "@0|V1@8|//@12|I2@16|I3@24|M4@32|RXB@36|" + str2 + "@40|??@48" + case "VRI-c": + mnemonic += " V1,V3,I2,M4" + enc = str1 + "@0|V1@8|V3@12|I2@16|M4@32|RXB@36|" + str2 + "@40|??@48" + case "VRI-d": + if strings.Contains(mnemonic, "VERIM") { // Check for M5 field + mnemonic += " V1,V2,V3,I4,M5" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|I4@24|M5@32|RXB@36|" + str2 + "@40|??@48" + } else { + mnemonic += " V1,V2,V3,I4" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|I4@24|//@32|RXB@36|" + str2 + "@40|??@48" + } + case "VRI-e": + mnemonic += " V1,V2,I3,M4,M5" + enc = str1 + "@0|V1@8|V2@12|I3@16|M5@28|M4@32|RXB@36|" + str2 + "@40|??@48" + case "VRI-f": + mnemonic += " V1,V2,V3,I4,M5" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|M5@24|I4@28|RXB@36|" + str2 + "@40|??@48" + case "VRI-g": + mnemonic += " V1,V2,I3,I4,M5" + enc = str1 + "@0|V1@8|V2@12|I4@16|M5@24|I3@28|RXB@36|" + str2 + "@40|??@48" + case "VRI-h": + mnemonic += " V1,I2,I3" + enc = str1 + "@0|V1@8|//@12|I2@16|I3@32|RXB@36|" + str2 + "@40|??@48" + case "VRI-i": + mnemonic += " V1,R2,I3,M4" + enc = str1 + "@0|V1@8|R2@12|//@16|M4@24|I3@28|RXB@36|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_VRR(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "VRR-a": + switch mnemonic { + case "VLR", "VTM": // V1,V2 + mnemonic += " V1,V2" + enc = str1 + "@0|V1@8|V2@12|//@16|RXB@36|" + str2 + "@40|??@48" + + case "VSEG", "VUPH", "VUPLH", "VUPL", "VUPLL", "VCLZ", "VCTZ", "VEC", "VECL", "VLC", "VLP", "VPOPCT": // V1,V2,M3 + mnemonic += " V1,V2,M3" + enc = str1 + "@0|V1@8|V2@12|//@16|M3@32|RXB@36|" + str2 + "@40|??@48" + + case "VISTR": // V1,V2,M3,M5 + mnemonic += " V1,V2,M3,M5" + enc = str1 + "@0|V1@8|V2@12|//@16|M5@24|//@28|M3@32|RXB@36|" + str2 + "@40|??@48" + + case "WFC", "WFK", "VFLL", "VFSQ", "VCLFNH", "VCLFNL", "VCFN", "VCNF": // V1,V2,M3,M4 + mnemonic += " V1,V2,M3,M4" + enc = str1 + "@0|V1@8|V2@12|//@16|M4@28|M3@32|RXB@36|" + str2 + "@40|??@48" + + case "VCFPS", "VCDG", "VCDLG", "VCGD", "VCFPL", "VCSFP", "VCLFP", "VCLGD", "VFI", "VFLR", "VFPSO": // V1,V2,M3,M4,M5 + mnemonic += " V1,V2,M3,M4,M5" + enc = str1 + "@0|V1@8|V2@12|//@16|M5@24|M4@28|M3@32|RXB@36|" + str2 + "@40|??@48" + } + case "VRR-b": + switch mnemonic { + case "VSCSHP": + mnemonic += " V1,V2,V3" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|RXB@36|" + str2 + "@40|??@48" + default: + mnemonic += " V1,V2,V3,M4,M5" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|M5@24|//@28|M4@32|RXB@36|" + str2 + "@40|??@48" + } + case "VRR-c": + switch mnemonic { + case "VFA", "VFD", "VFM", "VFS", "VCRNF": // V1,V2,V3,M4,M5 + mnemonic += " V1,V2,V3,M4,M5" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|M5@28|M4@32|RXB@36|" + str2 + "@40|??@48" + + case "VFCE", "VFCH", "VFCHE", "VFMAX", "VFMIN": // V1,V2,V3,M4,M5,M6 + mnemonic += " V1,V2,V3,M4,M5,M6" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|M6@24|M5@28|M4@32|RXB@36|" + str2 + "@40|??@48" + + case "VBPERM", "VN", "VNC", "VCKSM", "VX", "VNN", "VNO", "VNX", + "VO", "VOC", "VSL", "VSLB", "VSRA", "VSRAB", "VSRL", "VSRLB": // V1,V2,V3 + mnemonic += " V1,V2,V3" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|RXB@36|" + str2 + "@40|??@48" + default: // V1,V2,V3,M4 + mnemonic += " V1,V2,V3,M4" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|M4@32|RXB@36|" + str2 + "@40|??@48" + } + case "VRR-d": + switch mnemonic { + case "VMSL", "VSTRC", "VSTRS": // V1,V2,V3,V4,M5,M6 + mnemonic += " V1,V2,V3,V4,M5,M6" + enc = str1 + "@0|V1@8|V2@12|V3@16|M5@20|M6@24|//@28|V4@32|RXB@36|" + str2 + "@40|??@48" + default: + mnemonic += " V1,V2,V3,V4,M5" + enc = str1 + "@0|V1@8|V2@12|V3@16|M5@20|//@24|V4@32|RXB@36|" + str2 + "@40|??@48" + } + case "VRR-e": + switch mnemonic { + case "VPERM", "VSEL": + mnemonic += " V1,V2,V3,V4" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|V4@32|RXB@36|" + str2 + "@40|??@48" + default: + mnemonic += " V1,V2,V3,V4,M5,M6" + enc = str1 + "@0|V1@8|V2@12|V3@16|M6@20|//@24|M5@28|V4@32|RXB@36|" + str2 + "@40|??@48" + } + case "VRR-f": + mnemonic += " V1,R2,R3" + enc = str1 + "@0|V1@8|R2@12|R3@16|//@20|RXB@36|" + str2 + "@40|??@48" + case "VRR-g": + mnemonic += " V1" + enc = str1 + "@0|//@8|V1@12|//@16|RXB@36|" + str2 + "@40|??@48" + case "VRR-h": + mnemonic += " V1,V2,M3" + enc = str1 + "@0|//@8|V1@12|V2@16|//@20|M3@24|//@28|RXB@36|" + str2 + "@40|??@48" + case "VRR-i": + mnemonic += " R1,V2,M3,M4" + enc = str1 + "@0|R1@8|V2@12|//@16|M3@24|M4@28|//@32|RXB@36|" + str2 + "@40|??@48" + case "VRR-j": + mnemonic += " V1,V2,V3,M4" + enc = str1 + "@0|V1@8|V2@12|V3@16|//@20|M4@24|//@28|RXB@36|" + str2 + "@40|??@48" + case "VRR-k": + mnemonic += " V1,V2,M3" + enc = str1 + "@0|V1@8|V2@12|//@16|M3@24|//@28|RXB@36|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_VRS(mnemonic, format, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + switch format { + case "VRS-a": + mnemonic += " V1,V3,D2(B2),M4" + enc = str1 + "@0|V1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|" + str2 + "@40|??@48" + case "VRS-b": + if strings.Contains(mnemonic, "VLVG") { + mnemonic += " V1,R3,D2(B2),M4" + enc = str1 + "@0|V1@8|R3@12|B2@16|D2@20|M4@32|RXB@36|" + str2 + "@40|??@48" + } else { + mnemonic += " V1,R3,D2(B2)" + enc = str1 + "@0|V1@8|R3@12|B2@16|D2@20|//@32|RXB@36|" + str2 + "@40|??@48" + } + case "VRS-c": + mnemonic += " R1,V3,D2(B2),M4" + enc = str1 + "@0|R1@8|V3@12|B2@16|D2@20|M4@32|RXB@36|" + str2 + "@40|??@48" + case "VRS-d": + mnemonic += " V1,R3,D2(B2)" + enc = str1 + "@0|//@8|R3@12|B2@16|D2@20|V1@32|RXB@36|" + str2 + "@40|??@48" + } + return mnemonic, enc +} + +func mnemonic_VRV(mnemonic, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + mnemonic += " V1,D2(V2,B2),M3" + enc = str1 + "@0|V1@8|V2@12|B2@16|D2@20|M3@32|RXB@36|" + str2 + "@40|??@48" + return mnemonic, enc +} + +func mnemonic_VRX(mnemonic, opcode string) (string, string) { + var enc string + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + mnemonic += " V1,D2(X2,B2),M3" + enc = str1 + "@0|V1@8|X2@12|B2@16|D2@20|M3@32|RXB@36|" + str2 + "@40|??@48" + return mnemonic, enc +} + +func mnemonic_VSI(mnemonic, opcode string) (string, string) { + var enc string + mnemonic += " V1,D2(B2),I3" + val1, _ := strconv.ParseUint(opcode[:2], 16, 16) + str1 := strconv.Itoa(int(val1)) + val2, _ := strconv.ParseUint(opcode[2:], 16, 16) + str2 := strconv.Itoa(int(val2)) + enc = str1 + "@0|I3@8|B2@16|D2@20|V1@32|RXB@36|" + str2 + "@40|??@48" + return mnemonic, enc +} + +func matchXCord(t pdf.Text, Xcord float64) bool { + return math.Abs(t.X-Xcord) < 0.9 +} + +func match(t pdf.Text, font string, size float64, substr string) bool { + return t.Font == font && (size == 0 || math.Abs(t.FontSize-size) < 0.2) && strings.Contains(t.S, substr) +} + +func findWords(chars []pdf.Text) (words []pdf.Text) { + // Sort by Y coordinate and normalize. + const nudge = 1.5 + sort.Sort(pdf.TextVertical(chars)) + old := -100000.0 + for i, c := range chars { + if c.Y != old && math.Abs(old-c.Y) < nudge { + chars[i].Y = old + } else { + old = c.Y + } + } + + // Sort by Y coordinate, breaking ties with X. + // This will bring letters in a single word together. + sort.Sort(pdf.TextVertical(chars)) + + // Loop over chars. + for i := 0; i < len(chars); { + // Find all chars on line. + j := i + 1 + for j < len(chars) && chars[j].Y == chars[i].Y { + j++ + } + var end float64 + // Split line into words (really, phrases). + for k := i; k < j; { + ck := &chars[k] + s := ck.S + end = ck.X + ck.W + charSpace := ck.FontSize / 6 + wordSpace := ck.FontSize * 2 / 3 + l := k + 1 + for l < j { + // Grow word. + cl := &chars[l] + if sameFont(cl.Font, ck.Font) && math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+charSpace { + s += cl.S + end = cl.X + cl.W + l++ + continue + } + // Add space to phrase before next word. + if sameFont(cl.Font, ck.Font) && math.Abs(cl.FontSize-ck.FontSize) < 0.1 && cl.X <= end+wordSpace { + s += " " + cl.S + end = cl.X + cl.W + l++ + continue + } + break + } + f := ck.Font + f = strings.TrimSuffix(f, ",Italic") + f = strings.TrimSuffix(f, "-Italic") + words = append(words, pdf.Text{ + Font: f, + FontSize: ck.FontSize, + X: ck.X, + Y: ck.Y, + W: end - ck.X, + S: s, + }) + k = l + } + i = j + } + return words +} + +func sameFont(f1, f2 string) bool { + f1 = strings.TrimSuffix(f1, ",Italic") + f1 = strings.TrimSuffix(f1, "-Italic") + f2 = strings.TrimSuffix(f1, ",Italic") + f2 = strings.TrimSuffix(f1, "-Italic") + return strings.TrimSuffix(f1, ",Italic") == strings.TrimSuffix(f2, ",Italic") || f1 == "Symbol" || f2 == "Symbol" || f1 == "TimesNewRoman" || f2 == "TimesNewRoman" +} diff --git a/s390x/s390xutil/hack.h b/s390x/s390xutil/hack.h new file mode 100644 index 00000000..22ef049f --- /dev/null +++ b/s390x/s390xutil/hack.h @@ -0,0 +1,56 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. +// +// This file requires gcc and binutils with -march=z16 support. +// s390xutil runs a series of commands like: +// go run map.go -fmt=asm ../s390x.csv > asm.S +// /usr/bin/gcc -c asm.S -march=z16 +// /usr/bin/objdump -d asm.o +// to create the file decode_generated.txt used to verify the disassembler. +// +// Note, the Go disassembler is not expected to support every extended +// mnemonic, but it should support those which frequently show up in object +// files compiled by the Go toolchain. + + +#define R1 8 +#define R2 0 +#define R3 0 + +#define X2 2 + +#define L1 4 +#define L2 4 + +#define B1 2 +#define B2 1 +#define B3 6 +#define B4 8 + +#define D1 6 +#define D2 11 +#define D3 182 +#define D4 205 + +#define V1 18 +#define V2 3 +#define V3 5 +#define V4 8 + +#define I 124 +#define I1 12 +#define I2 8 +#define I3 9 +#define I4 105 +#define I5 18 + +#define RI2 0 +#define RI3 294 +#define RI4 -168 + +#define M1 7 +#define M3 3 +#define M4 1 +#define M5 9 +#define M6 11 diff --git a/s390x/s390xutil/util.go b/s390x/s390xutil/util.go new file mode 100644 index 00000000..003ce5df --- /dev/null +++ b/s390x/s390xutil/util.go @@ -0,0 +1,90 @@ +// Copyright 2024 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +//go:build ignore + +// Generate interesting test cases from s390x objdump via +// go run util.go +// +// This requires "/usr/bin/gcc" and "objdump" be in the PATH this command is run. +// +// These tools can be acquired from the IBM advance toolchain for amd64 hosts too. + +package main + +import ( + "bufio" + "fmt" + "io" + "os" + "os/exec" + "regexp" + "strconv" + "strings" +) + +// Emit a test file using the generator called name.txt. This requires +// a GCC toolchain which supports -march=z16. +func genOutput(name, tcPfx string, generator func(io.Writer)) { + // Generate object code from gcc + cmd := exec.Command(tcPfx+"gcc", "-c", "-march=z16", "-x", "assembler-with-cpp", "-o", name+".o", "-") + input, _ := cmd.StdinPipe() + cmd.Stderr = os.Stderr + go func() { + defer input.Close() + generator(input.(io.Writer)) + }() + if cmd.Run() != nil { + fmt.Printf("Failed running gcc for: %s\n", name) + return + } + defer os.Remove(name + ".o") + cmd = exec.Command(tcPfx+"objdump", "-d", name+".o") + + // Run objdump and parse output into test format + output, _ := cmd.StdoutPipe() + defer output.Close() + scanner := bufio.NewScanner(output) + spacere := regexp.MustCompile("[[:space:]]+") + outf, _ := os.Create(name + ".txt") + defer outf.Close() + if cmd.Start() != nil { + fmt.Printf("Failed running objdump for: %s\n", name) + return + } + + for scanner.Scan() { + ln := spacere.Split(scanner.Text(), -1) + var cnt int16 + if len(ln) >= 5 { + v, _ := strconv.ParseInt(ln[2], 16, 16) + if (v >> 6 & 0x3) == 0 { + cnt = 2 + } else if v>>6&0x3 == 1 || v>>6&0x3 == 2 { + cnt = 4 + } else { + cnt = 6 + } + opc := strings.Join(ln[2:cnt+2], "") + dec := strings.Join(ln[cnt+2:], " ") + fmt.Fprintf(outf, "%12s|\tgnu\t%-18s\n", opc, dec) + } + } + cmd.Wait() +} + +// Generate representative instructions for all[1] instructions in s390x.csv. +// +// [1] See hack.h for a few minor, exceptional workarounds. +func emitGenerated(out io.Writer) { + cmd := exec.Command("go", "run", "../s390xmap/map.go", "-fmt=asm", "../s390x.csv") + cmdout, _ := cmd.Output() + out.Write(cmdout) +} + +// Produce generated test outputs. This should be run every so often with +// new versions of objdump to ensure we stay up to date. +func main() { + genOutput("decode_generated", "/usr/bin/", emitGenerated) +} diff --git a/x86/x86asm/decode.go b/x86/x86asm/decode.go index 8c984970..059b73d3 100644 --- a/x86/x86asm/decode.go +++ b/x86/x86asm/decode.go @@ -1550,7 +1550,7 @@ var addr16 = [8]Mem{ {Base: BX}, } -// baseReg returns the base register for a given register size in bits. +// baseRegForBits returns the base register for a given register size in bits. func baseRegForBits(bits int) Reg { switch bits { case 8: diff --git a/x86/x86asm/ext_test.go b/x86/x86asm/ext_test.go index e63f1138..2e31dd30 100644 --- a/x86/x86asm/ext_test.go +++ b/x86/x86asm/ext_test.go @@ -653,7 +653,7 @@ func enum8bit(try func([]byte)) { } } -// enum8bit generates all possible 2-byte sequences, followed by distinctive padding. +// enum16bit generates all possible 2-byte sequences, followed by distinctive padding. func enum16bit(try func([]byte)) { for i := 0; i < 1<<16; i++ { try([]byte{byte(i), byte(i >> 8), 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88}) diff --git a/x86/x86asm/gnu.go b/x86/x86asm/gnu.go index 75cff72b..864f32c1 100644 --- a/x86/x86asm/gnu.go +++ b/x86/x86asm/gnu.go @@ -10,7 +10,7 @@ import ( ) // GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. -// This general form is often called ``AT&T syntax'' as a reference to AT&T System V Unix. +// This general form is often called “AT&T syntax” as a reference to AT&T System V Unix. func GNUSyntax(inst Inst, pc uint64, symname SymLookup) string { // Rewrite instruction to mimic GNU peculiarities. // Note that inst has been passed by value and contains @@ -667,12 +667,14 @@ func gnuArg(inst *Inst, pc uint64, symname SymLookup, x Arg, usedPrefixes *bool) } } case Imm: - if s, base := symname(uint64(x)); s != "" { - suffix := "" - if uint64(x) != base { - suffix = fmt.Sprintf("%+d", uint64(x)-base) + if (inst.Op == MOV || inst.Op == PUSH) && inst.DataSize == 32 { // See comment in plan9x.go. + if s, base := symname(uint64(x)); s != "" { + suffix := "" + if uint64(x) != base { + suffix = fmt.Sprintf("%+d", uint64(x)-base) + } + return fmt.Sprintf("$%s%s", s, suffix) } - return fmt.Sprintf("$%s%s", s, suffix) } if inst.Mode == 32 { return fmt.Sprintf("$%#x", uint32(x)) diff --git a/x86/x86asm/inst.go b/x86/x86asm/inst.go index 4632b506..e98f1a84 100644 --- a/x86/x86asm/inst.go +++ b/x86/x86asm/inst.go @@ -144,7 +144,7 @@ type Arg interface { // the interface value instead of requiring an allocation. // A Reg is a single register. -// The zero Reg value has no name but indicates ``no register.'' +// The zero Reg value has no name but indicates “no register.” type Reg uint8 const ( diff --git a/x86/x86asm/intel.go b/x86/x86asm/intel.go index 472eabda..a0622998 100644 --- a/x86/x86asm/intel.go +++ b/x86/x86asm/intel.go @@ -341,12 +341,14 @@ func IntelSyntax(inst Inst, pc uint64, symname SymLookup) string { func intelArg(inst *Inst, pc uint64, symname SymLookup, arg Arg) string { switch a := arg.(type) { case Imm: - if s, base := symname(uint64(a)); s != "" { - suffix := "" - if uint64(a) != base { - suffix = fmt.Sprintf("%+d", uint64(a)-base) + if (inst.Op == MOV || inst.Op == PUSH) && inst.DataSize == 32 { // See comment in plan9x.go. + if s, base := symname(uint64(a)); s != "" { + suffix := "" + if uint64(a) != base { + suffix = fmt.Sprintf("%+d", uint64(a)-base) + } + return fmt.Sprintf("$%s%s", s, suffix) } - return fmt.Sprintf("$%s%s", s, suffix) } if inst.Mode == 32 { return fmt.Sprintf("%#x", uint32(a)) diff --git a/x86/x86asm/plan9x.go b/x86/x86asm/plan9x.go index de417946..e82349ce 100644 --- a/x86/x86asm/plan9x.go +++ b/x86/x86asm/plan9x.go @@ -83,6 +83,12 @@ func GoSyntax(inst Inst, pc uint64, symname SymLookup) string { } } + if inst.Op == CMP { + // Use reads-left-to-right ordering for comparisons. + // See issue 60920. + args[0], args[1] = args[1], args[0] + } + if args != nil { op += " " + strings.Join(args, ", ") } @@ -110,12 +116,23 @@ func plan9Arg(inst *Inst, pc uint64, symname func(uint64) (string, uint64), arg return fmt.Sprintf("%#x", addr) case Imm: - if s, base := symname(uint64(a)); s != "" { - suffix := "" - if uint64(a) != base { - suffix = fmt.Sprintf("%+d", uint64(a)-base) + if (inst.Op == MOV || inst.Op == PUSH) && inst.DataSize == 32 { + // Only try to convert an immediate to a symbol in certain + // special circumstances. See issue 72942. + // + // On 64-bit, symbol addresses always hit the Mem case below. + // Particularly, we use LEAQ to materialize the address of + // a global or function. + // + // On 32-bit, we sometimes use MOVL. Still try to symbolize + // those immediates. + if s, base := symname(uint64(a)); s != "" { + suffix := "" + if uint64(a) != base { + suffix = fmt.Sprintf("%+d", uint64(a)-base) + } + return fmt.Sprintf("$%s%s(SB)", s, suffix) } - return fmt.Sprintf("$%s%s(SB)", s, suffix) } if inst.Mode == 32 { return fmt.Sprintf("$%#x", uint32(a)) diff --git a/x86/x86asm/tables.go b/x86/x86asm/tables.go index 6f57c70b..9710bbd8 100644 --- a/x86/x86asm/tables.go +++ b/x86/x86asm/tables.go @@ -1,4 +1,4 @@ -// Code generated by x86map -fmt=decoder x86.csv DO NOT EDIT. +// Code generated by x86map -fmt=decoder ../x86.csv DO NOT EDIT. package x86asm diff --git a/x86/x86asm/testdata/decode.txt b/x86/x86asm/testdata/decode.txt index cbd536a8..af840c2f 100644 --- a/x86/x86asm/testdata/decode.txt +++ b/x86/x86asm/testdata/decode.txt @@ -2125,35 +2125,35 @@ 37|11223344556677885f5f5f5f5f5f5f 64 intel error: unrecognized instruction 37|11223344556677885f5f5f5f5f5f5f 64 plan9 error: unrecognized instruction 3811|223344556677885f5f5f5f5f5f5f 32 intel cmp byte ptr [ecx], dl -3811|223344556677885f5f5f5f5f5f5f 32 plan9 CMPB DL, 0(CX) +3811|223344556677885f5f5f5f5f5f5f 32 plan9 CMPB 0(CX), DL 3811|223344556677885f5f5f5f5f5f5f 64 gnu cmp %dl,(%rcx) 3811|223344556677885f5f5f5f5f5f5f 64 intel cmp byte ptr [rcx], dl -3811|223344556677885f5f5f5f5f5f5f 64 plan9 CMPB DL, 0(CX) +3811|223344556677885f5f5f5f5f5f5f 64 plan9 CMPB 0(CX), DL 3911|223344556677885f5f5f5f5f5f5f 32 intel cmp dword ptr [ecx], edx -3911|223344556677885f5f5f5f5f5f5f 32 plan9 CMPL DX, 0(CX) +3911|223344556677885f5f5f5f5f5f5f 32 plan9 CMPL 0(CX), DX 3911|223344556677885f5f5f5f5f5f5f 64 gnu cmp %edx,(%rcx) 3911|223344556677885f5f5f5f5f5f5f 64 intel cmp dword ptr [rcx], edx -3911|223344556677885f5f5f5f5f5f5f 64 plan9 CMPL DX, 0(CX) +3911|223344556677885f5f5f5f5f5f5f 64 plan9 CMPL 0(CX), DX 3a11|223344556677885f5f5f5f5f5f5f 32 intel cmp dl, byte ptr [ecx] -3a11|223344556677885f5f5f5f5f5f5f 32 plan9 CMPB 0(CX), DL +3a11|223344556677885f5f5f5f5f5f5f 32 plan9 CMPB DL, 0(CX) 3a11|223344556677885f5f5f5f5f5f5f 64 gnu cmp (%rcx),%dl 3a11|223344556677885f5f5f5f5f5f5f 64 intel cmp dl, byte ptr [rcx] -3a11|223344556677885f5f5f5f5f5f5f 64 plan9 CMPB 0(CX), DL +3a11|223344556677885f5f5f5f5f5f5f 64 plan9 CMPB DL, 0(CX) 3b11|223344556677885f5f5f5f5f5f5f 32 intel cmp edx, dword ptr [ecx] -3b11|223344556677885f5f5f5f5f5f5f 32 plan9 CMPL 0(CX), DX +3b11|223344556677885f5f5f5f5f5f5f 32 plan9 CMPL DX, 0(CX) 3b11|223344556677885f5f5f5f5f5f5f 64 gnu cmp (%rcx),%edx 3b11|223344556677885f5f5f5f5f5f5f 64 intel cmp edx, dword ptr [rcx] -3b11|223344556677885f5f5f5f5f5f5f 64 plan9 CMPL 0(CX), DX +3b11|223344556677885f5f5f5f5f5f5f 64 plan9 CMPL DX, 0(CX) 3c11|223344556677885f5f5f5f5f5f5f 32 intel cmp al, 0x11 -3c11|223344556677885f5f5f5f5f5f5f 32 plan9 CMPL $0x11, AL +3c11|223344556677885f5f5f5f5f5f5f 32 plan9 CMPL AL, $0x11 3c11|223344556677885f5f5f5f5f5f5f 64 gnu cmp $0x11,%al 3c11|223344556677885f5f5f5f5f5f5f 64 intel cmp al, 0x11 -3c11|223344556677885f5f5f5f5f5f5f 64 plan9 CMPL $0x11, AL +3c11|223344556677885f5f5f5f5f5f5f 64 plan9 CMPL AL, $0x11 3d11223344|556677885f5f5f5f5f5f5f 32 intel cmp eax, 0x44332211 -3d11223344|556677885f5f5f5f5f5f5f 32 plan9 CMPL $0x44332211, AX +3d11223344|556677885f5f5f5f5f5f5f 32 plan9 CMPL AX, $0x44332211 3d11223344|556677885f5f5f5f5f5f5f 64 gnu cmp $0x44332211,%eax 3d11223344|556677885f5f5f5f5f5f5f 64 intel cmp eax, 0x44332211 -3d11223344|556677885f5f5f5f5f5f5f 64 plan9 CMPL $0x44332211, AX +3d11223344|556677885f5f5f5f5f5f5f 64 plan9 CMPL AX, $0x44332211 3e67e011|223344556677885f5f5f5f5f 32 intel addr16 loopne .+0x11 3e67e011|223344556677885f5f5f5f5f 32 plan9 LOOPNE .+17 3e67e011|223344556677885f5f5f5f5f 64 gnu loopne,pt .+0x11 @@ -2482,13 +2482,13 @@ 483511223344|556677885f5f5f5f5f5f 64 plan9 XORQ $0x44332211, AX 483911|223344556677885f5f5f5f5f5f 64 gnu cmp %rdx,(%rcx) 483911|223344556677885f5f5f5f5f5f 64 intel cmp qword ptr [rcx], rdx -483911|223344556677885f5f5f5f5f5f 64 plan9 CMPQ DX, 0(CX) +483911|223344556677885f5f5f5f5f5f 64 plan9 CMPQ 0(CX), DX 483b11|223344556677885f5f5f5f5f5f 64 gnu cmp (%rcx),%rdx 483b11|223344556677885f5f5f5f5f5f 64 intel cmp rdx, qword ptr [rcx] -483b11|223344556677885f5f5f5f5f5f 64 plan9 CMPQ 0(CX), DX +483b11|223344556677885f5f5f5f5f5f 64 plan9 CMPQ DX, 0(CX) 483d11223344|556677885f5f5f5f5f5f 64 gnu cmp $0x44332211,%rax 483d11223344|556677885f5f5f5f5f5f 64 intel cmp rax, 0x44332211 -483d11223344|556677885f5f5f5f5f5f 64 plan9 CMPQ $0x44332211, AX +483d11223344|556677885f5f5f5f5f5f 64 plan9 CMPQ AX, $0x44332211 4850|11223344556677885f5f5f5f5f5f 64 gnu push %rax 4850|11223344556677885f5f5f5f5f5f 64 intel push rax 4850|11223344556677885f5f5f5f5f5f 64 plan9 PUSHQ AX @@ -2536,7 +2536,7 @@ 48813011223344|556677885f5f5f5f5f 64 plan9 XORQ $0x44332211, 0(AX) 48813811223344|556677885f5f5f5f5f 64 gnu cmpq $0x44332211,(%rax) 48813811223344|556677885f5f5f5f5f 64 intel cmp qword ptr [rax], 0x44332211 -48813811223344|556677885f5f5f5f5f 64 plan9 CMPQ $0x44332211, 0(AX) +48813811223344|556677885f5f5f5f5f 64 plan9 CMPQ 0(AX), $0x44332211 48830011|223344556677885f5f5f5f5f 64 gnu addq $0x11,(%rax) 48830011|223344556677885f5f5f5f5f 64 intel add qword ptr [rax], 0x11 48830011|223344556677885f5f5f5f5f 64 plan9 ADDQ $0x11, 0(AX) @@ -2560,7 +2560,7 @@ 48833011|223344556677885f5f5f5f5f 64 plan9 XORQ $0x11, 0(AX) 48833811|223344556677885f5f5f5f5f 64 gnu cmpq $0x11,(%rax) 48833811|223344556677885f5f5f5f5f 64 intel cmp qword ptr [rax], 0x11 -48833811|223344556677885f5f5f5f5f 64 plan9 CMPQ $0x11, 0(AX) +48833811|223344556677885f5f5f5f5f 64 plan9 CMPQ 0(AX), $0x11 488511|223344556677885f5f5f5f5f5f 64 gnu test %rdx,(%rcx) 488511|223344556677885f5f5f5f5f5f 64 intel test qword ptr [rcx], rdx 488511|223344556677885f5f5f5f5f5f 64 plan9 TESTQ DX, 0(CX) @@ -4233,20 +4233,20 @@ 66351122|3344556677885f5f5f5f5f5f 64 intel xor ax, 0x2211 66351122|3344556677885f5f5f5f5f5f 64 plan9 XORW $0x2211, AX 663911|223344556677885f5f5f5f5f5f 32 intel cmp word ptr [ecx], dx -663911|223344556677885f5f5f5f5f5f 32 plan9 CMPW DX, 0(CX) +663911|223344556677885f5f5f5f5f5f 32 plan9 CMPW 0(CX), DX 663911|223344556677885f5f5f5f5f5f 64 gnu cmp %dx,(%rcx) 663911|223344556677885f5f5f5f5f5f 64 intel cmp word ptr [rcx], dx -663911|223344556677885f5f5f5f5f5f 64 plan9 CMPW DX, 0(CX) +663911|223344556677885f5f5f5f5f5f 64 plan9 CMPW 0(CX), DX 663b11|223344556677885f5f5f5f5f5f 32 intel cmp dx, word ptr [ecx] -663b11|223344556677885f5f5f5f5f5f 32 plan9 CMPW 0(CX), DX +663b11|223344556677885f5f5f5f5f5f 32 plan9 CMPW DX, 0(CX) 663b11|223344556677885f5f5f5f5f5f 64 gnu cmp (%rcx),%dx 663b11|223344556677885f5f5f5f5f5f 64 intel cmp dx, word ptr [rcx] -663b11|223344556677885f5f5f5f5f5f 64 plan9 CMPW 0(CX), DX +663b11|223344556677885f5f5f5f5f5f 64 plan9 CMPW DX, 0(CX) 663d1122|3344556677885f5f5f5f5f5f 32 intel cmp ax, 0x2211 -663d1122|3344556677885f5f5f5f5f5f 32 plan9 CMPW $0x2211, AX +663d1122|3344556677885f5f5f5f5f5f 32 plan9 CMPW AX, $0x2211 663d1122|3344556677885f5f5f5f5f5f 64 gnu cmp $0x2211,%ax 663d1122|3344556677885f5f5f5f5f5f 64 intel cmp ax, 0x2211 -663d1122|3344556677885f5f5f5f5f5f 64 plan9 CMPW $0x2211, AX +663d1122|3344556677885f5f5f5f5f5f 64 plan9 CMPW AX, $0x2211 6640|11223344556677885f5f5f5f5f5f 32 intel inc ax 6640|11223344556677885f5f5f5f5f5f 32 plan9 INCW AX 66480f3a161122|3344556677885f5f5f 64 gnu pextrq $0x22,%xmm2,(%rcx) @@ -4343,10 +4343,10 @@ 6681301122|3344556677885f5f5f5f5f 64 intel xor word ptr [rax], 0x2211 6681301122|3344556677885f5f5f5f5f 64 plan9 XORW $0x2211, 0(AX) 6681381122|3344556677885f5f5f5f5f 32 intel cmp word ptr [eax], 0x2211 -6681381122|3344556677885f5f5f5f5f 32 plan9 CMPW $0x2211, 0(AX) +6681381122|3344556677885f5f5f5f5f 32 plan9 CMPW 0(AX), $0x2211 6681381122|3344556677885f5f5f5f5f 64 gnu cmpw $0x2211,(%rax) 6681381122|3344556677885f5f5f5f5f 64 intel cmp word ptr [rax], 0x2211 -6681381122|3344556677885f5f5f5f5f 64 plan9 CMPW $0x2211, 0(AX) +6681381122|3344556677885f5f5f5f5f 64 plan9 CMPW 0(AX), $0x2211 66830011|223344556677885f5f5f5f5f 32 intel add word ptr [eax], 0x11 66830011|223344556677885f5f5f5f5f 32 plan9 ADDW $0x11, 0(AX) 66830011|223344556677885f5f5f5f5f 64 gnu addw $0x11,(%rax) @@ -4383,10 +4383,10 @@ 66833011|223344556677885f5f5f5f5f 64 intel xor word ptr [rax], 0x11 66833011|223344556677885f5f5f5f5f 64 plan9 XORW $0x11, 0(AX) 66833811|223344556677885f5f5f5f5f 32 intel cmp word ptr [eax], 0x11 -66833811|223344556677885f5f5f5f5f 32 plan9 CMPW $0x11, 0(AX) +66833811|223344556677885f5f5f5f5f 32 plan9 CMPW 0(AX), $0x11 66833811|223344556677885f5f5f5f5f 64 gnu cmpw $0x11,(%rax) 66833811|223344556677885f5f5f5f5f 64 intel cmp word ptr [rax], 0x11 -66833811|223344556677885f5f5f5f5f 64 plan9 CMPW $0x11, 0(AX) +66833811|223344556677885f5f5f5f5f 64 plan9 CMPW 0(AX), $0x11 668511|223344556677885f5f5f5f5f5f 32 intel test word ptr [ecx], dx 668511|223344556677885f5f5f5f5f5f 32 plan9 TESTW DX, 0(CX) 668511|223344556677885f5f5f5f5f5f 64 gnu test %dx,(%rcx) @@ -4959,10 +4959,10 @@ 803011|223344556677885f5f5f5f5f5f 64 intel xor byte ptr [rax], 0x11 803011|223344556677885f5f5f5f5f5f 64 plan9 XORB $0x11, 0(AX) 803811|223344556677885f5f5f5f5f5f 32 intel cmp byte ptr [eax], 0x11 -803811|223344556677885f5f5f5f5f5f 32 plan9 CMPB $0x11, 0(AX) +803811|223344556677885f5f5f5f5f5f 32 plan9 CMPB 0(AX), $0x11 803811|223344556677885f5f5f5f5f5f 64 gnu cmpb $0x11,(%rax) 803811|223344556677885f5f5f5f5f5f 64 intel cmp byte ptr [rax], 0x11 -803811|223344556677885f5f5f5f5f5f 64 plan9 CMPB $0x11, 0(AX) +803811|223344556677885f5f5f5f5f5f 64 plan9 CMPB 0(AX), $0x11 810011223344|556677885f5f5f5f5f5f 32 intel add dword ptr [eax], 0x44332211 810011223344|556677885f5f5f5f5f5f 32 plan9 ADDL $0x44332211, 0(AX) 810011223344|556677885f5f5f5f5f5f 64 gnu addl $0x44332211,(%rax) @@ -4999,10 +4999,10 @@ 813011223344|556677885f5f5f5f5f5f 64 intel xor dword ptr [rax], 0x44332211 813011223344|556677885f5f5f5f5f5f 64 plan9 XORL $0x44332211, 0(AX) 813811223344|556677885f5f5f5f5f5f 32 intel cmp dword ptr [eax], 0x44332211 -813811223344|556677885f5f5f5f5f5f 32 plan9 CMPL $0x44332211, 0(AX) +813811223344|556677885f5f5f5f5f5f 32 plan9 CMPL 0(AX), $0x44332211 813811223344|556677885f5f5f5f5f5f 64 gnu cmpl $0x44332211,(%rax) 813811223344|556677885f5f5f5f5f5f 64 intel cmp dword ptr [rax], 0x44332211 -813811223344|556677885f5f5f5f5f5f 64 plan9 CMPL $0x44332211, 0(AX) +813811223344|556677885f5f5f5f5f5f 64 plan9 CMPL 0(AX), $0x44332211 830011|223344556677885f5f5f5f5f5f 32 intel add dword ptr [eax], 0x11 830011|223344556677885f5f5f5f5f5f 32 plan9 ADDL $0x11, 0(AX) 830011|223344556677885f5f5f5f5f5f 64 gnu addl $0x11,(%rax) @@ -5039,10 +5039,10 @@ 833011|223344556677885f5f5f5f5f5f 64 intel xor dword ptr [rax], 0x11 833011|223344556677885f5f5f5f5f5f 64 plan9 XORL $0x11, 0(AX) 833811|223344556677885f5f5f5f5f5f 32 intel cmp dword ptr [eax], 0x11 -833811|223344556677885f5f5f5f5f5f 32 plan9 CMPL $0x11, 0(AX) +833811|223344556677885f5f5f5f5f5f 32 plan9 CMPL 0(AX), $0x11 833811|223344556677885f5f5f5f5f5f 64 gnu cmpl $0x11,(%rax) 833811|223344556677885f5f5f5f5f5f 64 intel cmp dword ptr [rax], 0x11 -833811|223344556677885f5f5f5f5f5f 64 plan9 CMPL $0x11, 0(AX) +833811|223344556677885f5f5f5f5f5f 64 plan9 CMPL 0(AX), $0x11 8411|223344556677885f5f5f5f5f5f5f 32 intel test byte ptr [ecx], dl 8411|223344556677885f5f5f5f5f5f5f 32 plan9 TESTB DL, 0(CX) 8411|223344556677885f5f5f5f5f5f5f 64 gnu test %dl,(%rcx) diff --git a/x86/x86avxgen/generate.go b/x86/x86avxgen/generate.go index 14985cb3..da7fd318 100644 --- a/x86/x86avxgen/generate.go +++ b/x86/x86avxgen/generate.go @@ -230,8 +230,8 @@ func (gen *generator) makeYtab(zoffset int, zform string, args []*argument) ytab // // This is required due to how masking is implemented in asm6. // Single MASK1() instruction produces 2 ytabs, for example: -// 1. OP xmm, mem | Yxr, Yxm | Does not permit K arguments (K0 implied) -// 2. OP xmm, K2, mem | Yxr, Yknot0, Yxm | Does not permit K0 argument +// 1. OP xmm, mem | Yxr, Yxm | Does not permit K arguments (K0 implied) +// 2. OP xmm, K2, mem | Yxr, Yknot0, Yxm | Does not permit K0 argument // // This function also exploits that both ytab entries have same opbytes, // hence it is efficient to emit only one opbytes line and 0 Z-offset diff --git a/x86/x86avxgen/main.go b/x86/x86avxgen/main.go index 9fdf262e..b759c505 100644 --- a/x86/x86avxgen/main.go +++ b/x86/x86avxgen/main.go @@ -224,16 +224,16 @@ func assignZforms(ctx *context) { // elements order inside ytabList. // // We want these rules to be satisfied: -// - EVEX-encoded entries go after VEX-encoded entries. -// This way, VEX forms are selected over EVEX variants. -// - EVEX forms with SAE/RC must go before forms without them. -// This helps to avoid problems with reg-reg instructions -// that encode either of them in ModRM.R/M which causes -// ambiguity in ytabList (more than 1 ytab can match args). -// If first matching ytab has SAE/RC, problem will not occur. -// - Memory argument position affects order. -// Required to be in sync with XED encoder when there -// are multiple choices of how to encode instruction. +// - EVEX-encoded entries go after VEX-encoded entries. +// This way, VEX forms are selected over EVEX variants. +// - EVEX forms with SAE/RC must go before forms without them. +// This helps to avoid problems with reg-reg instructions +// that encode either of them in ModRM.R/M which causes +// ambiguity in ytabList (more than 1 ytab can match args). +// If first matching ytab has SAE/RC, problem will not occur. +// - Memory argument position affects order. +// Required to be in sync with XED encoder when there +// are multiple choices of how to encode instruction. func sortGroups(ctx *context) { sort.SliceStable(ctx.groups, func(i, j int) bool { return ctx.groups[i].opcode < ctx.groups[j].opcode diff --git a/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt b/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt index 07cbc41b..70bda8dd 100644 --- a/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt +++ b/x86/x86avxgen/testdata/xedpath/all-dec-instructions.txt @@ -11873,29 +11873,22 @@ IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 ###FILE: ./datafiles/avx512f/avx512-foundation-isa.xed.txt - #BEGIN_LEGAL -#INTEL CONFIDENTIAL -# -#Copyright (c) 2017, Intel Corporation. All rights reserved. -# -#The source code contained or described herein and all documents -#related to the source code ("Material") are owned by Intel Corporation -#or its suppliers or licensors. Title to the Material remains with -#Intel Corporation or its suppliers and licensors. The Material -#contains trade secrets and proprietary and confidential information of -#Intel or its suppliers and licensors. The Material is protected by -#worldwide copyright and trade secret laws and treaty provisions. No -#part of the Material may be used, copied, reproduced, modified, -#published, uploaded, posted, transmitted, distributed, or disclosed in -#any way without Intel's prior express written permission. -# -#No license under any patent, copyright, trade secret or other -#intellectual property right is granted to or conferred upon you by -#disclosure or delivery of the Materials, either expressly, by -#implication, inducement, estoppel or otherwise. Any license under such -#intellectual property rights must be express and approved by Intel in -#writing. +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# #END_LEGAL # # @@ -13103,7 +13096,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 } @@ -13117,7 +13113,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 } @@ -13131,7 +13130,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 } @@ -13147,7 +13149,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 } @@ -13161,7 +13163,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 } @@ -13175,7 +13177,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512 } @@ -13235,7 +13237,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 } @@ -13249,7 +13254,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 } @@ -13263,7 +13271,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 } @@ -13279,7 +13290,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 } @@ -13293,7 +13304,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 } @@ -13307,7 +13318,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512 } @@ -13323,7 +13334,11 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E10NF REAL_OPCODE: Y ATTRIBUTES: SIMD_SCALAR -PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 +COMMENT: Ignores rounding controls: 32b-INT-to-FP64 does not need rounding +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 } @@ -13337,7 +13352,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E10NF REAL_OPCODE: Y ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 } @@ -13353,7 +13371,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 } @@ -13367,7 +13385,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 } @@ -13381,7 +13399,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64 IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 } @@ -13397,7 +13415,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 } @@ -13411,7 +13432,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 } @@ -13425,7 +13449,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 } @@ -13441,7 +13468,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 } @@ -13455,7 +13482,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 } @@ -13469,12 +13496,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64 IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 } - - # EMITTING VCVTSS2SD (VCVTSS2SD-128-1) { ICLASS: VCVTSS2SD @@ -13529,7 +13554,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 } @@ -13543,7 +13571,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 } @@ -13557,7 +13588,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 } @@ -13573,7 +13607,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 } @@ -13587,7 +13621,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 } @@ -13601,7 +13635,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR -PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512 } @@ -13617,7 +13651,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 } @@ -13631,7 +13668,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 } @@ -13645,7 +13685,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 } @@ -13661,7 +13704,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 } @@ -13675,7 +13718,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 } @@ -13689,7 +13732,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR -PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512 } @@ -13881,7 +13924,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 } @@ -13895,7 +13941,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 } @@ -13909,7 +13958,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 } @@ -13925,7 +13977,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 } @@ -13939,7 +13991,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 } @@ -13953,7 +14005,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512 } @@ -13969,7 +14021,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 } @@ -13983,7 +14038,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 } @@ -13997,7 +14055,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 } @@ -14013,7 +14074,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 } @@ -14027,7 +14088,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 } @@ -14041,7 +14102,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q -PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512 } @@ -14057,7 +14118,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 } @@ -14071,7 +14135,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 } @@ -14085,7 +14152,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 } @@ -14101,7 +14171,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 } @@ -14115,7 +14185,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 } @@ -14129,7 +14199,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR -PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512 } @@ -14145,7 +14215,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 } @@ -14159,7 +14232,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 } @@ -14173,7 +14249,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 } @@ -14189,7 +14268,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 } @@ -14203,7 +14282,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 } @@ -14217,7 +14296,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR -PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512 } @@ -14307,7 +14386,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E10NF REAL_OPCODE: Y ATTRIBUTES: SIMD_SCALAR -PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 } @@ -14321,7 +14403,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E10NF REAL_OPCODE: Y ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 } @@ -14337,7 +14422,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 } @@ -14351,7 +14436,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 } @@ -14365,7 +14450,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64 IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 } @@ -14381,7 +14466,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 MASK=0 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 } @@ -14395,7 +14483,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 ZEROING=0 MASK=0 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 } @@ -14409,7 +14500,10 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 } @@ -14425,7 +14519,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 mode64 ZEROING=0 MASK=0 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 } @@ -14439,7 +14533,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR -PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 } @@ -14453,7 +14547,7 @@ ISA_SET: AVX512F_SCALAR EXCEPTIONS: AVX512-E3NF REAL_OPCODE: Y ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER -PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64 IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 } @@ -18722,7 +18816,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 +IFORM: VMOVD_XMMu32_GPR32u32_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 IFORM: VMOVD_XMMu32_GPR32u32_AVX512 } @@ -18736,7 +18833,10 @@ ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_READER -PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 +IFORM: VMOVD_XMMu32_MEMu32_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 IFORM: VMOVD_XMMu32_MEMu32_AVX512 } @@ -18751,7 +18851,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 +IFORM: VMOVD_GPR32u32_XMMu32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IFORM: VMOVD_GPR32u32_XMMu32_AVX512 } @@ -18765,7 +18868,10 @@ ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVD_MEMu32_XMMu32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IFORM: VMOVD_MEMu32_XMMu32_AVX512 } @@ -19074,7 +19180,7 @@ ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64 IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 } @@ -19090,7 +19196,7 @@ ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64 IFORM: VMOVHPD_MEMf64_XMMf64_AVX512 } @@ -19153,7 +19259,7 @@ ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64 IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 } @@ -19169,7 +19275,7 @@ ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64 IFORM: VMOVLPD_MEMf64_XMMf64_AVX512 } @@ -19338,7 +19444,7 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64 IFORM: VMOVQ_XMMu64_XMMu64_AVX512 } @@ -19352,7 +19458,7 @@ ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 IFORM: VMOVQ_XMMu64_MEMu64_AVX512 } @@ -19367,7 +19473,7 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 +PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64 IFORM: VMOVQ_XMMu64_XMMu64_AVX512 } @@ -19381,7 +19487,7 @@ ISA_SET: AVX512F_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_SCALAR -PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IFORM: VMOVQ_MEMu64_XMMu64_AVX512 } @@ -20217,7 +20323,10 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 } @@ -20265,7 +20374,7 @@ ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 mode64 NOEVSR +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64 IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 } @@ -22272,9 +22381,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 } @@ -22286,9 +22396,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 } @@ -22332,9 +22443,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 } @@ -22346,9 +22458,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_512 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 } @@ -25350,7 +25463,6 @@ IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 - ###FILE: ./datafiles/avx512cd/vconflict-isa.xed.txt #BEGIN_LEGAL @@ -25533,29 +25645,22 @@ IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD ###FILE: ./datafiles/avx512-skx/skx-isa.xed.txt - #BEGIN_LEGAL -#INTEL CONFIDENTIAL -# -#Copyright (c) 2017, Intel Corporation. All rights reserved. -# -#The source code contained or described herein and all documents -#related to the source code ("Material") are owned by Intel Corporation -#or its suppliers or licensors. Title to the Material remains with -#Intel Corporation or its suppliers and licensors. The Material -#contains trade secrets and proprietary and confidential information of -#Intel or its suppliers and licensors. The Material is protected by -#worldwide copyright and trade secret laws and treaty provisions. No -#part of the Material may be used, copied, reproduced, modified, -#published, uploaded, posted, transmitted, distributed, or disclosed in -#any way without Intel's prior express written permission. -# -#No license under any patent, copyright, trade secret or other -#intellectual property right is granted to or conferred upon you by -#disclosure or delivery of the Materials, either expressly, by -#implication, inducement, estoppel or otherwise. Any license under such -#intellectual property rights must be express and approved by Intel in -#writing. +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# #END_LEGAL # # @@ -25818,8 +25923,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { @@ -25832,8 +25937,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDNPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } @@ -25848,8 +25953,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { @@ -25862,8 +25967,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDNPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } @@ -25878,8 +25983,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { @@ -25892,8 +25997,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDNPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } @@ -25908,8 +26013,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { @@ -25922,8 +26027,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDNPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } @@ -25938,8 +26043,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { @@ -25952,8 +26057,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDNPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } @@ -25968,8 +26073,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { @@ -25982,8 +26087,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDNPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } @@ -25998,8 +26103,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { @@ -26012,8 +26117,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } @@ -26028,8 +26133,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { @@ -26042,8 +26147,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } @@ -26058,8 +26163,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { @@ -26072,8 +26177,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VANDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } @@ -26088,8 +26193,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { @@ -26102,8 +26207,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } @@ -26118,8 +26223,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { @@ -26132,8 +26237,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } @@ -26148,8 +26253,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { @@ -26162,8 +26267,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VANDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } @@ -34886,8 +34991,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { @@ -34900,8 +35005,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } @@ -34916,8 +35021,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { @@ -34930,8 +35035,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } @@ -34946,8 +35051,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { @@ -34960,8 +35065,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } @@ -34976,8 +35081,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { @@ -34990,8 +35095,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } @@ -35006,8 +35111,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { @@ -35020,8 +35125,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } @@ -35036,8 +35141,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { @@ -35050,8 +35155,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } @@ -37365,7 +37470,10 @@ ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 } @@ -37413,7 +37521,10 @@ ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E7NM REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX -PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 } @@ -40497,7 +40608,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 } @@ -40511,7 +40625,10 @@ ISA_SET: AVX512DQ_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_WRITER_STORE -PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 } @@ -40577,16 +40694,22 @@ IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 # EMITTING VPEXTRW (VPEXTRW-128-2) { -ICLASS: VPEXTRW +ICLASS: VPEXTRW_C5 +DISASM: vpextrw CPL: 3 CATEGORY: AVX512 EXTENSION: AVX512EVEX ISA_SET: AVX512BW_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() + +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64 OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b -IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 + +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 } @@ -40756,7 +40879,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512DQ_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y -PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 } @@ -40770,7 +40896,10 @@ ISA_SET: AVX512DQ_128N EXCEPTIONS: AVX512-E9NF REAL_OPCODE: Y ATTRIBUTES: DISP8_GPR_READER -PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 } @@ -44731,9 +44860,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 } @@ -44745,9 +44875,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 } @@ -44761,9 +44892,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 } @@ -44775,9 +44907,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 } @@ -45301,9 +45434,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 } @@ -45315,9 +45449,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_128 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 } @@ -45331,9 +45466,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 } @@ -45345,9 +45481,10 @@ EXTENSION: AVX512EVEX ISA_SET: AVX512F_256 EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 } @@ -52592,8 +52729,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 -IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 } { @@ -52606,8 +52743,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VXORPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 } @@ -52622,8 +52759,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 -IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 } { @@ -52636,8 +52773,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VXORPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 } @@ -52652,8 +52789,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 -IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 } { @@ -52666,8 +52803,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR -IFORM: VXORPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 } @@ -52682,8 +52819,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 -IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 } { @@ -52696,8 +52833,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VXORPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 } @@ -52712,8 +52849,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 -IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 } { @@ -52726,8 +52863,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VXORPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 } @@ -52742,8 +52879,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MASKOP_EVEX PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 -IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 } { @@ -52756,8 +52893,8 @@ EXCEPTIONS: AVX512-E4 REAL_OPCODE: Y ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() -OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR -IFORM: VXORPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 } @@ -53606,7 +53743,6 @@ IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 - ###FILE: ./datafiles/avx512ifma/ifma-isa.xed.txt #BEGIN_LEGAL @@ -57891,3 +58027,79 @@ PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no6 OPERANDS : MEM0:r:y } + + + + +###FILE: ./datafiles/sha512/sha512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2023 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VSHA512MSG1 (VSHA512MSG1-256-1) +{ +ICLASS: VSHA512MSG1 +CPL: 3 +CATEGORY: SHA512 +EXTENSION: SHA512 +ISA_SET: SHA512 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xCC VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=XMM_B():r:dq:u64 +IFORM: VSHA512MSG1_YMMu64_XMMu64 +} + + +# EMITTING VSHA512MSG2 (VSHA512MSG2-256-1) +{ +ICLASS: VSHA512MSG2 +CPL: 3 +CATEGORY: SHA512 +EXTENSION: SHA512 +ISA_SET: SHA512 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xCD VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 NOVSR +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_B():r:qq:u64 +IFORM: VSHA512MSG2_YMMu64_YMMu64 +} + + +# EMITTING VSHA512RNDS2 (VSHA512RNDS2-256-1) +{ +ICLASS: VSHA512RNDS2 +CPL: 3 +CATEGORY: SHA512 +EXTENSION: SHA512 +ISA_SET: SHA512 +EXCEPTIONS: avx-type-6 +REAL_OPCODE: Y +PATTERN: VV1 0xCB VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL256 +OPERANDS: REG0=YMM_R():rw:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:dq:u64 +IFORM: VSHA512RNDS2_YMMu64_YMMu64_XMMu64 +} \ No newline at end of file diff --git a/x86/x86avxgen/testdata/xedpath/all-extra-widths.txt b/x86/x86avxgen/testdata/xedpath/all-extra-widths.txt new file mode 100644 index 00000000..30a004e6 --- /dev/null +++ b/x86/x86avxgen/testdata/xedpath/all-extra-widths.txt @@ -0,0 +1,3 @@ +# Copyright 2025 The Go Authors. All rights reserved. +# Use of this source code is governed by a BSD-style +# license that can be found in the LICENSE file. diff --git a/x86/x86csv/x86csv.go b/x86/x86csv/x86csv.go index e205c1b4..6f6b68c7 100644 --- a/x86/x86csv/x86csv.go +++ b/x86/x86csv/x86csv.go @@ -6,7 +6,7 @@ // Only latest version of "x86.csv" format is supported. // // Terminology: -// given "OPCODE [ARGS...]" line; +// given "OPCODE [ARGS...]" line; // Opcode - instruction name/mnemonic/class. // Args - instruction operands. // Syntax - Opcode with Args. diff --git a/x86/x86map/map.go b/x86/x86map/map.go index df8c68e5..9d45a704 100644 --- a/x86/x86map/map.go +++ b/x86/x86map/map.go @@ -5,13 +5,14 @@ // X86map constructs the x86 opcode map from the instruction set CSV file. // // Usage: +// // x86map [-fmt=format] x86.csv // // The known output formats are: // -// text (default) - print decoding tree in text form -// decoder - print decoding tables for the x86asm package -// scanner - print scanning tables for x86scan package +// text (default) - print decoding tree in text form +// decoder - print decoding tables for the x86asm package +// scanner - print scanning tables for x86scan package package main import ( diff --git a/x86/x86spec/parse.go b/x86/x86spec/parse.go index e5324bea..8a9adc98 100644 --- a/x86/x86spec/parse.go +++ b/x86/x86spec/parse.go @@ -510,7 +510,14 @@ func findWords(chars []pdf.Text) (words []pdf.Text) { f := ck.Font f = strings.TrimSuffix(f, ",Italic") f = strings.TrimSuffix(f, "-Italic") - words = append(words, pdf.Text{f, ck.FontSize, ck.X, ck.Y, end, s}) + words = append(words, pdf.Text{ + Font: f, + FontSize: ck.FontSize, + X: ck.X, + Y: ck.Y, + W: end, + S: s, + }) k = l } i = j diff --git a/x86/x86spec/spec.go b/x86/x86spec/spec.go index 25267941..57f3276c 100644 --- a/x86/x86spec/spec.go +++ b/x86/x86spec/spec.go @@ -2,7 +2,7 @@ // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. -// X86spec reads the ``Intel® 64 and IA-32 Architectures Software Developer's Manual'' +// X86spec reads the “Intel® 64 and IA-32 Architectures Software Developer's Manual” // to collect instruction encoding details and writes those details to standard output // in CSV format. // @@ -20,7 +20,7 @@ // // There are additional debugging flags, not shown. Run x86spec -help for the list. // -// File Format +// # File Format // // TODO: Mention comments at top of file. // TODO: Mention that this is version 0.2 of the file. @@ -59,7 +59,7 @@ // // "SHR r/m32, imm8","SHRL imm8, r/m32","shrl imm8, r/m32","C1 /5 ib","V","V","","operand32","rw,r","Y","32" // -// Mnemonics +// # Mnemonics // // The instruction mnemonics are as used in the Intel manual, with a few exceptions. // @@ -109,7 +109,7 @@ // moffs8, moffs16, moffs32, moffs64, vm32x, vm32y, vm64x, and vm64y // are all as in the Intel manual. // -// Encodings +// # Encodings // // The encodings are also as used in the Intel manual, with automated corrections. // For example, the Intel manual sometimes omits the modrm /r indicator or other trailing bytes, @@ -118,7 +118,7 @@ // tools for processing x86 machine code. // See https://golang.org/x/arch/x86/x86map for one such generator. // -// Valid32 and Valid64 +// # Valid32 and Valid64 // // These columns hold validity abbreviations as defined in the Intel manual: // V, I, N.E., N.P., N.S., or N.I. @@ -128,7 +128,7 @@ // For example, the manual lists many instruction forms using REX bytes // with an incorrect "V" in the Valid32 column. // -// CPUID Feature Flags +// # CPUID Feature Flags // // This column specifies CPUID feature flags that must be present in order // to use the instruction. If multiple flags are required, @@ -136,7 +136,7 @@ // The column can also list one of the values 486, Pentium, PentiumII, and P6, // indicating that the instruction was introduced on that architecture version. // -// Tags +// # Tags // // The tag column does not correspond to a traditional column in the Intel manual tables. // Instead, it is itself a comma-separated list of tags or hints derived by analysis @@ -169,7 +169,7 @@ // Since most decoders will handle the REX byte separately, the form with the // unnecessary REX is tagged pseudo64. // -// Corrections and Additions +// # Corrections and Additions // // The x86spec program makes various corrections to the Intel manual data // as part of extracting the information. Those corrections are described above. @@ -177,7 +177,7 @@ // The x86spec program also adds a few well-known undocumented instructions, // such as UD1 and FFREEP. // -// Examples +// # Examples // // The latest version of the CSV file is available in this Git repository and also // online at https://golang.org/s/x86.csv. It is meant to be human-readable for @@ -193,7 +193,6 @@ // reads the CSV file and generates an x86 instruction decoder in the form // of a simple byte-code program. This decoder is the core of the disassembler // in the x86asm package (https://golang.org/x/arch/x86/x86asm). -// package main import ( diff --git a/x86/xeddata/database.go b/x86/xeddata/database.go index 35d86d98..a6ec760d 100644 --- a/x86/xeddata/database.go +++ b/x86/xeddata/database.go @@ -74,9 +74,19 @@ type Database struct { widths map[string]*width // all-widths.txt states map[string]string // all-state.txt xtypes map[string]*xtype // all-element-types.txt + + // extraWidth is a "all-extra-widths.txt" record. + // + // It provides a default mapping from an operand type to a width code. + // + // The key is one of three things: + // - "XED_REG_" for a register (e.g., "XED_REG_EAX") + // - "()" for a non-terminal (e.g., "GPR32_R()"") + // - "" for an immediate const (e.g., "AGEN") + extraWidths map[string]string // all-extra-widths.txt } -// width is a "all-width.txt" record. +// width is a "all-widths.txt" record. type width struct { // Default xtype name (examples: int, i8, f32). xtype string @@ -104,9 +114,11 @@ type xtype struct { // parsing of found file is. // // Lookup: +// // "$xedPath/all-state.txt" => db.LoadStates() // "$xedPath/all-widths.txt" => db.LoadWidths() // "$xedPath/all-element-types.txt" => db.LoadXtypes() +// // $xedPath is the interpolated value of function argument. // // The call NewDatabase("") is valid and returns empty database. @@ -138,6 +150,14 @@ func NewDatabase(xedPath string) (*Database, error) { } } + extraWidths, err := os.Open(filepath.Join(xedPath, "all-extra-widths.txt")) + if err == nil { + db.extraWidths, err = parseExtraWidths(extraWidths) + if err != nil { + return &db, err + } + } + xtypes, err := os.Open(filepath.Join(xedPath, "all-element-types.txt")) if err == nil { err = db.LoadXtypes(xtypes) @@ -179,6 +199,10 @@ func (db *Database) LoadXtypes(r io.Reader) error { // WidthSize translates width string to size string using desired // SizeMode m. For some widths output is the same for any valid value of m. +// +// The size string may be a decimal number of bytes, like "8". It may of the +// form "%dbits" to indicate a bit width. Or in some cases it's "0" for +// "unusual" registers. func (db *Database) WidthSize(width string, m OperandSizeMode) string { info := db.widths[width] if info == nil { @@ -233,6 +257,30 @@ func parseWidths(r io.Reader) (map[string]*width, error) { return widths, nil } +func parseExtraWidths(r io.Reader) (map[string]string, error) { + extraWidths := make(map[string]string) + for line, err := range readLines(r) { + if err != nil { + return nil, err + } + f := bytes.Fields(line.data) + if len(f) != 3 { + return nil, fmt.Errorf("want 3 fields, got %d", len(f)) + } + switch string(f[0]) { + default: + return nil, fmt.Errorf("unknown extra width type %s", f[0]) + case "imm_const": + extraWidths[string(f[1])] = string(f[2]) + case "reg": + extraWidths["XED_REG_"+string(f[1])] = string(f[2]) + case "nt": + extraWidths[string(f[1])+"()"] = string(f[2]) + } + } + return extraWidths, nil +} + func parseStates(r io.Reader) (map[string]string, error) { data, err := ioutil.ReadAll(r) if err != nil { diff --git a/x86/xeddata/doc.go b/x86/xeddata/doc.go index bb1a96af..4439552b 100644 --- a/x86/xeddata/doc.go +++ b/x86/xeddata/doc.go @@ -5,40 +5,50 @@ // Package xeddata provides utilities to work with XED datafiles. // // Main features: -// * Fundamental XED enumerations (CPU modes, operand sizes, ...) -// * XED objects and their components -// * XED datafiles reader (see below) -// * Utility functions like ExpandStates +// - Fundamental XED enumerations (CPU modes, operand sizes, ...) +// - XED objects and their components +// - XED datafiles reader (see below) +// - Utility functions like ExpandStates // // The amount of file formats that is understood is a minimal // set required to generate x86.csv from XED tables: -// * states - simple macro substitutions used in patterns -// * widths - mappings from width names to their size -// * element-types - XED xtype information -// * objects - XED objects that constitute "the tables" +// - states - simple macro substitutions used in patterns +// - widths - mappings from width names to their size +// - element-types - XED xtype information +// - objects - XED objects that constitute "the tables" +// // Collectively, those files are called "datafiles". // // Terminology is borrowed from XED itself, // where appropriate, x86csv names are provided // as an alternative. // +// Suppose $XED is the path of a checkout of the +// https://github.com/intelxed/xed repo. +// // "$XED/foo/bar.txt" notation is used to specify a path to "foo/bar.txt" // file under local XED source repository folder. // // The default usage scheme: -// 1. Open "XED database" to load required metadata. -// 2. Read XED file with objects definitions. -// 3. Operate on XED objects. +// 1. Open "XED database" to load required metadata. +// 2. Read XED file with objects definitions. +// 3. Operate on XED objects. // // See example_test.go for complete examples. +// See testdata/xed_objects.txt for examples of "XED objects". +// +// # Obtain XED datafiles // // It is required to build Intel XED before attempting to use -// its datafiles, as this package expects "all" versions that +// its datafiles, as this package expects the "all" versions that // are a concatenated final versions of datafiles. +// To build it, follow the instruction on https://github.com/intelxed/xed. +// +// Once built, the "all" versions of data files are in "$XED/obj/dgen/". // If "$XED/obj/dgen/" does not contain relevant files, // then either this documentation is stale or your XED is not built. -// -// To see examples of "XED objects" see "testdata/xed_objects.txt". +// Pass $XED/obj/dgen (or a copy of it) as the "xedPath" to [NewDatabase] +// or to x86avxgen -xedPath. // // Intel XED https://github.com/intelxed/xed provides all documentation // that can be required to understand datafiles. diff --git a/x86/xeddata/object.go b/x86/xeddata/object.go index 4a739739..662aa694 100644 --- a/x86/xeddata/object.go +++ b/x86/xeddata/object.go @@ -21,6 +21,9 @@ import ( // Object contains multiple Inst elements that represent concrete // instruction with encoding pattern and operands description. type Object struct { + // Pos is the file position of the start of this object. + Pos Pos + // Iclass is instruction class name (opcode). // Iclass alone is not enough to uniquely identify machine instructions. // Example: "PSRLW". @@ -128,6 +131,9 @@ type Inst struct { // Inst objects. *Object + // Pos is the file position of this Inst's PATTERN. + Pos Pos + // Index is the position inside XED object. // Object.Insts[Index] returns this inst. Index int diff --git a/x86/xeddata/operand.go b/x86/xeddata/operand.go index 1632828d..33c5610f 100644 --- a/x86/xeddata/operand.go +++ b/x86/xeddata/operand.go @@ -44,13 +44,18 @@ type Operand struct { // Action describes argument types. // - // Possible values: "r", "w", "rw", "cr", "cw", "crw". - // Optional "c" prefix represents conditional access. + // Possible values: "r", "w", "rw", "cr", "cw", "crw", "rcw". + // The "c" prefix before "r" or "w" represents conditional read or write. Action string // Width descriptor. It can express simple width like "w" (word, 16bit) // or meta-width like "v", which corresponds to {16, 32, 64} bits. // + // The first column in all-widths.txt lists all possible widths. + // + // To deterine the size given a width string and a mode, use + // [Database.WidthSize]. + // // Possible values: "", "q", "ds", "dq", ... // Optional. Width string @@ -91,11 +96,14 @@ var xedVisibilities = map[string]OperandVisibility{ // See "$XED/pysrc/opnds.py" to learn about fields format // and valid combinations. // -// Requires database with xtypes and widths info. +// Requires database with xtypes, widths, and extraWidths info. func NewOperand(db *Database, s string) (*Operand, error) { if db.widths == nil { return nil, errors.New("Database.widths is nil") } + if db.extraWidths == nil { + return nil, errors.New("Database.extraWidths is nil") + } fields := strings.Split(s, ":") switch len(fields) { @@ -111,9 +119,10 @@ func NewOperand(db *Database, s string) (*Operand, error) { op.Action = fields[1] // Optional fields. + var w string for _, f := range fields[2:] { - if db.widths[f] != nil && op.Width == "" { - op.Width = f + if db.widths[f] != nil && w == "" { + w = f } else if vis, ok := xedVisibilities[f]; ok { op.Visibility = vis } else if xtype := db.xtypes[f]; xtype != nil { @@ -126,6 +135,33 @@ func NewOperand(db *Database, s string) (*Operand, error) { } } + // Get default width from operand type. + if w == "" { + if op.NonterminalName() { + if strings.HasPrefix(op.NameLHS(), "REG") { + rhs := op.NameRHS() + if strings.HasPrefix(rhs, "XED_REG_") { + // Register + w = db.extraWidths[rhs] + } else if strings.HasSuffix(rhs, "()") { + // Non-terminal + w = db.extraWidths[rhs] + } + } + } else { + // Try as an immediate. + w = db.extraWidths[op.Name] + } + } + + if w != "" { + op.Width = w + // If operand did not specify an xtype, get the default from the width + if op.Xtype == "" && db.widths[w] != nil { + op.Xtype = db.widths[w].xtype + } + } + return &op, nil } @@ -141,13 +177,15 @@ func (op *Operand) NonterminalName() bool { // NameLHS returns left hand side part of the non-terminal name. // Example: NameLHS("REG0=GPRv()") => "REG0". func (op *Operand) NameLHS() string { - return strings.Split(op.Name, "=")[0] + lhs, _, _ := strings.Cut(op.Name, "=") + return lhs } // NameRHS returns right hand side part of the non-terminal name. // Example: NameLHS("REG0=GPRv()") => "GPRv()". func (op *Operand) NameRHS() string { - return strings.Split(op.Name, "=")[1] + _, rhs, _ := strings.Cut(op.Name, "=") + return rhs } // IsVisible returns true for operands that are usually diff --git a/x86/xeddata/reader.go b/x86/xeddata/reader.go index 4176b66e..02fd9c81 100644 --- a/x86/xeddata/reader.go +++ b/x86/xeddata/reader.go @@ -5,47 +5,27 @@ package xeddata import ( - "bufio" "errors" "fmt" "io" + "iter" "regexp" "strings" ) // Reader reads enc/dec-instruction objects from XED datafile. type Reader struct { - scanner *bufio.Scanner + r io.Reader - lines []string // Re-used between Read calls - - // True if last line ends with newline escape (backslash). - joinLines bool + // Initialized on first call to Read + next func() (*Object, error, bool) + stop func() + err error } // NewReader returns a new Reader that reads from r. func NewReader(r io.Reader) *Reader { - return newReader(bufio.NewScanner(r)) -} - -func newReader(scanner *bufio.Scanner) *Reader { - r := &Reader{ - lines: make([]string, 0, 64), - scanner: scanner, - } - scanner.Split(r.split) - return r -} - -// split implements bufio.SplitFunc for Reader. -func (r *Reader) split(data []byte, atEOF bool) (int, []byte, error) { - // Wrapping bufio.ScanLines to handle \-style newline escapes. - // joinLines flag affects Reader.scanLine behavior. - advance, tok, err := bufio.ScanLines(data, atEOF) - if err == nil && len(tok) >= 1 { - r.joinLines = tok[len(tok)-1] == '\\' - } - return advance, tok, err + return &Reader{r: r} } // Read reads single XED instruction object from @@ -54,37 +34,69 @@ func (r *Reader) split(data []byte, atEOF bool) (int, []byte, error) { // If there is no data left to be read, // returned error is io.EOF. func (r *Reader) Read() (*Object, error) { - for line := r.scanLine(); line != ""; line = r.scanLine() { - if line[0] != '{' { - continue - } - lines := r.lines[:0] // Object lines - for line := r.scanLine(); line != ""; line = r.scanLine() { - if line[0] == '}' { - return r.parseLines(lines) - } - lines = append(lines, line) - } - return nil, errors.New("no matching '}' found") + if r.err != nil { + return nil, r.err } - - return nil, io.EOF + if r.next == nil { + r.next, r.stop = iter.Pull2(readObjects(r.r)) + } + obj, err, end := r.next() + if end { + err = io.EOF + } + if err != nil { + r.stop() + r.err, r.next, r.stop = err, nil, nil + return nil, err + } + return obj, nil } // ReadAll reads all the remaining objects from r. // A successful call returns err == nil, not err == io.EOF, // just like csv.Reader.ReadAll(). func (r *Reader) ReadAll() ([]*Object, error) { - objects := []*Object{} - for { - o, err := r.Read() - if err == io.EOF { - return objects, nil - } + var objects []*Object + for obj, err := range readObjects(r.r) { if err != nil { return objects, err } - objects = append(objects, o) + objects = append(objects, obj) + } + return objects, nil +} + +// readObjects yields all of the objects from r. +func readObjects(r io.Reader) iter.Seq2[*Object, error] { + iterLines := readLines(r) + return func(yield func(*Object, error) bool) { + var blockPos Pos + var block []string // Reused on each iteration + var linePos []Pos + inBlock := false + for line, err := range iterLines { + if err != nil { + yield(nil, err) + return + } + if !inBlock { + inBlock = line.data[0] == '{' + blockPos = line.Pos + } else if line.data[0] == '}' { + inBlock = false + obj, err := parseObjectLines(blockPos, block, linePos) + if !yield(obj, err) { + return + } + block, linePos = block[:0], linePos[:0] + } else { + block = append(block, string(line.data)) + linePos = append(linePos, line.Pos) + } + } + if inBlock { + yield(nil, errors.New("no matching '}' found")) + } } } @@ -92,15 +104,16 @@ func (r *Reader) ReadAll() ([]*Object, error) { // It expects lines that are joined by '\' to be concatenated. // // The format can be described as: +// // unquoted field name "[A-Z_]+" (captured) // field value delimiter ":" // field value string (captured) -// optional trailing comment that is ignored "[^#]*" -var instLineRE = regexp.MustCompile(`^([A-Z_]+)\s*:\s*([^#]*)`) +var instLineRE = regexp.MustCompile(`^([A-Z_]+)\s*:\s*(.*)`) // parseLines turns collected object lines into Object. -func (r *Reader) parseLines(lines []string) (*Object, error) { +func parseObjectLines(blockPos Pos, lines []string, linePos []Pos) (*Object, error) { o := &Object{} + o.Pos = blockPos // Repeatable tokens. // We can not assign them eagerly, because these fields @@ -109,9 +122,11 @@ func (r *Reader) parseLines(lines []string) (*Object, error) { operands []string iforms []string patterns []string + poses []Pos ) - for _, l := range lines { + for i, l := range lines { + l = strings.TrimLeft(l, " ") if l[0] == '#' { // Skip comment lines. continue } @@ -158,6 +173,7 @@ func (r *Reader) parseLines(lines []string) (*Object, error) { operands = append(operands, val) case "PATTERN": patterns = append(patterns, val) + poses = append(poses, linePos[i]) case "IFORM": iforms = append(iforms, val) @@ -179,6 +195,7 @@ func (r *Reader) parseLines(lines []string) (*Object, error) { Object: o, Index: i, Pattern: patterns[i], + Pos: poses[i], Operands: operands[i], } // There can be less IFORMs than insts. @@ -190,21 +207,3 @@ func (r *Reader) parseLines(lines []string) (*Object, error) { return o, nil } - -// scanLine tries to fetch non-empty line from scanner. -// -// Returns empty line when scanner.Scan() returns false -// before non-empty line is found. -func (r *Reader) scanLine() string { - for r.scanner.Scan() { - line := r.scanner.Text() - if line == "" { - continue - } - if r.joinLines { - return line[:len(line)-len("\\")] + r.scanLine() - } - return line - } - return "" -} diff --git a/x86/xeddata/readlines.go b/x86/xeddata/readlines.go new file mode 100644 index 00000000..d9638973 --- /dev/null +++ b/x86/xeddata/readlines.go @@ -0,0 +1,99 @@ +// Copyright 2025 The Go Authors. All rights reserved. +// Use of this source code is governed by a BSD-style +// license that can be found in the LICENSE file. + +package xeddata + +import ( + "bufio" + "bytes" + "fmt" + "io" + "iter" + "path/filepath" + "strings" +) + +type lineInfo struct { + Pos + data []byte +} + +type Pos struct { + Path string + Line int +} + +func (p Pos) String() string { + if p.Line == 0 { + if p.Path == "" { + return "?:?" + } + return p.Path + } else if p.Path == "" { + return fmt.Sprintf("?:%d", p.Line) + } + return fmt.Sprintf("%s:%d", p.Path, p.Line) +} + +func (p Pos) ShortString() string { + p2 := p + p2.Path = filepath.Base(p.Path) + return p2.String() +} + +// readLines yields lines from r, with continuation lines folded, comments and +// trailing whitespace removed, and blank lines omitted. +// +// The returned lineInfo.data buffer may be reused between yields. +// +// If r has a Name() string method, this is used to populate lineInfo.Path. +func readLines(r io.Reader) iter.Seq2[lineInfo, error] { + type Named interface { + Name() string // Matches os.File + } + path := "" + if f, ok := r.(Named); ok { + path = f.Name() + } + + s := bufio.NewScanner(r) + return func(yield func(lineInfo, error) bool) { + var info lineInfo + info.Path = path + var lineBuf []byte + for s.Scan() { + info.Line++ + + lineBuf = append(lineBuf, s.Bytes()...) + if len(lineBuf) > 0 && lineBuf[len(lineBuf)-1] == '\\' { + // Continuation line. Drop the \ and keep reading. + lineBuf = lineBuf[:len(lineBuf)-1] + continue + } + // Remove comments and trailing whitespace + if i := strings.IndexByte(string(lineBuf), '#'); i >= 0 { + lineBuf = lineBuf[:i] + } + lineBuf = bytes.TrimRight(lineBuf, " \t") + // Don't yield blank lines + if len(lineBuf) == 0 { + continue + } + + info.data = lineBuf + if !yield(info, nil) { + return + } + lineBuf = lineBuf[:0] + } + + if err := s.Err(); err != nil { + yield(lineInfo{}, err) + return + } + if len(lineBuf) > 0 { + yield(lineInfo{}, fmt.Errorf("continuation line at EOF")) + } + } +} diff --git a/x86/xeddata/testdata/xed_objects.txt b/x86/xeddata/testdata/xed_objects.txt index 9d0c52e5..c252acfd 100644 --- a/x86/xeddata/testdata/xed_objects.txt +++ b/x86/xeddata/testdata/xed_objects.txt @@ -13,6 +13,7 @@ # { # ICLASS : ADD # } + # comment with leading space ==== [] diff --git a/x86/xeddata/testdata/xedpath/all-extra-widths.txt b/x86/xeddata/testdata/xedpath/all-extra-widths.txt new file mode 100644 index 00000000..30a004e6 --- /dev/null +++ b/x86/xeddata/testdata/xedpath/all-extra-widths.txt @@ -0,0 +1,3 @@ +# Copyright 2025 The Go Authors. All rights reserved. +# Use of this source code is governed by a BSD-style +# license that can be found in the LICENSE file. diff --git a/x86/xeddata/xeddata.go b/x86/xeddata/xeddata.go index 7cc7a087..4d2b2012 100644 --- a/x86/xeddata/xeddata.go +++ b/x86/xeddata/xeddata.go @@ -5,7 +5,6 @@ package xeddata import ( - "io" "os" "path/filepath" ) @@ -16,17 +15,13 @@ func WalkInsts(xedPath string, visit func(*Inst)) error { if err != nil { return err } - r := NewReader(f) - for { - o, err := r.Read() - if err == io.EOF { - return nil - } + for obj, err := range readObjects(f) { if err != nil { return err } - for _, inst := range o.Insts { + for _, inst := range obj.Insts { visit(inst) } } + return nil } diff --git a/x86/xeddata/xeddata_test.go b/x86/xeddata/xeddata_test.go index ad0de1ec..8b64be4a 100644 --- a/x86/xeddata/xeddata_test.go +++ b/x86/xeddata/xeddata_test.go @@ -69,6 +69,12 @@ var ( "mem80real": {xtype: "f80", sizes: [3]string{"10", "10", "10"}}, "mfpxenv": {xtype: "struct", sizes: [3]string{"512", "512", "512"}}, } + + extraWidthsMap = map[string]string{ + "AGEN": "pseudo", + "XED_REG_EAX": "d", + "GPR32_R()": "d", + } ) // newStatesSource returns a reader that mocks "all-state.txt" file. @@ -118,6 +124,22 @@ func newWidthsSource() io.Reader { return &buf } +func newExtraWidthsSource() io.Reader { + var buf bytes.Buffer + for name, width := range extraWidthsMap { + buf.WriteString("# Line comment\n") + buf.WriteString("#\n\n\n") + if reg, ok := strings.CutPrefix(name, "XED_REG_"); ok { + fmt.Fprintf(&buf, "reg %s %s\n", reg, width) + } else if nt, ok := strings.CutSuffix(name, "()"); ok { + fmt.Fprintf(&buf, "nt %s %s\n", nt, width) + } else { + fmt.Fprintf(&buf, "imm_const %s %s\n", name, width) + } + } + return &buf +} + // newXtypesSource returns a reader that mocks "all-element-types.txt" file. // Input content is generated based on xtypesMap. func newXtypesSource() io.Reader { @@ -150,6 +172,10 @@ func newTestDatabase(t *testing.T) *Database { if err != nil { t.Fatal(err) } + db.extraWidths, err = parseExtraWidths(newExtraWidthsSource()) + if err != nil { + t.Fatal(err) + } err = db.LoadXtypes(newXtypesSource()) if err != nil { t.Fatal(err) @@ -258,7 +284,7 @@ func TestNewOperand(t *testing.T) { }, { "MEM0:rw:q", - Operand{Name: "MEM0", Action: "rw", Width: "q"}, + Operand{Name: "MEM0", Action: "rw", Width: "q", Xtype: "i64"}, }, { "REG0=XMM_R():rcw:ps:f32", @@ -266,13 +292,27 @@ func TestNewOperand(t *testing.T) { }, { "IMM0:r:z", - Operand{Name: "IMM0", Action: "r", Width: "z"}, + Operand{Name: "IMM0", Action: "r", Width: "z", Xtype: "int"}, }, { "IMM1:cw:b:i8", Operand{Name: "IMM1", Action: "cw", Width: "b", Xtype: "i8"}, }, + // Implied width code + { + "AGEN:r", + Operand{Name: "AGEN", Action: "r", Width: "pseudo"}, + }, + { + "REG0=XED_REG_EAX:r", + Operand{Name: "REG0=XED_REG_EAX", Action: "r", Width: "d", Xtype: "i32"}, + }, + { + "REG0=GPR32_R():r", + Operand{Name: "REG0=GPR32_R()", Action: "r", Width: "d", Xtype: "i32"}, + }, + // Optional fields and visibility. { "REG2:r:EXPL", @@ -280,19 +320,19 @@ func TestNewOperand(t *testing.T) { }, { "MEM1:w:d:IMPL", - Operand{Name: "MEM1", Action: "w", Width: "d", Visibility: VisImplicit}, + Operand{Name: "MEM1", Action: "w", Width: "d", Xtype: "i32", Visibility: VisImplicit}, }, { "MEM1:w:IMPL:d", - Operand{Name: "MEM1", Action: "w", Width: "d", Visibility: VisImplicit}, + Operand{Name: "MEM1", Action: "w", Width: "d", Xtype: "i32", Visibility: VisImplicit}, }, { - "MEM1:w:d:SUPP:i32", - Operand{Name: "MEM1", Action: "w", Width: "d", Visibility: VisSuppressed, Xtype: "i32"}, + "MEM1:w:d:SUPP:f32", + Operand{Name: "MEM1", Action: "w", Width: "d", Visibility: VisSuppressed, Xtype: "f32"}, }, { - "MEM1:w:SUPP:d:i32", - Operand{Name: "MEM1", Action: "w", Width: "d", Visibility: VisSuppressed, Xtype: "i32"}, + "MEM1:w:SUPP:d:f32", + Operand{Name: "MEM1", Action: "w", Width: "d", Visibility: VisSuppressed, Xtype: "f32"}, }, // Ambiguity: xtypes that look like widths. @@ -304,7 +344,7 @@ func TestNewOperand(t *testing.T) { // TXT=X field. { "REG1=MASK1():r:mskw:TXT=ZEROSTR", - Operand{Name: "REG1=MASK1()", Action: "r", Width: "mskw", + Operand{Name: "REG1=MASK1()", Action: "r", Width: "mskw", Xtype: "i1", Attributes: map[string]bool{"TXT=ZEROSTR": true}}, }, { @@ -314,26 +354,26 @@ func TestNewOperand(t *testing.T) { }, { "REG0=ZMM_R3():w:zf32:TXT=SAESTR", - Operand{Name: "REG0=ZMM_R3()", Action: "w", Width: "zf32", + Operand{Name: "REG0=ZMM_R3()", Action: "w", Width: "zf32", Xtype: "f32", Attributes: map[string]bool{"TXT=SAESTR": true}}, }, { "REG0=ZMM_R3():w:zf64:TXT=ROUNDC", - Operand{Name: "REG0=ZMM_R3()", Action: "w", Width: "zf64", + Operand{Name: "REG0=ZMM_R3()", Action: "w", Width: "zf64", Xtype: "f64", Attributes: map[string]bool{"TXT=ROUNDC": true}}, }, // Multi-source. { "REG2=ZMM_N3():r:zf32:MULTISOURCE4", - Operand{Name: "REG2=ZMM_N3()", Action: "r", Width: "zf32", + Operand{Name: "REG2=ZMM_N3()", Action: "r", Width: "zf32", Xtype: "f32", Attributes: map[string]bool{"MULTISOURCE4": true}}, }, // Multi-source + EVEX.b context. { "REG2=ZMM_N3():r:zf32:MULTISOURCE4:TXT=SAESTR", - Operand{Name: "REG2=ZMM_N3()", Action: "r", Width: "zf32", + Operand{Name: "REG2=ZMM_N3()", Action: "r", Width: "zf32", Xtype: "f32", Attributes: map[string]bool{"MULTISOURCE4": true, "TXT=SAESTR": true}}, }, } @@ -430,6 +470,42 @@ func TestReader(t *testing.T) { } } +func TestReaderPos(t *testing.T) { + const data = `# Comment +{ +ICLASS: iclass1 +DISASM: disasm1 + +PATTERN: pat1 pat1 +OPERANDS: ops1 ops1 +}` + r := NewReader(namedReader{strings.NewReader(data), "test"}) + objects, err := r.ReadAll() + if err != nil { + t.Fatal(err) + } + + if want := "test:2"; objects[0].Pos.String() != want { + t.Errorf("object Pos: got %q, want %q", objects[0].Pos, want) + } + if want := "test:6"; objects[0].Insts[0].Pos.String() != want { + t.Errorf("inst Pos: got %q, want %q", objects[0].Insts[0].Pos, want) + } +} + +type namedReader struct { + r io.Reader + name string +} + +func (n namedReader) Read(p []byte) (int, error) { + return n.r.Read(p) +} + +func (n namedReader) Name() string { + return n.name +} + func TestMacroExpand(t *testing.T) { tests := [...]struct { input string