Merge branch 'bugfix/fix_bss_clear' into 'master'

wujiangang · wujiangang · commit 4e15ca451a1b · 2018-08-10T11:26:31.000+08:00
Fix cached data is cleared by function of "clean bss"

See merge request sdk/ESP8266_RTOS_SDK!378
diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
@@ -494,6 +494,12 @@ static void set_cache_and_start_app(
 
 #include "esp_flash_partitions.h"
 
+#ifdef CONFIG_SOC_FULL_ICACHE
+#define SOC_CACHE_SIZE 1 // 32KB
+#else
+#define SOC_CACHE_SIZE 0 // 16KB
+#endif
+
 #define ESP_CACHE1_ADDR_MAX 0x100000
 #define ESP_CACHE2_ADDR_MAX 0x200000
 
@@ -777,7 +783,7 @@ bool bootloader_utility_load_boot_image(const bootloader_state_t *bs, int start_
 
 void bootloader_utility_load_image(const esp_image_metadata_t* image_data)
 {
-    void (*user_start)(size_t start_addr, size_t map);
+    void (*user_start)(size_t start_addr);
     extern void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v);
 
 #if defined(CONFIG_SECURE_BOOT_ENABLED) || defined(CONFIG_FLASH_ENCRYPTION_ENABLED)
@@ -838,10 +844,10 @@ void bootloader_utility_load_image(const esp_image_metadata_t* image_data)
         while (1);
     }
 
-    Cache_Read_Enable(map, 0, 0);
+    Cache_Read_Enable(map, 0, SOC_CACHE_SIZE);
 
     user_start = (void *)image_data->image.entry_addr;
-    user_start(image_data->start_addr, map);
+    user_start(image_data->start_addr);
 #endif /* BOOTLOADER_UNPACK_APP */
 }
 
diff --git a/components/esp8266/source/chip_boot.c b/components/esp8266/source/chip_boot.c
@@ -34,7 +34,7 @@ static const char *TAG = "chip_boot";
  * @brief initialize the chip including flash I/O and chip cache according to
  *        boot parameters which are stored at the flash
  */
-void chip_boot(size_t start_addr, size_t map)
+void chip_boot(size_t start_addr)
 {
     int ret;
     uint32_t freqdiv, flash_size;
@@ -91,9 +91,6 @@ void chip_boot(size_t start_addr, size_t map)
     }
     SET_PERI_REG_BITS(PERIPHS_SPI_FLASH_CTRL, 0xfff, freqbits, 0);
 
-    ESP_EARLY_LOGD(TAG, "SPI flash cache map is %d\n", map);
-    cache_init(map);
-
     if (fhdr.spi_mode == ESP_IMAGE_SPI_MODE_QIO) {
         ESP_EARLY_LOGD(TAG, "SPI flash enable QIO mode\n");
         user_spi_flash_dio_to_qio_pre_init();
diff --git a/components/esp8266/source/esp_cache.c b/components/esp8266/source/esp_cache.c
diff --git a/components/esp8266/source/startup.c b/components/esp8266/source/startup.c
@@ -30,7 +30,7 @@
 
 #define FLASH_MAP_ADDR 0x40200000
 
-extern void chip_boot(size_t start_addr, size_t map);
+extern void chip_boot(size_t start_addr);
 extern int rtc_init(void);
 extern int mac_init(void);
 extern int base_gpio_init(void);
@@ -68,7 +68,7 @@ static void user_init_entry(void *param)
     wifi_task_delete(NULL);
 }
 
-void call_user_start(size_t start_addr, size_t map)
+void call_user_start(size_t start_addr)
 {
     int i;
     int *p;
@@ -98,7 +98,7 @@ void call_user_start(size_t start_addr, size_t map)
         "wsr        a0, vecbase\n"
         : : :"memory");
 
-    chip_boot(start_addr, map);
+    chip_boot(start_addr);
 
     /* clear bss data */
     for (p = &_bss_start; p < &_bss_end; p++)
diff --git a/components/spi_flash/src/spi_flash.c b/components/spi_flash/src/spi_flash.c
@@ -229,11 +229,12 @@ static void IRAM_ATTR Cache_Read_Disable_2(void)
     CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL,SPI_ENABLE_AHB);
 }
 
-static void IRAM_ATTR Cache_Read_Enable_2()
+void IRAM_ATTR Cache_Read_Enable_2()
 {
     SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL,SPI_ENABLE_AHB);
     SET_PERI_REG_MASK(CACHE_FLASH_CTRL_REG,CACHE_READ_EN_BIT);
 }
+void Cache_Read_Enable_New(void) __attribute__((alias("Cache_Read_Enable_2")));
 
 static uint32_t IRAM_ATTR spi_flash_get_id(void)
 {

Original file line number	Diff line number	Diff line change
`@@ -229,11 +229,12 @@ static void IRAM_ATTR Cache_Read_Disable_2(void)`
`229`	`229`	`CLEAR_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL,SPI_ENABLE_AHB);`
`230`	`230`	`}`
`231`	`231`
`232`		`-static void IRAM_ATTR Cache_Read_Enable_2()`
	`232`	`+void IRAM_ATTR Cache_Read_Enable_2()`
`233`	`233`	`{`
`234`	`234`	`SET_PERI_REG_MASK(PERIPHS_SPI_FLASH_CTRL,SPI_ENABLE_AHB);`
`235`	`235`	`SET_PERI_REG_MASK(CACHE_FLASH_CTRL_REG,CACHE_READ_EN_BIT);`
`236`	`236`	`}`
	`237`	`+void Cache_Read_Enable_New(void) __attribute__((alias("Cache_Read_Enable_2")));`
`237`	`238`
`238`	`239`	`static uint32_t IRAM_ATTR spi_flash_get_id(void)`
`239`	`240`	`{`