stm32/powerctrlboot: Add support for HSI at 8MHz on F0 MCUs.

chrismas9 · dpgeorge · commit eb12fa38624a · 2019-09-26T17:34:04.000+10:00
For use with F0 MCUs that don't have HSI48.  Select the clock source
explicitly in mpconfigboard.h.

On the NUCLEO_F091RC board use HSE bypass when HSE is chosen because the
NUCLEO clock source is STLINK not a crystal.
diff --git a/ports/stm32/boards/NUCLEO_F091RC/mpconfigboard.h b/ports/stm32/boards/NUCLEO_F091RC/mpconfigboard.h
@@ -16,8 +16,14 @@
 #define MICROPY_HW_ENABLE_TIMER     (1)
 #define MICROPY_HW_HAS_SWITCH       (1)
 
-// For system clock, board uses internal 48MHz, HSI48
-#define MICROPY_HW_CLK_USE_HSI48    (1)
+// For system clock, enable one source:
+//#define MICROPY_HW_CLK_USE_HSI      (1) // internal 8MHz -> PLL = 48MHz.
+#define MICROPY_HW_CLK_USE_HSI48    (1) // internal 48MHz.
+//#define MICROPY_HW_CLK_USE_HSE      (1) // external crystal -> PLL = 48MHz.
+// For HSE set the crystal / clock input frequency HSE_VALUE in stm32f0xx_hal_conf.h
+#if MICROPY_HW_CLK_USE_HSE
+#define MICROPY_HW_CLK_USE_BYPASS   (1) // HSE comes from STLINK 8MHz, not crystal.
+#endif
 
 // The board has an external 32kHz crystal
 #define MICROPY_HW_RTC_USE_LSE      (1)
diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c
@@ -48,7 +48,7 @@ void SystemClock_Config(void) {
     RCC->CFGR = 0 << RCC_CFGR_PLLMUL_Pos | 3 << RCC_CFGR_PLLSRC_Pos; // PLL mult by 2, src = HSI48/PREDIV
     RCC->CFGR2 = 1; // Input clock divided by 2
 
-    #else
+    #elif MICROPY_HW_CLK_USE_HSE
     // Use HSE and the PLL to get a 48MHz SYSCLK
 
     #if MICROPY_HW_CLK_USE_BYPASS
@@ -61,6 +61,18 @@ void SystemClock_Config(void) {
     RCC->CFGR = ((48000000 / HSE_VALUE) - 2) << RCC_CFGR_PLLMUL_Pos | 2 << RCC_CFGR_PLLSRC_Pos;
     RCC->CFGR2 = 0; // Input clock not divided
 
+    #elif MICROPY_HW_CLK_USE_HSI
+    // Use the 8MHz internal oscillator and the PLL to get a 48MHz SYSCLK
+
+    RCC->CR |= RCC_CR_HSION;
+    while ((RCC->CR & RCC_CR_HSIRDY) == 0) {
+        // Wait for HSI to be ready
+    }
+    RCC->CFGR = 4 << RCC_CFGR_PLLMUL_Pos | 1 << RCC_CFGR_PLLSRC_Pos; // PLL mult by 6, src = HSI
+    RCC->CFGR2 = 0; // Input clock not divided
+
+    #else
+    #error System clock not specified
     #endif
 
     RCC->CR |= RCC_CR_PLLON; // Turn PLL on
