From 09ad692e7c83146061bd3d9688277e1de2fbb4ea Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Thu, 4 Sep 2025 13:39:32 -0700 Subject: [PATCH] [AMDGPU] Print high vgpr operand comments from objdump This followed the agreed convention: every basic block shall start with all MSBs zero. Codegen does the same lowering. --- .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 39 +++++++++++++++ .../MCTargetDesc/AMDGPUMCTargetDesc.cpp | 48 ++++++++++--------- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 23 +++++++++ .../CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir | 1 + 4 files changed, 89 insertions(+), 22 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index d1e8b7e4bad0d..f098e7a3c6c67 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -336,6 +336,42 @@ static MCPhysReg getRegForPrinting(MCPhysReg Reg, const MCRegisterInfo &MRI) { return RC->getRegister(Idx % 0x100); } +// Restore MSBs of a VGPR above 255 from the MCInstrAnalysis. +static MCPhysReg getRegFromMIA(MCPhysReg Reg, unsigned OpNo, + const MCInstrDesc &Desc, + const MCRegisterInfo &MRI, + const AMDGPUMCInstrAnalysis &MIA) { + unsigned VgprMSBs = MIA.getVgprMSBs(); + if (!VgprMSBs) + return Reg; + + unsigned Enc = MRI.getEncodingValue(Reg); + if (!(Enc & AMDGPU::HWEncoding::IS_VGPR)) + return Reg; + + auto Ops = AMDGPU::getVGPRLoweringOperandTables(Desc); + if (!Ops.first) + return Reg; + unsigned Opc = Desc.getOpcode(); + unsigned I; + for (I = 0; I < 4; ++I) { + if (Ops.first[I] != AMDGPU::OpName::NUM_OPERAND_NAMES && + (unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.first[I]) == OpNo) + break; + if (Ops.second && Ops.second[I] != AMDGPU::OpName::NUM_OPERAND_NAMES && + (unsigned)AMDGPU::getNamedOperandIdx(Opc, Ops.second[I]) == OpNo) + break; + } + if (I == 4) + return Reg; + unsigned OpMSBs = (VgprMSBs >> (I * 2)) & 3; + if (!OpMSBs) + return Reg; + if (MCRegister NewReg = AMDGPU::getVGPRWithMSBs(Reg, OpMSBs, MRI)) + return NewReg; + return Reg; +} + void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, raw_ostream &O, const MCRegisterInfo &MRI) { #if !defined(NDEBUG) @@ -359,6 +395,9 @@ void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, raw_ostream &O, void AMDGPUInstPrinter::printRegOperand(MCRegister Reg, unsigned Opc, unsigned OpNo, raw_ostream &O, const MCRegisterInfo &MRI) { + if (MIA) + Reg = getRegFromMIA(Reg, OpNo, MII.get(Opc), MRI, + *static_cast(MIA)); printRegOperand(Reg, O, MRI); } diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp index d66725d3a6c4b..90c56f6901460 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -21,9 +21,9 @@ #include "TargetInfo/AMDGPUTargetInfo.h" #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCContext.h" #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCInstPrinter.h" -#include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectWriter.h" @@ -130,31 +130,35 @@ static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context, std::move(Emitter)); } -namespace { - -class AMDGPUMCInstrAnalysis : public MCInstrAnalysis { -public: - explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info) - : MCInstrAnalysis(Info) {} - - bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, - uint64_t &Target) const override { - if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() || - Info->get(Inst.getOpcode()).operands()[0].OperandType != - MCOI::OPERAND_PCREL) - return false; +namespace llvm { +namespace AMDGPU { + +bool AMDGPUMCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, + uint64_t Size, + uint64_t &Target) const { + if (Inst.getNumOperands() == 0 || !Inst.getOperand(0).isImm() || + Info->get(Inst.getOpcode()).operands()[0].OperandType != + MCOI::OPERAND_PCREL) + return false; + + int64_t Imm = Inst.getOperand(0).getImm(); + // Our branches take a simm16. + Target = SignExtend64<16>(Imm) * 4 + Addr + Size; + return true; +} - int64_t Imm = Inst.getOperand(0).getImm(); - // Our branches take a simm16. - Target = SignExtend64<16>(Imm) * 4 + Addr + Size; - return true; - } -}; +void AMDGPUMCInstrAnalysis::updateState(const MCInst &Inst, uint64_t Addr) { + if (Inst.getOpcode() == AMDGPU::S_SET_VGPR_MSB_gfx12) + VgprMSBs = Inst.getOperand(0).getImm(); + else if (isTerminator(Inst)) + VgprMSBs = 0; +} -} // end anonymous namespace +} // end namespace AMDGPU +} // end namespace llvm static MCInstrAnalysis *createAMDGPUMCInstrAnalysis(const MCInstrInfo *Info) { - return new AMDGPUMCInstrAnalysis(Info); + return new AMDGPU::AMDGPUMCInstrAnalysis(Info); } extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h index 9c0b2da0fcb0a..9863884140969 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -15,6 +15,7 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H +#include "llvm/MC/MCInstrAnalysis.h" #include #include @@ -44,6 +45,28 @@ MCAsmBackend *createAMDGPUAsmBackend(const Target &T, std::unique_ptr createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend); + +namespace AMDGPU { +class AMDGPUMCInstrAnalysis : public MCInstrAnalysis { +private: + unsigned VgprMSBs = 0; + +public: + explicit AMDGPUMCInstrAnalysis(const MCInstrInfo *Info) + : MCInstrAnalysis(Info) {} + + bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, + uint64_t &Target) const override; + + void resetState() override { VgprMSBs = 0; } + + void updateState(const MCInst &Inst, uint64_t Addr) override; + + unsigned getVgprMSBs() const { return VgprMSBs; } +}; + +} // namespace AMDGPU + } // namespace llvm #define GET_REGINFO_ENUM diff --git a/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir b/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir index e7d676c6ba05c..f508df2292e90 100644 --- a/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir +++ b/llvm/test/CodeGen/AMDGPU/vgpr-lowering-gfx1250.mir @@ -1,4 +1,5 @@ # RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -start-before=amdgpu-lower-vgpr-encoding -o - %s | FileCheck -check-prefixes=GCN,ASM %s +# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -start-before=amdgpu-lower-vgpr-encoding -o - %s | llvm-mc -triple=amdgcn -mcpu=gfx1250 -filetype=obj -o - | llvm-objdump -d --mcpu=gfx1250 - | FileCheck -check-prefixes=GCN,DIS %s # ASM-LABEL: {{^}}high_vgprs: # DIS-LABEL: :