diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 780e8a31cae6d..8522f4123cd97 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -379,6 +379,10 @@ X86 Support - NOTE: Please avoid use of the __builtin_ia32_* intrinsics - these are not guaranteed to exist in future releases, or match behaviour with previous releases of clang or other compilers. +- Remove `m[no-]avx10.x-[256,512]` and `m[no-]evex512` options from Clang + driver. +- Remove `[no-]evex512` feature request from intrinsics and builtins. +- Change features `avx10.x-[256,512]` to `avx10.x`. Arm and AArch64 Support ^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index 0e85c8109fd5e..a8bbf146431ea 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -4581,59 +4581,14 @@ implicitly included in later levels. - ``-march=x86-64-v3``: (close to Haswell) AVX, AVX2, BMI1, BMI2, F16C, FMA, LZCNT, MOVBE, XSAVE - ``-march=x86-64-v4``: AVX512F, AVX512BW, AVX512CD, AVX512DQ, AVX512VL -`Intel AVX10 ISA `_ is +`Intel AVX10 ISA `_ is a major new vector ISA incorporating the modern vectorization aspects of Intel AVX-512. This ISA will be supported on all future Intel processors. -Users are supposed to use the new options ``-mavx10.N`` and ``-mavx10.N-512`` -on these processors and should not use traditional AVX512 options anymore. - -The ``N`` in ``-mavx10.N`` represents a continuous integer number starting -from ``1``. ``-mavx10.N`` is an alias of ``-mavx10.N-256``, which means to -enable all instructions within AVX10 version N at a maximum vector length of -256 bits. ``-mavx10.N-512`` enables all instructions at a maximum vector -length of 512 bits, which is a superset of instructions ``-mavx10.N`` enabled. - -Current binaries built with AVX512 features can run on Intel AVX10/512 capable -processors without re-compile, but cannot run on AVX10/256 capable processors. -Users need to re-compile their code with ``-mavx10.N``, and maybe update some -code that calling to 512-bit X86 specific intrinsics and passing or returning -512-bit vector types in function call, if they want to run on AVX10/256 capable -processors. Binaries built with ``-mavx10.N`` can run on both AVX10/256 and -AVX10/512 capable processors. - -Users can add a ``-mno-evex512`` in the command line with AVX512 options if -they want to run the binary on both legacy AVX512 and new AVX10/256 capable -processors. The option has the same constraints as ``-mavx10.N``, i.e., -cannot call to 512-bit X86 specific intrinsics and pass or return 512-bit vector -types in function call. - -Users should avoid using AVX512 features in function target attributes when -developing code for AVX10. If they have to do so, they need to add an explicit -``evex512`` or ``no-evex512`` together with AVX512 features for 512-bit or -non-512-bit functions respectively to avoid unexpected code generation. Both -command line option and target attribute of EVEX512 feature can only be used -with AVX512. They don't affect vector size of AVX10. - -User should not mix the use AVX10 and AVX512 options together at any time, -because the option combinations are conflicting sometimes. For example, a -combination of ``-mavx512f -mavx10.1-256`` doesn't show a clear intention to -compiler, since instructions in AVX512F and AVX10.1/256 intersect but do not -overlap. In this case, compiler will emit warning for it, but the behavior -is determined. It will generate the same code as option ``-mavx10.1-512``. -A similar case is ``-mavx512f -mavx10.2-256``, which equals to -``-mavx10.1-512 -mavx10.2-256``, because ``avx10.2-256`` implies ``avx10.1-256`` -and ``-mavx512f -mavx10.1-256`` equals to ``-mavx10.1-512``. - -There are some new macros introduced with AVX10 support. ``-mavx10.1-256`` will -enable ``__AVX10_1__`` and ``__EVEX256__``, while ``-mavx10.1-512`` enables -``__AVX10_1__``, ``__EVEX256__``, ``__EVEX512__`` and ``__AVX10_1_512__``. -Besides, both ``-mavx10.1-256`` and ``-mavx10.1-512`` will enable all AVX512 -feature specific macros. A AVX512 feature will enable both ``__EVEX256__``, -``__EVEX512__`` and its own macro. So ``__EVEX512__`` can be used to guard code -that can run on both legacy AVX512 and AVX10/512 capable processors but cannot -run on AVX10/256, while a AVX512 macro like ``__AVX512F__`` cannot tell the -difference among the three options. Users need to check additional macros -``__AVX10_1__`` and ``__EVEX512__`` if they want to make distinction. +Users are supposed to use the new options ``-mavx10.N`` on these processors +and should not use traditional AVX512 options anymore. The ``N`` in +``-mavx10.N`` represents a continuous integer number starting +from ``1``. Current binaries built with AVX512 features can run on Intel AVX10 +capable processors without re-compile. ARM ^^^ diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td index 0d44e78f879b9..0b97f4770b0bd 100644 --- a/clang/include/clang/Basic/BuiltinsX86.td +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -387,7 +387,7 @@ let Features = "vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def aesenc256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def aesenc512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -395,7 +395,7 @@ let Features = "vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def aesenclast256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def aesenclast512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -403,7 +403,7 @@ let Features = "vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def aesdec256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def aesdec512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -411,7 +411,7 @@ let Features = "vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def aesdeclast256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vaes", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def aesdeclast512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -423,7 +423,7 @@ let Features = "avx,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vgf2p8affineinvqb_v32qi : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>, _Constant char)">; } -let Features = "avx512f,evex512,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vgf2p8affineinvqb_v64qi : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>, _Constant char)">; } @@ -435,7 +435,7 @@ let Features = "avx,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vgf2p8affineqb_v32qi : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>, _Constant char)">; } -let Features = "avx512f,evex512,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vgf2p8affineqb_v64qi : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>, _Constant char)">; } @@ -447,7 +447,7 @@ let Features = "avx,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vgf2p8mulb_v32qi : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>)">; } -let Features = "avx512f,evex512,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,gfni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vgf2p8mulb_v64qi : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>)">; } @@ -459,7 +459,7 @@ let Features = "vpclmulqdq", Attributes = [NoThrow, Const, RequiredVectorWidth<2 def pclmulqdq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Constant char)">; } -let Features = "avx512f,evex512,vpclmulqdq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f,vpclmulqdq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pclmulqdq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Constant char)">; } @@ -830,7 +830,7 @@ let Features = "fma|fma4", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vfmaddsubpd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>, _Vector<4, double>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfmaddpd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, double>, unsigned char, _Constant int)">; def vfmaddpd512_maskz : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, double>, unsigned char, _Constant int)">; def vfmaddpd512_mask3 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, double>, unsigned char, _Constant int)">; @@ -936,7 +936,7 @@ let Features = "pku", Attributes = [NoThrow] in { def wrpkru : X86Builtin<"void(unsigned int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def sqrtpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Constant int)">; def sqrtps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Constant int)">; } @@ -946,7 +946,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def rsqrt14ss_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Vector<4, float>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rsqrt14pd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, unsigned char)">; def rsqrt14ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, unsigned short)">; } @@ -956,7 +956,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def rcp14ss_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Vector<4, float>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rcp14pd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, unsigned char)">; def rcp14ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, unsigned short)">; def cvttps2dq512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, float>, _Vector<16, int>, unsigned short, _Constant int)">; @@ -974,7 +974,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128 def cmpps128_mask : X86Builtin<"unsigned char(_Vector<4, float>, _Vector<4, float>, _Constant int, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cmppd512_mask : X86Builtin<"unsigned char(_Vector<8, double>, _Vector<8, double>, _Constant int, unsigned char, _Constant int)">; } @@ -986,7 +986,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<128 def cmppd128_mask : X86Builtin<"unsigned char(_Vector<2, double>, _Vector<2, double>, _Constant int, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rndscaleps_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Constant int, _Vector<16, float>, unsigned short, _Constant int)">; def rndscalepd_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Constant int, _Vector<8, double>, unsigned char, _Constant int)">; def cvtps2dq512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, float>, _Vector<16, int>, unsigned short, _Constant int)">; @@ -1004,12 +1004,12 @@ let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWi def vcvtph2ps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, short>, _Vector<16, float>, unsigned short, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def pmuldq512 : X86Builtin<"_Vector<8, long long int>(_Vector<16, int>, _Vector<16, int>)">; def pmuludq512 : X86Builtin<"_Vector<8, long long int>(_Vector<16, int>, _Vector<16, int>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def loaddqusi512_mask : X86Builtin<"_Vector<16, int>(int const *, _Vector<16, int>, unsigned short)">; def loaddqudi512_mask : X86Builtin<"_Vector<8, long long int>(long long int const *, _Vector<8, long long int>, unsigned char)">; def loadups512_mask : X86Builtin<"_Vector<16, float>(float const *, _Vector<16, float>, unsigned short)">; @@ -1024,7 +1024,7 @@ let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512 def storeaps512_mask : X86Builtin<"void(_Vector<16, float *>, _Vector<16, float>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def alignq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Constant int)">; def alignd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Constant int)">; } @@ -1045,7 +1045,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def alignq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def extractf64x4_mask : X86Builtin<"_Vector<4, double>(_Vector<8, double>, _Constant int, _Vector<4, double>, unsigned char)">; def extractf32x4_mask : X86Builtin<"_Vector<4, float>(_Vector<16, float>, _Constant int, _Vector<4, float>, unsigned char)">; } @@ -1058,7 +1058,7 @@ let Features = "avx512vl,avx512vnni|avxvnni", Attributes = [NoThrow, Const, Requ def vpdpbusd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512vnni,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vnni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpdpbusd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } @@ -1070,7 +1070,7 @@ let Features = "avx512vl,avx512vnni|avxvnni", Attributes = [NoThrow, Const, Requ def vpdpbusds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512vnni,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vnni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpdpbusds512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } @@ -1082,7 +1082,7 @@ let Features = "avx512vl,avx512vnni|avxvnni", Attributes = [NoThrow, Const, Requ def vpdpwssd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512vnni,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vnni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpdpwssd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } @@ -1094,55 +1094,55 @@ let Features = "avx512vl,avx512vnni|avxvnni", Attributes = [NoThrow, Const, Requ def vpdpwssds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512vnni,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vnni", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpdpwssds512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbssd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbssd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbssds128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbssds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbsud128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbsud256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbsuds128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbsuds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbuud128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbuud256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vpdpbuuds128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint8|avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avxvnniint8|avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vpdpbuuds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } @@ -1190,7 +1190,7 @@ let Features = "avx512vl", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def gather3siv8si : X86Builtin<"_Vector<8, int>(_Vector<8, int>, void const *, _Vector<8, int>, unsigned char, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def gathersiv8df : X86Builtin<"_Vector<8, double>(_Vector<8, double>, void const *, _Vector<8, int>, unsigned char, _Constant int)">; def gathersiv16sf : X86Builtin<"_Vector<16, float>(_Vector<16, float>, void const *, _Vector<16, int>, unsigned short, _Constant int)">; def gatherdiv8df : X86Builtin<"_Vector<8, double>(_Vector<8, double>, void const *, _Vector<8, long long int>, unsigned char, _Constant int)">; @@ -1248,16 +1248,16 @@ let Features = "avx512vl,avx512bw", Attributes = [NoThrow, Const, RequiredVector def cmpw256_mask : X86Builtin<"unsigned short(_Vector<16, short>, _Vector<16, short>, _Constant int, unsigned short)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cmpb512_mask : X86Builtin<"unsigned long long int(_Vector<64, char>, _Vector<64, char>, _Constant int, unsigned long long int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cmpd512_mask : X86Builtin<"unsigned short(_Vector<16, int>, _Vector<16, int>, _Constant int, unsigned short)">; def cmpq512_mask : X86Builtin<"unsigned char(_Vector<8, long long int>, _Vector<8, long long int>, _Constant int, unsigned char)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cmpw512_mask : X86Builtin<"unsigned int(_Vector<32, short>, _Vector<32, short>, _Constant int, unsigned int)">; } @@ -1287,16 +1287,16 @@ let Features = "avx512vl,avx512bw", Attributes = [NoThrow, Const, RequiredVector def ucmpw256_mask : X86Builtin<"unsigned short(_Vector<16, short>, _Vector<16, short>, _Constant int, unsigned short)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def ucmpb512_mask : X86Builtin<"unsigned long long int(_Vector<64, char>, _Vector<64, char>, _Constant int, unsigned long long int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def ucmpd512_mask : X86Builtin<"unsigned short(_Vector<16, int>, _Vector<16, int>, _Constant int, unsigned short)">; def ucmpq512_mask : X86Builtin<"unsigned char(_Vector<8, long long int>, _Vector<8, long long int>, _Constant int, unsigned char)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def ucmpw512_mask : X86Builtin<"unsigned int(_Vector<32, short>, _Vector<32, short>, _Constant int, unsigned int)">; def packssdw512 : X86Builtin<"_Vector<32, short>(_Vector<16, int>, _Vector<16, int>)">; def packsswb512 : X86Builtin<"_Vector<64, char>(_Vector<32, short>, _Vector<32, short>)">; @@ -1323,7 +1323,7 @@ let Features = "avx512cd,avx512vl", Attributes = [NoThrow, Const, RequiredVector def vpconflictsi_256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>)">; } -let Features = "avx512cd,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512cd", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpconflictdi_512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>)">; def vpconflictsi_512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>)">; } @@ -1336,20 +1336,20 @@ let Features = "avx512vl,avx512bitalg", Attributes = [NoThrow, Const, RequiredVe def vpshufbitqmb256_mask : X86Builtin<"unsigned int(_Vector<32, char>, _Vector<32, char>, unsigned int)">; } -let Features = "avx512bitalg,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bitalg", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpshufbitqmb512_mask : X86Builtin<"unsigned long long int(_Vector<64, char>, _Vector<64, char>, unsigned long long int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmulhrsw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def pmulhuw512 : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, unsigned short>, _Vector<32, unsigned short>)">; def pmulhw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def addpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Constant int)">; def addps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Constant int)">; def divpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Constant int)">; @@ -1360,7 +1360,7 @@ let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWi def subps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Constant int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmaddubsw512 : X86Builtin<"_Vector<32, short>(_Vector<64, char>, _Vector<64, char>)">; def pmaddwd512 : X86Builtin<"_Vector<16, int>(_Vector<32, short>, _Vector<32, short>)">; } @@ -1703,7 +1703,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vpermi2vard256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpermi2vard512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } @@ -1715,7 +1715,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vpermi2varpd256 : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, long long int>, _Vector<4, double>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpermi2varpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, long long int>, _Vector<8, double>)">; } @@ -1727,7 +1727,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vpermi2varps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, int>, _Vector<8, float>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpermi2varps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, int>, _Vector<16, float>)">; } @@ -1739,7 +1739,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vpermi2varq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpermi2varq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -1751,7 +1751,7 @@ let Features = "avx512vbmi,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vpermi2varqi256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>, _Vector<32, char>)">; } -let Features = "avx512vbmi,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpermi2varqi512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>, _Vector<64, char>)">; } @@ -1763,7 +1763,7 @@ let Features = "avx512vl,avx512bw", Attributes = [NoThrow, Const, RequiredVector def vpermi2varhi256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<16, short>, _Vector<16, short>)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpermi2varhi512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>, _Vector<32, short>)">; } @@ -1775,7 +1775,7 @@ let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVec def vpshldd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Constant int)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpshldd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Constant int)">; } @@ -1787,7 +1787,7 @@ let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVec def vpshldq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Constant int)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpshldq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Constant int)">; } @@ -1799,7 +1799,7 @@ let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVec def vpshldw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<16, short>, _Constant int)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpshldw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>, _Constant int)">; } @@ -1811,7 +1811,7 @@ let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVec def vpshrdd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Constant int)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpshrdd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Constant int)">; } @@ -1823,7 +1823,7 @@ let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVec def vpshrdq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Constant int)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpshrdq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Constant int)">; } @@ -1835,11 +1835,11 @@ let Features = "avx512vl,avx512vbmi2", Attributes = [NoThrow, Const, RequiredVec def vpshrdw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<16, short>, _Constant int)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpshrdw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>, _Constant int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovswb512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, short>, _Vector<32, char>, unsigned int)">; def pmovuswb512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, short>, _Vector<32, char>, unsigned int)">; def pmovwb512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, short>, _Vector<32, char>, unsigned int)">; @@ -1973,7 +1973,7 @@ let Features = "avx512vl,avx512bw", Attributes = [NoThrow, Const, RequiredVector def pmovwb128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, short>, _Vector<16, char>, unsigned char)">; } -let Features = "avx512dq,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512dq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cvtpd2qq512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, double>, _Vector<8, long long int>, unsigned char, _Constant int)">; def cvtpd2uqq512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, double>, _Vector<8, long long int>, unsigned char, _Constant int)">; def cvtps2qq512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, float>, _Vector<8, long long int>, unsigned char, _Constant int)">; @@ -1992,7 +1992,7 @@ let Features = "avx512dq,evex512", Attributes = [NoThrow, Const, RequiredVectorW def reduceps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Constant int, _Vector<16, float>, unsigned short, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def psllv16si : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">; def psrav16si : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">; def psrlv16si : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">; @@ -2017,7 +2017,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVect def prorq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Constant int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pshufhw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Constant int)">; def pshuflw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Constant int)">; def psllv32hi : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>)">; @@ -2032,14 +2032,14 @@ let Features = "avx512bw,avx512vl", Attributes = [NoThrow, Const, RequiredVector def psllv8hi : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; } -let Features = "avx512f,evex512", +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def psllwi512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, int)">; def pslldi512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, int)">; def psllqi512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def psrlv32hi : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>)">; } @@ -2051,14 +2051,14 @@ let Features = "avx512bw,avx512vl", Attributes = [NoThrow, Const, RequiredVector def psrlv8hi : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; } -let Features = "avx512f,evex512", +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def psrlwi512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, int)">; def psrldi512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, int)">; def psrlqi512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def psrav32hi : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>)">; } @@ -2078,7 +2078,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def psravq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def psraw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<8, short>)">; def psrlw512 @@ -2095,7 +2095,7 @@ let Features = "avx512vl", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def movdqa32load256_mask : X86Builtin<"_Vector<8, int>(_Vector<8, int const *>, _Vector<8, int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def movdqa32load512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, int const *>, _Vector<16, int>, unsigned short)">; def movdqa32store512_mask : X86Builtin<"void(_Vector<16, int *>, _Vector<16, int>, unsigned short)">; def movdqa64load512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int const *>, _Vector<8, long long int>, unsigned char)">; @@ -2126,7 +2126,7 @@ let Features = "avx512vl", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def movdqa64store256_mask : X86Builtin<"void(_Vector<4, long long int *>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx512ifma,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512ifma", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpmadd52huq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Vector<8, long long int>)">; def vpmadd52luq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -2157,12 +2157,12 @@ let Features = "avx512bw", Attributes = [NoThrow, Const] in { def kunpcksi : X86Builtin<"unsigned int(unsigned int, unsigned int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def loaddquhi512_mask : X86Builtin<"_Vector<32, short>(_Vector<32, short const *>, _Vector<32, short>, unsigned int)">; def loaddquqi512_mask : X86Builtin<"_Vector<64, char>(_Vector<64, char const *>, _Vector<64, char>, unsigned long long int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def fixupimmpd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, long long int>, _Constant int, unsigned char, _Constant int)">; def fixupimmpd512_maskz : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, long long int>, _Constant int, unsigned char, _Constant int)">; def fixupimmps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, int>, _Constant int, unsigned short, _Constant int)">; @@ -2272,7 +2272,7 @@ let Features = "avx512vl", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def loadups256_mask : X86Builtin<"_Vector<8, float>(_Vector<8, float const *>, _Vector<8, float>, unsigned char)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def storedquhi512_mask : X86Builtin<"void(_Vector<32, short *>, _Vector<32, short>, unsigned int)">; def storedquqi512_mask : X86Builtin<"void(_Vector<64, char *>, _Vector<64, char>, unsigned long long int)">; } @@ -2376,7 +2376,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def vcvttss2usi32 : X86Builtin<"unsigned int(_Vector<4, float>, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpermilpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Constant int)">; def vpermilps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Constant int)">; def vpermilvarpd512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, long long int>)">; @@ -2388,7 +2388,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def rndscaless_round_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Vector<4, float>, unsigned char, _Constant int, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def scalefpd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Vector<8, double>, unsigned char, _Constant int)">; def scalefps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; } @@ -2398,7 +2398,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def scalefss_round_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Vector<4, float>, unsigned char, _Constant int)">; } -let Features = "avx512f,evex512", +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def psrawi512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, int)">; def psradi512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, int)">; @@ -2423,7 +2423,7 @@ let Features = "avx512vl", def psraqi256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pslld512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<4, int>)">; def psllq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<2, long long int>)">; def psllv8di : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; @@ -2459,7 +2459,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def pternlogq256_maskz : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int>, _Vector<4, long long int>, _Vector<4, long long int>, _Constant int, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def shuf_f32x4 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Constant int)">; def shuf_f64x2 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Constant int)">; def shuf_i32x4 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Constant int)">; @@ -2496,13 +2496,13 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def rsqrt14ps256_mask : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, unsigned char)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cvtb2mask512 : X86Builtin<"unsigned long long int(_Vector<64, char>)">; def cvtmask2b512 : X86Builtin<"_Vector<64, char>(unsigned long long int)">; def cvtmask2w512 : X86Builtin<"_Vector<32, short>(unsigned int)">; } -let Features = "avx512dq,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512dq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cvtd2mask512 : X86Builtin<"unsigned short(_Vector<16, int>)">; def cvtmask2d512 : X86Builtin<"_Vector<16, int>(unsigned short)">; def cvtmask2q512 : X86Builtin<"_Vector<8, long long int>(unsigned char)">; @@ -2565,47 +2565,47 @@ let Features = "avx512dq,avx512vl", Attributes = [NoThrow, Const, RequiredVector def cvtq2mask256 : X86Builtin<"unsigned char(_Vector<4, long long int>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovsdb512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, int>, _Vector<16, char>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovsdb512mem_mask : X86Builtin<"void(_Vector<16, char *>, _Vector<16, int>, unsigned short)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovswb512mem_mask : X86Builtin<"void(_Vector<32, char *>, _Vector<32, short>, unsigned int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovsdw512_mask : X86Builtin<"_Vector<16, short>(_Vector<16, int>, _Vector<16, short>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovsdw512mem_mask : X86Builtin<"void(_Vector<16, short *>, _Vector<16, int>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovsqb512_mask : X86Builtin<"_Vector<16, char>(_Vector<8, long long int>, _Vector<16, char>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovsqb512mem_mask : X86Builtin<"void(_Vector<16, char *>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovsqd512_mask : X86Builtin<"_Vector<8, int>(_Vector<8, long long int>, _Vector<8, int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovsqd512mem_mask : X86Builtin<"void(_Vector<8, int *>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovsqw512_mask : X86Builtin<"_Vector<8, short>(_Vector<8, long long int>, _Vector<8, short>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovsqw512mem_mask : X86Builtin<"void(_Vector<8, short *>, _Vector<8, long long int>, unsigned char)">; } @@ -2697,47 +2697,47 @@ let Features = "avx512vl", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def pmovsqw256mem_mask : X86Builtin<"void(_Vector<8, short *>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovusdb512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, int>, _Vector<16, char>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovusdb512mem_mask : X86Builtin<"void(_Vector<16, char *>, _Vector<16, int>, unsigned short)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovuswb512mem_mask : X86Builtin<"void(_Vector<32, char *>, _Vector<32, short>, unsigned int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovusdw512_mask : X86Builtin<"_Vector<16, short>(_Vector<16, int>, _Vector<16, short>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovusdw512mem_mask : X86Builtin<"void(_Vector<16, short *>, _Vector<16, int>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovusqb512_mask : X86Builtin<"_Vector<16, char>(_Vector<8, long long int>, _Vector<16, char>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovusqb512mem_mask : X86Builtin<"void(_Vector<16, char *>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovusqd512_mask : X86Builtin<"_Vector<8, int>(_Vector<8, long long int>, _Vector<8, int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovusqd512mem_mask : X86Builtin<"void(_Vector<8, int *>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovusqw512_mask : X86Builtin<"_Vector<8, short>(_Vector<8, long long int>, _Vector<8, short>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovusqw512mem_mask : X86Builtin<"void(_Vector<8, short *>, _Vector<8, long long int>, unsigned char)">; } @@ -2829,47 +2829,47 @@ let Features = "avx512vl", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def pmovusqw256mem_mask : X86Builtin<"void(_Vector<8, short *>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovdb512_mask : X86Builtin<"_Vector<16, char>(_Vector<16, int>, _Vector<16, char>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovdb512mem_mask : X86Builtin<"void(_Vector<16, char *>, _Vector<16, int>, unsigned short)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovwb512mem_mask : X86Builtin<"void(_Vector<32, char *>, _Vector<32, short>, unsigned int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovdw512_mask : X86Builtin<"_Vector<16, short>(_Vector<16, int>, _Vector<16, short>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovdw512mem_mask : X86Builtin<"void(_Vector<16, short *>, _Vector<16, int>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovqb512_mask : X86Builtin<"_Vector<16, char>(_Vector<8, long long int>, _Vector<16, char>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovqb512mem_mask : X86Builtin<"void(_Vector<16, char *>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovqd512_mask : X86Builtin<"_Vector<8, int>(_Vector<8, long long int>, _Vector<8, int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovqd512mem_mask : X86Builtin<"void(_Vector<8, int *>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pmovqw512_mask : X86Builtin<"_Vector<8, short>(_Vector<8, long long int>, _Vector<8, short>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def pmovqw512mem_mask : X86Builtin<"void(_Vector<8, short *>, _Vector<8, long long int>, unsigned char)">; } @@ -2957,14 +2957,14 @@ let Features = "avx512vl", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def pmovqw256mem_mask : X86Builtin<"void(_Vector<8, short *>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx512dq,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512dq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def extractf32x8_mask : X86Builtin<"_Vector<8, float>(_Vector<16, float>, _Constant int, _Vector<8, float>, unsigned char)">; def extractf64x2_512_mask : X86Builtin<"_Vector<2, double>(_Vector<8, double>, _Constant int, _Vector<2, double>, unsigned char)">; def extracti32x8_mask : X86Builtin<"_Vector<8, int>(_Vector<16, int>, _Constant int, _Vector<8, int>, unsigned char)">; def extracti64x2_512_mask : X86Builtin<"_Vector<2, long long int>(_Vector<8, long long int>, _Constant int, _Vector<2, long long int>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def extracti32x4_mask : X86Builtin<"_Vector<4, int>(_Vector<16, int>, _Constant int, _Vector<4, int>, unsigned char)">; def extracti64x4_mask : X86Builtin<"_Vector<4, long long int>(_Vector<8, long long int>, _Constant int, _Vector<4, long long int>, unsigned char)">; } @@ -2979,14 +2979,14 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def extracti32x4_256_mask : X86Builtin<"_Vector<4, int>(_Vector<8, int>, _Constant int, _Vector<4, int>, unsigned char)">; } -let Features = "avx512dq,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512dq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def insertf32x8 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<8, float>, _Constant int)">; def insertf64x2_512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<2, double>, _Constant int)">; def inserti32x8 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<8, int>, _Constant int)">; def inserti64x2_512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<2, long long int>, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def insertf64x4 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<4, double>, _Constant int)">; def inserti64x4 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<4, long long int>, _Constant int)">; } @@ -3001,7 +3001,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def inserti32x4_256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<4, int>, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def insertf32x4 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<4, float>, _Constant int)">; def inserti32x4 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<4, int>, _Constant int)">; } @@ -3022,7 +3022,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def getmantps256_mask : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Constant int, _Vector<8, float>, unsigned char)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def getmantpd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Constant int, _Vector<8, double>, unsigned char, _Constant int)">; def getmantps512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Constant int, _Vector<16, float>, unsigned short, _Constant int)">; def getexppd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, unsigned char, _Constant int)">; @@ -3040,23 +3040,23 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def vfmsubss3_mask3 : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Vector<4, float>, unsigned char, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def permdf512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Constant int)">; def permdi512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Constant int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def permvarhi512 : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def permvardf512 : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, long long int>)">; def permvardi512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>)">; def permvarsf512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, int>)">; def permvarsi512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>)">; } -let Features = "avx512vbmi,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def permvarqi512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>)">; } @@ -3097,7 +3097,7 @@ let Features = "avx512dq,avx512vl", Attributes = [NoThrow, Const, RequiredVector def fpclassps256_mask : X86Builtin<"unsigned char(_Vector<8, float>, _Constant int, unsigned char)">; } -let Features = "avx512dq,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512dq", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def fpclassps512_mask : X86Builtin<"unsigned short(_Vector<16, float>, _Constant int, unsigned short)">; def fpclasspd512_mask : X86Builtin<"unsigned char(_Vector<8, double>, _Constant int, unsigned char)">; } @@ -3256,7 +3256,7 @@ let Features = "avx512bw", Attributes = [NoThrow, Const] in { def kmovq : X86Builtin<"unsigned long long int(unsigned long long int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def palignr512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>, _Constant int)">; } @@ -3268,22 +3268,22 @@ let Features = "avx512bw,avx512vl", Attributes = [NoThrow, Const, RequiredVector def dbpsadbw256 : X86Builtin<"_Vector<16, short>(_Vector<32, char>, _Vector<32, char>, _Constant int)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def dbpsadbw512 : X86Builtin<"_Vector<32, short>(_Vector<64, char>, _Vector<64, char>, _Constant int)">; def psadbw512 : X86Builtin<"_Vector<8, long long int>(_Vector<64, char>, _Vector<64, char>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def compressdf512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, unsigned char)">; def compressdi512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def compresshi512_mask : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>, unsigned int)">; def compressqi512_mask : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>, unsigned long long int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def compresssf512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, unsigned short)">; def compresssi512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, unsigned short)">; } @@ -3293,49 +3293,49 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def cmpss_mask : X86Builtin<"unsigned char(_Vector<4, float>, _Vector<4, float>, _Constant int, unsigned char, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def pshufd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Constant int)">; def expanddf512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, unsigned char)">; def expanddi512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def expandhi512_mask : X86Builtin<"_Vector<32, short>(_Vector<32, short>, _Vector<32, short>, unsigned int)">; def expandqi512_mask : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>, unsigned long long int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def expandloaddf512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double const *>, _Vector<8, double>, unsigned char)">; def expandloaddi512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int const *>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def expandloadhi512_mask : X86Builtin<"_Vector<32, short>(_Vector<32, short const *>, _Vector<32, short>, unsigned int)">; def expandloadqi512_mask : X86Builtin<"_Vector<64, char>(_Vector<64, char const *>, _Vector<64, char>, unsigned long long int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def expandloadsf512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float const *>, _Vector<16, float>, unsigned short)">; def expandloadsi512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, int const *>, _Vector<16, int>, unsigned short)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def expandsf512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, unsigned short)">; def expandsi512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, unsigned short)">; def cvtps2pd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, float>, _Vector<8, double>, unsigned char, _Constant int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def compressstoredf512_mask : X86Builtin<"void(_Vector<8, double *>, _Vector<8, double>, unsigned char)">; def compressstoredi512_mask : X86Builtin<"void(_Vector<8, long long int *>, _Vector<8, long long int>, unsigned char)">; } -let Features = "avx512vbmi2,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def compressstorehi512_mask : X86Builtin<"void(_Vector<32, short *>, _Vector<32, short>, unsigned int)">; def compressstoreqi512_mask : X86Builtin<"void(_Vector<64, char *>, _Vector<64, char>, unsigned long long int)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def compressstoresf512_mask : X86Builtin<"void(_Vector<16, float *>, _Vector<16, float>, unsigned short)">; def compressstoresi512_mask : X86Builtin<"void(_Vector<16, int *>, _Vector<16, int>, unsigned short)">; } @@ -3356,7 +3356,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, RequiredVectorWidth<256 def vcvtps2ph256_mask : X86Builtin<"_Vector<8, short>(_Vector<8, float>, _Constant int, _Vector<8, short>, unsigned char)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cvtw2mask512 : X86Builtin<"unsigned int(_Vector<32, short>)">; } @@ -3375,7 +3375,7 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def cvtusi2ss32 : X86Builtin<"_Vector<4, float>(_Vector<4, float>, unsigned int, _Constant int)">; } -let Features = "avx512vbmi,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512vbmi", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vpmultishiftqb512 : X86Builtin<"_Vector<64, char>(_Vector<64, char>, _Vector<64, char>)">; } @@ -3395,7 +3395,7 @@ let Features = "avx512bf16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def cvtne2ps2bf16_256 : X86Builtin<"_Vector<16, __bf16>(_Vector<8, float>, _Vector<8, float>)">; } -let Features = "avx512bf16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bf16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cvtne2ps2bf16_512 : X86Builtin<"_Vector<32, __bf16>(_Vector<16, float>, _Vector<16, float>)">; } @@ -3407,7 +3407,7 @@ let Features = "avx512bf16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def cvtneps2bf16_256_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, float>, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx512bf16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bf16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cvtneps2bf16_512_mask : X86Builtin<"_Vector<16, __bf16>(_Vector<16, float>, _Vector<16, __bf16>, unsigned short)">; } @@ -3419,7 +3419,7 @@ let Features = "avx512bf16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def dpbf16ps_256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<16, __bf16>, _Vector<16, __bf16>)">; } -let Features = "avx512bf16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512bf16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def dpbf16ps_512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<32, __bf16>, _Vector<32, __bf16>)">; } @@ -3427,7 +3427,7 @@ let Features = "avx512bf16", Attributes = [NoThrow, Const] in { def cvtsbf162ss_32 : X86Builtin<"float(__bf16)">; } -let Features = "avx512vp2intersect,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512vp2intersect", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vp2intersect_q_512 : X86Builtin<"void(_Vector<8, long long int>, _Vector<8, long long int>, unsigned char *, unsigned char *)">; } @@ -3439,7 +3439,7 @@ let Features = "avx512vp2intersect,avx512vl", Attributes = [NoThrow, RequiredVec def vp2intersect_q_128 : X86Builtin<"void(_Vector<2, long long int>, _Vector<2, long long int>, unsigned char *, unsigned char *)">; } -let Features = "avx512vp2intersect,evex512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx512vp2intersect", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vp2intersect_d_512 : X86Builtin<"void(_Vector<16, int>, _Vector<16, int>, unsigned short *, unsigned short *)">; } @@ -3455,7 +3455,7 @@ let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<1 def vcomish : X86Builtin<"int(_Vector<8, _Float16>, _Vector<8, _Float16>, _Constant int, _Constant int)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def addph512 : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Constant int)">; def subph512 : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Constant int)">; def mulph512 : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Constant int)">; @@ -3489,7 +3489,7 @@ let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<1 def minsh_round_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, _Float16>, _Vector<8, _Float16>, _Vector<8, _Float16>, unsigned char, _Constant int)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def cmpph512_mask : X86Builtin<"unsigned int(_Vector<32, _Float16>, _Vector<32, _Float16>, _Constant int, unsigned int, _Constant int)">; } @@ -3518,7 +3518,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def rcpph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rcpph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int)">; } @@ -3530,7 +3530,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def rsqrtph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rsqrtph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int)">; } @@ -3542,7 +3542,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def getmantph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Constant int, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def getmantph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Constant int, _Vector<32, _Float16>, unsigned int, _Constant int)">; } @@ -3554,7 +3554,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def getexpph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def getexpph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int, _Constant int)">; } @@ -3566,7 +3566,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def scalefph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Vector<16, _Float16>, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def scalefph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int, _Constant int)">; } @@ -3578,7 +3578,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def rndscaleph_256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Constant int, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def rndscaleph_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Constant int, _Vector<32, _Float16>, unsigned int, _Constant int)">; } @@ -3590,7 +3590,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def reduceph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Constant int, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduceph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Constant int, _Vector<32, _Float16>, unsigned int, _Constant int)">; } @@ -3612,7 +3612,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def sqrtph256 : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def sqrtph512 : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Constant int)">; } @@ -3628,7 +3628,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def fpclassph256_mask : X86Builtin<"unsigned short(_Vector<16, _Float16>, _Constant int, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def fpclassph512_mask : X86Builtin<"unsigned int(_Vector<32, _Float16>, _Constant int, unsigned int)">; } @@ -3644,7 +3644,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtpd2ph256_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<4, double>, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtpd2ph512_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, double>, _Vector<8, _Float16>, unsigned char, _Constant int)">; } @@ -3656,7 +3656,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtph2pd256_mask : X86Builtin<"_Vector<4, double>(_Vector<8, _Float16>, _Vector<4, double>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtph2pd512_mask : X86Builtin<"_Vector<8, double>(_Vector<8, _Float16>, _Vector<8, double>, unsigned char, _Constant int)">; } @@ -3675,7 +3675,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtph2w256_mask : X86Builtin<"_Vector<16, short>(_Vector<16, _Float16>, _Vector<16, short>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtph2w512_mask : X86Builtin<"_Vector<32, short>(_Vector<32, _Float16>, _Vector<32, short>, unsigned int, _Constant int)">; } @@ -3687,7 +3687,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvttph2w256_mask : X86Builtin<"_Vector<16, short>(_Vector<16, _Float16>, _Vector<16, short>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvttph2w512_mask : X86Builtin<"_Vector<32, short>(_Vector<32, _Float16>, _Vector<32, short>, unsigned int, _Constant int)">; } @@ -3699,7 +3699,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtw2ph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, short>, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtw2ph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, short>, _Vector<32, _Float16>, unsigned int, _Constant int)">; } @@ -3711,7 +3711,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtph2uw256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtph2uw512_mask : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, _Float16>, _Vector<32, unsigned short>, unsigned int, _Constant int)">; } @@ -3723,7 +3723,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvttph2uw256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvttph2uw512_mask : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, _Float16>, _Vector<32, unsigned short>, unsigned int, _Constant int)">; } @@ -3735,7 +3735,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtuw2ph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, unsigned short>, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtuw2ph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, unsigned short>, _Vector<32, _Float16>, unsigned int, _Constant int)">; } @@ -3747,7 +3747,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtph2dq256_mask : X86Builtin<"_Vector<8, int>(_Vector<8, _Float16>, _Vector<8, int>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtph2dq512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, _Float16>, _Vector<16, int>, unsigned short, _Constant int)">; } @@ -3759,7 +3759,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtph2udq256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, _Float16>, _Vector<8, unsigned int>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtph2udq512_mask : X86Builtin<"_Vector<16, unsigned int>(_Vector<16, _Float16>, _Vector<16, unsigned int>, unsigned short, _Constant int)">; } @@ -3771,7 +3771,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtdq2ph256_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, int>, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtdq2ph512_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, int>, _Vector<16, _Float16>, unsigned short, _Constant int)">; } @@ -3783,7 +3783,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtudq2ph256_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, unsigned int>, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtudq2ph512_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, unsigned int>, _Vector<16, _Float16>, unsigned short, _Constant int)">; } @@ -3795,7 +3795,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvttph2dq256_mask : X86Builtin<"_Vector<8, int>(_Vector<8, _Float16>, _Vector<8, int>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvttph2dq512_mask : X86Builtin<"_Vector<16, int>(_Vector<16, _Float16>, _Vector<16, int>, unsigned short, _Constant int)">; } @@ -3807,7 +3807,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvttph2udq256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, _Float16>, _Vector<8, unsigned int>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvttph2udq512_mask : X86Builtin<"_Vector<16, unsigned int>(_Vector<16, _Float16>, _Vector<16, unsigned int>, unsigned short, _Constant int)">; } @@ -3819,7 +3819,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtqq2ph256_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<4, long long int>, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtqq2ph512_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, long long int>, _Vector<8, _Float16>, unsigned char, _Constant int)">; } @@ -3831,7 +3831,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtph2qq256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<8, _Float16>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtph2qq512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, _Float16>, _Vector<8, long long int>, unsigned char, _Constant int)">; } @@ -3843,7 +3843,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtuqq2ph256_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<4, unsigned long long int>, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtuqq2ph512_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, unsigned long long int>, _Vector<8, _Float16>, unsigned char, _Constant int)">; } @@ -3855,7 +3855,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtph2uqq256_mask : X86Builtin<"_Vector<4, unsigned long long int>(_Vector<8, _Float16>, _Vector<4, unsigned long long int>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtph2uqq512_mask : X86Builtin<"_Vector<8, unsigned long long int>(_Vector<8, _Float16>, _Vector<8, unsigned long long int>, unsigned char, _Constant int)">; } @@ -3867,7 +3867,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvttph2qq256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<8, _Float16>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvttph2qq512_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, _Float16>, _Vector<8, long long int>, unsigned char, _Constant int)">; } @@ -3879,7 +3879,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvttph2uqq256_mask : X86Builtin<"_Vector<4, unsigned long long int>(_Vector<8, _Float16>, _Vector<4, unsigned long long int>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvttph2uqq512_mask : X86Builtin<"_Vector<8, unsigned long long int>(_Vector<8, _Float16>, _Vector<8, unsigned long long int>, unsigned char, _Constant int)">; } @@ -3900,7 +3900,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtph2psx256_mask : X86Builtin<"_Vector<8, float>(_Vector<8, _Float16>, _Vector<8, float>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtph2psx512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, _Float16>, _Vector<16, float>, unsigned short, _Constant int)">; } @@ -3912,11 +3912,11 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vcvtps2phx256_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, float>, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvtps2phx512_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, float>, _Vector<16, _Float16>, unsigned short, _Constant int)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfmaddph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int, _Constant int)">; def vfmaddph512_mask3 : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int, _Constant int)">; def vfmaddph512_maskz : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int, _Constant int)">; @@ -3930,7 +3930,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vfmaddsubph256 : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Vector<16, _Float16>, _Vector<16, _Float16>)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfmaddsubph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int, _Constant int)">; def vfmaddsubph512_maskz : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int, _Constant int)">; def vfmaddsubph512_mask3 : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Vector<32, _Float16>, unsigned int, _Constant int)">; @@ -3955,7 +3955,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vfmaddcph256_maskz : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Vector<8, float>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfmaddcph512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; def vfmaddcph512_maskz : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; def vfmaddcph512_mask3 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; @@ -3971,7 +3971,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vfcmaddcph256_maskz : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Vector<8, float>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfcmaddcph512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; def vfcmaddcph512_maskz : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; def vfcmaddcph512_mask3 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; @@ -3998,7 +3998,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vfmulcph256_mask : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Vector<8, float>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfmulcph512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; } @@ -4010,7 +4010,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def vfcmulcph256_mask : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Vector<8, float>, unsigned char)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfcmulcph512_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Vector<16, float>, unsigned short, _Constant int)">; } @@ -4022,7 +4022,7 @@ let Features = "avx512bw,avx512vl", Attributes = [NoThrow, Const, Constexpr, Req def selectb_256 : X86Builtin<"_Vector<32, char>(unsigned int, _Vector<32, char>, _Vector<32, char>)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def selectb_512 : X86Builtin<"_Vector<64, char>(unsigned long long int, _Vector<64, char>, _Vector<64, char>)">; } @@ -4034,7 +4034,7 @@ let Features = "avx512bw,avx512vl", Attributes = [NoThrow, Const, Constexpr, Req def selectw_256 : X86Builtin<"_Vector<16, short>(unsigned short, _Vector<16, short>, _Vector<16, short>)">; } -let Features = "avx512bw,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512bw", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def selectw_512 : X86Builtin<"_Vector<32, short>(unsigned int, _Vector<32, short>, _Vector<32, short>)">; } @@ -4046,7 +4046,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVect def selectd_256 : X86Builtin<"_Vector<8, int>(unsigned char, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def selectd_512 : X86Builtin<"_Vector<16, int>(unsigned short, _Vector<16, int>, _Vector<16, int>)">; } @@ -4058,7 +4058,7 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, Constexpr, R def selectph_256 : X86Builtin<"_Vector<16, _Float16>(unsigned short, _Vector<16, _Float16>, _Vector<16, _Float16>)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def selectph_512 : X86Builtin<"_Vector<32, _Float16>(unsigned int, _Vector<32, _Float16>, _Vector<32, _Float16>)">; } @@ -4070,7 +4070,7 @@ let Features = "avx512bf16,avx512vl", Attributes = [NoThrow, Const, Constexpr, R def selectpbf_256 : X86Builtin<"_Vector<16, __bf16>(unsigned short, _Vector<16, __bf16>, _Vector<16, __bf16>)">; } -let Features = "avx512bf16,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512bf16", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def selectpbf_512 : X86Builtin<"_Vector<32, __bf16>(unsigned int, _Vector<32, __bf16>, _Vector<32, __bf16>)">; } @@ -4082,7 +4082,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVect def selectq_256 : X86Builtin<"_Vector<4, long long int>(unsigned char, _Vector<4, long long int>, _Vector<4, long long int>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def selectq_512 : X86Builtin<"_Vector<8, long long int>(unsigned char, _Vector<8, long long int>, _Vector<8, long long int>)">; } @@ -4094,7 +4094,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVect def selectps_256 : X86Builtin<"_Vector<8, float>(unsigned char, _Vector<8, float>, _Vector<8, float>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def selectps_512 : X86Builtin<"_Vector<16, float>(unsigned short, _Vector<16, float>, _Vector<16, float>)">; } @@ -4106,7 +4106,7 @@ let Features = "avx512vl", Attributes = [NoThrow, Const, Constexpr, RequiredVect def selectpd_256 : X86Builtin<"_Vector<4, double>(unsigned char, _Vector<4, double>, _Vector<4, double>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<512>] in { def selectpd_512 : X86Builtin<"_Vector<8, double>(unsigned char, _Vector<8, double>, _Vector<8, double>)">; } @@ -4123,12 +4123,12 @@ let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<128> def selectsd_128 : X86Builtin<"_Vector<2, double>(unsigned char, _Vector<2, double>, _Vector<2, double>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduce_fadd_pd512 : X86Builtin<"double(double, _Vector<8, double>)">; def reduce_fadd_ps512 : X86Builtin<"float(float, _Vector<16, float>)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduce_fadd_ph512 : X86Builtin<"_Float16(_Float16, _Vector<32, _Float16>)">; } @@ -4140,12 +4140,12 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def reduce_fadd_ph128 : X86Builtin<"_Float16(_Float16, _Vector<8, _Float16>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduce_fmax_pd512 : X86Builtin<"double(_Vector<8, double>)">; def reduce_fmax_ps512 : X86Builtin<"float(_Vector<16, float>)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduce_fmax_ph512 : X86Builtin<"_Float16(_Vector<32, _Float16>)">; } @@ -4157,12 +4157,12 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def reduce_fmax_ph128 : X86Builtin<"_Float16(_Vector<8, _Float16>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduce_fmin_pd512 : X86Builtin<"double(_Vector<8, double>)">; def reduce_fmin_ps512 : X86Builtin<"float(_Vector<16, float>)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduce_fmin_ph512 : X86Builtin<"_Float16(_Vector<32, _Float16>)">; } @@ -4174,12 +4174,12 @@ let Features = "avx512fp16,avx512vl", Attributes = [NoThrow, Const, RequiredVect def reduce_fmin_ph128 : X86Builtin<"_Float16(_Vector<8, _Float16>)">; } -let Features = "avx512f,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512f", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduce_fmul_pd512 : X86Builtin<"double(double, _Vector<8, double>)">; def reduce_fmul_ps512 : X86Builtin<"float(float, _Vector<16, float>)">; } -let Features = "avx512fp16,evex512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx512fp16", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def reduce_fmul_ph512 : X86Builtin<"_Float16(_Float16, _Vector<32, _Float16>)">; } @@ -4300,15 +4300,15 @@ let Header = "intrin.h", Languages = "ALL_MS_LANGUAGES", Attributes = [NoThrow, def __readgsqword : X86LibBuiltin<"unsigned long long int(msuint32_t)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vdpphps128 : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<8, _Float16>, _Vector<8, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vdpphps256 : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<16, _Float16>, _Vector<16, _Float16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vdpphps512 : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<32, _Float16>, _Vector<32, _Float16>)">; def vpdpbssd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; def vpdpbssds512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; @@ -4318,7 +4318,7 @@ let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth< def vpdpbuuds512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vpdpwsud512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; def vpdpwsuds512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; def vpdpwusd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; @@ -4327,158 +4327,158 @@ let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] i def vpdpwuuds512 : X86Builtin<"_Vector<16, int>(_Vector<16, int>, _Vector<16, int>, _Vector<16, int>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def mpsadbw512 : X86Builtin<"_Vector<32, short>(_Vector<64, char>, _Vector<64, char>, _Constant char)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vpdpwsud128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vpdpwsud256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vpdpwsuds128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vpdpwsuds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vpdpwusd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vpdpwusd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vpdpwusds128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vpdpwusds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vpdpwuud128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vpdpwuud256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vpdpwuuds128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>, _Vector<4, int>)">; } -let Features = "avxvnniint16|avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avxvnniint16|avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vpdpwuuds256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>, _Vector<8, int>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vcvttsd2sis32 : X86Builtin<"int(_Vector<2, double>, _Constant int)">; def vcvttsd2usis32 : X86Builtin<"unsigned int(_Vector<2, double>, _Constant int)">; def vcvttss2sis32 : X86Builtin<"int(_Vector<4, float>, _Constant int)">; def vcvttss2usis32 : X86Builtin<"unsigned int(_Vector<4, float>, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttpd2dqs128_mask : X86Builtin<"_Vector<4, int>(_Vector<2, double>, _Vector<4, int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttpd2dqs256_mask : X86Builtin<"_Vector<4, int>(_Vector<4, double>, _Vector<4, int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttpd2dqs512_round_mask : X86Builtin<"_Vector<8, int>(_Vector<8, double>, _Vector<8, int>, unsigned char, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttpd2udqs128_mask : X86Builtin<"_Vector<4, int>(_Vector<2, double>, _Vector<4, int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttpd2udqs256_mask : X86Builtin<"_Vector<4, int>(_Vector<4, double>, _Vector<4, int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttpd2udqs512_round_mask : X86Builtin<"_Vector<8, int>(_Vector<8, double>, _Vector<8, int>, unsigned char, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttpd2qqs128_mask : X86Builtin<"_Vector<2, long long int>(_Vector<2, double>, _Vector<2, long long int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttpd2qqs256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, double>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttpd2qqs512_round_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, double>, _Vector<8, long long int>, unsigned char, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttpd2uqqs128_mask : X86Builtin<"_Vector<2, long long int>(_Vector<2, double>, _Vector<2, long long int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttpd2uqqs256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, double>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttpd2uqqs512_round_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, double>, _Vector<8, long long int>, unsigned char, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttps2dqs128_mask : X86Builtin<"_Vector<4, int>(_Vector<4, float>, _Vector<4, int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttps2dqs256_mask : X86Builtin<"_Vector<8, int>(_Vector<8, float>, _Vector<8, int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttps2dqs512_round_mask : X86Builtin<"_Vector<16, int>(_Vector<16, float>, _Vector<16, int>, unsigned short, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttps2udqs128_mask : X86Builtin<"_Vector<4, int>(_Vector<4, float>, _Vector<4, int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttps2udqs256_mask : X86Builtin<"_Vector<8, int>(_Vector<8, float>, _Vector<8, int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttps2udqs512_round_mask : X86Builtin<"_Vector<16, int>(_Vector<16, float>, _Vector<16, int>, unsigned short, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttps2qqs128_mask : X86Builtin<"_Vector<2, long long int>(_Vector<4, float>, _Vector<2, long long int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttps2qqs256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, float>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttps2qqs512_round_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, float>, _Vector<8, long long int>, unsigned char, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttps2uqqs128_mask : X86Builtin<"_Vector<2, long long int>(_Vector<4, float>, _Vector<2, long long int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttps2uqqs256_mask : X86Builtin<"_Vector<4, long long int>(_Vector<4, float>, _Vector<4, long long int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttps2uqqs512_round_mask : X86Builtin<"_Vector<8, long long int>(_Vector<8, float>, _Vector<8, long long int>, unsigned char, _Constant int)">; } @@ -4577,568 +4577,568 @@ let Features = "sm4", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vsm4rnds4256 : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, unsigned int>, _Vector<8, unsigned int>)">; } -let Features = "avx10.2-512,sm4", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2,sm4", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vsm4key4512 : X86Builtin<"_Vector<16, unsigned int>(_Vector<16, unsigned int>, _Vector<16, unsigned int>)">; def vsm4rnds4512 : X86Builtin<"_Vector<16, unsigned int>(_Vector<16, unsigned int>, _Vector<16, unsigned int>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vminmaxbf16128 : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vminmaxbf16256 : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>, _Constant int)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vminmaxbf16512 : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vminmaxpd128_mask : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>, _Constant int, _Vector<2, double>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vminmaxpd256_mask : X86Builtin<"_Vector<4, double>(_Vector<4, double>, _Vector<4, double>, _Constant int, _Vector<4, double>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vminmaxpd512_round_mask : X86Builtin<"_Vector<8, double>(_Vector<8, double>, _Vector<8, double>, _Constant int, _Vector<8, double>, unsigned char, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vminmaxph128_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, _Float16>, _Vector<8, _Float16>, _Constant int, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vminmaxph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, _Float16>, _Vector<16, _Float16>, _Constant int, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vminmaxph512_round_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, _Float16>, _Vector<32, _Float16>, _Constant int, _Vector<32, _Float16>, unsigned int, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vminmaxps128_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Constant int, _Vector<4, float>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vminmaxps256_mask : X86Builtin<"_Vector<8, float>(_Vector<8, float>, _Vector<8, float>, _Constant int, _Vector<8, float>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vminmaxps512_round_mask : X86Builtin<"_Vector<16, float>(_Vector<16, float>, _Vector<16, float>, _Constant int, _Vector<16, float>, unsigned short, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vminmaxsd_round_mask : X86Builtin<"_Vector<2, double>(_Vector<2, double>, _Vector<2, double>, _Constant int, _Vector<2, double>, unsigned char, _Constant int)">; def vminmaxsh_round_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<8, _Float16>, _Vector<8, _Float16>, _Constant int, _Vector<8, _Float16>, unsigned char, _Constant int)">; def vminmaxss_round_mask : X86Builtin<"_Vector<4, float>(_Vector<4, float>, _Vector<4, float>, _Constant int, _Vector<4, float>, unsigned char, _Constant int)">; def vcvtbf162ibs128 : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtbf162ibs256 : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtbf162ibs512 : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtbf162iubs128 : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtbf162iubs256 : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtbf162iubs512 : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtph2ibs128_mask : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, _Float16>, _Vector<8, unsigned short>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtph2ibs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtph2ibs512_mask : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, _Float16>, _Vector<32, unsigned short>, unsigned int, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtph2iubs128_mask : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, _Float16>, _Vector<8, unsigned short>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtph2iubs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtph2iubs512_mask : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, _Float16>, _Vector<32, unsigned short>, unsigned int, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtps2ibs128_mask : X86Builtin<"_Vector<4, unsigned int>(_Vector<4, float>, _Vector<4, unsigned int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtps2ibs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtps2ibs512_mask : X86Builtin<"_Vector<16, unsigned int>(_Vector<16, float>, _Vector<16, unsigned int>, unsigned short, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtps2iubs128_mask : X86Builtin<"_Vector<4, unsigned int>(_Vector<4, float>, _Vector<4, unsigned int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtps2iubs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtps2iubs512_mask : X86Builtin<"_Vector<16, unsigned int>(_Vector<16, float>, _Vector<16, unsigned int>, unsigned short, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttbf162ibs128 : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttbf162ibs256 : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttbf162ibs512 : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttbf162iubs128 : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttbf162iubs256 : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttbf162iubs512 : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttph2ibs128_mask : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, _Float16>, _Vector<8, unsigned short>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttph2ibs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttph2ibs512_mask : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, _Float16>, _Vector<32, unsigned short>, unsigned int, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttph2iubs128_mask : X86Builtin<"_Vector<8, unsigned short>(_Vector<8, _Float16>, _Vector<8, unsigned short>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttph2iubs256_mask : X86Builtin<"_Vector<16, unsigned short>(_Vector<16, _Float16>, _Vector<16, unsigned short>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttph2iubs512_mask : X86Builtin<"_Vector<32, unsigned short>(_Vector<32, _Float16>, _Vector<32, unsigned short>, unsigned int, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttps2ibs128_mask : X86Builtin<"_Vector<4, unsigned int>(_Vector<4, float>, _Vector<4, unsigned int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttps2ibs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttps2ibs512_mask : X86Builtin<"_Vector<16, unsigned int>(_Vector<16, float>, _Vector<16, unsigned int>, unsigned short, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvttps2iubs128_mask : X86Builtin<"_Vector<4, unsigned int>(_Vector<4, float>, _Vector<4, unsigned int>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvttps2iubs256_mask : X86Builtin<"_Vector<8, unsigned int>(_Vector<8, float>, _Vector<8, unsigned int>, unsigned char)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvttps2iubs512_mask : X86Builtin<"_Vector<16, unsigned int>(_Vector<16, float>, _Vector<16, unsigned int>, unsigned short, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vcvt2ps2phx128_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<4, float>, _Vector<4, float>, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vcvt2ps2phx256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<8, float>, _Vector<8, float>, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcvt2ps2phx512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<16, float>, _Vector<16, float>, _Vector<32, _Float16>, unsigned int, _Constant int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtbiasph2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtbiasph2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtbiasph2bf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<64, char>, _Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtbiasph2bf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtbiasph2bf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtbiasph2bf8s_512_mask : X86Builtin<"_Vector<32, char>(_Vector<64, char>, _Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtbiasph2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtbiasph2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtbiasph2hf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<64, char>, _Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtbiasph2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtbiasph2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<32, char>, _Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtbiasph2hf8s_512_mask : X86Builtin<"_Vector<32, char>(_Vector<64, char>, _Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvt2ph2bf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvt2ph2bf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvt2ph2bf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvt2ph2bf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvt2ph2bf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvt2ph2bf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvt2ph2hf8_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvt2ph2hf8_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvt2ph2hf8_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvt2ph2hf8s_128 : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<8, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvt2ph2hf8s_256 : X86Builtin<"_Vector<32, char>(_Vector<16, _Float16>, _Vector<16, _Float16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvt2ph2hf8s_512 : X86Builtin<"_Vector<64, char>(_Vector<32, _Float16>, _Vector<32, _Float16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvthf8_2ph128_mask : X86Builtin<"_Vector<8, _Float16>(_Vector<16, char>, _Vector<8, _Float16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvthf8_2ph256_mask : X86Builtin<"_Vector<16, _Float16>(_Vector<16, char>, _Vector<16, _Float16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvthf8_2ph512_mask : X86Builtin<"_Vector<32, _Float16>(_Vector<32, char>, _Vector<32, _Float16>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtph2bf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtph2bf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtph2bf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtph2bf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtph2bf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtph2bf8s_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtph2hf8_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtph2hf8_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtph2hf8_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vcvtph2hf8s_128_mask : X86Builtin<"_Vector<16, char>(_Vector<8, _Float16>, _Vector<16, char>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vcvtph2hf8s_256_mask : X86Builtin<"_Vector<16, char>(_Vector<16, _Float16>, _Vector<16, char>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vcvtph2hf8s_512_mask : X86Builtin<"_Vector<32, char>(_Vector<32, _Float16>, _Vector<32, char>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def loadsbf16128_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16 const *>, _Vector<8, __bf16>, unsigned char)">; def storesbf16128_mask : X86Builtin<"void(_Vector<8, __bf16 *>, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vaddbf16128 : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vaddbf16256 : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vaddbf16512 : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vdivbf16128 : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vdivbf16256 : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vdivbf16512 : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vmaxbf16128 : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vmaxbf16256 : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vmaxbf16512 : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vminbf16128 : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vminbf16256 : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vminbf16512 : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vmulbf16128 : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vmulbf16256 : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vmulbf16512 : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vsubbf16128 : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vsubbf16256 : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vsubbf16512 : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in foreach Cmp = ["eq", "lt", "le", "gt", "ge", "neq"] in def vcomisbf16#Cmp : X86Builtin<"int(_Vector<8, __bf16>, _Vector<8, __bf16>)">; -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vcmpbf16512_mask : X86Builtin<"unsigned int(_Vector<32, __bf16>, _Vector<32, __bf16>, _Constant int, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vcmpbf16256_mask : X86Builtin<"unsigned short(_Vector<16, __bf16>, _Vector<16, __bf16>, _Constant int, unsigned short)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vcmpbf16128_mask : X86Builtin<"unsigned char(_Vector<8, __bf16>, _Vector<8, __bf16>, _Constant int, unsigned char)">; def vfpclassbf16128_mask : X86Builtin<"unsigned char(_Vector<8, __bf16>, _Constant int, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vfpclassbf16256_mask : X86Builtin<"unsigned short(_Vector<16, __bf16>, _Constant int, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vfpclassbf16512_mask : X86Builtin<"unsigned int(_Vector<32, __bf16>, _Constant int, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vscalefbf16128_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vscalefbf16256_mask : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>, _Vector<16, __bf16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vscalefbf16512_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>, _Vector<32, __bf16>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vrcpbf16128_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vrcpbf16256_mask : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vrcpbf16512_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vgetexpbf16128_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vgetexpbf16256_mask : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vgetexpbf16512_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vrsqrtbf16128_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vrsqrtbf16256_mask : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Vector<16, __bf16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vrsqrtbf16512_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Vector<32, __bf16>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vreducebf16128_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Constant int, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vreducebf16256_mask : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Constant int, _Vector<16, __bf16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vreducebf16512_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Constant int, _Vector<32, __bf16>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vrndscalebf16_128_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Constant int, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vrndscalebf16_256_mask : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Constant int, _Vector<16, __bf16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vrndscalebf16_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Constant int, _Vector<32, __bf16>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vgetmantbf16128_mask : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>, _Constant int, _Vector<8, __bf16>, unsigned char)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vgetmantbf16256_mask : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>, _Constant int, _Vector<16, __bf16>, unsigned short)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vgetmantbf16512_mask : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>, _Constant int, _Vector<32, __bf16>, unsigned int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vsqrtbf16 : X86Builtin<"_Vector<8, __bf16>(_Vector<8, __bf16>)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] in { def vsqrtbf16256 : X86Builtin<"_Vector<16, __bf16>(_Vector<16, __bf16>)">; } -let Features = "avx10.2-512", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<512>] in { def vsqrtbf16512 : X86Builtin<"_Vector<32, __bf16>(_Vector<32, __bf16>)">; } diff --git a/clang/include/clang/Basic/BuiltinsX86_64.td b/clang/include/clang/Basic/BuiltinsX86_64.td index f2b35874e3876..214b175ace5eb 100644 --- a/clang/include/clang/Basic/BuiltinsX86_64.td +++ b/clang/include/clang/Basic/BuiltinsX86_64.td @@ -178,7 +178,7 @@ let Features = "movdiri", Attributes = [NoThrow] in { def directstore_u64 : X86Builtin<"void(unsigned long int *, unsigned long int)">; } -let Features = "avx10.2-256", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { +let Features = "avx10.2", Attributes = [NoThrow, Const, RequiredVectorWidth<128>] in { def vcvttsd2sis64 : X86Builtin<"long long int(_Vector<2, double>, _Constant int)">; def vcvttsd2usis64 : X86Builtin<"unsigned long long int(_Vector<2, double>, _Constant int)">; def vcvttss2sis64 : X86Builtin<"long long int(_Vector<4, float>, _Constant int)">; @@ -290,7 +290,7 @@ let Features = "amx-complex,amx-transpose", Attributes = [NoThrow] in { def tconjtfp16_internal : X86Builtin<"_Vector<256, int>(unsigned short, unsigned short, _Vector<256, int>)">; } -let Features = "amx-avx512,avx10.2-512", Attributes = [NoThrow] in { +let Features = "amx-avx512,avx10.2", Attributes = [NoThrow] in { def tcvtrowd2ps_internal : X86Builtin<"_Vector<16, float>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">; def tcvtrowps2bf16h_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">; def tcvtrowps2bf16l_internal : X86Builtin<"_Vector<32, __bf16>(unsigned short, unsigned short, _Vector<256, int>, unsigned int)">; @@ -382,7 +382,7 @@ let Features = "amx-complex,amx-transpose", Attributes = [NoThrow] in { def tconjtfp16 : X86Builtin<"void(_Constant unsigned char, _Constant unsigned char)">; } -let Features = "amx-avx512,avx10.2-512", Attributes = [NoThrow] in { +let Features = "amx-avx512,avx10.2", Attributes = [NoThrow] in { def tcvtrowd2ps : X86Builtin<"_Vector<16, float>(_Constant unsigned char, unsigned int)">; def tcvtrowps2bf16h : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">; def tcvtrowps2bf16l : X86Builtin<"_Vector<32, __bf16>(_Constant unsigned char, unsigned int)">; @@ -433,50 +433,50 @@ let Features = "movrs", Attributes = [NoThrow] in { def movrsdi : X86Builtin<"signed long long int(void const *)">; } -let Features = "movrs,avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vmovrsb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char const *>)">; } -let Features = "movrs,avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vmovrsb256 : X86Builtin<"_Vector<32, char>(_Vector<32, char const *>)">; } -let Features = "movrs,avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vmovrsb512 : X86Builtin<"_Vector<64, char>(_Vector<64, char const *>)">; } -let Features = "movrs,avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vmovrsd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int const *>)">; } -let Features = "movrs,avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vmovrsd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int const *>)">; } -let Features = "movrs,avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vmovrsd512 : X86Builtin<"_Vector<16, int>(_Vector<16, int const *>)">; } -let Features = "movrs,avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vmovrsq128 : X86Builtin<"_Vector<2, long long int>(_Vector<2, long long int const *>)">; } -let Features = "movrs,avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vmovrsq256 : X86Builtin<"_Vector<4, long long int>(_Vector<4, long long int const *>)">; } -let Features = "movrs,avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vmovrsq512 : X86Builtin<"_Vector<8, long long int>(_Vector<8, long long int const *>)">; } -let Features = "movrs,avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<128>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<128>] in { def vmovrsw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short const *>)">; } -let Features = "movrs,avx10.2-256", Attributes = [NoThrow, RequiredVectorWidth<256>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<256>] in { def vmovrsw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short const *>)">; } -let Features = "movrs,avx10.2-512", Attributes = [NoThrow, RequiredVectorWidth<512>] in { +let Features = "movrs,avx10.2", Attributes = [NoThrow, RequiredVectorWidth<512>] in { def vmovrsw512 : X86Builtin<"_Vector<32, short>(_Vector<32, short const *>)">; } diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 49e917a6a0786..718808d583e8c 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6651,16 +6651,10 @@ def msse4a : Flag<["-"], "msse4a">, Group; def mno_sse4a : Flag<["-"], "mno-sse4a">, Group; def mavx : Flag<["-"], "mavx">, Group; def mno_avx : Flag<["-"], "mno-avx">, Group; -def mavx10_1_256 : Flag<["-"], "mavx10.1-256">, Group; -def mno_avx10_1_256 : Flag<["-"], "mno-avx10.1-256">, Group; -def mavx10_1_512 : Flag<["-"], "mavx10.1-512">, Group; -def mno_avx10_1_512 : Flag<["-"], "mno-avx10.1-512">, Alias; -def mavx10_1 : Flag<["-"], "mavx10.1">, Group; -def mno_avx10_1 : Flag<["-"], "mno-avx10.1">, Group; -def mavx10_2_256 : Flag<["-"], "mavx10.2-256">, Group; -def mavx10_2_512 : Flag<["-"], "mavx10.2-512">, Group; -def mavx10_2 : Flag<["-"], "mavx10.2">, Group; -def mno_avx10_2 : Flag<["-"], "mno-avx10.2">, Group; +def mavx10_1 : Flag<["-"], "mavx10.1">, Group; +def mno_avx10_1 : Flag<["-"], "mno-avx10.1">, Group; +def mavx10_2 : Flag<["-"], "mavx10.2">, Group; +def mno_avx10_2 : Flag<["-"], "mno-avx10.2">, Group; def mavx2 : Flag<["-"], "mavx2">, Group; def mno_avx2 : Flag<["-"], "mno-avx2">, Group; def mavx512f : Flag<["-"], "mavx512f">, Group; @@ -6725,10 +6719,6 @@ def mcx16 : Flag<["-"], "mcx16">, Group; def mno_cx16 : Flag<["-"], "mno-cx16">, Group; def menqcmd : Flag<["-"], "menqcmd">, Group; def mno_enqcmd : Flag<["-"], "mno-enqcmd">, Group; -def mevex512 : Flag<["-"], "mevex512">, Group, - Visibility<[ClangOption, CLOption, FlangOption]>; -def mno_evex512 : Flag<["-"], "mno-evex512">, Group, - Visibility<[ClangOption, CLOption, FlangOption]>; def mf16c : Flag<["-"], "mf16c">, Group; def mno_f16c : Flag<["-"], "mno-f16c">, Group; def mfma : Flag<["-"], "mfma">, Group; diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp index f9424cb68ad7e..6eb4db51d4e6e 100644 --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -165,14 +165,6 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabled(Features, F, true); std::vector UpdatedFeaturesVec; - std::vector UpdatedAVX10FeaturesVec; - enum { FE_NOSET = -1, FE_FALSE, FE_TRUE }; - int HasEVEX512 = FE_NOSET; - bool HasAVX512F = Features.lookup("avx512f"); - bool HasAVX10 = Features.lookup("avx10.1-256"); - bool HasAVX10_512 = Features.lookup("avx10.1-512"); - std::string LastAVX10; - std::string LastAVX512; for (const auto &Feature : FeaturesVec) { // Expand general-regs-only to -x86, -mmx and -sse if (Feature == "+general-regs-only") { @@ -182,51 +174,8 @@ bool X86TargetInfo::initFeatureMap( continue; } - if (Feature.substr(1, 6) == "avx10.") { - if (Feature[0] == '+') { - HasAVX10 = true; - if (StringRef(Feature).ends_with("512")) - HasAVX10_512 = true; - LastAVX10 = Feature; - } else if (HasAVX10 && Feature == "-avx10.1-256") { - HasAVX10 = false; - HasAVX10_512 = false; - } else if (HasAVX10_512 && Feature == "-avx10.1-512") { - HasAVX10_512 = false; - } - // Postpone AVX10 features handling after AVX512 settled. - UpdatedAVX10FeaturesVec.push_back(Feature); - continue; - } else if (!HasAVX512F && StringRef(Feature).starts_with("+avx512")) { - HasAVX512F = true; - LastAVX512 = Feature; - } else if (HasAVX512F && Feature == "-avx512f") { - HasAVX512F = false; - } else if (HasEVEX512 != FE_TRUE && Feature == "+evex512") { - HasEVEX512 = FE_TRUE; - continue; - } else if (HasEVEX512 != FE_FALSE && Feature == "-evex512") { - HasEVEX512 = FE_FALSE; - continue; - } - UpdatedFeaturesVec.push_back(Feature); } - llvm::append_range(UpdatedFeaturesVec, UpdatedAVX10FeaturesVec); - // HasEVEX512 is a three-states flag. We need to turn it into [+-]evex512 - // according to other features. - if (!HasAVX10_512 && HasAVX512F) { - UpdatedFeaturesVec.push_back(HasEVEX512 == FE_FALSE ? "-evex512" - : "+evex512"); - if (HasAVX10 && HasEVEX512 != FE_FALSE) - Diags.Report(diag::warn_invalid_feature_combination) - << LastAVX512 + " " + LastAVX10 + "; will be promoted to avx10.1-512"; - } else if (HasAVX10) { - if (!HasAVX512F && HasEVEX512 != FE_NOSET) - Diags.Report(diag::warn_invalid_feature_combination) - << LastAVX10 + (HasEVEX512 == FE_TRUE ? " +evex512" : " -evex512"); - UpdatedFeaturesVec.push_back(HasAVX10_512 ? "+evex512" : "-evex512"); - } if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec)) return false; @@ -327,17 +276,11 @@ bool X86TargetInfo::handleTargetFeatures(std::vector &Features, HasF16C = true; } else if (Feature == "+gfni") { HasGFNI = true; - } else if (Feature == "+evex512") { - HasEVEX512 = true; - } else if (Feature == "+avx10.1-256") { + } else if (Feature == "+avx10.1") { HasAVX10_1 = true; - } else if (Feature == "+avx10.1-512") { - HasAVX10_1_512 = true; - } else if (Feature == "+avx10.2-256") { + } else if (Feature == "+avx10.2") { HasAVX10_2 = true; HasFullBFloat16 = true; - } else if (Feature == "+avx10.2-512") { - HasAVX10_2_512 = true; } else if (Feature == "+avx512cd") { HasAVX512CD = true; } else if (Feature == "+avx512vpopcntdq") { @@ -868,16 +811,14 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasGFNI) Builder.defineMacro("__GFNI__"); - if (HasEVEX512) - Builder.defineMacro("__EVEX512__"); - if (HasAVX10_1) + if (HasAVX10_1) { Builder.defineMacro("__AVX10_1__"); - if (HasAVX10_1_512) Builder.defineMacro("__AVX10_1_512__"); - if (HasAVX10_2) + } + if (HasAVX10_2) { Builder.defineMacro("__AVX10_2__"); - if (HasAVX10_2_512) Builder.defineMacro("__AVX10_2_512__"); + } if (HasAVX512CD) Builder.defineMacro("__AVX512CD__"); if (HasAVX512VPOPCNTDQ) @@ -896,7 +837,6 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__AVX512BW__"); if (HasAVX512VL) { Builder.defineMacro("__AVX512VL__"); - Builder.defineMacro("__EVEX256__"); } if (HasAVX512VBMI) Builder.defineMacro("__AVX512VBMI__"); @@ -1128,10 +1068,8 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("amx-tile", true) .Case("amx-transpose", true) .Case("avx", true) - .Case("avx10.1-256", true) - .Case("avx10.1-512", true) - .Case("avx10.2-256", true) - .Case("avx10.2-512", true) + .Case("avx10.1", true) + .Case("avx10.2", true) .Case("avx2", true) .Case("avx512f", true) .Case("avx512cd", true) @@ -1162,7 +1100,6 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const { .Case("crc32", true) .Case("cx16", true) .Case("enqcmd", true) - .Case("evex512", true) .Case("f16c", true) .Case("fma", true) .Case("fma4", true) @@ -1252,10 +1189,8 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("amx-tile", HasAMXTILE) .Case("amx-transpose", HasAMXTRANSPOSE) .Case("avx", SSELevel >= AVX) - .Case("avx10.1-256", HasAVX10_1) - .Case("avx10.1-512", HasAVX10_1_512) - .Case("avx10.2-256", HasAVX10_2) - .Case("avx10.2-512", HasAVX10_2_512) + .Case("avx10.1", HasAVX10_1) + .Case("avx10.2", HasAVX10_2) .Case("avx2", SSELevel >= AVX2) .Case("avx512f", SSELevel >= AVX512F) .Case("avx512cd", HasAVX512CD) @@ -1287,7 +1222,6 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("cx8", HasCX8) .Case("cx16", HasCX16) .Case("enqcmd", HasENQCMD) - .Case("evex512", HasEVEX512) .Case("f16c", HasF16C) .Case("fma", HasFMA) .Case("fma4", XOPLevel >= FMA4) @@ -1766,9 +1700,8 @@ bool X86TargetInfo::validateOperandSize(const llvm::StringMap &FeatureMap, return Size <= 64; case 'z': // XMM0/YMM/ZMM0 - if (hasFeatureEnabled(FeatureMap, "avx512f") && - hasFeatureEnabled(FeatureMap, "evex512")) - // ZMM0 can be used if target supports AVX512F and EVEX512 is set. + if (hasFeatureEnabled(FeatureMap, "avx512f")) + // ZMM0 can be used if target supports AVX512F. return Size <= 512U; else if (hasFeatureEnabled(FeatureMap, "avx")) // YMM0 can be used if target supports AVX. @@ -1787,10 +1720,8 @@ bool X86TargetInfo::validateOperandSize(const llvm::StringMap &FeatureMap, break; case 'v': case 'x': - if (hasFeatureEnabled(FeatureMap, "avx512f") && - hasFeatureEnabled(FeatureMap, "evex512")) - // 512-bit zmm registers can be used if target supports AVX512F and - // EVEX512 is set. + if (hasFeatureEnabled(FeatureMap, "avx512f")) + // 512-bit zmm registers can be used if target supports AVX512F. return Size <= 512U; else if (hasFeatureEnabled(FeatureMap, "avx")) // 256-bit ymm registers can be used if target supports AVX. diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h index eb151034dec85..6e013c95dbf01 100644 --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -95,10 +95,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo { bool HasFMA = false; bool HasF16C = false; bool HasAVX10_1 = false; - bool HasAVX10_1_512 = false; bool HasAVX10_2 = false; - bool HasAVX10_2_512 = false; - bool HasEVEX512 = false; bool HasAVX512CD = false; bool HasAVX512VPOPCNTDQ = false; bool HasAVX512VNNI = false; diff --git a/clang/lib/CodeGen/Targets/X86.cpp b/clang/lib/CodeGen/Targets/X86.cpp index 71db63bb89645..7ee8a0dc2a0db 100644 --- a/clang/lib/CodeGen/Targets/X86.cpp +++ b/clang/lib/CodeGen/Targets/X86.cpp @@ -1533,24 +1533,6 @@ static bool checkAVXParamFeature(DiagnosticsEngine &Diag, return false; } -static bool checkAVX512ParamFeature(DiagnosticsEngine &Diag, - SourceLocation CallLoc, - const llvm::StringMap &CallerMap, - const llvm::StringMap &CalleeMap, - QualType Ty, bool IsArgument) { - bool Caller256 = CallerMap.lookup("avx512f") && !CallerMap.lookup("evex512"); - bool Callee256 = CalleeMap.lookup("avx512f") && !CalleeMap.lookup("evex512"); - - // Forbid 512-bit or larger vector pass or return when we disabled ZMM - // instructions. - if (Caller256 || Callee256) - return Diag.Report(CallLoc, diag::err_avx_calling_convention) - << IsArgument << Ty << "evex512"; - - return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, - "avx512f", IsArgument); -} - static bool checkAVXParam(DiagnosticsEngine &Diag, ASTContext &Ctx, SourceLocation CallLoc, const llvm::StringMap &CallerMap, @@ -1558,8 +1540,8 @@ static bool checkAVXParam(DiagnosticsEngine &Diag, ASTContext &Ctx, bool IsArgument) { uint64_t Size = Ctx.getTypeSize(Ty); if (Size > 256) - return checkAVX512ParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, - IsArgument); + return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, + "avx512f", IsArgument); if (Size > 128) return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, "avx", diff --git a/clang/lib/Driver/ToolChains/Arch/X86.cpp b/clang/lib/Driver/ToolChains/Arch/X86.cpp index b22faac3b0779..1373905a5120e 100644 --- a/clang/lib/Driver/ToolChains/Arch/X86.cpp +++ b/clang/lib/Driver/ToolChains/Arch/X86.cpp @@ -226,40 +226,6 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple, << D.getOpts().getOptionName(LVIOpt); } - for (const Arg *A : Args.filtered(options::OPT_m_x86_AVX10_Features_Group)) { - StringRef Name = A->getOption().getName(); - A->claim(); - - // Skip over "-m". - assert(Name.starts_with("m") && "Invalid feature name."); - Name = Name.substr(1); - - bool IsNegative = Name.consume_front("no-"); - - StringRef Version, Width; - std::tie(Version, Width) = Name.substr(6).split('-'); - assert(Name.starts_with("avx10.") && "Invalid AVX10 feature name."); - assert((Version == "1" || Version == "2") && "Invalid AVX10 feature name."); - - if (Width == "") { - if (IsNegative) - Features.push_back(Args.MakeArgString("-" + Name + "-256")); - else - Features.push_back(Args.MakeArgString("+" + Name + "-512")); - } else { - if (Width == "512") - D.Diag(diag::warn_drv_deprecated_arg) << Name << 1 << Name.drop_back(4); - else if (Width == "256") - D.Diag(diag::warn_drv_deprecated_custom) - << Name - << "no alternative argument provided because " - "AVX10/256 is not supported and will be removed"; - else - assert((Width == "256" || Width == "512") && "Invalid vector length."); - Features.push_back(Args.MakeArgString((IsNegative ? "-" : "+") + Name)); - } - } - // Now add any that the user explicitly requested on the command line, // which may override the defaults. for (const Arg *A : Args.filtered(options::OPT_m_x86_Features_Group, @@ -284,13 +250,6 @@ void x86::getX86TargetFeatures(const Driver &D, const llvm::Triple &Triple, D.Diag(diag::err_drv_unsupported_opt_for_target) << A->getSpelling() << Triple.getTriple(); - if (A->getOption().matches(options::OPT_mevex512) || - A->getOption().matches(options::OPT_mno_evex512)) - D.Diag(diag::warn_drv_deprecated_custom) - << Name - << "no alternative argument provided because " - "AVX10/256 is not supported and will be removed"; - if (A->getOption().matches(options::OPT_mapx_features_EQ) || A->getOption().matches(options::OPT_mno_apx_features_EQ)) { diff --git a/clang/lib/Headers/amxavx512intrin.h b/clang/lib/Headers/amxavx512intrin.h index bbde44fc265b3..373a54f46290f 100644 --- a/clang/lib/Headers/amxavx512intrin.h +++ b/clang/lib/Headers/amxavx512intrin.h @@ -16,7 +16,7 @@ #define __DEFAULT_FN_ATTRS_AVX512 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("amx-avx512,avx10.2-512"))) + __target__("amx-avx512,avx10.2"))) /// Moves a row from a tile register to a zmm destination register, converting /// the int32 source elements to fp32. The row of the tile is selected by a diff --git a/clang/lib/Headers/avx10_2_512bf16intrin.h b/clang/lib/Headers/avx10_2_512bf16intrin.h index 95e9bd7a36f9b..37ebc4f46a826 100644 --- a/clang/lib/Headers/avx10_2_512bf16intrin.h +++ b/clang/lib/Headers/avx10_2_512bf16intrin.h @@ -21,7 +21,7 @@ typedef __bf16 __m512bh_u __attribute__((__vector_size__(64), __aligned__(1))); /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS512 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(512))) static __inline __m512bh __DEFAULT_FN_ATTRS512 _mm512_setzero_pbh(void) { diff --git a/clang/lib/Headers/avx10_2_512convertintrin.h b/clang/lib/Headers/avx10_2_512convertintrin.h index ee8cbf28ca41c..ffaed08cee798 100644 --- a/clang/lib/Headers/avx10_2_512convertintrin.h +++ b/clang/lib/Headers/avx10_2_512convertintrin.h @@ -18,7 +18,7 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS512 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(512))) static __inline__ __m512h __DEFAULT_FN_ATTRS512 _mm512_cvtx2ps_ph(__m512 __A, diff --git a/clang/lib/Headers/avx10_2_512niintrin.h b/clang/lib/Headers/avx10_2_512niintrin.h index 9d96e36c74ca4..67679fce82296 100644 --- a/clang/lib/Headers/avx10_2_512niintrin.h +++ b/clang/lib/Headers/avx10_2_512niintrin.h @@ -17,7 +17,7 @@ #define __AVX10_2_512NIINTRIN_H #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(512))) /* VNNI FP16 */ diff --git a/clang/lib/Headers/avx10_2_512satcvtdsintrin.h b/clang/lib/Headers/avx10_2_512satcvtdsintrin.h index 012a6282b5b18..3688f4c0dfd0f 100644 --- a/clang/lib/Headers/avx10_2_512satcvtdsintrin.h +++ b/clang/lib/Headers/avx10_2_512satcvtdsintrin.h @@ -16,7 +16,7 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(512))) // 512 bit : Double -> Int diff --git a/clang/lib/Headers/avx10_2bf16intrin.h b/clang/lib/Headers/avx10_2bf16intrin.h index 0c7f381f04fa5..5bcec4bdaa2b2 100644 --- a/clang/lib/Headers/avx10_2bf16intrin.h +++ b/clang/lib/Headers/avx10_2bf16intrin.h @@ -21,10 +21,10 @@ typedef __bf16 __m256bh_u __attribute__((__vector_size__(32), __aligned__(1))); /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(256))) #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(128))) static __inline __m256bh __DEFAULT_FN_ATTRS256 _mm256_setzero_pbh(void) { diff --git a/clang/lib/Headers/avx10_2convertintrin.h b/clang/lib/Headers/avx10_2convertintrin.h index 19d91d41f7bde..2800ee73118d7 100644 --- a/clang/lib/Headers/avx10_2convertintrin.h +++ b/clang/lib/Headers/avx10_2convertintrin.h @@ -18,10 +18,10 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(256))) // clang-format off diff --git a/clang/lib/Headers/avx10_2copyintrin.h b/clang/lib/Headers/avx10_2copyintrin.h index 76b8f8ced540d..37dc06ac9ebce 100644 --- a/clang/lib/Headers/avx10_2copyintrin.h +++ b/clang/lib/Headers/avx10_2copyintrin.h @@ -16,7 +16,7 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(128))) /// Constructs a 128-bit integer vector, setting the lower 32 bits to the diff --git a/clang/lib/Headers/avx10_2niintrin.h b/clang/lib/Headers/avx10_2niintrin.h index d5a66cfef536c..9a772ec434f4e 100644 --- a/clang/lib/Headers/avx10_2niintrin.h +++ b/clang/lib/Headers/avx10_2niintrin.h @@ -16,10 +16,10 @@ #define __AVX10_2NIINTRIN_H #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(256))) /* VNNI FP16 */ diff --git a/clang/lib/Headers/avx10_2satcvtdsintrin.h b/clang/lib/Headers/avx10_2satcvtdsintrin.h index cc840368c308f..57d299606a173 100644 --- a/clang/lib/Headers/avx10_2satcvtdsintrin.h +++ b/clang/lib/Headers/avx10_2satcvtdsintrin.h @@ -17,11 +17,11 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(256))) #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx10.2-256"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx10.2"), \ __min_vector_width__(128))) #define _mm_cvtts_roundsd_i32(__A, __R) \ diff --git a/clang/lib/Headers/avx2intrin.h b/clang/lib/Headers/avx2intrin.h index 5a32312be200e..578d42cd28acb 100644 --- a/clang/lib/Headers/avx2intrin.h +++ b/clang/lib/Headers/avx2intrin.h @@ -15,21 +15,12 @@ #define __AVX2INTRIN_H /* Define the default attributes for the functions in this file. */ -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -#define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx2,no-evex512"), __min_vector_width__(256))) -#define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx2,no-evex512"), __min_vector_width__(128))) -#else #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, __target__("avx2"), \ __min_vector_width__(256))) #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, __target__("avx2"), \ __min_vector_width__(128))) -#endif #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr diff --git a/clang/lib/Headers/avx512bf16intrin.h b/clang/lib/Headers/avx512bf16intrin.h index b28d2e243f2cb..3973f0e389685 100644 --- a/clang/lib/Headers/avx512bf16intrin.h +++ b/clang/lib/Headers/avx512bf16intrin.h @@ -19,12 +19,11 @@ typedef __bf16 __v32bf __attribute__((__vector_size__(64), __aligned__(64))); typedef __bf16 __m512bh __attribute__((__vector_size__(64), __aligned__(64))); typedef __bf16 __bfloat16 __attribute__((deprecated("use __bf16 instead"))); -#define __DEFAULT_FN_ATTRS512 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx512bf16,evex512"), \ +#define __DEFAULT_FN_ATTRS512 \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512bf16"), \ __min_vector_width__(512))) #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512bf16,no-evex512"))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512bf16"))) /// Convert One BF16 Data to One Single Float Data. /// diff --git a/clang/lib/Headers/avx512bitalgintrin.h b/clang/lib/Headers/avx512bitalgintrin.h index 5cc32077c2c04..98197e468370d 100644 --- a/clang/lib/Headers/avx512bitalgintrin.h +++ b/clang/lib/Headers/avx512bitalgintrin.h @@ -16,8 +16,7 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512bitalg,evex512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512bitalg"), \ __min_vector_width__(512))) #if defined(__cplusplus) && (__cplusplus >= 201103L) diff --git a/clang/lib/Headers/avx512bwintrin.h b/clang/lib/Headers/avx512bwintrin.h index a08735b937704..f19d21009a23f 100644 --- a/clang/lib/Headers/avx512bwintrin.h +++ b/clang/lib/Headers/avx512bwintrin.h @@ -19,11 +19,10 @@ typedef unsigned long long __mmask64; /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS512 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512bw,evex512"), __min_vector_width__(512))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512bw"), \ + __min_vector_width__(512))) #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512bw,no-evex512"))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512bw"))) #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS512_CONSTEXPR __DEFAULT_FN_ATTRS512 constexpr diff --git a/clang/lib/Headers/avx512cdintrin.h b/clang/lib/Headers/avx512cdintrin.h index 39e76711ca7b3..ac8120e3f7afa 100644 --- a/clang/lib/Headers/avx512cdintrin.h +++ b/clang/lib/Headers/avx512cdintrin.h @@ -16,8 +16,8 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512cd,evex512"), __min_vector_width__(512))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512cd"), \ + __min_vector_width__(512))) #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr diff --git a/clang/lib/Headers/avx512dqintrin.h b/clang/lib/Headers/avx512dqintrin.h index ee211d3eae9d7..95fdc2851cb9b 100644 --- a/clang/lib/Headers/avx512dqintrin.h +++ b/clang/lib/Headers/avx512dqintrin.h @@ -15,10 +15,11 @@ #define __AVX512DQINTRIN_H /* Define the default attributes for the functions in this file. */ -#define __DEFAULT_FN_ATTRS512 __attribute__((__always_inline__, __nodebug__, __target__("avx512dq,evex512"), __min_vector_width__(512))) +#define __DEFAULT_FN_ATTRS512 \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512dq"), \ + __min_vector_width__(512))) #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512dq,no-evex512"))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512dq"))) #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS512_CONSTEXPR __DEFAULT_FN_ATTRS512 constexpr diff --git a/clang/lib/Headers/avx512fintrin.h b/clang/lib/Headers/avx512fintrin.h index 3e285f031ffe8..d14a2249d828b 100644 --- a/clang/lib/Headers/avx512fintrin.h +++ b/clang/lib/Headers/avx512fintrin.h @@ -167,13 +167,14 @@ typedef enum } _MM_MANTISSA_SIGN_ENUM; /* Define the default attributes for the functions in this file. */ -#define __DEFAULT_FN_ATTRS512 __attribute__((__always_inline__, __nodebug__, __target__("avx512f,evex512"), __min_vector_width__(512))) +#define __DEFAULT_FN_ATTRS512 \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512f"), \ + __min_vector_width__(512))) #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512f,no-evex512"), __min_vector_width__(128))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512f"), \ + __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512f,no-evex512"))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512f"))) #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr diff --git a/clang/lib/Headers/avx512fp16intrin.h b/clang/lib/Headers/avx512fp16intrin.h index 5a5d21d2dc790..d30b49e552e1b 100644 --- a/clang/lib/Headers/avx512fp16intrin.h +++ b/clang/lib/Headers/avx512fp16intrin.h @@ -22,15 +22,13 @@ typedef _Float16 __m512h_u __attribute__((__vector_size__(64), __aligned__(1))); /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS512 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512fp16,evex512"), __min_vector_width__(512))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512fp16"), \ + __min_vector_width__(512))) #define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512fp16,no-evex512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512fp16"), \ __min_vector_width__(256))) #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512fp16,no-evex512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512fp16"), \ __min_vector_width__(128))) #if defined(__cplusplus) && (__cplusplus >= 201103L) diff --git a/clang/lib/Headers/avx512ifmaintrin.h b/clang/lib/Headers/avx512ifmaintrin.h index 9468d17556e72..f01b322ce7787 100644 --- a/clang/lib/Headers/avx512ifmaintrin.h +++ b/clang/lib/Headers/avx512ifmaintrin.h @@ -16,8 +16,8 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512ifma,evex512"), __min_vector_width__(512))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512ifma"), \ + __min_vector_width__(512))) static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_madd52hi_epu64 (__m512i __X, __m512i __Y, __m512i __Z) diff --git a/clang/lib/Headers/avx512ifmavlintrin.h b/clang/lib/Headers/avx512ifmavlintrin.h index 8787cd471d423..a72b56113a12b 100644 --- a/clang/lib/Headers/avx512ifmavlintrin.h +++ b/clang/lib/Headers/avx512ifmavlintrin.h @@ -17,11 +17,11 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512ifma,avx512vl,no-evex512"), \ + __target__("avx512ifma,avx512vl"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512ifma,avx512vl,no-evex512"), \ + __target__("avx512ifma,avx512vl"), \ __min_vector_width__(256))) #define _mm_madd52hi_epu64(X, Y, Z) \ diff --git a/clang/lib/Headers/avx512vbmi2intrin.h b/clang/lib/Headers/avx512vbmi2intrin.h index f9a5f82b61f82..012053332c539 100644 --- a/clang/lib/Headers/avx512vbmi2intrin.h +++ b/clang/lib/Headers/avx512vbmi2intrin.h @@ -15,8 +15,9 @@ #define __AVX512VBMI2INTRIN_H /* Define the default attributes for the functions in this file. */ -#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("avx512vbmi2,evex512"), __min_vector_width__(512))) - +#define __DEFAULT_FN_ATTRS \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512vbmi2"), \ + __min_vector_width__(512))) static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_mask_compress_epi16(__m512i __S, __mmask32 __U, __m512i __D) diff --git a/clang/lib/Headers/avx512vbmiintrin.h b/clang/lib/Headers/avx512vbmiintrin.h index e47cd5caddaad..964535c4c4900 100644 --- a/clang/lib/Headers/avx512vbmiintrin.h +++ b/clang/lib/Headers/avx512vbmiintrin.h @@ -16,8 +16,8 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vbmi,evex512"), __min_vector_width__(512))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512vbmi"), \ + __min_vector_width__(512))) static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_permutex2var_epi8(__m512i __A, __m512i __I, __m512i __B) diff --git a/clang/lib/Headers/avx512vbmivlintrin.h b/clang/lib/Headers/avx512vbmivlintrin.h index 848ca2d18c3ce..4c50be7d9e7e5 100644 --- a/clang/lib/Headers/avx512vbmivlintrin.h +++ b/clang/lib/Headers/avx512vbmivlintrin.h @@ -17,11 +17,11 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vbmi,avx512vl,no-evex512"), \ + __target__("avx512vbmi,avx512vl"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vbmi,avx512vl,no-evex512"), \ + __target__("avx512vbmi,avx512vl"), \ __min_vector_width__(256))) static __inline__ __m128i __DEFAULT_FN_ATTRS128 diff --git a/clang/lib/Headers/avx512vlbf16intrin.h b/clang/lib/Headers/avx512vlbf16intrin.h index 89c9f49c7aed0..2d7ea0114d6a5 100644 --- a/clang/lib/Headers/avx512vlbf16intrin.h +++ b/clang/lib/Headers/avx512vlbf16intrin.h @@ -17,11 +17,11 @@ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512bf16,no-evex512"), \ + __target__("avx512vl,avx512bf16"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512bf16,no-evex512"), \ + __target__("avx512vl,avx512bf16"), \ __min_vector_width__(256))) /// Convert Two Packed Single Data to One Packed BF16 Data. diff --git a/clang/lib/Headers/avx512vlbitalgintrin.h b/clang/lib/Headers/avx512vlbitalgintrin.h index 21bf858a20c59..1874adce4ea6e 100644 --- a/clang/lib/Headers/avx512vlbitalgintrin.h +++ b/clang/lib/Headers/avx512vlbitalgintrin.h @@ -17,11 +17,11 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512bitalg,no-evex512"), \ + __target__("avx512vl,avx512bitalg"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512bitalg,no-evex512"), \ + __target__("avx512vl,avx512bitalg"), \ __min_vector_width__(256))) #if defined(__cplusplus) && (__cplusplus >= 201103L) diff --git a/clang/lib/Headers/avx512vlbwintrin.h b/clang/lib/Headers/avx512vlbwintrin.h index 888086dc214f1..ff57553f8cd9c 100644 --- a/clang/lib/Headers/avx512vlbwintrin.h +++ b/clang/lib/Headers/avx512vlbwintrin.h @@ -17,12 +17,10 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512bw,no-evex512"), \ - __min_vector_width__(128))) + __target__("avx512vl,avx512bw"), __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512bw,no-evex512"), \ - __min_vector_width__(256))) + __target__("avx512vl,avx512bw"), __min_vector_width__(256))) #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS128_CONSTEXPR __DEFAULT_FN_ATTRS128 constexpr diff --git a/clang/lib/Headers/avx512vlcdintrin.h b/clang/lib/Headers/avx512vlcdintrin.h index 8f42675ba9b5d..9020374353977 100644 --- a/clang/lib/Headers/avx512vlcdintrin.h +++ b/clang/lib/Headers/avx512vlcdintrin.h @@ -16,12 +16,10 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512cd,no-evex512"), \ - __min_vector_width__(128))) + __target__("avx512vl,avx512cd"), __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512cd,no-evex512"), \ - __min_vector_width__(256))) + __target__("avx512vl,avx512cd"), __min_vector_width__(256))) #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr diff --git a/clang/lib/Headers/avx512vldqintrin.h b/clang/lib/Headers/avx512vldqintrin.h index e93eb10c31ce2..e23a92151a055 100644 --- a/clang/lib/Headers/avx512vldqintrin.h +++ b/clang/lib/Headers/avx512vldqintrin.h @@ -17,12 +17,10 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512dq,no-evex512"), \ - __min_vector_width__(128))) + __target__("avx512vl,avx512dq"), __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512dq,no-evex512"), \ - __min_vector_width__(256))) + __target__("avx512vl,avx512dq"), __min_vector_width__(256))) #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS256_CONSTEXPR __DEFAULT_FN_ATTRS256 constexpr diff --git a/clang/lib/Headers/avx512vlfp16intrin.h b/clang/lib/Headers/avx512vlfp16intrin.h index 3b10050a01f66..573533bd895f0 100644 --- a/clang/lib/Headers/avx512vlfp16intrin.h +++ b/clang/lib/Headers/avx512vlfp16intrin.h @@ -19,11 +19,11 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512fp16,avx512vl,no-evex512"), \ + __target__("avx512fp16,avx512vl"), \ __min_vector_width__(256))) #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512fp16,avx512vl,no-evex512"), \ + __target__("avx512fp16,avx512vl"), \ __min_vector_width__(128))) #if defined(__cplusplus) && (__cplusplus >= 201103L) diff --git a/clang/lib/Headers/avx512vlintrin.h b/clang/lib/Headers/avx512vlintrin.h index e7e02624f56c0..faccb0929193a 100644 --- a/clang/lib/Headers/avx512vlintrin.h +++ b/clang/lib/Headers/avx512vlintrin.h @@ -15,12 +15,10 @@ #define __AVX512VLINTRIN_H #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,no-evex512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512vl"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,no-evex512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512vl"), \ __min_vector_width__(256))) #if defined(__cplusplus) && (__cplusplus >= 201103L) diff --git a/clang/lib/Headers/avx512vlvbmi2intrin.h b/clang/lib/Headers/avx512vlvbmi2intrin.h index 04db52c822640..3d6e99b2f0bd8 100644 --- a/clang/lib/Headers/avx512vlvbmi2intrin.h +++ b/clang/lib/Headers/avx512vlvbmi2intrin.h @@ -17,11 +17,11 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512vbmi2,no-evex512"), \ + __target__("avx512vl,avx512vbmi2"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512vbmi2,no-evex512"), \ + __target__("avx512vl,avx512vbmi2"), \ __min_vector_width__(256))) static __inline__ __m128i __DEFAULT_FN_ATTRS128 diff --git a/clang/lib/Headers/avx512vlvnniintrin.h b/clang/lib/Headers/avx512vlvnniintrin.h index d1e5cd9d6983f..bc76348c13df9 100644 --- a/clang/lib/Headers/avx512vlvnniintrin.h +++ b/clang/lib/Headers/avx512vlvnniintrin.h @@ -17,11 +17,11 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512vnni,no-evex512"), \ + __target__("avx512vl,avx512vnni"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512vnni,no-evex512"), \ + __target__("avx512vl,avx512vnni"), \ __min_vector_width__(256))) /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a A with diff --git a/clang/lib/Headers/avx512vlvp2intersectintrin.h b/clang/lib/Headers/avx512vlvp2intersectintrin.h index 63a31241a5ede..8cb33169e570b 100644 --- a/clang/lib/Headers/avx512vlvp2intersectintrin.h +++ b/clang/lib/Headers/avx512vlvp2intersectintrin.h @@ -30,12 +30,12 @@ #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512vp2intersect,no-evex512"), \ + __target__("avx512vl,avx512vp2intersect"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vl,avx512vp2intersect,no-evex512"), \ + __target__("avx512vl,avx512vp2intersect"), \ __min_vector_width__(256))) /// Store, in an even/odd pair of mask registers, the indicators of the /// locations of value matches between dwords in operands __a and __b. diff --git a/clang/lib/Headers/avx512vnniintrin.h b/clang/lib/Headers/avx512vnniintrin.h index 0fb381a12f2fd..0b722af8d0e1d 100644 --- a/clang/lib/Headers/avx512vnniintrin.h +++ b/clang/lib/Headers/avx512vnniintrin.h @@ -16,8 +16,8 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vnni,evex512"), __min_vector_width__(512))) + __attribute__((__always_inline__, __nodebug__, __target__("avx512vnni"), \ + __min_vector_width__(512))) static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_dpbusd_epi32(__m512i __S, __m512i __A, __m512i __B) diff --git a/clang/lib/Headers/avx512vp2intersectintrin.h b/clang/lib/Headers/avx512vp2intersectintrin.h index 16552cae3b4fb..7d999960a574b 100644 --- a/clang/lib/Headers/avx512vp2intersectintrin.h +++ b/clang/lib/Headers/avx512vp2intersectintrin.h @@ -30,8 +30,7 @@ #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vp2intersect,evex512"), \ - __min_vector_width__(512))) + __target__("avx512vp2intersect"), __min_vector_width__(512))) /// Store, in an even/odd pair of mask registers, the indicators of the /// locations of value matches between dwords in operands __a and __b. diff --git a/clang/lib/Headers/avx512vpopcntdqintrin.h b/clang/lib/Headers/avx512vpopcntdqintrin.h index ac71808f69803..cc884fea41c7b 100644 --- a/clang/lib/Headers/avx512vpopcntdqintrin.h +++ b/clang/lib/Headers/avx512vpopcntdqintrin.h @@ -19,13 +19,12 @@ #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vpopcntdq,evex512"), \ + __target__("avx512vpopcntdq"), \ __min_vector_width__(512))) constexpr #else #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vpopcntdq,evex512"), \ - __min_vector_width__(512))) + __target__("avx512vpopcntdq"), __min_vector_width__(512))) #endif static __inline__ __m512i __DEFAULT_FN_ATTRS _mm512_popcnt_epi64(__m512i __A) { diff --git a/clang/lib/Headers/avx512vpopcntdqvlintrin.h b/clang/lib/Headers/avx512vpopcntdqvlintrin.h index bed951b764cf7..9b26aa1e634c4 100644 --- a/clang/lib/Headers/avx512vpopcntdqvlintrin.h +++ b/clang/lib/Headers/avx512vpopcntdqvlintrin.h @@ -20,20 +20,20 @@ #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vpopcntdq,avx512vl,no-evex512"), \ + __target__("avx512vpopcntdq,avx512vl"), \ __min_vector_width__(128))) constexpr #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vpopcntdq,avx512vl,no-evex512"), \ + __target__("avx512vpopcntdq,avx512vl"), \ __min_vector_width__(256))) constexpr #else #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vpopcntdq,avx512vl,no-evex512"), \ + __target__("avx512vpopcntdq,avx512vl"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512vpopcntdq,avx512vl,no-evex512"), \ + __target__("avx512vpopcntdq,avx512vl"), \ __min_vector_width__(256))) #endif diff --git a/clang/lib/Headers/avxintrin.h b/clang/lib/Headers/avxintrin.h index 03c034f64cbea..bfd62dfd9a6b2 100644 --- a/clang/lib/Headers/avxintrin.h +++ b/clang/lib/Headers/avxintrin.h @@ -50,21 +50,12 @@ typedef __bf16 __m256bh __attribute__((__vector_size__(32), __aligned__(32))); #endif /* Define the default attributes for the functions in this file. */ -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -#define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \ - __min_vector_width__(256))) -#define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \ - __min_vector_width__(128))) -#else #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, __target__("avx"), \ __min_vector_width__(256))) #define __DEFAULT_FN_ATTRS128 \ __attribute__((__always_inline__, __nodebug__, __target__("avx"), \ __min_vector_width__(128))) -#endif #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr diff --git a/clang/lib/Headers/emmintrin.h b/clang/lib/Headers/emmintrin.h index 482632157d9b4..a366e0df407a9 100644 --- a/clang/lib/Headers/emmintrin.h +++ b/clang/lib/Headers/emmintrin.h @@ -44,15 +44,9 @@ typedef __bf16 __m128bh __attribute__((__vector_size__(16), __aligned__(16))); #endif /* Define the default attributes for the functions in this file. */ -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -#define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("sse2,no-evex512"), __min_vector_width__(128))) -#else #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, __target__("sse2"), \ __min_vector_width__(128))) -#endif #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr diff --git a/clang/lib/Headers/fmaintrin.h b/clang/lib/Headers/fmaintrin.h index a1c117e5f9d89..c51009079f8d5 100644 --- a/clang/lib/Headers/fmaintrin.h +++ b/clang/lib/Headers/fmaintrin.h @@ -16,10 +16,10 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, __target__("fma,no-evex512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("fma"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, __target__("fma,no-evex512"), \ + __attribute__((__always_inline__, __nodebug__, __target__("fma"), \ __min_vector_width__(256))) #if defined(__cplusplus) && (__cplusplus >= 201103L) diff --git a/clang/lib/Headers/gfniintrin.h b/clang/lib/Headers/gfniintrin.h index 9a5743d4b673b..1df1eace63759 100644 --- a/clang/lib/Headers/gfniintrin.h +++ b/clang/lib/Headers/gfniintrin.h @@ -14,28 +14,6 @@ #ifndef __GFNIINTRIN_H #define __GFNIINTRIN_H -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -/* Default attributes for simple form (no masking). */ -#define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("gfni,no-evex512"), __min_vector_width__(128))) - -/* Default attributes for YMM unmasked form. */ -#define __DEFAULT_FN_ATTRS_Y \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx,gfni,no-evex512"), \ - __min_vector_width__(256))) - -/* Default attributes for VLX masked forms. */ -#define __DEFAULT_FN_ATTRS_VL128 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512bw,avx512vl,gfni,no-evex512"), \ - __min_vector_width__(128))) -#define __DEFAULT_FN_ATTRS_VL256 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512bw,avx512vl,gfni,no-evex512"), \ - __min_vector_width__(256))) -#else /* Default attributes for simple form (no masking). */ #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, __target__("gfni"), \ @@ -55,17 +33,14 @@ __attribute__((__always_inline__, __nodebug__, \ __target__("avx512bw,avx512vl,gfni"), \ __min_vector_width__(256))) -#endif /* Default attributes for ZMM unmasked forms. */ #define __DEFAULT_FN_ATTRS_Z \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512f,evex512,gfni"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512f,gfni"), \ __min_vector_width__(512))) /* Default attributes for ZMM masked forms. */ #define __DEFAULT_FN_ATTRS_Z_MASK \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512bw,evex512,gfni"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512bw,gfni"), \ __min_vector_width__(512))) #define _mm_gf2p8affineinv_epi64_epi8(A, B, I) \ diff --git a/clang/lib/Headers/mmintrin.h b/clang/lib/Headers/mmintrin.h index 4ed95c5b7bb71..18e2c2154362a 100644 --- a/clang/lib/Headers/mmintrin.h +++ b/clang/lib/Headers/mmintrin.h @@ -39,15 +39,9 @@ typedef short __v8hi __attribute__((__vector_size__(16))); typedef char __v16qi __attribute__((__vector_size__(16))); /* Define the default attributes for the functions in this file. */ -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -#define __DEFAULT_FN_ATTRS_SSE2 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("sse2,no-evex512"), __min_vector_width__(128))) -#else #define __DEFAULT_FN_ATTRS_SSE2 \ __attribute__((__always_inline__, __nodebug__, __target__("sse2"), \ __min_vector_width__(128))) -#endif #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_SSE2_CONSTEXPR __DEFAULT_FN_ATTRS_SSE2 constexpr @@ -71,9 +65,9 @@ typedef char __v16qi __attribute__((__vector_size__(16))); /// /// This intrinsic corresponds to the EMMS instruction. /// -static __inline__ void __attribute__((__always_inline__, __nodebug__, - __target__("mmx,no-evex512"))) -_mm_empty(void) { +static __inline__ void + __attribute__((__always_inline__, __nodebug__, __target__("mmx"))) + _mm_empty(void) { __builtin_ia32_emms(); } diff --git a/clang/lib/Headers/movrs_avx10_2_512intrin.h b/clang/lib/Headers/movrs_avx10_2_512intrin.h index 5cd907a597349..75d7ce93db7d4 100644 --- a/clang/lib/Headers/movrs_avx10_2_512intrin.h +++ b/clang/lib/Headers/movrs_avx10_2_512intrin.h @@ -17,8 +17,8 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS512 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("movrs, avx10.2-512"), __min_vector_width__(512))) + __attribute__((__always_inline__, __nodebug__, __target__("movrs, avx10.2"), \ + __min_vector_width__(512))) static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_loadrs_epi8(void const *__A) { diff --git a/clang/lib/Headers/movrs_avx10_2intrin.h b/clang/lib/Headers/movrs_avx10_2intrin.h index 27b625b6b4313..1c78b214fd7d0 100644 --- a/clang/lib/Headers/movrs_avx10_2intrin.h +++ b/clang/lib/Headers/movrs_avx10_2intrin.h @@ -17,11 +17,11 @@ /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS128 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("movrs,avx10.2-256"), __min_vector_width__(128))) + __attribute__((__always_inline__, __nodebug__, __target__("movrs,avx10.2"), \ + __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS256 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("movrs,avx10.2-256"), __min_vector_width__(256))) + __attribute__((__always_inline__, __nodebug__, __target__("movrs,avx10.2"), \ + __min_vector_width__(256))) static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_loadrs_epi8(void const *__A) { diff --git a/clang/lib/Headers/pmmintrin.h b/clang/lib/Headers/pmmintrin.h index cd605df7fb52d..f0c9b2ba38b0c 100644 --- a/clang/lib/Headers/pmmintrin.h +++ b/clang/lib/Headers/pmmintrin.h @@ -17,15 +17,9 @@ #include /* Define the default attributes for the functions in this file. */ -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -#define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("sse3,no-evex512"), __min_vector_width__(128))) -#else #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, __target__("sse3"), \ __min_vector_width__(128))) -#endif #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr diff --git a/clang/lib/Headers/sm4evexintrin.h b/clang/lib/Headers/sm4evexintrin.h index f6ae0037baea0..9c15d1fca96c9 100644 --- a/clang/lib/Headers/sm4evexintrin.h +++ b/clang/lib/Headers/sm4evexintrin.h @@ -14,8 +14,8 @@ #define __SM4EVEXINTRIN_H #define __DEFAULT_FN_ATTRS512 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("sm4,avx10.2-512"), __min_vector_width__(512))) + __attribute__((__always_inline__, __nodebug__, __target__("sm4,avx10.2"), \ + __min_vector_width__(512))) static __inline__ __m512i __DEFAULT_FN_ATTRS512 _mm512_sm4key4_epi32(__m512i __A, __m512i __B) { diff --git a/clang/lib/Headers/smmintrin.h b/clang/lib/Headers/smmintrin.h index 06b3da8b48dfe..a519cd6e2995f 100644 --- a/clang/lib/Headers/smmintrin.h +++ b/clang/lib/Headers/smmintrin.h @@ -17,15 +17,9 @@ #include /* Define the default attributes for the functions in this file. */ -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -#define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("sse4.1,no-evex512"), __min_vector_width__(128))) -#else #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, __target__("sse4.1"), \ __min_vector_width__(128))) -#endif #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr diff --git a/clang/lib/Headers/tmmintrin.h b/clang/lib/Headers/tmmintrin.h index f01c61afa8ea2..6e7107e36ea79 100644 --- a/clang/lib/Headers/tmmintrin.h +++ b/clang/lib/Headers/tmmintrin.h @@ -17,15 +17,9 @@ #include /* Define the default attributes for the functions in this file. */ -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -#define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("ssse3,no-evex512"), __min_vector_width__(128))) -#else #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, __target__("ssse3"), \ __min_vector_width__(128))) -#endif #define __trunc64(x) \ (__m64) __builtin_shufflevector((__v2di)(x), __extension__(__v2di){}, 0) diff --git a/clang/lib/Headers/vaesintrin.h b/clang/lib/Headers/vaesintrin.h index d7c162f5c0b16..5194ca6c50276 100644 --- a/clang/lib/Headers/vaesintrin.h +++ b/clang/lib/Headers/vaesintrin.h @@ -19,8 +19,7 @@ /* Default attributes for ZMM forms. */ #define __DEFAULT_FN_ATTRS_F \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("avx512f,evex512,vaes"), \ + __attribute__((__always_inline__, __nodebug__, __target__("avx512f,vaes"), \ __min_vector_width__(512))) static __inline__ __m256i __DEFAULT_FN_ATTRS diff --git a/clang/lib/Headers/xmmintrin.h b/clang/lib/Headers/xmmintrin.h index 08f562cc38bc8..4b52904315451 100644 --- a/clang/lib/Headers/xmmintrin.h +++ b/clang/lib/Headers/xmmintrin.h @@ -32,21 +32,12 @@ typedef unsigned short __v8hu __attribute__((__vector_size__(16))); #endif /* Define the default attributes for the functions in this file. */ -#if defined(__EVEX512__) && !defined(__AVX10_1_512__) -#define __DEFAULT_FN_ATTRS \ - __attribute__((__always_inline__, __nodebug__, __target__("sse,no-evex512"), \ - __min_vector_width__(128))) -#define __DEFAULT_FN_ATTRS_SSE2 \ - __attribute__((__always_inline__, __nodebug__, \ - __target__("sse2,no-evex512"), __min_vector_width__(128))) -#else #define __DEFAULT_FN_ATTRS \ __attribute__((__always_inline__, __nodebug__, __target__("sse"), \ __min_vector_width__(128))) #define __DEFAULT_FN_ATTRS_SSE2 \ __attribute__((__always_inline__, __nodebug__, __target__("sse2"), \ __min_vector_width__(128))) -#endif #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr diff --git a/clang/test/CodeGen/X86/amx_avx512_api.c b/clang/test/CodeGen/X86/amx_avx512_api.c index fac41ea6c214f..cf3d5dbc81a70 100644 --- a/clang/test/CodeGen/X86/amx_avx512_api.c +++ b/clang/test/CodeGen/X86/amx_avx512_api.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64-unknown-unknown \ -// RUN: -target-feature +amx-avx512 -target-feature +avx10.2-512 \ +// RUN: -target-feature +amx-avx512 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Werror -pedantic | FileCheck %s --check-prefixes=CHECK #include diff --git a/clang/test/CodeGen/X86/amxavx512-builtins.c b/clang/test/CodeGen/X86/amxavx512-builtins.c index d60929994901a..dada53c2d6f83 100644 --- a/clang/test/CodeGen/X86/amxavx512-builtins.c +++ b/clang/test/CodeGen/X86/amxavx512-builtins.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +amx-tile -target-feature +amx-avx512 \ -// RUN: -target-feature +avx10.2-512 -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression -flax-vector-conversions=none | FileCheck %s +// RUN: -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression -flax-vector-conversions=none | FileCheck %s #include #include diff --git a/clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c b/clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c index 78405d63984f6..25559d6cbfe95 100644 --- a/clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2_512bf16-builtins.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2-512 -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2-512 -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2 -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2 -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2_512convert-builtins.c b/clang/test/CodeGen/X86/avx10_2_512convert-builtins.c index 3ac7c2cc8716f..7fbdcdc2d18c2 100644 --- a/clang/test/CodeGen/X86/avx10_2_512convert-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2_512convert-builtins.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c b/clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c index 4e467b36b2348..fa338253f58df 100644 --- a/clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2_512minmax-builtins.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2_512minmax-error.c b/clang/test/CodeGen/X86/avx10_2_512minmax-error.c index 2ee496d317a5a..ddc4d8df28ead 100644 --- a/clang/test/CodeGen/X86/avx10_2_512minmax-error.c +++ b/clang/test/CodeGen/X86/avx10_2_512minmax-error.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2 \ // RUN: -Wno-invalid-feature-combination -verify -fsyntax-only -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2 \ // RUN: -Wno-invalid-feature-combination -verify -fsyntax-only #include diff --git a/clang/test/CodeGen/X86/avx10_2_512ni-builtins.c b/clang/test/CodeGen/X86/avx10_2_512ni-builtins.c index d143188ee0f31..728c9f5652dd9 100644 --- a/clang/test/CodeGen/X86/avx10_2_512ni-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2_512ni-builtins.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2-512 -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i686 -target-feature +avx10.2-512 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i686 -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2_512satcvt-builtins.c b/clang/test/CodeGen/X86/avx10_2_512satcvt-builtins.c index 0a1c329144398..ac1b8cd88db0b 100755 --- a/clang/test/CodeGen/X86/avx10_2_512satcvt-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2_512satcvt-builtins.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-errors.c b/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-errors.c index 46d4764844072..2343016d7249b 100644 --- a/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-errors.c +++ b/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-errors.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386-unknown-unknown -target-feature +avx10.2-512 -Wall -Werror -verify +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386-unknown-unknown -target-feature +avx10.2 -Wall -Werror -verify #include #include @@ -49,4 +49,4 @@ __m512i test_mm512_mask_cvtts_roundps_epu32(__m512i W, __mmask8 U, __m512 A) { __m512i test_mm512_maskz_cvtts_roundps_epu32(__mmask8 U, __m512 A) { return _mm512_maskz_cvtts_roundps_epu32(U, A, 22); // expected-error {{invalid rounding argument}} -} \ No newline at end of file +} diff --git a/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64-error.c b/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64-error.c index 334edfb501e2f..f85d8f4d94a69 100755 --- a/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64-error.c +++ b/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64-error.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx10.2-512 -Wall -Werror -verify +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx10.2 -Wall -Werror -verify #include #include diff --git a/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64.c b/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64.c index 1aaa6544d1f9c..a5296820bc68b 100644 --- a/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64.c +++ b/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins-x64.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx10.2-512 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s #include #include diff --git a/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins.c b/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins.c index c1b6df3cb07f5..a5e8121bddc9a 100644 --- a/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2_512satcvtds-builtins.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2-512 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86 -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2-512 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X64 +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X86 +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK,X64 #include #include diff --git a/clang/test/CodeGen/X86/avx10_2bf16-builtins.c b/clang/test/CodeGen/X86/avx10_2bf16-builtins.c index 3cc9e1d4233b0..c7fea07421b56 100644 --- a/clang/test/CodeGen/X86/avx10_2bf16-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2bf16-builtins.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2-256 -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2-256 -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2 -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2 -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2convert-builtins.c b/clang/test/CodeGen/X86/avx10_2convert-builtins.c index 31dd0ecc381ef..025ab77b4bae6 100644 --- a/clang/test/CodeGen/X86/avx10_2convert-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2convert-builtins.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-256 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-256 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2minmax-builtins.c b/clang/test/CodeGen/X86/avx10_2minmax-builtins.c index 7dad153a15c37..97faaf1ef4e12 100644 --- a/clang/test/CodeGen/X86/avx10_2minmax-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2minmax-builtins.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-256 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-256 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wno-invalid-feature-combination -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2ni-builtins.c b/clang/test/CodeGen/X86/avx10_2ni-builtins.c index b4b12c9531942..a250d91ae5989 100644 --- a/clang/test/CodeGen/X86/avx10_2ni-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2ni-builtins.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i686 -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i686 -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2satcvt-builtins.c b/clang/test/CodeGen/X86/avx10_2satcvt-builtins.c index 7f30befefffe9..12b845cda44b2 100644 --- a/clang/test/CodeGen/X86/avx10_2satcvt-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2satcvt-builtins.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2-256 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64 -target-feature +avx10.2 \ // RUN: -Wno-invalid-feature-combination -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2-256 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=i386 -target-feature +avx10.2 \ // RUN: -Wno-invalid-feature-combination -emit-llvm -o - -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c index 070065228e5a5..bcfe43b1f34a6 100644 --- a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c +++ b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins-x64.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s #include #include diff --git a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c index 86e9df44c0669..a0e5cfdcd5ec6 100644 --- a/clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c +++ b/clang/test/CodeGen/X86/avx10_2satcvtds-builtins.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK -// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2-256 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=i386 -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK +// RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64 -target-feature +avx10.2 -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK #include #include diff --git a/clang/test/CodeGen/X86/avx512-error.c b/clang/test/CodeGen/X86/avx512-error.c index 645126916572c..e76d0d7a4551f 100644 --- a/clang/test/CodeGen/X86/avx512-error.c +++ b/clang/test/CodeGen/X86/avx512-error.c @@ -1,12 +1,9 @@ -// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512bw -target-feature -evex512 -emit-llvm -o /dev/null -verify=noevex // RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx512bw -emit-llvm -o /dev/null -verify -// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.1-256 -emit-llvm -o /dev/null -verify=noevex -// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.1-512 -emit-llvm -o /dev/null -verify +// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.1 -emit-llvm -o /dev/null -verify #include -// No error emitted whether we have "evex512" feature or not. -__attribute__((target("avx512bw,no-evex512"))) +__attribute__((target("avx512bw"))) __mmask64 k64_verify_1(__mmask64 a) { return _knot_mask64(a); // expected-no-diagnostics } @@ -15,19 +12,12 @@ __mmask64 k64_verify_2(__mmask64 a) { return _knot_mask64(a); // expected-no-diagnostic } -__attribute__((target("avx512bw,evex512"))) +__attribute__((target("avx512bw"))) __m512d zmm_verify_ok(__m512d a) { - // No error emitted if we have "evex512" feature. return __builtin_ia32_sqrtpd512(a, _MM_FROUND_CUR_DIRECTION); // expected-no-diagnostic } __m512d zmm_error(__m512d a) { // CHECK-LABEL: @test_mm512_sqrt_pd - return __builtin_ia32_sqrtpd512(a, _MM_FROUND_CUR_DIRECTION); // noevex-error {{'__builtin_ia32_sqrtpd512' needs target feature avx512f,evex512}} + return __builtin_ia32_sqrtpd512(a, _MM_FROUND_CUR_DIRECTION); // noevex-error {{'__builtin_ia32_sqrtpd512' needs target feature avx512f}} } -#if defined(__AVX10_1__) && !defined(__AVX10_1_512__) -// noevex-warning@*:* {{invalid feature combination: +avx512bw +avx10.1-256; will be promoted to avx10.1-512}} -// noevex-warning@*:* {{invalid feature combination: +avx512bw +avx10.1-256; will be promoted to avx10.1-512}} -// noevex-warning@*:* {{invalid feature combination: +avx512bw +avx10.1-256; will be promoted to avx10.1-512}} -// noevex-warning@*:* {{invalid feature combination: +avx512bw +avx10.1-256; will be promoted to avx10.1-512}} -#endif diff --git a/clang/test/CodeGen/X86/avx512copy-builtins.c b/clang/test/CodeGen/X86/avx512copy-builtins.c index 06f7507bde53e..cf27e3073fdac 100644 --- a/clang/test/CodeGen/X86/avx512copy-builtins.c +++ b/clang/test/CodeGen/X86/avx512copy-builtins.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.2-512 \ +// RUN: %clang_cc1 %s -flax-vector-conversions=none -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.2 \ // RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avx512vlbw-builtins.c b/clang/test/CodeGen/X86/avx512vlbw-builtins.c index 4527c9175dcaa..5f78a6a6bddd8 100644 --- a/clang/test/CodeGen/X86/avx512vlbw-builtins.c +++ b/clang/test/CodeGen/X86/avx512vlbw-builtins.c @@ -1,16 +1,16 @@ // RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512bw -target-feature +avx512vl -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s // RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512bw -target-feature +avx512vl -fno-signed-char -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s -// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx10.1-512 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s +// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx10.1 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s // RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512bw -target-feature +avx512vl -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s // RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512bw -target-feature +avx512vl -fno-signed-char -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s -// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx10.1-512 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s +// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx10.1 -emit-llvm -o - -Wall -Werror -Wsign-conversion | FileCheck %s // RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512bw -target-feature +avx512vl -emit-llvm -o - -Wall -Werror -Wsign-conversion -fexperimental-new-constant-interpreter | FileCheck %s // RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512bw -target-feature +avx512vl -fno-signed-char -emit-llvm -o - -Wall -Werror -Wsign-conversion -fexperimental-new-constant-interpreter | FileCheck %s -// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx10.1-512 -emit-llvm -o - -Wall -Werror -Wsign-conversion -fexperimental-new-constant-interpreter | FileCheck %s +// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx10.1 -emit-llvm -o - -Wall -Werror -Wsign-conversion -fexperimental-new-constant-interpreter | FileCheck %s // RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512bw -target-feature +avx512vl -emit-llvm -o - -Wall -Werror -Wsign-conversion -fexperimental-new-constant-interpreter | FileCheck %s // RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx512bw -target-feature +avx512vl -fno-signed-char -emit-llvm -o - -Wall -Werror -Wsign-conversion -fexperimental-new-constant-interpreter | FileCheck %s -// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx10.1-512 -emit-llvm -o - -Wall -Werror -Wsign-conversion -fexperimental-new-constant-interpreter | FileCheck %s +// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin -target-feature +avx10.1 -emit-llvm -o - -Wall -Werror -Wsign-conversion -fexperimental-new-constant-interpreter | FileCheck %s #include #include "builtin_test_helpers.h" diff --git a/clang/test/CodeGen/X86/avxvnniint16-builtins.c b/clang/test/CodeGen/X86/avxvnniint16-builtins.c index c25367bdd8502..941da9aa223b5 100644 --- a/clang/test/CodeGen/X86/avxvnniint16-builtins.c +++ b/clang/test/CodeGen/X86/avxvnniint16-builtins.c @@ -1,11 +1,11 @@ // RUN: %clang_cc1 -x c %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avxvnniint16 -emit-llvm -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 -x c %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avxvnniint16 -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -x c %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -x c %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -x c %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -x c %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 -x c++ %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avxvnniint16 -emit-llvm -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 -x c++ %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avxvnniint16 -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -x c++ %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -x c++ %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -x c++ %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -x c++ %s -ffreestanding -triple=i386-unknown-unknown -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/avxvnniint8-builtins.c b/clang/test/CodeGen/X86/avxvnniint8-builtins.c index f808dee40519c..dd4a4483abaab 100644 --- a/clang/test/CodeGen/X86/avxvnniint8-builtins.c +++ b/clang/test/CodeGen/X86/avxvnniint8-builtins.c @@ -1,11 +1,11 @@ // RUN: %clang_cc1 -x c -ffreestanding %s -triple=x86_64- -target-feature +avxvnniint8 -emit-llvm -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 -x c -ffreestanding %s -triple=i386- -target-feature +avxvnniint8 -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -x c -ffreestanding %s -triple=x86_64- -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -x c -ffreestanding %s -triple=i386- -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -x c -ffreestanding %s -triple=x86_64- -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -x c -ffreestanding %s -triple=i386- -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 -x c++ -ffreestanding %s -triple=x86_64- -target-feature +avxvnniint8 -emit-llvm -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 -x c++ -ffreestanding %s -triple=i386- -target-feature +avxvnniint8 -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -x c++ -ffreestanding %s -triple=x86_64- -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s -// RUN: %clang_cc1 -x c++ -ffreestanding %s -triple=i386- -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -x c++ -ffreestanding %s -triple=x86_64- -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -x c++ -ffreestanding %s -triple=i386- -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/movrs-avx10.2-512-builtins-error-32.c b/clang/test/CodeGen/X86/movrs-avx10.2-512-builtins-error-32.c index a4d887f0be416..8d54eb1da08d9 100644 --- a/clang/test/CodeGen/X86/movrs-avx10.2-512-builtins-error-32.c +++ b/clang/test/CodeGen/X86/movrs-avx10.2-512-builtins-error-32.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -ffreestanding %s -Wno-implicit-function-declaration -triple=i386-- -target-feature +movrs -target-feature +avx10.2-512 -verify +// RUN: %clang_cc1 -ffreestanding %s -Wno-implicit-function-declaration -triple=i386-- -target-feature +movrs -target-feature +avx10.2 -verify #include __m512i test_mm512_loadrs_epi8(const __m512i * __A) { diff --git a/clang/test/CodeGen/X86/movrs-avx10.2-512-builtins.c b/clang/test/CodeGen/X86/movrs-avx10.2-512-builtins.c index 997d6dbc53a8b..4b75c6049f2f7 100644 --- a/clang/test/CodeGen/X86/movrs-avx10.2-512-builtins.c +++ b/clang/test/CodeGen/X86/movrs-avx10.2-512-builtins.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-- -target-feature +movrs -target-feature +avx10.2-512 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-- -target-feature +movrs -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/movrs-avx10.2-builtins-error-32.c b/clang/test/CodeGen/X86/movrs-avx10.2-builtins-error-32.c index 2a7204e39b830..c11e28b2d3850 100644 --- a/clang/test/CodeGen/X86/movrs-avx10.2-builtins-error-32.c +++ b/clang/test/CodeGen/X86/movrs-avx10.2-builtins-error-32.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -ffreestanding %s -Wno-implicit-function-declaration -triple=i386-unknown-unknown -target-feature +movrs -target-feature +avx10.2-256 -verify +// RUN: %clang_cc1 -ffreestanding %s -Wno-implicit-function-declaration -triple=i386-unknown-unknown -target-feature +movrs -target-feature +avx10.2 -verify #include __m128i test_mm_loadrs_epi8(const __m128i * __A) { diff --git a/clang/test/CodeGen/X86/movrs-avx10.2-builtins.c b/clang/test/CodeGen/X86/movrs-avx10.2-builtins.c index 2011b2a862473..05524ab1f9420 100644 --- a/clang/test/CodeGen/X86/movrs-avx10.2-builtins.c +++ b/clang/test/CodeGen/X86/movrs-avx10.2-builtins.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-- -target-feature +movrs -target-feature +avx10.2-256 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-- -target-feature +movrs -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s #include diff --git a/clang/test/CodeGen/X86/sm4-evex-builtins.c b/clang/test/CodeGen/X86/sm4-evex-builtins.c index 0e54bd008d4fb..a819f252e513d 100644 --- a/clang/test/CodeGen/X86/sm4-evex-builtins.c +++ b/clang/test/CodeGen/X86/sm4-evex-builtins.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-- -target-feature +sm4 \ -// RUN: -target-feature +avx10.2-512 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s // RUN: %clang_cc1 %s -ffreestanding -triple=i386-- -target-feature +sm4 \ -// RUN: -target-feature +avx10.2-512 -emit-llvm -o - -Wall -Werror | FileCheck %s +// RUN: -target-feature +avx10.2 -emit-llvm -o - -Wall -Werror | FileCheck %s #include #include diff --git a/clang/test/CodeGen/attr-cpuspecific.c b/clang/test/CodeGen/attr-cpuspecific.c index 6eb2fb2758738..44f51887be389 100644 --- a/clang/test/CodeGen/attr-cpuspecific.c +++ b/clang/test/CodeGen/attr-cpuspecific.c @@ -360,7 +360,7 @@ void OrderDispatchUsageSpecific(void) {} // CHECK: attributes #[[S]] = {{.*}}"target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" // CHECK-SAME: "tune-cpu"="ivybridge" -// CHECK: attributes #[[K]] = {{.*}}"target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512f,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+evex512,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" +// CHECK: attributes #[[K]] = {{.*}}"target-features"="+adx,+aes,+avx,+avx2,+avx512cd,+avx512f,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt" // CHECK-SAME: "tune-cpu"="knl" // CHECK: attributes #[[O]] = {{.*}}"target-features"="+cmov,+cx16,+cx8,+fxsr,+mmx,+movbe,+sahf,+sse,+sse2,+sse3,+ssse3,+x87" // CHECK-SAME: "tune-cpu"="atom" diff --git a/clang/test/CodeGen/attr-target-x86.c b/clang/test/CodeGen/attr-target-x86.c index e5067c1c3b075..d89e386061702 100644 --- a/clang/test/CodeGen/attr-target-x86.c +++ b/clang/test/CodeGen/attr-target-x86.c @@ -16,8 +16,7 @@ // CHECK: define {{.*}}@f_x86_64_v2({{.*}} [[f_x86_64_v2:#[0-9]+]] // CHECK: define {{.*}}@f_x86_64_v3({{.*}} [[f_x86_64_v3:#[0-9]+]] // CHECK: define {{.*}}@f_x86_64_v4({{.*}} [[f_x86_64_v4:#[0-9]+]] -// CHECK: define {{.*}}@f_avx10_1_256{{.*}} [[f_avx10_1_256:#[0-9]+]] -// CHECK: define {{.*}}@f_avx10_1_512{{.*}} [[f_avx10_1_512:#[0-9]+]] +// CHECK: define {{.*}}@f_avx10_1{{.*}} [[f_avx10_1:#[0-9]+]] // CHECK: define {{.*}}@f_prefer_256_bit({{.*}} [[f_prefer_256_bit:#[0-9]+]] // CHECK: define {{.*}}@f_no_prefer_256_bit({{.*}} [[f_no_prefer_256_bit:#[0-9]+]] @@ -34,7 +33,7 @@ __attribute__((target("fpmath=387"))) void f_fpmath_387(void) {} // CHECK-NOT: tune-cpu -// CHECK: [[f_no_sse2]] = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-amx-avx512,-avx,-avx10.1-256,-avx10.1-512,-avx10.2-256,-avx10.2-512,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sm4,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686" +// CHECK: [[f_no_sse2]] = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-amx-avx512,-avx,-avx10.1,-avx10.1-512,-avx10.2,-avx10.2-512,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sm4,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686" __attribute__((target("no-sse2"))) void f_no_sse2(void) {} @@ -42,7 +41,7 @@ void f_no_sse2(void) {} __attribute__((target("sse4"))) void f_sse4(void) {} -// CHECK: [[f_no_sse4]] = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-amx-avx512,-avx,-avx10.1-256,-avx10.1-512,-avx10.2-256,-avx10.2-512,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sm4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686" +// CHECK: [[f_no_sse4]] = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-amx-avx512,-avx,-avx10.1,-avx10.1-512,-avx10.2,-avx10.2-512,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512f,-avx512fp16,-avx512ifma,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint16,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sm4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686" __attribute__((target("no-sse4"))) void f_no_sse4(void) {} @@ -94,17 +93,13 @@ __attribute__((target("arch=x86-64-v3"))) void f_x86_64_v3(void) {} // CHECK: [[f_x86_64_v4]] = {{.*}}"target-cpu"="x86-64-v4" -// CHECK-SAME: "target-features"="+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+evex512,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" +// CHECK-SAME: "target-features"="+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" __attribute__((target("arch=x86-64-v4"))) void f_x86_64_v4(void) {} -// CHECK: [[f_avx10_1_256]] = {{.*}}"target-cpu"="i686" "target-features"="+avx,+avx10.1-256,+avx2,+avx512bf16,+avx512bitalg,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512fp16,+avx512ifma,+avx512vbmi,+avx512vbmi2,+avx512vl,+avx512vnni,+avx512vpopcntdq,+cmov,+crc32,+cx8,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,-amx-avx512,-avx10.1-512,-avx10.2-512,-evex512" -__attribute__((target("avx10.1-256"))) -void f_avx10_1_256(void) {} - -// CHECK: [[f_avx10_1_512]] = {{.*}}"target-cpu"="i686" "target-features"="+avx,+avx10.1-256,+avx10.1-512,+avx2,+avx512bf16,+avx512bitalg,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512fp16,+avx512ifma,+avx512vbmi,+avx512vbmi2,+avx512vl,+avx512vnni,+avx512vpopcntdq,+cmov,+crc32,+cx8,+evex512,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" -__attribute__((target("avx10.1-512"))) -void f_avx10_1_512(void) {} +// CHECK: [[f_avx10_1]] = {{.*}}"target-cpu"="i686" "target-features"="+avx,+avx10.1,+avx2,+avx512bf16,+avx512bitalg,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512fp16,+avx512ifma,+avx512vbmi,+avx512vbmi2,+avx512vl,+avx512vnni,+avx512vpopcntdq,+cmov,+crc32,+cx8,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" +__attribute__((target("avx10.1"))) +void f_avx10_1(void) {} // CHECK: [[f_prefer_256_bit]] = {{.*}}"target-features"="{{.*}}+prefer-256-bit __attribute__((target("prefer-256-bit"))) diff --git a/clang/test/CodeGen/regcall2.c b/clang/test/CodeGen/regcall2.c index 42619369677b2..d89d800270957 100644 --- a/clang/test/CodeGen/regcall2.c +++ b/clang/test/CodeGen/regcall2.c @@ -21,8 +21,8 @@ double __regcall bar(__sVector a) { // FIXME: Do we need to change for Windows? // Win: define dso_local x86_regcallcc void @__regcall3__foo(ptr dead_on_unwind noalias writable sret(%struct.__sVector) align 64 %agg.result, i32 noundef %a) #0 // Win: define dso_local x86_regcallcc double @__regcall3__bar(ptr dead_on_return noundef %a) #0 -// Win: attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+avx,+avx2,+avx512f,+avx512vl,+crc32,+cx8,+evex512,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" } +// Win: attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="0" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+avx,+avx2,+avx512f,+avx512vl,+crc32,+cx8,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" } // Lin: define dso_local x86_regcallcc %struct.__sVector @__regcall3__foo(i32 noundef %a) #0 // Lin: define dso_local x86_regcallcc double @__regcall3__bar([4 x <8 x double>] %a.coerce0, [4 x <16 x float>] %a.coerce1) #0 -// Lin: attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="512" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+avx,+avx2,+avx512f,+avx512vl,+crc32,+cx8,+evex512,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" } +// Lin: attributes #0 = { noinline nounwind optnone "min-legal-vector-width"="512" "no-builtins" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+avx,+avx2,+avx512f,+avx512vl,+crc32,+cx8,+f16c,+fma,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" } diff --git a/clang/test/CodeGen/target-avx-abi-diag.c b/clang/test/CodeGen/target-avx-abi-diag.c index 116959d60788f..b015163e9e663 100644 --- a/clang/test/CodeGen/target-avx-abi-diag.c +++ b/clang/test/CodeGen/target-avx-abi-diag.c @@ -1,10 +1,7 @@ // RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -verify=no256,no512 -o - -S // RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -target-feature +avx -verify=no512 -o - -S // RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -target-feature +avx512f -verify=both -o - -S -// RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -target-feature +avx512f -target-feature +evex512 -verify=both -o - -S -// RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -target-feature +avx512f -target-feature -evex512 -verify=avx512-256 -DNOEVEX512 -o - -S -// RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -target-feature +avx10.1-512 -verify=both -o - -S -// RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -target-feature +avx10.1-256 -verify=avx512-256 -o - -S +// RUN: %clang_cc1 %s -triple=x86_64-linux-gnu -target-feature +avx10.1 -verify=both -o - -S // REQUIRES: x86-registered-target // both-no-diagnostics @@ -14,7 +11,6 @@ typedef short avx256Type __attribute__((vector_size(32))); __attribute__((target("avx"))) void takesAvx256(avx256Type t); __attribute__((target("avx512f"))) void takesAvx512(avx512fType t); -__attribute__((target("avx512f,evex512"))) void takesAvx512_2(avx512fType t); void takesAvx256_no_target(avx256Type t); void takesAvx512_no_target(avx512fType t); @@ -27,11 +23,9 @@ void call_warn(void) { takesAvx256_no_target(t1); // no256-warning {{AVX vector argument of type 'avx256Type' (vector of 16 'short' values) without 'avx' enabled changes the ABI}} avx512fType t2; - // avx512-256-error@+1 {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'evex512' enabled changes the ABI}} takesAvx512_no_target(t2); // no512-warning {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'avx512f' enabled changes the ABI}} variadic(1, t1); // no256-warning {{AVX vector argument of type 'avx256Type' (vector of 16 'short' values) without 'avx' enabled changes the ABI}} - // avx512-256-error@+1 {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'evex512' enabled changes the ABI}} variadic(3, t2); // no512-warning {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'avx512f' enabled changes the ABI}} } @@ -40,25 +34,9 @@ void call_errors(void) { avx256Type t1; takesAvx256(t1); // no256-error {{AVX vector argument of type 'avx256Type' (vector of 16 'short' values) without 'avx' enabled changes the ABI}} avx512fType t2; - // avx512-256-error@+1 {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'evex512' enabled changes the ABI}} takesAvx512(t2); // no512-error {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'avx512f' enabled changes the ABI}} variadic_err(1, t1); // no256-error {{AVX vector argument of type 'avx256Type' (vector of 16 'short' values) without 'avx' enabled changes the ABI}} - // avx512-256-error@+1 {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'evex512' enabled changes the ABI}} - variadic_err(3, t2); // no512-error {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'avx512f' enabled changes the ABI}} -} - -// Check that these errors are treated as non-fatal, so we can report them for -// all functions, not just the first. -void call_errors_2(void) { - avx256Type t1; - takesAvx256(t1); // no256-error {{AVX vector argument of type 'avx256Type' (vector of 16 'short' values) without 'avx' enabled changes the ABI}} - avx512fType t2; - // avx512-256-error@+1 {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'evex512' enabled changes the ABI}} - takesAvx512(t2); // no512-error {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'avx512f' enabled changes the ABI}} - - variadic_err(1, t1); // no256-error {{AVX vector argument of type 'avx256Type' (vector of 16 'short' values) without 'avx' enabled changes the ABI}} - // avx512-256-error@+1 {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'evex512' enabled changes the ABI}} variadic_err(3, t2); // no512-error {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'avx512f' enabled changes the ABI}} } @@ -67,37 +45,7 @@ __attribute__((target("avx"))) void call_avx256_ok(void) { takesAvx256(t); } -// Option -mno-evex512 affects target attributes. To retain the 512-bit capability, an explict "evex512" must be added together. -__attribute__((target("avx512f,evex512"))) void call_avx512_ok1(void) { - avx512fType t; - takesAvx512_2(t); -} - __attribute__((target("avx512f"))) void call_avx512_ok2(void) { avx512fType t; -#if defined(NOEVEX512) -// avx512-256-error@+2 {{AVX vector argument of type 'avx512fType' (vector of 32 'short' values) without 'evex512' enabled changes the ABI}} -#endif takesAvx512(t); } -#if defined(__AVX10_1__) -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -// avx512-256-warning@*:* {{invalid feature combination: +avx512f +avx10.1-256; will be promoted to avx10.1-512}} -#endif diff --git a/clang/test/CodeGen/target-builtin-noerror.c b/clang/test/CodeGen/target-builtin-noerror.c index 5cf53b2d2fc8f..120f1a5f981e1 100644 --- a/clang/test/CodeGen/target-builtin-noerror.c +++ b/clang/test/CodeGen/target-builtin-noerror.c @@ -141,10 +141,8 @@ void verifyfeaturestrings(void) { (void)__builtin_cpu_supports("sm4"); (void)__builtin_cpu_supports("apxf"); (void)__builtin_cpu_supports("usermsr"); - (void)__builtin_cpu_supports("avx10.1-256"); - (void)__builtin_cpu_supports("avx10.1-512"); - (void)__builtin_cpu_supports("avx10.2-256"); - (void)__builtin_cpu_supports("avx10.2-512"); + (void)__builtin_cpu_supports("avx10.1"); + (void)__builtin_cpu_supports("avx10.2"); (void)__builtin_cpu_supports("movrs"); } diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c index 7ec453108b264..3717c449d6601 100644 --- a/clang/test/Driver/x86-target-features.c +++ b/clang/test/Driver/x86-target-features.c @@ -390,41 +390,15 @@ // AVXVNNIINT16: "-target-feature" "+avxvnniint16" // NO-AVXVNNIINT16: "-target-feature" "-avxvnniint16" -// RUN: %clang --target=i386 -mevex512 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=EVEX512,WARN-EVEX512 %s -// RUN: %clang --target=i386 -mno-evex512 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=NO-EVEX512,WARN-EVEX512 %s -// RUN: %clang --target=i386 -march=i386 -mavx10.1 %s -### -o %t.o 2>&1 -Werror | FileCheck -check-prefix=AVX10_1_512 %s -// RUN: %clang --target=i386 -march=i386 -mno-avx10.1 %s -### -o %t.o 2>&1 -Werror | FileCheck -check-prefix=NO-AVX10_1 %s -// RUN: %clang --target=i386 -mavx10.1-256 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=AVX10_1_256,WARN-AVX10-256 %s -// RUN: %clang --target=i386 -mavx10.1-512 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=AVX10_1_512,WARN-AVX10-512 %s -// RUN: %clang --target=i386 -mavx10.1-256 -mavx10.1-512 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=AVX10_1_512 %s -// RUN: %clang --target=i386 -mavx10.1-512 -mavx10.1-256 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=AVX10_1_256 %s -// RUN: not %clang --target=i386 -march=i386 -mavx10.1-128 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=BAD-AVX10 %s -// RUN: not %clang --target=i386 -march=i386 -mavx10.a-256 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=BAD-AVX10 %s -// RUN: not %clang --target=i386 -march=i386 -mavx10.1024-512 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=BAD-AVX10 %s -// RUN: %clang --target=i386 -march=i386 -mavx10.1-256 -mavx512f %s -### -o %t.o 2>&1 | FileCheck -check-prefix=AVX10-AVX512 %s -// RUN: %clang --target=i386 -march=i386 -mavx10.1-256 -mno-avx512f %s -### -o %t.o 2>&1 | FileCheck -check-prefix=AVX10-AVX512 %s -// RUN: %clang --target=i386 -march=i386 -mavx10.1-256 -mevex512 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=AVX10-EVEX512,WARN-EVEX512 %s -// RUN: %clang --target=i386 -march=i386 -mavx10.1-256 -mno-evex512 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=AVX10-EVEX512,WARN-EVEX512 %s -// RUN: %clang --target=i386 -mavx10.2 %s -### -o %t.o 2>&1 -Werror | FileCheck -check-prefix=AVX10_2_512 %s +// RUN: %clang --target=i386 -mavx10.1 %s -### -o %t.o 2>&1 -Werror | FileCheck -check-prefix=AVX10_1 %s +// RUN: %clang --target=i386 -mno-avx10.1 %s -### -o %t.o 2>&1 -Werror | FileCheck -check-prefix=NO-AVX10_1 %s +// AVX10_1: "-target-feature" "+avx10.1" +// NO-AVX10_1: "-target-feature" "-avx10.1" + +// RUN: %clang --target=i386 -mavx10.2 %s -### -o %t.o 2>&1 -Werror | FileCheck -check-prefix=AVX10_2 %s // RUN: %clang --target=i386 -mno-avx10.2 %s -### -o %t.o 2>&1 -Werror | FileCheck -check-prefix=NO-AVX10_2 %s -// RUN: %clang --target=i386 -mavx10.2-256 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=AVX10_2_256,WARN-AVX10-256 %s -// RUN: %clang --target=i386 -mavx10.2-512 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=AVX10_2_512,WARN-AVX10-512 %s -// RUN: %clang --target=i386 -mavx10.2-256 -mavx10.1-512 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=AVX10_2_256,AVX10_1_512 %s -// RUN: %clang --target=i386 -mavx10.2-512 -mavx10.1-256 %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=AVX10_2_512,AVX10_1_256 %s -// WARN-EVEX512: warning: argument '{{.*}}evex512' is deprecated, no alternative argument provided because AVX10/256 is not supported and will be removed [-Wdeprecated] -// WARN-AVX10-256: warning: argument 'avx10.{{.*}}-256' is deprecated, no alternative argument provided because AVX10/256 is not supported and will be removed [-Wdeprecated] -// WARN-AVX10-512: warning: argument 'avx10.{{.*}}-512' is deprecated, use 'avx10.{{.*}}' instead [-Wdeprecated] -// EVEX512: "-target-feature" "+evex512" -// NO-EVEX512: "-target-feature" "-evex512" -// NO-AVX10_1: "-target-feature" "-avx10.1-256" -// NO-AVX10_2: "-target-feature" "-avx10.2-256" -// AVX10_2_256: "-target-feature" "+avx10.2-256" -// AVX10_2_512: "-target-feature" "+avx10.2-512" -// AVX10_1_256: "-target-feature" "+avx10.1-256" -// AVX10_1_512: "-target-feature" "+avx10.1-512" -// BAD-AVX10: error: unknown argument{{:?}} '-mavx10.{{.*}}' -// AVX10-AVX512: "-target-feature" "+avx10.1-256" "-target-feature" "{{.}}avx512f" -// AVX10-EVEX512: "-target-feature" "+avx10.1-256" "-target-feature" "{{.}}evex512" +// AVX10_2: "-target-feature" "+avx10.2" +// NO-AVX10_2: "-target-feature" "-avx10.2" // RUN: %clang --target=i386 -musermsr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=USERMSR %s // RUN: %clang --target=i386 -mno-usermsr %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-USERMSR %s diff --git a/clang/test/Preprocessor/predefined-arch-macros-x86.c b/clang/test/Preprocessor/predefined-arch-macros-x86.c index a727e51bdd45f..37b7c612b4919 100644 --- a/clang/test/Preprocessor/predefined-arch-macros-x86.c +++ b/clang/test/Preprocessor/predefined-arch-macros-x86.c @@ -52,4 +52,3 @@ // X86_64_V4-NEXT: #define __AVX512F__ 1 // X86_64_V4-NEXT: #define __AVX512VL__ 1 // X86_64_V4-NOT: #define __AVX512{{.*}} -// X86_64_V4: #define __EVEX512__ 1 diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c index 2ea2d511f5e4e..ecddf130a5c51 100644 --- a/clang/test/Preprocessor/predefined-arch-macros.c +++ b/clang/test/Preprocessor/predefined-arch-macros.c @@ -795,8 +795,6 @@ // CHECK_KNL_M32: #define __AVX__ 1 // CHECK_KNL_M32: #define __BMI2__ 1 // CHECK_KNL_M32: #define __BMI__ 1 -// CHECK_KNL_M32-NOT: #define __EVEX256__ 1 -// CHECK_KNL_M32: #define __EVEX512__ 1 // CHECK_KNL_M32: #define __F16C__ 1 // CHECK_KNL_M32: #define __FMA__ 1 // CHECK_KNL_M32: #define __LZCNT__ 1 @@ -831,8 +829,6 @@ // CHECK_KNL_M64: #define __AVX__ 1 // CHECK_KNL_M64: #define __BMI2__ 1 // CHECK_KNL_M64: #define __BMI__ 1 -// CHECK_KNL_M64-NOT: #define __EVEX256__ 1 -// CHECK_KNL_M64: #define __EVEX512__ 1 // CHECK_KNL_M64: #define __F16C__ 1 // CHECK_KNL_M64: #define __FMA__ 1 // CHECK_KNL_M64: #define __LZCNT__ 1 @@ -871,8 +867,6 @@ // CHECK_KNM_M32: #define __AVX__ 1 // CHECK_KNM_M32: #define __BMI2__ 1 // CHECK_KNM_M32: #define __BMI__ 1 -// CHECK_KNM_M32-NOT: #define __EVEX256__ 1 -// CHECK_KNM_M32: #define __EVEX512__ 1 // CHECK_KNM_M32: #define __F16C__ 1 // CHECK_KNM_M32: #define __FMA__ 1 // CHECK_KNM_M32: #define __LZCNT__ 1 @@ -905,8 +899,6 @@ // CHECK_KNM_M64: #define __AVX__ 1 // CHECK_KNM_M64: #define __BMI2__ 1 // CHECK_KNM_M64: #define __BMI__ 1 -// CHECK_KNM_M64-NOT: #define __EVEX256__ 1 -// CHECK_KNM_M64: #define __EVEX512__ 1 // CHECK_KNM_M64: #define __F16C__ 1 // CHECK_KNM_M64: #define __FMA__ 1 // CHECK_KNM_M64: #define __LZCNT__ 1 @@ -946,8 +938,6 @@ // CHECK_SKX_M32: #define __BMI__ 1 // CHECK_SKX_M32: #define __CLFLUSHOPT__ 1 // CHECK_SKX_M32: #define __CLWB__ 1 -// CHECK_SKX_M32: #define __EVEX256__ 1 -// CHECK_SKX_M32: #define __EVEX512__ 1 // CHECK_SKX_M32: #define __F16C__ 1 // CHECK_SKX_M32: #define __FMA__ 1 // CHECK_SKX_M32: #define __INVPCID__ 1 @@ -993,8 +983,6 @@ // CHECK_SKX_M64: #define __BMI__ 1 // CHECK_SKX_M64: #define __CLFLUSHOPT__ 1 // CHECK_SKX_M64: #define __CLWB__ 1 -// CHECK_SKX_M64: #define __EVEX256__ 1 -// CHECK_SKX_M64: #define __EVEX512__ 1 // CHECK_SKX_M64: #define __F16C__ 1 // CHECK_SKX_M64: #define __FMA__ 1 // CHECK_SKX_M64: #define __INVPCID__ 1 @@ -1044,8 +1032,6 @@ // CHECK_CLX_M32: #define __BMI__ 1 // CHECK_CLX_M32: #define __CLFLUSHOPT__ 1 // CHECK_CLX_M32: #define __CLWB__ 1 -// CHECK_CLX_M32: #define __EVEX256__ 1 -// CHECK_CLX_M32: #define __EVEX512__ 1 // CHECK_CLX_M32: #define __F16C__ 1 // CHECK_CLX_M32: #define __FMA__ 1 // CHECK_CLX_M32: #define __INVPCID__ 1 @@ -1092,8 +1078,6 @@ // CHECK_CLX_M64: #define __BMI__ 1 // CHECK_CLX_M64: #define __CLFLUSHOPT__ 1 // CHECK_CLX_M64: #define __CLWB__ 1 -// CHECK_CLX_M64: #define __EVEX256__ 1 -// CHECK_CLX_M64: #define __EVEX512__ 1 // CHECK_CLX_M64: #define __F16C__ 1 // CHECK_CLX_M64: #define __FMA__ 1 // CHECK_CLX_M64: #define __INVPCID__ 1 @@ -1144,8 +1128,6 @@ // CHECK_CPX_M32: #define __BMI__ 1 // CHECK_CPX_M32: #define __CLFLUSHOPT__ 1 // CHECK_CPX_M32: #define __CLWB__ 1 -// CHECK_CPX_M32: #define __EVEX256__ 1 -// CHECK_CPX_M32: #define __EVEX512__ 1 // CHECK_CPX_M32: #define __F16C__ 1 // CHECK_CPX_M32: #define __FMA__ 1 // CHECK_CPX_M32: #define __INVPCID__ 1 @@ -1193,8 +1175,6 @@ // CHECK_CPX_M64: #define __BMI__ 1 // CHECK_CPX_M64: #define __CLFLUSHOPT__ 1 // CHECK_CPX_M64: #define __CLWB__ 1 -// CHECK_CPX_M64: #define __EVEX256__ 1 -// CHECK_CPX_M64: #define __EVEX512__ 1 // CHECK_CPX_M64: #define __F16C__ 1 // CHECK_CPX_M64: #define __FMA__ 1 // CHECK_CPX_M64: #define __INVPCID__ 1 @@ -1245,8 +1225,6 @@ // CHECK_CNL_M32: #define __BMI__ 1 // CHECK_CNL_M32: #define __CLFLUSHOPT__ 1 // CHECK_CNL_M32-NOT: #define __CLWB__ 1 -// CHECK_CNL_M32: #define __EVEX256__ 1 -// CHECK_CNL_M32: #define __EVEX512__ 1 // CHECK_CNL_M32: #define __F16C__ 1 // CHECK_CNL_M32: #define __FMA__ 1 // CHECK_CNL_M32: #define __INVPCID__ 1 @@ -1295,8 +1273,6 @@ // CHECK_CNL_M64: #define __BMI__ 1 // CHECK_CNL_M64: #define __CLFLUSHOPT__ 1 // CHECK_CNL_M64-NOT: #define __CLWB__ 1 -// CHECK_CNL_M64: #define __EVEX256__ 1 -// CHECK_CNL_M64: #define __EVEX512__ 1 // CHECK_CNL_M64: #define __F16C__ 1 // CHECK_CNL_M64: #define __FMA__ 1 // CHECK_CNL_M64: #define __INVPCID__ 1 @@ -1353,8 +1329,6 @@ // CHECK_ICL_M32: #define __BMI__ 1 // CHECK_ICL_M32: #define __CLFLUSHOPT__ 1 // CHECK_ICL_M32-NOT: #define __CLWB__ 1 -// CHECK_ICL_M32: #define __EVEX256__ 1 -// CHECK_ICL_M32: #define __EVEX512__ 1 // CHECK_ICL_M32: #define __F16C__ 1 // CHECK_ICL_M32: #define __FMA__ 1 // CHECK_ICL_M32: #define __GFNI__ 1 @@ -1416,8 +1390,6 @@ // CHECK_ICL_M64: #define __BMI__ 1 // CHECK_ICL_M64: #define __CLFLUSHOPT__ 1 // CHECK_ICL_M64-NOT: #define __CLWB__ 1 -// CHECK_ICL_M64: #define __EVEX256__ 1 -// CHECK_ICL_M64: #define __EVEX512__ 1 // CHECK_ICL_M64: #define __F16C__ 1 // CHECK_ICL_M64: #define __FMA__ 1 // CHECK_ICL_M64: #define __GFNI__ 1 @@ -1477,8 +1449,6 @@ // CHECK_ICX_M32: #define __BMI__ 1 // CHECK_ICX_M32: #define __CLFLUSHOPT__ 1 // CHECK_ICX_M32: #define __CLWB__ 1 -// CHECK_ICX_M32: #define __EVEX256__ 1 -// CHECK_ICX_M32: #define __EVEX512__ 1 // CHECK_ICX_M32: #define __F16C__ 1 // CHECK_ICX_M32: #define __FMA__ 1 // CHECK_ICX_M32: #define __GFNI__ 1 @@ -1537,8 +1507,6 @@ // CHECK_ICX_M64: #define __BMI__ 1 // CHECK_ICX_M64: #define __CLFLUSHOPT__ 1 // CHECK_ICX_M64: #define __CLWB__ 1 -// CHECK_ICX_M64: #define __EVEX256__ 1 -// CHECK_ICX_M64: #define __EVEX512__ 1 // CHECK_ICX_M64: #define __F16C__ 1 // CHECK_ICX_M64: #define __FMA__ 1 // CHECK_ICX_M64: #define __GFNI__ 1 @@ -1599,8 +1567,6 @@ // CHECK_TGL_M32: #define __BMI__ 1 // CHECK_TGL_M32: #define __CLFLUSHOPT__ 1 // CHECK_TGL_M32: #define __CLWB__ 1 -// CHECK_TGL_M32: #define __EVEX256__ 1 -// CHECK_TGL_M32: #define __EVEX512__ 1 // CHECK_TGL_M32: #define __F16C__ 1 // CHECK_TGL_M32: #define __FMA__ 1 // CHECK_TGL_M32: #define __GFNI__ 1 @@ -1663,8 +1629,6 @@ // CHECK_TGL_M64: #define __BMI__ 1 // CHECK_TGL_M64: #define __CLFLUSHOPT__ 1 // CHECK_TGL_M64: #define __CLWB__ 1 -// CHECK_TGL_M64: #define __EVEX256__ 1 -// CHECK_TGL_M64: #define __EVEX512__ 1 // CHECK_TGL_M64: #define __F16C__ 1 // CHECK_TGL_M64: #define __FMA__ 1 // CHECK_TGL_M64: #define __GFNI__ 1 @@ -1738,8 +1702,6 @@ // CHECK_SPR_M32: #define __CLFLUSHOPT__ 1 // CHECK_SPR_M32: #define __CLWB__ 1 // CHECK_SPR_M32: #define __ENQCMD__ 1 -// CHECK_SPR_M32: #define __EVEX256__ 1 -// CHECK_SPR_M32: #define __EVEX512__ 1 // CHECK_SPR_M32: #define __F16C__ 1 // CHECK_SPR_M32: #define __FMA__ 1 // CHECK_SPR_M32: #define __GFNI__ 1 @@ -1815,8 +1777,6 @@ // CHECK_SPR_M64: #define __CLFLUSHOPT__ 1 // CHECK_SPR_M64: #define __CLWB__ 1 // CHECK_SPR_M64: #define __ENQCMD__ 1 -// CHECK_SPR_M64: #define __EVEX256__ 1 -// CHECK_SPR_M64: #define __EVEX512__ 1 // CHECK_SPR_M64: #define __F16C__ 1 // CHECK_SPR_M64: #define __FMA__ 1 // CHECK_SPR_M64: #define __GFNI__ 1 @@ -1913,8 +1873,6 @@ // CHECK_DMR_M32: #define __CMPCCXADD__ 1 // CHECK_DMR_M32: #define __EGPR__ 1 // CHECK_GNR_M32: #define __ENQCMD__ 1 -// CHECK_GNR_M32: #define __EVEX256__ 1 -// CHECK_GNR_M32: #define __EVEX512__ 1 // CHECK_GNR_M32: #define __F16C__ 1 // CHECK_GNR_M32: #define __FMA__ 1 // CHECK_GNR_M32: #define __GFNI__ 1 @@ -2022,8 +1980,6 @@ // CHECK_DMR_M64: #define __CMPCCXADD__ 1 // CHECK_DMR_M64: #define __EGPR__ 1 // CHECK_GNR_M64: #define __ENQCMD__ 1 -// CHECK_GNR_M64: #define __EVEX256__ 1 -// CHECK_GNR_M64: #define __EVEX512__ 1 // CHECK_GNR_M64: #define __F16C__ 1 // CHECK_GNR_M64: #define __FMA__ 1 // CHECK_GNR_M64: #define __GFNI__ 1 @@ -3877,8 +3833,6 @@ // CHECK_ZNVER4_M32: #define __CLFLUSHOPT__ 1 // CHECK_ZNVER4_M32: #define __CLWB__ 1 // CHECK_ZNVER4_M32: #define __CLZERO__ 1 -// CHECK_ZNVER4_M32: #define __EVEX256__ 1 -// CHECK_ZNVER4_M32: #define __EVEX512__ 1 // CHECK_ZNVER4_M32: #define __F16C__ 1 // CHECK_ZNVER4_M32-NOT: #define __FMA4__ 1 // CHECK_ZNVER4_M32: #define __FMA__ 1 @@ -3941,8 +3895,6 @@ // CHECK_ZNVER4_M64: #define __CLFLUSHOPT__ 1 // CHECK_ZNVER4_M64: #define __CLWB__ 1 // CHECK_ZNVER4_M64: #define __CLZERO__ 1 -// CHECK_ZNVER4_M64: #define __EVEX256__ 1 -// CHECK_ZNVER4_M64: #define __EVEX512__ 1 // CHECK_ZNVER4_M64: #define __F16C__ 1 // CHECK_ZNVER4_M64-NOT: #define __FMA4__ 1 // CHECK_ZNVER4_M64: #define __FMA__ 1 diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c index 43bf177c689ca..5f17641878761 100644 --- a/clang/test/Preprocessor/x86_target_features.c +++ b/clang/test/Preprocessor/x86_target_features.c @@ -64,7 +64,6 @@ // AVX512F: #define __AVX2__ 1 // AVX512F: #define __AVX512F__ 1 // AVX512F: #define __AVX__ 1 -// AVX512F: #define __EVEX512__ 1 // AVX512F: #define __SSE2_MATH__ 1 // AVX512F: #define __SSE2__ 1 // AVX512F: #define __SSE3__ 1 @@ -80,7 +79,6 @@ // AVX512CD: #define __AVX512CD__ 1 // AVX512CD: #define __AVX512F__ 1 // AVX512CD: #define __AVX__ 1 -// AVX512CD: #define __EVEX512__ 1 // AVX512CD: #define __SSE2_MATH__ 1 // AVX512CD: #define __SSE2__ 1 // AVX512CD: #define __SSE3__ 1 @@ -96,7 +94,6 @@ // AVX512DQ: #define __AVX512DQ__ 1 // AVX512DQ: #define __AVX512F__ 1 // AVX512DQ: #define __AVX__ 1 -// AVX512DQ: #define __EVEX512__ 1 // AVX512DQ: #define __SSE2_MATH__ 1 // AVX512DQ: #define __SSE2__ 1 // AVX512DQ: #define __SSE3__ 1 @@ -112,7 +109,6 @@ // AVX512BW: #define __AVX512BW__ 1 // AVX512BW: #define __AVX512F__ 1 // AVX512BW: #define __AVX__ 1 -// AVX512BW: #define __EVEX512__ 1 // AVX512BW: #define __SSE2_MATH__ 1 // AVX512BW: #define __SSE2__ 1 // AVX512BW: #define __SSE3__ 1 @@ -128,8 +124,6 @@ // AVX512VL: #define __AVX512F__ 1 // AVX512VL: #define __AVX512VL__ 1 // AVX512VL: #define __AVX__ 1 -// AVX512VL: #define __EVEX256__ 1 -// AVX512VL: #define __EVEX512__ 1 // AVX512VL: #define __SSE2_MATH__ 1 // AVX512VL: #define __SSE2__ 1 // AVX512VL: #define __SSE3__ 1 @@ -145,7 +139,6 @@ // AVX512IFMA: #define __AVX512F__ 1 // AVX512IFMA: #define __AVX512IFMA__ 1 // AVX512IFMA: #define __AVX__ 1 -// AVX512IFMA: #define __EVEX512__ 1 // AVX512IFMA: #define __SSE2_MATH__ 1 // AVX512IFMA: #define __SSE2__ 1 // AVX512IFMA: #define __SSE3__ 1 @@ -162,7 +155,6 @@ // AVX512VBMI: #define __AVX512F__ 1 // AVX512VBMI: #define __AVX512VBMI__ 1 // AVX512VBMI: #define __AVX__ 1 -// AVX512VBMI: #define __EVEX512__ 1 // AVX512VBMI: #define __SSE2_MATH__ 1 // AVX512VBMI: #define __SSE2__ 1 // AVX512VBMI: #define __SSE3__ 1 @@ -179,7 +171,6 @@ // AVX512BITALG: #define __AVX512BW__ 1 // AVX512BITALG: #define __AVX512F__ 1 // AVX512BITALG: #define __AVX__ 1 -// AVX512BITALG: #define __EVEX512__ 1 // AVX512BITALG: #define __SSE2_MATH__ 1 // AVX512BITALG: #define __SSE2__ 1 // AVX512BITALG: #define __SSE3__ 1 @@ -194,7 +185,6 @@ // AVX512VBMINOAVX512BW-NOT: #define __AVX512BW__ 1 // AVX512VBMINOAVX512BW-NOT: #define __AVX512VBMI__ 1 -// AVX512VBMINOAVX512BW: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512vbmi2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512VBMI2 %s @@ -203,7 +193,6 @@ // AVX512VBMI2: #define __AVX512F__ 1 // AVX512VBMI2: #define __AVX512VBMI2__ 1 // AVX512VBMI2: #define __AVX__ 1 -// AVX512VBMI2: #define __EVEX512__ 1 // AVX512VBMI2: #define __SSE2_MATH__ 1 // AVX512VBMI2: #define __SSE2__ 1 // AVX512VBMI2: #define __SSE3__ 1 @@ -217,13 +206,11 @@ // AVX512VBMI2NOAVX512BW-NOT: #define __AVX512BW__ 1 // AVX512VBMI2NOAVX512BW-NOT: #define __AVX512VBMI2__ 1 -// AVX512VBMI2NOAVX512BW: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bitalg -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BITALGNOAVX512BW %s // AVX512BITALGNOAVX512BW-NOT: #define __AVX512BITALG__ 1 // AVX512BITALGNOAVX512BW-NOT: #define __AVX512BW__ 1 -// AVX512BITALGNOAVX512BW: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -msse4.2 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SSE42POPCNT %s @@ -435,31 +422,24 @@ // AVX512BF16: #define __AVX512BF16__ 1 // AVX512BF16: #define __AVX512BW__ 1 // AVX512BF16-NOT: #define __AVX512VL__ 1 -// AVX512BF16: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bf16 -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BF16_NOAVX512BW %s // AVX512BF16_NOAVX512BW-NOT: #define __AVX512BF16__ 1 -// AVX512BF16_NOAVX512BW: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bf16 -mno-avx512vl -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BF16_NOAVX512VL %s // AVX512BF16_NOAVX512VL: #define __AVX512BF16__ 1 -// AVX512BF16_NOAVX512VL-NOT: #define __EVEX256__ 1 -// AVX512BF16_NOAVX512VL: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -x c -E -dM -o - %s | FileCheck -check-prefix=VP2INTERSECT %s // VP2INTERSECT: #define __AVX512F__ 1 // VP2INTERSECT: #define __AVX512VP2INTERSECT__ 1 -// VP2INTERSECT: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512vp2intersect -x c -E -dM -o - %s | FileCheck -check-prefix=NOVP2INTERSECT %s // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512vp2intersect -mno-avx512f -x c -E -dM -o - %s | FileCheck -check-prefix=NOVP2INTERSECT %s // NOVP2INTERSECT-NOT: #define __AVX512VP2INTERSECT__ 1 -// NOVP2INTERSECT-NOT: #define __EVEX256__ 1 -// NOVP2INTERSECT-NOT: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mkl -x c -E -dM -o - %s | FileCheck -check-prefix=KEYLOCKER %s @@ -597,36 +577,20 @@ // AVX512FP16: #define __AVX512BW__ 1 // AVX512FP16: #define __AVX512FP16__ 1 -// AVX512FP16: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512fp16 -mno-avx512vl -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512FP16NOAVX512VL %s // AVX512FP16NOAVX512VL: #define __AVX512FP16__ 1 -// AVX512FP16NOAVX512VL: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512fp16 -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512FP16NOAVX512BW %s // AVX512FP16NOAVX512BW-NOT: #define __AVX512BW__ 1 // AVX512FP16NOAVX512BW-NOT: #define __AVX512FP16__ 1 -// AVX512FP16NOAVX512BW: #define __EVEX512__ 1 // RUN: %clang -target i386-unknown-unknown -march=atom -mavx512fp16 -mno-avx512dq -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512FP16NOAVX512DQ %s // AVX512FP16NOAVX512DQ-NOT: #define __AVX512DQ__ 1 // AVX512FP16NOAVX512DQ: #define __AVX512FP16__ 1 -// AVX512FP16NOAVX512DQ: #define __EVEX512__ 1 - -// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512f -mno-avx512f -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOEVEX512 %s -// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512cd -mno-avx512f -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOEVEX512 %s -// NOEVEX512-NOT: #define __AVX512F__ 1 -// NOEVEX512-NOT: #define __EVEX256__ 1 -// NOEVEX512-NOT: #define __EVEX512__ 1 - -// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512f -mno-evex512 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512NOEVEX512 %s -// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512cd -mno-evex512 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512NOEVEX512 %s -// AVX512NOEVEX512: #define __AVX512F__ 1 -// AVX512NOEVEX512-NOT: #define __EVEX256__ 1 -// AVX512NOEVEX512-NOT: #define __EVEX512__ 1 // RUN: %clang -target x86_64-unknown-linux-gnu -march=atom -mcmpccxadd -x c -E -dM -o - %s | FileCheck -check-prefix=CMPCCXADD %s @@ -735,29 +699,20 @@ // AVXVNNIINT16NOAVX2-NOT: #define __AVX2__ 1 // AVXVNNIINT16NOAVX2-NOT: #define __AVXVNNIINT16__ 1 -// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.1-256 -x c -E -dM -o - %s | FileCheck -check-prefix=AVX10_1_256 %s -// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.1-256 -mno-avx512f -x c -E -dM -o - %s | FileCheck -check-prefix=AVX10_1_256 %s -// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.2-256 -x c -E -dM -o - %s | FileCheck -check-prefixes=AVX10_1_256,AVX10_2_256 %s -// AVX10_1_256-NOT: __AVX10_1_512__ -// AVX10_1_256: #define __AVX10_1__ 1 -// AVX10_2_256-NOT: __AVX10_2_512__ -// AVX10_2_256: #define __AVX10_2__ 1 -// AVX10_1_256: #define __AVX512F__ 1 -// AVX10_1_256: #define __EVEX256__ 1 -// AVX10_1_256-NOT: __EVEX512__ - -// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.1-512 -x c -E -dM -o - %s | FileCheck -check-prefix=AVX10_1_512 %s -// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.1-512 -mno-avx512f -x c -E -dM -o - %s | FileCheck -check-prefix=AVX10_1_512 %s -// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.1-512 -mno-evex512 -x c -E -dM -o - %s | FileCheck -check-prefix=AVX10_1_512 %s -// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.2 -x c -E -dM -o - %s | FileCheck -check-prefixes=AVX10_1_512,AVX10_2_512 %s -// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.2-512 -x c -E -dM -o - %s | FileCheck -check-prefixes=AVX10_1_512,AVX10_2_512 %s -// AVX10_1_512: #define __AVX10_1_512__ 1 -// AVX10_1_512: #define __AVX10_1__ 1 -// AVX10_2_512: #define __AVX10_2_512__ 1 -// AVX10_2_512: #define __AVX10_2__ 1 -// AVX10_1_512: #define __AVX512F__ 1 -// AVX10_1_512: #define __EVEX256__ 1 -// AVX10_1_512: #define __EVEX512__ 1 +// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.1 -x c -E -dM -o - %s | FileCheck -check-prefix=AVX10_1 %s +// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.1 -mno-avx512f -x c -E -dM -o - %s | FileCheck -check-prefix=NO-AVX10_1 %s +// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.2 -x c -E -dM -o - %s | FileCheck -check-prefixes=AVX10_1,AVX10_2 %s +// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mavx10.2 -mno-avx10.1 -x c -E -dM -o - %s | FileCheck -check-prefixes=NO-AVX10_1,NO-AVX10_2 %s +// AVX10_1: #define __AVX10_1_512__ 1 +// AVX10_1: #define __AVX10_1__ 1 +// AVX10_2: #define __AVX10_2_512__ 1 +// AVX10_2: #define __AVX10_2__ 1 +// AVX10_1: #define __AVX512F__ 1 +// NO-AVX10_1-NOT: __AVX10_1_512__ +// NO-AVX10_1-NOT: __AVX10_1__ +// NO-AVX10_1-NOT: __AVX10_2_512__ +// NO-AVX10_1-NOT: __AVX10_2__ +// NO-AVX10_2: #define __AVX512F__ 1 // RUN: %clang -target i686-unknown-linux-gnu -march=atom -musermsr -x c -E -dM -o - %s | FileCheck -check-prefix=USERMSR %s // USERMSR: #define __USERMSR__ 1 diff --git a/flang/test/Driver/target-cpu-features.f90 b/flang/test/Driver/target-cpu-features.f90 index 17b8be49d9168..58ee670d46c51 100644 --- a/flang/test/Driver/target-cpu-features.f90 +++ b/flang/test/Driver/target-cpu-features.f90 @@ -23,12 +23,6 @@ ! RUN: %flang --target=x86_64-linux-gnu -mno-apx-features=ccmp -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-NO-APX -! RUN: %flang --target=x86_64-linux-gnu -mevex512 -c %s -### 2>&1 \ -! RUN: | FileCheck %s -check-prefix=CHECK-EVEX512 - -! RUN: %flang --target=x86_64-linux-gnu -mno-evex512 -c %s -### 2>&1 \ -! RUN: | FileCheck %s -check-prefix=CHECK-NO-EVEX512 - ! RUN: %flang --target=x86_64h-linux-gnu -c %s -### 2>&1 \ ! RUN: | FileCheck %s -check-prefix=CHECK-X86_64H @@ -76,12 +70,6 @@ ! CHECK-NO-APX: "-fc1" "-triple" "x86_64-unknown-linux-gnu" ! CHECK-NO-APX-SAME: "-target-feature" "-ccmp" -! CHECK-EVEX512: "-fc1" "-triple" "x86_64-unknown-linux-gnu" -! CHECK-EVEX512-SAME: "-target-feature" "+evex512" - -! CHECK-NO-EVEX512: "-fc1" "-triple" "x86_64-unknown-linux-gnu" -! CHECK-NO-EVEX512-SAME: "-target-feature" "-evex512" - ! CHECK-X86_64H: "-fc1" "-triple" "x86_64h-unknown-linux-gnu" ! CHECK-X86_64H-SAME: "-target-cpu" "x86-64" "-target-feature" "-rdrnd" "-target-feature" "-aes" "-target-feature" "-pclmul" "-target-feature" "-rtm" "-target-feature" "-fsgsbase" diff --git a/llvm/include/llvm/TargetParser/X86TargetParser.def b/llvm/include/llvm/TargetParser/X86TargetParser.def index 5b719a2b0eb39..e62aa6d6dadbc 100644 --- a/llvm/include/llvm/TargetParser/X86TargetParser.def +++ b/llvm/include/llvm/TargetParser/X86TargetParser.def @@ -258,9 +258,9 @@ X86_FEATURE_COMPAT(SHA512, "sha512", 0) X86_FEATURE_COMPAT(SM4, "sm4", 0) X86_FEATURE (EGPR, "egpr") X86_FEATURE_COMPAT(USERMSR, "usermsr", 0) -X86_FEATURE_COMPAT(AVX10_1, "avx10.1-256", 36) +X86_FEATURE_COMPAT(AVX10_1, "avx10.1", 36) X86_FEATURE_COMPAT(AVX10_1_512, "avx10.1-512", 37) -X86_FEATURE_COMPAT(AVX10_2, "avx10.2-256", 0) +X86_FEATURE_COMPAT(AVX10_2, "avx10.2", 0) X86_FEATURE_COMPAT(AVX10_2_512, "avx10.2-512", 0) //FIXME: make MOVRS _COMPAT defined when gcc landed relate patch. X86_FEATURE (MOVRS, "movrs") diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 4e71a673bde6b..5d65b23e44071 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -2446,16 +2446,6 @@ void Verifier::verifyFunctionAttrs(FunctionType *FT, AttributeList Attrs, CheckFailed("invalid value for 'frame-pointer' attribute: " + FP, V); } - // Check EVEX512 feature. - if (TT.isX86() && MaxParameterWidth >= 512) { - Attribute TargetFeaturesAttr = Attrs.getFnAttr("target-features"); - if (TargetFeaturesAttr.isValid()) { - StringRef TF = TargetFeaturesAttr.getValueAsString(); - Check(!TF.contains("+avx512f") || !TF.contains("-evex512"), - "512-bit vector arguments require 'evex512' for AVX512", V); - } - } - checkUnsignedBaseTenFuncAttr(Attrs, "patchable-function-prefix", V); checkUnsignedBaseTenFuncAttr(Attrs, "patchable-function-entry", V); if (Attrs.hasFnAttr("patchable-function-entry-section")) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index a15930c1433f7..cfe5b1094811a 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -1047,9 +1047,6 @@ X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI, Prefix.setL(TSFlags & X86II::VEX_L); Prefix.setL2(TSFlags & X86II::EVEX_L2); - if ((TSFlags & X86II::EVEX_L2) && STI.hasFeature(X86::FeatureAVX512) && - !STI.hasFeature(X86::FeatureEVEX512)) - report_fatal_error("ZMM registers are not supported without EVEX512"); switch (TSFlags & X86II::OpPrefixMask) { case X86II::PD: Prefix.setPP(0x1); // 66 diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index cc7bcd678cb31..bb1e716c33ed5 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -397,18 +397,6 @@ MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, if (CPU.empty()) CPU = "generic"; - size_t posNoEVEX512 = FS.rfind("-evex512"); - // Make sure we won't be cheated by "-avx512fp16". - size_t posNoAVX512F = - FS.ends_with("-avx512f") ? FS.size() - 8 : FS.rfind("-avx512f,"); - size_t posEVEX512 = FS.rfind("+evex512"); - size_t posAVX512F = FS.rfind("+avx512"); // Any AVX512XXX will enable AVX512F. - - if (posAVX512F != StringRef::npos && - (posNoAVX512F == StringRef::npos || posNoAVX512F < posAVX512F)) - if (posEVEX512 == StringRef::npos && posNoEVEX512 == StringRef::npos) - ArchFS += ",+evex512"; - return createX86MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, ArchFS); } diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 9cfe081b87109..7c9e821c02fda 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -113,6 +113,7 @@ def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", "Support 16-bit floating point conversion instructions", [FeatureAVX]>; +// Deprecated feature. Keep it here to suppress warnings in old IRs. def FeatureEVEX512 : SubtargetFeature<"evex512", "HasEVEX512", "true", "Support ZMM and 64-bit mask instructions">; def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512", @@ -329,20 +330,22 @@ def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", "Support movdiri instruction (direct store integer)">; def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", "Support movdir64b instruction (direct store 64 bytes)">; -def FeatureAVX10_1 : SubtargetFeature<"avx10.1-256", "HasAVX10_1", "true", - "Support AVX10.1 up to 256-bit instruction", +def FeatureAVX10_1 : SubtargetFeature<"avx10.1", "HasAVX10_1", "true", + "Support AVX10.1 instruction", [FeatureCDI, FeatureVBMI, FeatureIFMA, FeatureVNNI, FeatureBF16, FeatureVPOPCNTDQ, FeatureVBMI2, FeatureBITALG, FeatureFP16, FeatureVLX, FeatureDQI]>; +// Deprecated feature. Keep it here to suppress warnings in old IRs. def FeatureAVX10_1_512 : SubtargetFeature<"avx10.1-512", "HasAVX10_1_512", "true", - "Support AVX10.1 up to 512-bit instruction", - [FeatureAVX10_1, FeatureEVEX512]>; -def FeatureAVX10_2 : SubtargetFeature<"avx10.2-256", "HasAVX10_2", "true", - "Support AVX10.2 up to 256-bit instruction", + "Support AVX10.1 instruction", + [FeatureAVX10_1]>; +def FeatureAVX10_2 : SubtargetFeature<"avx10.2", "HasAVX10_2", "true", + "Support AVX10.2 instruction", [FeatureAVX10_1]>; +// Deprecated feature. Keep it here to suppress warnings in old IRs. def FeatureAVX10_2_512 : SubtargetFeature<"avx10.2-512", "HasAVX10_2_512", "true", - "Support AVX10.2 up to 512-bit instruction", - [FeatureAVX10_2, FeatureAVX10_1_512]>; + "Support AVX10.2 instruction", + [FeatureAVX10_2]>; def FeatureEGPR : SubtargetFeature<"egpr", "HasEGPR", "true", "Support extended general purpose register">; def FeaturePush2Pop2 : SubtargetFeature<"push2pop2", "HasPush2Pop2", "true", @@ -871,7 +874,6 @@ def ProcessorFeatures { ]; list X86_64V4Features = !listconcat(X86_64V3Features, [ - FeatureEVEX512, FeatureBWI, FeatureCDI, FeatureDQI, @@ -996,7 +998,6 @@ def ProcessorFeatures { FeatureXSAVES, FeatureCLFLUSHOPT, FeatureAVX512, - FeatureEVEX512, FeatureCDI, FeatureDQI, FeatureBWI, @@ -1039,7 +1040,6 @@ def ProcessorFeatures { // Cannonlake list CNLAdditionalFeatures = [FeatureAVX512, - FeatureEVEX512, FeatureCDI, FeatureDQI, FeatureBWI, @@ -1155,7 +1155,7 @@ def ProcessorFeatures { !listconcat(GNRFeatures, GNRDAdditionalFeatures); // Diamond Rapids - list DMRAdditionalFeatures = [FeatureAVX10_2_512, + list DMRAdditionalFeatures = [FeatureAVX10_2, FeatureSM4, FeatureCMPCCXADD, FeatureAVXIFMA, @@ -1368,7 +1368,6 @@ def ProcessorFeatures { FeatureF16C, FeatureFSGSBase, FeatureAVX512, - FeatureEVEX512, FeatureCDI, FeatureADX, FeatureRDSEED, @@ -1586,7 +1585,6 @@ def ProcessorFeatures { list ZN4Tuning = !listconcat(ZN3Tuning, ZN4AdditionalTuning); list ZN4AdditionalFeatures = [FeatureAVX512, - FeatureEVEX512, FeatureCDI, FeatureDQI, FeatureBWI, diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 8affeab2117fd..cdc97faf394ca 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -326,15 +326,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, if (Subtarget.hasAVX10_2()) { setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v2i32, Custom); setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v2i32, Custom); + setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v8i64, Legal); + setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v8i64, Legal); for (MVT VT : {MVT::i32, MVT::v4i32, MVT::v8i32, MVT::v16i32, MVT::v2i64, MVT::v4i64}) { setOperationAction(ISD::FP_TO_UINT_SAT, VT, Legal); setOperationAction(ISD::FP_TO_SINT_SAT, VT, Legal); } - if (Subtarget.hasAVX10_2_512()) { - setOperationAction(ISD::FP_TO_UINT_SAT, MVT::v8i64, Legal); - setOperationAction(ISD::FP_TO_SINT_SAT, MVT::v8i64, Legal); - } if (Subtarget.is64Bit()) { setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Legal); setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Legal); @@ -2457,6 +2455,17 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, } if (!Subtarget.useSoftFloat() && Subtarget.hasAVX10_2()) { + setOperationAction(ISD::FADD, MVT::v32bf16, Legal); + setOperationAction(ISD::FSUB, MVT::v32bf16, Legal); + setOperationAction(ISD::FMUL, MVT::v32bf16, Legal); + setOperationAction(ISD::FDIV, MVT::v32bf16, Legal); + setOperationAction(ISD::FSQRT, MVT::v32bf16, Legal); + setOperationAction(ISD::FMA, MVT::v32bf16, Legal); + setOperationAction(ISD::SETCC, MVT::v32bf16, Custom); + setOperationAction(ISD::FMINIMUM, MVT::v32bf16, Custom); + setOperationAction(ISD::FMAXIMUM, MVT::v32bf16, Custom); + setOperationAction(ISD::FMINIMUMNUM, MVT::v32bf16, Custom); + setOperationAction(ISD::FMAXIMUMNUM, MVT::v32bf16, Custom); for (auto VT : {MVT::v8bf16, MVT::v16bf16}) { setOperationAction(ISD::FADD, VT, Legal); setOperationAction(ISD::FSUB, VT, Legal); @@ -2470,19 +2479,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(ISD::FMINIMUMNUM, VT, Custom); setOperationAction(ISD::FMAXIMUMNUM, VT, Custom); } - if (Subtarget.hasAVX10_2_512()) { - setOperationAction(ISD::FADD, MVT::v32bf16, Legal); - setOperationAction(ISD::FSUB, MVT::v32bf16, Legal); - setOperationAction(ISD::FMUL, MVT::v32bf16, Legal); - setOperationAction(ISD::FDIV, MVT::v32bf16, Legal); - setOperationAction(ISD::FSQRT, MVT::v32bf16, Legal); - setOperationAction(ISD::FMA, MVT::v32bf16, Legal); - setOperationAction(ISD::SETCC, MVT::v32bf16, Custom); - setOperationAction(ISD::FMINIMUM, MVT::v32bf16, Custom); - setOperationAction(ISD::FMAXIMUM, MVT::v32bf16, Custom); - setOperationAction(ISD::FMINIMUMNUM, MVT::v32bf16, Custom); - setOperationAction(ISD::FMAXIMUMNUM, MVT::v32bf16, Custom); - } for (auto VT : {MVT::f16, MVT::f32, MVT::f64}) { setCondCodeAction(ISD::SETOEQ, VT, Custom); setCondCodeAction(ISD::SETUNE, VT, Custom); @@ -31414,9 +31410,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget, return R; // AVX512 implicitly uses modulo rotation amounts. - if ((Subtarget.hasVLX() || - (Subtarget.hasAVX512() && Subtarget.hasEVEX512())) && - 32 <= EltSizeInBits) { + if ((Subtarget.hasVLX() || Subtarget.hasAVX512()) && 32 <= EltSizeInBits) { // Attempt to rotate by immediate. if (IsCstSplat) { unsigned RotOpc = IsROTL ? X86ISD::VROTLI : X86ISD::VROTRI; diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp index 1c745a338a617..3bc46af4d130b 100644 --- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp +++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp @@ -302,7 +302,7 @@ EVT X86TargetLowering::getOptimalMemOpType( if (Op.size() >= 16 && (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(Align(16)))) { // FIXME: Check if unaligned 64-byte accesses are slow. - if (Op.size() >= 64 && Subtarget.hasAVX512() && Subtarget.hasEVEX512() && + if (Op.size() >= 64 && Subtarget.hasAVX512() && (Subtarget.getPreferVectorWidth() >= 512)) { return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32; } @@ -416,7 +416,7 @@ bool X86TargetLowering::allowsMemoryAccess(LLVMContext &Context, return true; return false; case 512: - if (Subtarget.hasAVX512() && Subtarget.hasEVEX512()) + if (Subtarget.hasAVX512()) return true; return false; default: diff --git a/llvm/lib/Target/X86/X86InstrAMX.td b/llvm/lib/Target/X86/X86InstrAMX.td index 1beaaafb159e3..69a5115201ef2 100644 --- a/llvm/lib/Target/X86/X86InstrAMX.td +++ b/llvm/lib/Target/X86/X86InstrAMX.td @@ -550,7 +550,7 @@ let Predicates = [HasAMXMOVRS, In64BitMode], SchedRW = [WriteSystem] in { } // HasAMXMOVRS, In64BitMode multiclass m_tcvtrowd2ps { - let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in { + let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in { let SchedRW = [WriteSystem] in { def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst), (ins TILE:$src1, i32u8imm:$src2), @@ -561,12 +561,12 @@ multiclass m_tcvtrowd2ps { "tcvtrowd2ps\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, T8,XS, EVEX, VVVV, EVEX_V512; } - } // HasAMXAVX512, HasAVX10_2_512, In64BitMode + } // HasAMXAVX512, HasAVX10_2, In64BitMode } defm TCVTROWD2PS : m_tcvtrowd2ps; -let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in { +let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in { let SchedRW = [WriteSystem] in { let usesCustomInserter = 1 in { def PTCVTROWD2PSrri : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2), @@ -630,7 +630,7 @@ let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in { multiclass AMXAVX512_BASE Opcode1, bits<8> Opcode2, string Opstr, Prefix P1, Prefix P2> { - let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode], SchedRW = [WriteSystem] in { + let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode], SchedRW = [WriteSystem] in { let OpPrefix = P1 in def rre : I; defm TCVTROWPS2BF16L : AMXAVX512_BASE<0x6d, 0x77, "tcvtrowps2bf16l", XS, XS>; multiclass m_tilemovrow { - let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in { + let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in { let SchedRW = [WriteSystem] in { def rri : Ii8<0x7, MRMSrcReg, (outs VR512:$dst), (ins TILE:$src1, u8imm:$src2), @@ -669,12 +669,12 @@ multiclass m_tilemovrow { "tilemovrow\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, T8,PD, EVEX, VVVV, EVEX_V512; } - } // HasAMXAVX512, HasAVX10_2_512, In64BitMode + } // HasAMXAVX512, HasAVX10_2, In64BitMode } defm TILEMOVROW : m_tilemovrow; -let Predicates = [HasAMXAVX512, HasAVX10_2_512, In64BitMode] in { +let Predicates = [HasAMXAVX512, HasAVX10_2, In64BitMode] in { let SchedRW = [WriteSystem] in { let usesCustomInserter = 1 in { def PTILEMOVROWrri : PseudoI<(outs VR512:$dst), (ins u8imm:$src1, i32u8imm:$src2), diff --git a/llvm/lib/Target/X86/X86InstrAVX10.td b/llvm/lib/Target/X86/X86InstrAVX10.td index 2d2bf1f6c725e..764ff998bb562 100644 --- a/llvm/lib/Target/X86/X86InstrAVX10.td +++ b/llvm/lib/Target/X86/X86InstrAVX10.td @@ -15,36 +15,36 @@ // VNNI FP16 let ExeDomain = SSEPackedSingle in defm VDPPHPS : avx512_dpf16ps_sizes<0x52, "vdpphps", X86dpfp16ps, avx512vl_f16_info, - [HasAVX10_2], [HasAVX10_2_512]>, + [HasAVX10_2], [HasAVX10_2]>, T8, PS, EVEX_CD8<32, CD8VF>; // VNNI INT8 defm VPDPBSSD : VNNI_common<0x50, "vpdpbssd", X86vpdpbssd, SchedWriteVecIMul, 1, - [HasAVX10_2], [HasAVX10_2_512]>, XD; + [HasAVX10_2], [HasAVX10_2]>, XD; defm VPDPBSSDS : VNNI_common<0x51, "vpdpbssds", X86vpdpbssds, SchedWriteVecIMul, 1, - [HasAVX10_2], [HasAVX10_2_512]>, XD; + [HasAVX10_2], [HasAVX10_2]>, XD; defm VPDPBSUD : VNNI_common<0x50, "vpdpbsud", X86vpdpbsud, SchedWriteVecIMul, 0, - [HasAVX10_2], [HasAVX10_2_512]>, XS; + [HasAVX10_2], [HasAVX10_2]>, XS; defm VPDPBSUDS : VNNI_common<0x51, "vpdpbsuds", X86vpdpbsuds, SchedWriteVecIMul, 0, - [HasAVX10_2], [HasAVX10_2_512]>, XS; + [HasAVX10_2], [HasAVX10_2]>, XS; defm VPDPBUUD : VNNI_common<0x50, "vpdpbuud", X86vpdpbuud, SchedWriteVecIMul, 1, - [HasAVX10_2], [HasAVX10_2_512]>, PS; + [HasAVX10_2], [HasAVX10_2]>, PS; defm VPDPBUUDS : VNNI_common<0x51, "vpdpbuuds", X86vpdpbuuds, SchedWriteVecIMul, 1, - [HasAVX10_2], [HasAVX10_2_512]>, PS; + [HasAVX10_2], [HasAVX10_2]>, PS; // VNNI INT16 defm VPDPWSUD : VNNI_common<0xd2, "vpdpwsud", X86vpdpwsud, SchedWriteVecIMul, 0, - [HasAVX10_2], [HasAVX10_2_512]>, XS; + [HasAVX10_2], [HasAVX10_2]>, XS; defm VPDPWSUDS : VNNI_common<0xd3, "vpdpwsuds", X86vpdpwsuds, SchedWriteVecIMul, 0, - [HasAVX10_2], [HasAVX10_2_512]>, XS; + [HasAVX10_2], [HasAVX10_2]>, XS; defm VPDPWUSD : VNNI_common<0xd2, "vpdpwusd", X86vpdpwusd, SchedWriteVecIMul, 0, - [HasAVX10_2], [HasAVX10_2_512]>, PD; + [HasAVX10_2], [HasAVX10_2]>, PD; defm VPDPWUSDS : VNNI_common<0xd3, "vpdpwusds", X86vpdpwusds, SchedWriteVecIMul, 0, - [HasAVX10_2], [HasAVX10_2_512]>, PD; + [HasAVX10_2], [HasAVX10_2]>, PD; defm VPDPWUUD : VNNI_common<0xd2, "vpdpwuud", X86vpdpwuud, SchedWriteVecIMul, 1, - [HasAVX10_2], [HasAVX10_2_512]>, PS; + [HasAVX10_2], [HasAVX10_2]>, PS; defm VPDPWUUDS : VNNI_common<0xd3, "vpdpwuuds", X86vpdpwuuds, SchedWriteVecIMul, 1, - [HasAVX10_2], [HasAVX10_2_512]>, PS; + [HasAVX10_2], [HasAVX10_2]>, PS; // VMPSADBW defm VMPSADBW : avx512_common_3Op_rm_imm8<0x42, X86Vmpsadbw, "vmpsadbw", SchedWritePSADBW, @@ -94,9 +94,8 @@ multiclass avx10_minmax_packed_sae { - let Predicates = [HasAVX10_2_512] in - defm Z : avx10_minmax_packed_base, EVEX_V512; let Predicates = [HasAVX10_2] in { + defm Z : avx10_minmax_packed_base, EVEX_V512; defm Z256 : avx10_minmax_packed_base, EVEX_V256; defm Z128 : avx10_minmax_packed_base, EVEX_V128; } @@ -201,7 +200,7 @@ multiclass avx10_sat_cvt_rmb Opc, string OpStr, X86FoldableSchedWrite sc multiclass avx10_sat_cvt_rc Opc, string OpStr, X86SchedWriteWidths sched, AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo, SDNode MaskNode> { - let Predicates = [HasAVX10_2_512], Uses = [MXCSR] in + let Predicates = [HasAVX10_2], Uses = [MXCSR] in defm Zrrb : AVX512_maskable Opc, string OpStr, X86SchedWriteWidths sched multiclass avx10_sat_cvt_sae Opc, string OpStr, X86SchedWriteWidths sched, AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo, SDNode Node> { - let Predicates = [HasAVX10_2_512], Uses = [MXCSR] in + let Predicates = [HasAVX10_2], Uses = [MXCSR] in defm Zrrb : AVX512_maskable Opc, string OpStr, X86SchedWriteWidths sche multiclass avx10_sat_cvt_base Opc, string OpStr, X86SchedWriteWidths sched, SDNode MaskNode, AVX512VLVectorVTInfo DestInfo, AVX512VLVectorVTInfo SrcInfo> { - let Predicates = [HasAVX10_2_512] in - defm Z : avx10_sat_cvt_rmb, - EVEX, EVEX_V512; let Predicates = [HasAVX10_2] in { + defm Z : avx10_sat_cvt_rmb, + EVEX, EVEX_V512; defm Z256 : avx10_sat_cvt_rmb opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in { + let Predicates = [HasAVX10_2] in { defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; - } - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_vcvt_fp, EVEX_V128; @@ -410,13 +406,11 @@ multiclass avx10_cvttpd2dqs opc, string OpcodeStr, SDPatternOperator OpN multiclass avx10_cvttpd2qqs opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in { + let Predicates = [HasAVX10_2] in { defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; - } - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_vcvt_fp, EVEX_V128; defm Z256 : avx512_vcvt_fp opc, string OpcodeStr, SDPatternOperator OpN multiclass avx10_cvttps2qqs opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeRnd, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in { + let Predicates = [HasAVX10_2] in { defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; - } - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_vcvt_fp opc, string OpcodeStr, SDPatternOperator OpN multiclass avx10_cvttps2dqs opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, SDNode OpNodeSAE, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in { + let Predicates = [HasAVX10_2] in { defm Z : avx512_vcvt_fp, avx512_vcvt_fp_sae, EVEX_V512; - } - - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_vcvt_fp, EVEX_V128; defm Z256 : avx512_vcvt_fp opc, string OpcodeStr, AVX512VLVectorVTInfo _SrcVTInfo, AVX512VLVectorVTInfo _DstVTInfo, SDNode OpNode, SDNode OpNodeRnd> { - let Predicates = [HasAVX10_2_512], Uses = [MXCSR] in { + let Predicates = [HasAVX10_2] in { defm Z : avx512_binop_rm2, @@ -727,8 +716,6 @@ multiclass avx10_cvt2ps2ph opc, string OpcodeStr, _SrcVTInfo.info512, _DstVTInfo.info512, OpNodeRnd>, EVEX_V512, EVEX_CD8<32, CD8VF>; - } - let Predicates = [HasAVX10_2] in { defm Z256 : avx512_binop_rm2, @@ -747,19 +734,19 @@ defm VCVT2PS2PHX : avx10_cvt2ps2ph<0x67, "vcvt2ps2phx", defm VCVT2PH2BF8 : avx512_binop_all<0x74, "vcvt2ph2bf8", SchedWriteCvtPD2PS, avx512vl_f16_info, avx512vl_i8_info, - X86vcvt2ph2bf8, [HasAVX10_2_512], [HasAVX10_2]>, + X86vcvt2ph2bf8, [HasAVX10_2], [HasAVX10_2]>, EVEX_CD8<16, CD8VF>, T8, XD; defm VCVT2PH2BF8S : avx512_binop_all<0x74, "vcvt2ph2bf8s", SchedWriteCvtPD2PS, avx512vl_f16_info, avx512vl_i8_info, - X86vcvt2ph2bf8s, [HasAVX10_2_512], [HasAVX10_2]>, + X86vcvt2ph2bf8s, [HasAVX10_2], [HasAVX10_2]>, EVEX_CD8<16, CD8VF>, T_MAP5, XD; defm VCVT2PH2HF8 : avx512_binop_all<0x18, "vcvt2ph2hf8", SchedWriteCvtPD2PS, avx512vl_f16_info, avx512vl_i8_info, - X86vcvt2ph2hf8, [HasAVX10_2_512], [HasAVX10_2]>, + X86vcvt2ph2hf8, [HasAVX10_2], [HasAVX10_2]>, EVEX_CD8<16, CD8VF>, T_MAP5, XD; defm VCVT2PH2HF8S : avx512_binop_all<0x1b, "vcvt2ph2hf8s", SchedWriteCvtPD2PS, avx512vl_f16_info, avx512vl_i8_info, - X86vcvt2ph2hf8s, [HasAVX10_2_512], [HasAVX10_2]>, + X86vcvt2ph2hf8s, [HasAVX10_2], [HasAVX10_2]>, EVEX_CD8<16, CD8VF>, T_MAP5, XD; //TODO: Merge into avx512_vcvt_fp, diffrence is one more source register here. @@ -836,11 +823,10 @@ multiclass avx10_convert_3op OpCode, string OpcodeStr, PatFrag bcast128 = vt_src.info128.BroadcastLdFrag, PatFrag loadVT128 = vt_src.info128.LdFrag, RegisterClass maskRC128 = vt_src.info128.KRCWM> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx10_convert_3op_packed, EVEX_V512, EVEX_CD8<16, CD8VF>; - let Predicates = [HasAVX10_2] in { defm Z256 : avx10_convert_3op_packed, EVEX_V256, EVEX_CD8<16, CD8VF>; @@ -920,25 +906,25 @@ defm VCVTBIASPH2HF8S : avx10_convert_3op<0x1b, "vcvtbiasph2hf8s", defm VCVTPH2BF8 : avx512_cvt_trunc_ne<0x74, "vcvtph2bf8", avx512vl_i8_info, avx512vl_f16_info, SchedWriteCvtPD2PS, X86vcvtph2bf8, X86vmcvtph2bf8, - [HasAVX10_2], [HasAVX10_2_512]>, + [HasAVX10_2], [HasAVX10_2]>, T8, XS, EVEX_CD8<16, CD8VF>; defm VCVTPH2BF8S : avx512_cvt_trunc_ne<0x74, "vcvtph2bf8s", avx512vl_i8_info, avx512vl_f16_info, SchedWriteCvtPD2PS, X86vcvtph2bf8s, X86vmcvtph2bf8s, - [HasAVX10_2], [HasAVX10_2_512]>, + [HasAVX10_2], [HasAVX10_2]>, T_MAP5, XS, EVEX_CD8<16, CD8VF>; defm VCVTPH2HF8 : avx512_cvt_trunc_ne<0x18, "vcvtph2hf8", avx512vl_i8_info, avx512vl_f16_info, SchedWriteCvtPD2PS, X86vcvtph2hf8, X86vmcvtph2hf8, - [HasAVX10_2], [HasAVX10_2_512]>, + [HasAVX10_2], [HasAVX10_2]>, T_MAP5, XS, EVEX_CD8<16, CD8VF>; defm VCVTPH2HF8S : avx512_cvt_trunc_ne<0x1b, "vcvtph2hf8s", avx512vl_i8_info, avx512vl_f16_info, SchedWriteCvtPD2PS, X86vcvtph2hf8s, X86vmcvtph2hf8s, - [HasAVX10_2], [HasAVX10_2_512]>, + [HasAVX10_2], [HasAVX10_2]>, T_MAP5, XS, EVEX_CD8<16, CD8VF>; multiclass avx10_convert_2op_nomb_packed opc, string OpcodeStr, @@ -962,10 +948,9 @@ multiclass avx10_convert_2op_nomb_packed opc, string OpcodeStr, multiclass avx10_convert_2op_nomb opc, SDNode OpNode> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx10_convert_2op_nomb_packed, EVEX_V512; - let Predicates = [HasAVX10_2] in { defm Z128 : avx10_convert_2op_nomb_packed, EVEX_V128; defm Z256 : avx10_convert_2op_nomb_packed opc, string OpcodeStr, X86SchedWriteSizes sched, bit IsCommutable = 0> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx512_fp_packed("int_x86_avx10_"#OpcodeStr#"bf16512"), !cast("int_x86_avx10_"#OpcodeStr#"bf16512"), v32bf16_info, sched.PH.ZMM, IsCommutable>, EVEX_V512, T_MAP5, PD, EVEX_CD8<16, CD8VF>; - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_fp_packed("int_x86_avx10_"#OpcodeStr#"bf16128"), !cast("int_x86_avx10_"#OpcodeStr#"bf16128"), @@ -1009,11 +993,10 @@ multiclass avx10_fp_binop_bf16 opc, string OpcodeStr, SDPatternOperator X86SchedWriteSizes sched, bit IsCommutable = 0, SDPatternOperator MaskOpNode = OpNode> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx512_fp_packed, EVEX_V512, T_MAP5, PD, EVEX_CD8<16, CD8VF>; - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_fp_packed, EVEX_V128, T_MAP5, PD, EVEX_CD8<16, CD8VF>; @@ -1086,9 +1069,8 @@ multiclass avx10_vcmp_common_bf16 { - let Predicates = [HasAVX10_2_512] in - defm Z : avx10_vcmp_common_bf16, EVEX_V512; let Predicates = [HasAVX10_2] in { + defm Z : avx10_vcmp_common_bf16, EVEX_V512; defm Z128 : avx10_vcmp_common_bf16, EVEX_V128; defm Z256 : avx10_vcmp_common_bf16, EVEX_V256; } @@ -1102,11 +1084,10 @@ defm VCMPBF16 : avx10_vcmp_bf16, // VSQRTBF16 multiclass avx10_sqrt_packed_bf16 opc, string OpcodeStr, X86SchedWriteSizes sched> { - let Predicates = [HasAVX10_2_512] in - defm Z : avx512_sqrt_packed, - EVEX_V512, PD, T_MAP5, EVEX_CD8<16, CD8VF>; let Predicates = [HasAVX10_2] in { + defm Z : avx512_sqrt_packed, + EVEX_V512, PD, T_MAP5, EVEX_CD8<16, CD8VF>; defm Z128 : avx512_sqrt_packed, EVEX_V128, PD, T_MAP5, EVEX_CD8<16, CD8VF>; @@ -1122,11 +1103,10 @@ defm VSQRTBF16 : avx10_sqrt_packed_bf16<0x51, "vsqrt", SchedWriteFSqrtSizes>; // VRSQRTBF16, VRCPBF16, VSRQTBF16, VGETEXPBF16 multiclass avx10_fp14_bf16 opc, string OpcodeStr, SDNode OpNode, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in - defm BF16Z : avx512_fp14_p, - EVEX_V512; let Predicates = [HasAVX10_2] in { + defm BF16Z : avx512_fp14_p, + EVEX_V512; defm BF16Z128 : avx512_fp14_p, EVEX_V128; @@ -1146,10 +1126,9 @@ defm VGETEXP : avx10_fp14_bf16<0x42, "vgetexp", X86fgetexp, SchedWriteFRnd>, // VSCALEFBF16 multiclass avx10_fp_scalef_bf16 opc, string OpcodeStr, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx512_fp_scalef_p, EVEX_V512, T_MAP6, PS, EVEX_CD8<16, CD8VF>; - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_fp_scalef_p, EVEX_V128, EVEX_CD8<16, CD8VF>, T_MAP6, PS; defm Z256 : avx512_fp_scalef_p, @@ -1164,10 +1143,9 @@ defm VSCALEFBF16 : avx10_fp_scalef_bf16<0x2C, "vscalef", SchedWriteFAdd>; multiclass avx10_common_unary_fp_packed_imm_bf16 opc, SDPatternOperator OpNode, SDPatternOperator MaskOpNode, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx512_unary_fp_packed_imm, EVEX_V512; - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_unary_fp_packed_imm, EVEX_V128; defm Z256 : avx512_unary_fp_packed_imm opcVec, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx512_vector_fpclass>, EVEX_V512; - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_vector_fpclass>, EVEX_V128; @@ -1211,11 +1188,10 @@ defm VFPCLASSBF16 : avx10_fp_fpclass_bf16<"vfpclass", 0x66, SchedWriteFCmp>, multiclass avx10_fma3p_213_bf16 opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx512_fma3p_213_rm, EVEX_V512, T_MAP6, PS, EVEX_CD8<16, CD8VF>; - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_fma3p_213_rm, EVEX_V128, T_MAP6, PS, EVEX_CD8<16, CD8VF>; @@ -1239,11 +1215,10 @@ defm VFNMSUB213BF16 : avx10_fma3p_213_bf16<0xAE, "vfnmsub213bf16", X86any_Fnmsub multiclass avx10_fma3p_231_bf16 opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx512_fma3p_231_rm, EVEX_V512, T_MAP6, PS, EVEX_CD8<16, CD8VF>; - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_fma3p_231_rm, EVEX_V128, T_MAP6, PS, EVEX_CD8<16, CD8VF>; @@ -1267,11 +1242,10 @@ defm VFNMSUB231BF16 : avx10_fma3p_231_bf16<0xBE, "vfnmsub231bf16", X86any_Fnmsub multiclass avx10_fma3p_132_bf16 opc, string OpcodeStr, SDPatternOperator OpNode, SDNode MaskOpNode, X86SchedWriteWidths sched> { - let Predicates = [HasAVX10_2_512] in + let Predicates = [HasAVX10_2] in { defm Z : avx512_fma3p_132_rm, EVEX_V512, T_MAP6, PS, EVEX_CD8<16, CD8VF>; - let Predicates = [HasAVX10_2] in { defm Z128 : avx512_fma3p_132_rm, EVEX_V128, T_MAP6, PS, EVEX_CD8<16, CD8VF>; @@ -1440,9 +1414,8 @@ multiclass vmovrs_p opc, string OpStr, X86VectorVTInfo _> { } multiclass vmovrs_p_vl opc, string OpStr, AVX512VLVectorVTInfo _Vec> { - let Predicates = [HasMOVRS, HasAVX10_2_512, In64BitMode] in - defm Z : vmovrs_p, EVEX_V512; let Predicates = [HasMOVRS, HasAVX10_2, In64BitMode] in { + defm Z : vmovrs_p, EVEX_V512; defm Z128 : vmovrs_p, EVEX_V128; defm Z256 : vmovrs_p, EVEX_V256; } @@ -1464,7 +1437,7 @@ multiclass avx10_sm4_base { defm Z128 : SM4_Base, EVEX_V128; defm Z256 : SM4_Base, EVEX_V256; } - let Predicates = [HasSM4, HasAVX10_2_512] in + let Predicates = [HasSM4, HasAVX10_2] in defm Z : SM4_Base, EVEX_V512; } diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 0ab94cca41425..3401f6f04800e 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -834,7 +834,7 @@ defm : vextract_for_size_lowering<"VEXTRACTF64X4Z", v32bf16_info, v16bf16x_info, // A 128-bit extract from bits [255:128] of a 512-bit vector should use a // smaller extract to enable EVEX->VEX. -let Predicates = [NoVLX, HasEVEX512] in { +let Predicates = [NoVLX] in { def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 2))), (v2i64 (VEXTRACTI128rri (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm)), @@ -3088,7 +3088,7 @@ def : Pat<(Narrow.KVT (and Narrow.KRC:$mask, addr:$src2, (X86cmpm_imm_commute timm:$cc)), Narrow.KRC)>; } -let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { +let Predicates = [HasAVX512, NoVLX] in { defm : axv512_icmp_packed_cc_no_vlx_lowering; defm : axv512_icmp_packed_cc_no_vlx_lowering; @@ -3119,7 +3119,7 @@ let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { defm : axv512_cmp_packed_cc_no_vlx_lowering<"VCMPPD", v2f64x_info, v8f64_info>; } -let Predicates = [HasBWI, NoVLX, HasEVEX512] in { +let Predicates = [HasBWI, NoVLX] in { defm : axv512_icmp_packed_cc_no_vlx_lowering; defm : axv512_icmp_packed_cc_no_vlx_lowering; @@ -3513,7 +3513,7 @@ multiclass mask_move_lowering; defm : mask_move_lowering<"VMOVDQA32Z", v4i32x_info, v16i32_info>; defm : mask_move_lowering<"VMOVAPSZ", v8f32x_info, v16f32_info>; @@ -3525,7 +3525,7 @@ let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { defm : mask_move_lowering<"VMOVDQA64Z", v4i64x_info, v8i64_info>; } -let Predicates = [HasBWI, NoVLX, HasEVEX512] in { +let Predicates = [HasBWI, NoVLX] in { defm : mask_move_lowering<"VMOVDQU8Z", v16i8x_info, v64i8_info>; defm : mask_move_lowering<"VMOVDQU8Z", v32i8x_info, v64i8_info>; @@ -5021,8 +5021,8 @@ defm VPMINUD : avx512_binop_rm_vl_d<0x3B, "vpminud", umin, defm VPMINUQ : avx512_binop_rm_vl_q<0x3B, "vpminuq", umin, SchedWriteVecALU, HasAVX512, 1>, T8; -// PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX, HasEVEX512. -let Predicates = [HasDQI, NoVLX, HasEVEX512] in { +// PMULLQ: Use 512bit version to implement 128/256 bit in case NoVLX. +let Predicates = [HasDQI, NoVLX] in { def : Pat<(v4i64 (mul (v4i64 VR256X:$src1), (v4i64 VR256X:$src2))), (EXTRACT_SUBREG (VPMULLQZrr @@ -5078,7 +5078,7 @@ multiclass avx512_min_max_lowering { sub_xmm)>; } -let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { +let Predicates = [HasAVX512, NoVLX] in { defm : avx512_min_max_lowering<"VPMAXUQZ", umax>; defm : avx512_min_max_lowering<"VPMINUQZ", umin>; defm : avx512_min_max_lowering<"VPMAXSQZ", smax>; @@ -6055,7 +6055,7 @@ defm VPSRL : avx512_shift_types<0xD2, 0xD3, 0xD1, "vpsrl", X86vsrl, SchedWriteVecShift>; // Use 512bit VPSRA/VPSRAI version to implement v2i64/v4i64 in case NoVLX. -let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { +let Predicates = [HasAVX512, NoVLX] in { def : Pat<(v4i64 (X86vsra (v4i64 VR256X:$src1), (v2i64 VR128X:$src2))), (EXTRACT_SUBREG (v8i64 (VPSRAQZrr @@ -6184,14 +6184,14 @@ defm VPSRLV : avx512_var_shift_types<0x45, "vpsrlv", X86vsrlv, SchedWriteVarVecS defm VPRORV : avx512_var_shift_types<0x14, "vprorv", rotr, SchedWriteVarVecShift>; defm VPROLV : avx512_var_shift_types<0x15, "vprolv", rotl, SchedWriteVarVecShift>; -defm : avx512_var_shift_lowering; -defm : avx512_var_shift_lowering; -defm : avx512_var_shift_lowering; -defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; +defm : avx512_var_shift_lowering; // Use 512bit VPROL/VPROLI version to implement v2i64/v4i64 + v4i32/v8i32 in case NoVLX. -let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { +let Predicates = [HasAVX512, NoVLX] in { def : Pat<(v2i64 (rotl (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), (EXTRACT_SUBREG (v8i64 (VPROLVQZrr @@ -6242,7 +6242,7 @@ let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { } // Use 512bit VPROR/VPRORI version to implement v2i64/v4i64 + v4i32/v8i32 in case NoVLX. -let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { +let Predicates = [HasAVX512, NoVLX] in { def : Pat<(v2i64 (rotr (v2i64 VR128X:$src1), (v2i64 VR128X:$src2))), (EXTRACT_SUBREG (v8i64 (VPRORVQZrr @@ -9933,7 +9933,7 @@ defm VPMOVUSWB : avx512_trunc_wb<0x10, "vpmovuswb", X86vtruncus, truncstore_us_vi8, masked_truncstore_us_vi8, X86vtruncus, X86vmtruncus>; -let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { +let Predicates = [HasAVX512, NoVLX] in { def: Pat<(v8i16 (trunc (v8i32 VR256X:$src))), (v8i16 (EXTRACT_SUBREG (v16i16 (VPMOVDWZrr (v16i32 (INSERT_SUBREG (IMPLICIT_DEF), @@ -9944,7 +9944,7 @@ def: Pat<(v4i32 (trunc (v4i64 VR256X:$src))), VR256X:$src, sub_ymm)))), sub_xmm))>; } -let Predicates = [HasBWI, NoVLX, HasEVEX512] in { +let Predicates = [HasBWI, NoVLX] in { def: Pat<(v16i8 (trunc (v16i16 VR256X:$src))), (v16i8 (EXTRACT_SUBREG (VPMOVWBZrr (v32i16 (INSERT_SUBREG (IMPLICIT_DEF), VR256X:$src, sub_ymm))), sub_xmm))>; @@ -10487,7 +10487,7 @@ multiclass avx512_convert_vector_to_mask opc, string OpcodeStr, defm Z128 : convert_vector_to_mask_common, EVEX_V128; } - let Predicates = [prd, NoVLX, HasEVEX512] in { + let Predicates = [prd, NoVLX] in { defm Z256_Alt : convert_vector_to_mask_lowering; defm Z128_Alt : convert_vector_to_mask_lowering; } @@ -11283,7 +11283,7 @@ defm VPABS : avx512_unary_rm_vl_all<0x1C, 0x1D, 0x1E, 0x1F, "vpabs", abs, SchedWriteVecALU>; // VPABS: Use 512bit version to implement 128/256 bit in case NoVLX. -let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { +let Predicates = [HasAVX512, NoVLX] in { def : Pat<(v4i64 (abs VR256X:$src)), (EXTRACT_SUBREG (VPABSQZrr @@ -11299,7 +11299,7 @@ let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { // Use 512bit version to implement 128/256 bit. multiclass avx512_unary_lowering { - let Predicates = [prd, NoVLX, HasEVEX512] in { + let Predicates = [prd, NoVLX] in { def : Pat<(_.info256.VT (OpNode (_.info256.VT _.info256.RC:$src1))), (EXTRACT_SUBREG (!cast(InstrStr # "Zrr") @@ -11918,7 +11918,7 @@ let Predicates = [HasAVX512] in { (VPTERNLOGQZrri VR512:$src, VR512:$src, VR512:$src, (i8 15))>; } -let Predicates = [HasAVX512, NoVLX, HasEVEX512] in { +let Predicates = [HasAVX512, NoVLX] in { def : Pat<(v16i8 (vnot VR128X:$src)), (EXTRACT_SUBREG (VPTERNLOGQZrri diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td index df1541e9085bb..8a2846bcfdf34 100644 --- a/llvm/lib/Target/X86/X86InstrPredicates.td +++ b/llvm/lib/Target/X86/X86InstrPredicates.td @@ -69,11 +69,8 @@ def NoAVX : Predicate<"!Subtarget->hasAVX()">; def HasAVX : Predicate<"Subtarget->hasAVX()">; def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; -def HasEVEX512 : Predicate<"Subtarget->hasEVEX512()">; def HasAVX10_1 : Predicate<"Subtarget->hasAVX10_1()">; -def HasAVX10_1_512 : Predicate<"Subtarget->hasAVX10_1_512()">; def HasAVX10_2 : Predicate<"Subtarget->hasAVX10_2()">; -def HasAVX10_2_512 : Predicate<"Subtarget->hasAVX10_2_512()">; def NoAVX10_2 : Predicate<"!Subtarget->hasAVX10_2()">; def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index 3745c1e379b1b..fd5f34b60efb8 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -261,24 +261,6 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, if (!FS.empty()) FullFS = (Twine(FullFS) + "," + FS).str(); - // Attach EVEX512 feature when we have AVX512 features with a default CPU. - // "pentium4" is default CPU for 32-bit targets. - // "x86-64" is default CPU for 64-bit targets. - if (CPU == "generic" || CPU == "pentium4" || CPU == "x86-64") { - size_t posNoEVEX512 = FS.rfind("-evex512"); - // Make sure we won't be cheated by "-avx512fp16". - size_t posNoAVX512F = - FS.ends_with("-avx512f") ? FS.size() - 8 : FS.rfind("-avx512f,"); - size_t posEVEX512 = FS.rfind("+evex512"); - // Any AVX512XXX will enable AVX512F. - size_t posAVX512F = FS.rfind("+avx512"); - - if (posAVX512F != StringRef::npos && - (posNoAVX512F == StringRef::npos || posNoAVX512F < posAVX512F)) - if (posEVEX512 == StringRef::npos && posNoEVEX512 == StringRef::npos) - FullFS += ",+evex512"; - } - // Disable 64-bit only features in non-64-bit mode. StringRef FeaturesIn64BitOnly[] = { "egpr", "push2pop2", "ppx", "ndd", "ccmp", "nf", "cf", "zu", "uintr"}; diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index be49214e041ea..fa3f3b59741df 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -226,8 +226,7 @@ class X86Subtarget final : public X86GenSubtargetInfo { // TODO: Currently we're always allowing widening on CPUs without VLX, // because for many cases we don't have a better option. bool canExtendTo512DQ() const { - return hasAVX512() && hasEVEX512() && - (!hasVLX() || getPreferVectorWidth() >= 512); + return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512); } bool canExtendTo512BW() const { return hasBWI() && canExtendTo512DQ(); @@ -247,8 +246,7 @@ class X86Subtarget final : public X86GenSubtargetInfo { // If there are no 512-bit vectors and we prefer not to use 512-bit registers, // disable them in the legalizer. bool useAVX512Regs() const { - return hasAVX512() && hasEVEX512() && - (canExtendTo512DQ() || RequiredVectorWidth > 256); + return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256); } bool useLight256BitInstructions() const { diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 62f95277d0169..910c724a4e3aa 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -213,7 +213,7 @@ X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { case TargetTransformInfo::RGK_Scalar: return TypeSize::getFixed(ST->is64Bit() ? 64 : 32); case TargetTransformInfo::RGK_FixedWidthVector: - if (ST->hasAVX512() && ST->hasEVEX512() && PreferVectorWidth >= 512) + if (ST->hasAVX512() && PreferVectorWidth >= 512) return TypeSize::getFixed(512); if (ST->hasAVX() && PreferVectorWidth >= 256) return TypeSize::getFixed(256); @@ -6591,7 +6591,7 @@ X86TTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const { // Only enable vector loads for equality comparison. Right now the vector // version is not as fast for three way compare (see #33329). const unsigned PreferredWidth = ST->getPreferVectorWidth(); - if (PreferredWidth >= 512 && ST->hasAVX512() && ST->hasEVEX512()) + if (PreferredWidth >= 512 && ST->hasAVX512()) Options.LoadSizes.push_back(64); if (PreferredWidth >= 256 && ST->hasAVX()) Options.LoadSizes.push_back(32); if (PreferredWidth >= 128 && ST->hasSSE2()) Options.LoadSizes.push_back(16); diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index 24827537eb19c..63848160636a2 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -1396,7 +1396,6 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf, setFeature(X86::FEATURE_BMI2); if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save) { setFeature(X86::FEATURE_AVX512F); - setFeature(X86::FEATURE_EVEX512); } if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save) setFeature(X86::FEATURE_AVX512DQ); @@ -2063,8 +2062,6 @@ StringMap sys::getHostCPUFeatures() { Features["rtm"] = HasLeaf7 && ((EBX >> 11) & 1); // AVX512 is only supported if the OS supports the context save for it. Features["avx512f"] = HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save; - if (Features["avx512f"]) - Features["evex512"] = true; Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save; Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1); Features["adx"] = HasLeaf7 && ((EBX >> 19) & 1); @@ -2176,11 +2173,8 @@ StringMap sys::getHostCPUFeatures() { MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX); int AVX10Ver = HasLeaf24 && (EBX & 0xff); - int Has512Len = HasLeaf24 && ((EBX >> 18) & 1); - Features["avx10.1-256"] = HasAVX10 && AVX10Ver >= 1; - Features["avx10.1-512"] = HasAVX10 && AVX10Ver >= 1 && Has512Len; - Features["avx10.2-256"] = HasAVX10 && AVX10Ver >= 2; - Features["avx10.2-512"] = HasAVX10 && AVX10Ver >= 2 && Has512Len; + Features["avx10.1"] = HasAVX10 && AVX10Ver >= 1; + Features["avx10.2"] = HasAVX10 && AVX10Ver >= 2; return Features; } diff --git a/llvm/lib/TargetParser/X86TargetParser.cpp b/llvm/lib/TargetParser/X86TargetParser.cpp index b72096553ad9b..edca7c18062ae 100644 --- a/llvm/lib/TargetParser/X86TargetParser.cpp +++ b/llvm/lib/TargetParser/X86TargetParser.cpp @@ -72,7 +72,7 @@ constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF | constexpr FeatureBitset FeaturesX86_64_V3 = FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C | FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE; -constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | FeatureEVEX512 | +constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | FeatureAVX512BW | FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512VL; @@ -95,9 +95,8 @@ constexpr FeatureBitset FeaturesBroadwell = // Intel Knights Landing and Knights Mill // Knights Landing has feature parity with Broadwell. -constexpr FeatureBitset FeaturesKNL = FeaturesBroadwell | FeatureAES | - FeatureAVX512F | FeatureEVEX512 | - FeatureAVX512CD; +constexpr FeatureBitset FeaturesKNL = + FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD; constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ; // Intel Skylake processors. @@ -107,9 +106,9 @@ constexpr FeatureBitset FeaturesSkylakeClient = // SkylakeServer inherits all SkylakeClient features except SGX. // FIXME: That doesn't match gcc. constexpr FeatureBitset FeaturesSkylakeServer = - (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureEVEX512 | - FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | - FeatureCLWB | FeaturePKU; + (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | + FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | + FeaturePKU; constexpr FeatureBitset FeaturesCascadeLake = FeaturesSkylakeServer | FeatureAVX512VNNI; constexpr FeatureBitset FeaturesCooperLake = @@ -117,9 +116,9 @@ constexpr FeatureBitset FeaturesCooperLake = // Intel 10nm processors. constexpr FeatureBitset FeaturesCannonlake = - FeaturesSkylakeClient | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD | - FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | - FeatureAVX512VBMI | FeaturePKU | FeatureSHA; + FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | + FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | + FeaturePKU | FeatureSHA; constexpr FeatureBitset FeaturesICLClient = FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID | @@ -139,7 +138,7 @@ constexpr FeatureBitset FeaturesSapphireRapids = constexpr FeatureBitset FeaturesGraniteRapids = FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI; constexpr FeatureBitset FeaturesDiamondRapids = - FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2_512 | + FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2 | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureAVXNECONVERT | FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 | @@ -244,11 +243,10 @@ static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 | FeatureINVPCID | FeaturePKU | FeatureVAES | FeatureVPCLMULQDQ; static constexpr FeatureBitset FeaturesZNVER4 = - FeaturesZNVER3 | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD | - FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | - FeatureAVX512VBMI | FeatureAVX512VBMI2 | FeatureAVX512VNNI | - FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | - FeatureGFNI | FeatureSHSTK; + FeaturesZNVER3 | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | + FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | + FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512BITALG | + FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | FeatureGFNI | FeatureSHSTK; static constexpr FeatureBitset FeaturesZNVER5 = FeaturesZNVER4 | FeatureAVXVNNI | FeatureMOVDIRI | FeatureMOVDIR64B | @@ -394,7 +392,7 @@ constexpr ProcInfo Processors[] = { // Clearwaterforest microarchitecture based processors. { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false }, // Diamond Rapids microarchitecture based processors. - { {"diamondrapids"}, CK_Diamondrapids, FEATURE_AVX10_2_512, FeaturesDiamondRapids, 'z', false }, + { {"diamondrapids"}, CK_Diamondrapids, FEATURE_AVX10_2, FeaturesDiamondRapids, 'z', false }, // Knights Landing processor. { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false }, { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true }, @@ -616,7 +614,7 @@ constexpr FeatureBitset ImpliedFeaturesAMX_FP8 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_TRANSPOSE = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_MOVRS = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_AVX512 = - FeatureAMX_TILE | FeatureAVX10_2_512; + FeatureAMX_TILE | FeatureAVX10_2; constexpr FeatureBitset ImpliedFeaturesAMX_TF32 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesHRESET = {}; @@ -642,11 +640,9 @@ constexpr FeatureBitset ImpliedFeaturesAVX10_1 = FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ | FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureAVX512FP16 | FeatureAVX512DQ | FeatureAVX512VL; -constexpr FeatureBitset ImpliedFeaturesAVX10_1_512 = - FeatureAVX10_1 | FeatureEVEX512; constexpr FeatureBitset ImpliedFeaturesAVX10_2 = FeatureAVX10_1; -constexpr FeatureBitset ImpliedFeaturesAVX10_2_512 = - FeatureAVX10_2 | FeatureAVX10_1_512; +constexpr FeatureBitset ImpliedFeaturesAVX10_1_512 = FeatureAVX10_1; +constexpr FeatureBitset ImpliedFeaturesAVX10_2_512 = FeatureAVX10_2; // APX Features constexpr FeatureBitset ImpliedFeaturesEGPR = {}; diff --git a/llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll b/llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll index 71f8f231747fe..885bc805d6552 100644 --- a/llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll +++ b/llvm/test/CodeGen/X86/amx-across-func-tilemovrow.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2-512 -mattr=+amx-avx512 -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2-512 -mattr=+amx-avx512 -verify-machineinstrs -enable-ipra | FileCheck -check-prefix=IPRA %s -; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2-512 -mattr=+amx-avx512 -verify-machineinstrs | FileCheck -check-prefix=O0 %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2 -mattr=+amx-avx512 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2 -mattr=+amx-avx512 -verify-machineinstrs -enable-ipra | FileCheck -check-prefix=IPRA %s +; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-int8 -mattr=+avx10.2 -mattr=+amx-avx512 -verify-machineinstrs | FileCheck -check-prefix=O0 %s @buf = dso_local global [3072 x i8] zeroinitializer, align 64 diff --git a/llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll b/llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll index 8f82bd2587ec3..41208d6adb300 100644 --- a/llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll +++ b/llvm/test/CodeGen/X86/amx-avx512-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+amx-tile,+amx-avx512,+avx10.2-512 | FileCheck %s +; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+amx-tile,+amx-avx512,+avx10.2 | FileCheck %s define <16 x float> @test_tcvtrowd2ps(i32 %A) { ; CHECK-LABEL: test_tcvtrowd2ps: diff --git a/llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll b/llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll index fd3925fabc513..dc8252ae7aca1 100644 --- a/llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll +++ b/llvm/test/CodeGen/X86/amx-tile-avx512-internals.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx10.2-512, \ +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-bf16,+avx10.2, \ ; RUN: -mattr=+amx-avx512 -verify-machineinstrs | FileCheck %s define void @test_amx(i8* %pointer, i8* %base, i32 %index, i64 %stride) { diff --git a/llvm/test/CodeGen/X86/avx10.2-fma-commute.ll b/llvm/test/CodeGen/X86/avx10.2-fma-commute.ll index ab8ac4fbd4193..b43b1f7b9c32b 100644 --- a/llvm/test/CodeGen/X86/avx10.2-fma-commute.ll +++ b/llvm/test/CodeGen/X86/avx10.2-fma-commute.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s --mtriple=x86_64-unknown-unknown -mattr=avx10.2-512 | FileCheck %s +; RUN: llc < %s --mtriple=x86_64-unknown-unknown -mattr=avx10.2 | FileCheck %s define <8 x bfloat> @fma_123_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y, <8 x bfloat> %z) { ; CHECK-LABEL: fma_123_v8bf16: diff --git a/llvm/test/CodeGen/X86/avx10_2-cmp.ll b/llvm/test/CodeGen/X86/avx10_2-cmp.ll index 0f90f1a0a3561..566ce533683f7 100644 --- a/llvm/test/CodeGen/X86/avx10_2-cmp.ll +++ b/llvm/test/CodeGen/X86/avx10_2-cmp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefix=X64 -; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefix=X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2 | FileCheck %s --check-prefix=X64 +; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+avx10.2 | FileCheck %s --check-prefix=X86 define i1 @hoeq(half %x, half %y) { ; X64-LABEL: hoeq: diff --git a/llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll b/llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll index c22a394e6c4e0..79849a7153c91 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512bf16-arith.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 define <32 x bfloat> @test_int_x86_avx10_vaddbf16512(<32 x bfloat> %x1, <32 x bfloat> %x2) { ; CHECK-LABEL: test_int_x86_avx10_vaddbf16512: diff --git a/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll index cbac76e9de273..9225bd88b0896 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512bf16-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 declare <32 x bfloat> @llvm.x86.avx10.vminbf16512(<32 x bfloat>, <32 x bfloat>) diff --git a/llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll index c4a904cc3bc41..cc87ae0aad1f5 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512convert-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 define <32 x half> @test_int_x86_avx10_vcvt2ps2phx512(<16 x float> %A, <16 x float> %B) { ; CHECK-LABEL: test_int_x86_avx10_vcvt2ps2phx512: diff --git a/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll b/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll index d7ad7b048c6d6..c50da22193b20 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512fptosi_satcvtds.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X86 -; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 ; VCVTTPD2DQS define <8 x i32> @test_signed_v8i32_v8f64(<8 x double> %f) nounwind { diff --git a/llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll index b7713128f4721..c27ee1680dea3 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512minmax-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=X86 define <32 x bfloat> @test_int_x86_avx10_vminmaxbf16512(<32 x bfloat> %A, <32 x bfloat> %B) nounwind { ; X64-LABEL: test_int_x86_avx10_vminmaxbf16512: diff --git a/llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll index b2e7caa15944c..09eb53faaaada 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx10.2-512 --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-512 --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx10.2 --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2 --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64 ; VNNI FP16 diff --git a/llvm/test/CodeGen/X86/avx10_2_512satcvt-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512satcvt-intrinsics.ll index 8430b2e1c028d..2e69b41d282b5 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512satcvt-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512satcvt-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64 --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686 --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64 --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686 --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 define dso_local <8 x i64> @test_mm512_ipcvtbf16_epi8(<32 x bfloat> noundef %__A) { ; CHECK-LABEL: test_mm512_ipcvtbf16_epi8: diff --git a/llvm/test/CodeGen/X86/avx10_2_512satcvtds-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2_512satcvtds-intrinsics.ll index 652c35c777091..591349aabef45 100644 --- a/llvm/test/CodeGen/X86/avx10_2_512satcvtds-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2_512satcvtds-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-512 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 define <8 x i32> @test_int_x86_mask_vcvtt_pd2dqs_512(<8 x double> %x0, <8 x i32> %src, i8 %mask) { diff --git a/llvm/test/CodeGen/X86/avx10_2bf16-arith.ll b/llvm/test/CodeGen/X86/avx10_2bf16-arith.ll index 435f67a0f1e4b..0f2c75b15d5b4 100644 --- a/llvm/test/CodeGen/X86/avx10_2bf16-arith.ll +++ b/llvm/test/CodeGen/X86/avx10_2bf16-arith.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 define <16 x bfloat> @test_int_x86_avx10_add_bf16_256(<16 x bfloat> %x1, <16 x bfloat> %x2) { ; CHECK-LABEL: test_int_x86_avx10_add_bf16_256: @@ -1168,23 +1168,10 @@ entry: } define <32 x bfloat> @addv(<32 x bfloat> %a, <32 x bfloat> %b) nounwind { -; X64-LABEL: addv: -; X64: # %bb.0: -; X64-NEXT: vaddbf16 %ymm2, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7d,0x28,0x58,0xc2] -; X64-NEXT: vaddbf16 %ymm3, %ymm1, %ymm1 # encoding: [0x62,0xf5,0x75,0x28,0x58,0xcb] -; X64-NEXT: retq # encoding: [0xc3] -; -; X86-LABEL: addv: -; X86: # %bb.0: -; X86-NEXT: pushl %ebp # encoding: [0x55] -; X86-NEXT: movl %esp, %ebp # encoding: [0x89,0xe5] -; X86-NEXT: andl $-32, %esp # encoding: [0x83,0xe4,0xe0] -; X86-NEXT: subl $32, %esp # encoding: [0x83,0xec,0x20] -; X86-NEXT: vaddbf16 %ymm2, %ymm0, %ymm0 # encoding: [0x62,0xf5,0x7d,0x28,0x58,0xc2] -; X86-NEXT: vaddbf16 8(%ebp), %ymm1, %ymm1 # encoding: [0x62,0xf5,0x75,0x28,0x58,0x8d,0x08,0x00,0x00,0x00] -; X86-NEXT: movl %ebp, %esp # encoding: [0x89,0xec] -; X86-NEXT: popl %ebp # encoding: [0x5d] -; X86-NEXT: retl # encoding: [0xc3] +; CHECK-LABEL: addv: +; CHECK: # %bb.0: +; CHECK-NEXT: vaddbf16 %zmm1, %zmm0, %zmm0 # encoding: [0x62,0xf5,0x7d,0x48,0x58,0xc1] +; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] %add = fadd <32 x bfloat> %a, %b ret <32 x bfloat> %add } diff --git a/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll index ba32b2adc7999..3efc8cc3d1290 100644 --- a/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2bf16-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 declare <16 x bfloat> @llvm.x86.avx10.vminbf16256(<16 x bfloat>, <16 x bfloat>) diff --git a/llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll index 90e2146cc2c0b..04c93eb1ee6d0 100644 --- a/llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2convert-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 define <8 x half> @test_int_x86_avx10_vcvt2ps2phx128(<4 x float> %A, <4 x float> %B) { ; CHECK-LABEL: test_int_x86_avx10_vcvt2ps2phx128: diff --git a/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll b/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll index a2f167e94cc23..e0c2139b5e37e 100644 --- a/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll +++ b/llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X86 -; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -mtriple=i686-linux -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 ; ; 32-bit float to signed integer diff --git a/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll index 916d439ab77f0..8ae5b670764e2 100644 --- a/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2minmax-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=X86 define <8 x bfloat> @test_int_x86_avx10_vminmaxbf16128(<8 x bfloat> %A, <8 x bfloat> %B) nounwind { ; X64-LABEL: test_int_x86_avx10_vminmaxbf16128: diff --git a/llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll index ed5ae01448c59..0c5fd3bf9d241 100644 --- a/llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx10.2-256 --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx10.2 --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2 --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64 ; VNNI FP16 diff --git a/llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll index 957523f87b7c3..094637270503d 100644 --- a/llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2satcvt-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64 --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686 --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64 --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686 --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 define dso_local <2 x i64> @test_mm_ipcvtbf16_epi8(<8 x bfloat> noundef %__A) { ; CHECK-LABEL: test_mm_ipcvtbf16_epi8: diff --git a/llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll index e9b739074b453..38d54cff6dc23 100644 --- a/llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2satcvtds-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X64 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=CHECK,X86 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=CHECK,X86 define i32 @test_x86_avx512_vcvttsd2usis(<2 x double> %a0) { ; CHECK-LABEL: test_x86_avx512_vcvttsd2usis: diff --git a/llvm/test/CodeGen/X86/avx10_2satcvtds-x64-intrinsics.ll b/llvm/test/CodeGen/X86/avx10_2satcvtds-x64-intrinsics.ll index f5be929bc85ce..c853da5d2168b 100644 --- a/llvm/test/CodeGen/X86/avx10_2satcvtds-x64-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx10_2satcvtds-x64-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3 -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s define i64 @test_x86_avx512_vcvttsd2si64(<2 x double> %a0) { ; CHECK-LABEL: test_x86_avx512_vcvttsd2si64: diff --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll index 33819c9e01027..97ca0d88b7d4d 100644 --- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll +++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll @@ -1,6 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,EVEX512 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,-evex512 | FileCheck %s --check-prefixes=CHECK,EVEX256 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK ; 256-bit @@ -237,32 +236,19 @@ define <8 x i16> @vpmullw128_test(<8 x i16> %i, <8 x i16> %j) { } define i16 @PR90356(<16 x i1> %a) { -; EVEX512-LABEL: PR90356: -; EVEX512: # %bb.0: -; EVEX512-NEXT: vpsllw $7, %xmm0, %xmm0 -; EVEX512-NEXT: vpmovb2m %xmm0, %k1 -; EVEX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; EVEX512-NEXT: movb $63, %al -; EVEX512-NEXT: kmovd %eax, %k1 -; EVEX512-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} -; EVEX512-NEXT: vptestmd %zmm0, %zmm0, %k0 -; EVEX512-NEXT: kmovd %k0, %eax -; EVEX512-NEXT: # kill: def $ax killed $ax killed $eax -; EVEX512-NEXT: vzeroupper -; EVEX512-NEXT: retq -; -; EVEX256-LABEL: PR90356: -; EVEX256: # %bb.0: -; EVEX256-NEXT: vpsllw $7, %xmm0, %xmm0 -; EVEX256-NEXT: vpmovb2m %xmm0, %k0 -; EVEX256-NEXT: vpmovm2w %k0, %ymm0 -; EVEX256-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; EVEX256-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7] -; EVEX256-NEXT: vpmovw2m %ymm0, %k0 -; EVEX256-NEXT: kmovd %k0, %eax -; EVEX256-NEXT: # kill: def $ax killed $ax killed $eax -; EVEX256-NEXT: vzeroupper -; EVEX256-NEXT: retq +; CHECK-LABEL: PR90356: +; CHECK: # %bb.0: +; CHECK-NEXT: vpsllw $7, %xmm0, %xmm0 +; CHECK-NEXT: vpmovb2m %xmm0, %k1 +; CHECK-NEXT: vpternlogd {{.*#+}} zmm0 {%k1} {z} = -1 +; CHECK-NEXT: movb $63, %al +; CHECK-NEXT: kmovd %eax, %k1 +; CHECK-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} +; CHECK-NEXT: vptestmd %zmm0, %zmm0, %k0 +; CHECK-NEXT: kmovd %k0, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax +; CHECK-NEXT: vzeroupper +; CHECK-NEXT: retq %1 = shufflevector <16 x i1> %a, <16 x i1> zeroinitializer, <16 x i32> %2 = bitcast <16 x i1> %1 to i16 ret i16 %2 diff --git a/llvm/test/CodeGen/X86/avx512copy-intrinsics.ll b/llvm/test/CodeGen/X86/avx512copy-intrinsics.ll index a2af7df44010e..d09807e4a3346 100644 --- a/llvm/test/CodeGen/X86/avx512copy-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512copy-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=AVX102 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefixes=AVX102 ; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx512f | FileCheck %s --check-prefixes=NOAVX512MOVZXC define <4 x i32> @test_mm_move_epi32(<4 x i32> %a0) nounwind { diff --git a/llvm/test/CodeGen/X86/avxvnniint16-intrinsics.ll b/llvm/test/CodeGen/X86/avxvnniint16-intrinsics.ll index 8601d454215ad..abdc296ae1e1c 100644 --- a/llvm/test/CodeGen/X86/avxvnniint16-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avxvnniint16-intrinsics.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avxvnniint16 | FileCheck %s ; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avxvnniint16 | FileCheck %s -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefix=AVX10 -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2-256 | FileCheck %s --check-prefix=AVX10 +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefix=AVX10 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+avx10.2 | FileCheck %s --check-prefix=AVX10 define <4 x i32> @test_int_x86_avx2_vpdpwsud_128(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) { ; CHECK-LABEL: test_int_x86_avx2_vpdpwsud_128: diff --git a/llvm/test/CodeGen/X86/avxvnniint8-intrinsics.ll b/llvm/test/CodeGen/X86/avxvnniint8-intrinsics.ll index 607720fbc3f33..0ddd0171a58a0 100644 --- a/llvm/test/CodeGen/X86/avxvnniint8-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avxvnniint8-intrinsics.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avxvnniint8 --show-mc-encoding | FileCheck %s --check-prefixes=X86 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avxvnniint8 --show-mc-encoding | FileCheck %s --check-prefixes=X64 -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx10.2-256 --show-mc-encoding | FileCheck %s --check-prefixes=AVX10-X86 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 --show-mc-encoding | FileCheck %s --check-prefixes=AVX10-X64 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx10.2 --show-mc-encoding | FileCheck %s --check-prefixes=AVX10-X86 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2 --show-mc-encoding | FileCheck %s --check-prefixes=AVX10-X64 declare <4 x i32> @llvm.x86.avx2.vpdpbssd.128(<4 x i32>, <4 x i32>, <4 x i32>) diff --git a/llvm/test/CodeGen/X86/comi-flags.ll b/llvm/test/CodeGen/X86/comi-flags.ll index 6f520aa57dcd0..805b1b54d5b6e 100644 --- a/llvm/test/CodeGen/X86/comi-flags.ll +++ b/llvm/test/CodeGen/X86/comi-flags.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,NO-AVX10_2 -; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=AVX,AVX10_2 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx10.2 | FileCheck %s --check-prefixes=AVX,AVX10_2 ; ; SSE diff --git a/llvm/test/CodeGen/X86/evex512-mem.ll b/llvm/test/CodeGen/X86/evex512-mem.ll deleted file mode 100644 index 85bb3b3a5487f..0000000000000 --- a/llvm/test/CodeGen/X86/evex512-mem.ll +++ /dev/null @@ -1,29 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f,avx512bw,avx512vl < %s | FileCheck %s --check-prefix=AVX512 -; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx512f,avx512bw,avx512vl,-evex512 < %s | FileCheck %s --check-prefix=AVX256 - -define void @test1() { -; AVX512-LABEL: test1: -; AVX512: # %bb.0: -; AVX512-NEXT: movq 64, %rax -; AVX512-NEXT: movq %rax, (%rax) -; AVX512-NEXT: vmovups 0, %zmm0 -; AVX512-NEXT: vmovups %zmm0, (%rax) -; AVX512-NEXT: vzeroupper -; AVX512-NEXT: retq -; -; AVX256-LABEL: test1: -; AVX256: # %bb.0: -; AVX256-NEXT: movq 64, %rax -; AVX256-NEXT: movq %rax, (%rax) -; AVX256-NEXT: vmovups 0, %ymm0 -; AVX256-NEXT: vmovups 32, %ymm1 -; AVX256-NEXT: vmovups %ymm1, (%rax) -; AVX256-NEXT: vmovups %ymm0, (%rax) -; AVX256-NEXT: vzeroupper -; AVX256-NEXT: retq - call void @llvm.memcpy.p0.p0.i64(ptr align 8 poison, ptr align 8 null, i64 72, i1 false) - ret void -} - -declare void @llvm.memcpy.p0.p0.i64(ptr, ptr, i64, i1) diff --git a/llvm/test/CodeGen/X86/fminimum-fmaximum.ll b/llvm/test/CodeGen/X86/fminimum-fmaximum.ll index 989aabc9e87bd..864c2336f37c2 100644 --- a/llvm/test/CodeGen/X86/fminimum-fmaximum.ll +++ b/llvm/test/CodeGen/X86/fminimum-fmaximum.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=AVX,AVX512,AVX512DQ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=AVX10_2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2 | FileCheck %s --check-prefixes=AVX10_2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86 declare float @llvm.maximum.f32(float, float) diff --git a/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll b/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll index eef87b5a9f85a..54d82b0c1c929 100644 --- a/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll +++ b/llvm/test/CodeGen/X86/fminimumnum-fmaximumnum.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=AVX,AVX512,AVX512DQ -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-256 | FileCheck %s --check-prefixes=AVX10_2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2 | FileCheck %s --check-prefixes=AVX10_2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=X86 declare float @llvm.maximumnum.f32(float, float) diff --git a/llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll b/llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll index a730ef519c015..a478577155f16 100644 --- a/llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll +++ b/llvm/test/CodeGen/X86/movrs-avx10.2-512-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-- -mattr=+movrs,+avx10.2-512 -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK +; RUN: llc < %s -mtriple=x86_64-- -mattr=+movrs,+avx10.2 -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK declare <64 x i8> @llvm.x86.avx10.vmovrsb512(ptr) declare <16 x i32> @llvm.x86.avx10.vmovrsd512(ptr) diff --git a/llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll b/llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll index 583e16351652b..62613d773a360 100644 --- a/llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll +++ b/llvm/test/CodeGen/X86/movrs-avx10.2-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-- -mattr=+movrs,+avx10.2-256 -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK +; RUN: llc < %s -mtriple=x86_64-- -mattr=+movrs,+avx10.2 -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefixes=CHECK define <2 x i64> @test_mm_movrsb_epu8(ptr %__A) { ; CHECK-LABEL: test_mm_movrsb_epu8: diff --git a/llvm/test/CodeGen/X86/pr90844.ll b/llvm/test/CodeGen/X86/pr90844.ll deleted file mode 100644 index b250c3f6f9a2e..0000000000000 --- a/llvm/test/CodeGen/X86/pr90844.ll +++ /dev/null @@ -1,36 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 -; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512f,-evex512 < %s | FileCheck %s - -define void @PR90844() { -; CHECK-LABEL: PR90844: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0 -; CHECK-NEXT: vmovaps %xmm0, (%rax) -; CHECK-NEXT: retq -entry: - %0 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> poison, <2 x i32> poison, <2 x i32> ) - %1 = and <2 x i32> %0, - %2 = or disjoint <2 x i32> zeroinitializer, %1 - %3 = zext <2 x i32> %2 to <2 x i64> - %4 = shl nuw <2 x i64> %3, - %5 = or disjoint <2 x i64> %4, zeroinitializer - store <2 x i64> %5, ptr poison, align 16 - ret void -} - -define void @foo(ptr %0) { -; CHECK-LABEL: foo: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vpbroadcastw {{.*#+}} ymm0 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0] -; CHECK-NEXT: vpxor 32(%rdi), %ymm0, %ymm1 -; CHECK-NEXT: vpxor (%rdi), %ymm0, %ymm0 -; CHECK-NEXT: vmovdqa %ymm0, (%rdi) -; CHECK-NEXT: vmovdqa %ymm1, 32(%rdi) -; CHECK-NEXT: vzeroupper -; CHECK-NEXT: retq -entry: - %1 = load <32 x half>, ptr %0 - %2 = fneg <32 x half> %1 - store <32 x half> %2, ptr %0 - ret void -} diff --git a/llvm/test/CodeGen/X86/sm4-evex-intrinsics.ll b/llvm/test/CodeGen/X86/sm4-evex-intrinsics.ll index 825a11d66cd45..8d99ad07e22e6 100644 --- a/llvm/test/CodeGen/X86/sm4-evex-intrinsics.ll +++ b/llvm/test/CodeGen/X86/sm4-evex-intrinsics.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-- --show-mc-encoding -mattr=+sm4,+avx10.2-512 | FileCheck %s -; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- --show-mc-encoding -mattr=+sm4,+avx10.2-512 | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-- --show-mc-encoding -mattr=+sm4,+avx10.2 | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-- --show-mc-encoding -mattr=+sm4,+avx10.2 | FileCheck %s define <4 x i32> @test_int_x86_vsm4key4128(<4 x i32> %A, <4 x i32> %B) { ; CHECK-LABEL: test_int_x86_vsm4key4128: diff --git a/llvm/test/CodeGen/X86/vector-fshl-128.ll b/llvm/test/CodeGen/X86/vector-fshl-128.ll index 6b8a03ba5eb76..762900e0bb18d 100644 --- a/llvm/test/CodeGen/X86/vector-fshl-128.ll +++ b/llvm/test/CodeGen/X86/vector-fshl-128.ll @@ -9,8 +9,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2 | FileCheck %s --check-prefixes=AVX512VBMI2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512VLBW ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2,+avx512vl | FileCheck %s --check-prefixes=AVX512VLVBMI2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-256 | FileCheck %s --check-prefixes=AVX512VLVBMI2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-512 | FileCheck %s --check-prefixes=AVX512VLVBMI2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1 | FileCheck %s --check-prefixes=AVX512VLVBMI2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefixes=XOP,XOPAVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefixes=XOP,XOPAVX2 diff --git a/llvm/test/CodeGen/X86/vector-fshl-256.ll b/llvm/test/CodeGen/X86/vector-fshl-256.ll index 6fbc10307e0bb..0b98a9388adc1 100644 --- a/llvm/test/CodeGen/X86/vector-fshl-256.ll +++ b/llvm/test/CodeGen/X86/vector-fshl-256.ll @@ -6,9 +6,8 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512BW ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2 | FileCheck %s --check-prefixes=AVX512VBMI2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512VLBW -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2,+avx512vl | FileCheck %s --check-prefixes=AVX10,AVX512VLVBMI2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-256 | FileCheck %s --check-prefixes=AVX10,AVX10_256 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-512 | FileCheck %s --check-prefixes=AVX10,AVX512VLVBMI2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2,+avx512vl | FileCheck %s --check-prefixes=AVX512VLVBMI2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1 | FileCheck %s --check-prefixes=AVX512VLVBMI2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefixes=XOPAVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefixes=XOPAVX2 @@ -118,10 +117,10 @@ define <4 x i64> @var_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %amt) ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: var_funnnel_v4i64: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldvq %ymm2, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: var_funnnel_v4i64: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldvq %ymm2, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: var_funnnel_v4i64: ; XOPAVX1: # %bb.0: @@ -273,10 +272,10 @@ define <8 x i32> @var_funnnel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %amt) ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: var_funnnel_v8i32: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldvd %ymm2, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: var_funnnel_v8i32: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldvd %ymm2, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: var_funnnel_v8i32: ; XOPAVX1: # %bb.0: @@ -426,10 +425,10 @@ define <16 x i16> @var_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> % ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: var_funnnel_v16i16: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldvw %ymm2, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: var_funnnel_v16i16: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldvw %ymm2, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: var_funnnel_v16i16: ; XOPAVX1: # %bb.0: @@ -680,34 +679,6 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt) ; AVX512VLBW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX512VLVBMI2-LABEL: var_funnnel_v32i8: -; AVX512VLVBMI2: # %bb.0: -; AVX512VLVBMI2-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 -; AVX512VLVBMI2-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512VLVBMI2-NEXT: vmovdqa64 {{.*#+}} zmm3 = [0,64,1,65,2,66,3,67,4,68,5,69,6,70,7,71,8,72,9,73,10,74,11,75,12,76,13,77,14,78,15,79,16,80,17,81,18,82,19,83,20,84,21,85,22,86,23,87,24,88,25,89,26,90,27,91,28,92,29,93,30,94,31,95] -; AVX512VLVBMI2-NEXT: vpermi2b %zmm0, %zmm1, %zmm3 -; AVX512VLVBMI2-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm0 -; AVX512VLVBMI2-NEXT: vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero -; AVX512VLVBMI2-NEXT: vpsllvw %zmm0, %zmm3, %zmm0 -; AVX512VLVBMI2-NEXT: vpsrlw $8, %zmm0, %zmm0 -; AVX512VLVBMI2-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512VLVBMI2-NEXT: retq -; -; AVX10_256-LABEL: var_funnnel_v32i8: -; AVX10_256: # %bb.0: -; AVX10_256-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] -; AVX10_256-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2 -; AVX10_256-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; AVX10_256-NEXT: vpunpckhbw {{.*#+}} ymm5 = ymm2[8],ymm4[8],ymm2[9],ymm4[9],ymm2[10],ymm4[10],ymm2[11],ymm4[11],ymm2[12],ymm4[12],ymm2[13],ymm4[13],ymm2[14],ymm4[14],ymm2[15],ymm4[15],ymm2[24],ymm4[24],ymm2[25],ymm4[25],ymm2[26],ymm4[26],ymm2[27],ymm4[27],ymm2[28],ymm4[28],ymm2[29],ymm4[29],ymm2[30],ymm4[30],ymm2[31],ymm4[31] -; AVX10_256-NEXT: vpsllvw %ymm5, %ymm3, %ymm3 -; AVX10_256-NEXT: vpsrlw $8, %ymm3, %ymm3 -; AVX10_256-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23] -; AVX10_256-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm2[0],ymm4[0],ymm2[1],ymm4[1],ymm2[2],ymm4[2],ymm2[3],ymm4[3],ymm2[4],ymm4[4],ymm2[5],ymm4[5],ymm2[6],ymm4[6],ymm2[7],ymm4[7],ymm2[16],ymm4[16],ymm2[17],ymm4[17],ymm2[18],ymm4[18],ymm2[19],ymm4[19],ymm2[20],ymm4[20],ymm2[21],ymm4[21],ymm2[22],ymm4[22],ymm2[23],ymm4[23] -; AVX10_256-NEXT: vpsllvw %ymm1, %ymm0, %ymm0 -; AVX10_256-NEXT: vpsrlw $8, %ymm0, %ymm0 -; AVX10_256-NEXT: vpackuswb %ymm3, %ymm0, %ymm0 -; AVX10_256-NEXT: retq -; ; XOPAVX1-LABEL: var_funnnel_v32i8: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm1, %xmm3 @@ -840,11 +811,11 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> % ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatvar_funnnel_v4i64: -; AVX10: # %bb.0: -; AVX10-NEXT: vpbroadcastq %xmm2, %ymm2 -; AVX10-NEXT: vpshldvq %ymm2, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatvar_funnnel_v4i64: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpbroadcastq %xmm2, %ymm2 +; AVX512VLVBMI2-NEXT: vpshldvq %ymm2, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_funnnel_v4i64: ; XOPAVX1: # %bb.0: @@ -957,11 +928,11 @@ define <8 x i32> @splatvar_funnnel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> % ; AVX512VLBW-NEXT: vshufps {{.*#+}} ymm0 = ymm0[1,3],ymm3[1,3],ymm0[5,7],ymm3[5,7] ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatvar_funnnel_v8i32: -; AVX10: # %bb.0: -; AVX10-NEXT: vpbroadcastd %xmm2, %ymm2 -; AVX10-NEXT: vpshldvd %ymm2, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatvar_funnnel_v8i32: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpbroadcastd %xmm2, %ymm2 +; AVX512VLVBMI2-NEXT: vpshldvd %ymm2, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_funnnel_v8i32: ; XOPAVX1: # %bb.0: @@ -1078,11 +1049,11 @@ define <16 x i16> @splatvar_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatvar_funnnel_v16i16: -; AVX10: # %bb.0: -; AVX10-NEXT: vpbroadcastw %xmm2, %ymm2 -; AVX10-NEXT: vpshldvw %ymm2, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatvar_funnnel_v16i16: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpbroadcastw %xmm2, %ymm2 +; AVX512VLVBMI2-NEXT: vpshldvw %ymm2, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_funnnel_v16i16: ; XOPAVX1: # %bb.0: @@ -1212,17 +1183,17 @@ define <32 x i8> @splatvar_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> % ; AVX512VLBW-NEXT: vpackuswb %ymm3, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatvar_funnnel_v32i8: -; AVX10: # %bb.0: -; AVX10-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] -; AVX10-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 -; AVX10-NEXT: vpsllw %xmm2, %ymm3, %ymm3 -; AVX10-NEXT: vpsrlw $8, %ymm3, %ymm3 -; AVX10-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23] -; AVX10-NEXT: vpsllw %xmm2, %ymm0, %ymm0 -; AVX10-NEXT: vpsrlw $8, %ymm0, %ymm0 -; AVX10-NEXT: vpackuswb %ymm3, %ymm0, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatvar_funnnel_v32i8: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] +; AVX512VLVBMI2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 +; AVX512VLVBMI2-NEXT: vpsllw %xmm2, %ymm3, %ymm3 +; AVX512VLVBMI2-NEXT: vpsrlw $8, %ymm3, %ymm3 +; AVX512VLVBMI2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23] +; AVX512VLVBMI2-NEXT: vpsllw %xmm2, %ymm0, %ymm0 +; AVX512VLVBMI2-NEXT: vpsrlw $8, %ymm0, %ymm0 +; AVX512VLVBMI2-NEXT: vpackuswb %ymm3, %ymm0, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_funnnel_v32i8: ; XOPAVX1: # %bb.0: @@ -1452,25 +1423,25 @@ define void @fancierRotate2(ptr %arr, ptr %control, i32 %rot0, i32 %rot1) { ; AVX512VLBW-NEXT: vzeroupper ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: fancierRotate2: -; AVX10: # %bb.0: # %entry -; AVX10-NEXT: vpbroadcastd %edx, %ymm0 -; AVX10-NEXT: vpbroadcastd %ecx, %ymm1 -; AVX10-NEXT: movq $-1024, %rax # imm = 0xFC00 -; AVX10-NEXT: .p2align 4 -; AVX10-NEXT: .LBB8_1: # %loop -; AVX10-NEXT: # =>This Inner Loop Header: Depth=1 -; AVX10-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero -; AVX10-NEXT: vptestnmb %xmm2, %xmm2, %k1 -; AVX10-NEXT: vpblendmd %ymm0, %ymm1, %ymm2 {%k1} -; AVX10-NEXT: vmovdqu 4096(%rdi,%rax,4), %ymm3 -; AVX10-NEXT: vprolvd %ymm2, %ymm3, %ymm2 -; AVX10-NEXT: vmovdqu %ymm2, 4096(%rdi,%rax,4) -; AVX10-NEXT: addq $8, %rax -; AVX10-NEXT: jne .LBB8_1 -; AVX10-NEXT: # %bb.2: # %exit -; AVX10-NEXT: vzeroupper -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: fancierRotate2: +; AVX512VLVBMI2: # %bb.0: # %entry +; AVX512VLVBMI2-NEXT: vpbroadcastd %edx, %ymm0 +; AVX512VLVBMI2-NEXT: vpbroadcastd %ecx, %ymm1 +; AVX512VLVBMI2-NEXT: movq $-1024, %rax # imm = 0xFC00 +; AVX512VLVBMI2-NEXT: .p2align 4 +; AVX512VLVBMI2-NEXT: .LBB8_1: # %loop +; AVX512VLVBMI2-NEXT: # =>This Inner Loop Header: Depth=1 +; AVX512VLVBMI2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero +; AVX512VLVBMI2-NEXT: vptestnmb %xmm2, %xmm2, %k1 +; AVX512VLVBMI2-NEXT: vpblendmd %ymm0, %ymm1, %ymm2 {%k1} +; AVX512VLVBMI2-NEXT: vmovdqu 4096(%rdi,%rax,4), %ymm3 +; AVX512VLVBMI2-NEXT: vprolvd %ymm2, %ymm3, %ymm2 +; AVX512VLVBMI2-NEXT: vmovdqu %ymm2, 4096(%rdi,%rax,4) +; AVX512VLVBMI2-NEXT: addq $8, %rax +; AVX512VLVBMI2-NEXT: jne .LBB8_1 +; AVX512VLVBMI2-NEXT: # %bb.2: # %exit +; AVX512VLVBMI2-NEXT: vzeroupper +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: fancierRotate2: ; XOPAVX1: # %bb.0: # %entry @@ -1623,10 +1594,10 @@ define <4 x i64> @constant_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: constant_funnnel_v4i64: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: constant_funnnel_v4i64: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: constant_funnnel_v4i64: ; XOPAVX1: # %bb.0: @@ -1721,10 +1692,10 @@ define <8 x i32> @constant_funnnel_v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: constant_funnnel_v8i32: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: constant_funnnel_v8i32: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: constant_funnnel_v8i32: ; XOPAVX1: # %bb.0: @@ -1824,10 +1795,10 @@ define <16 x i16> @constant_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y) nounwin ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: constant_funnnel_v16i16: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: constant_funnnel_v16i16: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: constant_funnnel_v16i16: ; XOPAVX1: # %bb.0: @@ -1947,28 +1918,6 @@ define <32 x i8> @constant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind { ; AVX512VLBW-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX512VLVBMI2-LABEL: constant_funnnel_v32i8: -; AVX512VLVBMI2: # %bb.0: -; AVX512VLVBMI2-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1 -; AVX512VLVBMI2-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512VLVBMI2-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,64,1,65,2,66,3,67,4,68,5,69,6,70,7,71,8,72,9,73,10,74,11,75,12,76,13,77,14,78,15,79,16,80,17,81,18,82,19,83,20,84,21,85,22,86,23,87,24,88,25,89,26,90,27,91,28,92,29,93,30,94,31,95] -; AVX512VLVBMI2-NEXT: vpermi2b %zmm0, %zmm1, %zmm2 -; AVX512VLVBMI2-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm0 -; AVX512VLVBMI2-NEXT: vpsrlw $8, %zmm0, %zmm0 -; AVX512VLVBMI2-NEXT: vpmovwb %zmm0, %ymm0 -; AVX512VLVBMI2-NEXT: retq -; -; AVX10_256-LABEL: constant_funnnel_v32i8: -; AVX10_256: # %bb.0: -; AVX10_256-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] -; AVX10_256-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 -; AVX10_256-NEXT: vpsrlw $8, %ymm2, %ymm2 -; AVX10_256-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23] -; AVX10_256-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 -; AVX10_256-NEXT: vpsrlw $8, %ymm0, %ymm0 -; AVX10_256-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 -; AVX10_256-NEXT: retq -; ; XOPAVX1-LABEL: constant_funnnel_v32i8: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 @@ -2069,10 +2018,10 @@ define <4 x i64> @splatconstant_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y) nounwi ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatconstant_funnnel_v4i64: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldq $14, %ymm1, %ymm0, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v4i64: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldq $14, %ymm1, %ymm0, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_funnnel_v4i64: ; XOPAVX1: # %bb.0: @@ -2154,10 +2103,10 @@ define <8 x i32> @splatconstant_funnnel_v8i32(<8 x i32> %x, <8 x i32> %y) nounwi ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatconstant_funnnel_v8i32: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldd $4, %ymm1, %ymm0, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v8i32: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldd $4, %ymm1, %ymm0, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_funnnel_v8i32: ; XOPAVX1: # %bb.0: @@ -2239,10 +2188,10 @@ define <16 x i16> @splatconstant_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y) no ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatconstant_funnnel_v16i16: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshldw $7, %ymm1, %ymm0, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v16i16: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshldw $7, %ymm1, %ymm0, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_funnnel_v16i16: ; XOPAVX1: # %bb.0: @@ -2330,12 +2279,12 @@ define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwi ; AVX512VLBW-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 ^ (m32bcst & (ymm0 ^ ymm2)) ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatconstant_funnnel_v32i8: -; AVX10: # %bb.0: -; AVX10-NEXT: vpsllw $4, %ymm0, %ymm2 -; AVX10-NEXT: vpsrlw $4, %ymm1, %ymm0 -; AVX10-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 ^ (m32bcst & (ymm0 ^ ymm2)) -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v32i8: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpsllw $4, %ymm0, %ymm2 +; AVX512VLVBMI2-NEXT: vpsrlw $4, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 ^ (m32bcst & (ymm0 ^ ymm2)) +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_funnnel_v32i8: ; XOPAVX1: # %bb.0: diff --git a/llvm/test/CodeGen/X86/vector-fshr-128.ll b/llvm/test/CodeGen/X86/vector-fshr-128.ll index bf525442a419b..20be5791309fd 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-128.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-128.ll @@ -9,8 +9,7 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2 | FileCheck %s --check-prefixes=AVX512VBMI2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512VLBW ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2,+avx512vl | FileCheck %s --check-prefixes=AVX512VLVBMI2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-256 | FileCheck %s --check-prefixes=AVX512VLVBMI2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-512 | FileCheck %s --check-prefixes=AVX512VLVBMI2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1 | FileCheck %s --check-prefixes=AVX512VLVBMI2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefixes=XOP,XOPAVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefixes=XOP,XOPAVX2 diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll index b0a1a91bdccc5..1f164635910c0 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-256.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll @@ -6,9 +6,8 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512BW ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2 | FileCheck %s --check-prefixes=AVX512VBMI2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=AVX512VLBW -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2,+avx512vl | FileCheck %s --check-prefixes=AVX10,AVX512VLVBMI2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-256 | FileCheck %s --check-prefixes=AVX10,AVX10_256 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-512 | FileCheck %s --check-prefixes=AVX10,AVX512VLVBMI2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vbmi,+avx512vbmi2,+avx512vl | FileCheck %s --check-prefixes=AVX512VLVBMI2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1 | FileCheck %s --check-prefixes=AVX512VLVBMI2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefixes=XOPAVX1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefixes=XOPAVX2 @@ -118,11 +117,11 @@ define <4 x i64> @var_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %amt) ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: var_funnnel_v4i64: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdvq %ymm2, %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: var_funnnel_v4i64: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdvq %ymm2, %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: var_funnnel_v4i64: ; XOPAVX1: # %bb.0: @@ -274,11 +273,11 @@ define <8 x i32> @var_funnnel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %amt) ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: var_funnnel_v8i32: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdvd %ymm2, %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: var_funnnel_v8i32: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdvd %ymm2, %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: var_funnnel_v8i32: ; XOPAVX1: # %bb.0: @@ -454,11 +453,11 @@ define <16 x i16> @var_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> % ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: var_funnnel_v16i16: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdvw %ymm2, %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: var_funnnel_v16i16: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdvw %ymm2, %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: var_funnnel_v16i16: ; XOPAVX1: # %bb.0: @@ -720,20 +719,6 @@ define <32 x i8> @var_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %amt) ; AVX512VLVBMI2-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512VLVBMI2-NEXT: retq ; -; AVX10_256-LABEL: var_funnnel_v32i8: -; AVX10_256: # %bb.0: -; AVX10_256-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] -; AVX10_256-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2 -; AVX10_256-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; AVX10_256-NEXT: vpunpckhbw {{.*#+}} ymm5 = ymm2[8],ymm4[8],ymm2[9],ymm4[9],ymm2[10],ymm4[10],ymm2[11],ymm4[11],ymm2[12],ymm4[12],ymm2[13],ymm4[13],ymm2[14],ymm4[14],ymm2[15],ymm4[15],ymm2[24],ymm4[24],ymm2[25],ymm4[25],ymm2[26],ymm4[26],ymm2[27],ymm4[27],ymm2[28],ymm4[28],ymm2[29],ymm4[29],ymm2[30],ymm4[30],ymm2[31],ymm4[31] -; AVX10_256-NEXT: vpsrlvw %ymm5, %ymm3, %ymm3 -; AVX10_256-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23] -; AVX10_256-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm2[0],ymm4[0],ymm2[1],ymm4[1],ymm2[2],ymm4[2],ymm2[3],ymm4[3],ymm2[4],ymm4[4],ymm2[5],ymm4[5],ymm2[6],ymm4[6],ymm2[7],ymm4[7],ymm2[16],ymm4[16],ymm2[17],ymm4[17],ymm2[18],ymm4[18],ymm2[19],ymm4[19],ymm2[20],ymm4[20],ymm2[21],ymm4[21],ymm2[22],ymm4[22],ymm2[23],ymm4[23] -; AVX10_256-NEXT: vpsrlvw %ymm1, %ymm0, %ymm1 -; AVX10_256-NEXT: vmovdqa {{.*#+}} ymm0 = [0,2,4,6,8,10,12,14,32,34,36,38,40,42,44,46,16,18,20,22,24,26,28,30,48,50,52,54,56,58,60,62] -; AVX10_256-NEXT: vpermi2b %ymm3, %ymm1, %ymm0 -; AVX10_256-NEXT: retq -; ; XOPAVX1-LABEL: var_funnnel_v32i8: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} ymm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] @@ -870,12 +855,12 @@ define <4 x i64> @splatvar_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> % ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatvar_funnnel_v4i64: -; AVX10: # %bb.0: -; AVX10-NEXT: vpbroadcastq %xmm2, %ymm2 -; AVX10-NEXT: vpshrdvq %ymm2, %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatvar_funnnel_v4i64: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpbroadcastq %xmm2, %ymm2 +; AVX512VLVBMI2-NEXT: vpshrdvq %ymm2, %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_funnnel_v4i64: ; XOPAVX1: # %bb.0: @@ -988,12 +973,12 @@ define <8 x i32> @splatvar_funnnel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> % ; AVX512VLBW-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm3[0,2],ymm0[4,6],ymm3[4,6] ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatvar_funnnel_v8i32: -; AVX10: # %bb.0: -; AVX10-NEXT: vpbroadcastd %xmm2, %ymm2 -; AVX10-NEXT: vpshrdvd %ymm2, %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatvar_funnnel_v8i32: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpbroadcastd %xmm2, %ymm2 +; AVX512VLVBMI2-NEXT: vpshrdvd %ymm2, %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_funnnel_v8i32: ; XOPAVX1: # %bb.0: @@ -1110,12 +1095,12 @@ define <16 x i16> @splatvar_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatvar_funnnel_v16i16: -; AVX10: # %bb.0: -; AVX10-NEXT: vpbroadcastw %xmm2, %ymm2 -; AVX10-NEXT: vpshrdvw %ymm2, %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatvar_funnnel_v16i16: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpbroadcastw %xmm2, %ymm2 +; AVX512VLVBMI2-NEXT: vpshrdvw %ymm2, %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatvar_funnnel_v16i16: ; XOPAVX1: # %bb.0: @@ -1265,17 +1250,6 @@ define <32 x i8> @splatvar_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> % ; AVX512VLVBMI2-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512VLVBMI2-NEXT: retq ; -; AVX10_256-LABEL: splatvar_funnnel_v32i8: -; AVX10_256: # %bb.0: -; AVX10_256-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] -; AVX10_256-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 -; AVX10_256-NEXT: vpsrlw %xmm2, %ymm3, %ymm3 -; AVX10_256-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23] -; AVX10_256-NEXT: vpsrlw %xmm2, %ymm0, %ymm1 -; AVX10_256-NEXT: vmovdqa {{.*#+}} ymm0 = [0,2,4,6,8,10,12,14,32,34,36,38,40,42,44,46,16,18,20,22,24,26,28,30,48,50,52,54,56,58,60,62] -; AVX10_256-NEXT: vpermi2b %ymm3, %ymm1, %ymm0 -; AVX10_256-NEXT: retq -; ; XOPAVX1-LABEL: splatvar_funnnel_v32i8: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm0, %xmm3 @@ -1388,11 +1362,11 @@ define <4 x i64> @constant_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: constant_funnnel_v4i64: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: constant_funnnel_v4i64: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: constant_funnnel_v4i64: ; XOPAVX1: # %bb.0: @@ -1487,11 +1461,11 @@ define <8 x i32> @constant_funnnel_v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: constant_funnnel_v8i32: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: constant_funnnel_v8i32: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: constant_funnnel_v8i32: ; XOPAVX1: # %bb.0: @@ -1591,11 +1565,11 @@ define <16 x i16> @constant_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y) nounwin ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: constant_funnnel_v16i16: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 -; AVX10-NEXT: vmovdqa %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: constant_funnnel_v16i16: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 +; AVX512VLVBMI2-NEXT: vmovdqa %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: constant_funnnel_v16i16: ; XOPAVX1: # %bb.0: @@ -1761,16 +1735,6 @@ define <32 x i8> @constant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwind { ; AVX512VLVBMI2-NEXT: vpmovwb %zmm0, %ymm0 ; AVX512VLVBMI2-NEXT: retq ; -; AVX10_256-LABEL: constant_funnnel_v32i8: -; AVX10_256: # %bb.0: -; AVX10_256-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8],ymm0[8],ymm1[9],ymm0[9],ymm1[10],ymm0[10],ymm1[11],ymm0[11],ymm1[12],ymm0[12],ymm1[13],ymm0[13],ymm1[14],ymm0[14],ymm1[15],ymm0[15],ymm1[24],ymm0[24],ymm1[25],ymm0[25],ymm1[26],ymm0[26],ymm1[27],ymm0[27],ymm1[28],ymm0[28],ymm1[29],ymm0[29],ymm1[30],ymm0[30],ymm1[31],ymm0[31] -; AVX10_256-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 -; AVX10_256-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[1],ymm0[1],ymm1[2],ymm0[2],ymm1[3],ymm0[3],ymm1[4],ymm0[4],ymm1[5],ymm0[5],ymm1[6],ymm0[6],ymm1[7],ymm0[7],ymm1[16],ymm0[16],ymm1[17],ymm0[17],ymm1[18],ymm0[18],ymm1[19],ymm0[19],ymm1[20],ymm0[20],ymm1[21],ymm0[21],ymm1[22],ymm0[22],ymm1[23],ymm0[23] -; AVX10_256-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 -; AVX10_256-NEXT: vmovdqa {{.*#+}} ymm0 = [0,2,4,6,8,10,12,14,32,34,36,38,40,42,44,46,16,18,20,22,24,26,28,30,48,50,52,54,56,58,60,62] -; AVX10_256-NEXT: vpermi2b %ymm2, %ymm1, %ymm0 -; AVX10_256-NEXT: retq -; ; XOPAVX1-LABEL: constant_funnnel_v32i8: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vextractf128 $1, %ymm1, %xmm2 @@ -1869,10 +1833,10 @@ define <4 x i64> @splatconstant_funnnel_v4i64(<4 x i64> %x, <4 x i64> %y) nounwi ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatconstant_funnnel_v4i64: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdq $14, %ymm0, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v4i64: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdq $14, %ymm0, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_funnnel_v4i64: ; XOPAVX1: # %bb.0: @@ -1954,10 +1918,10 @@ define <8 x i32> @splatconstant_funnnel_v8i32(<8 x i32> %x, <8 x i32> %y) nounwi ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatconstant_funnnel_v8i32: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdd $4, %ymm0, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v8i32: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdd $4, %ymm0, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_funnnel_v8i32: ; XOPAVX1: # %bb.0: @@ -2039,10 +2003,10 @@ define <16 x i16> @splatconstant_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y) no ; AVX512VLBW-NEXT: vpor %ymm1, %ymm0, %ymm0 ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatconstant_funnnel_v16i16: -; AVX10: # %bb.0: -; AVX10-NEXT: vpshrdw $7, %ymm0, %ymm1, %ymm0 -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v16i16: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpshrdw $7, %ymm0, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_funnnel_v16i16: ; XOPAVX1: # %bb.0: @@ -2130,12 +2094,12 @@ define <32 x i8> @splatconstant_funnnel_v32i8(<32 x i8> %x, <32 x i8> %y) nounwi ; AVX512VLBW-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 ^ (m32bcst & (ymm0 ^ ymm2)) ; AVX512VLBW-NEXT: retq ; -; AVX10-LABEL: splatconstant_funnnel_v32i8: -; AVX10: # %bb.0: -; AVX10-NEXT: vpsllw $4, %ymm0, %ymm2 -; AVX10-NEXT: vpsrlw $4, %ymm1, %ymm0 -; AVX10-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 ^ (m32bcst & (ymm0 ^ ymm2)) -; AVX10-NEXT: retq +; AVX512VLVBMI2-LABEL: splatconstant_funnnel_v32i8: +; AVX512VLVBMI2: # %bb.0: +; AVX512VLVBMI2-NEXT: vpsllw $4, %ymm0, %ymm2 +; AVX512VLVBMI2-NEXT: vpsrlw $4, %ymm1, %ymm0 +; AVX512VLVBMI2-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 ^ (m32bcst & (ymm0 ^ ymm2)) +; AVX512VLVBMI2-NEXT: retq ; ; XOPAVX1-LABEL: splatconstant_funnnel_v32i8: ; XOPAVX1: # %bb.0: diff --git a/llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2_512ni-intrinsics.ll b/llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2_512ni-intrinsics.ll index 802cffc8aebb1..93006ae30f926 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2_512ni-intrinsics.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2_512ni-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt < %s -mattr=+avx10.2-512 -passes=msan -S | FileCheck %s +; RUN: opt < %s -mattr=+avx10.2 -passes=msan -S | FileCheck %s ; Forked from llvm/test/CodeGen/X86/avx10_2_512ni-intrinsics.ll ; diff --git a/llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2ni-intrinsics.ll b/llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2ni-intrinsics.ll index 491a890ee0b26..e121c3b6ea177 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2ni-intrinsics.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/X86/avx10_2ni-intrinsics.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 -; RUN: opt < %s -mattr=+avx10.2-256 -passes=msan -S | FileCheck %s +; RUN: opt < %s -mattr=+avx10.2 -passes=msan -S | FileCheck %s ; Forked from llvm/test/CodeGen/X86/avx10_2ni-intrinsics.ll ; diff --git a/llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll b/llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll index 67f0201476602..20a16325c3999 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/cost-conditional-branches.ll @@ -181,28 +181,186 @@ exit: define i64 @avx512_cond_load_cost(ptr %src, i32 %a, i64 %b, i32 %c, i32 %d) #1 { ; CHECK-LABEL: @avx512_cond_load_cost( ; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP63:%.*]] = add i32 [[C:%.*]], 1 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP63]], 8 +; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[ENTRY:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP63]], 8 +; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP63]], [[N_MOD_VF]] +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i64> poison, i64 [[B:%.*]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i64> [[BROADCAST_SPLATINSERT]], <8 x i64> poison, <8 x i32> zeroinitializer ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] -; CHECK: loop.header: -; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] -; CHECK-NEXT: [[C_1:%.*]] = icmp slt i32 [[IV]], 0 +; CHECK: vector.body: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i32> [ , [[ENTRY]] ], [ [[VEC_IND_NEXT:%.*]], [[LOOP_LATCH]] ] +; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <8 x i32> [[VEC_IND]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i1> [[TMP1]], i32 0 +; CHECK-NEXT: br i1 [[TMP2]], label [[PRED_UREM_IF:%.*]], label [[PRED_UREM_CONTINUE:%.*]] +; CHECK: pred.urem.if: +; CHECK-NEXT: [[TMP3:%.*]] = urem i32 [[A:%.*]], [[C]] +; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> poison, i32 [[TMP3]], i32 0 +; CHECK-NEXT: br label [[PRED_UREM_CONTINUE]] +; CHECK: pred.urem.continue: +; CHECK-NEXT: [[TMP5:%.*]] = phi <8 x i32> [ poison, [[LOOP_HEADER]] ], [ [[TMP4]], [[PRED_UREM_IF]] ] +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x i1> [[TMP1]], i32 1 +; CHECK-NEXT: br i1 [[TMP6]], label [[PRED_UREM_IF1:%.*]], label [[PRED_UREM_CONTINUE2:%.*]] +; CHECK: pred.urem.if1: +; CHECK-NEXT: [[TMP7:%.*]] = urem i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP8:%.*]] = insertelement <8 x i32> [[TMP5]], i32 [[TMP7]], i32 1 +; CHECK-NEXT: br label [[PRED_UREM_CONTINUE2]] +; CHECK: pred.urem.continue2: +; CHECK-NEXT: [[TMP9:%.*]] = phi <8 x i32> [ [[TMP5]], [[PRED_UREM_CONTINUE]] ], [ [[TMP8]], [[PRED_UREM_IF1]] ] +; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i1> [[TMP1]], i32 2 +; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_UREM_IF3:%.*]], label [[PRED_UREM_CONTINUE4:%.*]] +; CHECK: pred.urem.if3: +; CHECK-NEXT: [[TMP11:%.*]] = urem i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i32> [[TMP9]], i32 [[TMP11]], i32 2 +; CHECK-NEXT: br label [[PRED_UREM_CONTINUE4]] +; CHECK: pred.urem.continue4: +; CHECK-NEXT: [[TMP13:%.*]] = phi <8 x i32> [ [[TMP9]], [[PRED_UREM_CONTINUE2]] ], [ [[TMP12]], [[PRED_UREM_IF3]] ] +; CHECK-NEXT: [[TMP14:%.*]] = extractelement <8 x i1> [[TMP1]], i32 3 +; CHECK-NEXT: br i1 [[TMP14]], label [[PRED_UREM_IF5:%.*]], label [[PRED_UREM_CONTINUE6:%.*]] +; CHECK: pred.urem.if5: +; CHECK-NEXT: [[TMP15:%.*]] = urem i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP16:%.*]] = insertelement <8 x i32> [[TMP13]], i32 [[TMP15]], i32 3 +; CHECK-NEXT: br label [[PRED_UREM_CONTINUE6]] +; CHECK: pred.urem.continue6: +; CHECK-NEXT: [[TMP17:%.*]] = phi <8 x i32> [ [[TMP13]], [[PRED_UREM_CONTINUE4]] ], [ [[TMP16]], [[PRED_UREM_IF5]] ] +; CHECK-NEXT: [[TMP18:%.*]] = extractelement <8 x i1> [[TMP1]], i32 4 +; CHECK-NEXT: br i1 [[TMP18]], label [[PRED_UREM_IF7:%.*]], label [[PRED_UREM_CONTINUE8:%.*]] +; CHECK: pred.urem.if7: +; CHECK-NEXT: [[TMP19:%.*]] = urem i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP20:%.*]] = insertelement <8 x i32> [[TMP17]], i32 [[TMP19]], i32 4 +; CHECK-NEXT: br label [[PRED_UREM_CONTINUE8]] +; CHECK: pred.urem.continue8: +; CHECK-NEXT: [[TMP21:%.*]] = phi <8 x i32> [ [[TMP17]], [[PRED_UREM_CONTINUE6]] ], [ [[TMP20]], [[PRED_UREM_IF7]] ] +; CHECK-NEXT: [[TMP22:%.*]] = extractelement <8 x i1> [[TMP1]], i32 5 +; CHECK-NEXT: br i1 [[TMP22]], label [[PRED_UREM_IF9:%.*]], label [[PRED_UREM_CONTINUE10:%.*]] +; CHECK: pred.urem.if9: +; CHECK-NEXT: [[TMP23:%.*]] = urem i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP24:%.*]] = insertelement <8 x i32> [[TMP21]], i32 [[TMP23]], i32 5 +; CHECK-NEXT: br label [[PRED_UREM_CONTINUE10]] +; CHECK: pred.urem.continue10: +; CHECK-NEXT: [[TMP25:%.*]] = phi <8 x i32> [ [[TMP21]], [[PRED_UREM_CONTINUE8]] ], [ [[TMP24]], [[PRED_UREM_IF9]] ] +; CHECK-NEXT: [[TMP26:%.*]] = extractelement <8 x i1> [[TMP1]], i32 6 +; CHECK-NEXT: br i1 [[TMP26]], label [[PRED_UREM_IF11:%.*]], label [[PRED_UREM_CONTINUE12:%.*]] +; CHECK: pred.urem.if11: +; CHECK-NEXT: [[TMP27:%.*]] = urem i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP28:%.*]] = insertelement <8 x i32> [[TMP25]], i32 [[TMP27]], i32 6 +; CHECK-NEXT: br label [[PRED_UREM_CONTINUE12]] +; CHECK: pred.urem.continue12: +; CHECK-NEXT: [[TMP29:%.*]] = phi <8 x i32> [ [[TMP25]], [[PRED_UREM_CONTINUE10]] ], [ [[TMP28]], [[PRED_UREM_IF11]] ] +; CHECK-NEXT: [[TMP30:%.*]] = extractelement <8 x i1> [[TMP1]], i32 7 +; CHECK-NEXT: br i1 [[TMP30]], label [[PRED_UREM_IF13:%.*]], label [[PRED_UREM_CONTINUE14:%.*]] +; CHECK: pred.urem.if13: +; CHECK-NEXT: [[TMP31:%.*]] = urem i32 [[A]], [[C]] +; CHECK-NEXT: [[TMP32:%.*]] = insertelement <8 x i32> [[TMP29]], i32 [[TMP31]], i32 7 +; CHECK-NEXT: br label [[PRED_UREM_CONTINUE14]] +; CHECK: pred.urem.continue14: +; CHECK-NEXT: [[TMP33:%.*]] = phi <8 x i32> [ [[TMP29]], [[PRED_UREM_CONTINUE12]] ], [ [[TMP32]], [[PRED_UREM_IF13]] ] +; CHECK-NEXT: [[TMP34:%.*]] = sub <8 x i32> zeroinitializer, [[TMP33]] +; CHECK-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP1]], i32 0 +; CHECK-NEXT: br i1 [[TMP35]], label [[PRED_UDIV_IF:%.*]], label [[PRED_UDIV_CONTINUE:%.*]] +; CHECK: pred.udiv.if: +; CHECK-NEXT: [[TMP36:%.*]] = udiv i32 [[C]], [[D:%.*]] +; CHECK-NEXT: [[TMP37:%.*]] = insertelement <8 x i32> poison, i32 [[TMP36]], i32 0 +; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE]] +; CHECK: pred.udiv.continue: +; CHECK-NEXT: [[TMP38:%.*]] = phi <8 x i32> [ poison, [[PRED_UREM_CONTINUE14]] ], [ [[TMP37]], [[PRED_UDIV_IF]] ] +; CHECK-NEXT: [[TMP39:%.*]] = extractelement <8 x i1> [[TMP1]], i32 1 +; CHECK-NEXT: br i1 [[TMP39]], label [[PRED_UDIV_IF15:%.*]], label [[PRED_UDIV_CONTINUE16:%.*]] +; CHECK: pred.udiv.if15: +; CHECK-NEXT: [[TMP40:%.*]] = udiv i32 [[C]], [[D]] +; CHECK-NEXT: [[TMP41:%.*]] = insertelement <8 x i32> [[TMP38]], i32 [[TMP40]], i32 1 +; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE16]] +; CHECK: pred.udiv.continue16: +; CHECK-NEXT: [[TMP42:%.*]] = phi <8 x i32> [ [[TMP38]], [[PRED_UDIV_CONTINUE]] ], [ [[TMP41]], [[PRED_UDIV_IF15]] ] +; CHECK-NEXT: [[TMP43:%.*]] = extractelement <8 x i1> [[TMP1]], i32 2 +; CHECK-NEXT: br i1 [[TMP43]], label [[PRED_UDIV_IF17:%.*]], label [[PRED_UDIV_CONTINUE18:%.*]] +; CHECK: pred.udiv.if17: +; CHECK-NEXT: [[TMP44:%.*]] = udiv i32 [[C]], [[D]] +; CHECK-NEXT: [[TMP45:%.*]] = insertelement <8 x i32> [[TMP42]], i32 [[TMP44]], i32 2 +; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE18]] +; CHECK: pred.udiv.continue18: +; CHECK-NEXT: [[TMP46:%.*]] = phi <8 x i32> [ [[TMP42]], [[PRED_UDIV_CONTINUE16]] ], [ [[TMP45]], [[PRED_UDIV_IF17]] ] +; CHECK-NEXT: [[TMP47:%.*]] = extractelement <8 x i1> [[TMP1]], i32 3 +; CHECK-NEXT: br i1 [[TMP47]], label [[PRED_UDIV_IF19:%.*]], label [[PRED_UDIV_CONTINUE20:%.*]] +; CHECK: pred.udiv.if19: +; CHECK-NEXT: [[TMP48:%.*]] = udiv i32 [[C]], [[D]] +; CHECK-NEXT: [[TMP49:%.*]] = insertelement <8 x i32> [[TMP46]], i32 [[TMP48]], i32 3 +; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE20]] +; CHECK: pred.udiv.continue20: +; CHECK-NEXT: [[TMP50:%.*]] = phi <8 x i32> [ [[TMP46]], [[PRED_UDIV_CONTINUE18]] ], [ [[TMP49]], [[PRED_UDIV_IF19]] ] +; CHECK-NEXT: [[TMP51:%.*]] = extractelement <8 x i1> [[TMP1]], i32 4 +; CHECK-NEXT: br i1 [[TMP51]], label [[PRED_UDIV_IF21:%.*]], label [[PRED_UDIV_CONTINUE22:%.*]] +; CHECK: pred.udiv.if21: +; CHECK-NEXT: [[TMP52:%.*]] = udiv i32 [[C]], [[D]] +; CHECK-NEXT: [[TMP53:%.*]] = insertelement <8 x i32> [[TMP50]], i32 [[TMP52]], i32 4 +; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE22]] +; CHECK: pred.udiv.continue22: +; CHECK-NEXT: [[TMP54:%.*]] = phi <8 x i32> [ [[TMP50]], [[PRED_UDIV_CONTINUE20]] ], [ [[TMP53]], [[PRED_UDIV_IF21]] ] +; CHECK-NEXT: [[TMP55:%.*]] = extractelement <8 x i1> [[TMP1]], i32 5 +; CHECK-NEXT: br i1 [[TMP55]], label [[PRED_UDIV_IF23:%.*]], label [[PRED_UDIV_CONTINUE24:%.*]] +; CHECK: pred.udiv.if23: +; CHECK-NEXT: [[TMP56:%.*]] = udiv i32 [[C]], [[D]] +; CHECK-NEXT: [[TMP57:%.*]] = insertelement <8 x i32> [[TMP54]], i32 [[TMP56]], i32 5 +; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE24]] +; CHECK: pred.udiv.continue24: +; CHECK-NEXT: [[TMP58:%.*]] = phi <8 x i32> [ [[TMP54]], [[PRED_UDIV_CONTINUE22]] ], [ [[TMP57]], [[PRED_UDIV_IF23]] ] +; CHECK-NEXT: [[TMP59:%.*]] = extractelement <8 x i1> [[TMP1]], i32 6 +; CHECK-NEXT: br i1 [[TMP59]], label [[PRED_UDIV_IF25:%.*]], label [[PRED_UDIV_CONTINUE26:%.*]] +; CHECK: pred.udiv.if25: +; CHECK-NEXT: [[TMP60:%.*]] = udiv i32 [[C]], [[D]] +; CHECK-NEXT: [[TMP61:%.*]] = insertelement <8 x i32> [[TMP58]], i32 [[TMP60]], i32 6 +; CHECK-NEXT: br label [[PRED_UDIV_CONTINUE26]] +; CHECK: pred.udiv.continue26: +; CHECK-NEXT: [[TMP62:%.*]] = phi <8 x i32> [ [[TMP58]], [[PRED_UDIV_CONTINUE24]] ], [ [[TMP61]], [[PRED_UDIV_IF25]] ] +; CHECK-NEXT: [[C_1:%.*]] = extractelement <8 x i1> [[TMP1]], i32 7 ; CHECK-NEXT: br i1 [[C_1]], label [[IF_THEN:%.*]], label [[LOOP_LATCH]] +; CHECK: pred.udiv.if27: +; CHECK-NEXT: [[TMP64:%.*]] = udiv i32 [[C]], [[D]] +; CHECK-NEXT: [[TMP65:%.*]] = insertelement <8 x i32> [[TMP62]], i32 [[TMP64]], i32 7 +; CHECK-NEXT: br label [[LOOP_LATCH]] +; CHECK: pred.udiv.continue28: +; CHECK-NEXT: [[TMP66:%.*]] = phi <8 x i32> [ [[TMP62]], [[PRED_UDIV_CONTINUE26]] ], [ [[TMP65]], [[IF_THEN]] ] +; CHECK-NEXT: [[TMP67:%.*]] = or <8 x i32> [[TMP66]], [[TMP34]] +; CHECK-NEXT: [[TMP68:%.*]] = sext <8 x i32> [[TMP67]] to <8 x i64> +; CHECK-NEXT: [[TMP69:%.*]] = getelementptr { i64, i64, i64 }, ptr [[SRC:%.*]], <8 x i64> [[TMP68]], i32 2 +; CHECK-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <8 x i64> @llvm.masked.gather.v8i64.v8p0(<8 x ptr> [[TMP69]], i32 8, <8 x i1> [[TMP1]], <8 x i64> poison) +; CHECK-NEXT: [[TMP70:%.*]] = or <8 x i64> [[WIDE_MASKED_GATHER]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[PREDPHI:%.*]] = select <8 x i1> [[TMP1]], <8 x i64> [[TMP70]], <8 x i64> zeroinitializer +; CHECK-NEXT: [[IV_NEXT]] = add nuw i32 [[IV]], 8 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i32> [[VEC_IND]], splat (i32 8) +; CHECK-NEXT: [[TMP71:%.*]] = icmp eq i32 [[IV_NEXT]], [[N_VEC]] +; CHECK-NEXT: br i1 [[TMP71]], label [[MIDDLE_BLOCK:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: [[TMP72:%.*]] = extractelement <8 x i64> [[PREDPHI]], i32 7 +; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP63]], [[N_VEC]] +; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY1:%.*]] ] +; CHECK-NEXT: br label [[LOOP_HEADER1:%.*]] +; CHECK: loop.header: +; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT1:%.*]], [[LOOP_LATCH1:%.*]] ] +; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[IV1]], 0 +; CHECK-NEXT: br i1 [[C_2]], label [[IF_THEN1:%.*]], label [[LOOP_LATCH1]] ; CHECK: if.then: -; CHECK-NEXT: [[TMP0:%.*]] = urem i32 [[A:%.*]], [[C:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = urem i32 [[A]], [[C]] ; CHECK-NEXT: [[MUL:%.*]] = sub i32 0, [[TMP0]] -; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[C]], [[D:%.*]] +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[C]], [[D]] ; CHECK-NEXT: [[OR:%.*]] = or i32 [[DIV]], [[MUL]] ; CHECK-NEXT: [[EXT:%.*]] = sext i32 [[OR]] to i64 -; CHECK-NEXT: [[GEP:%.*]] = getelementptr { i64, i64, i64 }, ptr [[SRC:%.*]], i64 [[EXT]], i32 2 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr { i64, i64, i64 }, ptr [[SRC]], i64 [[EXT]], i32 2 ; CHECK-NEXT: [[L:%.*]] = load i64, ptr [[GEP]], align 8 -; CHECK-NEXT: [[OR_2:%.*]] = or i64 [[L]], [[B:%.*]] -; CHECK-NEXT: br label [[LOOP_LATCH]] +; CHECK-NEXT: [[OR_2:%.*]] = or i64 [[L]], [[B]] +; CHECK-NEXT: br label [[LOOP_LATCH1]] ; CHECK: loop.latch: -; CHECK-NEXT: [[RES:%.*]] = phi i64 [ 0, [[LOOP_HEADER]] ], [ [[OR_2]], [[IF_THEN]] ] -; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 -; CHECK-NEXT: [[EC:%.*]] = icmp ult i32 [[IV]], [[C]] -; CHECK-NEXT: br i1 [[EC]], label [[LOOP_HEADER]], label [[EXIT:%.*]] +; CHECK-NEXT: [[RES:%.*]] = phi i64 [ 0, [[LOOP_HEADER1]] ], [ [[OR_2]], [[IF_THEN1]] ] +; CHECK-NEXT: [[IV_NEXT1]] = add i32 [[IV1]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp ult i32 [[IV1]], [[C]] +; CHECK-NEXT: br i1 [[EC]], label [[LOOP_HEADER1]], label [[EXIT]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK: exit: -; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i64 [ [[RES]], [[LOOP_LATCH]] ] +; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi i64 [ [[RES]], [[LOOP_LATCH1]] ], [ [[TMP72]], [[MIDDLE_BLOCK]] ] ; CHECK-NEXT: ret i64 [[RES_LCSSA]] ; entry: @@ -420,13 +578,13 @@ define void @cost_duplicate_recipe_for_sinking(ptr %A, i64 %N) #2 { ; CHECK: pred.store.continue37: ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 ; CHECK-NEXT: [[TMP83:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] -; CHECK-NEXT: br i1 [[TMP83]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP83]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: br label [[VEC_EPILOG_ITER_CHECK:%.*]] ; CHECK: vec.epilog.iter.check: ; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[TMP0]], [[N_VEC]] ; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ule i64 [[N_VEC_REMAINING]], 4 -; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]] +; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF7:![0-9]+]] ; CHECK: vec.epilog.ph: ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL1:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] ; CHECK-NEXT: [[N_MOD_VF38:%.*]] = urem i64 [[TMP0]], 4 @@ -479,7 +637,7 @@ define void @cost_duplicate_recipe_for_sinking(ptr %A, i64 %N) #2 { ; CHECK: pred.store.continue50: ; CHECK-NEXT: [[INDEX_NEXT51]] = add nuw i64 [[INDEX40]], 4 ; CHECK-NEXT: [[TMP106:%.*]] = icmp eq i64 [[INDEX_NEXT51]], [[N_VEC39]] -; CHECK-NEXT: br i1 [[TMP106]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP106]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] ; CHECK: vec.epilog.middle.block: ; CHECK-NEXT: br label [[VEC_EPILOG_SCALAR_PH]] ; CHECK: vec.epilog.scalar.ph: @@ -499,7 +657,7 @@ define void @cost_duplicate_recipe_for_sinking(ptr %A, i64 %N) #2 { ; CHECK: loop.latch: ; CHECK-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 1 ; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] -; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP6:![0-9]+]] +; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP9:![0-9]+]] ; CHECK: exit: ; CHECK-NEXT: ret void ; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/revec-getExtractWithExtendCost.ll b/llvm/test/Transforms/SLPVectorizer/X86/revec-getExtractWithExtendCost.ll index 8d3d9f2979298..28c0989b004e8 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/revec-getExtractWithExtendCost.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/revec-getExtractWithExtendCost.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=x86_64-unknown-linux-gnu -mattr=+avx10.2-512 -passes=slp-vectorizer -S -slp-revec %s | FileCheck %s +; RUN: opt -mtriple=x86_64-unknown-linux-gnu -mattr=+avx10.2 -passes=slp-vectorizer -S -slp-revec %s | FileCheck %s define void @test() { ; CHECK-LABEL: @test( diff --git a/llvm/test/Transforms/SLPVectorizer/X86/revec-load-compress.ll b/llvm/test/Transforms/SLPVectorizer/X86/revec-load-compress.ll index 4990fe102564a..75a866f97a8b4 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/revec-load-compress.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/revec-load-compress.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=x86_64-unknown-linux-gnu -mattr=+avx10.1-512 -passes=slp-vectorizer -S -slp-revec < %s | FileCheck %s +; RUN: opt -mtriple=x86_64-unknown-linux-gnu -mattr=+avx10.1 -passes=slp-vectorizer -S -slp-revec < %s | FileCheck %s define void @test(ptr %in) { ; CHECK-LABEL: @test(