A scalable physical design framework for tileable FPGA architectures provides all the required functionality, from generating Verilog netlist using the OpenFPGA framework to implementing a final tapeout-ready GDS layout.
This repository contains all the extensible base scripts for netlist_generation, design restructuring, place and route, and signoff. To design an FPGA fabric, please clone the following tapeout template repository, which contains openfpga-physical repository as a subtree. OpenFPGA-Physical-Tapeout-Template
Please read How to contribute to the Document's OpenFPGA Physical section to understand how to keep in sync with the updated scripts.
The complete API documentation for the OpenFPGA-Physical scripts is available on the following link. OpenFPGA-Physical Documentation