Skip to content
This repository was archived by the owner on May 26, 2024. It is now read-only.

Commit aed20ea

Browse files
aentingeraentinger
committed
Tracing works like this ...
1 parent eb7cb2f commit aed20ea

File tree

2 files changed

+59
-62
lines changed

2 files changed

+59
-62
lines changed

‎.gdbinit-trace

Lines changed: 47 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -33,68 +33,53 @@ set $GPIOE_AFRL = $GPIOE_BASE_ADDR + 0x20
3333

3434
####################################################################
3535

36-
# DBGMCU_CR: enable clock domains for debugging
37-
# D3DBGCKEN | D1DBGCKEN | TRACECLKEN
38-
set *$DBGMCU_CR |= (1<<22) | (1<<21) | (1<<20)
39-
40-
set $bits = 1
41-
set $drive = 1
42-
43-
# enable peripheral clock for Port E
44-
set *$RCC_AHB4ENR |= 0x000000010
45-
46-
# enable SYSCFG peripheral clock
47-
set *$RCC_APB4ENR |= 0x00000001
48-
49-
# Enable compensation cell
50-
set *$SYSCFG_CCCSR |= 0x00000001
51-
52-
# Setup PE2 & PE3
53-
# enable alternate function mode
54-
set *$GPIOE_MODER &= ~(0x000000F0)
55-
set *$GPIOE_MODER |= 0xA0
56-
57-
# Drive speed
58-
set *$GPIOE_OSPEEDR &= ~0xf0
59-
set *$GPIOE_OSPEEDR |= ($drive<<4)|($drive<<6)
60-
61-
# no pull-up, no pull-down
62-
set *$GPIOE_PUDR &= ~0xF0
63-
# AF0
64-
set *$GPIOE_AFRL &= ~0xF0
65-
66-
# Set number of bits in DBGMCU_CR
67-
#set *0xE0042004 &= ~(3<<6)
68-
69-
if ($bits<3)
70-
set *0xE0042004 |= ((($bits+1)<<6) | (1<<5))
71-
else
72-
set *0xE0042004 |= ((3<<6) | (1<<5))
36+
define enableTraceSTM32H747_M7
37+
38+
# enable SYSCFG peripheral clock (Bit #1: SYSCFGEN)
39+
set *$RCC_APB4ENR |= 0x00000002
40+
# enable I/O compensation cell (Bit #0: EN)
41+
set *$SYSCFG_CCCSR |= 0x00000001
42+
43+
# enable peripheral clock for Port E (Bit #4: GPIOEEN)
44+
set *$RCC_AHB4ENR |= 0x000000010
45+
# enable alternate function mode
46+
set *$GPIOE_MODER &= ~0x000000F0
47+
set *$GPIOE_MODER |= 0x000000A0
48+
# set speed to high speed
49+
set *$GPIOE_OSPEEDR |= 0x000000A0
50+
# no pull-up, no pull-down
51+
set *$GPIOE_PUDR &= ~0x000000F0
52+
# set to alternate function #0 (TRACECLK, TRACED0)
53+
set *$GPIOE_AFRL &= ~0x0000FF00
54+
55+
# DBGMCU_CR: enable clock domains for debugging
56+
# D3DBGCKEN | D1DBGCKEN | TRACECLKEN
57+
set *$DBGMCU_CR |= (1<<22) | (1<<21) | (1<<20)
58+
59+
# Enable Trace TRCENA (DCB DEMCR)
60+
set $CDBBASE=0xE000EDF0
61+
set *($CDBBASE+0xC)=(1<<24)
62+
63+
# Finally start the trace output
64+
set $bits=1
65+
_doTRACE
66+
67+
dwtSamplePC 1
68+
dwtSyncTap 3
69+
dwtPostTap 1
70+
dwtPostInit 1
71+
dwtPostReset 10
72+
dwtCycEna 1
73+
74+
ITMId 1
75+
ITMGTSFreq 3
76+
ITMTSPrescale 3
77+
ITMTXEna 1
78+
ITMSYNCEna 1
79+
ITMEna 1
80+
81+
ITMTER 0 0xFFFFFFFF
82+
ITMTPR 0xFFFFFFFF
7383
end
74-
75-
# Enable Trace TRCENA (DCB DEMCR)
76-
set *($CDBBASE+0xC)=(1<<24)
77-
78-
# Finally start the trace output
79-
_doTRACE
80-
81-
82-
83-
dwtSamplePC 1
84-
dwtSyncTap 3
85-
dwtPostTap 1
86-
dwtPostInit 1
87-
dwtPostReset 10
88-
dwtCycEna 1
89-
90-
ITMId 1
91-
ITMGTSFreq 3
92-
ITMTSPrescale 3
93-
ITMTXEna 1
94-
ITMSYNCEna 1
95-
ITMEna 1
96-
97-
ITMTER 0 0xFFFFFFFF
98-
ITMTPR 0xFFFFFFFF
9984
####################################################################
10085
run

‎README.md

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,3 +51,15 @@ which results in i.e.
5151

5252
[---H] Interval = 999mS
5353
```
54+
55+
### How-to-trace using TRACECLK / TRACED0 and ORBTrace mini
56+
```bash
57+
ln -s .gdbinit-trace .gdbinit
58+
arm-none-eabi-gdb -iex 'add-auto-load-safe-path .'
59+
...
60+
c
61+
Ctrl+C
62+
enableTraceSTM32H747_M7
63+
c
64+
....
65+
```

0 commit comments

Comments
 (0)