From e7edf0783e945f4107dcc7f68543ed05e92189a4 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 9 Apr 2025 21:30:17 +1000 Subject: [PATCH 1/8] drivers/memory/spiflash: Allow a board/port to configure chip params. This commit allows the user of this driver to dynamically configure the SPI flash chip parameters. For this, enable `MICROPY_HW_SPIFLASH_CHIP_PARAMS` and then set the `mp_spiflash_t::chip_params` element to point to a valid `mp_spiflash_chip_params_t` struct. Signed-off-by: Damien George --- drivers/memory/spiflash.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/memory/spiflash.h b/drivers/memory/spiflash.h index edd7d49330da1..a22742fc6f2b9 100644 --- a/drivers/memory/spiflash.h +++ b/drivers/memory/spiflash.h @@ -29,6 +29,11 @@ #include "drivers/bus/spi.h" #include "drivers/bus/qspi.h" +// Whether to enable dynamic configuration of SPI flash through mp_spiflash_chip_params_t. +#ifndef MICROPY_HW_SPIFLASH_CHIP_PARAMS +#define MICROPY_HW_SPIFLASH_CHIP_PARAMS (0) +#endif + #define MP_SPIFLASH_ERASE_BLOCK_SIZE (4096) // must be a power of 2 enum { @@ -66,8 +71,20 @@ typedef struct _mp_spiflash_config_t { #endif } mp_spiflash_config_t; +#if MICROPY_HW_SPIFLASH_CHIP_PARAMS +typedef struct _mp_spiflash_chip_params_t { + uint32_t jedec_id; + uint8_t memory_size_bytes_log2; + uint8_t qspi_prescaler; + uint8_t qread_num_dummy; +} mp_spiflash_chip_params_t; +#endif + typedef struct _mp_spiflash_t { const mp_spiflash_config_t *config; + #if MICROPY_HW_SPIFLASH_CHIP_PARAMS + const mp_spiflash_chip_params_t *chip_params; + #endif volatile uint32_t flags; } mp_spiflash_t; From b078569cffb4b32585806b42ef7a0501bc4d0bca Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 2 Apr 2025 12:47:48 +1100 Subject: [PATCH 2/8] drivers/memory/spiflash: Allow a board/port to detect SPI flash. This commit allows the user of this driver to intercept the SPI flash initialisation routine and possibly take some action based on the JEDEC id, for example change the `mp_spiflash_t::chip_params` element. To do this, enable `MICROPY_HW_SPIFLASH_DETECT_DEVICE` and define a function called `mp_spiflash_detect()`. Signed-off-by: Damien George --- drivers/memory/spiflash.c | 12 +++++++++--- drivers/memory/spiflash.h | 10 ++++++++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/memory/spiflash.c b/drivers/memory/spiflash.c index 09ab7157b88eb..b4133fe2f068f 100644 --- a/drivers/memory/spiflash.c +++ b/drivers/memory/spiflash.c @@ -31,6 +31,10 @@ #include "py/mphal.h" #include "drivers/memory/spiflash.h" +#if defined(CHECK_DEVID) +#error "CHECK_DEVID no longer supported, use MICROPY_HW_SPIFLASH_DETECT_DEVICE instead" +#endif + #define QSPI_QE_MASK (0x02) #define USE_WR_DELAY (1) @@ -198,11 +202,13 @@ void mp_spiflash_init(mp_spiflash_t *self) { mp_hal_delay_ms(1); #endif - #if defined(CHECK_DEVID) - // Validate device id + #if MICROPY_HW_SPIFLASH_DETECT_DEVICE + // Attempt to detect SPI flash based on its JEDEC id. uint32_t devid; int ret = mp_spiflash_read_cmd(self, CMD_RD_DEVID, 3, &devid); - if (ret != 0 || devid != CHECK_DEVID) { + ret = mp_spiflash_detect(self, ret, devid); + if (ret != 0) { + // Could not read device id. mp_spiflash_release_bus(self); return; } diff --git a/drivers/memory/spiflash.h b/drivers/memory/spiflash.h index a22742fc6f2b9..d98047c89f07c 100644 --- a/drivers/memory/spiflash.h +++ b/drivers/memory/spiflash.h @@ -34,6 +34,11 @@ #define MICROPY_HW_SPIFLASH_CHIP_PARAMS (0) #endif +// Whether to enable detection of SPI flash during initialisation. +#ifndef MICROPY_HW_SPIFLASH_DETECT_DEVICE +#define MICROPY_HW_SPIFLASH_DETECT_DEVICE (0) +#endif + #define MP_SPIFLASH_ERASE_BLOCK_SIZE (4096) // must be a power of 2 enum { @@ -91,6 +96,11 @@ typedef struct _mp_spiflash_t { void mp_spiflash_init(mp_spiflash_t *self); void mp_spiflash_deepsleep(mp_spiflash_t *self, int value); +#if MICROPY_HW_SPIFLASH_DETECT_DEVICE +// A board/port should define this function to perform actions based on the JEDEC id. +int mp_spiflash_detect(mp_spiflash_t *spiflash, int ret, uint32_t devid); +#endif + // These functions go direct to the SPI flash device int mp_spiflash_erase_block(mp_spiflash_t *self, uint32_t addr); int mp_spiflash_read(mp_spiflash_t *self, uint32_t addr, size_t len, uint8_t *dest); From 2c0240e068b66b5f7b063125a7977cbca03d9483 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 2 Apr 2025 12:47:40 +1100 Subject: [PATCH 3/8] drivers/bus/qspi: Make num_dummy configurable for quad reads. Signed-off-by: Damien George --- drivers/bus/qspi.h | 2 +- drivers/bus/softqspi.c | 6 +++--- drivers/memory/spiflash.c | 14 ++++++++++++-- ports/stm32/boards/STM32F769DISC/board_init.c | 4 +++- ports/stm32/octospi.c | 4 ++-- ports/stm32/qspi.c | 14 +++++++++----- ports/stm32/qspi.h | 2 +- 7 files changed, 31 insertions(+), 15 deletions(-) diff --git a/drivers/bus/qspi.h b/drivers/bus/qspi.h index 7ba2e750943c5..32b2890e3fc4a 100644 --- a/drivers/bus/qspi.h +++ b/drivers/bus/qspi.h @@ -45,7 +45,7 @@ typedef struct _mp_qspi_proto_t { int (*write_cmd_data)(void *self, uint8_t cmd, size_t len, uint32_t data); int (*write_cmd_addr_data)(void *self, uint8_t cmd, uint32_t addr, size_t len, const uint8_t *src); int (*read_cmd)(void *self, uint8_t cmd, size_t len, uint32_t *dest); - int (*read_cmd_qaddr_qdata)(void *self, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest); + int (*read_cmd_qaddr_qdata)(void *self, uint8_t cmd, uint32_t addr, uint8_t num_dummy, size_t len, uint8_t *dest); } mp_qspi_proto_t; typedef struct _mp_soft_qspi_obj_t { diff --git a/drivers/bus/softqspi.c b/drivers/bus/softqspi.c index 5cfc4db5e3383..06dcd03b02dda 100644 --- a/drivers/bus/softqspi.c +++ b/drivers/bus/softqspi.c @@ -189,13 +189,13 @@ static int mp_soft_qspi_read_cmd(void *self_in, uint8_t cmd, size_t len, uint32_ return 0; } -static int mp_soft_qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) { +static int mp_soft_qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, uint8_t num_dummy, size_t len, uint8_t *dest) { mp_soft_qspi_obj_t *self = (mp_soft_qspi_obj_t*)self_in; - uint8_t cmd_buf[7] = {cmd}; + uint8_t cmd_buf[16] = {cmd}; uint8_t addr_len = mp_spi_set_addr_buff(&cmd_buf[1], addr); CS_LOW(self); mp_soft_qspi_transfer(self, 1, cmd_buf, NULL); - mp_soft_qspi_qwrite(self, addr_len + 3, &cmd_buf[1]); // 3/4 addr bytes, 1 extra byte (0), 2 dummy bytes (4 dummy cycles) + mp_soft_qspi_qwrite(self, addr_len + 1 + num_dummy, &cmd_buf[1]); // 3/4 addr bytes, 1 extra byte (0), N dummy bytes (2*N dummy cycles) mp_soft_qspi_qread(self, len, dest); CS_HIGH(self); return 0; diff --git a/drivers/memory/spiflash.c b/drivers/memory/spiflash.c index b4133fe2f068f..1ae0bbbc6792a 100644 --- a/drivers/memory/spiflash.c +++ b/drivers/memory/spiflash.c @@ -35,6 +35,14 @@ #error "CHECK_DEVID no longer supported, use MICROPY_HW_SPIFLASH_DETECT_DEVICE instead" #endif +// The default number of dummy bytes for quad-read is 2. This can be changed by enabling +// MICROPY_HW_SPIFLASH_CHIP_PARAMS and configuring the value in mp_spiflash_chip_params_t. +#if MICROPY_HW_SPIFLASH_CHIP_PARAMS +#define MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(spiflash) (spiflash->chip_params->qread_num_dummy) +#else +#define MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(spiflash) (2) +#endif + #define QSPI_QE_MASK (0x02) #define USE_WR_DELAY (1) @@ -115,7 +123,8 @@ static int mp_spiflash_transfer_cmd_addr_data(mp_spiflash_t *self, uint8_t cmd, mp_hal_pin_write(c->bus.u_spi.cs, 1); } else { if (dest != NULL) { - ret = c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, cmd, addr, len, dest); + uint8_t num_dummy = MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(self); + ret = c->bus.u_qspi.proto->read_cmd_qaddr_qdata(c->bus.u_qspi.data, cmd, addr, num_dummy, len, dest); } else { ret = c->bus.u_qspi.proto->write_cmd_addr_data(c->bus.u_qspi.data, cmd, addr, len, src); } @@ -186,7 +195,8 @@ void mp_spiflash_init(mp_spiflash_t *self) { mp_hal_pin_output(self->config->bus.u_spi.cs); self->config->bus.u_spi.proto->ioctl(self->config->bus.u_spi.data, MP_SPI_IOCTL_INIT); } else { - self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT, 0); + uint8_t num_dummy = MICROPY_HW_SPIFLASH_QREAD_NUM_DUMMY(self); + self->config->bus.u_qspi.proto->ioctl(self->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT, num_dummy); } mp_spiflash_acquire_bus(self); diff --git a/ports/stm32/boards/STM32F769DISC/board_init.c b/ports/stm32/boards/STM32F769DISC/board_init.c index 578dc9adb6c82..001b18bc06783 100644 --- a/ports/stm32/boards/STM32F769DISC/board_init.c +++ b/ports/stm32/boards/STM32F769DISC/board_init.c @@ -3,6 +3,8 @@ // This configuration is needed for mboot to be able to write to the external QSPI flash +#define QSPI_QREAD_NUM_DUMMY (2) + #if MICROPY_HW_SPIFLASH_ENABLE_CACHE static mp_spiflash_cache_t spi_bdev_cache; #endif @@ -21,6 +23,6 @@ spi_bdev_t spi_bdev; // This init function is needed to memory map the QSPI flash early in the boot process void board_early_init(void) { - qspi_init(); + qspi_init(QSPI_QREAD_NUM_DUMMY); qspi_memory_map(); } diff --git a/ports/stm32/octospi.c b/ports/stm32/octospi.c index 345c4a2374128..861941325c615 100644 --- a/ports/stm32/octospi.c +++ b/ports/stm32/octospi.c @@ -283,7 +283,7 @@ static int octospi_read_cmd(void *self_in, uint8_t cmd, size_t len, uint32_t *de return 0; } -static int octospi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) { +static int octospi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, uint8_t num_dummy, size_t len, uint8_t *dest) { (void)self_in; #if defined(MICROPY_HW_OSPIFLASH_IO1) && !defined(MICROPY_HW_OSPIFLASH_IO2) && !defined(MICROPY_HW_OSPIFLASH_IO4) @@ -293,7 +293,7 @@ static int octospi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t add uint32_t adsize = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 3 : 2; uint32_t dmode = 2; // data on 2-lines uint32_t admode = 2; // address on 2-lines - uint32_t dcyc = 4; // 4 dummy cycles + uint32_t dcyc = 2 * num_dummy; // 2N dummy cycles if (cmd == 0xeb || cmd == 0xec) { // Convert to 2-line command. diff --git a/ports/stm32/qspi.c b/ports/stm32/qspi.c index 7334ece4f2181..1360d9b490d29 100644 --- a/ports/stm32/qspi.c +++ b/ports/stm32/qspi.c @@ -62,6 +62,8 @@ #define QSPI_ADSIZE 2 #endif +static uint8_t qspi_num_dummy; + static inline void qspi_mpu_disable_all(void) { // Configure MPU to disable access to entire QSPI region, to prevent CPU // speculative execution from accessing this region and modifying QSPI registers. @@ -110,7 +112,9 @@ static inline void qspi_mpu_enable_mapped(void) { mpu_config_end(irq_state); } -void qspi_init(void) { +void qspi_init(uint8_t num_dummy) { + qspi_num_dummy = num_dummy; + qspi_mpu_disable_all(); // Configure pins @@ -158,7 +162,7 @@ void qspi_memory_map(void) { | 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction | 3 << QUADSPI_CCR_FMODE_Pos // memory-mapped mode | 3 << QUADSPI_CCR_DMODE_Pos // data on 4 lines - | 4 << QUADSPI_CCR_DCYC_Pos // 4 dummy cycles + | (2 * qspi_num_dummy) << QUADSPI_CCR_DCYC_Pos // 2N dummy cycles | 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte | 3 << QUADSPI_CCR_ABMODE_Pos // alternate byte on 4 lines | QSPI_ADSIZE << QUADSPI_CCR_ADSIZE_Pos @@ -193,7 +197,7 @@ static int qspi_ioctl(void *self_in, uint32_t cmd, uintptr_t arg) { (void)self_in; switch (cmd) { case MP_QSPI_IOCTL_INIT: - qspi_init(); + qspi_init(arg); break; case MP_QSPI_IOCTL_BUS_ACQUIRE: // Disable memory-mapped region during bus access @@ -369,7 +373,7 @@ static int qspi_read_cmd(void *self_in, uint8_t cmd, size_t len, uint32_t *dest) return 0; } -static int qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, size_t len, uint8_t *dest) { +static int qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, uint8_t num_dummy, size_t len, uint8_t *dest) { (void)self_in; uint8_t adsize = MICROPY_HW_SPI_ADDR_IS_32BIT(addr) ? 3 : 2; @@ -383,7 +387,7 @@ static int qspi_read_cmd_qaddr_qdata(void *self_in, uint8_t cmd, uint32_t addr, | 0 << QUADSPI_CCR_SIOO_Pos // send instruction every transaction | 1 << QUADSPI_CCR_FMODE_Pos // indirect read mode | 3 << QUADSPI_CCR_DMODE_Pos // data on 4 lines - | 4 << QUADSPI_CCR_DCYC_Pos // 4 dummy cycles + | (2 * num_dummy) << QUADSPI_CCR_DCYC_Pos // 2N dummy cycles | 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte | 3 << QUADSPI_CCR_ABMODE_Pos // alternate byte on 4 lines | adsize << QUADSPI_CCR_ADSIZE_Pos // 32 or 24-bit address size diff --git a/ports/stm32/qspi.h b/ports/stm32/qspi.h index a2d6b9f328db2..c8a3181653db7 100644 --- a/ports/stm32/qspi.h +++ b/ports/stm32/qspi.h @@ -33,7 +33,7 @@ extern const mp_qspi_proto_t qspi_proto; -void qspi_init(void); +void qspi_init(uint8_t num_dummy); void qspi_memory_map(void); void qspi_memory_map_exit(void); void qspi_memory_map_restart(void); From 1d83c8175680b911ab24ba834b7f8bcadaa5aa79 Mon Sep 17 00:00:00 2001 From: Damien George Date: Tue, 1 Apr 2025 14:31:26 +1100 Subject: [PATCH 4/8] stm32/vfs_rom_ioctl: Allow ROMFS configuration to be dynamic. Options for a board to configure ROMFS are: - Leave ROMFS disabled, do nothing. - Enable by defining `MICROPY_HW_ROMFS_ENABLE_PARTx` to 1 and then in the linker script define `_micropy_hw_romfs_partX_start` and `_micropy_hw_romfs_partX_size`. - Enable by defining `MICROPY_HW_ROMFS_ENABLE_PARTx` to 1 and also define `MICROPY_HW_ROMFS_PARTx_START` and `MICROPY_HW_ROMFS_PARTx_SIZE` which can be arbitrary expressions (not necessarily static) Signed-off-by: Damien George --- ports/stm32/vfs_rom_ioctl.c | 41 ++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/ports/stm32/vfs_rom_ioctl.c b/ports/stm32/vfs_rom_ioctl.c index 1fa4408c53796..7592aa22d622a 100644 --- a/ports/stm32/vfs_rom_ioctl.c +++ b/ports/stm32/vfs_rom_ioctl.c @@ -36,28 +36,32 @@ #if MICROPY_VFS_ROM_IOCTL -#if MICROPY_HW_ROMFS_ENABLE_PART0 && !defined(MICROPY_HW_ROMFS_PART0_START) -#define MICROPY_HW_ROMFS_PART0_START (uintptr_t)(&_micropy_hw_romfs_part0_start) -#define MICROPY_HW_ROMFS_PART0_SIZE (uintptr_t)(&_micropy_hw_romfs_part0_size) +#if MICROPY_HW_ROMFS_ENABLE_PART0 && defined(MICROPY_HW_ROMFS_PART0_START) +#define ROMFS0_DYNAMIC (1) +static MP_DEFINE_MEMORYVIEW_OBJ(romfs0_obj, 'B', 0, (uintptr_t)-1, (void *)-1); +#elif MICROPY_HW_ROMFS_ENABLE_PART0 && !defined(MICROPY_HW_ROMFS_PART0_START) +#define ROMFS0_DYNAMIC (0) extern uint8_t _micropy_hw_romfs_part0_start; extern uint8_t _micropy_hw_romfs_part0_size; +static const MP_DEFINE_MEMORYVIEW_OBJ(romfs0_obj, 'B', 0, (uintptr_t)&_micropy_hw_romfs_part0_size, (void *)&_micropy_hw_romfs_part0_start); #endif -#if MICROPY_HW_ROMFS_ENABLE_PART1 && !defined(MICROPY_HW_ROMFS_PART1_START) -#define MICROPY_HW_ROMFS_PART1_START (uintptr_t)(&_micropy_hw_romfs_part1_start) -#define MICROPY_HW_ROMFS_PART1_SIZE (uintptr_t)(&_micropy_hw_romfs_part1_size) +#if MICROPY_HW_ROMFS_ENABLE_PART1 && defined(MICROPY_HW_ROMFS_PART1_START) +#define ROMFS1_DYNAMIC (1) +static MP_DEFINE_MEMORYVIEW_OBJ(romfs1_obj, 'B', 0, (uintptr_t)-1, (void *)-1); +#elif MICROPY_HW_ROMFS_ENABLE_PART1 && !defined(MICROPY_HW_ROMFS_PART1_START) +#define ROMFS1_DYNAMIC (0) extern uint8_t _micropy_hw_romfs_part1_start; extern uint8_t _micropy_hw_romfs_part1_size; +static const MP_DEFINE_MEMORYVIEW_OBJ(romfs1_obj, 'B', 0, (uintptr_t)&_micropy_hw_romfs_part1_size, (void *)&_micropy_hw_romfs_part1_start); #endif -#define ROMFS_MEMORYVIEW(base, size) {{&mp_type_memoryview}, 'B', 0, (size), (void *)(base)} - -static const mp_obj_array_t romfs_obj_table[] = { +static const mp_obj_array_t *romfs_obj_table[] = { #if MICROPY_HW_ROMFS_ENABLE_PART0 - ROMFS_MEMORYVIEW(MICROPY_HW_ROMFS_PART0_START, MICROPY_HW_ROMFS_PART0_SIZE), + &romfs0_obj, #endif #if MICROPY_HW_ROMFS_ENABLE_PART1 - ROMFS_MEMORYVIEW(MICROPY_HW_ROMFS_PART1_START, MICROPY_HW_ROMFS_PART1_SIZE), + &romfs1_obj, #endif }; @@ -76,7 +80,20 @@ mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { return MP_OBJ_NEW_SMALL_INT(-MP_EINVAL); } - const mp_obj_array_t *romfs_obj = &romfs_obj_table[romfs_id]; + #if ROMFS0_DYNAMIC + if (romfs_id == 0) { + romfs0_obj.items = (void *)MICROPY_HW_ROMFS_PART0_START; + romfs0_obj.len = MICROPY_HW_ROMFS_PART0_SIZE; + } + #endif + #if ROMFS1_DYNAMIC + if (romfs_id == 1) { + romfs1_obj.items = (void *)MICROPY_HW_ROMFS_PART1_START; + romfs1_obj.len = MICROPY_HW_ROMFS_PART1_SIZE; + } + #endif + + const mp_obj_array_t *romfs_obj = romfs_obj_table[romfs_id]; uintptr_t romfs_base = (uintptr_t)romfs_obj->items; uintptr_t romfs_len = romfs_obj->len; From aa0945698b714c25f85b1234e0b03f34ac76c24c Mon Sep 17 00:00:00 2001 From: Damien George Date: Thu, 13 Mar 2025 11:09:01 +1100 Subject: [PATCH 5/8] stm32/qspi: Allow SPI flash size to be decided at runtime. Allows `MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2` and `MICROPY_HW_QSPI_MPU_REGION_SIZE` to be arbitrary expressions, eg function calls. The `storage.h` header needs to be included in case access to `spi_bdev_t` is needed by the macros. Signed-off-by: Damien George --- ports/stm32/qspi.c | 77 ++++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 36 deletions(-) diff --git a/ports/stm32/qspi.c b/ports/stm32/qspi.c index 1360d9b490d29..781aae803ef21 100644 --- a/ports/stm32/qspi.c +++ b/ports/stm32/qspi.c @@ -31,6 +31,7 @@ #include "mpu.h" #include "qspi.h" #include "pin_static_af.h" +#include "storage.h" #if defined(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2) @@ -50,18 +51,11 @@ #define MICROPY_HW_QSPI_CS_HIGH_CYCLES 2 // nCS stays high for 2 cycles #endif +// Region size in units of 1024*1024 bytes. #ifndef MICROPY_HW_QSPI_MPU_REGION_SIZE #define MICROPY_HW_QSPI_MPU_REGION_SIZE ((1 << (MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3)) >> 20) #endif -#if (MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3 - 1) >= 24 -#define QSPI_CMD 0xec -#define QSPI_ADSIZE 3 -#else -#define QSPI_CMD 0xeb -#define QSPI_ADSIZE 2 -#endif - static uint8_t qspi_num_dummy; static inline void qspi_mpu_disable_all(void) { @@ -83,32 +77,32 @@ static inline void qspi_mpu_enable_mapped(void) { // other enabled region overlaps the disabled subregion, and the access is // unprivileged or the background region is disabled, the MPU issues a fault. uint32_t irq_state = mpu_config_start(); - #if MICROPY_HW_QSPI_MPU_REGION_SIZE > 128 - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0xFF, MPU_REGION_SIZE_256MB)); - #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 64 - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_256MB)); - #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 32 - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_256MB)); - #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 16 - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); - #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 8 - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); - mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_32MB)); - #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 4 - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); - mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_32MB)); - #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 2 - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); - mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_32MB)); - #elif MICROPY_HW_QSPI_MPU_REGION_SIZE > 1 - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); - mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_32MB)); - mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_16MB)); - #else - mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); - mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_32MB)); - mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_4MB)); - #endif + if (MICROPY_HW_QSPI_MPU_REGION_SIZE > 128) { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0xFF, MPU_REGION_SIZE_256MB)); + } else if (MICROPY_HW_QSPI_MPU_REGION_SIZE > 64) { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_256MB)); + } else if (MICROPY_HW_QSPI_MPU_REGION_SIZE > 32) { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_256MB)); + } else if (MICROPY_HW_QSPI_MPU_REGION_SIZE > 16) { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + } else if (MICROPY_HW_QSPI_MPU_REGION_SIZE > 8) { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_32MB)); + } else if (MICROPY_HW_QSPI_MPU_REGION_SIZE > 4) { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_32MB)); + } else if (MICROPY_HW_QSPI_MPU_REGION_SIZE > 2) { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_32MB)); + } else if (MICROPY_HW_QSPI_MPU_REGION_SIZE > 1) { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x0F, MPU_REGION_SIZE_32MB)); + mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_16MB)); + } else { + mpu_config_region(MPU_REGION_QSPI1, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_256MB)); + mpu_config_region(MPU_REGION_QSPI2, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x01, MPU_REGION_SIZE_32MB)); + mpu_config_region(MPU_REGION_QSPI3, QSPI_MAP_ADDR, MPU_CONFIG_NOACCESS(0x03, MPU_REGION_SIZE_4MB)); + } mpu_config_end(irq_state); } @@ -155,6 +149,17 @@ void qspi_init(uint8_t num_dummy) { void qspi_memory_map(void) { // Enable memory-mapped mode + // Work out command to use for reads, based on size of the memory. + uint8_t cmd; + uint8_t adsize; + if ((MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3 - 1) >= 24) { + cmd = 0xec; + adsize = 3; + } else { + cmd = 0xeb; + adsize = 2; + } + QUADSPI->ABR = 0; // disable continuous read mode QUADSPI->CCR = @@ -165,10 +170,10 @@ void qspi_memory_map(void) { | (2 * qspi_num_dummy) << QUADSPI_CCR_DCYC_Pos // 2N dummy cycles | 0 << QUADSPI_CCR_ABSIZE_Pos // 8-bit alternate byte | 3 << QUADSPI_CCR_ABMODE_Pos // alternate byte on 4 lines - | QSPI_ADSIZE << QUADSPI_CCR_ADSIZE_Pos + | adsize << QUADSPI_CCR_ADSIZE_Pos | 3 << QUADSPI_CCR_ADMODE_Pos // address on 4 lines | 1 << QUADSPI_CCR_IMODE_Pos // instruction on 1 line - | QSPI_CMD << QUADSPI_CCR_INSTRUCTION_Pos + | cmd << QUADSPI_CCR_INSTRUCTION_Pos ; qspi_mpu_enable_mapped(); From de08190cb736f3bb1027d15bdf88135e49603c23 Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 2 Apr 2025 12:49:54 +1100 Subject: [PATCH 6/8] stm32/mboot: Allow USB strings to be dynamic. Signed-off-by: Damien George --- ports/stm32/mboot/main.c | 76 +++++++++++++++++++++++++++++++--------- 1 file changed, 60 insertions(+), 16 deletions(-) diff --git a/ports/stm32/mboot/main.c b/ports/stm32/mboot/main.c index 9bb2dcfcaf408..01f8892a514c8 100644 --- a/ports/stm32/mboot/main.c +++ b/ports/stm32/mboot/main.c @@ -429,38 +429,82 @@ void mp_hal_pin_config_speed(uint32_t port_pin, uint32_t speed) { || defined(STM32F723xx) \ || defined(STM32F732xx) \ || defined(STM32F733xx) -#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/04*016Kg,01*064Kg,07*128Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT +#define INTERNAL_FLASH_LAYOUT "@Internal Flash /0x08000000/04*016Kg,01*064Kg,07*128Kg" #elif defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) -#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/04*032Kg,01*128Kg,07*256Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT +#define INTERNAL_FLASH_LAYOUT "@Internal Flash /0x08000000/04*032Kg,01*128Kg,07*256Kg" #elif defined(STM32G0) -#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/256*02Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT +#define INTERNAL_FLASH_LAYOUT "@Internal Flash /0x08000000/256*02Kg" #elif defined(STM32H5) -#define FLASH_LAYOUT_TEMPLATE "@Internal Flash /0x08000000/???*08Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT +#define INTERNAL_FLASH_LAYOUT "@Internal Flash /0x08000000/???*08Kg" +#define INTERNAL_FLASH_LAYOUT_HAS_TEMPLATE (1) #elif defined(STM32H743xx) -#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/16*128Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT +#define INTERNAL_FLASH_LAYOUT "@Internal Flash /0x08000000/16*128Kg" #elif defined(STM32H750xx) -#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/01*128Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT +#define INTERNAL_FLASH_LAYOUT "@Internal Flash /0x08000000/01*128Kg" #elif defined(STM32WB) -#define FLASH_LAYOUT_STR "@Internal Flash /0x08000000/256*04Kg" MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT +#define INTERNAL_FLASH_LAYOUT "@Internal Flash /0x08000000/256*04Kg" #endif -#if !defined(FLASH_LAYOUT_STR) +#if INTERNAL_FLASH_LAYOUT_HAS_TEMPLATE \ + || defined(MBOOT_SPIFLASH_LAYOUT_DYNAMIC_MAX_LEN) \ + || defined(MBOOT_SPIFLASH2_LAYOUT_DYNAMIC_MAX_LEN) -#define FLASH_LAYOUT_STR_ALLOC (sizeof(FLASH_LAYOUT_TEMPLATE)) +#ifndef MBOOT_SPIFLASH_LAYOUT_DYNAMIC_MAX_LEN +#define MBOOT_SPIFLASH_LAYOUT_DYNAMIC_MAX_LEN (sizeof(MBOOT_SPIFLASH_LAYOUT) - 1) +#endif + +#ifndef MBOOT_SPIFLASH2_LAYOUT_DYNAMIC_MAX_LEN +#define MBOOT_SPIFLASH2_LAYOUT_DYNAMIC_MAX_LEN (sizeof(MBOOT_SPIFLASH2_LAYOUT) - 1) +#endif + +#define FLASH_LAYOUT_STR_ALLOC \ + ( \ + (sizeof(INTERNAL_FLASH_LAYOUT) - 1) \ + + MBOOT_SPIFLASH_LAYOUT_DYNAMIC_MAX_LEN \ + + MBOOT_SPIFLASH2_LAYOUT_DYNAMIC_MAX_LEN \ + + 1 \ + ) // Build the flash layout string from a template with total flash size inserted. -static size_t build_flash_layout_str(char *buf) { - size_t len = FLASH_LAYOUT_STR_ALLOC - 1; - memcpy(buf, FLASH_LAYOUT_TEMPLATE, len + 1); +static size_t build_flash_layout_str(uint8_t *buf) { + const char *internal_layout = INTERNAL_FLASH_LAYOUT; + size_t internal_layout_len = strlen(internal_layout); + + const char *spiflash_layout = MBOOT_SPIFLASH_LAYOUT; + size_t spiflash_layout_len = strlen(spiflash_layout); + + const char *spiflash2_layout = MBOOT_SPIFLASH2_LAYOUT; + size_t spiflash2_layout_len = strlen(spiflash2_layout); + + uint8_t *buf_orig = buf; + + memcpy(buf, internal_layout, internal_layout_len); + buf += internal_layout_len; + + #if INTERNAL_FLASH_LAYOUT_HAS_TEMPLATE unsigned int num_sectors = FLASH_SIZE / FLASH_SECTOR_SIZE; - buf += 31; // location of "???" in FLASH_LAYOUT_TEMPLATE + uint8_t *buf_size = buf_orig + 31; // location of "???" in FLASH_LAYOUT_TEMPLATE for (unsigned int i = 0; i < 3; ++i) { - *buf-- = '0' + num_sectors % 10; + *buf_size-- = '0' + num_sectors % 10; num_sectors /= 10; } - return len; + #endif + + memcpy(buf, spiflash_layout, spiflash_layout_len); + buf += spiflash_layout_len; + + memcpy(buf, spiflash2_layout, spiflash2_layout_len); + buf += spiflash2_layout_len; + + *buf++ = '\0'; + + return buf - buf_orig; } +#else + +#define FLASH_LAYOUT_STR INTERNAL_FLASH_LAYOUT MBOOT_SPIFLASH_LAYOUT MBOOT_SPIFLASH2_LAYOUT + #endif static bool flash_is_modifiable_addr_range(uint32_t addr, uint32_t len) { @@ -1188,7 +1232,7 @@ static uint8_t *pyb_usbdd_StrDescriptor(USBD_HandleTypeDef *pdev, uint8_t idx, u USBD_GetString((uint8_t *)FLASH_LAYOUT_STR, str_desc, length); #else { - char buf[FLASH_LAYOUT_STR_ALLOC]; + uint8_t buf[FLASH_LAYOUT_STR_ALLOC]; build_flash_layout_str(buf); USBD_GetString((uint8_t *)buf, str_desc, length); } From ed4833d495e1a328ef35edda1666799a9c84802c Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 2 Apr 2025 12:50:23 +1100 Subject: [PATCH 7/8] stm32/modmachine: Add SPI flash size to machine.info dump. Signed-off-by: Damien George --- ports/stm32/modmachine.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/ports/stm32/modmachine.c b/ports/stm32/modmachine.c index 7c1c4da60bff2..620ae468cb9b3 100644 --- a/ports/stm32/modmachine.c +++ b/ports/stm32/modmachine.c @@ -247,6 +247,14 @@ static mp_obj_t machine_info(size_t n_args, const mp_obj_t *args) { mp_printf(print, " 1=%u 2=%u m=%u\n", info.num_1block, info.num_2block, info.max_block); } + // SPI flash size + #if defined(MICROPY_HW_SPIFLASH_SIZE_BITS) + mp_printf(print, "SPI flash size: %d\n", MICROPY_HW_SPIFLASH_SIZE_BITS / 8); + #endif + #if defined(MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2) + mp_printf(print, "QSPI flash size: %d\n", 1 << (MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 - 3)); + #endif + // free space on flash { #if MICROPY_VFS_FAT From db854270719bfa4dda003d38893c1b8f39bf58de Mon Sep 17 00:00:00 2001 From: Damien George Date: Wed, 2 Apr 2025 12:48:48 +1100 Subject: [PATCH 8/8] stm32/boards/PYBD_SF6: Support boards with larger SPI flash. There are some newer PYBD_SF6 being produced which have a larger flash, namely two of 8MiB (instead of the older ones with two of 2MiB). This commit adds support for these boards. The idea is to have the same PYBD_SF6 firmware run on both old and new boards. That means autodetecting the flash at start-up and configuring all the relevant SPI/QSPI parameters, including for ROMFS and mboot. Signed-off-by: Damien George --- ports/stm32/boards/PYBD_SF6/board_init.c | 88 +++++++++++++++++++++ ports/stm32/boards/PYBD_SF6/f767.ld | 3 +- ports/stm32/boards/PYBD_SF6/mpconfigboard.h | 50 ++++++++++++ 3 files changed, 139 insertions(+), 2 deletions(-) diff --git a/ports/stm32/boards/PYBD_SF6/board_init.c b/ports/stm32/boards/PYBD_SF6/board_init.c index c7a9f28006be3..836c4db8b5d24 100644 --- a/ports/stm32/boards/PYBD_SF6/board_init.c +++ b/ports/stm32/boards/PYBD_SF6/board_init.c @@ -1 +1,89 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2025 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include "boardctrl.h" +#include "qspi.h" + +#if BUILDING_MBOOT +#include "mboot/mboot.h" +#endif + +// Use PYBD_SF2 as base configuration. #include "boards/PYBD_SF2/board_init.c" + +// Adesto AT25SF161 16-MBit. +static const mp_spiflash_chip_params_t chip_params_at25sf161 = { + .jedec_id = 0x01861f, + .memory_size_bytes_log2 = 21, + .qspi_prescaler = 3, // maximum frequency 104MHz + .qread_num_dummy = 2, +}; + +// Infineon S25FL064 64-MBit. +static const mp_spiflash_chip_params_t chip_params_s25fl064 = { + .jedec_id = 0x176001, + .memory_size_bytes_log2 = 23, + .qspi_prescaler = 2, // maximum frequency 108MHz + .qread_num_dummy = 4, +}; + +// Selection of possible SPI flash chips. +static const mp_spiflash_chip_params_t *const chip_params_table[] = { + &chip_params_at25sf161, + &chip_params_s25fl064, +}; + +void board_early_init_sf6(void) { + // Initialise default SPI flash parameters. + MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0 = &chip_params_at25sf161; + MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1 = &chip_params_at25sf161; + + // Continue with standard board early init. + board_early_init(); +} + +int mp_spiflash_detect(mp_spiflash_t *spiflash, int ret, uint32_t devid) { + if (ret != 0) { + // Could not identify flash. Succeed anyway using default chip parameters. + return 0; + } + + // Try to detect the SPI flash based on the JEDEC id. + for (size_t i = 0; i < MP_ARRAY_SIZE(chip_params_table); ++i) { + if (devid == chip_params_table[i]->jedec_id) { + spiflash->chip_params = chip_params_table[i]; + if (spiflash->config->bus_kind == MP_SPIFLASH_BUS_QSPI) { + // Reinitialise the QSPI but to set new size, prescaler and dummy bytes. + uint8_t num_dummy = spiflash->chip_params->qread_num_dummy; + spiflash->config->bus.u_qspi.proto->ioctl(spiflash->config->bus.u_qspi.data, MP_QSPI_IOCTL_INIT, num_dummy); + } + break; + } + } + + return 0; +} diff --git a/ports/stm32/boards/PYBD_SF6/f767.ld b/ports/stm32/boards/PYBD_SF6/f767.ld index 0ee6cf76355fe..37fb3715d67ee 100644 --- a/ports/stm32/boards/PYBD_SF6/f767.ld +++ b/ports/stm32/boards/PYBD_SF6/f767.ld @@ -18,7 +18,7 @@ MEMORY { FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K FLASH_APP (rx) : ORIGIN = 0x08008000, LENGTH = 2016K /* sectors 1-11 3x32K 1*128K 7*256K */ - FLASH_ROMFS (rx): ORIGIN = 0x90000000, LENGTH = 2048K /* external QSPI */ + FLASH_ROMFS (rx): ORIGIN = 0x90000000, LENGTH = 2048K /* external QSPI, at least 2MiB */ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 512K /* DTCM=128k, SRAM1=368K, SRAM2=16K */ } @@ -39,6 +39,5 @@ _heap_end = _sstack; /* ROMFS location */ _micropy_hw_romfs_part0_start = ORIGIN(FLASH_ROMFS); -_micropy_hw_romfs_part0_size = LENGTH(FLASH_ROMFS); INCLUDE common_bl.ld diff --git a/ports/stm32/boards/PYBD_SF6/mpconfigboard.h b/ports/stm32/boards/PYBD_SF6/mpconfigboard.h index 45261523bdaa0..8cd1e52d3bd78 100644 --- a/ports/stm32/boards/PYBD_SF6/mpconfigboard.h +++ b/ports/stm32/boards/PYBD_SF6/mpconfigboard.h @@ -69,3 +69,53 @@ #define MICROPY_HW_ETH_RMII_TX_EN (pyb_pin_W8) #define MICROPY_HW_ETH_RMII_TXD0 (pyb_pin_W45) #define MICROPY_HW_ETH_RMII_TXD1 (pyb_pin_W49) + +// The below code reconfigures SPI flash for dynamic size detection. + +#undef MICROPY_BOARD_EARLY_INIT +#undef MICROPY_HW_SPIFLASH_SIZE_BITS +#undef MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 +#undef MBOOT_SPIFLASH_BYTE_SIZE +#undef MBOOT_SPIFLASH_LAYOUT +#undef MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE +#undef MBOOT_SPIFLASH2_BYTE_SIZE +#undef MBOOT_SPIFLASH2_LAYOUT +#undef MBOOT_SPIFLASH2_ERASE_BLOCKS_PER_PAGE + +// These are convenience macros to refer to the SPI flash chip parameters for the external SPI flash. +#define MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0 (spi_bdev.spiflash.chip_params) // SPI flash #1, R/W storage +#define MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1 (spi_bdev2.spiflash.chip_params) // SPI flash #2, memory mapped + +// Early init is needed to initialise the default SPI flash chip parameters. +#define MICROPY_BOARD_EARLY_INIT board_early_init_sf6 + +// Enable dynamic detection of SPI flash. +#define MICROPY_HW_SPIFLASH_CHIP_PARAMS (1) +#define MICROPY_HW_SPIFLASH_DETECT_DEVICE (1) + +// Settings for SPI flash #1. +#define MICROPY_HW_SPIFLASH_SIZE_BITS (1 << (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2 + 3)) + +// Settings for SPI flash #2. +#define MICROPY_HW_QSPI_PRESCALER (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->qspi_prescaler) +#define MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2 (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2 + 3) + +// ROMFS partition 0 is dynamically sized (SPI flash #2). +#define MICROPY_HW_ROMFS_PART0_START (uintptr_t)(&_micropy_hw_romfs_part0_start) +#define MICROPY_HW_ROMFS_PART0_SIZE (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2) + +// Mboot SPI flash #1 configuration. +#define MBOOT_SPIFLASH_LAYOUT_DYNAMIC_MAX_LEN (20) +#define MBOOT_SPIFLASH_LAYOUT (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2 == 21 ? "/0x80000000/512*4Kg" : "/0x80000000/2048*4Kg") +#define MBOOT_SPIFLASH_BYTE_SIZE (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS0->memory_size_bytes_log2) +#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1) + +// Mboot SPI flash #2 configuration. +#define MBOOT_SPIFLASH2_LAYOUT_DYNAMIC_MAX_LEN (20) +#define MBOOT_SPIFLASH2_LAYOUT (MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2 == 21 ? "/0x90000000/512*4Kg" : "/0x90000000/2048*4Kg") +#define MBOOT_SPIFLASH2_BYTE_SIZE (1 << MICROPY_BOARD_SPIFLASH_CHIP_PARAMS1->memory_size_bytes_log2) +#define MBOOT_SPIFLASH2_ERASE_BLOCKS_PER_PAGE (1) + +extern unsigned char _micropy_hw_romfs_part0_start; + +void board_early_init_sf6(void);