/*

* Copyright 2012 Advanced Micro Devices, Inc.

*

* Permission is hereby granted, free of charge, to any person obtaining a

* copy of this software and associated documentation files (the "Software"),

* to deal in the Software without restriction, including without limitation

* the rights to use, copy, modify, merge, publish, distribute, sublicense,

* and/or sell copies of the Software, and to permit persons to whom the

* Software is furnished to do so, subject to the following conditions:

*

* The above copyright notice and this permission notice shall be included in

* all copies or substantial portions of the Software.

*

* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

* OTHER DEALINGS IN THE SOFTWARE.

*

* Authors: Alex Deucher

*/

#ifndef CIK_H

#define CIK_H

#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001

#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003

#define CIK_RB_BITMAP_WIDTH_PER_SH 2

#define HAWAII_RB_BITMAP_WIDTH_PER_SH 4

/* DIDT IND registers */

#define DIDT_SQ_CTRL0 0x0

# define DIDT_CTRL_EN (1 << 0)

#define DIDT_DB_CTRL0 0x20

#define DIDT_TD_CTRL0 0x40

#define DIDT_TCP_CTRL0 0x60

/* SMC IND registers */

#define DPM_TABLE_475 0x3F768

# define SamuBootLevel(x) ((x) << 0)

# define SamuBootLevel_MASK 0x000000ff

# define SamuBootLevel_SHIFT 0

# define AcpBootLevel(x) ((x) << 8)

# define AcpBootLevel_MASK 0x0000ff00

# define AcpBootLevel_SHIFT 8

# define VceBootLevel(x) ((x) << 16)

# define VceBootLevel_MASK 0x00ff0000

# define VceBootLevel_SHIFT 16

# define UvdBootLevel(x) ((x) << 24)

# define UvdBootLevel_MASK 0xff000000

# define UvdBootLevel_SHIFT 24

#define FIRMWARE_FLAGS 0x3F800

# define INTERRUPTS_ENABLED (1 << 0)

#define NB_DPM_CONFIG_1 0x3F9E8

# define Dpm0PgNbPsLo(x) ((x) << 0)

# define Dpm0PgNbPsLo_MASK 0x000000ff

# define Dpm0PgNbPsLo_SHIFT 0

# define Dpm0PgNbPsHi(x) ((x) << 8)

# define Dpm0PgNbPsHi_MASK 0x0000ff00

# define Dpm0PgNbPsHi_SHIFT 8

# define DpmXNbPsLo(x) ((x) << 16)

# define DpmXNbPsLo_MASK 0x00ff0000

# define DpmXNbPsLo_SHIFT 16

# define DpmXNbPsHi(x) ((x) << 24)

# define DpmXNbPsHi_MASK 0xff000000

# define DpmXNbPsHi_SHIFT 24

#define SMC_SYSCON_RESET_CNTL 0x80000000

# define RST_REG (1 << 0)

#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004

# define CK_DISABLE (1 << 0)

# define CKEN (1 << 24)

#define SMC_SYSCON_MISC_CNTL 0x80000010

#define SMC_SYSCON_MSG_ARG_0 0x80000068

#define SMC_PC_C 0x80000370

#define SMC_SCRATCH9 0x80000424

#define RCU_UC_EVENTS 0xC0000004

# define BOOT_SEQ_DONE (1 << 7)

#define GENERAL_PWRMGT 0xC0200000

# define GLOBAL_PWRMGT_EN (1 << 0)

# define STATIC_PM_EN (1 << 1)

# define THERMAL_PROTECTION_DIS (1 << 2)

# define THERMAL_PROTECTION_TYPE (1 << 3)

# define SW_SMIO_INDEX(x) ((x) << 6)

# define SW_SMIO_INDEX_MASK (1 << 6)

# define SW_SMIO_INDEX_SHIFT 6

# define VOLT_PWRMGT_EN (1 << 10)

# define GPU_COUNTER_CLK (1 << 15)

# define DYN_SPREAD_SPECTRUM_EN (1 << 23)

#define CNB_PWRMGT_CNTL 0xC0200004

# define GNB_SLOW_MODE(x) ((x) << 0)

# define GNB_SLOW_MODE_MASK (3 << 0)

# define GNB_SLOW_MODE_SHIFT 0

# define GNB_SLOW (1 << 2)

# define FORCE_NB_PS1 (1 << 3)

# define DPM_ENABLED (1 << 4)

#define SCLK_PWRMGT_CNTL 0xC0200008

# define SCLK_PWRMGT_OFF (1 << 0)

# define RESET_BUSY_CNT (1 << 4)

# define RESET_SCLK_CNT (1 << 5)

# define DYNAMIC_PM_EN (1 << 21)

#define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014

# define CURRENT_STATE_MASK (0xf << 4)

# define CURRENT_STATE_SHIFT 4

# define CURR_MCLK_INDEX_MASK (0xf << 8)

# define CURR_MCLK_INDEX_SHIFT 8

# define CURR_SCLK_INDEX_MASK (0x1f << 16)

# define CURR_SCLK_INDEX_SHIFT 16

#define CG_SSP 0xC0200044

# define SST(x) ((x) << 0)

# define SST_MASK (0xffff << 0)

# define SSTU(x) ((x) << 16)

# define SSTU_MASK (0xf << 16)

#define CG_DISPLAY_GAP_CNTL 0xC0200060

# define DISP_GAP(x) ((x) << 0)

# define DISP_GAP_MASK (3 << 0)

# define VBI_TIMER_COUNT(x) ((x) << 4)

# define VBI_TIMER_COUNT_MASK (0x3fff << 4)

# define VBI_TIMER_UNIT(x) ((x) << 20)

# define VBI_TIMER_UNIT_MASK (7 << 20)

# define DISP_GAP_MCHG(x) ((x) << 24)

# define DISP_GAP_MCHG_MASK (3 << 24)

#define SMU_VOLTAGE_STATUS 0xC0200094

# define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)

# define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1

#define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0

# define CURR_PCIE_INDEX_MASK (0xf << 24)

# define CURR_PCIE_INDEX_SHIFT 24

#define CG_ULV_PARAMETER 0xC0200158

#define CG_FTV_0 0xC02001A8

#define CG_FTV_1 0xC02001AC

#define CG_FTV_2 0xC02001B0

#define CG_FTV_3 0xC02001B4

#define CG_FTV_4 0xC02001B8

#define CG_FTV_5 0xC02001BC

#define CG_FTV_6 0xC02001C0

#define CG_FTV_7 0xC02001C4

#define CG_DISPLAY_GAP_CNTL2 0xC0200230

#define LCAC_SX0_OVR_SEL 0xC0400D04

#define LCAC_SX0_OVR_VAL 0xC0400D08

#define LCAC_MC0_CNTL 0xC0400D30

#define LCAC_MC0_OVR_SEL 0xC0400D34

#define LCAC_MC0_OVR_VAL 0xC0400D38

#define LCAC_MC1_CNTL 0xC0400D3C

#define LCAC_MC1_OVR_SEL 0xC0400D40

#define LCAC_MC1_OVR_VAL 0xC0400D44

#define LCAC_MC2_OVR_SEL 0xC0400D4C

#define LCAC_MC2_OVR_VAL 0xC0400D50

#define LCAC_MC3_OVR_SEL 0xC0400D58

#define LCAC_MC3_OVR_VAL 0xC0400D5C

#define LCAC_CPL_CNTL 0xC0400D80

#define LCAC_CPL_OVR_SEL 0xC0400D84

#define LCAC_CPL_OVR_VAL 0xC0400D88

/* dGPU */

#define CG_THERMAL_CTRL 0xC0300004

#define DPM_EVENT_SRC(x) ((x) << 0)

#define DPM_EVENT_SRC_MASK (7 << 0)

#define DIG_THERM_DPM(x) ((x) << 14)

#define DIG_THERM_DPM_MASK 0x003FC000

#define DIG_THERM_DPM_SHIFT 14

#define CG_THERMAL_INT 0xC030000C

#define CI_DIG_THERM_INTH(x) ((x) << 8)

#define CI_DIG_THERM_INTH_MASK 0x0000FF00

#define CI_DIG_THERM_INTH_SHIFT 8

#define CI_DIG_THERM_INTL(x) ((x) << 16)

#define CI_DIG_THERM_INTL_MASK 0x00FF0000

#define CI_DIG_THERM_INTL_SHIFT 16

#define THERM_INT_MASK_HIGH (1 << 24)

#define THERM_INT_MASK_LOW (1 << 25)

#define CG_MULT_THERMAL_STATUS 0xC0300014

#define ASIC_MAX_TEMP(x) ((x) << 0)

#define ASIC_MAX_TEMP_MASK 0x000001ff

#define ASIC_MAX_TEMP_SHIFT 0

#define CTF_TEMP(x) ((x) << 9)

#define CTF_TEMP_MASK 0x0003fe00

#define CTF_TEMP_SHIFT 9

#define CG_ECLK_CNTL 0xC05000AC

# define ECLK_DIVIDER_MASK 0x7f

# define ECLK_DIR_CNTL_EN (1 << 8)

#define CG_ECLK_STATUS 0xC05000B0

# define ECLK_STATUS (1 << 0)

#define CG_SPLL_FUNC_CNTL 0xC0500140

#define SPLL_RESET (1 << 0)

#define SPLL_PWRON (1 << 1)

#define SPLL_BYPASS_EN (1 << 3)

#define SPLL_REF_DIV(x) ((x) << 5)

#define SPLL_REF_DIV_MASK (0x3f << 5)

#define SPLL_PDIV_A(x) ((x) << 20)

#define SPLL_PDIV_A_MASK (0x7f << 20)

#define SPLL_PDIV_A_SHIFT 20

#define CG_SPLL_FUNC_CNTL_2 0xC0500144

#define SCLK_MUX_SEL(x) ((x) << 0)

#define SCLK_MUX_SEL_MASK (0x1ff << 0)

#define CG_SPLL_FUNC_CNTL_3 0xC0500148

#define SPLL_FB_DIV(x) ((x) << 0)

#define SPLL_FB_DIV_MASK (0x3ffffff << 0)

#define SPLL_FB_DIV_SHIFT 0

#define SPLL_DITHEN (1 << 28)

#define CG_SPLL_FUNC_CNTL_4 0xC050014C

#define CG_SPLL_SPREAD_SPECTRUM 0xC0500164

#define SSEN (1 << 0)

#define CLK_S(x) ((x) << 4)

#define CLK_S_MASK (0xfff << 4)

#define CLK_S_SHIFT 4

#define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168

#define CLK_V(x) ((x) << 0)

#define CLK_V_MASK (0x3ffffff << 0)

#define CLK_V_SHIFT 0

#define MPLL_BYPASSCLK_SEL 0xC050019C

# define MPLL_CLKOUT_SEL(x) ((x) << 8)

# define MPLL_CLKOUT_SEL_MASK 0xFF00

#define CG_CLKPIN_CNTL 0xC05001A0

# define XTALIN_DIVIDE (1 << 1)

# define BCLK_AS_XCLK (1 << 2)

#define CG_CLKPIN_CNTL_2 0xC05001A4

# define FORCE_BIF_REFCLK_EN (1 << 3)

# define MUX_TCLK_TO_XCLK (1 << 8)

#define THM_CLK_CNTL 0xC05001A8

# define CMON_CLK_SEL(x) ((x) << 0)

# define CMON_CLK_SEL_MASK 0xFF

# define TMON_CLK_SEL(x) ((x) << 8)

# define TMON_CLK_SEL_MASK 0xFF00

#define MISC_CLK_CTRL 0xC05001AC

# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)

# define DEEP_SLEEP_CLK_SEL_MASK 0xFF

# define ZCLK_SEL(x) ((x) << 8)

# define ZCLK_SEL_MASK 0xFF00

/* KV/KB */

#define CG_THERMAL_INT_CTRL 0xC2100028

#define DIG_THERM_INTH(x) ((x) << 0)

#define DIG_THERM_INTH_MASK 0x000000FF

#define DIG_THERM_INTH_SHIFT 0

#define DIG_THERM_INTL(x) ((x) << 8)

#define DIG_THERM_INTL_MASK 0x0000FF00

#define DIG_THERM_INTL_SHIFT 8

#define THERM_INTH_MASK (1 << 24)

#define THERM_INTL_MASK (1 << 25)

/* PCIE registers idx/data 0x38/0x3c */

#define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */

# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)

# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)

# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7

# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)

# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)

# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10

# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)

# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)

# define PLL_RAMP_UP_TIME_0_SHIFT 24

#define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */

# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)

# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)

# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7

# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)

# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)

# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10

# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)

# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)

# define PLL_RAMP_UP_TIME_1_SHIFT 24

#define PCIE_CNTL2 0x1001001c /* PCIE */

# define SLV_MEM_LS_EN (1 << 16)

# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)

# define MST_MEM_LS_EN (1 << 18)

# define REPLAY_MEM_LS_EN (1 << 19)

#define PCIE_LC_STATUS1 0x1400028 /* PCIE */

# define LC_REVERSE_RCVR (1 << 0)

# define LC_REVERSE_XMIT (1 << 1)

# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)

# define LC_OPERATING_LINK_WIDTH_SHIFT 2

# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)

# define LC_DETECTED_LINK_WIDTH_SHIFT 5

#define PCIE_P_CNTL 0x1400040 /* PCIE */

# define P_IGNORE_EDB_ERR (1 << 6)

#define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */

#define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */

#define PCIE_LC_CNTL 0x100100A0 /* PCIE */

# define LC_L0S_INACTIVITY(x) ((x) << 8)

# define LC_L0S_INACTIVITY_MASK (0xf << 8)

# define LC_L0S_INACTIVITY_SHIFT 8

# define LC_L1_INACTIVITY(x) ((x) << 12)

# define LC_L1_INACTIVITY_MASK (0xf << 12)

# define LC_L1_INACTIVITY_SHIFT 12

# define LC_PMI_TO_L1_DIS (1 << 16)

# define LC_ASPM_TO_L1_DIS (1 << 24)

#define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */

# define LC_LINK_WIDTH_SHIFT 0

# define LC_LINK_WIDTH_MASK 0x7

# define LC_LINK_WIDTH_X0 0

# define LC_LINK_WIDTH_X1 1

# define LC_LINK_WIDTH_X2 2

# define LC_LINK_WIDTH_X4 3

# define LC_LINK_WIDTH_X8 4

# define LC_LINK_WIDTH_X16 6

# define LC_LINK_WIDTH_RD_SHIFT 4

# define LC_LINK_WIDTH_RD_MASK 0x70

# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)

# define LC_RECONFIG_NOW (1 << 8)

# define LC_RENEGOTIATION_SUPPORT (1 << 9)

# define LC_RENEGOTIATE_EN (1 << 10)

# define LC_SHORT_RECONFIG_EN (1 << 11)

# define LC_UPCONFIGURE_SUPPORT (1 << 12)

# define LC_UPCONFIGURE_DIS (1 << 13)

# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)

# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)

# define LC_DYN_LANES_PWR_STATE_SHIFT 21

#define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */

# define LC_XMIT_N_FTS(x) ((x) << 0)

# define LC_XMIT_N_FTS_MASK (0xff << 0)

# define LC_XMIT_N_FTS_SHIFT 0

# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)

# define LC_N_FTS_MASK (0xff << 24)

#define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */

# define LC_GEN2_EN_STRAP (1 << 0)

# define LC_GEN3_EN_STRAP (1 << 1)

# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)

# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)

# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3

# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)

# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)

# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)

# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)

# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)

# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10

# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */

# define LC_CURRENT_DATA_RATE_SHIFT 13

# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)

# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)

# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)

# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)

# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)

#define PCIE_LC_CNTL2 0x100100B1 /* PCIE */

# define LC_ALLOW_PDWN_IN_L1 (1 << 17)

# define LC_ALLOW_PDWN_IN_L23 (1 << 18)

#define PCIE_LC_CNTL3 0x100100B5 /* PCIE */

# define LC_GO_TO_RECOVERY (1 << 30)

#define PCIE_LC_CNTL4 0x100100B6 /* PCIE */

# define LC_REDO_EQ (1 << 5)

# define LC_SET_QUIESCE (1 << 13)

/* direct registers */

#define PCIE_INDEX 0x38

#define PCIE_DATA 0x3C

#define SMC_IND_INDEX_0 0x200

#define SMC_IND_DATA_0 0x204

#define SMC_IND_ACCESS_CNTL 0x240

#define AUTO_INCREMENT_IND_0 (1 << 0)

#define SMC_MESSAGE_0 0x250

#define SMC_MSG_MASK 0xffff

#define SMC_RESP_0 0x254

#define SMC_RESP_MASK 0xffff

#define SMC_MSG_ARG_0 0x290

#define VGA_HDP_CONTROL 0x328

#define VGA_MEMORY_DISABLE (1 << 4)

#define DMIF_ADDR_CALC 0xC00

#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0

# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)

# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)

#define SRBM_GFX_CNTL 0xE44

#define PIPEID(x) ((x) << 0)

#define MEID(x) ((x) << 2)

#define VMID(x) ((x) << 4)

#define QUEUEID(x) ((x) << 8)

#define SRBM_STATUS2 0xE4C

#define SDMA_BUSY (1 << 5)

#define SDMA1_BUSY (1 << 6)

#define SRBM_STATUS 0xE50

#define UVD_RQ_PENDING (1 << 1)

#define GRBM_RQ_PENDING (1 << 5)

#define VMC_BUSY (1 << 8)

#define MCB_BUSY (1 << 9)

#define MCB_NON_DISPLAY_BUSY (1 << 10)

#define MCC_BUSY (1 << 11)

#define MCD_BUSY (1 << 12)

#define SEM_BUSY (1 << 14)

#define IH_BUSY (1 << 17)

#define UVD_BUSY (1 << 19)

#define SRBM_SOFT_RESET 0xE60

#define SOFT_RESET_BIF (1 << 1)

#define SOFT_RESET_R0PLL (1 << 4)

#define SOFT_RESET_DC (1 << 5)

#define SOFT_RESET_SDMA1 (1 << 6)

#define SOFT_RESET_GRBM (1 << 8)

#define SOFT_RESET_HDP (1 << 9)

#define SOFT_RESET_IH (1 << 10)

#define SOFT_RESET_MC (1 << 11)

#define SOFT_RESET_ROM (1 << 14)

#define SOFT_RESET_SEM (1 << 15)

#define SOFT_RESET_VMC (1 << 17)

#define SOFT_RESET_SDMA (1 << 20)

#define SOFT_RESET_TST (1 << 21)

#define SOFT_RESET_REGBB (1 << 22)

#define SOFT_RESET_ORB (1 << 23)

#define SOFT_RESET_VCE (1 << 24)

#define VM_L2_CNTL 0x1400

#define ENABLE_L2_CACHE (1 << 0)

#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)

#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)

#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)

#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)

#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)

#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)

#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)

#define VM_L2_CNTL2 0x1404

#define INVALIDATE_ALL_L1_TLBS (1 << 0)

#define INVALIDATE_L2_CACHE (1 << 1)

#define INVALIDATE_CACHE_MODE(x) ((x) << 26)

#define INVALIDATE_PTE_AND_PDE_CACHES 0

#define INVALIDATE_ONLY_PTE_CACHES 1

#define INVALIDATE_ONLY_PDE_CACHES 2

#define VM_L2_CNTL3 0x1408

#define BANK_SELECT(x) ((x) << 0)

#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)

#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)

#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)

#define VM_L2_STATUS 0x140C

#define L2_BUSY (1 << 0)

#define VM_CONTEXT0_CNTL 0x1410

#define ENABLE_CONTEXT (1 << 0)

#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)

#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)

#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)

#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)

#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)

#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)

#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)

#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)

#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)

#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)

#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)

#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)

#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)

#define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)

#define VM_CONTEXT1_CNTL 0x1414

#define VM_CONTEXT0_CNTL2 0x1430

#define VM_CONTEXT1_CNTL2 0x1434

#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438

#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c

#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440

#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444

#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448

#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c

#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450

#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454

#define VM_INVALIDATE_REQUEST 0x1478

#define VM_INVALIDATE_RESPONSE 0x147c

#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC

#define PROTECTIONS_MASK (0xf << 0)

#define PROTECTIONS_SHIFT 0

/* bit 0: range

* bit 1: pde0

* bit 2: valid

* bit 3: read

* bit 4: write

*/

#define MEMORY_CLIENT_ID_MASK (0xff << 12)

#define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12)

#define MEMORY_CLIENT_ID_SHIFT 12

#define MEMORY_CLIENT_RW_MASK (1 << 24)

#define MEMORY_CLIENT_RW_SHIFT 24

#define FAULT_VMID_MASK (0xf << 25)

#define FAULT_VMID_SHIFT 25

#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4

#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC

#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518

#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c

#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c

#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540

#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544

#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548

#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c

#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550

#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554

#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558

#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c

#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560

#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C

#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580

#define VM_L2_CG 0x15c0

#define MC_CG_ENABLE (1 << 18)

#define MC_LS_ENABLE (1 << 19)

#define MC_SHARED_CHMAP 0x2004

#define NOOFCHAN_SHIFT 12

#define NOOFCHAN_MASK 0x0000f000

#define MC_SHARED_CHREMAP 0x2008

#define CHUB_CONTROL 0x1864

#define BYPASS_VM (1 << 0)

#define MC_VM_FB_LOCATION 0x2024

#define MC_VM_AGP_TOP 0x2028

#define MC_VM_AGP_BOT 0x202C

#define MC_VM_AGP_BASE 0x2030

#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034

#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038

#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C

#define MC_VM_MX_L1_TLB_CNTL 0x2064

#define ENABLE_L1_TLB (1 << 0)

#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)

#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)

#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)

#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)

#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)

#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)

#define MC_VM_FB_OFFSET 0x2068

#define MC_SHARED_BLACKOUT_CNTL 0x20ac

#define MC_HUB_MISC_HUB_CG 0x20b8

#define MC_HUB_MISC_VM_CG 0x20bc

#define MC_HUB_MISC_SIP_CG 0x20c0

#define MC_XPB_CLK_GAT 0x2478

#define MC_CITF_MISC_RD_CG 0x2648

#define MC_CITF_MISC_WR_CG 0x264c

#define MC_CITF_MISC_VM_CG 0x2650

#define MC_ARB_RAMCFG 0x2760

#define NOOFBANK_SHIFT 0

#define NOOFBANK_MASK 0x00000003

#define NOOFRANK_SHIFT 2

#define NOOFRANK_MASK 0x00000004

#define NOOFROWS_SHIFT 3

#define NOOFROWS_MASK 0x00000038

#define NOOFCOLS_SHIFT 6

#define NOOFCOLS_MASK 0x000000C0

#define CHANSIZE_SHIFT 8

#define CHANSIZE_MASK 0x00000100

#define NOOFGROUPS_SHIFT 12

#define NOOFGROUPS_MASK 0x00001000

#define MC_ARB_DRAM_TIMING 0x2774

#define MC_ARB_DRAM_TIMING2 0x2778

#define MC_ARB_BURST_TIME 0x2808

#define STATE0(x) ((x) << 0)

#define STATE0_MASK (0x1f << 0)

#define STATE0_SHIFT 0

#define STATE1(x) ((x) << 5)

#define STATE1_MASK (0x1f << 5)

#define STATE1_SHIFT 5

#define STATE2(x) ((x) << 10)

#define STATE2_MASK (0x1f << 10)

#define STATE2_SHIFT 10

#define STATE3(x) ((x) << 15)

#define STATE3_MASK (0x1f << 15)

#define STATE3_SHIFT 15

#define MC_SEQ_RAS_TIMING 0x28a0

#define MC_SEQ_CAS_TIMING 0x28a4

#define MC_SEQ_MISC_TIMING 0x28a8

#define MC_SEQ_MISC_TIMING2 0x28ac

#define MC_SEQ_PMG_TIMING 0x28b0

#define MC_SEQ_RD_CTL_D0 0x28b4

#define MC_SEQ_RD_CTL_D1 0x28b8

#define MC_SEQ_WR_CTL_D0 0x28bc

#define MC_SEQ_WR_CTL_D1 0x28c0

#define MC_SEQ_SUP_CNTL 0x28c8

#define RUN_MASK (1 << 0)

#define MC_SEQ_SUP_PGM 0x28cc

#define MC_PMG_AUTO_CMD 0x28d0

#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8

#define TRAIN_DONE_D0 (1 << 30)

#define TRAIN_DONE_D1 (1 << 31)

#define MC_IO_PAD_CNTL_D0 0x29d0

#define MEM_FALL_OUT_CMD (1 << 8)

#define MC_SEQ_MISC0 0x2a00

#define MC_SEQ_MISC0_VEN_ID_SHIFT 8

#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00

#define MC_SEQ_MISC0_VEN_ID_VALUE 3

#define MC_SEQ_MISC0_REV_ID_SHIFT 12

#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000

#define MC_SEQ_MISC0_REV_ID_VALUE 1

#define MC_SEQ_MISC0_GDDR5_SHIFT 28

#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000

#define MC_SEQ_MISC0_GDDR5_VALUE 5

#define MC_SEQ_MISC1 0x2a04

#define MC_SEQ_RESERVE_M 0x2a08

#define MC_PMG_CMD_EMRS 0x2a0c

#define MC_SEQ_IO_DEBUG_INDEX 0x2a44

#define MC_SEQ_IO_DEBUG_DATA 0x2a48

#define MC_SEQ_MISC5 0x2a54

#define MC_SEQ_MISC6 0x2a58

#define MC_SEQ_MISC7 0x2a64

#define MC_SEQ_RAS_TIMING_LP 0x2a6c

#define MC_SEQ_CAS_TIMING_LP 0x2a70

#define MC_SEQ_MISC_TIMING_LP 0x2a74

#define MC_SEQ_MISC_TIMING2_LP 0x2a78

#define MC_SEQ_WR_CTL_D0_LP 0x2a7c

#define MC_SEQ_WR_CTL_D1_LP 0x2a80

#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84

#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88

#define MC_PMG_CMD_MRS 0x2aac

#define MC_SEQ_RD_CTL_D0_LP 0x2b1c

#define MC_SEQ_RD_CTL_D1_LP 0x2b20

#define MC_PMG_CMD_MRS1 0x2b44

#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48

#define MC_SEQ_PMG_TIMING_LP 0x2b4c

#define MC_SEQ_WR_CTL_2 0x2b54

#define MC_SEQ_WR_CTL_2_LP 0x2b58

#define MC_PMG_CMD_MRS2 0x2b5c

#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60

#define MCLK_PWRMGT_CNTL 0x2ba0

# define DLL_SPEED(x) ((x) << 0)

# define DLL_SPEED_MASK (0x1f << 0)

# define DLL_READY (1 << 6)

# define MC_INT_CNTL (1 << 7)

# define MRDCK0_PDNB (1 << 8)

# define MRDCK1_PDNB (1 << 9)

# define MRDCK0_RESET (1 << 16)

# define MRDCK1_RESET (1 << 17)

# define DLL_READY_READ (1 << 24)

#define DLL_CNTL 0x2ba4

# define MRDCK0_BYPASS (1 << 24)

# define MRDCK1_BYPASS (1 << 25)

#define MPLL_FUNC_CNTL 0x2bb4

#define BWCTRL(x) ((x) << 20)

#define BWCTRL_MASK (0xff << 20)

#define MPLL_FUNC_CNTL_1 0x2bb8

#define VCO_MODE(x) ((x) << 0)

#define VCO_MODE_MASK (3 << 0)

#define CLKFRAC(x) ((x) << 4)

#define CLKFRAC_MASK (0xfff << 4)

#define CLKF(x) ((x) << 16)

#define CLKF_MASK (0xfff << 16)

#define MPLL_FUNC_CNTL_2 0x2bbc

#define MPLL_AD_FUNC_CNTL 0x2bc0

#define YCLK_POST_DIV(x) ((x) << 0)

#define YCLK_POST_DIV_MASK (7 << 0)

#define MPLL_DQ_FUNC_CNTL 0x2bc4

#define YCLK_SEL(x) ((x) << 4)

#define YCLK_SEL_MASK (1 << 4)

#define MPLL_SS1 0x2bcc

#define CLKV(x) ((x) << 0)

#define CLKV_MASK (0x3ffffff << 0)

#define MPLL_SS2 0x2bd0

#define CLKS(x) ((x) << 0)

#define CLKS_MASK (0xfff << 0)

#define HDP_HOST_PATH_CNTL 0x2C00

#define CLOCK_GATING_DIS (1 << 23)

#define HDP_NONSURFACE_BASE 0x2C04

#define HDP_NONSURFACE_INFO 0x2C08

#define HDP_NONSURFACE_SIZE 0x2C0C

#define HDP_ADDR_CONFIG 0x2F48

#define HDP_MISC_CNTL 0x2F4C

#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)

#define HDP_MEM_POWER_LS 0x2F50

#define HDP_LS_ENABLE (1 << 0)

#define ATC_MISC_CG 0x3350

#define GMCON_RENG_EXECUTE 0x3508

#define RENG_EXECUTE_ON_PWR_UP (1 << 0)

#define GMCON_MISC 0x350c

#define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)

#define STCTRL_STUTTER_EN (1 << 16)

#define GMCON_PGFSM_CONFIG 0x3538

#define GMCON_PGFSM_WRITE 0x353c

#define GMCON_PGFSM_READ 0x3540

#define GMCON_MISC3 0x3544

#define MC_SEQ_CNTL_3 0x3600

# define CAC_EN (1 << 31)

#define MC_SEQ_G5PDX_CTRL 0x3604

#define MC_SEQ_G5PDX_CTRL_LP 0x3608

#define MC_SEQ_G5PDX_CMD0 0x360c

#define MC_SEQ_G5PDX_CMD0_LP 0x3610

#define MC_SEQ_G5PDX_CMD1 0x3614

#define MC_SEQ_G5PDX_CMD1_LP 0x3618

#define MC_SEQ_PMG_DVS_CTL 0x3628

#define MC_SEQ_PMG_DVS_CTL_LP 0x362c

#define MC_SEQ_PMG_DVS_CMD 0x3630

#define MC_SEQ_PMG_DVS_CMD_LP 0x3634

#define MC_SEQ_DLL_STBY 0x3638

#define MC_SEQ_DLL_STBY_LP 0x363c

#define IH_RB_CNTL 0x3e00

# define IH_RB_ENABLE (1 << 0)

# define IH_RB_SIZE(x) ((x) << 1) /* log2 */

# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)

# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)

# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */

# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)

# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)

#define IH_RB_BASE 0x3e04

#define IH_RB_RPTR 0x3e08

#define IH_RB_WPTR 0x3e0c

# define RB_OVERFLOW (1 << 0)

# define WPTR_OFFSET_MASK 0x3fffc

#define IH_RB_WPTR_ADDR_HI 0x3e10

#define IH_RB_WPTR_ADDR_LO 0x3e14

#define IH_CNTL 0x3e18

# define ENABLE_INTR (1 << 0)

# define IH_MC_SWAP(x) ((x) << 1)

# define IH_MC_SWAP_NONE 0

# define IH_MC_SWAP_16BIT 1

# define IH_MC_SWAP_32BIT 2

# define IH_MC_SWAP_64BIT 3

# define RPTR_REARM (1 << 4)

# define MC_WRREQ_CREDIT(x) ((x) << 15)

# define MC_WR_CLEAN_CNT(x) ((x) << 20)

# define MC_VMID(x) ((x) << 25)

#define BIF_LNCNT_RESET 0x5220

# define RESET_LNCNT_EN (1 << 0)

#define CONFIG_MEMSIZE 0x5428

#define INTERRUPT_CNTL 0x5468

# define IH_DUMMY_RD_OVERRIDE (1 << 0)

# define IH_DUMMY_RD_EN (1 << 1)

# define IH_REQ_NONSNOOP_EN (1 << 3)

# define GEN_IH_INT_EN (1 << 8)

#define INTERRUPT_CNTL2 0x546c

#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480

#define BIF_FB_EN 0x5490

#define FB_READ_EN (1 << 0)

#define FB_WRITE_EN (1 << 1)

#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0

#define GPU_HDP_FLUSH_REQ 0x54DC

#define GPU_HDP_FLUSH_DONE 0x54E0

#define CP0 (1 << 0)

#define CP1 (1 << 1)

#define CP2 (1 << 2)

#define CP3 (1 << 3)

#define CP4 (1 << 4)

#define CP5 (1 << 5)

#define CP6 (1 << 6)

#define CP7 (1 << 7)

#define CP8 (1 << 8)

#define CP9 (1 << 9)

#define SDMA0 (1 << 10)

#define SDMA1 (1 << 11)

/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */

#define LB_MEMORY_CTRL 0x6b04

#define LB_MEMORY_SIZE(x) ((x) << 0)

#define LB_MEMORY_CONFIG(x) ((x) << 20)

#define DPG_WATERMARK_MASK_CONTROL 0x6cc8

# define LATENCY_WATERMARK_MASK(x) ((x) << 8)

#define DPG_PIPE_LATENCY_CONTROL 0x6ccc

# define LATENCY_LOW_WATERMARK(x) ((x) << 0)

# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)

/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */

#define LB_VLINE_STATUS 0x6b24

# define VLINE_OCCURRED (1 << 0)

# define VLINE_ACK (1 << 4)

# define VLINE_STAT (1 << 12)

# define VLINE_INTERRUPT (1 << 16)

# define VLINE_INTERRUPT_TYPE (1 << 17)

/* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */

#define LB_VBLANK_STATUS 0x6b2c

# define VBLANK_OCCURRED (1 << 0)

# define VBLANK_ACK (1 << 4)

# define VBLANK_STAT (1 << 12)

# define VBLANK_INTERRUPT (1 << 16)

# define VBLANK_INTERRUPT_TYPE (1 << 17)

/* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */

#define LB_INTERRUPT_MASK 0x6b20

# define VBLANK_INTERRUPT_MASK (1 << 0)

# define VLINE_INTERRUPT_MASK (1 << 4)

# define VLINE2_INTERRUPT_MASK (1 << 8)

#define DISP_INTERRUPT_STATUS 0x60f4

# define LB_D1_VLINE_INTERRUPT (1 << 2)

# define LB_D1_VBLANK_INTERRUPT (1 << 3)

# define DC_HPD1_INTERRUPT (1 << 17)

# define DC_HPD1_RX_INTERRUPT (1 << 18)

# define DACA_AUTODETECT_INTERRUPT (1 << 22)

# define DACB_AUTODETECT_INTERRUPT (1 << 23)

# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)

# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)

#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8

# define LB_D2_VLINE_INTERRUPT (1 << 2)

# define LB_D2_VBLANK_INTERRUPT (1 << 3)

# define DC_HPD2_INTERRUPT (1 << 17)

# define DC_HPD2_RX_INTERRUPT (1 << 18)

# define DISP_TIMER_INTERRUPT (1 << 24)

#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc

# define LB_D3_VLINE_INTERRUPT (1 << 2)

# define LB_D3_VBLANK_INTERRUPT (1 << 3)

# define DC_HPD3_INTERRUPT (1 << 17)

# define DC_HPD3_RX_INTERRUPT (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100

# define LB_D4_VLINE_INTERRUPT (1 << 2)

# define LB_D4_VBLANK_INTERRUPT (1 << 3)

# define DC_HPD4_INTERRUPT (1 << 17)

# define DC_HPD4_RX_INTERRUPT (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c

# define LB_D5_VLINE_INTERRUPT (1 << 2)

# define LB_D5_VBLANK_INTERRUPT (1 << 3)

# define DC_HPD5_INTERRUPT (1 << 17)

# define DC_HPD5_RX_INTERRUPT (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150

# define LB_D6_VLINE_INTERRUPT (1 << 2)

# define LB_D6_VBLANK_INTERRUPT (1 << 3)

# define DC_HPD6_INTERRUPT (1 << 17)

# define DC_HPD6_RX_INTERRUPT (1 << 18)

#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780

/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */

#define GRPH_INT_STATUS 0x6858

# define GRPH_PFLIP_INT_OCCURRED (1 << 0)

# define GRPH_PFLIP_INT_CLEAR (1 << 8)

/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */

#define GRPH_INT_CONTROL 0x685c

# define GRPH_PFLIP_INT_MASK (1 << 0)

# define GRPH_PFLIP_INT_TYPE (1 << 8)

#define DAC_AUTODETECT_INT_CONTROL 0x67c8

#define DC_HPD1_INT_STATUS 0x601c

#define DC_HPD2_INT_STATUS 0x6028

#define DC_HPD3_INT_STATUS 0x6034

#define DC_HPD4_INT_STATUS 0x6040

#define DC_HPD5_INT_STATUS 0x604c

#define DC_HPD6_INT_STATUS 0x6058

# define DC_HPDx_INT_STATUS (1 << 0)

# define DC_HPDx_SENSE (1 << 1)

# define DC_HPDx_SENSE_DELAYED (1 << 4)

# define DC_HPDx_RX_INT_STATUS (1 << 8)

#define DC_HPD1_INT_CONTROL 0x6020

#define DC_HPD2_INT_CONTROL 0x602c

#define DC_HPD3_INT_CONTROL 0x6038

#define DC_HPD4_INT_CONTROL 0x6044

#define DC_HPD5_INT_CONTROL 0x6050

#define DC_HPD6_INT_CONTROL 0x605c

# define DC_HPDx_INT_ACK (1 << 0)

# define DC_HPDx_INT_POLARITY (1 << 8)

# define DC_HPDx_INT_EN (1 << 16)

# define DC_HPDx_RX_INT_ACK (1 << 20)

# define DC_HPDx_RX_INT_EN (1 << 24)

#define DC_HPD1_CONTROL 0x6024

#define DC_HPD2_CONTROL 0x6030

#define DC_HPD3_CONTROL 0x603c

#define DC_HPD4_CONTROL 0x6048

#define DC_HPD5_CONTROL 0x6054

#define DC_HPD6_CONTROL 0x6060

# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)

# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)

# define DC_HPDx_EN (1 << 28)

#define DPG_PIPE_STUTTER_CONTROL 0x6cd4

# define STUTTER_ENABLE (1 << 0)

/* DCE8 FMT blocks */

#define FMT_DYNAMIC_EXP_CNTL 0x6fb4

# define FMT_DYNAMIC_EXP_EN (1 << 0)

# define FMT_DYNAMIC_EXP_MODE (1 << 4)

/* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */

#define FMT_CONTROL 0x6fb8

# define FMT_PIXEL_ENCODING (1 << 16)

/* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */

#define FMT_BIT_DEPTH_CONTROL 0x6fc8

# define FMT_TRUNCATE_EN (1 << 0)

# define FMT_TRUNCATE_MODE (1 << 1)

# define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

# define FMT_SPATIAL_DITHER_EN (1 << 8)

# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)

# define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

# define FMT_FRAME_RANDOM_ENABLE (1 << 13)

# define FMT_RGB_RANDOM_ENABLE (1 << 14)

# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)

# define FMT_TEMPORAL_DITHER_EN (1 << 16)

# define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */

# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)

# define FMT_TEMPORAL_LEVEL (1 << 24)

# define FMT_TEMPORAL_DITHER_RESET (1 << 25)

# define FMT_25FRC_SEL(x) ((x) << 26)

# define FMT_50FRC_SEL(x) ((x) << 28)

# define FMT_75FRC_SEL(x) ((x) << 30)

#define FMT_CLAMP_CONTROL 0x6fe4

# define FMT_CLAMP_DATA_EN (1 << 0)

# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)

# define FMT_CLAMP_6BPC 0

# define FMT_CLAMP_8BPC 1

# define FMT_CLAMP_10BPC 2

#define GRBM_CNTL 0x8000

#define GRBM_READ_TIMEOUT(x) ((x) << 0)

#define GRBM_STATUS2 0x8008

#define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F

#define ME0PIPE1_CF_RQ_PENDING (1 << 4)

#define ME0PIPE1_PF_RQ_PENDING (1 << 5)

#define ME1PIPE0_RQ_PENDING (1 << 6)

#define ME1PIPE1_RQ_PENDING (1 << 7)

#define ME1PIPE2_RQ_PENDING (1 << 8)

#define ME1PIPE3_RQ_PENDING (1 << 9)

#define ME2PIPE0_RQ_PENDING (1 << 10)

#define ME2PIPE1_RQ_PENDING (1 << 11)

#define ME2PIPE2_RQ_PENDING (1 << 12)

#define ME2PIPE3_RQ_PENDING (1 << 13)

#define RLC_RQ_PENDING (1 << 14)

#define RLC_BUSY (1 << 24)

#define TC_BUSY (1 << 25)

#define CPF_BUSY (1 << 28)

#define CPC_BUSY (1 << 29)

#define CPG_BUSY (1 << 30)

#define GRBM_STATUS 0x8010

#define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F

#define SRBM_RQ_PENDING (1 << 5)

#define ME0PIPE0_CF_RQ_PENDING (1 << 7)

#define ME0PIPE0_PF_RQ_PENDING (1 << 8)

#define GDS_DMA_RQ_PENDING (1 << 9)

#define DB_CLEAN (1 << 12)