Skip to content

Commit cd3a91a

Browse files
6by9pelwell
6by9
authored and
pelwell
committed
drm/vc4: Disable the 2pixel/clock odd timings workaround for interlaced
Whilst BCM2712 does fix using odd horizontal timings, it doesn't work with interlaced modes. Drop the workaround for interlaced modes and revert to the same behaviour as BCM2711. #6281 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
1 parent 21dc82f commit cd3a91a

File tree

4 files changed

+30
-4
lines changed

4 files changed

+30
-4
lines changed

‎drivers/gpu/drm/vc4/vc4_crtc.c

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -378,7 +378,9 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
378378
bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
379379
bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
380380
u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
381-
u8 ppc = pv_data->pixels_per_clock;
381+
u8 ppc = (mode->flags & DRM_MODE_FLAG_INTERLACE) ?
382+
pv_data->pixels_per_clock_int :
383+
pv_data->pixels_per_clock;
382384

383385
u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
384386
u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
@@ -443,7 +445,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
443445
*/
444446
CRTC_WRITE(PV_V_CONTROL,
445447
PV_VCONTROL_CONTINUOUS |
446-
(vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
448+
(vc4->gen >= VC4_GEN_6 && ppc == 1 ?
449+
PV_VCONTROL_ODD_TIMING : 0) |
447450
(is_dsi ? PV_VCONTROL_DSI : 0) |
448451
PV_VCONTROL_INTERLACE |
449452
(odd_field_first
@@ -455,7 +458,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
455458
} else {
456459
CRTC_WRITE(PV_V_CONTROL,
457460
PV_VCONTROL_CONTINUOUS |
458-
(vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
461+
(vc4->gen >= VC4_GEN_6 && ppc == 1 ?
462+
PV_VCONTROL_ODD_TIMING : 0) |
459463
(is_dsi ? PV_VCONTROL_DSI : 0));
460464
CRTC_WRITE(PV_VSYNCD_EVEN, 0);
461465
}
@@ -1223,6 +1227,7 @@ const struct vc4_pv_data bcm2835_pv0_data = {
12231227
},
12241228
.fifo_depth = 64,
12251229
.pixels_per_clock = 1,
1230+
.pixels_per_clock_int = 1,
12261231
.encoder_types = {
12271232
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
12281233
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
@@ -1238,6 +1243,7 @@ const struct vc4_pv_data bcm2835_pv1_data = {
12381243
},
12391244
.fifo_depth = 64,
12401245
.pixels_per_clock = 1,
1246+
.pixels_per_clock_int = 1,
12411247
.encoder_types = {
12421248
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
12431249
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
@@ -1253,6 +1259,7 @@ const struct vc4_pv_data bcm2835_pv2_data = {
12531259
},
12541260
.fifo_depth = 64,
12551261
.pixels_per_clock = 1,
1262+
.pixels_per_clock_int = 1,
12561263
.encoder_types = {
12571264
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
12581265
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
@@ -1268,6 +1275,7 @@ const struct vc4_pv_data bcm2711_pv0_data = {
12681275
},
12691276
.fifo_depth = 64,
12701277
.pixels_per_clock = 1,
1278+
.pixels_per_clock_int = 1,
12711279
.encoder_types = {
12721280
[0] = VC4_ENCODER_TYPE_DSI0,
12731281
[1] = VC4_ENCODER_TYPE_DPI,
@@ -1283,6 +1291,7 @@ const struct vc4_pv_data bcm2711_pv1_data = {
12831291
},
12841292
.fifo_depth = 64,
12851293
.pixels_per_clock = 1,
1294+
.pixels_per_clock_int = 1,
12861295
.encoder_types = {
12871296
[0] = VC4_ENCODER_TYPE_DSI1,
12881297
[1] = VC4_ENCODER_TYPE_SMI,
@@ -1298,6 +1307,7 @@ const struct vc4_pv_data bcm2711_pv2_data = {
12981307
},
12991308
.fifo_depth = 256,
13001309
.pixels_per_clock = 2,
1310+
.pixels_per_clock_int = 2,
13011311
.encoder_types = {
13021312
[0] = VC4_ENCODER_TYPE_HDMI0,
13031313
},
@@ -1312,6 +1322,7 @@ const struct vc4_pv_data bcm2711_pv3_data = {
13121322
},
13131323
.fifo_depth = 64,
13141324
.pixels_per_clock = 1,
1325+
.pixels_per_clock_int = 1,
13151326
.encoder_types = {
13161327
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
13171328
},
@@ -1326,6 +1337,7 @@ const struct vc4_pv_data bcm2711_pv4_data = {
13261337
},
13271338
.fifo_depth = 64,
13281339
.pixels_per_clock = 2,
1340+
.pixels_per_clock_int = 2,
13291341
.encoder_types = {
13301342
[0] = VC4_ENCODER_TYPE_HDMI1,
13311343
},
@@ -1339,6 +1351,7 @@ const struct vc4_pv_data bcm2712_pv0_data = {
13391351
},
13401352
.fifo_depth = 64,
13411353
.pixels_per_clock = 1,
1354+
.pixels_per_clock_int = 2,
13421355
.encoder_types = {
13431356
[0] = VC4_ENCODER_TYPE_HDMI0,
13441357
},
@@ -1352,6 +1365,7 @@ const struct vc4_pv_data bcm2712_pv1_data = {
13521365
},
13531366
.fifo_depth = 64,
13541367
.pixels_per_clock = 1,
1368+
.pixels_per_clock_int = 2,
13551369
.encoder_types = {
13561370
[0] = VC4_ENCODER_TYPE_HDMI1,
13571371
},

‎drivers/gpu/drm/vc4/vc4_drv.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -569,6 +569,8 @@ struct vc4_pv_data {
569569

570570
/* Number of pixels output per clock period */
571571
u8 pixels_per_clock;
572+
/* Number of pixels output per clock period when in an interlaced mode */
573+
u8 pixels_per_clock_int;
572574

573575
enum vc4_encoder_type encoder_types[4];
574576
};

‎drivers/gpu/drm/vc4/vc4_hdmi.c

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2274,7 +2274,9 @@ static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
22742274
unsigned long long tmds_bit_rate;
22752275
int ret;
22762276

2277-
if (vc4_hdmi->variant->unsupported_odd_h_timings) {
2277+
if (vc4_hdmi->variant->unsupported_odd_h_timings ||
2278+
(vc4_hdmi->variant->unsupported_int_odd_h_timings &&
2279+
(mode->flags & DRM_MODE_FLAG_INTERLACE))) {
22782280
if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
22792281
/* Only try to fixup DBLCLK modes to get 480i and 576i
22802282
* working.
@@ -3985,6 +3987,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
39853987
PHY_LANE_CK,
39863988
},
39873989
.unsupported_odd_h_timings = true,
3990+
.unsupported_int_odd_h_timings = true,
39883991
.external_irq_controller = true,
39893992

39903993
.init_resources = vc5_hdmi_init_resources,
@@ -4014,6 +4017,7 @@ static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
40144017
PHY_LANE_2,
40154018
},
40164019
.unsupported_odd_h_timings = true,
4020+
.unsupported_int_odd_h_timings = true,
40174021
.external_irq_controller = true,
40184022

40194023
.init_resources = vc5_hdmi_init_resources,
@@ -4043,6 +4047,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = {
40434047
PHY_LANE_CK,
40444048
},
40454049
.unsupported_odd_h_timings = false,
4050+
.unsupported_int_odd_h_timings = true,
40464051
.external_irq_controller = true,
40474052

40484053
.init_resources = vc5_hdmi_init_resources,
@@ -4070,6 +4075,7 @@ static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = {
40704075
PHY_LANE_CK,
40714076
},
40724077
.unsupported_odd_h_timings = false,
4078+
.unsupported_int_odd_h_timings = true,
40734079
.external_irq_controller = true,
40744080

40754081
.init_resources = vc5_hdmi_init_resources,

‎drivers/gpu/drm/vc4/vc4_hdmi.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,10 @@ struct vc4_hdmi_variant {
4949

5050
/* The BCM2711 cannot deal with odd horizontal pixel timings */
5151
bool unsupported_odd_h_timings;
52+
/* The BCM2712 can handle odd horizontal pixel timings, but not in
53+
* interlaced modes
54+
*/
55+
bool unsupported_int_odd_h_timings;
5256

5357
/*
5458
* The BCM2711 CEC/hotplug IRQ controller is shared between the

0 commit comments

Comments
 (0)