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Commit a95b44d

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author
Andrew Waterman
committed
Upgrade to latest SoftFloat
1 parent bea2835 commit a95b44d

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204 files changed

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-5178
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204 files changed

+9842
-5178
lines changed

‎riscv/decode.h

+4
Original file line numberDiff line numberDiff line change
@@ -200,6 +200,10 @@ class regfile_t
200200

201201
#define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */
202202

203+
/* Convenience wrappers to simplify softfloat code sequences */
204+
#define f32(x) ((float32_t){(uint32_t)x})
205+
#define f64(x) ((float64_t){(uint64_t)x})
206+
203207
#define validate_csr(which, write) ({ \
204208
if (!STATE.serialized) return PC_SERIALIZE; \
205209
STATE.serialized = false; \

‎riscv/insn_template.h

+1-2
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,6 @@
33
#include "mmu.h"
44
#include "mulhi.h"
55
#include "softfloat.h"
6+
#include "internals.h"
67
#include "tracer.h"
7-
#include "platform.h" // softfloat isNaNF32UI, etc.
8-
#include "internals.h" // ditto
98
#include <assert.h>

‎riscv/insns/fadd_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2));
4+
WRITE_FRD(f64_add(f64(FRS1), f64(FRS2)).v);
55
set_fp_exceptions;

‎riscv/insns/fadd_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2));
4+
WRITE_FRD(f32_add(f32(FRS1), f32(FRS2)).v);
55
set_fp_exceptions;

‎riscv/insns/fclass_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
11
require_extension('D');
22
require_fp;
3-
WRITE_RD(f64_classify(FRS1));
3+
WRITE_RD(f64_classify(f64(FRS1)));

‎riscv/insns/fclass_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
11
require_extension('F');
22
require_fp;
3-
WRITE_RD(f32_classify(FRS1));
3+
WRITE_RD(f32_classify(f32(FRS1)));

‎riscv/insns/fcvt_d_l.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,5 @@ require_extension('D');
22
require_rv64;
33
require_fp;
44
softfloat_roundingMode = RM;
5-
WRITE_FRD(i64_to_f64(RS1));
5+
WRITE_FRD(i64_to_f64(RS1).v);
66
set_fp_exceptions;

‎riscv/insns/fcvt_d_lu.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,5 @@ require_extension('D');
22
require_rv64;
33
require_fp;
44
softfloat_roundingMode = RM;
5-
WRITE_FRD(ui64_to_f64(RS1));
5+
WRITE_FRD(ui64_to_f64(RS1).v);
66
set_fp_exceptions;

‎riscv/insns/fcvt_d_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_to_f64(FRS1));
4+
WRITE_FRD(f32_to_f64(f32(FRS1)).v);
55
set_fp_exceptions;

‎riscv/insns/fcvt_d_w.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(i32_to_f64((int32_t)RS1));
4+
WRITE_FRD(i32_to_f64((int32_t)RS1).v);
55
set_fp_exceptions;

‎riscv/insns/fcvt_d_wu.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(ui32_to_f64((uint32_t)RS1));
4+
WRITE_FRD(ui32_to_f64((uint32_t)RS1).v);
55
set_fp_exceptions;

‎riscv/insns/fcvt_l_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,5 @@ require_extension('D');
22
require_rv64;
33
require_fp;
44
softfloat_roundingMode = RM;
5-
WRITE_RD(f64_to_i64(FRS1, RM, true));
5+
WRITE_RD(f64_to_i64(f64(FRS1), RM, true));
66
set_fp_exceptions;

‎riscv/insns/fcvt_l_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,5 @@ require_extension('F');
22
require_rv64;
33
require_fp;
44
softfloat_roundingMode = RM;
5-
WRITE_RD(f32_to_i64(FRS1, RM, true));
5+
WRITE_RD(f32_to_i64(f32(FRS1), RM, true));
66
set_fp_exceptions;

‎riscv/insns/fcvt_lu_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,5 @@ require_extension('D');
22
require_rv64;
33
require_fp;
44
softfloat_roundingMode = RM;
5-
WRITE_RD(f64_to_ui64(FRS1, RM, true));
5+
WRITE_RD(f64_to_ui64(f64(FRS1), RM, true));
66
set_fp_exceptions;

‎riscv/insns/fcvt_lu_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,5 @@ require_extension('F');
22
require_rv64;
33
require_fp;
44
softfloat_roundingMode = RM;
5-
WRITE_RD(f32_to_ui64(FRS1, RM, true));
5+
WRITE_RD(f32_to_ui64(f32(FRS1), RM, true));
66
set_fp_exceptions;

‎riscv/insns/fcvt_s_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_to_f32(FRS1));
4+
WRITE_FRD(f64_to_f32(f64(FRS1)).v);
55
set_fp_exceptions;

‎riscv/insns/fcvt_s_l.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,5 @@ require_extension('F');
22
require_rv64;
33
require_fp;
44
softfloat_roundingMode = RM;
5-
WRITE_FRD(i64_to_f32(RS1));
5+
WRITE_FRD(i64_to_f32(RS1).v);
66
set_fp_exceptions;

‎riscv/insns/fcvt_s_lu.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,5 @@ require_extension('F');
22
require_rv64;
33
require_fp;
44
softfloat_roundingMode = RM;
5-
WRITE_FRD(ui64_to_f32(RS1));
5+
WRITE_FRD(ui64_to_f32(RS1).v);
66
set_fp_exceptions;

‎riscv/insns/fcvt_s_w.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(i32_to_f32((int32_t)RS1));
4+
WRITE_FRD(i32_to_f32((int32_t)RS1).v);
55
set_fp_exceptions;

‎riscv/insns/fcvt_s_wu.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(ui32_to_f32((uint32_t)RS1));
4+
WRITE_FRD(ui32_to_f32((uint32_t)RS1).v);
55
set_fp_exceptions;

‎riscv/insns/fcvt_w_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_RD(sext32(f64_to_i32(FRS1, RM, true)));
4+
WRITE_RD(sext32(f64_to_i32(f64(FRS1), RM, true)));
55
set_fp_exceptions;

‎riscv/insns/fcvt_w_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_RD(sext32(f32_to_i32(FRS1, RM, true)));
4+
WRITE_RD(sext32(f32_to_i32(f32(FRS1), RM, true)));
55
set_fp_exceptions;

‎riscv/insns/fcvt_wu_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_RD(sext32(f64_to_ui32(FRS1, RM, true)));
4+
WRITE_RD(sext32(f64_to_ui32(f64(FRS1), RM, true)));
55
set_fp_exceptions;

‎riscv/insns/fcvt_wu_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_RD(sext32(f32_to_ui32(FRS1, RM, true)));
4+
WRITE_RD(sext32(f32_to_ui32(f32(FRS1), RM, true)));
55
set_fp_exceptions;

‎riscv/insns/fdiv_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_div(FRS1, FRS2));
4+
WRITE_FRD(f64_div(f64(FRS1), f64(FRS2)).v);
55
set_fp_exceptions;

‎riscv/insns/fdiv_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_div(FRS1, FRS2));
4+
WRITE_FRD(f32_div(f32(FRS1), f32(FRS2)).v);
55
set_fp_exceptions;

‎riscv/insns/feq_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
require_extension('D');
22
require_fp;
3-
WRITE_RD(f64_eq(FRS1, FRS2));
3+
WRITE_RD(f64_eq(f64(FRS1), f64(FRS2)));
44
set_fp_exceptions;

‎riscv/insns/feq_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
require_extension('F');
22
require_fp;
3-
WRITE_RD(f32_eq(FRS1, FRS2));
3+
WRITE_RD(f32_eq(f32(FRS1), f32(FRS2)));
44
set_fp_exceptions;

‎riscv/insns/fle_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
require_extension('D');
22
require_fp;
3-
WRITE_RD(f64_le(FRS1, FRS2));
3+
WRITE_RD(f64_le(f64(FRS1), f64(FRS2)));
44
set_fp_exceptions;

‎riscv/insns/fle_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
require_extension('F');
22
require_fp;
3-
WRITE_RD(f32_le(FRS1, FRS2));
3+
WRITE_RD(f32_le(f32(FRS1), f32(FRS2)));
44
set_fp_exceptions;

‎riscv/insns/flt_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
require_extension('D');
22
require_fp;
3-
WRITE_RD(f64_lt(FRS1, FRS2));
3+
WRITE_RD(f64_lt(f64(FRS1), f64(FRS2)));
44
set_fp_exceptions;

‎riscv/insns/flt_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
require_extension('F');
22
require_fp;
3-
WRITE_RD(f32_lt(FRS1, FRS2));
3+
WRITE_RD(f32_lt(f32(FRS1), f32(FRS2)));
44
set_fp_exceptions;

‎riscv/insns/fmadd_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3));
4+
WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3)).v);
55
set_fp_exceptions;

‎riscv/insns/fmadd_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3));
4+
WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3)).v);
55
set_fp_exceptions;

‎riscv/insns/fmax_d.h

+1-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
require_extension('D');
22
require_fp;
3-
WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
4-
? FRS1 : FRS2);
3+
WRITE_FRD(isNaNF64UI(FRS2) || f64_le_quiet(f64(FRS2), f64(FRS1)) ? FRS1 : FRS2);
54
set_fp_exceptions;

‎riscv/insns/fmax_s.h

+1-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
require_extension('F');
22
require_fp;
3-
WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(FRS2,FRS1) /* && FRS1 not NaN */
4-
? FRS1 : FRS2);
3+
WRITE_FRD(isNaNF32UI(FRS2) || f32_le_quiet(f32(FRS2), f32(FRS1)) ? FRS1 : FRS2);
54
set_fp_exceptions;

‎riscv/insns/fmin_d.h

+1-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
require_extension('D');
22
require_fp;
3-
WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
4-
? FRS1 : FRS2);
3+
WRITE_FRD(isNaNF64UI(FRS2) || f64_lt_quiet(f64(FRS1), f64(FRS2)) ? FRS1 : FRS2);
54
set_fp_exceptions;

‎riscv/insns/fmin_s.h

+1-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
require_extension('F');
22
require_fp;
3-
WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
4-
? FRS1 : FRS2);
3+
WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(f32(FRS1), f32(FRS2)) ? FRS1 : FRS2);
54
set_fp_exceptions;

‎riscv/insns/fmsub_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
4+
WRITE_FRD(f64_mulAdd(f64(FRS1), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)).v);
55
set_fp_exceptions;

‎riscv/insns/fmsub_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
4+
WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v);
55
set_fp_exceptions;

‎riscv/insns/fmul_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN));
4+
WRITE_FRD(f64_mul(f64(FRS1), f64(FRS2)).v);
55
set_fp_exceptions;

‎riscv/insns/fmul_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN));
4+
WRITE_FRD(f32_mul(f32(FRS1), f32(FRS2)).v);
55
set_fp_exceptions;

‎riscv/insns/fnmadd_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
4+
WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3 ^ (uint64_t)INT64_MIN)).v);
55
set_fp_exceptions;

‎riscv/insns/fnmadd_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
4+
WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v);
55
set_fp_exceptions;

‎riscv/insns/fnmsub_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3));
4+
WRITE_FRD(f64_mulAdd(f64(FRS1 ^ (uint64_t)INT64_MIN), f64(FRS2), f64(FRS3)).v);
55
set_fp_exceptions;

‎riscv/insns/fnmsub_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3));
4+
WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3)).v);
55
set_fp_exceptions;

‎riscv/insns/fsqrt_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_sqrt(FRS1));
4+
WRITE_FRD(f64_sqrt(f64(FRS1)).v);
55
set_fp_exceptions;

‎riscv/insns/fsqrt_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_sqrt(FRS1));
4+
WRITE_FRD(f32_sqrt(f32(FRS1)).v);
55
set_fp_exceptions;

‎riscv/insns/fsub_d.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('D');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN));
4+
WRITE_FRD(f64_sub(f64(FRS1), f64(FRS2)).v);
55
set_fp_exceptions;

‎riscv/insns/fsub_s.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
require_extension('F');
22
require_fp;
33
softfloat_roundingMode = RM;
4-
WRITE_FRD(f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN));
4+
WRITE_FRD(f32_sub(f32(FRS1), f32(FRS2)).v);
55
set_fp_exceptions;

‎softfloat/8086/OLD-specialize.c

-40
This file was deleted.

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