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@xver

xver

Ottawa, Ontario, Canada

We are delighted to introduce our major open source project, "TCP/IP Shunt" This is a communication library for SystemVerilog and SystemC simulators. The "TCP/IP Shunt" has gained significant interest from the DV community since its introduction at the SNUG Boston conference in 2018. Please see the following link for more details about this project https://github.com/xver/Shunt .
We have received numerous requests for new features and extensions beyond its initial product scope. To continue to keep "TCP/IP Shunt" as an open tool and address all extension requests, we are seeking funding to support the project's growth and development.
We are committed to providing our sponsors with access to the latest updates, documentation, and technical support, ensuring that our sponsors can fully utilize "TCP/IP Shunt" to its fullest potential.
We look forward to working with you to advance the project and push the boundaries of SystemVerilog and SystemC simulations.

Featured work

  1. xver/Shunt

    SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

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