Merge #566

bors[bot] · lulf · web-flow · commit 0996ce10045d · 2021-07-08T20:49:40.000Z
566: Fix bit offset for RMVF in STM32l0x2 and STM32l0x3 r=richardeoin a=lulf

According to the reference manuals for STM32L0x{2, 3}, the RCC_CSR
register RMVF has the offset 23 and not 24. Offset 24 is occupied by a
Firewall reset which is also added in this change

Page 219 in the STM32L0x2 release manual can be used to verify.

Co-authored-by: Ulf Lilleengen &lt;ulf.lilleengen@gmail.com&gt;
diff --git a/devices/stm32l0x2.yaml b/devices/stm32l0x2.yaml
@@ -73,6 +73,14 @@ RCC:
     _modify:
       LPWRSTF:
         name: LPWRRSTF
+      RMVF:
+        bitOffset: 23
+    _add:
+      FWRSTF:
+        description: Firewall reset flag
+        bitOffset: 24
+        bitWidth: 1
+
   APB2RSTR:
     _modify:
       TM12RST:
diff --git a/devices/stm32l0x3.yaml b/devices/stm32l0x3.yaml
@@ -84,6 +84,13 @@ RCC:
     _modify:
       LPWRSTF:
         name: LPWRRSTF
+      RMVF:
+        bitOffset: 23
+    _add:
+      FWRSTF:
+        description: Firewall reset flag
+        bitOffset: 24
+        bitWidth: 1
   APB2RSTR:
     _modify:
       TM12RST:
