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Merge #606
606: [stm32f7] Fix all timers registers r=adamgreig a=maximeborges This pull request fix all the registers for every timers on every F7xx chips, based on the reference manual for those (`RM0431`, `RM0385` and`RM0410`). I'd like to get suggestions for better names for the new common patches that I created, they don't seem to fit with the others but I'm not sure what would be the best way to name them. Co-authored-by: Maxime <contact@maximeborg.es> Co-authored-by: Maxime BORGES <contact@maximeborg.es>
2 parents 20b0f7e + 545e6ff commit 1aa623b

15 files changed

+296
-60
lines changed

‎devices/common_patches/f730_f7x2_f7x3_tim.yaml

Lines changed: 31 additions & 0 deletions
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@@ -0,0 +1,31 @@
1+
TIM1:
2+
CCMR3_Output:
3+
_modify:
4+
OC5M3:
5+
name: OC5M_3
6+
OC6M3:
7+
name: OC6M_3
8+
9+
TIM1[0134]:
10+
CNT:
11+
_add:
12+
UIFCPY:
13+
description: >
14+
UIF copy
15+
This bit is a read-only copy of the UIF bit of the TIMx_ISR register.
16+
If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0
17+
bitOffset: 31
18+
bitWidth: 1
19+
access: read-only
20+
21+
TIM[18]:
22+
SR:
23+
_add:
24+
CC5IF:
25+
description: Compare 5 interrupt flag
26+
bitOffset: 16
27+
bitWidth: 1
28+
CC6IF:
29+
description: Compare 6 interrupt flag
30+
bitOffset: 17
31+
bitWidth: 1

‎devices/common_patches/f745_f750_f765_f7x6_f7x7_f7x9_tim.yaml

Lines changed: 33 additions & 0 deletions
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@@ -0,0 +1,33 @@
1+
TIM5:
2+
OR:
3+
_modify:
4+
TI4_RMP:
5+
bitOffset: 6
6+
7+
TIM10:
8+
CR1:
9+
_add:
10+
OPM:
11+
description: One-pulse mode
12+
bitOffset: 3
13+
bitWidth: 1
14+
access: read-write
15+
16+
TIM[16]:
17+
CNT:
18+
_add:
19+
UIFCPY:
20+
description: >
21+
UIF copy
22+
This bit is a read-only copy of the UIF bit of the TIMx_ISR register.
23+
If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0
24+
bitOffset: 31
25+
bitWidth: 1
26+
access: read-only
27+
TIM[18]:
28+
CCER:
29+
_add:
30+
CC4NP:
31+
description: Capture/Compare 4 complementary output polarity
32+
bitOffset: 15
33+
bitWidth: 1

‎devices/common_patches/f745_f750_f765_f7x6_f7x9_tim.yaml

Lines changed: 26 additions & 0 deletions
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@@ -0,0 +1,26 @@
1+
TIM[18]:
2+
BDTR:
3+
_add:
4+
BKF:
5+
description: Break filter
6+
bitOffset: 16
7+
bitWidth: 4
8+
BK2F:
9+
description: Break 2 filter
10+
bitOffset: 20
11+
bitWidth: 4
12+
BK2E:
13+
description: Break 2 enable
14+
bitOffset: 24
15+
bitWidth: 1
16+
BK2P:
17+
description: Break 2 polarity
18+
bitOffset: 25
19+
bitWidth: 1
20+
21+
TIM2:
22+
OR:
23+
_modify:
24+
ITR1_RMP:
25+
bitOffset: 10
26+
bitWidth: 2

‎devices/common_patches/f765_f7x6_f7x9_tim.yaml

Lines changed: 40 additions & 0 deletions
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@@ -0,0 +1,40 @@
1+
TIM[18]:
2+
_add:
3+
AF1:
4+
description: alternate function option register 1
5+
addressOffset: "0x60"
6+
size: 0x20
7+
resetValue: 0x00000001
8+
access: read-write
9+
fields:
10+
BKINE:
11+
description: BRK BKIN input enable
12+
bitOffset: 0
13+
bitWidth: 1
14+
BKDFBKE:
15+
description: BRK DFSDM_BREAK[0] enable
16+
bitOffset: 8
17+
bitWidth: 1
18+
BKINP:
19+
description: BRK BKIN input polarity
20+
bitOffset: 9
21+
bitWidth: 1
22+
AF2:
23+
description: alternate function option register 2
24+
addressOffset: "0x64"
25+
size: 0x20
26+
resetValue: 0x00000001
27+
access: read-write
28+
fields:
29+
BK2INE:
30+
description: BRK2 BKIN input enable
31+
bitOffset: 0
32+
bitWidth: 1
33+
BK2DFBKE:
34+
description: BRK2 DFSDM_BREAK[0] enable
35+
bitOffset: 8
36+
bitWidth: 1
37+
BK2INP:
38+
description: BRK2 BKIN input polarity
39+
bitOffset: 9
40+
bitWidth: 1

‎devices/common_patches/f7_tim.yaml

Lines changed: 58 additions & 0 deletions
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@@ -0,0 +1,58 @@
1+
TIM*:
2+
CR1:
3+
_delete:
4+
- UIFREMAP
5+
_add:
6+
UIFREMAP:
7+
description: UIF status bit remapping
8+
bitOffset: 11
9+
bitWidth: 1
10+
11+
TIM[18]:
12+
_modify:
13+
CRR6:
14+
name: CCR6
15+
16+
TIM1[0134]:
17+
_delete:
18+
- SMCR
19+
20+
21+
TIM[2-579],TIM1[02]:
22+
CNT:
23+
_add:
24+
UIFCPY:
25+
description: >
26+
UIF copy
27+
This bit is a read-only copy of the UIF bit of the TIMx_ISR register.
28+
If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0
29+
bitOffset: 31
30+
bitWidth: 1
31+
access: read-only
32+
33+
TIM3:
34+
CNT:
35+
_delete:
36+
- CNT_H
37+
ARR:
38+
_delete:
39+
- ARR_H
40+
CCR%s:
41+
_delete:
42+
- CCR1_H
43+
44+
TIM9:
45+
SMCR:
46+
_add:
47+
SMS_3:
48+
description: Slave mode selection - bit 3
49+
bitOffset: 16
50+
bitWidth: 1
51+
52+
TIM[1-58]:
53+
DMAR:
54+
_modify:
55+
# Self-inconsistency between the register map and the
56+
# specific register field documentation in RMs
57+
DMAB:
58+
bitWidth: 32

‎devices/common_patches/tim/v2/f7.yaml

Lines changed: 66 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,10 @@ TIM2:
2222
_delete:
2323
- TI4_RMP
2424
- ETR1_RMP
25+
_modify:
26+
ITR1_RMP:
27+
bitOffset: 10
28+
bitWidth: 2
2529

2630
TIM5:
2731
OR:
@@ -30,44 +34,14 @@ TIM5:
3034
- ITR1_RMP
3135

3236
TIM1:
33-
CCMR1_Output:
34-
_add:
35-
OC1M_3:
36-
description: "Output Compare 1 mode, bit 3"
37-
bitOffset: 16
38-
bitWidth: 1
39-
OC2M_3:
40-
description: "Output Compare 2 mode, bit 3"
41-
bitOffset: 24
42-
bitWidth: 1
43-
CCMR2_Output:
44-
_add:
45-
OC3M_3:
46-
description: "Output Compare 3 mode, bit 3"
47-
bitOffset: 16
48-
bitWidth: 1
49-
OC4M_3:
50-
description: "Output Compare 4 mode, bit 3"
51-
bitOffset: 24
52-
bitWidth: 1
5337
CCMR3_Output:
5438
_modify:
5539
OC5M3:
5640
name: OC5M_3
5741
OC6M3:
5842
name: OC6M_3
5943

60-
TIM[235]:
61-
CCMR1_Output:
62-
_add:
63-
OC1M_3:
64-
description: "Output Compare 1 mode, bit 3"
65-
bitOffset: 16
66-
bitWidth: 1
67-
OC2M_3:
68-
description: "Output Compare 2 mode, bit 3"
69-
bitOffset: 24
70-
bitWidth: 1
44+
TIM[1235]:
7145
CCMR2_Output:
7246
_add:
7347
OC3M_3:
@@ -79,16 +53,72 @@ TIM[235]:
7953
bitOffset: 24
8054
bitWidth: 1
8155

82-
TIM9:
56+
TIM[12359]:
8357
CCMR1_Output:
8458
_add:
85-
OC1M_3:
86-
description: "Output Compare 1 mode, bit 3"
87-
bitOffset: 16
88-
bitWidth: 1
8959
OC2M_3:
9060
description: "Output Compare 2 mode, bit 3"
9161
bitOffset: 24
9262
bitWidth: 1
9363

64+
TIM[12359],TIM10:
65+
CCMR1_Output:
66+
_add:
67+
OC1M_3:
68+
description: "Output Compare 1 mode, bit 3"
69+
bitOffset: 16
70+
bitWidth: 1
9471

72+
TIM[18]:
73+
CR2:
74+
_add:
75+
OIS5:
76+
description: Output Idle state 5 (OC5 output)
77+
bitOffset: 16
78+
bitWidth: 1
79+
OIS6:
80+
description: Output Idle state 6 (OC6 output)
81+
bitOffset: 18
82+
bitWidth: 1
83+
MMS2:
84+
description: Master mode selection 2
85+
bitOffset: 20
86+
bitWidth: 4
87+
SR:
88+
_add:
89+
B2IF:
90+
description: Break 2 interrupt flag
91+
bitOffset: 8
92+
bitWidth: 1
93+
CC5IF:
94+
description: Compare 5 interrupt flag
95+
bitOffset: 16
96+
bitWidth: 1
97+
CC6IF:
98+
description: Compare 6 interrupt flag
99+
bitOffset: 17
100+
bitWidth: 1
101+
EGR:
102+
_add:
103+
B2G:
104+
description: Break 2 generation
105+
bitOffset: 8
106+
bitWidth: 1
107+
CCER:
108+
_add:
109+
CC5E:
110+
description: Capture/Compare 5 output enable
111+
bitOffset: 16
112+
bitWidth: 1
113+
CC5P:
114+
description: Capture/Compare 5 output polarity
115+
bitOffset: 17
116+
bitWidth: 1
117+
CC6E:
118+
description: Capture/Compare 6 output enable
119+
bitOffset: 20
120+
bitWidth: 1
121+
CC6P:
122+
description: Capture/Compare 6 output polarity
123+
bitOffset: 21
124+
bitWidth: 1

‎devices/stm32f730.yaml

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -12,14 +12,6 @@ _modify:
1212
C_ADC:
1313
name: ADC_Common
1414

15-
TIM1:
16-
CCMR3_Output:
17-
_modify:
18-
OC5M3:
19-
name: OC5M_3
20-
OC6M3:
21-
name: OC6M_3
22-
2315
_include:
2416
- common_patches/f7x23_pllsai.yaml
2517
- common_patches/dma_fcr_wo.yaml
@@ -63,6 +55,8 @@ _include:
6355
- common_patches/tim/tim2345_mixed_l.yaml
6456
- ../peripherals/tim/tim_advanced.yaml
6557
- common_patches/tim/tim_ccr.yaml
58+
- common_patches/f7_tim.yaml
59+
- common_patches/f730_f7x2_f7x3_tim.yaml
6660
- ../peripherals/tim/v2/ccm.yaml
6761
- ../peripherals/iwdg/iwdg_with_WINR.yaml
6862
- ../peripherals/exti/exti.yaml

‎devices/stm32f745.yaml

Lines changed: 3 additions & 0 deletions
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@@ -155,7 +155,10 @@ _include:
155155
- common_patches/tim/tim2345_mixed_l.yaml
156156
- ../peripherals/tim/tim_advanced.yaml
157157
- common_patches/tim/tim_ccr.yaml
158+
- common_patches/f7_tim.yaml
158159
- common_patches/tim/v2/f7.yaml
160+
- common_patches/f745_f750_f765_f7x6_f7x7_f7x9_tim.yaml
161+
- common_patches/f745_f750_f765_f7x6_f7x9_tim.yaml
159162
- ../peripherals/tim/v2/ccm.yaml
160163
- ../peripherals/iwdg/iwdg_with_WINR.yaml
161164
- ../peripherals/exti/exti.yaml

‎devices/stm32f750.yaml

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@@ -81,7 +81,10 @@ _include:
8181
- ../peripherals/tim/tim2345_mixed.yaml
8282
- ../peripherals/tim/tim_advanced.yaml
8383
- common_patches/tim/tim_ccr.yaml
84+
- common_patches/f7_tim.yaml
8485
- common_patches/tim/v2/f7.yaml
86+
- common_patches/f745_f750_f765_f7x6_f7x7_f7x9_tim.yaml
87+
- common_patches/f745_f750_f765_f7x6_f7x9_tim.yaml
8588
- ../peripherals/tim/v2/ccm.yaml
8689
- ../peripherals/iwdg/iwdg_with_WINR.yaml
8790
- ../peripherals/exti/exti.yaml

‎devices/stm32f765.yaml

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -169,7 +169,11 @@ _include:
169169
- common_patches/tim/common.yaml
170170
- ../peripherals/tim/tim_advanced.yaml
171171
- common_patches/tim/tim_ccr.yaml
172+
- common_patches/f7_tim.yaml
172173
- common_patches/tim/v2/f7.yaml
174+
- common_patches/f745_f750_f765_f7x6_f7x7_f7x9_tim.yaml
175+
- common_patches/f745_f750_f765_f7x6_f7x9_tim.yaml
176+
- common_patches/f765_f7x6_f7x9_tim.yaml
173177
- ../peripherals/tim/v2/ccm.yaml
174178
- ../peripherals/iwdg/iwdg_with_WINR.yaml
175179
- ../peripherals/exti/exti.yaml

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