fix f7 OR register

burrbull · burrbull · commit 30d83ca078b8 · 2021-08-16T14:04:01.000+03:00
diff --git a/devices/common_patches/tim/v2/f7.yaml b/devices/common_patches/tim/v2/f7.yaml
@@ -1,6 +1,34 @@
 _derive:
   TIM4: TIM3
 
+TIM3:
+  _delete:
+    - OR1
+    - OR2
+
+_copy:
+  TIM5:
+    from: TIM2
+
+TIM[25]:
+  _modify:
+    OR1:
+      name: OR
+  _delete:
+    - OR2
+
+TIM2:
+  OR:
+    _delete:
+      - TI4_RMP
+      - ETR1_RMP
+
+TIM5:
+  OR:
+    _delete:
+      - ETR1_RMP
+      - ITR1_RMP
+
 TIM1:
   CCMR1_Output:
     _add:
@@ -29,7 +57,7 @@ TIM1:
       OC6M3:
         name: OC6M_3
 
-TIM[23]:
+TIM[235]:
   CCMR1_Output:
     _add:
       OC1M_3:
@@ -62,3 +90,5 @@ TIM9:
         description: "Output Compare 2 mode, bit 3"
         bitOffset: 24
         bitWidth: 1
+
+
