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Broke out the include from g4_rcc.yaml to the individual files, and added CCIFR/2 enums
1 parent ab5647e commit 331ef9c

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10 files changed

+80
-29
lines changed

10 files changed

+80
-29
lines changed

‎devices/common_patches/g4_rcc.yaml

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
11
# Edits required to match RM0440.
22

3-
_include:
4-
- ../../peripherals/rcc/rcc_g4.yaml
5-
63
RCC:
74
_modify:
85
PLLSYSCFGR:
@@ -18,7 +15,7 @@ RCC:
1815
name: PLLON
1916
HSECSSON:
2017
name: CSSON
21-
18+
2219
PLLCFGR:
2320
_modify:
2421
PLLSYSPDIV:
@@ -228,6 +225,7 @@ RCC:
228225
name: IWDGRSTF
229226
PADRSTF:
230227
name: PINRSTF
228+
231229
CRRCR:
232230
_modify:
233231
RC48ON:
@@ -248,4 +246,4 @@ RCC:
248246
"A?B?ENR,A?BENR,A?B?ENR?":
249247
"*EN":
250248
Disabled: [0, "The selected clock is disabled"]
251-
Enabled: [1, "The selected clock is enabled"]
249+
Enabled: [1, "The selected clock is enabled"]

‎devices/stm32g431.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,3 +19,4 @@ _include:
1919
- ../peripherals/i2c/i2c_v2.yaml
2020
- ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
2121
- ./common_patches/g4_usb.yaml
22+
- ../peripherals/rcc/rcc_g4.yaml

‎devices/stm32g441.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,3 +19,4 @@ _include:
1919
- ../peripherals/i2c/i2c_v2.yaml
2020
- ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
2121
- ./common_patches/g4_usb.yaml
22+
- ../peripherals/rcc/rcc_g4.yaml

‎devices/stm32g471.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,3 +19,4 @@ _include:
1919
- ../peripherals/i2c/i2c_v2.yaml
2020
- ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
2121
- ./common_patches/g4_usb.yaml
22+
- ../peripherals/rcc/rcc_g4.yaml

‎devices/stm32g473.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,3 +21,4 @@ _include:
2121
- ../peripherals/i2c/i2c_v2.yaml
2222
- ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
2323
- ./common_patches/g4_usb.yaml
24+
- ../peripherals/rcc/rcc_g4.yaml

‎devices/stm32g474.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,3 +21,4 @@ _include:
2121
- ../peripherals/i2c/i2c_v2.yaml
2222
- ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
2323
- ./common_patches/g4_usb.yaml
24+
- ../peripherals/rcc/rcc_g4.yaml

‎devices/stm32g483.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,3 +22,4 @@ _include:
2222
- ../peripherals/i2c/i2c_v2.yaml
2323
- ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
2424
- ./common_patches/g4_usb.yaml
25+
- ../peripherals/rcc/rcc_g4.yaml

‎devices/stm32g484.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,3 +21,4 @@ _include:
2121
- ../peripherals/i2c/i2c_v2.yaml
2222
- ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
2323
- ./common_patches/g4_usb.yaml
24+
- ../peripherals/rcc/rcc_g4.yaml

‎devices/stm32g491.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,3 +30,4 @@ _include:
3030
- ../peripherals/i2c/i2c_v2.yaml
3131
- ./common_patches/rename_USB_FS_peripheral_to_USB.yaml
3232
- ./common_patches/g4_usb.yaml
33+
- ../peripherals/rcc/rcc_g4.yaml

‎peripherals/rcc/rcc_g4.yaml

Lines changed: 69 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ RCC:
1313
HSION,HSEON,PLLON,PLLI2SON,PLLSAION:
1414
"Off": [0, "Clock Off"]
1515
"On": [1, "Clock On"]
16-
16+
1717
CFGR:
1818
MCOPRE:
1919
Div1: [0, "MCO divided by 1"]
@@ -226,7 +226,7 @@ RCC:
226226
Div125: [125, "pll_n_ck = vco_ck / 125"]
227227
Div126: [126, "pll_n_ck = vco_ck / 126"]
228228
Div127: [127, "pll_n_ck = vco_ck / 127"]
229-
PLLM:
229+
PLLM:
230230
Div1: [0, "pll_p_ck = vco_ck / 1"]
231231
Div2: [1, "pll_p_ck = vco_ck / 2"]
232232
Div3: [2, "pll_p_ck = vco_ck / 3"]
@@ -247,10 +247,10 @@ RCC:
247247
None: [0, "No clock sent to PLL"]
248248
HSI16: [2, "No clock sent to PLL"]
249249
HSE: [3, "No clock sent to PLL"]
250-
250+
251251
BDCR:
252252
LSCOSEL:
253-
LSI: [0, LSI clock selected"]
253+
LSI: [0, "LSI clock selected"]
254254
LSE: [1, "LSE clock selected"]
255255
LSCOEN:
256256
Disabled: [0, "LSCO disabled"]
@@ -297,11 +297,6 @@ RCC:
297297
"On": [1, "LSE oscillator On"]
298298

299299
CSR:
300-
_modify:
301-
WDGRSTF:
302-
name: IWDGRSTF
303-
PADRSTF:
304-
name: PINRSTF
305300
"*RSTF":
306301
_read:
307302
NoReset: [0, "No reset has occured"]
@@ -317,18 +312,68 @@ RCC:
317312
"Off": [0, "LSI oscillator Off"]
318313
"On": [1, "LSI oscillator On"]
319314

320-
# CSR:
321-
# "*RSTF":
322-
# _read:
323-
# NoReset: [0, "No reset has occured"]
324-
# Reset: [1, "A reset has occured"]
325-
# RMVF:
326-
# _write:
327-
# Clear: [1, "Clears the reset flag"]
328-
# LSIRDY:
329-
# _read:
330-
# NotReady: [0, "LSI oscillator not ready"]
331-
# Ready: [1, "LSI oscillator ready"]
332-
# LSION:
333-
# "Off": [0, "LSI oscillator Off"]
334-
# "On": [1, "LSI oscillator On"]
315+
<<<<<<< HEAD
316+
=======
317+
CSR:
318+
"*RSTF":
319+
_read:
320+
NoReset: [0, "No reset has occured"]
321+
Reset: [1, "A reset has occured"]
322+
RMVF:
323+
_write:
324+
Clear: [1, "Clears the reset flag"]
325+
LSIRDY:
326+
_read:
327+
NotReady: [0, "LSI oscillator not ready"]
328+
Ready: [1, "LSI oscillator ready"]
329+
LSION:
330+
"Off": [0, "LSI oscillator Off"]
331+
"On": [1, "LSI oscillator On"]
332+
333+
>>>>>>> df175cc... Broke out the include from g4_rcc.yaml to the individual files, and added CCIFR/2 enums
334+
CCIPR:
335+
"ADC*SEL":
336+
None: [0, "No clock selected for ADC"]
337+
PLLP: [1, "PLL 'P' clock selected for ADC"]
338+
System: [2, "System clock selected for ADC"]
339+
CLK48SEL:
340+
HSI48: [0, "HSI48 clock selected as 48MHz clock"]
341+
PLLQ: [2, "PLL 'Q' (PLL48M1CLK) clock selected as 48MHz clock"]
342+
FDCANSEL:
343+
HSE: [0, "HSE clock selected as FDCAN clock"]
344+
PLLQ: [1, "PLL 'Q' clock selected as FDCAN clock"]
345+
PCLK: [2, "PCLK clock selected as FDCAN clock"]
346+
I2S23SEL:
347+
System: [0, "System clock selected as I2S23 clock"]
348+
PLLQ: [1, "PLL 'Q' clock selected as I2S23 clock"]
349+
I2S_CKIN: [2, "Clock provided on I2S_CKIN pin is selected as I2S23 clock"]
350+
HSI16: [3, "HSI16 clock selected as I2S23 clock"]
351+
SAI1SEL:
352+
System: [0, "System clock selected as SAI clock"]
353+
PLLQ: [1, "PLL 'Q' clock selected as SAI clock"]
354+
I2S_CKIN: [2, "Clock provided on I2S_CKIN pin is selected as SAI clock"]
355+
HSI16: [3, "HSI16 clock selected as SAI clock"]
356+
LPTIM1SEL:
357+
PCLK: [0, "PCLK clock selected as LPTIM1 clock"]
358+
LSI: [1, "LSI clock selected as LPTIM1 clock"]
359+
HSI16: [2, "HSI16 clock selected as LPTIM1 clock"]
360+
LSE: [3, "LSE clock selected as LPTIM1 clock"]
361+
"I2C*SEL":
362+
PCLK: [0, "PCLK clock selected as I2C clock"]
363+
System: [1, "System clock (SYSCLK) selected as I2C clock"]
364+
HSI16: [2, "HSI16 clock selected as I2C clock"]
365+
"*UART*SEL":
366+
PCLK: [0, "PCLK clock selected as UART clock"]
367+
System: [1, "System clock (SYSCLK) selected as UART clock"]
368+
HSI16: [2, "HSI16 clock selected as UART clock"]
369+
LSE: [3, "LSE clock selected as UART clock"]
370+
371+
CCIPR2:
372+
QSPISEL:
373+
System: [0, "System clock selected as QUADSPI kernel clock"]
374+
HSI16: [1, "HSI16 clock selected as QUADSPI kernel clock"]
375+
PLLQ: [2, "PLL 'Q' clock selected as QUADSPI kernel clock"]
376+
I2C4SEL:
377+
PCLK: [0, "PCLK clock selected as I2C clock"]
378+
System: [1, "System clock (SYSCLK) selected as I2C clock"]
379+
HSI16: [2, "HSI16 clock selected as I2C clock"]

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