Skip to content

Commit 3d54137

Browse files
burrbullburrbull
authored
Merge pull request #1233 from stm32-rs/newotg
L4+ unify OTG and other patches
2 parents b4ba897 + 104048c commit 3d54137

File tree

16 files changed

+626
-626
lines changed

16 files changed

+626
-626
lines changed

‎CHANGELOG.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -230,6 +230,7 @@ Family-specific:
230230
* L4:
231231
* Update L4/L4+ vendor SVD bundles to v1.4 (#1084)
232232
* Add missing CAN registers to l4x3/x5 (#914)
233+
* L4+ unify patches (#1233)
233234

234235
* L5:
235236
* Fix DMA cluster (#922)

‎devices/collect/hash/v3.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,5 +12,5 @@ _array:
1212
CSR*:
1313
description: HASH context swap register %s
1414
_modify:
15-
CS0:
15+
"CS0,CSR0":
1616
name: CS

‎devices/collect/usb_otg/fs_global.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
_array:
22
DIEPTXF[1-5]:
33
displayName: DIEPTXF%s
4-
description: OTF_FS device IN endpoint transmit FIFO size register
4+
description: OTG_FS device IN endpoint transmit FIFO size register

‎devices/fields/flash/flash_l4+.yaml

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -39,13 +39,13 @@ ACR:
3939
WS15: [15, 15 wait states]
4040

4141
PDKEYR:
42-
PDKEY: [0, 0xFFFFFFFF]
42+
PDKEYR: [0, 0xFFFFFFFF]
4343

4444
KEYR:
45-
KEY: [0, 0xFFFFFFFF]
45+
KEYR: [0, 0xFFFFFFFF]
4646

4747
OPTKEYR:
48-
OPTKEY: [0, 0xFFFFFFFF]
48+
OPTKEYR: [0, 0xFFFFFFFF]
4949

5050
SR:
5151
PEMPTY:
@@ -292,7 +292,7 @@ OPTR:
292292
IWDG_STOP:
293293
Frozen: [0, Independent watchdog counter is frozen in Stop mode]
294294
Running: [1, Independent watchdog counter is running in Stop mode]
295-
IDWG_SW:
295+
IWDG_SW:
296296
Hardware: [0, Hardware independent watchdog]
297297
Software: [1, Software independent watchdog]
298298

‎devices/fields/pssi/pssi.yaml

Lines changed: 77 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -1,91 +1,90 @@
1-
PSSI:
2-
CR:
3-
OUTEN:
4-
ReceiveMode: [0, Data is input synchronously with PSSI_PDCK]
5-
TransmitMode: [1, Data is output synchronously with PSSI_PDCK]
1+
CR:
2+
OUTEN:
3+
ReceiveMode: [0, Data is input synchronously with PSSI_PDCK]
4+
TransmitMode: [1, Data is output synchronously with PSSI_PDCK]
65

7-
DMAEN:
8-
Disabled:
9-
[
10-
0,
11-
DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled.,
12-
]
13-
Enabled:
14-
[
15-
1,
16-
DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR,
17-
]
6+
DMAEN:
7+
Disabled:
8+
[
9+
0,
10+
DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled.,
11+
]
12+
Enabled:
13+
[
14+
1,
15+
DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR,
16+
]
1817

19-
DERDYCFG:
20-
Disabled: [0, PSSI_DE and PSSI_RDY both disabled]
21-
Rdy: [1, Only PSSI_RDY enabled]
22-
De: [2, Only PSSI_DE enabled]
23-
RdyDeAlt: [3, Both PSSI_RDY and PSSI_DE alternate functions enabled]
24-
RdyDe: [4, Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin]
25-
RdyRemapped: [5, "Only PSSI_RDY function enabled, but mapped to PSSI_DE pin"]
26-
DeRemapped: [6, "Only PSSI_DE function enabled, but mapped to PSSI_RDY pin"]
27-
RdyDeBidi: [7, Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin]
18+
DERDYCFG:
19+
Disabled: [0, PSSI_DE and PSSI_RDY both disabled]
20+
Rdy: [1, Only PSSI_RDY enabled]
21+
De: [2, Only PSSI_DE enabled]
22+
RdyDeAlt: [3, Both PSSI_RDY and PSSI_DE alternate functions enabled]
23+
RdyDe: [4, Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin]
24+
RdyRemapped: [5, "Only PSSI_RDY function enabled, but mapped to PSSI_DE pin"]
25+
DeRemapped: [6, "Only PSSI_DE function enabled, but mapped to PSSI_RDY pin"]
26+
RdyDeBidi: [7, Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin]
2827

29-
ENABLE:
30-
Disabled: [0, PSSI disabled]
31-
Enabled: [1, PSSI enabled]
28+
ENABLE:
29+
Disabled: [0, PSSI disabled]
30+
Enabled: [1, PSSI enabled]
3231

33-
EDM:
34-
BitWidth8: [0, Interface captures 8-bit data on every parallel data clock]
35-
BitWidth16: [3, The interface captures 16-bit data on every parallel data clock]
32+
EDM:
33+
BitWidth8: [0, Interface captures 8-bit data on every parallel data clock]
34+
BitWidth16: [3, The interface captures 16-bit data on every parallel data clock]
3635

37-
RDYPOL:
38-
ActiveLow: [0, PSSI_RDY active low (0 indicates that the receiver is ready to receive)]
39-
ActiveHigh: [1, PSSI_RDY active high (1 indicates that the receiver is ready to receive)]
36+
RDYPOL:
37+
ActiveLow: [0, PSSI_RDY active low (0 indicates that the receiver is ready to receive)]
38+
ActiveHigh: [1, PSSI_RDY active high (1 indicates that the receiver is ready to receive)]
4039

41-
DEPOL:
42-
ActiveLow: [0, PSSI_DE active low (0 indicates that data is valid)]
43-
ActiveHigh: [1, PSSI_DE active high (1 indicates that data is valid)]
40+
DEPOL:
41+
ActiveLow: [0, PSSI_DE active low (0 indicates that data is valid)]
42+
ActiveHigh: [1, PSSI_DE active high (1 indicates that data is valid)]
4443

45-
CKPOL:
46-
FallingEdge: [0, Falling edge active for inputs or rising edge active for outputs]
47-
RisingEdge: [1, Rising edge active for inputs or falling edge active for outputs]
44+
CKPOL:
45+
FallingEdge: [0, Falling edge active for inputs or rising edge active for outputs]
46+
RisingEdge: [1, Rising edge active for inputs or falling edge active for outputs]
4847

49-
SR:
50-
RTT1B:
51-
Ready:
52-
[
53-
1,
54-
"FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO",
55-
]
56-
NotReady: [0, FIFO is not ready for a 1-byte transfer]
48+
SR:
49+
RTT1B:
50+
Ready:
51+
[
52+
1,
53+
"FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO",
54+
]
55+
NotReady: [0, FIFO is not ready for a 1-byte transfer]
5756

58-
RTT4B:
59-
Ready:
60-
[
61-
1,
62-
"FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO",
63-
]
64-
NotReady: [0, FIFO is not ready for a four-byte transfer]
57+
RTT4B:
58+
Ready:
59+
[
60+
1,
61+
"FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO",
62+
]
63+
NotReady: [0, FIFO is not ready for a four-byte transfer]
6564

66-
RIS:
67-
OVR_RIS:
68-
Cleared: [0, No overrun/underrun occurred]
69-
Occurred:
70-
[
71-
1,
72-
"An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR",
73-
]
65+
RIS:
66+
OVR_RIS:
67+
Cleared: [0, No overrun/underrun occurred]
68+
Occurred:
69+
[
70+
1,
71+
"An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR",
72+
]
7473

75-
IER:
76-
OVR_IE:
77-
Disabled: [0, No interrupt generation]
78-
Enabled: [1, An interrupt is generated if either an overrun or an underrun error occurred]
74+
IER:
75+
OVR_IE:
76+
Disabled: [0, No interrupt generation]
77+
Enabled: [1, An interrupt is generated if either an overrun or an underrun error occurred]
7978

80-
MIS:
81-
OVR_MIS:
82-
Disabled: [0, No interrupt is generated when an overrun/underrun error occurs]
83-
Enabled:
84-
[
85-
1,
86-
An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER,
87-
]
79+
MIS:
80+
OVR_MIS:
81+
Disabled: [0, No interrupt is generated when an overrun/underrun error occurs]
82+
Enabled:
83+
[
84+
1,
85+
An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER,
86+
]
8887

89-
ICR:
90-
OVR_ISC:
91-
Clear: [1, Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS]
88+
ICR:
89+
OVR_ISC:
90+
Clear: [1, Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS]

‎devices/patches/flash/l4+.yaml

Lines changed: 6 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
1+
_include:
2+
- flash_boot0s.yaml
3+
14
_add:
25
CFGR:
36
description: flash configuration register
@@ -17,21 +20,6 @@ _modify:
1720
WRP1BR:
1821
addressOffset: 0x4C
1922

20-
KEYR:
21-
_modify:
22-
KEYR:
23-
name: KEY
24-
25-
OPTKEYR:
26-
_modify:
27-
OPTKEYR:
28-
name: OPTKEY
29-
30-
PDKEYR:
31-
_modify:
32-
PDKEYR:
33-
name: PDKEY
34-
3523
SR:
3624
_add:
3725
PEMPTY:
@@ -54,20 +42,15 @@ ECCR:
5442

5543
OPTR:
5644
_add:
57-
nBOOT0:
58-
description: nBOOT0 option bit
59-
bitOffset: 27
60-
bitWidth: 1
61-
nSWBOOT0:
62-
description: nSWBOOT0 option bit
63-
bitOffset: 26
64-
bitWidth: 1
6545
DBANK:
6646
bitOffset: 22
6747
bitWidth: 1
6848
DB1M:
6949
bitOffset: 21
7050
bitWidth: 1
51+
_modify:
52+
IDWG_SW:
53+
name: IWDG_SW
7154

7255
_delete:
7356
- DUALBANK

‎devices/patches/hash/hash_l4+.yaml

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
_modify:
22
HR0:
33
name: HRA0
4+
displayName: HRA0
45
# strip doesn't work because otherwise we end up with two HRA0 registers...
56
HASH_HR0:
67
name: HR0
@@ -21,6 +22,7 @@ _modify:
2122

2223
_add:
2324
HRA1:
25+
displayName: HRA1
2426
description: digest registers
2527
addressOffset: 0x10
2628
resetValue: 0x0
@@ -30,6 +32,7 @@ _add:
3032
bitOffset: 0
3133
bitWidth: 32
3234
HRA2:
35+
displayName: HRA2
3336
description: digest registers
3437
addressOffset: 0x14
3538
resetValue: 0x0
@@ -39,6 +42,7 @@ _add:
3942
bitOffset: 0
4043
bitWidth: 32
4144
HRA3:
45+
displayName: HRA3
4246
description: digest registers
4347
addressOffset: 0x18
4448
resetValue: 0x0
@@ -48,6 +52,7 @@ _add:
4852
bitOffset: 0
4953
bitWidth: 32
5054
HRA4:
55+
displayName: HRA4
5156
description: digest registers
5257
addressOffset: 0x1C
5358
resetValue: 0x0

‎devices/patches/octospim/l4+.yaml

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,14 @@
1-
OCTOSPIM:
2-
_add:
3-
CR:
4-
description: configuration register
5-
addressOffset: 0x0
6-
resetValue: 0x0
7-
fields:
8-
MUXEN:
9-
description: Multiplexed mode enable
10-
bitOffset: 0
11-
bitWidth: 1
12-
REQ2ACK_TIME:
13-
description: REQ to ACK time
14-
bitOffset: 16
15-
bitWidth: 8
1+
_add:
2+
CR:
3+
description: configuration register
4+
addressOffset: 0x0
5+
resetValue: 0x0
6+
fields:
7+
MUXEN:
8+
description: Multiplexed mode enable
9+
bitOffset: 0
10+
bitWidth: 1
11+
REQ2ACK_TIME:
12+
description: REQ to ACK time
13+
bitOffset: 16
14+
bitWidth: 8

0 commit comments

Comments
 (0)