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bors[bot]newAMadamgreig
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Merge #628
628: stm32wl: add register descriptions for dual-core variants r=adamgreig a=newAM This adds register descriptions for registers that are exclusive to the dual-core STM32WL's cc `@jorgeig-space` Co-authored-by: Alex Martens <alexmgit@protonmail.com> Co-authored-by: Adam Greig <adam@adamgreig.com>
2 parents 5c8b42d + 6c1aa66 commit 63311f2

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8 files changed

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8 files changed

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lines changed

‎devices/stm32wl5x_cm0p.yaml

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,10 @@ HSEM:
4141
HSEM_C2ICR:
4242
access: read-write
4343

44+
IPCC:
45+
_strip:
46+
- IPCC_
47+
4448
TIM1:
4549
_modify:
4650
CCMR3OutputComparemode:
@@ -125,9 +129,11 @@ _include:
125129
- ../peripherals/dma/dmamux_wl.yaml
126130
- ../peripherals/exti/exti.yaml
127131
- ../peripherals/flash/flash_wl.yaml
132+
- ../peripherals/flash/flash_wl_c2.yaml
128133
- ../peripherals/gpio/gpio_v2_common.yaml
129134
- ../peripherals/gpio/gpio_wl_with_brr.yaml
130135
- ../peripherals/hsem/hsem_wl.yaml
136+
- ../peripherals/ipcc/ipcc_wl.yaml
131137
- ../peripherals/i2c/i2c_v2.yaml
132138
- ../peripherals/iwdg/iwdg.yaml
133139
- ../peripherals/iwdg/iwdg_sr.yaml
@@ -136,7 +142,9 @@ _include:
136142
- ../peripherals/usart/lpuart_wl.yaml
137143
- ../peripherals/pka/pka.yaml
138144
- ../peripherals/pwr/pwr_wl.yaml
145+
- ../peripherals/pwr/pwr_wl_c2.yaml
139146
- ../peripherals/rcc/rcc_wl.yaml
147+
- ../peripherals/rcc/rcc_wl_c2.yaml
140148
- ../peripherals/rtc/rtc_wl.yaml
141149
- ../peripherals/rng/rng_wl.yaml
142150
- ../peripherals/spi/spi_v2.yaml

‎devices/stm32wl5x_cm4.yaml

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,10 @@ HSEM:
4141
HSEM_C2ICR:
4242
access: read-write
4343

44+
IPCC:
45+
_strip:
46+
- IPCC_
47+
4448
TIM1:
4549
_modify:
4650
CCMR3OutputComparemode:
@@ -128,9 +132,11 @@ _include:
128132
- ../peripherals/dbg/dbg_wl.yaml
129133
- ../peripherals/exti/exti.yaml
130134
- ../peripherals/flash/flash_wl.yaml
135+
- ../peripherals/flash/flash_wl_c2.yaml
131136
- ../peripherals/gpio/gpio_v2_common.yaml
132137
- ../peripherals/gpio/gpio_wl_with_brr.yaml
133138
- ../peripherals/hsem/hsem_wl.yaml
139+
- ../peripherals/ipcc/ipcc_wl.yaml
134140
- ../peripherals/i2c/i2c_v2.yaml
135141
- ../peripherals/iwdg/iwdg.yaml
136142
- ../peripherals/iwdg/iwdg_sr.yaml
@@ -139,7 +145,9 @@ _include:
139145
- ../peripherals/usart/lpuart_wl.yaml
140146
- ../peripherals/pka/pka.yaml
141147
- ../peripherals/pwr/pwr_wl.yaml
148+
- ../peripherals/pwr/pwr_wl_c2.yaml
142149
- ../peripherals/rcc/rcc_wl.yaml
150+
- ../peripherals/rcc/rcc_wl_c2.yaml
143151
- ../peripherals/rtc/rtc_wl.yaml
144152
- ../peripherals/rng/rng_wl.yaml
145153
- ../peripherals/spi/spi_v2.yaml

‎peripherals/flash/flash_wl.yaml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ FLASH:
55
Empty: [1, "User Flash empty"]
66
PES:
77
Granted: [0, "Flash program and erase operations granted"]
8-
Suspended: [1, "Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_SR is set when PES bit in FLASH_ACRis set"]
8+
Suspended: [1, "Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_SR is set when PES bit in FLASH_ACR is set"]
99
DCRST:
1010
NotReset: [0, "Data cache is not reset"]
1111
Reset: [1, "Data cache is reset"]
@@ -156,7 +156,7 @@ FLASH:
156156
Done: [0, "Options modification completed or idle"]
157157
_write:
158158
Start: [1, "Trigger options programming operation"]
159-
PNB: [0, 0x63]
159+
PNB: [0, 0x7F]
160160
MER:
161161
NoErase: [0, "No mass erase"]
162162
MassErase: [1, "Trigger mass erase"]

‎peripherals/flash/flash_wl_c2.yaml

Lines changed: 145 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,145 @@
1+
FLASH:
2+
IPCCBR:
3+
IPCCDBA: [0, 0x3FFF]
4+
C2ACR:
5+
PES:
6+
Granted: [0, "Flash program and erase operations granted"]
7+
Suspended: [1, "Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_C2SR is set when PES bit in FLASH_C2ACR is set"]
8+
ICRST:
9+
NotReset: [0, "CPU2 instruction cache is not reset"]
10+
Reset: [1, "CPU2 instruction cache is reset"]
11+
ICEN:
12+
Disabled: [0, "CPU2 instruction cache is disabled"]
13+
Enabled: [1, "CPU2 instruction cache is enabled"]
14+
PRFTEN:
15+
Disabled: [0, "CPU2 prefetch is disabled"]
16+
Enabled: [1, "CPU2 prefetch is enabled"]
17+
C2SR:
18+
_modify:
19+
MISERR:
20+
name: MISSERR
21+
PESD:
22+
Granted: [0, "Flash program and erase operations granted"]
23+
Suspended: [1, "Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set."]
24+
CFGBSY:
25+
Free: [0, "PG, PNB, PER, MER bits available for writing"]
26+
Busy: [1, "PG, PNB, PER, MER bits not available for writing (operation ongoing)"]
27+
BSY:
28+
Inactive: [0, "No write/erase operation is in progress"]
29+
Active: [1, "No write/erase operation is in progress"]
30+
RDERR:
31+
_read:
32+
NoError: [0, "No read-only error happened"]
33+
Error: [1, "Read-only error happened"]
34+
_write:
35+
Clear: [1, "Clear the flag"]
36+
FASTERR:
37+
_read:
38+
NoError: [0, "No fast programming error happened"]
39+
Error: [1, "Fast programming error happened"]
40+
_write:
41+
Clear: [1, "Clear the flag"]
42+
MISSERR:
43+
_read:
44+
NoError: [0, "No fast programming data miss error happened"]
45+
Error: [1, "Fast programming data miss error happened"]
46+
_write:
47+
Clear: [1, "Clear the flag"]
48+
PGSERR:
49+
_read:
50+
NoError: [0, "No fast programming sequence error happened"]
51+
Error: [1, "Fast programming sequence error happened"]
52+
_write:
53+
Clear: [1, "Clear the flag"]
54+
SIZERR:
55+
_read:
56+
NoError: [0, "No size error happened"]
57+
Error: [1, "Size error happened"]
58+
_write:
59+
Clear: [1, "Clear the flag"]
60+
PGAERR:
61+
_read:
62+
NoError: [0, "No programming alignment error happened"]
63+
Error: [1, "Programming alignment error happened"]
64+
_write:
65+
Clear: [1, "Clear the flag"]
66+
WRPERR:
67+
_read:
68+
NoError: [0, "No write protection error happened"]
69+
Error: [1, "Write protection error happened"]
70+
_write:
71+
Clear: [1, "Clear the flag"]
72+
PROGERR:
73+
_read:
74+
NoError: [0, "No size programming error happened"]
75+
Error: [1, "Programming error happened"]
76+
_write:
77+
Clear: [1, "Clear the flag"]
78+
OPERR:
79+
_read:
80+
NoError: [0, "No memory opreation error happened"]
81+
Error: [1, "Memory operation error happened"]
82+
_write:
83+
Clear: [1, "Clear the flag"]
84+
EOP:
85+
_read:
86+
NoEvent: [0, "No EOP operation occurred"]
87+
Event: [1, "An EOP event occurred"]
88+
_write:
89+
Clear: [1, "Clear the flag"]
90+
C2CR:
91+
RDERRIE:
92+
Disabled: [0, "PCROP read error interrupt disable"]
93+
Enabled: [1, "PCROP read error interrupt enable"]
94+
ERRIE:
95+
Disabled: [0, "OPERR Error interrupt disable"]
96+
Enabled: [1, "OPERR Error interrupt enable"]
97+
EOPIE:
98+
Disabled: [0, "End of program interrupt disable"]
99+
Enabled: [1, "End of program interrupt enable"]
100+
FSTPG:
101+
Disabled: [0, "Fast programming disabled"]
102+
Enabled: [1, "Fast programming enabled"]
103+
STRT:
104+
_read:
105+
Done: [0, "Options modification completed or idle"]
106+
_write:
107+
Start: [1, "Trigger options programming operation"]
108+
PNB: [0, 0x7F]
109+
MER:
110+
NoErase: [0, "No mass erase"]
111+
MassErase: [1, "Trigger mass erase"]
112+
PER:
113+
Disabled: [0, "Page erase disabled"]
114+
Enabled: [1, "Page erase enabled"]
115+
PG:
116+
Disabled: [0, "Flash programming disabled"]
117+
Enabled: [1, "Flash programming enabled"]
118+
SFR:
119+
SUBGHSPISD:
120+
Enabled: [0, "sub-GHz radio SPI security enabled"]
121+
Disabled: [1, "sub-GHz radio SPI security disabled"]
122+
HDPAD:
123+
Enabled: [0, "User Flash memory hide protection area enabled. HDPSA[6:0] contains the start address of the first 2-Kbyte page of the user Flash memory hide protection area"]
124+
Disabled: [1, "User Flash memory hide protection area disabled"]
125+
HDPSA: [0, 0x7F]
126+
DDS:
127+
Enabled: [0, "CPU2 debug access enabled"]
128+
Disabled: [1, "CPU2 debug access disabled"]
129+
FSD:
130+
Secure: [0, "System and Flash memory secure"]
131+
NonSecure: [1, "System and Flash memory non-secure"]
132+
SFSA: [0, 0x7F]
133+
SRRVR:
134+
C2OPT:
135+
SRAM: [0, "SBRV offset addresses SRAM1 or SRAM2, from start address 0x2000_0000 + SBRV"]
136+
Flash: [1, "SBRV offset addresses the Flash memory, from start address 0x0800_0000 + SBRV"]
137+
NBRSD:
138+
Secure: [0, 'SRAM1 is secure. SNBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure non-backup SRAM1 area']
139+
NonSecure: [1, 'SRAM1 is non-secure']
140+
SNBRSA: [0, 0x1F]
141+
BRSD:
142+
Secure: [0, 'SRAM2 is secure. SNBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure backup SRAM2 area']
143+
NonSecure: [1, 'SRAM2 is non-secure']
144+
SBRSA: [0, 0x1F]
145+
SBRV: [0, 0xFFFF]

‎peripherals/ipcc/ipcc_wl.yaml

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,26 @@
1+
IPCC:
2+
"C[12]CR":
3+
TXFIE:
4+
Enabled: [1, "Enable an unmasked processor transmit channel free to generate a TX free interrupt"]
5+
Disabled: [0, "Processor TX free interrupt disabled"]
6+
RXOIE:
7+
Enabled: [1, "Enable an unmasked processor receive channel occupied to generate an RX occupied interrupt"]
8+
Disabled: [0, "Processor RX occupied interrupt disabled"]
9+
"C[12]MR":
10+
"CH[1-6]FM":
11+
Masked: [1, "Transmit channel n free interrupt masked"]
12+
Unmasked: [0, "Transmit channel n free interrupt not masked"]
13+
"CH[1-6]OM":
14+
Masked: [1, "Receive channel n occupied interrupt masked"]
15+
Unmasked: [0, "Receive channel n occupied interrupt not masked"]
16+
"C[12]SCR":
17+
"CH[1-6]S":
18+
Set: [1, "Processor transmit channel n status bit set"]
19+
NoAction: [0, "No action"]
20+
"CH[1-6]C":
21+
Clear: [1, "Processor receive channel n status bit clear"]
22+
NoAction: [0, "No action"]
23+
"C[12]TOC[12]SR":
24+
"CH[1-5]F":
25+
Occupied: [1, "Channel occupied, data can be read by the receiving processor. Generates a channel RX occupied interrupt to the other processor, when unmasked"]
26+
Free: [0, "Channel free, data can be written by the sending processor. Generates a channel TX free interrupt to the current processor, when unmasked"]

‎peripherals/pwr/pwr_wl.yaml

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -42,14 +42,14 @@ PWR:
4242
Enabled: [1, "PVD Enabled"]
4343
CR3:
4444
EIWUL:
45-
Disabled: [0, "Internal wakeup line interrupt to CPU disabled"]
46-
Enabled: [1, "Internal wakeup line interrupt to CPU enabled"]
45+
Disabled: [0, "Internal wakeup line interrupt to CPU1 disabled"]
46+
Enabled: [1, "Internal wakeup line interrupt to CPU1 enabled"]
4747
EWRFIRQ:
48-
Disabled: [0, "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU."]
49-
Enabled: [1, "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU."]
48+
Disabled: [0, "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU1."]
49+
Enabled: [1, "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU1."]
5050
EWRFBUSY:
51-
Disabled: [0, "Radio Busy is disabled and does not trigger a wakeup from Standby event to CPUwhen a rising or a falling edge occurs"]
52-
Enabled: [1, "Radio Busy is enabled and triggers a wakeup from Standby event to CPUwhen a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4"]
51+
Disabled: [0, "Radio Busy is disabled and does not trigger a wakeup from Standby event to CPU1 when a rising or a falling edge occurs"]
52+
Enabled: [1, "Radio Busy is enabled and triggers a wakeup from Standby event to CPU1 when a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4"]
5353
APC:
5454
Disabled: [0, "I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied"]
5555
Enabled: [1, "PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os"]

‎peripherals/pwr/pwr_wl_c2.yaml

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
PWR:
2+
C2CR1:
3+
FPDS:
4+
Idle: [0, "Flash memory in Idle mode when system is in LPSleep mode"]
5+
PowerDown: [1, "Flash memory in Power-down mode when system is in LPSleep mode"]
6+
FPDR:
7+
Idle: [0, "Flash memory in Idle mode when system is in LPRun mode"]
8+
PowerDown: [1, "Flash memory in Power-down mode when system is in LPRun mode"]
9+
LPMS:
10+
Stop0: [0, "Stop 0 mode"]
11+
Stop1: [1, "Stop 1 mode"]
12+
Stop2: [2, "Stop 2 mode"]
13+
Standby: [3, "Standby mode"]
14+
Shutdown: [4, "Shutdown mode"]
15+
C2CR3:
16+
EIWUL:
17+
Disabled: [0, "Internal wakeup line interrupt to CPU2 disabled"]
18+
Enabled: [1, "Internal wakeup line interrupt to CPU2 enabled"]
19+
EWRFIRQ:
20+
Disabled: [0, "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU2."]
21+
Enabled: [1, "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU2."]
22+
EWRFBUSY:
23+
Disabled: [0, "Radio Busy is disabled and does not trigger a wakeup from Standby event to CPU2 when a rising or a falling edge occurs"]
24+
Enabled: [1, "Radio Busy is enabled and triggers a wakeup from Standby event to CPU2 when a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4"]
25+
APC:
26+
Disabled: [0, "I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied"]
27+
Enabled: [1, "PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os"]
28+
EWPVD:
29+
Disabled: [0, "PVD not enabled by the sub-GHz radio active state"]
30+
Enabled: [1, "PVD enabled while the sub-GHz radio is active"]
31+
EWUP3:
32+
Disabled: [0, "WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode"]
33+
Enabled: [1, "WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode)"]
34+
EWUP2:
35+
Disabled: [0, "WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode"]
36+
Enabled: [1, "WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode)"]
37+
EWUP1:
38+
Disabled: [0, "WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode"]
39+
Enabled: [1, "WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode)"]

‎peripherals/rcc/rcc_wl_c2.yaml

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
RCC:
2+
"C2A[PH]B[123]ENR":
3+
"*":
4+
Disabled: [0, "Clock disabled"]
5+
Enabled: [1, "Clock enabled"]
6+
7+
"C2APB[123]ENR?":
8+
"*":
9+
Disabled: [0, "Clock disabled"]
10+
Enabled: [1, "Clock enabled"]
11+
12+
"C2A[PH]B[123]SMENR?":
13+
"*":
14+
Disabled: [0, "Clock disabled"]
15+
Enabled: [1, "Clock enabled"]

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