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Merge pull request #1220 from stm32-rs/rng
RNG enums
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‎CHANGELOG.md

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* Add DAC enums
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* DCMI enums
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* DFSDM enums and fixes
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* RNG enums
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* SDIO/SDMMC v1
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* TSC enums and arrays
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* USB v2

‎devices/fields/rng/rng_f4.yaml

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‎devices/fields/rng/rng_f4_ced.yaml

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‎devices/fields/rng/rng_v1.yaml

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‎devices/fields/rng/rng_v1_ced.yaml

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‎devices/fields/rng/v1.yaml

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CR:
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RNGEN:
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Disabled: [0, Random number generator is disabled]
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Enabled: [1, Random number generator is enabled]
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IE:
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Disabled: [0, RNG interrupt is disabled]
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Enabled: [1, RNG interrupt is enabled]
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"?~CED":
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Enabled: [0, Clock error detection is enabled]
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Disabled: [1, Clock error detection is disabled]
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SR:
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"[CS]EIS":
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_W0C:
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Clear: [0, Clear flag]
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SEIS:
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_read:
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NoFault: [0, No faulty sequence detected]
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Fault:
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[
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1,
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"At least one faulty sequence has been detected. See **SECS** bit description for details.\nAn interrupt is pending if IE = 1 in the RNG_CR register.",
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]
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CEIS:
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_read:
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Correct: [0, The RNG clock is correct]
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Slow: [1, "The RNG has been detected too slow\nAn interrupt is pending if IE = 1 in the RNG_CR register"]
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SECS:
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NoFault:
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[
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0,
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"No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.",
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]
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Fault: [1, At least one faulty sequence has been detected - see ref manual for details]
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CECS:
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Correct:
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[
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0,
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"The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.",
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]
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Slow: [1, The RNG clock is too slow]
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DRDY:
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Invalid: [0, "The RNG_DR register is not yet valid, no random data is available"]
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Valid:
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[
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1,
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"The RNG_DR register contains valid random data.\nOnce the RNG_DR register has been read, this bit returns to 0 until a new random value is generated.",
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]
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DR:
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RNDATA: [0, 0xFFFFFFFF]

‎devices/fields/rng/rng_wl.yaml renamed to ‎devices/fields/rng/v2.yaml

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_include:
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- ./rng_v1.yaml
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- ./rng_v1_ced.yaml
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- ./v1.yaml
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CR:
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CONFIGLOCK:
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]
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Custom: [1, Custom values for NIST compliant RNG]
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SR:
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SEIS:
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NoFault: [0, No faulty sequence detected]
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Fault: [1, At least one faulty sequence has been detected]
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CEIS:
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Correct: [0, "The RNG clock is correct (fRNGCLK> fHCLK/32)"]
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Slow: [1, "The RNG clock before internal divider has been detected too slow (fRNGCLK< fHCLK/32)"]
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SECS:
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_read:
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NoFault:
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[
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0,
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"No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered",
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]
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Fault: [1, At least one faulty sequence has been detected - see ref manual for details]
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CECS:
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_read:
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Correct: [0, "The RNG clock is correct (fRNGCLK> fHCLK/32)"]
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Slow: [1, "The RNG clock before internal divider has been detected too slow (fRNGCLK< fHCLK/32)"]
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DRDY:
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Invalid: [0, "The RNG_DR register is not yet valid, no random data is available"]
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Valid: [1, The RNG_DR register contains valid random data]
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HTCR:
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HTCFG:
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Magic: [0x1759_0ABC, Magic number to be written before any write (0x1759_0ABC)]

‎devices/patches/rcc/h7_common_singlecore.yaml

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_include: h7_usb1otghs.yaml
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_modify:
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CIFR:
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access: read-only

‎devices/stm32f215.yaml

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- fields/rcc/v2/i2s.yaml
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- fields/rcc/v2/i2s_pll.yaml
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RNG: {}
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RNG:
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_include:
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- fields/rng/v1.yaml
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RTC:
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_derive:

‎devices/stm32f217.yaml

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- fields/rcc/v2/i2s.yaml
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- fields/rcc/v2/i2s_pll.yaml
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RNG: {}
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RNG:
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_include:
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- fields/rng/v1.yaml
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RTC:
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_derive:

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