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Merge branch 'master' into h7-hi-mem-flash
2 parents bfc8c07 + 34987dd commit 90ddf07

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‎CHANGELOG.md

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@@ -2,8 +2,8 @@
22

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## [Unreleased]
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5-
* Updated to `svd2rust` 0.36.1, `svdtools` 0.4.6, `form` 0.12.1, use tools binaries for CI (#1174)
6-
* bump `defmt` dependency to 1.0
5+
* Updated to `svd2rust` 0.36.1, `svdtools` 0.4.6, `form` 0.13.0, use tools binaries for CI (#1174)
6+
* bump `defmt` dependency to 1.0 (#1209)
77
* Use `svd2rust.toml` config, use custom ident suffixes (#948)
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* Replace `makehtml.py` with `svdtools html` (#881)
99
* Remove workaround for bug in duckscript's `mv` (#981)
@@ -74,21 +74,22 @@
7474
* F2, F4, F7: Add definitions for OPTCR, OPTCR1 and OPTCR2 registers of FLASH peripheral (#1157)
7575
* F2, F4, F7: Fix several fields of FLASH peripheral and reorganise 'patches', 'fields' and 'collect' according to impacted registers (#1161)
7676
* F1, F2, F4: Derive identical UART registers from USART1, add GPTR.PSC (#1179)
77-
* CCMR3_Output fix
78-
* CRC enums and fixes
79-
* Add DAC enums
80-
* DCMI enums
81-
* DFSDM enums and fixes
82-
* RNG enums
83-
* SDIO/SDMMC v1
84-
* TSC enums and arrays
85-
* USB v2
86-
* Use arrays for DAC channels
87-
* Derive TIM registers
77+
* CCMR3_Output fix (#1184)
78+
* CRC enums and fixes (#1206)
79+
* Add DAC enums (#1196)
80+
* DCMI enums (#1205)
81+
* DFSDM enums and fixes (#1218)
82+
* RNG enums (#1220)
83+
* SDIO/SDMMC v1 (#1204)
84+
* OCTOSPI, TAMP, LTDC enums (#1226)
85+
* TSC enums and arrays (#1221)
86+
* USB v2 (#1202)
87+
* Use arrays for DAC channels (#1197)
88+
* Derive TIM registers (#1184)
8889
* Update README.md (#1152)
89-
* Add SPI enums for G4, U5, H7+
90-
* FMC/FSMC enums, arrays & derives
91-
* CRS enums
90+
* Add SPI enums for G4, U5, H7+ (#1199)
91+
* FMC/FSMC enums, arrays & derives (#1200)
92+
* CRS enums (#1208)
9293
* HRTIM:
9394
* H7 & G4 fixes and enums (#1021) (#1022)
9495
* Remove timer block suffixes from register/field names (#1023)

‎README.md

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@@ -95,7 +95,7 @@ contain the latest patches and updates.
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* On x86-64 Linux, run `make install` to download pre-built binaries at the
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current version used by stm32-rs
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* Otherwise, build using `cargo` (double check versions against `scripts/tool_install.sh`):
98-
* `cargo install form --version 0.12.1`
98+
* `cargo install form --version 0.13.0`
9999
* `cargo install svdtools --version 0.4.6`
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* `cargo install svd2rust --version 0.36.1`
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* Install rustfmt: `rustup component add rustfmt`

‎devices/collect/lpgpio/lp.yaml

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MODER:
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_array:
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MODE*: {}
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IDR:
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_array:
6+
ID*: {}
7+
ODR:
8+
_array:
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OD*: {}
10+
BSRR:
11+
_array:
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BS*: {}
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BR*: {}
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BRR:
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_array:
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BR*: {}

‎devices/collect/tamp/bkp.yaml

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This file was deleted.

‎devices/fields/octospi/common.yaml

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@@ -69,7 +69,6 @@ DCR1:
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"HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used",
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]
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DEVSIZE: [0, 0x1F]
72-
CSHT: [0, 0x3F]
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DLYBYP:
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DelayBlockEnabled:
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[
@@ -99,7 +98,7 @@ DCR2:
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10099
DCR3:
101100
CSBOUND: [0, 0x1F]
102-
MAXTRAN: [0, 0xFF]
101+
"?~MAXTRAN": [0, 0xFF]
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104103
DCR4:
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REFRESH: [0, 0xFFFFFFFF]
@@ -163,7 +162,7 @@ PIR:
163162
INTERVAL: [0, 0xFFFF]
164163

165164
CCR:
166-
SIOO:
165+
"?~SIOO":
167166
SendEveryTransaction: [0, Send instruction on every transaction]
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SendOnlyFirstCmd: [1, Send instruction only for the first command]
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DQSE:

‎devices/fields/octospi/l4.yaml

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@@ -7,3 +7,5 @@ CR:
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DMM:
88
Disabled: [0, Dual-quad configuration disabled]
99
Enabled: [1, Dual-quad configuration enabled]
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DCR1:
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CSHT: [0, 0x3F]

‎devices/fields/octospi/l5.yaml

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_include:
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- common.yaml
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CR:
4+
FSEL:
5+
FLASH1: [0, "FLASH 1 selected (data exchanged over IO[3:0])"]
6+
FLASH2: [1, "FLASH 2 selected (data exchanged over IO[7:4])"]
7+
DMM:
8+
Disabled: [0, Dual-quad configuration disabled]
9+
Enabled: [1, Dual-quad configuration enabled]
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DCR1:
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CSHT: [0, 7]

‎devices/fields/octospi/u5.yaml

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DMM:
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Disabled: [0, Dual-memory configuration disabled]
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Enabled: [1, Dual-memory configuration enabled]
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DCR1:
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CSHT: [0, 0x3F]

‎devices/fields/tamp/tamp_wl.yaml

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COUNTR:
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COUNT: [0, 0xFFFFFFFF]
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107-
BKP?R:
108-
BKP: [0, 0xFFFFFFFF]
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BKP1?R:
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BKP?*R:
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BKP: [0, 0xFFFFFFFF]

‎devices/patches/octospi/add_wrap.yaml

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_add:
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WPCCR:
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description: wrap communication configuration register
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addressOffset: 0x140
5+
resetValue: 0x00000000
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fields:
7+
DQSE:
8+
description: DQS enable
9+
bitOffset: 29
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bitWidth: 1
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DDTR:
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description: Data double transfer rate
13+
bitOffset: 27
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bitWidth: 1
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DMODE:
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description: Data mode
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bitOffset: 24
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bitWidth: 3
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ABSIZE:
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description: Alternate bytes size
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bitOffset: 20
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bitWidth: 2
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ABDTR:
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description: Alternate bytes double transfer rate
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bitOffset: 19
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bitWidth: 1
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ABMODE:
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description: Alternate-byte mode
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bitOffset: 16
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bitWidth: 3
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ADSIZE:
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description: Address size
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bitOffset: 12
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bitWidth: 2
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ADDTR:
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description: Address double transfer rate
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bitOffset: 11
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bitWidth: 1
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ADMODE:
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description: Address mode
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bitOffset: 8
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bitWidth: 3
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ISIZE:
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description: Instruction size
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bitOffset: 4
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bitWidth: 2
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IDTR:
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description: Instruction double transfer rate
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bitOffset: 3
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bitWidth: 1
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IMODE:
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description: Instruction mode
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bitOffset: 0
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bitWidth: 3
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WPTCR:
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description: Wrap timing configuration register
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addressOffset: 0x148
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resetValue: 0x00000000
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fields:
61+
SSHIFT:
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description: Sample shift
63+
bitOffset: 30
64+
bitWidth: 1
65+
DHQC:
66+
description: Delay hold quarter cycle
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bitOffset: 28
68+
bitWidth: 1
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DCYC:
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description: Number of dummy cycles
71+
bitOffset: 0
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bitWidth: 5
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74+
WPIR:
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description: Wrap instruction register
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addressOffset: 0x150
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resetValue: 0x00000000
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fields:
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INSTRUCTION:
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description: Instruction
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bitOffset: 0
82+
bitWidth: 32
83+
84+
WPABR:
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description: Wrap alternate bytes register
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addressOffset: 0x160
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resetValue: 0x00000000
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fields:
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ALTERNATE:
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description: Alternate bytes
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bitOffset: 0
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bitWidth: 32

‎devices/patches/octospi/address.yaml

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AR:
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_modify:
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ADRESS:
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name: ADDRESS

‎devices/patches/octospi/ddm.yaml

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CR:
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_modify:
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DQM:
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name: DMM
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description: Dual-memory configuration

‎devices/patches/octospi/h7.yaml

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# OCTOSPI v1 peripheral on at least H7
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_include:
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- address.yaml
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- ddm.yaml
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DCR1:
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_add:
59
DLYBYP:
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_modify:
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REFRESH:
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bitWidth: 32
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AR:
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_modify:
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ADRESS:
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name: ADDRESS

‎devices/patches/octospi/l4+.yaml

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_include:
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- ddm.yaml
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- add_wrap.yaml
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_delete:
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- HWCFGR
37
- VER
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_add:
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DCR4:
9-
description: Device configuration register 4
13+
displayName: DCR4
14+
description: device configuration register 4
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addressOffset: 0x14
16+
access: read-write
1117
resetValue: 0x00000000
1218
fields:
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REFRESH:
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description: Refresh rate
1521
bitOffset: 0
1622
bitWidth: 32
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18-
WPCCR:
19-
description: wrap communication configuration register
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addressOffset: 0x140
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resetValue: 0x00000000
22-
fields:
23-
DQSE:
24-
description: DQS enable
25-
bitOffset: 29
26-
bitWidth: 1
27-
DDTR:
28-
description: Data double transfer rate
29-
bitOffset: 27
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bitWidth: 1
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DMODE:
32-
description: Data mode
33-
bitOffset: 24
34-
bitWidth: 3
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ABSIZE:
36-
description: Alternate bytes size
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bitOffset: 20
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bitWidth: 2
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ABDTR:
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description: Alternate bytes double transfer rate
41-
bitOffset: 19
42-
bitWidth: 1
43-
ABMODE:
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description: Alternate-byte mode
45-
bitOffset: 16
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bitWidth: 3
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ADSIZE:
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description: Address size
49-
bitOffset: 12
50-
bitWidth: 2
51-
ADDTR:
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description: Address double transfer rate
53-
bitOffset: 11
54-
bitWidth: 1
55-
ADMODE:
56-
description: Address mode
57-
bitOffset: 8
58-
bitWidth: 3
59-
ISIZE:
60-
description: Instruction size
61-
bitOffset: 4
62-
bitWidth: 2
63-
IDTR:
64-
description: Instruction double transfer rate
65-
bitOffset: 3
66-
bitWidth: 1
67-
IMODE:
68-
description: Instruction mode
69-
bitOffset: 0
70-
bitWidth: 3
71-
72-
WPTCR:
73-
description: Wrap timing configuration register
74-
addressOffset: 0x148
75-
resetValue: 0x00000000
76-
fields:
77-
SSHIFT:
78-
description: Sample shift
79-
bitOffset: 30
80-
bitWidth: 1
81-
DHQC:
82-
description: Delay hold quarter cycle
83-
bitOffset: 28
84-
bitWidth: 1
85-
DCYC:
86-
description: Number of dummy cycles
87-
bitOffset: 0
88-
bitWidth: 5
89-
90-
WPIR:
91-
description: Wrap instruction register
92-
addressOffset: 0x150
93-
resetValue: 0x00000000
94-
fields:
95-
INSTRUCTION:
96-
description: Instruction
97-
bitOffset: 0
98-
bitWidth: 32
99-
100-
WPABR:
101-
description: Wrap alternate bytes register
102-
addressOffset: 0x160
103-
resetValue: 0x00000000
104-
fields:
105-
ALTERNATE:
106-
description: Alternate bytes
107-
bitOffset: 0
108-
bitWidth: 32
109-
110-
CR:
111-
_modify:
112-
DQM:
113-
name: DMM
114-
description: Dual-memory configuration
24+
_modify:
25+
SR:
26+
access: read-only
11527

11628
DCR1:
11729
_modify:
11830
MTYP:
11931
bitWidth: 3
32+
CSHT:
33+
bitWidth: 6
12034

12135
_add:
12236
DLYBYP:
@@ -130,3 +44,6 @@ DCR3:
13044
description: Maximum transfer
13145
bitOffset: 0
13246
bitWidth: 8
47+
48+
WCCR:
49+
_delete: SIOO

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