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bors[bot]maximeborgesrichardeoinkorken89Gekkio
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700: F7/tim: access to bits() without unsafe for single-field registers r=adamgreig a=maximeborges When writing to `CNT`/`ARR`/`CCR%s` single-field registers via `bits()`, it requires the use of unsafe for timers 9 to 14. This PR allows to use safe `bits()` writing just like the other timers 704: H7 flash: Add registers that are mirrored between banks for rm0399 r=adamgreig a=richardeoin See RM0399 Rev 3 Table 19. These mirrored registers are present on other H7 parts Including these registers changes the svd2rust access style for bank2, from a public member to a method that returns a reference. This makes it consistent with other H7 parts 705: Added CH2 on TIM15 for STM32L4 r=adamgreig a=korken89 706: Apply OTG_FS v1 fixes to F215/F217 r=adamgreig a=Gekkio These devices have OTG_FS with CID 0x0000 1200 (same as F401), and the SVD files seem to have the same bugs as F401/F411 SVD files. Co-authored-by: Maxime Borges <contact@maximeborg.es> Co-authored-by: Richard Meadows <962920+richardeoin@users.noreply.github.com> Co-authored-by: Emil Fresk <emil.fresk@gmail.com> Co-authored-by: Joonas Javanainen <joonas.javanainen@gmail.com>
5 parents f289be0 + aa0b544 + ee4ccad + 0dfa922 + 48bc703 commit fa72d11

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‎CHANGELOG.md

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Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@ Family-specific:
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* H7:
2020
* h7b3: clear all enumeratedValues
21+
* h747: add flash registers mirrored in bank2
2122

2223
* F2:
2324
* Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)
@@ -26,6 +27,9 @@ Family-specific:
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* Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)
2728
* Fix OTG_FS registers
2829

30+
* L4:
31+
* Added missing channel 2 on TIM15
32+
2933
* F7:
3034
* Add SDMMC2EN and SDMMC2RST to F765, F7x7, F7x9 (#662)
3135
* Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689)

‎devices/common_patches/f7_tim.yaml

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -55,4 +55,12 @@ TIM[1-58]:
5555
# Self-inconsistency between the register map and the
5656
# specific register field documentation in RMs
5757
DMAB:
58-
bitWidth: 32
58+
bitWidth: 32
59+
60+
"TIM9,TIM1[0-4]":
61+
CNT:
62+
CNT: [0, 65535]
63+
ARR:
64+
ARR: [0, 65535]
65+
CCR%s:
66+
CCR: [0, 65535]

‎devices/common_patches/h7_dualcore_flash.yaml

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Original file line numberDiff line numberDiff line change
@@ -648,6 +648,19 @@ _add:
648648
description: Bank 1 ECC error address
649649
bitOffset: 0
650650
bitWidth: 15
651+
ACR_:
652+
description: FLASH access control register
653+
addressOffset: 0x100
654+
resetValue: 0x00000037
655+
fields:
656+
WRHIGHFREQ:
657+
description: Flash signal delay
658+
bitOffset: 4
659+
bitWidth: 2
660+
LATENCY:
661+
description: Read latency
662+
bitOffset: 0
663+
bitWidth: 4
651664
KEYR2:
652665
description: FLASH key register for bank 2
653666
addressOffset: 0x104
@@ -658,6 +671,17 @@ _add:
658671
description: Bank access configuration unlock key
659672
bitOffset: 0
660673
bitWidth: 32
674+
OPTKEYR_:
675+
description: FLASH option key register
676+
addressOffset: 0x108
677+
resetValue: 0x00000000
678+
access: write-only
679+
fields:
680+
OPTKEYR:
681+
description: FLASH option bytes control access unlock key
682+
bitOffset: 0
683+
bitWidth: 32
684+
661685
CR2:
662686
description: FLASH control register for bank 2
663687
addressOffset: 0x10C
@@ -869,6 +893,186 @@ _add:
869893
description: Bank 2 EOP2 flag clear bit
870894
bitOffset: 16
871895
bitWidth: 1
896+
OPTCR_:
897+
description: FLASH option control register
898+
addressOffset: 0x118
899+
resetValue: 0x00000001
900+
fields:
901+
SWAP_BANK:
902+
description: Bank swapping option configuration bit
903+
bitOffset: 31
904+
bitWidth: 1
905+
OPTCHANGEERRIE:
906+
description: Option byte change error interrupt enable bit
907+
bitOffset: 30
908+
bitWidth: 1
909+
MER:
910+
description: mass erase request
911+
bitOffset: 4
912+
bitWidth: 1
913+
OPTSTART:
914+
description: Option byte start change option configuration bit
915+
bitOffset: 1
916+
bitWidth: 1
917+
OPTLOCK:
918+
description: FLASH
919+
bitOffset: 0
920+
bitWidth: 1
921+
OPTSR_CUR_:
922+
description: FLASH option status register
923+
addressOffset: 0x11C
924+
resetValue: 0x00000000
925+
fields:
926+
SWAP_BANK_OPT:
927+
description: Bank swapping option status bit
928+
bitOffset: 31
929+
bitWidth: 1
930+
OPTCHANGEERR:
931+
description: Option byte change error flag
932+
bitOffset: 30
933+
bitWidth: 1
934+
IO_HSLV:
935+
description: I
936+
bitOffset: 29
937+
bitWidth: 1
938+
NRST_STBY_D2:
939+
description: D2 domain DStandby entry reset option status bit
940+
bitOffset: 25
941+
bitWidth: 1
942+
NRST_STOP_D2:
943+
description: D2 domain DStop entry reset option status bit
944+
bitOffset: 24
945+
bitWidth: 1
946+
BOOT_CM7:
947+
description: Arm Cortex
948+
bitOffset: 23
949+
bitWidth: 1
950+
BOOT_CM4:
951+
description: Arm Cortex
952+
bitOffset: 22
953+
bitWidth: 1
954+
SECURITY:
955+
description: Security enable option status bit
956+
bitOffset: 21
957+
bitWidth: 1
958+
ST_RAM_SIZE:
959+
description: ST RAM size option status
960+
bitOffset: 19
961+
bitWidth: 2
962+
IWDG_FZ_SDBY:
963+
description: IWDG Standby mode freeze option status bit
964+
bitOffset: 18
965+
bitWidth: 1
966+
IWDG_FZ_STOP:
967+
description: IWDG Stop mode freeze option status bit
968+
bitOffset: 17
969+
bitWidth: 1
970+
RDP:
971+
description: Readout protection level option status byte
972+
bitOffset: 8
973+
bitWidth: 8
974+
RST_STDY_D1:
975+
description: D1 domain DStandby entry reset option status bit
976+
bitOffset: 7
977+
bitWidth: 1
978+
NRST_STOP_D1:
979+
description: D1 domain DStop entry reset option status bit
980+
bitOffset: 6
981+
bitWidth: 1
982+
IWDG2_SW:
983+
description: IWDG2 control mode option status bit
984+
bitOffset: 5
985+
bitWidth: 1
986+
IWDG_SW:
987+
description: IWDG control mode option status bit
988+
bitOffset: 4
989+
bitWidth: 1
990+
BOR_LEV:
991+
description: Brownout level option status bit
992+
bitOffset: 2
993+
bitWidth: 2
994+
OPT_BUSY:
995+
description: Option byte change ongoing flag
996+
bitOffset: 0
997+
bitWidth: 1
998+
OPTSR_PRG_:
999+
description: FLASH option status register
1000+
addressOffset: 0x120
1001+
resetValue: 0x00000000
1002+
fields:
1003+
SWAP_BANK_OPT:
1004+
description: Bank swapping option configuration bit
1005+
bitOffset: 31
1006+
bitWidth: 1
1007+
IO_HSLV:
1008+
description: I
1009+
bitOffset: 29
1010+
bitWidth: 1
1011+
NRST_STBY_D2:
1012+
description: D2 domain DStandby entry reset option configuration bit
1013+
bitOffset: 25
1014+
bitWidth: 1
1015+
NRST_STOP_D2:
1016+
description: D2 domain DStop entry reset option configuration bit
1017+
bitOffset: 24
1018+
bitWidth: 1
1019+
BOOT_CM7:
1020+
description: Arm Cortex
1021+
bitOffset: 23
1022+
bitWidth: 1
1023+
BOOT_CM4:
1024+
description: Arm Cortex
1025+
bitOffset: 22
1026+
bitWidth: 1
1027+
SECURITY:
1028+
description: Security enable option configuration bit
1029+
bitOffset: 21
1030+
bitWidth: 1
1031+
ST_RAM_SIZE:
1032+
description: ST RAM size option configuration bits
1033+
bitOffset: 19
1034+
bitWidth: 2
1035+
IWDG_FZ_SDBY:
1036+
description: IWDG Standby mode freeze option configuration bit
1037+
bitOffset: 18
1038+
bitWidth: 1
1039+
IWDG_FZ_STOP:
1040+
description: IWDG Stop mode freeze option configuration bit
1041+
bitOffset: 17
1042+
bitWidth: 1
1043+
RDP:
1044+
description: Readout protection level option configuration bits
1045+
bitOffset: 8
1046+
bitWidth: 8
1047+
NRST_STDY_D1:
1048+
description: D1 domain DStandby entry reset option configuration bit
1049+
bitOffset: 7
1050+
bitWidth: 1
1051+
NRST_STOP_D1:
1052+
description: D1 domain DStop entry reset option configuration bit
1053+
bitOffset: 6
1054+
bitWidth: 1
1055+
IWDG2_SW:
1056+
description: IWDG2 control mode option configuration bit
1057+
bitOffset: 5
1058+
bitWidth: 1
1059+
IWDG_SW:
1060+
description: IWDG control mode option configuration bit
1061+
bitOffset: 4
1062+
bitWidth: 1
1063+
BOR_LEV:
1064+
description: Brownout level option configuration bit
1065+
bitOffset: 2
1066+
bitWidth: 2
1067+
OPTCCR_:
1068+
description: FLASH option clear control register
1069+
addressOffset: 0x124
1070+
resetValue: 0x00000000
1071+
fields:
1072+
CLR_OPTCHANGEERR:
1073+
description: OPTCHANGEERR reset bit
1074+
bitOffset: 30
1075+
bitWidth: 1
8721076
PRAR_CUR2:
8731077
description: FLASH protection address for bank 2
8741078
addressOffset: 0x128
@@ -955,6 +1159,58 @@ _add:
9551159
description: Bank 2 sector write protection option status byte
9561160
bitOffset: 0
9571161
bitWidth: 8
1162+
BOOT7_CURR_:
1163+
description: FLASH register boot address for Arm Cortex-M7 core
1164+
addressOffset: 0x140
1165+
resetValue: 0x00000000
1166+
fields:
1167+
BOOT_CM7_ADD1:
1168+
description: Arm Cortex-M7 boot address 1
1169+
bitOffset: 16
1170+
bitWidth: 16
1171+
BOOT_CM7_ADD0:
1172+
description: Arm Cortex-M7 boot address 0
1173+
bitOffset: 0
1174+
bitWidth: 16
1175+
BOOT7_PRGR_:
1176+
description: FLASH register boot address for Arm Cortex-M7 core
1177+
addressOffset: 0x144
1178+
resetValue: 0x00000000
1179+
fields:
1180+
BOOT_CM7_ADD1:
1181+
description: Arm Cortex-M7 boot address 1 configuration
1182+
bitOffset: 16
1183+
bitWidth: 16
1184+
BOOT_CM7_ADD0:
1185+
description: Arm Cortex-M7 boot address 0 configuration
1186+
bitOffset: 0
1187+
bitWidth: 16
1188+
BOOT4_CURR_:
1189+
description: FLASH register boot address for Arm Cortex-M4 core
1190+
addressOffset: 0x148
1191+
resetValue: 0x00000000
1192+
fields:
1193+
BOOT_CM4_ADD1:
1194+
description: Arm Cortex-M4 boot address 1
1195+
bitOffset: 16
1196+
bitWidth: 16
1197+
BOOT_CM4_ADD0:
1198+
description: Arm Cortex-M4 boot address 0
1199+
bitOffset: 0
1200+
bitWidth: 16
1201+
BOOT4_PRGR_:
1202+
description: FLASH register boot address for Arm Cortex-M4 core
1203+
addressOffset: 0x14C
1204+
resetValue: 0x00000000
1205+
fields:
1206+
BOOT_CM4_ADD1:
1207+
description: Arm Cortex-M4 boot address 1 configuration
1208+
bitOffset: 16
1209+
bitWidth: 16
1210+
BOOT_CM4_ADD0:
1211+
description: Arm Cortex-M4 boot address 0 configuration
1212+
bitOffset: 0
1213+
bitWidth: 16
9581214
CRCCR2:
9591215
description: FLASH CRC control register for bank 2
9601216
addressOffset: 0x150

‎devices/common_patches/l4_tim15_ch2.yaml

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@@ -0,0 +1,67 @@
1+
2+
# TIM15 channel 2 for STM32L4x
3+
"TIM15":
4+
CCER:
5+
_add:
6+
CC2E:
7+
description: Capture/Compare 2 output enable
8+
bitWidth: 1
9+
bitOffset: 4
10+
CC2P:
11+
description: Capture/Compare 2 output polarity
12+
bitWidth: 1
13+
bitOffset: 5
14+
CC2NP:
15+
description: Capture/Compare 2 complementary output polarity
16+
bitWidth: 1
17+
bitOffset: 7
18+
19+
CCMR1_Input:
20+
_add:
21+
CC2S:
22+
description: Capture/Compare 2 selection
23+
bitWidth: 2
24+
bitOffset: 8
25+
IC2PSC:
26+
description: Input capture 2 prescaler
27+
bitWidth: 2
28+
bitOffset: 10
29+
IC2F:
30+
description: Input capture 2 filter
31+
bitWidth: 4
32+
bitOffset: 12
33+
34+
CCMR1_Output:
35+
_add:
36+
CC2S:
37+
description: Capture/Compare 2 selection
38+
bitWidth: 2
39+
bitOffset: 8
40+
OC2FE:
41+
description: Output Compare 2 fast enable
42+
bitWidth: 1
43+
bitOffset: 10
44+
OC2PE:
45+
description: Capture/Compare 2 selection
46+
bitWidth: 1
47+
bitOffset: 11
48+
OC2M:
49+
description: Output Compare 2 mode
50+
bitWidth: 3
51+
bitOffset: 12
52+
OC2M_3:
53+
description: Output Compare 2 mode - bit 3
54+
bitWidth: 1
55+
bitOffset: 24
56+
57+
_add:
58+
CCR2:
59+
description: Channel 2 capture/compare register
60+
addressOffset: 0x38
61+
fields:
62+
CCR2:
63+
description: Capture/Compare 2 value
64+
access: read-write
65+
bitOffset: 0
66+
bitWidth: 16
67+

‎devices/common_patches/usb_otg/otg_fs_fixes_v1.yaml

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@@ -1,4 +1,4 @@
1-
# For F401, F411
1+
# For F215, F217, F401, F411
22

33
OTG_FS_GLOBAL:
44
GINTMSK:

‎devices/stm32f215.yaml

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@@ -93,4 +93,6 @@ _include:
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- common_patches/hash/hash_v1.yaml
9494
- common_patches/rtc/rtc_bkpr.yaml
9595
- common_patches/rtc/rtc_cr.yaml
96+
- common_patches/usb_otg/otg_fs_remove_prefix.yaml
97+
- common_patches/usb_otg/otg_fs_fixes_v1.yaml
9698
- common_patches/dbgmcu.yaml

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