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Prepare for v0.14.0 release
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‎CHANGELOG.md

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## [Unreleased]
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## [v0.14.0] 2021-10-02
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Family-specific:
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* F0:
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* Fix duplicated aliased registers WAIT/AUTDLY and DMAEN/DMA1EN (#538)
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* F3:
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* Mark HRTIM ISR FLT fields read-write (#592)
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* Fix reset value for FLASH OBR (#600)
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* F4:
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* Add FLASH and PLLR description for F446 (#533)
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* Add FLTR register to all I2C peripherals (#534)
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* Rename DSIHOST to DSI for F469 (#585)
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* Fix UART RCC enable/reset bits (#589)
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* Remove non-existant TIM8 from F401 (#633)
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* F7:
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* Strip DSI prefix from DSI registers (#585)
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* Fix reset value for RCC DCKCFGR (#600)
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* Fix all timer registers (#606)
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* Fix all SYSCFG registers (#612)
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* Fix all RCC registers (#613)
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* Fix all SDMMC registers (#620)
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* Fix CRC INIT and POL register offsets (#632)
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* L0:
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* Add L0x0 family (#505)
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* Fix TIM CNT, ARR, CCR register sizes (#581)
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* Fix RCC_CSR RMVF bit offset in L0x2 and L0x3 (#566)
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* L4:
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* Fix ADC SQR1.L name and description (#519)
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* Add missing APB1RSTR1.USBFSRST field for L4x3 (#526)
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* Fix AHB1 CRC bits for L4x3 (#517)
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* Add STM32L4R9 (#532)
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* Add SPI register descriptions (#535)
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* Strip DSI prefix from DSI registers (#585)
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* Fix RTC registers in L41x and L42x (#580)
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* Add USB_BCDR register, fix USB base address, and add USB interrupt (#580)
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* Add CRSEN to APB1ENR1 (#580)
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* Fix bit offset for CRC and USART bits in RCC (#571)
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* Fix LCD RAM_COM register size and arrayify (#552)
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* L5:
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* Fix TIM15 CCR2 address offset (#518)
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* H7:
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* Add WWDG field descriptions (#502)
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* Add DAC2AMEN to H7B3 (#500)
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* Add LTDC field descriptions (#512)
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* Fix FDCAN_TEST register to be writable (#574)
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* Update to latest ST SVDs and add H72x/H73x devices (#554)
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* Fix invalid patches to RCC registers (#615)
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* Fix and cluster DFSDM registers (#637)
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* G0:
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* Update to new ST SVD release (#514)
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* G4:
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* Add I2C register definitions (#510)
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* Add USB BCDR register (#506)
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* Add GPIO register definitions (#531)
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* Add more descriptions for RCC (#528)
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* WB:
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* Enable in nightly releases (#509)
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* Fix ADC SQR1.L name and description (#519)
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* Add missing EXTI fields (#580)
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* Fix TIM16 CR1 (#580)
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* Rename ADC to ADC1, add new ADC_Common peripheral (#623)
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* Fix SYSCFG register offsets (#624)
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* Fixes for ADC, TIM16, and TIM17 (#625)
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* Rename EXTI10_15 and EXTI5_9 interrupts to EXTI15_10 and EXTI9_5 (#634)
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* Fix TIM2.CNT bit width (#635)
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* WL:
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* Update to new ST SVD release (#507)
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* Extensive patches and descriptions for WLE5, covering many peripherals (#559)
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* Unify EXTI.IMRx for WLE5 to match dual-core parts (#590)
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* Fix EXTI14 enumerated values (#599)
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* Add register descriptions for dual-core variants (#628)
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* MP:
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* Strip DSI prefix from DSI registers (#585)
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* Add initial support for STM32MP153 device (#614)
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Common:
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* Many devices using USART "v2" had write constraints fixed to allow 9-bit
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words, affecting F0, F3, F7, H7, L0, L4, and WL families. (#558)
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* The `rt` feature is now enabled by default; use `default-features=false` to
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disable.
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disable (#582).
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* Updated to svd2rust 0.19, with changes to the generated crate API.
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This update required a number of fixes to bugs in the SVD files,
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especially including fixes to timers across all families (#540, #546, #596).
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* Fix a bug causing aliased registers to be suppressed in the HTML output
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(#591)
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* Added a register map to HTML output (#598).
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* Allow generating HTML output for selected families only (#607).
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* Cortex-m-rt version 0.7 is now supported (#595, #603).
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Contributors to this release:
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[@diondokter] [@mattico] [@noslaver] [@jglauche] [@ofauchon] [@richardeoin]
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[@Geens] [@wallacejohn] [@kevswims] [@qwandor] [@cyrusmetcalf] [@ByteNaked]
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[@cyberillithid] [@kenbell] [@tachiniererin] [@yusefkarim] [@lynaghk]
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[@sirhcel] [@timblakely] [@lulf] [@ijager] [@jorgeig-space] [@burrbull]
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[@timokroeger] [@newAM] [@maximeborges] [@David-OConnor] [@rmsc] [@jhbruhn]
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[@karlp] [@AndreasKarg]
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## [v0.13.1] 2021-06-02
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* Fix nvicPrioBits being incorrect in many STM32s (de117ef)
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* Add support for specifying interrupts and modifying CPU node
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[Unreleased]: https://github.com/stm32-rs/stm32-rs/compare/v0.13.0...HEAD
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[Unreleased]: https://github.com/stm32-rs/stm32-rs/compare/v0.14.0...HEAD
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[v0.14.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.13.0...v0.14.0
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[v0.13.1]: https://github.com/stm32-rs/stm32-rs/compare/v0.13.0...v0.13.1
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[v0.13.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.12.1...v0.13.0
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[v0.12.1]: https://github.com/stm32-rs/stm32-rs/compare/v0.12.0...v0.12.1
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[@albru123]: https://github.com/albru123
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[@almusil]: https://github.com/almusil
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[@AlyoshaVasilieva]: https://github.com/AlyoshaVasilieva
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[@AndreasKarg]: https://github.com/AndreasKarg
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[@arkorobotics]: https://github.com/arkorobotics
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[@astro]: https://github.com/astro
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[@aurabindo]: https://github.com/aurabindo
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[@aurelj]: https://github.com/aurelj
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[@birkenfeld]: https://github.com/birkenfeld
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[@BryanKadzban]: https://github.com/BryanKadzban
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[@burrbull]: https://github.com/burrbull
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[@ByteNaked]: https://github.com/ByteNaked
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[@chengsun]: https://github.com/chengsun
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[@cyberillithid]: https://github.com/cyberillithid
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[@cyrusmetcalf]: https://github.com/cyrusmetcalf
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[@David-OConnor]: https://github.com/David-OConnor
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[@diondokter]: https://github.com/diondokter
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[@dirk-dms]: https://github.com/dirk-dms
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[@disasm]: https://github.com/disasm
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[@diseraluca]: https://github.com/diseraluca
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[@dotcypress]: https://github.com/dotcypress
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[@ehntoo]: https://github.com/ehntoo
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[@eupn]: https://github.com/eupn
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[@Geens]: https://github.com/Geens
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[@HarkonenBade]: https://github.com/HarkonenBade
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[@helgrind]: https://github.com/helgrind
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[@hnez]: https://github.com/hnez
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[@hoachin]: https://github.com/hoachin
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[@ijager]: https://github.com/ijager
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[@JarLob]: https://github.com/JarLob
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[@jessebraham]: https://github.com/jessebraham
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[@jglauche]: https://github.com/jglauche
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[@jhbruhn]: https://github.com/jhbruhn
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[@jkristell]: https://github.com/jkristell
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[@jonas-schievink]: https://github.com/jonas-schievink
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[@jordens]: https://github.com/jordens
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[@jorgeig-space]: https://github.com/jorgeig-space
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[@karlp]: https://github.com/karlp
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[@kenbell]: https://github.com/kenbell
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[@kevswims]: https://github.com/kevswims
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[@kitzin]: https://github.com/kitzin
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[@korken89]: https://github.com/korken89
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[@lichtfeind]: https://github.com/lichtfeind
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[@lochsh]: https://github.com/lochsh
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[@lulf]: https://github.com/lulf
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[@lynaghk]: https://github.com/lynaghk
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[@mabezdev]: https://github.com/mabezdev
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[@MarcoIeni]: https://github.com/MarcoIeni
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[@MattCatz]: https://github.com/MattCatz
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[@mattico]: https://github.com/mattico
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[@maximeborges]: https://github.com/maximeborges
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[@newAM]: https://github.com/newAM
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[@nickray]: https://github.com/nickray
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[@noslaver]: https://github.com/noslaver
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[@octronics]: https://github.com/octronics
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[@ofauchon]: https://github.com/ofauchon
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[@osannolik]: https://github.com/osannolik
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[@Pagten]: https://github.com/Pagten
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[@pawelchcki]: https://github.com/pawelchcki
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[@Piroro-hs]: https://github.com/Piroro-hs
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[@Rahix]: https://github.com/Rahix
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[@qwandor]: https://github.com/qwandor
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[@ra-kete]: https://github.com/ra-kete
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[@Rahix]: https://github.com/Rahix
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[@rfuest]: https://github.com/rfuest
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[@richard7770]: https://github.com/richard7770
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[@richardeoin]: https://github.com/richardeoin
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[@rmsc]: https://github.com/rmsc
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[@ryan-summers]: https://github.com/ryan-summers
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[@samcrow]: https://github.com/samcrow
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[@Sh3Rm4n]: https://github.com/Sh3Rm4n
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[@sirhcel]: https://github.com/sirhcel
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[@solderjs]: https://github.com/solderjs
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[@tachiniererin]: https://github.com/tachiniererin
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[@therealprof]: https://github.com/therealprof
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[@thinxer]: https://github.com/thinxer
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[@timblakely]: https://github.com/timblakely
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[@timokroeger]: https://github.com/timokroeger
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[@torkeldanielsson]: https://github.com/torkeldanielsson
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[@TwoHandz]: https://github.com/TwoHandz
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[@wallacejohn]: https://github.com/wallacejohn

‎README.md

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In your own project's `Cargo.toml`:
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```toml
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[dependencies.stm32f4]
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version = "0.13.0"
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version = "0.14.0"
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features = ["stm32f405", "rt"]
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```
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‎scripts/makecrates.py

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import re
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import yaml
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VERSION = "0.13.0"
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VERSION = "0.14.0"
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SVD2RUST_VERSION = "0.19.0"
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CRATE_DOC_FEATURES = {

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