diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 000000000..90a56e6b8 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,3 @@ +# linux script files +*.sh text eol=lf + diff --git a/.github/bors.toml b/.github/bors.toml deleted file mode 100644 index cc5ccacc1..000000000 --- a/.github/bors.toml +++ /dev/null @@ -1,19 +0,0 @@ -required_approvals = 1 -block_labels = ["wip"] -delete_merged_branches = true -status = [ - "Check (stm32f0)", - "Check (stm32f1)", - "Check (stm32f2)", - "Check (stm32f3)", - "Check (stm32f4)", - "Check (stm32f7)", - "Check (stm32h7)", - "Check (stm32l0)", - "Check (stm32l1)", - "Check (stm32l4)", - "Check (stm32l5)", - "Check (stm32g0)", - "Check (stm32g4)", - "Check (stm32mp1)", -] diff --git a/.github/workflows/cargo-make.yaml b/.github/workflows/cargo-make.yaml new file mode 100644 index 000000000..69679ac55 --- /dev/null +++ b/.github/workflows/cargo-make.yaml @@ -0,0 +1,54 @@ +name: Cargo Make + +on: + push: + branches: + - master + pull_request: + merge_group: + +jobs: + cargo_make: + name: Cargo Make + runs-on: ubuntu-latest + + env: + CRATES: stm32f0 + CARGO_INCREMENTAL: 0 + SVDTOOLS: svdtools + + steps: + - name: Checkout code + uses: actions/checkout@v4 + + - name: Install Rust + uses: dtolnay/rust-toolchain@stable + with: + components: rustfmt + + - name: Install cargo-make + run: | + wget https://github.com/sagiegurari/cargo-make/releases/download/0.36.8/cargo-make-v0.36.8-x86_64-unknown-linux-gnu.zip + unzip cargo-make-*.zip + mv cargo-make*/cargo-make $HOME/.cargo/bin + + - name: Create working crate + run: cargo make crates + + - name: Install tools + run: cargo make install + + - name: Patch SVDs + run: cargo make patch + + - name: Build PACs + run: cargo make svd2rust + + - name: Format PACs + run: cargo make form + + - name: Check PACs + run: cargo make check-patched + + - name: Clean up + run: cargo make clean-all diff --git a/.github/workflows/changelog.yaml b/.github/workflows/changelog.yaml new file mode 100644 index 000000000..c0e3a4758 --- /dev/null +++ b/.github/workflows/changelog.yaml @@ -0,0 +1,22 @@ +on: + pull_request: + # Run on labeled/unlabeled in addition to defaults to detect + # adding/removing skip-changelog labels. + types: [ opened, reopened, labeled, unlabeled, synchronize ] + merge_group: + +name: Changelog + +jobs: + changelog: + name: Require Changelog + runs-on: ubuntu-latest + steps: + - name: Checkout sources + uses: actions/checkout@v4 + + - name: Check changelog update + uses: dangoslen/changelog-enforcer@v3 + with: + skipLabels: skip-changelog + missingUpdateErrorMessage: 'Please add a changelog entry to the appropriate section of the CHANGELOG.md file.' diff --git a/.github/workflows/ci.yaml b/.github/workflows/ci.yaml index 2a66c1c61..81985f0fd 100644 --- a/.github/workflows/ci.yaml +++ b/.github/workflows/ci.yaml @@ -2,8 +2,10 @@ name: CI on: push: - branches: [ staging, trying, master ] + branches: + - master pull_request: + merge_group: jobs: check: @@ -12,12 +14,14 @@ jobs: strategy: matrix: crate: + - stm32c0 - stm32f0 - stm32f1 - stm32f2 - stm32f3 - stm32f4 - stm32f7 + - stm32h5 - stm32h7 - stm32l0 - stm32l1 @@ -26,53 +30,47 @@ jobs: - stm32g0 - stm32g4 - stm32mp1 + - stm32n6 + - stm32u0 + - stm32u5 + - stm32wl + - stm32wb + env: CRATES: ${{ matrix.crate }} CARGO_INCREMENTAL: 0 + SVDTOOLS: svdtools + steps: - name: Checkout code - uses: actions/checkout@v2 + uses: actions/checkout@v4 + - name: Install Rust - uses: actions-rs/toolchain@v1 + uses: dtolnay/rust-toolchain@stable with: - toolchain: stable - profile: minimal - override: true components: rustfmt + - name: Install xmllint - run: sudo apt-get install libxml2-utils - - name: Install Python dependencies - run: | - pip3 install --user setuptools wheel - pip3 install --user svdtools - - name: Put pip binary directory into path - run: | - echo "::add-path::~/.local/bin" - - name: Cache Cargo installed binaries - uses: actions/cache@v1 - id: cache-cargo - with: - path: ~/cargo-bin - key: ${{ runner.os }}-svd2rust-0.17.0 - - name: Install svd2rust - if: steps.cache-cargo.outputs.cache-hit != 'true' - uses: actions-rs/install@v0.1 - with: - crate: svd2rust - version: 0.17.0 - - name: Copy svd2rust to cache directory - if: steps.cache-cargo.outputs.cache-hit != 'true' run: | - mkdir ~/cargo-bin - cp ~/.cargo/bin/svd2rust ~/cargo-bin - - name: Put new cargo binary directory into path + sudo apt-get update + sudo apt-get install libxml2-utils + + - name: Create working crate + run: make crates + + - name: Install tools run: | - echo "::add-path::~/cargo-bin" + ./scripts/tool_install.sh svdtools + ./scripts/tool_install.sh svd2rust + - name: Patch SVDs run: make -j2 patch + - name: Check SVDs run: make lint + - name: Build PACs run: make -j2 svd2rust + - name: Check PACs run: make -j2 check diff --git a/.github/workflows/gh-pages.yaml b/.github/workflows/gh-pages.yaml index 1517b6319..b21d639c7 100644 --- a/.github/workflows/gh-pages.yaml +++ b/.github/workflows/gh-pages.yaml @@ -7,25 +7,35 @@ on: jobs: build_html: name: Build HTML - runs-on: ubuntu-18.04 + runs-on: ubuntu-latest + env: + SVDTOOLS: svdtools steps: - name: Checkout master - uses: actions/checkout@v2 + uses: actions/checkout@v4 with: persist-credentials: false - - name: Install Python dependencies + - name: Install tools run: | - pip3 install --user setuptools wheel - pip3 install --user svdtools - - name: Put pip binary directory into path - run: | - echo "::add-path::~/.local/bin" + ./scripts/tool_install.sh svdtools - name: Build HTML - run: | - make -j2 html - - name: Publish to GitHub Pages - uses: peaceiris/actions-gh-pages@v3 + run: make -j2 html + - name: Upload artifact + uses: actions/upload-pages-artifact@v3 with: - github_token: ${{ secrets.GITHUB_TOKEN }} - publish_dir: html - force_orphan: true + path: html + + deploy_pages: + name: Deploy GH Pages + runs-on: ubuntu-latest + needs: build_html + permissions: + pages: write + id-token: write + environment: + name: github-pages + url: ${{ steps.deployment.outputs.page_url }} + steps: + - name: Deploy to Github Pages + id: deployment + uses: actions/deploy-pages@v4 diff --git a/.github/workflows/mmaps_master.yaml b/.github/workflows/mmaps_master.yaml new file mode 100644 index 000000000..864c6cf79 --- /dev/null +++ b/.github/workflows/mmaps_master.yaml @@ -0,0 +1,48 @@ +name: build mmaps + +on: + push: + branches: + - master + +jobs: + build: + name: Build mmaps + runs-on: ubuntu-latest + + env: + SVDTOOLS: svdtools + + steps: + - name: Checkout stm32-rs + uses: actions/checkout@v4 + with: + path: stm32-rs + + - name: Checkout mmaps + uses: actions/checkout@v4 + with: + repository: stm32-rs/stm32-rs-mmaps + ssh-key: ${{ secrets.MMAPS_KEY }} + path: stm32-rs-mmaps + + - name: Add fictive crate + run: | + cargo init + + - name: Install tools + run: | + ./stm32-rs/scripts/tool_install.sh svdtools + + - name: Build and publish + run: | + cd stm32-rs + COMMIT=$(git rev-parse HEAD) + make -j2 mmaps + mv mmaps/* ../stm32-rs-mmaps/ + cd ../stm32-rs-mmaps + git config user.name "stm32-rs builder" + git config user.email "action@github.com" + git add . + git commit --allow-empty -m "stm32-rs master $COMMIT" + git push origin master diff --git a/.github/workflows/mmaps_pr_compare.yaml b/.github/workflows/mmaps_pr_compare.yaml new file mode 100644 index 000000000..8be9d1949 --- /dev/null +++ b/.github/workflows/mmaps_pr_compare.yaml @@ -0,0 +1,48 @@ +name: Compare PR mmaps + +on: + workflow_run: + workflows: [Generate PR mmaps] + types: [completed] + +jobs: + compare: + if: ${{ github.event.workflow_run.conclusion == 'success' }} + permissions: + pull-requests: write # add PR comment + runs-on: ubuntu-latest + steps: + - name: Checkout mmaps + uses: actions/checkout@v4 + with: + repository: stm32-rs/stm32-rs-mmaps + ssh-key: ${{ secrets.MMAPS_KEY }} + + - name: Download new mmaps + uses: dawidd6/action-download-artifact@v8 + with: + name: mmaps + run_id: ${{ github.event.workflow_run.id }} + + - name: Commit new mmaps + run: | + PR=${{ github.event.workflow_run.pull_requests[0].number }} + COMMIT=${{ github.event.workflow_run.pull_requests[0].head.sha }} + BRANCH=pr-$PR-$COMMIT + echo "BRANCH=$BRANCH" >> $GITHUB_ENV + + git checkout -b $BRANCH + git add . + git config user.name "stm32-rs builder" + git config user.email "action@github.com" + git commit --allow-empty -m "stm32-rs PR #$PR $COMMIT" + git push -f origin $BRANCH + + - name: Comment + uses: mshick/add-pr-comment@v2 + with: + message: | + [Memory map comparison](https://github.com/stm32-rs/stm32-rs-mmaps/compare/${{ env.BRANCH }}) + repo-token: ${{ secrets.GITHUB_TOKEN }} + repo-token-user-login: "github-actions[bot]" + issue: ${{ github.event.workflow_run.pull_requests[0].number }} diff --git a/.github/workflows/mmaps_pr_generate.yaml b/.github/workflows/mmaps_pr_generate.yaml new file mode 100644 index 000000000..c88bf9ace --- /dev/null +++ b/.github/workflows/mmaps_pr_generate.yaml @@ -0,0 +1,34 @@ +name: Generate PR mmaps + +on: + pull_request: + branches: + - master + paths: + - 'svd/**' + - 'devices/**' + - 'cortex_m/**' + - 'Makefile' + - 'Makefile.toml' + - 'scripts/tool_install.sh' + +jobs: + generate: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + + - name: Install svdtools + run: ./scripts/tool_install.sh svdtools + + - name: Generate mmaps + run: make -j2 mmaps + + - uses: actions/upload-artifact@v4 + with: + name: mmaps + path: mmaps/ + if-no-files-found: error + retention-days: 7 + + # commit and push to stm32-rs-mmaps is handled in mmaps_pr_compare.yaml diff --git a/.github/workflows/nightlies.yaml b/.github/workflows/nightlies.yaml index 74455ddda..5d9352a0f 100644 --- a/.github/workflows/nightlies.yaml +++ b/.github/workflows/nightlies.yaml @@ -1,4 +1,5 @@ name: build nightlies + on: push: branches: @@ -7,52 +8,29 @@ on: jobs: build: name: Build - runs-on: ubuntu-18.04 + runs-on: ubuntu-latest + + env: + SVDTOOLS: svdtools + steps: - name: Checkout master - uses: actions/checkout@v2 + uses: actions/checkout@v4 with: path: stm32-rs - - name: Install Python dependencies - run: | - pip3 install --user setuptools wheel - pip3 install --user svdtools - - name: Put pip binary directory into path - run: | - echo "::add-path::~/.local/bin" + - name: Install Rust - uses: actions-rs/toolchain@v1 + uses: dtolnay/rust-toolchain@stable with: - toolchain: stable - profile: minimal components: rustfmt - override: true - - name: Cache Cargo installed binaries - uses: actions/cache@v1 - id: cache-cargo - with: - path: ~/cargo-bin - key: ${{ runner.os }}-cargo-binaries-0.17.0 - - name: Install svd2rust - if: steps.cache-cargo.outputs.cache-hit != 'true' - uses: actions-rs/cargo@v1 - with: - command: install - args: svd2rust --version 0.17.0 - - name: Install form - if: steps.cache-cargo.outputs.cache-hit != 'true' - uses: actions-rs/cargo@v1 - with: - command: install - args: form --version 0.7.0 - - name: Copy svd2rust and form to cache directory - if: steps.cache-cargo.outputs.cache-hit != 'true' - run: | - mkdir ~/cargo-bin - cp ~/.cargo/bin/{svd2rust,form} ~/cargo-bin - - name: Put cargo binary directory into path + + - name: Add fictive crate run: | - echo "::add-path::~/cargo-bin" + cargo init + + - name: Install tools + run: ./stm32-rs/scripts/tool_install.sh + - name: Deploy SSH key run: | mkdir ~/.ssh @@ -66,7 +44,7 @@ jobs: cd stm32-rs COMMIT=$(git rev-parse HEAD) make -j2 form - mv stm32{f,g,h,l,mp}* ../nightly + mv stm32{c,f,g,h,l,mp,n,u,wl,wb}* ../nightly cp .github/workflows/README-nightlies.md ../nightly/README.md cd ../nightly git init diff --git a/.gitignore b/.gitignore index 48efc63f6..1f22d04ae 100644 --- a/.gitignore +++ b/.gitignore @@ -6,7 +6,12 @@ */src/stm32*/ */src/generic.rs html/ +mmaps/ +settings/ +svdconv/ /venv +.devcontainer # automatically generated crates /stm32*/ +.zed diff --git a/.prettierrc.toml b/.prettierrc.toml new file mode 100644 index 000000000..186dc9bc4 --- /dev/null +++ b/.prettierrc.toml @@ -0,0 +1,4 @@ +tabWidth = 2 +quoteProps = "as-needed" +files = "devices/**/*.yaml" +printWidth = 120 diff --git a/CHANGELOG.md b/CHANGELOG.md index f722c97cc..5d99e52a2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,593 @@ ## [Unreleased] +## [v0.16.0] 2025-05-13 + +* Updated to `svd2rust` 0.36.1, `svdtools` 0.4.6, `form` 0.13.0, use tools binaries for CI (#1174) +* bump `defmt` dependency to 1.0 (#1209) +* Use `svd2rust.toml` config, use custom ident suffixes (#948) +* Replace `makehtml.py` with `svdtools html` (#881) +* Remove workaround for bug in duckscript's `mv` (#981) +* move `_array` and `_cluster` patches to `devices/collect` (#980) +* rename `devices/common_patches` to just `devices/patches` (#1066) +* move field related patches from `peripherals` to `devices/fields` (#1067) +* Normalized docs. Split (for `cargo make`) `form` task on `form` and `fmt` (#949) +* Show available device features if no one selected (#998) +* Add `download.sh` for fast source archives update (#1134) +* Add Open-CMSIS `svdconv` to for more checks (#908) +* Add `cargo make` `yamls` task for easy compare (#1050) +* Add `derivePathType` to CMSIS-SVD schema (#1025) +* Add possibility to publish crates with different versions (#1145) +* Enable atomic operations on register support, Rust edition 2021 (#846) +* files in devices/patches moved to subdirectories (#1066) +* remove executable file perm bit from yaml file (#854) +* TIM1/8 DMAR fix (#1172) +* HPDMA derive registers between CH and CH2D clusters (#1164) +* USART: refactor and add missing enums (#1156) +* Refactor timers, add enums (#1133) +* TIM: fix TS/SMS field names (#1186) +* Add placeholders for all peripherals (#1163) +* Fix DMA & collect (#1167) +* Format yamls: remove unneeded quotes (#1099) +* Apply existing RTC patches for new families, RTC alarm arrays (#1120) +* Manual enum names for EXRI & GPIO (#964) +* AES enums & patches (#1058) +* HPDMA: clusters (#1140) +* Derive GPIO registers (#1144) +* Fix yaml parsing errors (#1002) +* Collent in field arrays: ADC, GPIO, CAN, DSI, EXTI, SAI, DMA, TIM (#1097 +* ADC: C0+G0+WL field arrays (#1051) +* Derive SYSCFG EXTI fields (#1108) +* modify `LP_Timer1` interrupt instead of adding new (#902) +* rename `KEY` field variants of `IWDG_KR` (#866) +* DMAMUX: merge registers in arrays (#873) +* move merge CAN FB fields in patch file (#904) +* G4, L5, U5 TIM common fixes (#912) +* Fix several array descriptions (#916) +* Fix ADC SQR ranges (#1102) +* Fix missing ADC.SMPR.SMPx_x (#1000) +* Fix EXTI_IMR_IM9 field, H7 DMAMUX cluster names (#891) +* Fix ADC SR OVR enums (#882) +* Fix ADC modifiedWriteValues (#1062) +* Add ADC enums for L4, L5, G0, H5, WB (#1062) +* Fix ETH_MACFFR bitOffsets (#903) +* Fix adding OTG_FS GCCFG NOVBUSSENS (#909) +* GFXMMU LUT cluster (#906) +* Fix writeConstraint bugs (#911) +* DMA ISR fixes for G0, G4 (#910) +* tools_install: support `$CARGO_HOME` environment variable (#953) +* Split `mmaps_pr` workflow on `mmaps_pr_generate` and `mmaps_pr_compare` (#949) +* TIM: rename & clean files (#800) +* Add GPIOx:HSLVR (#956) +* Fix incorrectly used `_read`, `_modify` (#968) +* `isDefault` for some RCC enums (#929) +* Doc `QUADSPI` peripheral (#875) + `DR` register can be access by 1 byte, half word and full word. Use `.dr8()`, `.dr16()`, `.dr()` to access this register. +* 16-bit registers: IWDG, WWDG, U*ART (#1177) +* 16-bit SPI registers, add DR8 (#993) (fixed) +* 16-bit I2C registers (#995) +* U5/H5: collect GTZC registers in arrays (#1056) +* G0X1, G4, H5, H7R/S, L5, U5: Add UCPD peripheral (#1001) +* C0,G0,H5,U0: merge USB CHEP[0-7]R registers into array (#1036) +* C0,G0,H5: fix field names in cmmr1_output registers (#1038) +* LCD: fix and unify RAM registers (#1083) +* H5, U5: Add cluster definitions for GPDMA channels (#1121) +* F2, F4, F7: Add definitions for OPTCR, OPTCR1 and OPTCR2 registers of FLASH peripheral (#1157) +* F2, F4, F7: Fix several fields of FLASH peripheral and reorganise 'patches', 'fields' and 'collect' according to impacted registers (#1161) +* F1, F2, F4: Derive identical UART registers from USART1, add GPTR.PSC (#1179) +* CCMR3_Output fix (#1184) +* CRC enums and fixes (#1206) +* Add DAC enums (#1196) +* DCMI enums (#1205) +* DFSDM enums and fixes (#1218) +* RNG enums (#1220) +* SDIO/SDMMC v1 (#1204) +* OCTOSPI, TAMP, LTDC enums (#1226) +* TSC enums and arrays (#1221) +* USB v2 (#1202) +* Use arrays for DAC channels (#1197) +* Derive TIM registers (#1184) +* Update README.md (#1152) +* Add SPI enums for G4, U5, H7+ (#1199) +* FMC/FSMC enums, arrays & derives (#1200) +* CRS enums (#1208) +* PSSI enums (#1234) +* HRTIM: + * H7 & G4 fixes and enums (#1021) (#1022) + * Remove timer block suffixes from register/field names (#1023) + * Derive identical registers (#1025) + * Specify TIM events for each block (#1030) +* LPTIM v1/2 + +Family-specific: + +* C0: + * Initial support (#765) + +* F1: + * F103: USB RESP1 fix name (#927) + * Remove CAN from F101/102 (#935) + * Remove CAN2 from F103, rename CAN1 to CAN (#941) + * Derive ADC registers/fields (#1194) + +* F3: + * Update vendor SVD bundle to v1.3 (#1059) + * F373 GPIOC LCKR, collect GPIO.BRR (#943) + +* F4: + * Update vendor SVD bundle to v2.0 (#1060) + * doc on `SYSCFG` peripheral for STM32F4 (#852) + * `PWR` peripherals for STM32F4 (#857) + * doc on `RNG` peripheral for STM32F4 (#870) + * Fix DAC for stm32f4 (#921) + * F4: collect SDIO RESP (#932) + +* F7: + * Update vendor SVD bundle to v2.4 (#1085) + * Fix DSI WPCR indices (#1239) + +* G0: + * Update vendor SVD bundle from v1.1 to v1.6 (#947) (#1012) (#1049) + * remove Cortex-M0+ core peripherals (use `cortex-m` crate instead) + * add enums for `RCC` & `SYSCFG` + * `DMA?:IFCR` changed from read-only (wrong) to write-only + * split `ADC:CHSELR1:CHSEL` into separate 1-bit fields + * correct multiple fields in + `EXTI`, `FLASH`, `PWR`, `RCC`, `TAMP`, and `SYSCFG` + * Fix TIM1 CCMR?_Input fields (#912) + * Fix typo in HSIDIV (Div3 -> Div4) (#1015) + * G0B1: make TIM4 16-bit timer (#1035) + * G0B1: force ARR field width to 16 bit when SVD describes ARR as 32-bit field for 16-bit timer (#1038) + * G0: describe USB CHEP?R register (#1039) + * Mark interrupt flags in USB ISTR as W0C (#1088) + * Mark flags in USB CHEPR as W0C/W1T (#1088) + * Add value enums for EXTICR[2-4] (#1088) + * G030/G031/G041: + * rename `DMA` to `DMA1` + * remove `DMA_Channel4_5_6_7` interrupt from `DMAMUX` + (replaced by `DMA1_Channel_4_5_DMAMUX` in `DMA1`) + * move `PVD` interrupt from `EXTI` to `PWR` + * move `ITLINE*` registers from `SYSCFG_ITLINE` to `SYSCFG` + * G050/G051/G061: + * add missing peripherals `AES` (G061), `COMP`, `DBG`, `DMA1`, `EXTI`, + `FLASH`, `GPIO?`, `LPUART1` (G0x1), `PWR`, `RCC`, `RNG` (G061), + `RTC`, `SPI?`, `SYSCFG`, and `TAMP` + * `USART?:CR1`: change `RXFNEIE` to `RXNEIE` and `TXFNEIE` to `TXEIE` + * remove `DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5` interrupt + from `DMAMUX` (replaced by `DMA1_Channel_4_5_6_7_DMAMUX` in `DMA1`) + * remove register prefix from `LPTIM[12]` (G0x1) + * G070/G071/G081: + * remove non-existent registers `HWCFG*`, `VERR`, `IPIDR`, and `SIDR` + from `ADC`, `RTC`, and `TAMP` + * rename `DMA` to `DMA1` + * remove `DMA_Channel4_5_6_7` interrupt from `DMAMUX` + (replaced by `DMA1_Channel_4_5_6_7_DMAMUX` in `DMA1`) + * split `SYSCFG_VREFBUF` peripheral into `SYSCFG` and `VREFBUF` (G0x1) + * G0B0: + * add missing peripherals `ADC`, `EXTI`, `FLASH`, `I2C3`, + `PWR`, `RCC`, `RTC`, `SPI?`, `SYSCFG`, `TAMP`, `TIM4`, `USB` + * `USART?`: many changes to `CR1` and `ISR` + * remove `DMA_Channel4_5_6_7` interrupt from `DMAMUX` (replaced by + `DMA1_Channel_4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5` in `DMA1`) + * rename `I2C2` interrupt to `I2C2_I2C3` + * rename `TIM3` interrupt to `TIM3_TIM4` + * G0B1/G0C1: + * add missing peripheral `SYSCFG` + * fix `SPI` register sizes + * remove `TIM6_DAC` interrupt + * `USART?`: many changes to `CR1` and `ISR` + * add `DMA?` interrupts + * TIM3's CCRx is 16-bit (#1119) + +* G4: + * Update vendor SVD bundle to v2.2 (#1087) + * Fix inconsistencies for HRTIM_TIMF - stm32g4x4 (#860) + * Add dual bank flash related fields to g4 cat 3 devices (#880) + * STM32G491: Add FDCAN2 peripheral (#915) + * Fix typo in STM32G491 FDCAN2 patch (#917) + * Fix swapped reset values for SPI4 CR1 and CR2 by deriving SPI4 from SPI1 (#957) + * Merge USART BRR fields (#959) + * Add USART v2C peripheral (#960) + * Add DAC peripheral (#961) + * COMP fix and collect array (#969) + * Fix FDCAN interrupt numbers being swapped (#996) + * G4A1: Add FDCAN2 and rename USB peripheral (#1003) + * G4A1: Add BCDR and adjust to be closer to G491 (#1004) + * G491 and G4A1: Add TIM20 (#1004) + * G471: Add OPAMP6 (#1005) + +* H5: + * Update vendor SVD bundle to v1.7 (#1086) (#1124) + * Add CRS, WWDG, IWDG, I2C, SBS, PWR, GPIO, EXTI, GPDMA, SPI, UART, RCC, TIM1-8 definitions (#956) + * Add H523 (#1124) + * STM32H503: Add missing RNG_NSCR register (#1148) + * STM32H5xx: Add H533 (#1129) + * Array gpio registers (#1053) + * Add RCC defitions for H56x/H573 (#1033) + +* H7: + * Update vendor SVD bundle to v1.9 (#1092) + * H72x/3x: add ADC3 fields + * H735: add I2C5 (#864) + * Update RNG for stm32h735 (#925) + * Add bit TRBUFF of DMA_SxCR of H747 cm4 (#958) + * Add stm32h7r/s devices (#972) + * Fix GPIO register reset values (#973) + * HRTIM H7 fix EECR3 (#1042) + * HRTIM H7: delete DLL (#1044) + * Add H723/25/30/33/42/50/55/A3/B0 (#1107) + * RAMECC fixes & collect + * RCC - Unify usbotg field naming and remove invalid fields (#1219) + * Flash - Make dual core devices naming consistent with single core devices (#1222) + +* L0: + * Update vendor SVD bundle to v1.4 (#1081) + * Fix RCC CIER register access (#1238) + +* L1: + * Update vendor SVD bundle to v1.4 (#1080) + * L1 TIM9: add CCER (#905) + * Fix ADC SMPR fieldFs in L1 (#1085) + +* L4: + * Update L4/L4+ vendor SVD bundles to v1.4 (#1084) + * Add missing CAN registers to l4x3/x5 (#914) + * Fix L412 RTC interrupts (#1236) (#1240) + * L4+ unify patches (#1233) + +* L5: + * Fix DMA cluster (#922) + +* MP1: + * Fix DIGBYP bit access in RCC_BDCR (#1011) + * Strip prefixes from peripherals (#1014) + +* N6: + * Initial support (#1211) + +* U0: + * Initial support (#1057) + +* U5: + * Update vendor SVD bundle to 1.3 (#844) (#890) + * Add U535,45,95,A5,99,A9 (#844) + * Strip prefixes from peripheral registers (#983) + * Add ADC, DMA2D, EXTI, FMC, GPIO, I2C, OCTOSPI, PWR, RCC peripherals (#986) + * MDF cluster (#1055) + +* WB: + * Update vendor SVD bundle to v1.2 (#1093) + * Add `RCC`, `SYSCFG` enums (#777) + +* WL: + * Update vendor SVD bundle to v1.2 (#1093) + +Contributors to this release: + +[@adamgreig] [@astapleton] [@burrbull] [@David-OConnor] [@dotcypress] +[@datdenkikniet] [@Elemecca] [@eZioPan] [@FerdinandvHagen] [@FrigoreD] [@hydra] +[@ianic] [@iostat] [@jonathanherbst] [@jspngh] [@kevswims] [@liamkinne] +[@mattthebaker] [@newAM] [@noppej] [@rblaze] [@reitermarkus] [@richardeoin] +[@RootCubed] [@sorki] [@tdaede] [@Urhengulas] [@usbalbin] [@vinchatl] +[@YruamaLairba] + +## [v0.15.1] 2022-07-04 + +* Updated to svd2rust 0.24.1 to fix critical codegen issue (#751) +* Fix FSDEF field being marked read-only in SAI (#752) + +## [v0.15.0] 2022-07-04 + +This release has been yanked from crates.io as it was generated using svd2rust +0.24.0 which suffered from a codegen bug (see #748). + +Common changes: + +* Strip prefixes from many peripheral registers (#661) +* Add `SVDTOOLS` env value for specifying patching tool (#673) +* Fix HTML generation on macOS (#679) +* Replace Python svd tools with Rust alternatives (#701) +* Added missing TIMx:CR1:OPM, removed unused CNT_H, ARR_H, CCR_H (#684) +* Use PascalCase for generated values of enums (#727) +* Updated to svd2rust 0.24.0 (#733) +* Document RTC ALARM and BKPR (#724) +* Extensive internal refactor of GPIO patches (#717) +* Change groupName of ADC_Common to ADC_Common (#719) +* Fix field access on many SAI fields (#691) + +Family-specific: + +* G0: + * G0B1/G0C1: Update SVDs (#666) + * G0B1/G0C1: Fix previous incorrect deletion of DMA1/2 (#675) + * Clear all vendor provided enumeratedValues (#686) + * Update SVDs, document DMA, various other patches (#687) + * Make FLASH_WRP??R and FLASH_SECR writeable (#690) + * G070: Rename SYSCFG_VREFBUF to SYSCFG, remove VREFBUF registers (#716) + * Fix DMA and TIM15 register field names (#695) + +* G4: + * Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699) + * Remove RNGSMEN -> RNGEN renaming to have AHB2SMENR.RNGSMEN (#729) + +* H7: + * h747: add midding DSI interrupt (#646) + * h735, h7b3: remove unavailable DSI peripheral (#648) + * Make ETH_MAC MMC mask register writable (#658) + * RM0455: Fix incorrect rename of OCTOSPI peripheral (#653) + * Arrayify HASH registers (#663) + * Add bit ranges to HDMI CRC registers (#671) + * H743/H753: Fix Overdrive and BDMADR fields (#649) + * h7b3: clear all enumeratedValues (#686) + * Change DMA CR to only cover SxCR, not LIFCR and HIFCR (#702) + * H735: Add TIM23 and TIM24 (#712) + * Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699) + * Arrayify HSEM registers (#735, #737) + * h747: add flash registers mirrored in bank2 (#704) + * H735: Add CORDIC and FMAC peripherals (#677) + * H735: Add missing TIM1, DCMI, OTG USB, RNG, LTDC, RAMECC interrupts (#677) + * Rename DBGSTBD1, DBGSTPD1, DBGSLPD1 fields to match RM (#677) + * RM0468: Add UART9/USART10, RM0455: fix USART base addresses (#652) + +* F0: + * F0x1/2/8: Add bit ranges to HDMI CRC registers (#671) + * Add missing CRC POL register (#710) + +* F2: + * Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689) + * Add ADC EXTSEL enumerations (#707) + * Apply existing OTG_FSv1 fixes (#706) + +* F3: + * Add missing 'P' to JADST (#696) + * Fix ADC ADSTP, ADSTART, ADDIS, ADEN bit enumerations (#699) + * Fix various fields access (#734) + * F302: Rename `DAC` to `DAC1` (#742) + +* F4: + * F469: Fix `DSIHSOT_CCR` register name (#664) + * Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689) + * F411: Fix OTG_FS registers (#697) + * Add ADC EXTSEL enumerations (#707) + * Add GTPR register to UART (#713) + * Document TIM2 ITR1_RMP enums (#678) + * F410/411/412: add BDCR LSEMOD field (#708) + +* F7: + * Add SDMMC2EN and SDMMC2RST to F765, F7x7, F7x9 (#662) + * Fix incorrect bit position for Ethernet MMCTIMR TGFM (#689) + * Add bit ranges to HDMI CRC registers (#671) + * Add ADC EXTSEL enumerations (#707) + * Fix ADC DR RDATA name and description (#723) + * Document safe ranges for CNT/ARR/CCR (#700) + * Arrayify JPEG memory registers (#725) + +* L0: + * Re-add TIM21/TIM22 (#659) + * Fix various fields access (#734) + +* L4: + * Add documentation for FIREWALL (#660) + * Arrayify HASH registers (#663) + * L4R9: Fix `DSIHSOT` interrupt name (#664) + * L4R9: Add TIM3 and TIM4 (#669) + * L4x5/6/R9: Rename DBGMCU APB_FZR to remove underscores (#681) + * Add GPIOx ASCR and BRR registers (#680) + * Added missing channel 2 on TIM15 (#705) + * Fix ADC RDATA field name and description. (#723) + * Add more enums for clock selection registers (#720) + * Rename `Polynomialcoefficients` field to `POL` (#710) + * Remove COMP1/COMP2 prefix from field names, document fields (#682) + * Add L4R5 device (#740) + +* L5: + * Fix DMA CCR fields, arrayify GTZC VCTR (#715) + +* WB: + * Arrayify HSEM registers (#735, #737) + +* WL: + * Put all timers into common TIM group (#657) + * Fix various fields access (#734) + * Arrayify HSEM registers (#735, #737) + +Contributors to this release: + +[@LeonSkoog] [@kenbell] [@ryan-summers] [@burrbull] [@richardeoin] +[@systec-ms] [@DerFetzer] [@newAM] [@jspngh] [@jamwaffles] [@sephamorr] +[@MathiasKoch] [@omion] [@davidlattimore] [@Sh3Rm4n] [@Windfisch] [@sorki] +[@taylorh140] [@reitermarkus] [@larchuto] [@jonas-schievink] [@tim-seoss] +[@Wassasin] [@Gekkio] [@korken89] [@maximeborges] [@sphw] [@dgoodland] +[@X-yl] [@disasm] [@Pagten] [@oldsheep68] [@TomDeRybel] [@mattcarp12] + +## [v0.14.0] 2021-10-02 + +Family-specific: + +* F0: + * Fix duplicated aliased registers WAIT/AUTDLY and DMAEN/DMA1EN (#538) +* F3: + * Mark HRTIM ISR FLT fields read-write (#592) + * Fix reset value for FLASH OBR (#600) +* F4: + * Add FLASH and PLLR description for F446 (#533) + * Add FLTR register to all I2C peripherals (#534) + * Rename DSIHOST to DSI for F469 (#585) + * Fix UART RCC enable/reset bits (#589) + * Remove non-existant TIM8 from F401 (#633) +* F7: + * Strip DSI prefix from DSI registers (#585) + * Fix reset value for RCC DCKCFGR (#600) + * Fix all timer registers (#606) + * Fix all SYSCFG registers (#612) + * Fix all RCC registers (#613) + * Fix all SDMMC registers (#620) + * Fix CRC INIT and POL register offsets (#632) +* L0: + * Add L0x0 family (#505) + * Fix TIM CNT, ARR, CCR register sizes (#581) + * Fix RCC_CSR RMVF bit offset in L0x2 and L0x3 (#566) +* L4: + * Fix ADC SQR1.L name and description (#519) + * Add missing APB1RSTR1.USBFSRST field for L4x3 (#526) + * Fix AHB1 CRC bits for L4x3 (#517) + * Add STM32L4R9 (#532) + * Add SPI register descriptions (#535) + * Strip DSI prefix from DSI registers (#585) + * Fix RTC registers in L41x and L42x (#580) + * Add USB_BCDR register, fix USB base address, and add USB interrupt (#580) + * Add CRSEN to APB1ENR1 (#580) + * Fix bit offset for CRC and USART bits in RCC (#571) + * Fix LCD RAM_COM register size and arrayify (#552) + * Copy L4x2-6 timers from L4x1 +* L5: + * Fix TIM15 CCR2 address offset (#518) +* H7: + * Add WWDG field descriptions (#502) + * Add DAC2AMEN to H7B3 (#500) + * Add LTDC field descriptions (#512) + * Fix FDCAN_TEST register to be writable (#574) + * Update to latest ST SVDs and add H72x/H73x devices (#554) + * Fix invalid patches to RCC registers (#615) + * Fix and cluster DFSDM registers (#637) + * Add SAI CR1 NOMCK alias bit to H743/753 and remove MCKEN (#640) +* G0: + * Update to new ST SVD release (#514) +* G4: + * Add I2C register definitions (#510) + * Add USB BCDR register (#506) + * Add GPIO register definitions (#531) + * Add more descriptions for RCC (#528) +* WB: + * Enable in nightly releases (#509) + * Fix ADC SQR1.L name and description (#519) + * Add missing EXTI fields (#580) + * Fix TIM16 CR1 (#580) + * Rename ADC to ADC1, add new ADC_Common peripheral (#623) + * Fix SYSCFG register offsets (#624) + * Fixes for ADC, TIM16, and TIM17 (#625) + * Rename EXTI10_15 and EXTI5_9 interrupts to EXTI15_10 and EXTI9_5 (#634) + * Fix TIM2.CNT bit width (#635) +* WL: + * Update to new ST SVD release (#507) + * Extensive patches and descriptions for WLE5, covering many peripherals (#559) + * Unify EXTI.IMRx for WLE5 to match dual-core parts (#590) + * Fix EXTI14 enumerated values (#599) + * Add register descriptions for dual-core variants (#628) +* MP: + * Strip DSI prefix from DSI registers (#585) + * Add initial support for STM32MP153 device (#614) + +Common: + +* Many devices using USART "v2" had write constraints fixed to allow 9-bit + words, affecting F0, F3, F7, H7, L0, L4, and WL families. (#558) +* The `rt` feature is now enabled by default; use `default-features=false` to + disable (#582). +* Updated to svd2rust 0.19, with changes to the generated crate API. + This update required a number of fixes to bugs in the SVD files, + especially including fixes to timers across all families (#540, #546, #596). +* Fix a bug causing aliased registers to be suppressed in the HTML output + (#591) +* Added a register map to HTML output (#598). +* Allow generating HTML output for selected families only (#607). +* Cortex-m-rt version 0.7 is now supported (#595, #603). + +Contributors to this release: + +[@diondokter] [@mattico] [@noslaver] [@jglauche] [@ofauchon] [@richardeoin] +[@Geens] [@wallacejohn] [@kevswims] [@qwandor] [@cyrusmetcalf] [@ByteNaked] +[@cyberillithid] [@kenbell] [@tachiniererin] [@yusefkarim] [@lynaghk] +[@sirhcel] [@timblakely] [@lulf] [@ijager] [@jorgeig-space] [@burrbull] +[@timokroeger] [@newAM] [@maximeborges] [@David-OConnor] [@rmsc] [@jhbruhn] +[@karlp] [@AndreasKarg] + +## [v0.13.1] 2021-06-02 + +This version has only been released as a patch release for the +stm32f3 family. + +* F3: + * Backport #558 to allow use in Discovery book + +## [v0.13.0] 2021-02-06 + +Family-specific: + +* F3: + * Fix GPIO OSPEEDR variants (#466) + * Remove F3x8 device, which is now supported by F303 device (#495) + * Rename DAC to DAC1 and add DAC2 to F303 (#497) + * Correct EXTI IMR2/EMR2/RTSR2/FTSR2/SWIER2 addresses (#496) +* F4: + * Fix ADC SMPR registers (#460) + * Fix and document LTDC peripheral (#448) + * Add OTG_FS interrupt to F413 (#470) + * Add DSIHOST interrupt to F469 (#498) +* F7: + * Add missing CRC fields (#447) + * Fix and document LTDC peripheral (#448) + * Add STM32F750 device (#464) +* L4: + * Add ADC common register (#463) + * Rename ADC to ADC1, add ADC2 (#465) + * Add missing SMPR fields to ADC (#484) + * Fix ADC CCR CH17SEL/CH18SEL field names (#491) +* L5: + * Fix L552 TIMx interrupts (#468) + * Add missing CPU blocks to SVD file (#476) + * Add GPIO enum variants (#479) + * Add RCC enum variants (#472) + * Add basic FDCAN support (#478) +* G0: + * Update which devices are built on docs.rs (#442) +* G4: + * Fix incorrect IWDG/WWDG addresses (#475) + * Fix SP3EN field name to SPI3EN (#481) + * Add basic FDCAN support (#478) + * Add CORDIC descriptions (#485) + * Update to newest SVD files, adding G491 and G4A1 devices (#492) + * Document OPAMP registers (#486) +* H7: + * Array RTC_BCKP registers (#445) + * Document RTC registers (#446) + * Enable broken DMAMUX patch for H7B3 (#453) + * Add/fix interrupts for H7B3 (#449) + * Add cluster for MDMA registers (#454) + * Fix CRC INIT and POL register addresses (#458) + * Add basic FDCAN support (#478) + * H7B3: Add DAC2 fields, remove LPTIM4/5 fields from RCC (#499) +* WL: + * Family added with STM32WLE5 chpi (#444) +* WB: + * Family added with STM32WB55 chip (#467) +* MP1: + * Add missing CPU blocks to SVD file (#476) + * Add basic FDCAN support (#478) + +Common: + +* Fixed a security issue in CI scripts (b7f023c), + GHSL-2020-278 (thanks to [@JarLob]). +* CRC IDR set as 8 or 32 bit as appropriate across many families (#461) +* Fix description for RCC SWS field in many devices (#482) +* Fix misspelled MCJDIV to MCKDIV field in SAI CR1 register across many + devices in f4, f7, f4, l4, l5, and wb55 families (#490) +* Fix misspelled WCKSEL to WUCKSEL field in RTC CR register across many + devices in f2, g4, l1, l4, and wb55 (#494) + +Thanks to: + +[@ijager] [@mattico] [@chengsun] [@richardeoin] [@maximeborges] +[@AlyoshaVasilieva] [@YruamaLairba] [@korken89] [@Piroro-hs] [@eupn] +[@kenbell] [@matoushybl] [@diseraluca] [@TwoHandz] [@pawelchcki] +[@wallacejohn] + +## [v0.12.1] 2020-09-22 + +* Fixes a bug introduced by a new version of svdtools which resulted in + missing interrupts for devices which used `_copy` in their patches (see #440) + ## [v0.12.0] 2020-09-20 Family-specific: @@ -49,6 +636,7 @@ Family-specific: * Add preliminary support for MP1 family (#425) Common: + * Document CRC for F3, F7, H7, L0, L4 (#376) * Swap to GHA for CI (#377) * Fix Makefile for MacOS (#396) @@ -101,9 +689,10 @@ Family-specific: * ADC documentation (#338) Common: - * Fixed typo in I2C `OA1EN` `Disabled` variant name for many devices (#365) - * Hopefully fixed docs.rs building (#355) - * Generated crate directories no longer stored in git (#346) + +* Fixed typo in I2C `OA1EN` `Disabled` variant name for many devices (#365) +* Hopefully fixed docs.rs building (#355) +* Generated crate directories no longer stored in git (#346) Thanks to: @@ -169,6 +758,7 @@ Common: * Added new nightlies repository which can be directly used in Cargo: [nightlies] Thanks to: + [@aurelj] [@dotcypress] [@hannobraun] [@samcrow] [@korken89] [@richardeoin] [@rfuest] [@Sh3Rm4n] [@nickray] [@thinxer] [@lynaghk] @@ -218,6 +808,7 @@ Thanks to: ## [v0.8.0] 2019-07-28 Family-specific: + * F1: * FLASH ACR LATENCY field (#221) * ADC definitions (#233) @@ -258,6 +849,7 @@ Family-specific: * Split into four devices: H743/H743v/H753/H753v (#247) Common: + * Updated svdpatch.py to prohibit enumerated values with leading numerals (#199) * PAR register added to DMA cluster on many families (#214) @@ -282,6 +874,7 @@ Thanks to: ## [v0.7.0] 2019-04-22 Family-specific: + * F0: Add missing DMA interrupts (#181), flash peripheral (#172) * F1: Add enumerated values for GPIO (#186) * F3: Split up and fix `SYSCFG`, `COMP`, and `OPAMP` (#173, #189) @@ -431,7 +1024,12 @@ work in this release! * Fix nvicPrioBits being incorrect in many STM32s (de117ef) * Add support for specifying interrupts and modifying CPU node -[Unreleased]: https://github.com/stm32-rs/stm32-rs/compare/v0.12.0...HEAD +[Unreleased]: https://github.com/stm32-rs/stm32-rs/compare/v0.15.0...HEAD +[v0.15.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.14.0...v0.15.0 +[v0.14.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.13.0...v0.14.0 +[v0.13.1]: https://github.com/stm32-rs/stm32-rs/compare/v0.13.0...v0.13.1 +[v0.13.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.12.1...v0.13.0 +[v0.12.1]: https://github.com/stm32-rs/stm32-rs/compare/v0.12.0...v0.12.1 [v0.12.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.11.0...v0.12.0 [v0.11.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.10.0...v0.11.0 [v0.10.0]: https://github.com/stm32-rs/stm32-rs/compare/v0.9.0...v0.10.0 @@ -449,9 +1047,13 @@ work in this release! [v0.2.1]: https://github.com/stm32-rs/stm32-rs/compare/v0.2.0...v0.2.1 [v0.2.0]: https://github.com/stm32-rs/stm32-rs/compare/7b47b4...v0.2.0 +[@adamgreig]: https://github.com/adamgreig +[@astapleton]: https://github.com/astapleton [@ajfrantz]: https://github.com/ajfrantz [@albru123]: https://github.com/albru123 [@almusil]: https://github.com/almusil +[@AlyoshaVasilieva]: https://github.com/AlyoshaVasilieva +[@AndreasKarg]: https://github.com/AndreasKarg [@arkorobotics]: https://github.com/arkorobotics [@astro]: https://github.com/astro [@aurabindo]: https://github.com/aurabindo @@ -459,49 +1061,118 @@ work in this release! [@birkenfeld]: https://github.com/birkenfeld [@BryanKadzban]: https://github.com/BryanKadzban [@burrbull]: https://github.com/burrbull +[@ByteNaked]: https://github.com/ByteNaked +[@chengsun]: https://github.com/chengsun [@cyberillithid]: https://github.com/cyberillithid +[@cyrusmetcalf]: https://github.com/cyrusmetcalf +[@David-OConnor]: https://github.com/David-OConnor +[@davidlattimore]: https://github.com/davidlattimore +[@datdenkikniet]: https://github.com/datdenkikniet +[@DerFetzer]: https://github.com/DerFetzer +[@dgoodland]: https://github.com/dgoodland [@diondokter]: https://github.com/diondokter [@dirk-dms]: https://github.com/dirk-dms [@disasm]: https://github.com/disasm +[@diseraluca]: https://github.com/diseraluca [@dotcypress]: https://github.com/dotcypress [@ehntoo]: https://github.com/ehntoo +[@Elemecca]: https://github.com/Elemecca +[@eupn]: https://github.com/eupn +[@eZioPan]: https://github.com/eZioPan +[@FerdinandvHagen]: https://github.com/FerdinandvHagen +[@FrigoreD]: https://github.com/FrigoreD +[@Geens]: https://github.com/Geens +[@Gekkio]: https://github.com/Gekkio [@HarkonenBade]: https://github.com/HarkonenBade [@helgrind]: https://github.com/helgrind [@hnez]: https://github.com/hnez [@hoachin]: https://github.com/hoachin +[@hydra]: https://github.com/hydra +[@ianic]: https://github.com/ianic [@ijager]: https://github.com/ijager +[@iostat]: https://github.com/iostat +[@jamwaffles]: https://github.com/jamwaffles +[@JarLob]: https://github.com/JarLob [@jessebraham]: https://github.com/jessebraham +[@jglauche]: https://github.com/jglauche +[@jhbruhn]: https://github.com/jhbruhn [@jkristell]: https://github.com/jkristell [@jonas-schievink]: https://github.com/jonas-schievink +[@jonathanherbst]: https://github.com/jonathanherbst [@jordens]: https://github.com/jordens +[@jorgeig-space]: https://github.com/jorgeig-space +[@jspngh]: https://github.com/jspngh +[@karlp]: https://github.com/karlp +[@kenbell]: https://github.com/kenbell +[@kevswims]: https://github.com/kevswims [@kitzin]: https://github.com/kitzin [@korken89]: https://github.com/korken89 +[@larchuto]: https://github.com/larchuto +[@LeonSkoog]: https://github.com/LeonSkoog +[@liamkinne]: https://github.com/liamkinne [@lichtfeind]: https://github.com/lichtfeind [@lochsh]: https://github.com/lochsh +[@lulf]: https://github.com/lulf [@lynaghk]: https://github.com/lynaghk [@mabezdev]: https://github.com/mabezdev [@MarcoIeni]: https://github.com/MarcoIeni +[@MathiasKoch]: https://github.com/MathiasKoch [@mathk]: https://github.com/mathk +[@matoushybl]: https://github.com/matoushybl] +[@mattcarp12]: https://github.com/mattcarp12 [@MattCatz]: https://github.com/MattCatz [@mattico]: https://github.com/mattico +[@mattthebaker]: https://github.com/mattthebaker [@maximeborges]: https://github.com/maximeborges +[@newAM]: https://github.com/newAM [@nickray]: https://github.com/nickray +[@noslaver]: https://github.com/noslaver +[@noppej]: https://github.com/noppej [@octronics]: https://github.com/octronics +[@ofauchon]: https://github.com/ofauchon +[@oldsheep68]: https://github.com/oldsheep68 +[@omion]: https://github.com/omion [@osannolik]: https://github.com/osannolik [@Pagten]: https://github.com/Pagten +[@pawelchcki]: https://github.com/pawelchcki [@Piroro-hs]: https://github.com/Piroro-hs -[@Rahix]: https://github.com/Rahix +[@qwandor]: https://github.com/qwandor [@ra-kete]: https://github.com/ra-kete +[@Rahix]: https://github.com/Rahix +[@rblaze]: https://github.com/rblaze +[@reitermarkus]: https://github.com/reitermarkus [@rfuest]: https://github.com/rfuest [@richard7770]: https://github.com/richard7770 [@richardeoin]: https://github.com/richardeoin +[@rmsc]: https://github.com/rmsc +[@RootCubed]: https://github.com/RootCubed [@ryan-summers]: https://github.com/ryan-summers [@samcrow]: https://github.com/samcrow +[@sephamorr]: https://github.com/sephamorr [@Sh3Rm4n]: https://github.com/Sh3Rm4n +[@sirhcel]: https://github.com/sirhcel [@solderjs]: https://github.com/solderjs +[@sorki]: https://github.com/sorki +[@sphw]: https://github.com/sphw +[@systec-ms]: https://github.com/systec-ms [@tachiniererin]: https://github.com/tachiniererin +[@taylorh140]: https://github.com/taylorh140 +[@tdaede]: https://github.com/tdaede [@therealprof]: https://github.com/therealprof [@thinxer]: https://github.com/thinxer +[@tim-seoss]: https://github.com/tim-seoss +[@timblakely]: https://github.com/timblakely +[@timokroeger]: https://github.com/timokroeger +[@TomDeRybel]: https://github.com/TomDeRybel [@torkeldanielsson]: https://github.com/torkeldanielsson +[@TwoHandz]: https://github.com/TwoHandz +[@Urhengulas]: https://github.com/Urhengulas +[@usbalbin]: https://github.com/usbalbin +[@vinchatl]: https://github.com/vinchatl +[@wallacejohn]: https://github.com/wallacejohn +[@Wassasin]: https://github.com/Wassasin +[@Windfisch]: https://github.com/Windfisch +[@X-yl]: https://github.com/X-yl [@x37v]: https://github.com/x37v +[@YruamaLairba]: https://github.com/YruamaLairba [@yusefkarim]: https://github.com/yusefkarim diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 000000000..c301b6da3 --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,176 @@ +# Contributing Guidelines + +Thank you for your interest in contributing to stm32-rs! Below are some guides +to help with common contribution tasks. If you think anything is missing, +please open an issue or PR to fix this file. + +## Before you start + +It's worth double-checking that the change you want hasn't already been made, +either in the current master branch (but not yet released), or in another +device but still applies to your device. Try using GitHub search or grepping +the repository for relevant register or field names; if someone else has +already described the peripheral or created the fix you need, you can simply +include it in the device that requires it, or you might be able to copy or +refactor their change to also apply to your situation. + +Next, check where your changes should go: + +* Fixes to the structure of an SVD file, such as adding a register, renaming a + field, or deleting a peripheral, go in `devices/`, either in the + device-specific file `devices/stm32xxxx.yaml` or the shared patches under + `devices/patches/`. +* Descriptions of fields, which means either enumerated values ("you can write + 1 to this field to mean 'Start'") or write constraints ("this field can take + any value from 2 to 30") go in `devices/fields/`. +* Patches which collect registers, clusters and fields in SVD arrays and + patches which collect registers in clusters should go in `devices/collect/`. + +## Fixing bugs in SVD files + +If there's an error in the SVD (or generated crate) for a device, for example +a missing register or field, or a field that's the wrong width or name, you +can fix these using the [svdtools](https://github.com/stm32-rs/svdtools) YAML +patching syntax. + +If your fix is only for a specific device, the patch should go into the +`devices/stm32xxxx.yaml` file. If your fix applies to multiple devices, +there may already be a suitable file in `devices/patches/` which +you could edit, or otherwise please create a new file in that directory. + +As an example, PR [#526](https://github.com/stm32-rs/stm32-rs/pull/526) added +a missing field for the L4x3 device. Here the missing field is specific to +that device, so the patch goes in `devices/stm32l4x3.yaml`, inside the existing +`RCC` top-level section: + +```diff + RCC: + APB1ENR1: + ... ++ APB1RSTR1: ++ _add: ++ USBFSRST: ++ description: USB FS reset ++ bitOffset: 26 ++ bitWidth: 1 +``` + +It's important to not duplicate top-level YAML keys: because the `RCC` section +already existed, adding a new one would cause the previous one to be ignored. + +See the [svdtools](https://github.com/stm32-rs/svdtools) README for more +information on the YAML patching syntax, or have a look at some existing +patches to get an idea of how patching works. + +## Adding descriptions + +The SVD files supplied by ST do not contain any information on what values may +be written to fields, but [svd2rust](https://crates.io/crates/svd2rust) uses +such information to create its safe and user-friendly API in the crates we +generate. We place this sort of change in the `devices/fields/` directory, and +then include them in each device that uses them. Typically it's possible to +cover a lot of devices, since many share the same peripherals, and someone may +have already described the peripheral you're interested in for another device, +in which case you can simply include their YAML file into your device. + +There are two types of description: either "enumerated values", which describe +the list of possible named values the field may take, or "write constraints", +which are a set of integers that may be written to the field. The syntax is +described in the [svdtools] readme. + +For example, PR [#486](https://github.com/stm32-rs/stm32-rs/pull/486) added +descriptions for the OPAMP peripheral in the STM32G4 family: + +```yaml +OPAMP: + OPAMP?_CSR: + LOCK: + ReadWrite: [0, "CSR is read-write"] + ReadOnly: [1, "CSR is read-only, can only be cleared by system reset"] + TRIMOFFSETN: [0, 31] +``` + +Here any register matching `OPAMP?_CSR` is updated, meaning any single digit +in place of the `?`. The `LOCK` field can be written with `ReadWrite` or +`ReadOnly`, corresponding to values 0 and 1, while the `TRIMOFFSETN` field can +take any value in the range 0 to 31 inclusive. With this information, svd2rust +generates safe APIs allowing code like `opamp1_csr.write(|w| +w.lock().read_write().trimoffsetn().bits(15))`. + +For more complicated peripherals, it's common to split the descriptions into +separate files, as some devices may only use a subset of the full descriptions. + +## Adding a new device + +Before adding a new device, check if it's meant to be covered by an existing +device - for example, the STM32F415 is covered by the `stm32f405` feature, +because they are very similar and share an SVD file. You can check in the +`stm32_parts_table.yaml` file if this is the case. + +If the device is not already supported, we need an SVD file to add it. +Sometimes the SVD file already exists but is not used yet -- in a local clone of +the repository, run `svd/extract.sh` and check if a suitable SVD file is +present. If not, you'll need to download it from ST's website, possibly +updating the entire family's zip file. See PR +[#514](https://github.com/stm32-rs/stm32-rs/pull/514) for an example. + +Once the SVD file exists, create a new file `devices/stm32xxxxx.yaml` with the +`_svd` top-level key set to the path of the SVD file to use. You can then +include any patches or descriptions that are relevant to the new device; +the script `scripts/matchperipherals.py` might be helpful to find matching +patches. See PR [#532](https://github.com/stm32-rs/stm32-rs/pull/532) for an +example of adding a new device. + +Finally, the new device must be added to the `stm32_parts_table.yaml` file, +along with some metadata about its reference manual, web page, and the list +of chips it covers (which may be just one chip). + +## Adding a new family + +To add a whole new family (for exmaple, STM32F4), in addition to the steps +above for adding a new device, the family must be added to a few other +locations: + +* Update `.github/workflows/ci.yaml` to add the family to `crates` +* Update `.github/workflows/nightlies.yaml` and check the `Build and publish` + step will move the generated files to `../nightly` +* Update `Makefile` to add the family to `CRATES` +* Update `scripts/makecrates.py` to add the family to `CRATE_DOC_FEATURES` + and `CRATE_DOC_TARGETS`, and possibly update the family-name logic in `main` + +For an example, see PR [#467](https://github.com/stm32-rs/stm32-rs/pull/467). + +## Checking your work + +If possible, run `make` in a local clone of the repository to rebuild the +patched SVDs and crates after your change. To build only the SVD files and +not generate the crate, run `make patch`. If you specify the `CRATES` +environment variable, only that family is updated: `CRATES=stm32f0 make`. + +The continuous integration (CI) system will also build everything from scratch +when you submit a PR, and also generates a text-based memory map diff which +can help check your changes had the intended effect. These diffs won't show +changes to descriptions or reflect newly added SVD files, though. + +## Getting help + +Please open a draft PR or an issue if you want an error fixed or other change +made but aren't sure how to do it. + +## Once your PR is merged + +After your PR is merged, an updated crate is automatically pushed to +[stm32-rs/nightlies](https://github.com/stm32-rs/stm32-rs-nightlies) which you +can use as a git dependency in your `Cargo.toml`. The published crates on +crates.io are updated on a slower cadence, typically every few months. + +## Licensing + +As mentioned in the [README](https://github.com/stm32-rs/stm32-rs#readme), +the stm32-rs project contributions are dual licensed under the Apache license +version 2.0 and the MIT license, and: + +> Unless you explicitly state otherwise, any contribution intentionally +> submitted for inclusion in the work by you, as defined in the Apache-2.0 +> license, shall be dual licensed as above, without any additional terms or +> conditions. diff --git a/Makefile b/Makefile index d2e8ffea0..ac26f8446 100644 --- a/Makefile +++ b/Makefile @@ -1,21 +1,32 @@ all: patch svd2rust -.PHONY: patch crates svd2rust form check clean-rs clean-patch clean-html clean-svd clean +.PHONY: extract patch crates svd2rust svdconv form check clean_mmaps clean-rs clean-patch clean-html clean-svd clean_svdconv clean lint mmaps .PRECIOUS: svd/%.svd .deps/%.d SHELL := /usr/bin/env bash -CRATES ?= stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32h7 \ - stm32l0 stm32l1 stm32l4 stm32l5 stm32g0 stm32g4 stm32mp1 +# Path to `svd`/`svdtools` +SVDTOOLS ?= svdtools + +CRATES ?= stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 \ + stm32h5 stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32g0 stm32g4 \ + stm32mp1 stm32n6 stm32u0 stm32u5 stm32wl stm32wb # All yaml files in devices/ will be used to patch an SVD YAMLS := $(foreach crate, $(CRATES), \ $(wildcard devices/$(crate)*.yaml)) # Each yaml file in devices/ exactly name-matches an SVD file in svd/ +EXTRACTED_SVDS := $(patsubst devices/%.yaml, svd/%.svd, $(YAMLS)) PATCHED_SVDS := $(patsubst devices/%.yaml, svd/%.svd.patched, $(YAMLS)) FORMATTED_SVDS := $(patsubst devices/%.yaml, svd/%.svd.formatted, $(YAMLS)) +# Each yaml file also corresponds to a mmap in mmaps/ +MMAPS := $(patsubst devices/%.yaml, mmaps/%.mmap, $(YAMLS)) + +# Each yaml file also corresponds to svdconv report in svdconv/ +SVDCONV_REPORTS := $(patsubst devices/%.yaml, svdconv/%.txt, $(YAMLS)) + # Each device will lead to a crate/src/device/mod.rs file RUST_SRCS := $(foreach crate, $(CRATES), \ $(patsubst devices/$(crate)%.yaml, \ @@ -36,33 +47,46 @@ CHECK_SRCS := $(foreach crate, $(CRATES), \ # Turn a devices/device.yaml and svd/device.svd into svd/device.svd.patched svd/%.svd.patched: devices/%.yaml svd/%.svd .deps/%.d - svd patch $< + $(SVDTOOLS) patch $< svd/%.svd.formatted: svd/%.svd.patched xmllint $< --format -o $@ +# Generate mmap from patched SVD +mmaps/%.mmap: svd/%.svd.patched + @mkdir -p mmaps + $(SVDTOOLS) mmap $< > $@ + +# Generate svdconv reports from patched SVD +svdconv/%.txt: svd/%.svd.patched + @mkdir -p svdconv + svdconv --suppress-warnings $< > $@ | true + # Generates the common crate files: Cargo.toml, build.rs, src/lib.rs, README.md crates: python3 scripts/makecrates.py devices/ -y --families $(CRATES) define crate_template -$(1)/src/%/mod.rs: svd/%.svd.patched $(1)/Cargo.toml +$(1)/src/%/mod.rs: svd/%.svd.patched settings/%.yaml $(1)/Cargo.toml mkdir -p $$(@D) - cd $$(@D); svd2rust -g -i ../../../$$< - rustfmt --config-path="rustfmt.toml" $$(@D)/lib.rs - sed "1,20d;23,28d" $$(@D)/lib.rs > $$@ - rm $$(@D)/build.rs $$(@D)/lib.rs + cd $$(@D); svd2rust -c ../../../svd2rust.toml -i ../../../$$< --settings "../../../$$(word 2,$$^)" + rustfmt $$@ + rm $$(@D)/build.rs mv -f $$(@D)/generic.rs $$(@D)/../ +settings/%.yaml: svd/%.svd.patched + mkdir -p settings + scripts/makesettings.sh $$< $$@ + $(1)/src/%/.form: $(1)/src/%/mod.rs - form -i $$< -o $$(@D) + form -f -i $$< -o $$(@D) rm $$< mv $$(@D)/lib.rs $$< - rustfmt --config-path="rustfmt.toml" $$< + rustfmt $$< touch $$@ $(1)/src/%/.check: $(1)/src/%/mod.rs - cd $(1) && cargo check --target-dir ../target/check/ --features rt,$$* + cd $(1) && cargo check --target-dir ../target/check/ --features rt,atomics,$$* touch $$@ $(1)/Cargo.toml: crates @@ -76,6 +100,8 @@ svd/%.svd: svd/.extracted ; svd/.extracted: cd svd && ./extract.sh && touch .extracted +extract: $(EXTRACTED_SVDS) + patch: $(PATCHED_SVDS) svd2rust: $(RUST_SRCS) crates @@ -88,16 +114,24 @@ check: $(CHECK_SRCS) html/index.html: $(PATCHED_SVDS) @mkdir -p html - python3 scripts/makehtml.py html/ svd/stm32*.svd.patched + svdtools html html/ $(PATCHED_SVDS) -html: html/index.html +html/comparisons.html: $(PATCHED_SVDS) scripts/htmlcomparesvdall.sh + scripts/htmlcomparesvdall.sh + +html: html/index.html html/comparisons.html lint: $(PATCHED_SVDS) xmllint --schema svd/cmsis-svd.xsd --noout $(PATCHED_SVDS) +mmaps: $(MMAPS) + +svdconv: $(SVDCONV_REPORTS) + clean-rs: rm -rf $(RUST_DIRS) rm -f */src/generic.rs + rm -rf settings clean-patch: rm -f $(PATCHED_SVDS) @@ -106,6 +140,12 @@ clean-patch: clean-html: rm -rf html +clean-mmaps: + rm -rf mmaps + +clean-svdconv: + rm -rf svdconv + clean-crates: rm -rf $(CRATES) @@ -113,7 +153,7 @@ clean-svd: rm -f svd/*.svd rm -f svd/.extracted -clean: clean-rs clean-patch clean-html clean-svd +clean: clean-rs clean-patch clean-html clean-svd clean-mmaps clean-svdconv rm -rf .deps # As alternative to `pip install --user svdtools`: @@ -125,9 +165,12 @@ update-venv: venv/bin/pip install -U pip venv/bin/pip install -U -r requirements.txt +install: + scripts/tool_install.sh + # Generate dependencies for each device YAML .deps/%.d: devices/%.yaml @mkdir -p .deps - svd makedeps $< $@ + $(SVDTOOLS) makedeps $< $@ -include .deps/* diff --git a/Makefile.toml b/Makefile.toml new file mode 100644 index 000000000..bc9800f88 --- /dev/null +++ b/Makefile.toml @@ -0,0 +1,433 @@ +env_scripts = [''' +#!@duckscript +crates = get_env CRATES +crates = array %{crates} +NAMES = set "" +CRATE_NAMES = set "" +YAMLS = set "" +PATCHED_SVDS = set "" +FORMATTED_SVDS = set "" +RUST_DIRS = set "" +for crate in ${crates} + crate_yamls = glob_array devices/${crate}*.yaml + for yaml in ${crate_yamls} + serie = substring ${yaml} 8 + serie = substring ${serie} -5 + NAMES = concat ${NAMES} " " ${serie} + CRATE_NAMES = concat ${CRATE_NAMES} " " ${crate} + YAMLS = concat ${YAMLS} " " ${yaml} + PATCHED_SVDS = concat ${PATCHED_SVDS} " " svd/${serie}.svd.patched + FORMATTED_SVDS = concat ${FORMATTED_SVDS} " " svd/${serie}.svd.formatted + RUST_DIRS = concat ${RUST_DIRS} " " ${crate}/src/${serie}/ + end + release ${crate_yamls} +end +NAMES = trim ${NAMES} +set_env NAMES ${NAMES} +CRATE_NAMES = trim ${CRATE_NAMES} +set_env CRATE_NAMES ${CRATE_NAMES} +YAMLS = trim ${YAMLS} +set_env YAMLS ${YAMLS} +PATCHED_SVDS = trim ${PATCHED_SVDS} +set_env PATCHED_SVDS ${PATCHED_SVDS} +FORMATTED_SVDS = trim ${FORMATTED_SVDS} +set_env FORMATTED_SVDS ${FORMATTED_SVDS} +RUST_DIRS = trim ${RUST_DIRS} +set_env RUST_DIRS ${RUST_DIRS} +'''] + +[tasks.default] +alias = "patch" + +[tasks.install_svdtools] +install_crate = "svdtools" + +[tasks.install_svd2rust] +install_crate = "svd2rust" + +[tasks.install] +#dependencies = ["install_svdtools", "install_svd2rust"] +command = "scripts/tool_install.sh" + +[tasks.check-patched] +env = { "CRATES" = "${CRATE_NAMES}", "NAMES" = "${NAMES}" } +dependencies = ["svd2rust"] +script_runner = "@duckscript" +script = ''' +NAMES = array %{NAMES} +CRATES = array %{CRATES} +count = array_length ${NAMES} +handle = range 0 ${count} +for i in ${handle} + serie = array_get ${NAMES} ${i} + crate = array_get ${CRATES} ${i} + dir_name = set ${crate}/src/${serie} + modpath = set ${dir_name}/mod.rs + checkpath = set ${dir_name}/.check + + mod_modified = get_last_modified_time ${modpath} + if is_path_exists ${checkpath} + check_modified = get_last_modified_time ${checkpath} + need_update = less_than ${check_modified} ${mod_modified} + else + need_update = set true + end + if ${need_update} + echo "check: ${serie}" + cd ${crate} + exec cargo check --target-dir ../target/check/ --features rt,${serie} + cd .. + touch ${checkpath} + end +end +''' + +[tasks.form] +env = { "CRATES" = "${CRATE_NAMES}", "NAMES" = "${NAMES}" } +dependencies = ["svd2rust"] +script_runner = "@duckscript" +script = ''' +NAMES = array %{NAMES} +CRATES = array %{CRATES} +count = array_length ${NAMES} +handle = range 0 ${count} +for i in ${handle} + serie = array_get ${NAMES} ${i} + crate = array_get ${CRATES} ${i} + dir_name = set ${crate}/src/${serie} + modpath = set ${dir_name}/mod.rs + formpath = set ${dir_name}/.form + + mod_modified = get_last_modified_time ${modpath} + if is_path_exists ${formpath} + form_modified = get_last_modified_time ${formpath} + need_update = less_than ${form_modified} ${mod_modified} + else + need_update = set true + end + if ${need_update} + echo "form: ${serie}" + exec form -f -i ${modpath} -o ${dir_name} + rm ${modpath} + cp ${dir_name}/lib.rs ${modpath} + rm ${dir_name}/lib.rs + touch ${formpath} + end +end +''' + +[tasks.fmt] +env = { "CRATES" = "${CRATE_NAMES}", "NAMES" = "${NAMES}" } +dependencies = ["svd2rust"] +script_runner = "@duckscript" +script = ''' +NAMES = array %{NAMES} +CRATES = array %{CRATES} +count = array_length ${NAMES} +handle = range 0 ${count} +for i in ${handle} + serie = array_get ${NAMES} ${i} + crate = array_get ${CRATES} ${i} + dir_name = set ${crate}/src/${serie} + modpath = set ${dir_name}/mod.rs + formpath = set ${dir_name}/.form + + mod_modified = get_last_modified_time ${modpath} + if is_path_exists ${formpath} + form_modified = get_last_modified_time ${formpath} + need_update = less_than ${form_modified} ${mod_modified} + else + need_update = set true + end + if ${need_update} + echo "form: ${serie}" + exec form -f -i ${modpath} -o ${dir_name} + rm ${modpath} + cp ${dir_name}/lib.rs ${modpath} + rm ${dir_name}/lib.rs + touch ${formpath} + end + echo "rustfmt: ${serie}" + exec rustfmt ${modpath} +end +''' + +[tasks.svd2rust] +env = { "CRATES" = "${CRATE_NAMES}", "NAMES" = "${NAMES}" } +dependencies = ["patch", "crates"] +script_runner = "@duckscript" +script = ''' +NAMES = array %{NAMES} +CRATES = array %{CRATES} +count = array_length ${NAMES} +handle = range 0 ${count} +for i in ${handle} + serie = array_get ${NAMES} ${i} + crate = array_get ${CRATES} ${i} + dir_name = set ${crate}/src/${serie} + mkdir ${dir_name} + patchedpath = set svd/${serie}.svd.patched + modpath = set ${crate}/src/${serie}/mod.rs + + patched_modified = get_last_modified_time ${patchedpath} + if is_path_exists ${modpath} + mod_modified = get_last_modified_time ${modpath} + need_update = less_than ${mod_modified} ${patched_modified} + else + need_update = set true + end + if ${need_update} + echo "svd2rust: ${serie}" + output = exec svdtools info svd/${serie}.svd.patched device-name --input-format xml + devicename = trim ${output.stdout} + settings_path = set "settings/${serie}.yaml" + if not is_path_exists ${settings_path} + writefile "${settings_path}" "html_url: https://stm32-rs.github.io/stm32-rs/${devicename}.html\ncrate_path: crate::${serie}" + end + cd ${dir_name} + exec svd2rust -c "../../../svd2rust.toml" -i "../../../${patchedpath}" --settings "../../../${settings_path}" + rm build.rs + rm ../generic.rs + mv generic.rs ../ + cd ../../.. + exec rustfmt ${modpath} + end +end +''' + +[tasks.mmaps] +env = { "SVDTOOLS" = "${SVDTOOLS}", "NAMES" = "${NAMES}" } +dependencies = ["patch"] +script_runner = "@duckscript" +script = ''' +mkdir mmaps +NAMES = array %{NAMES} +for serie in ${NAMES} + patchedpath = set svd/${serie}.svd.patched + mmappath = set mmaps/${serie}.mmap + + patched_modified = get_last_modified_time ${patchedpath} + if is_path_exists ${mmappath} + mmap_modified = get_last_modified_time ${mmappath} + need_update = less_than ${mmap_modified} ${patched_modified} + else + need_update = set true + end + if ${need_update} + echo "mmaps: ${serie}" + command = set ${SVDTOOLS} + output = exec ${command} mmap ${patchedpath} + stdout = set ${output.stdout} + writefile ${mmappath} ${stdout} + end +end +''' + +[tasks.yamls] +env = { "SVDTOOLS" = "${SVDTOOLS}", "NAMES" = "${NAMES}" } +dependencies = ["patch"] +script_runner = "@duckscript" +script = ''' +mkdir yaml +NAMES = array %{NAMES} +for serie in ${NAMES} + patchedpath = set svd/${serie}.svd.patched + ymlpath = set yaml/${serie}.yaml + + patched_modified = get_last_modified_time ${patchedpath} + if is_path_exists ${ymlpath} + mmap_modified = get_last_modified_time ${ymlpath} + need_update = less_than ${mmap_modified} ${patched_modified} + else + need_update = set true + end + if ${need_update} + echo "yaml: ${serie}" + command = set ${SVDTOOLS} + exec ${command} convert --input-format xml ${patchedpath} ${ymlpath} + end +end +''' + +[tasks.svdconv] +env = { "NAMES" = "${NAMES}" } +dependencies = ["patch"] +script_runner = "@duckscript" +script = ''' +mkdir svdconv +NAMES = array %{NAMES} +for serie in ${NAMES} + patchedpath = set svd/${serie}.svd.patched + txtpath = set svdconv/${serie}.txt + + patched_modified = get_last_modified_time ${patchedpath} + if is_path_exists ${txtpath} + mmap_modified = get_last_modified_time ${txtpath} + need_update = less_than ${mmap_modified} ${patched_modified} + else + need_update = set true + end + if ${need_update} + echo "svdconv: ${serie}" + command = set ${SVDTOOLS} + output = exec svdconv --suppress-warnings ${patchedpath} + stdout = set ${output.stdout} + writefile ${txtpath} ${stdout} + end +end +''' + +[tasks.patch] +env = { "SVDTOOLS" = "${SVDTOOLS}", "NAMES" = "${NAMES}" } +dependencies = ["deps", "extracted"] +script_runner = "@duckscript" +script = ''' +NAMES = array %{NAMES} +for serie in ${NAMES} + patchedpath = set svd/${serie}.svd.patched + deppath = set .deps/${serie}.d + ymlpath = set devices/${serie}.yaml + + dep_modified = get_last_modified_time ${deppath} + if is_path_exists ${patchedpath} + patched_modified = get_last_modified_time ${patchedpath} + need_update = less_than ${patched_modified} ${dep_modified} + else + need_update = set true + end + if ${need_update} + echo "patch: ${serie}" + command = set ${SVDTOOLS} + exec ${command} patch ${ymlpath} + end +end +''' + +[tasks.deps] +private = true +env = { "SVDTOOLS" = "${SVDTOOLS}", "NAMES" = "${NAMES}" } +script_runner = "@duckscript" +script = ''' +mkdir .deps +NAMES = array %{NAMES} +for serie in ${NAMES} + deppath = set .deps/${serie}.d + ymlpath = set devices/${serie}.yaml + need_update = set false + yaml_modified = get_last_modified_time ${ymlpath} + if is_path_exists ${deppath} + dep_modified = get_last_modified_time ${deppath} + need_update = less_than ${dep_modified} ${yaml_modified} + + deps = readfile ${deppath} + handle = split ${deps} ": " + dep_files = array_pop ${handle} + dep_files = trim ${dep_files} + release ${handle} + if not starts_with ${dep_files} ".deps" + dep_files = array %{dep_files} + for file in ${dep_files} + if is_path_exists ${file} + dep_yaml_modified = get_last_modified_time ${file} + if less_than ${dep_modified} ${dep_yaml_modified} + echo "modified ${file}" + need_update = set true + end + else + echo "File ${file} is not founded" + need_update = set true + end + end + end + else + need_update = set true + end + if ${need_update} + echo "makedeps: ${serie}" + command = set ${SVDTOOLS} + exec ${command} makedeps ${ymlpath} ${deppath} + end +end +''' + +[tasks.extracted] +private = true +script_runner = "@duckscript" +condition = { files_not_exist = ["svd/.extracted"] } +script = { file = "svd/extract.ds" } + +[tasks.crates] +env = { "PYTHON" = "${PYTHON}" } +script_runner = "@duckscript" +script = ''' +command = set ${PYTHON} +exec ${command} scripts/makecrates.py devices/ -y --families ${CRATES} +''' + +[tasks.clean-rs] +env = { "RUST_DIRS" = "${RUST_DIRS}" } +script_runner = "@duckscript" +script = ''' +rm -r $RUST_DIRS +handle = glob_array */src/generic.rs +for file in ${handle} + rm ${file} +end +rm -r settings +''' + +[tasks.clean-patch] +env = { "PATCHED_SVDS" = "${PATCHED_SVDS}", "FORMATTED_SVDS" = "${FORMATTED_SVDS}" } +script_runner = "@duckscript" +script = ''' +rm %{PATCHED_SVDS} +rm %{FORMATTED_SVDS} +''' + +[tasks.clean-html] +script_runner = "@duckscript" +script = "rm -r html" + +[tasks.clean-mmaps] +script_runner = "@duckscript" +script = "rm -r mmaps" + +[tasks.clean-svdconv] +script_runner = "@duckscript" +script = "rm -r svdconv" + +[tasks.clean-crates] +env = { "CRATES" = "${CRATES}" } +script_runner = "@duckscript" +script = ''' +rm -r %{CRATES} +''' + +[tasks.clean-svd] +script_runner = "@duckscript" +script = ''' +handle = glob_array svd/*.svd +for file in ${handle} + rm ${file} +end +rm svd/.extracted +''' + +[tasks.clean-all] +dependencies = [ + "clean-rs", + "clean-patch", + "clean-html", + "clean-svd", + "clean-mmaps", + "clean-svdconv", +] +script_runner = "@duckscript" +script = "rm -r .deps" + +[env] +PYTHON = { value = "python3", condition = { env_not_set = ["PYTHON"] } } +SVDTOOLS = { value = "svdtools", condition = { env_not_set = ["SVDTOOLS"] } } +CRATES = { value = "stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32h5 stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32g0 stm32g4 stm32n6 stm32mp1 stm32wl stm32wb stm32u0 stm32u5", condition = { env_not_set = [ + "CRATES", +] } } diff --git a/README.md b/README.md index 126f33a1d..372c9feec 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,7 @@ # STM32 Peripheral Access Crates [![CI](https://github.com/stm32-rs/stm32-rs/workflows/CI/badge.svg?branch=master)](https://github.com/stm32-rs/stm32-rs) +[![crates.io](https://img.shields.io/crates/v/stm32c0.svg?label=stm32c0)](https://crates.io/crates/stm32c0) [![crates.io](https://img.shields.io/crates/v/stm32f0.svg?label=stm32f0)](https://crates.io/crates/stm32f0) [![crates.io](https://img.shields.io/crates/v/stm32f1.svg?label=stm32f1)](https://crates.io/crates/stm32f1) [![crates.io](https://img.shields.io/crates/v/stm32f2.svg?label=stm32f2)](https://crates.io/crates/stm32f2) @@ -9,12 +10,16 @@ [![crates.io](https://img.shields.io/crates/v/stm32f7.svg?label=stm32f7)](https://crates.io/crates/stm32f7) [![crates.io](https://img.shields.io/crates/v/stm32g0.svg?label=stm32g0)](https://crates.io/crates/stm32g0) [![crates.io](https://img.shields.io/crates/v/stm32g4.svg?label=stm32g4)](https://crates.io/crates/stm32g4) +[![crates.io](https://img.shields.io/crates/v/stm32h5.svg?label=stm32h5)](https://crates.io/crates/stm32h5) [![crates.io](https://img.shields.io/crates/v/stm32h7.svg?label=stm32h7)](https://crates.io/crates/stm32h7) [![crates.io](https://img.shields.io/crates/v/stm32l0.svg?label=stm32l0)](https://crates.io/crates/stm32l0) [![crates.io](https://img.shields.io/crates/v/stm32l1.svg?label=stm32l1)](https://crates.io/crates/stm32l1) [![crates.io](https://img.shields.io/crates/v/stm32l4.svg?label=stm32l4)](https://crates.io/crates/stm32l4) [![crates.io](https://img.shields.io/crates/v/stm32l5.svg?label=stm32l5)](https://crates.io/crates/stm32l5) +[![crates.io](https://img.shields.io/crates/v/stm32l5.svg?label=stm32n6)](https://crates.io/crates/stm32n6) [![crates.io](https://img.shields.io/crates/v/stm32mp1.svg?label=stm32mp1)](https://crates.io/crates/stm32mp1) +[![crates.io](https://img.shields.io/crates/v/stm32wl.svg?label=stm32wl)](https://crates.io/crates/stm32wl) +[![crates.io](https://img.shields.io/crates/v/stm32wb.svg?label=stm32wb)](https://crates.io/crates/stm32wb) [![Matrix](https://img.shields.io/matrix/stm32-rs:matrix.org)](https://matrix.to/#/#stm32-rs:matrix.org) This repository provides Rust device support crates for all STM32 @@ -47,7 +52,7 @@ to drill down into each field on each register on each peripheral. In your own project's `Cargo.toml`: ```toml [dependencies.stm32f4] -version = "0.12.0" +version = "0.16.0" features = ["stm32f405", "rt"] ``` @@ -85,18 +90,69 @@ features = ["stm32f405", "rt"] The nightlies should always build and be as stable as the latest release, but contain the latest patches and updates. - ## Generating Device Crates / Building Locally -* Install `svd2rust`: `cargo install svd2rust` -* Install `form`: `cargo install form` +* Install `svd2rust`, `svdtools`, and `form`: + * On x86-64 Linux, run `make install` to download pre-built binaries at the + current version used by stm32-rs + * Otherwise, build using `cargo` (double check versions against `scripts/tool_install.sh`): + * `cargo install form --version 0.13.0` + * `cargo install svdtools --version 0.4.6` + * `cargo install svd2rust --version 0.36.1` * Install rustfmt: `rustup component add rustfmt` -* Install svdtools: `pip install --user svdtools` -* Unzip bundled SVD zip files: `cd svd; ./extract.sh; cd ..` * Generate patched SVD files: `make patch` (you probably want `-j` for all `make` invocations) + * Alternatively you could install `cargo-make` runner and then use it instead of `make`. Works on MS Windows natively: + * `cargo install cargo-make` + * `cargo make patch` * Generate svd2rust device crates: `make svd2rust` * Optional: Format device crates: `make form` +Basically, the full process is: + +``` ++--------------------------+ +------------------------+ +--------------------------+ +--------------------------+ +| ST-supplied SVD archives | | SVD peripheral patches | | Peripheral fields detail | | Perip. fields collecting | +| in 'svd/vendor/' | | in 'devices/patches/' | | in 'devices/fields' | | in 'devices/collect' | ++--------------------------+ +------------------------+ +--------------------------+ +--------------------------+ + | | | | + | | (optional) (optional) + `make extract` | | | + | +----------------------------+-----------------------------+ + | | + v v ++----------------------------+ +--------------------------+ +| ST-supplied SVD files | | SVD device changes | +| in 'svd/' | | in 'devices/' | ++----------------------------+ +--------------------------+ + | | + +---------------------------+----------------------------+ + | + `make patch` + (using svdtools) + | + v + +------------------------+ + | Patched SVD files | + | in 'svd/' | + +------------------------+ + | + `make svd2rust` + | + v + +------------------------+ + | Generated STM32 crates | + | in 'stm32*/' | + +------------------------+ + | + `make form` (optional) + | + v + +------------------------+ + | Formatted STM32 crates | + | in 'stm32*/' | + +------------------------+ +``` + ## Motivation and Objectives This project serves two purposes: @@ -118,58 +174,48 @@ the community's STM32 device support in one place. This project is still young and there's a lot to do! * More peripheral patches need to be written, most of all. See what we've got - in `peripherals/` and grab a reference manual! + in `devices/` and grab a reference manual! + * Each `stm32*.yaml` file is a patch for a specific device SVD. + * To avoid repetition, common patches are written per peripheral in + `devices/patches`. Search there if a patch you want to add doesn't already + exist! + * Register fields description in `devices/fields` are not a part of the + CMSIS-SVD specification but enable type-safe friendly-name interface + (enumerated values) for highly detailed crates. + * `devices/collect` is here for collecting in `array`s, `cluster`s and `derive`s + to minimize duplication. * Also everything needs testing, and you can't so easily automate finding bugs in the SVD files... -## Supported Device Families - -[![crates.io](https://img.shields.io/crates/v/stm32f0.svg?label=stm32f0)](https://crates.io/crates/stm32f0) -[![crates.io](https://img.shields.io/crates/v/stm32f1.svg?label=stm32f1)](https://crates.io/crates/stm32f1) -[![crates.io](https://img.shields.io/crates/v/stm32f2.svg?label=stm32f2)](https://crates.io/crates/stm32f2) -[![crates.io](https://img.shields.io/crates/v/stm32f3.svg?label=stm32f3)](https://crates.io/crates/stm32f3) -[![crates.io](https://img.shields.io/crates/v/stm32f4.svg?label=stm32f4)](https://crates.io/crates/stm32f4) -[![crates.io](https://img.shields.io/crates/v/stm32f7.svg?label=stm32f7)](https://crates.io/crates/stm32f7) -[![crates.io](https://img.shields.io/crates/v/stm32g0.svg?label=stm32g0)](https://crates.io/crates/stm32g0) -[![crates.io](https://img.shields.io/crates/v/stm32g4.svg?label=stm32g4)](https://crates.io/crates/stm32g4) -[![crates.io](https://img.shields.io/crates/v/stm32h7.svg?label=stm32h7)](https://crates.io/crates/stm32h7) -[![crates.io](https://img.shields.io/crates/v/stm32l0.svg?label=stm32l0)](https://crates.io/crates/stm32l0) -[![crates.io](https://img.shields.io/crates/v/stm32l1.svg?label=stm32l1)](https://crates.io/crates/stm32l1) -[![crates.io](https://img.shields.io/crates/v/stm32l4.svg?label=stm32l4)](https://crates.io/crates/stm32l4) -[![crates.io](https://img.shields.io/crates/v/stm32l5.svg?label=stm32l5)](https://crates.io/crates/stm32l5) -[![crates.io](https://img.shields.io/crates/v/stm32mp1.svg?label=stm32mp1)](https://crates.io/crates/stm32mp1) - -Please see the individual crate READMEs for the full list of devices each crate -supports. All SVDs released by ST for STM32 devices are covered, so probably -your device is supported to some extent! - -**Devices that are nearly identical, like the STM32F405/F415, are supported by -ST under a single SVD file STM32F405, so if you can't find your exact device -check if its sibling is supported instead. The crate READMEs make this clear.** - -Many peripherals are not yet patched to provide the type-safe friendly-name -interface (enumerated values); please consider helping out with this! +### Adding New Devices -Check out the full list of supported devices [here](https://stm32-rs.github.io/stm32-rs/). - -## Adding New Devices - -* Update SVD zips in `svd/vendor` to include new SVD. -* Run `svd/extract.sh` to extract the zips into `svd` (ignored in git). +* Update SVD zips in `svd/vendor` to include new SVDs. +* Run `make extract` to extract the new zip files. * Add new YAML file in `devices/` with the new SVD path and include any required SVD patches for this device, such as renaming or merging fields. +* Add the new devices to `stm32_part_table.yaml`. +* Add the new devices to `scripts/makecrates.py`. * You can run `scripts/matchperipherals.py` script to find out what existing peripherals could be cleanly applied to this new SVD. If they look sensible, - you can include them in your device YAML. + you can include them in your device YAML. This requires a Python environment with the `pyyaml` + and `svdtools` dependencies. + Example command: `python scripts/matchperipherals.py devices/fields/rcc devices/stm32h562.yaml` * Re-run `scripts/makecrates.py devices/` to update the crates with the new devices. * Run `make` to rebuild, which will make a patched SVD and then run `svd2rust` on it to generate the final library. -## Updating Existing Devices/Peripherals +If adding a new STM32 family (not just a new device to an existing family), complete +these steps as well: + +* Add the new devices to the `CRATES` field in `Makefile`. +* Update this Readme to include the new devices. +* Add the devices to `workflows/ci.yaml` and `workflows/nightlies.yaml`. + +### Updating Existing Devices/Peripherals -* You'll need to run `svd/extract.sh` at least once to pull the SVDs out. +* Using Linux, run `make extract` at least once to pull the SVDs out. * Edit the device or peripheral YAML (see below for format). -* Run `make` to rebuild all the crates using `svd patch` and `svd2rust`. +* Using Linux, run `make` to rebuild all the crates using `svd patch` and `svd2rust`. * Test your new stuff compiles: `cd stm32f4; cargo build --features stm32f405` If you've added a new peripheral, consider using the `matchperipherals.py` @@ -181,12 +227,11 @@ SVD file, with registers and fields ready to be populated. For single bit wide fields with names ending in 'E' or 'D' it additionally generates sample "Enabled"/"Disabled" entries to save time. -## Device and Peripheral YAML Format +### Device and Peripheral YAML Format Please see the [svdtools](https://github.com/stm32-rs/svdtools) documentation for full details of the patch file format. - ### Style Guide * Enumerated values should be named in the past tense ("enabled", "masked", @@ -197,21 +242,16 @@ for full details of the patch file format. Notes for maintainers: -``` -$ make -j16 form -$ env CARGO_INCREMENTAL=0 make -j12 check -$ vi scripts/makecrates.py # update version number -$ python3 scripts/makecrates.py devices/ -$ vi CHANGELOG.md # add changelog entry -$ vi README.md # update version number -$ git checkout -b vX.X.X -$ git commit -am "vX.X.X" -$ git push origin vX.X.X -# wait for CI build to succeed -$ git tag -a 'vX.X.X' -m 'vX.X.X' -$ git push origin vX.X.X -$ for f in stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32g0 stm32g4 stm32mp1; cd $f; pwd; cargo publish --allow-dirty; cd ..; end -``` +1. Create PR preparing for new release: + * Update `CHANGELOG.md` with changes since last release and new contributors + * Update `README.md` to bump version number in example snippet + * Update `scripts/makecrates.py` to update version number for generated PACs +2. Merge PR once CI passes, pull master locally. +3. `make clean` +4. `make -j16 form` +5. `for f in stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32h5 stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32g0 stm32g4 stm32mp1 stm32n6 stm32u0 stm32u5 stm32wl stm32wb; cd $f; pwd; cargo publish --allow-dirty --no-default-features; cd ..; end` +6. `git tag -a vX.X.X -m vX.X.X` +7. `git push vX.X.X` ## License diff --git a/cortex_m/armv8m.svd b/cortex_m/armv8m.svd new file mode 100644 index 000000000..c3afb03f7 --- /dev/null +++ b/cortex_m/armv8m.svd @@ -0,0 +1,24 @@ + + + ARMv8-M + 1.0 + ARMv8-M Common Peripherals + + CM33 + r1p0 + little + true + false + 3 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + diff --git a/cortex_m/armv8m.yaml b/cortex_m/armv8m.yaml new file mode 100644 index 000000000..920f82fc1 --- /dev/null +++ b/cortex_m/armv8m.yaml @@ -0,0 +1,3 @@ +_svd: armv8m.svd + +# No files included yet. diff --git a/cortex_m/peripherals/bak/scb.yaml b/cortex_m/peripherals/bak/scb.yaml index afe2f806f..de22e63de 100644 --- a/cortex_m/peripherals/bak/scb.yaml +++ b/cortex_m/peripherals/bak/scb.yaml @@ -48,4 +48,3 @@ _add: description: Debug Fault Status Register addressOffset: 0x30 access: read-write - diff --git a/cortex_m/peripherals/cpb.yaml b/cortex_m/peripherals/cpb.yaml index 891f51759..4b5de2916 100644 --- a/cortex_m/peripherals/cpb.yaml +++ b/cortex_m/peripherals/cpb.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 52 + usage: registers registers: ICIALLU: description: I-cache invalidate all to PoU diff --git a/cortex_m/peripherals/cpuid_v6.yaml b/cortex_m/peripherals/cpuid_v6.yaml index 6c1dd2e07..894155538 100644 --- a/cortex_m/peripherals/cpuid_v6.yaml +++ b/cortex_m/peripherals/cpuid_v6.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 4 + usage: registers registers: Base: description: Provides identification information for the processor diff --git a/cortex_m/peripherals/cpuid_v7.yaml b/cortex_m/peripherals/cpuid_v7.yaml index f23a26e5c..af7df7bfc 100644 --- a/cortex_m/peripherals/cpuid_v7.yaml +++ b/cortex_m/peripherals/cpuid_v7.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x88 + usage: registers registers: Base: description: Provides identification information for the processor diff --git a/cortex_m/peripherals/dcb.yaml b/cortex_m/peripherals/dcb.yaml index a522b557c..5c6123d62 100644 --- a/cortex_m/peripherals/dcb.yaml +++ b/cortex_m/peripherals/dcb.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x110 + usage: registers registers: DHCSR: description: Debug Halting Control and Status Register diff --git a/cortex_m/peripherals/dwt.yaml b/cortex_m/peripherals/dwt.yaml index 8b686fd87..70e6df3bd 100644 --- a/cortex_m/peripherals/dwt.yaml +++ b/cortex_m/peripherals/dwt.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x1000 + usage: registers registers: CTRL: description: Control Register diff --git a/cortex_m/peripherals/fpb.yaml b/cortex_m/peripherals/fpb.yaml index e1beee49d..595d2ac35 100644 --- a/cortex_m/peripherals/fpb.yaml +++ b/cortex_m/peripherals/fpb.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x1000 + usage: registers registers: CTRL: description: FlashPatch Control Register diff --git a/cortex_m/peripherals/fpu.yaml b/cortex_m/peripherals/fpu.yaml index 85b392e03..ffa53d3b6 100644 --- a/cortex_m/peripherals/fpu.yaml +++ b/cortex_m/peripherals/fpu.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x1C + usage: registers registers: FPCCR: description: Floating Point Context Control Register diff --git a/cortex_m/peripherals/itm.yaml b/cortex_m/peripherals/itm.yaml index fdc3c0823..1801bbb8e 100644 --- a/cortex_m/peripherals/itm.yaml +++ b/cortex_m/peripherals/itm.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x1000 + usage: registers registers: STIM0: description: Stimulus Port Register 0 diff --git a/cortex_m/peripherals/mpu.yaml b/cortex_m/peripherals/mpu.yaml index 2d51fa1c8..74f8db992 100644 --- a/cortex_m/peripherals/mpu.yaml +++ b/cortex_m/peripherals/mpu.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x60 + usage: registers registers: TYPE: description: MPU Type Register diff --git a/cortex_m/peripherals/nvic.yaml b/cortex_m/peripherals/nvic.yaml index 7d4eb4056..9842f0a40 100644 --- a/cortex_m/peripherals/nvic.yaml +++ b/cortex_m/peripherals/nvic.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0xC00 + usage: registers registers: ISER0: description: Interrupt Set-Enable Register 0 diff --git a/cortex_m/peripherals/scb.yaml b/cortex_m/peripherals/scb.yaml index 90c815fdb..627bda719 100644 --- a/cortex_m/peripherals/scb.yaml +++ b/cortex_m/peripherals/scb.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x90 + usage: registers registers: CPUID: description: CPUID Base Register diff --git a/cortex_m/peripherals/syst.yaml b/cortex_m/peripherals/syst.yaml index 3638c13a9..8a466da14 100644 --- a/cortex_m/peripherals/syst.yaml +++ b/cortex_m/peripherals/syst.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0xF0 + usage: registers registers: CSR: description: SysTick Control and Status Register diff --git a/cortex_m/peripherals/tpiu.yaml b/cortex_m/peripherals/tpiu.yaml index 7c2e43d34..a3e0c71e6 100644 --- a/cortex_m/peripherals/tpiu.yaml +++ b/cortex_m/peripherals/tpiu.yaml @@ -7,6 +7,7 @@ _add: addressBlock: offset: 0x0 size: 0x1000 + usage: registers registers: SSPSR: description: Supported Parallel Port Sizes Register diff --git a/devices/collect/adc/c0_g0_wl.yaml b/devices/collect/adc/c0_g0_wl.yaml new file mode 100644 index 000000000..711ba0cf7 --- /dev/null +++ b/devices/collect/adc/c0_g0_wl.yaml @@ -0,0 +1,28 @@ +CHSELR0: + _array: + CHSEL*: + description: Channel-%s selection +CHSELR1: + _array: + SQ?: + description: "%s conversion of the sequence" +ISR: + _array: + AWD?: + description: Analog watchdog %s flag +IER: + _array: + AWD?IE: + description: Analog watchdog %s interrupt enable +SMPR: + _array: + SMP?: + description: Sampling time selection %s + SMPSEL*: + description: Channel-%s sampling time selection +AWD2CR: + _array: + AWD2CH*: {} +AWD3CR: + _array: + AWD3CH*: {} diff --git a/devices/collect/adc/derive_sq.yaml b/devices/collect/adc/derive_sq.yaml new file mode 100644 index 000000000..98c9740c8 --- /dev/null +++ b/devices/collect/adc/derive_sq.yaml @@ -0,0 +1,7 @@ +SMPR[023]: + _derive: + SMP%s: SMPR1.SMP%s + +SQR[2-5]: + _derive: + SQ%s: SQR1.SQ%s diff --git a/devices/collect/adc/f0_l0.yaml b/devices/collect/adc/f0_l0.yaml new file mode 100644 index 000000000..e0390c70b --- /dev/null +++ b/devices/collect/adc/f0_l0.yaml @@ -0,0 +1,3 @@ +CHSELR: + _array: + CHSEL*: {} diff --git a/devices/collect/adc/jofr_jdr.yaml b/devices/collect/adc/jofr_jdr.yaml new file mode 100644 index 000000000..999f4af39 --- /dev/null +++ b/devices/collect/adc/jofr_jdr.yaml @@ -0,0 +1,22 @@ +_array: + JOFR?: + JOFFSET: [0, 4095] + description: injected channel data offset register %s + _modify: + JOFFSET1: + name: JOFFSET + description: Data offset for injected channel + JDR?: {} + +JSQR: + _array: + JSQ?: + description: "%s conversion in injected sequence" +SQR?: + _array: + SQ*: + description: "%s conversion in regular sequence" +SMPR?: + _array: + "SMP?,SMP??": + description: Channel %s sample time selection diff --git a/devices/collect/adc/v1/adc2_derive.yaml b/devices/collect/adc/v1/adc2_derive.yaml new file mode 100644 index 000000000..b3dc1f0c6 --- /dev/null +++ b/devices/collect/adc/v1/adc2_derive.yaml @@ -0,0 +1,4 @@ +_include: derive.yaml + +_derive: + CR2: ADC1.CR2 diff --git a/devices/collect/adc/v1/adc3_derive.yaml b/devices/collect/adc/v1/adc3_derive.yaml new file mode 100644 index 000000000..98667b353 --- /dev/null +++ b/devices/collect/adc/v1/adc3_derive.yaml @@ -0,0 +1,15 @@ +_include: derive.yaml + +CR2: + _derive: + TSVREFE: ADC1.CR2.TSVREFE + SWSTART: ADC1.CR2.SWSTART + JSWSTART: ADC1.CR2.JSWSTART + EXTTRIG: ADC1.CR2.EXTTRIG + JEXTTRIG: ADC1.CR2.JEXTTRIG + ALIGN: ADC1.CR2.ALIGN + DMA: ADC1.CR2.DMA + RSTCAL: ADC1.CR2.RSTCAL + CAL: ADC1.CR2.CAL + CONT: ADC1.CR2.CONT + ADON: ADC1.CR2.ADON diff --git a/devices/collect/adc/v1/derive.yaml b/devices/collect/adc/v1/derive.yaml new file mode 100644 index 000000000..cc81b0f39 --- /dev/null +++ b/devices/collect/adc/v1/derive.yaml @@ -0,0 +1,31 @@ +_derive: + SR: ADC1.SR + SMPR1: ADC1.SMPR1 + SMPR2: ADC1.SMPR2 + JOFR%s: ADC1.JOFR%s + HTR: ADC1.HTR + LTR: ADC1.LTR + SQR1: ADC1.SQR1 + SQR2: ADC1.SQR2 + SQR3: ADC1.SQR3 + JSQR: ADC1.JSQR + JDR%s: ADC1.JDR%s + +CR1: + _derive: + AWDEN: ADC1.CR1.AWDEN + JAWDEN: ADC1.CR1.JAWDEN + DISCNUM: ADC1.CR1.DISCNUM + JDISCEN: ADC1.CR1.JDISCEN + DISCEN: ADC1.CR1.DISCEN + JAUTO: ADC1.CR1.JAUTO + AWDSGL: ADC1.CR1.AWDSGL + SCAN: ADC1.CR1.SCAN + JEOCIE: ADC1.CR1.JEOCIE + AWDIE: ADC1.CR1.AWDIE + EOCIE: ADC1.CR1.EOCIE + AWDCH: ADC1.CR1.AWDCH + +DR: + _derive: + DATA: ADC1.DR.DATA diff --git a/devices/collect/adc/v3.yaml b/devices/collect/adc/v3.yaml new file mode 100644 index 000000000..588906abc --- /dev/null +++ b/devices/collect/adc/v3.yaml @@ -0,0 +1,52 @@ +_array: + OFR?: {} + JDR?: {} + +# H7 only +"?~CFGR2": + _array: + "?~RSHIFT?": + description: Right-shift data after Offset %s correction +CR: + _array: + "?~LINCALRDYW?": + description: Linearity calibration ready Word %s + +ISR: + _array: + AWD?: + description: Analog watchdog %s flag +IER: + _array: + AWD?IE: + description: Analog watchdog %s interrupt enable + +AWD2CR: + _array: + "AWD2CH[0-9],AWD2CH1[0-9]": {} +AWD3CR: + _array: + "AWD3CH[0-9],AWD3CH1[0-9]": {} + +JSQR: + _array: + JSQ?: + description: "%s conversion in injected sequence" +SQR?: + _array: + SQ*: + description: "%s conversion in regular sequence" +SMPR?: + _array: + "SMP?,SMP??": + description: Channel %s sample time selection + +# F3/L4/G4/WB +DIFSEL: + _array: + "?~DIFSEL[0-9],DIFSEL1[0-9]": + name: DIFSEL%s + description: Differential mode for channel %s + "?~DIFSEL_1[0-9],DIFSEL_11[0-9]": + name: DIFSEL%s + description: Differential mode for channel %s diff --git a/devices/collect/bkp/dr.yaml b/devices/collect/bkp/dr.yaml new file mode 100644 index 000000000..f6ce2cf06 --- /dev/null +++ b/devices/collect/bkp/dr.yaml @@ -0,0 +1,13 @@ +_array: + "DR[1-9],DR1[0]": + _modify: + D1: + name: D + D: [0, 0xFFFF] + "DR[1][1-9],DR[234][0-9]": + name: BKP_DR%s + displayName: BKP_DR%s + _modify: + DR11: + name: D + D: [0, 0xFFFF] diff --git a/devices/collect/bsec/n6.yaml b/devices/collect/bsec/n6.yaml new file mode 100644 index 000000000..d50d653bd --- /dev/null +++ b/devices/collect/bsec/n6.yaml @@ -0,0 +1,21 @@ +_array: + FVR*: {} + SPLOCK*: {} + SWLOCK*: {} + SRLOCK*: {} + OTPVLDR*: {} + SCRATCHR*: {} + EPOCHR*: {} + WOSCR*: {} +SPLOCK*: + _array: + SPLOCK*: {} +SWLOCK*: + _array: + SWLOCK*: {} +SRLOCK*: + _array: + SRLOCK*: {} +OTPVLDR*: + _array: + VLDF*: {} diff --git a/devices/collect/can/can.yaml b/devices/collect/can/can.yaml new file mode 100644 index 000000000..643e7bb6a --- /dev/null +++ b/devices/collect/can/can.yaml @@ -0,0 +1,34 @@ +"TDL?R,TDH?R,RDL?R,RDH?R": + _array: + DATA?: + description: DATA%s + +_cluster: + TX%s: + description: CAN Transmit cluster + TI?R: {} + TDT?R: {} + TDL?R: {} + TDH?R: {} + RX%s: + description: CAN Receive cluster + RI?R: {} + RDT?R: {} + RDL?R: {} + RDH?R: {} +_array: + RF?R: + _modify: + RFOM0: + name: RFOM + FOVR0: + name: FOVR + FULL0: + name: FULL + FMP0: + name: FMP + +TSR: + _array: + TME?: {} + LOW?: {} diff --git a/devices/collect/can/filter_bank.yaml b/devices/collect/can/filter_bank.yaml new file mode 100644 index 000000000..a6e1155fa --- /dev/null +++ b/devices/collect/can/filter_bank.yaml @@ -0,0 +1,31 @@ +_cluster: + FB%s: + description: CAN Filter Bank cluster + F*R1: + description: Filter bank x register 1 + F*R2: + description: Filter bank x register 2 + +FM?R: + _array: + FBM*: + description: Filter mode +FS?R: + _array: + FSC*: + description: Filter scale configuration +FFA?R: + _array: + FFA*: + description: Filter FIFO assignment for filter %s +FA?R: + _array: + FACT*: + description: Filter active + +# Merge the thousands of individal bit fields into a single field for each +# CAN filter register. This is not only much easier to use but also saves +# a huge amount of filespace and compilation time etc -- as much as 30% of all +# fields in many devices are just these CAN filter bank fields. +"F?R?,F??R?": + _merge: FB* diff --git a/devices/collect/comp/csr.yaml b/devices/collect/comp/csr.yaml new file mode 100644 index 000000000..35ed6b435 --- /dev/null +++ b/devices/collect/comp/csr.yaml @@ -0,0 +1,4 @@ +COMP: + _array: + C?CSR: + displayName: C%sCSR diff --git a/devices/collect/cryp/v1.yaml b/devices/collect/cryp/v1.yaml new file mode 100644 index 000000000..7f2975ec8 --- /dev/null +++ b/devices/collect/cryp/v1.yaml @@ -0,0 +1,7 @@ +_cluster: + KEY%s: + K?LR: {} + K?RR: {} + INIT%s: + IV?LR: {} + IV?RR: {} diff --git a/devices/collect/cryp/v2.yaml b/devices/collect/cryp/v2.yaml new file mode 100644 index 000000000..bb6fc4ab8 --- /dev/null +++ b/devices/collect/cryp/v2.yaml @@ -0,0 +1,17 @@ +_cluster: + KEY%s: + K?LR: {} + K?RR: {} + INIT%s: + IV?LR: {} + IV?RR: {} + +_array: + CSGCMCCM?R: + _modify: + CSGCMCCM0R: + name: CSGCMCCMR + CSGCM?R: + _modify: + CSGCM0R: + name: CSGCMR diff --git a/devices/collect/dac/array.yaml b/devices/collect/dac/array.yaml new file mode 100644 index 000000000..0f10b0c0a --- /dev/null +++ b/devices/collect/dac/array.yaml @@ -0,0 +1,21 @@ +_array: + DHR12R[12]: + description: channel%s 12-bit right-aligned data holding register + _modify: + DACC[12]DHR: + name: DACCDHR + DHR12L[12]: + description: channel%s 12-bit left aligned data holding register + _modify: + DACC[12]DHR: + name: DACCDHR + DHR8R[12]: + description: channel%s 8-bit right aligned data holding register + _modify: + DACC[12]DHR: + name: DACCDHR + DOR[12]: + description: channel%s data output register + _modify: + DACC[12]DOR: + name: DACCDOR diff --git a/devices/collect/dac/v2.yaml b/devices/collect/dac/v2.yaml new file mode 100644 index 000000000..e9ad75494 --- /dev/null +++ b/devices/collect/dac/v2.yaml @@ -0,0 +1,34 @@ +_include: + - array.yaml + +CR: + _array: + EN[12]: + description: DAC channel%s enable + BOFF[12]: + description: DAC channel%s output buffer disable + TEN[12]: + description: DAC channel%s trigger enable + WAVE[12]: + description: DAC channel%s noise/triangle wave generation enable + MAMP[12]: + description: DAC channel%s mask/amplitude selector + DMAEN[12]: {} + "?~DMAUDRIE[12]": + description: DAC channel%s DMA Underrun Interrupt enable +SWTRIGR: + _array: + SWTRIG[12]: {} +"?~DHR12RD": + _array: + DACC[12]DHR: {} +"?~DHR12LD": + _array: + DACC[12]DHR: + description: DAC channel%s 12-bit left-aligned data +"?~DHR8RD": + _array: + DACC[12]DHR: {} +"?~SR": + _array: + DMAUDR[12]: {} diff --git a/devices/collect/dac/v3.yaml b/devices/collect/dac/v3.yaml new file mode 100644 index 000000000..4dc665627 --- /dev/null +++ b/devices/collect/dac/v3.yaml @@ -0,0 +1,81 @@ +_include: + - array.yaml + +_array: + SHSR[12]: + description: DAC channel%s sample and hold sample time register + _strip_end: "1" + "?~STR[12]": + _strip_end: "1" + +CR: + _array: + EN[12]: + description: DAC channel%s enable + TEN[12]: + description: DAC channel%s trigger enable + WAVE[12]: + description: DAC channel%s noise/triangle wave generation enable + MAMP[12]: + description: DAC channel%s mask/amplitude selector + DMAEN[12]: + description: DAC channel%s DMA enable + DMAUDRIE[12]: + description: DAC channel%s DMA Underrun Interrupt enable + CEN[12]: + description: DAC channel%s calibration enable + +"SWTRGR,SWTRIGR": + _array: + SWTRIG[12]: + description: DAC channel%s software trigger + "?~SWTRIGB[12]": {} +"?~DHR12RD": + _array: + DACC[12]DHR: + description: DAC channel%s 12-bit right-aligned data +"?~DHR12LD": + _array: + DACC[12]DHR: + description: DAC channel%s 12-bit left-aligned data +"?~DHR8RD": + _array: + DACC[12]DHR: + description: DAC channel%s 8-bit right-aligned data +SR: + _array: + DMAUDR[12]: + description: DAC channel%s DMA underrun flag + CAL_FLAG[12]: + description: DAC channel%s calibration offset status + BWST[12]: + description: DAC channel%s busy writing sample time flag + "?~DAC[12]RDY": + description: DAC channel%s ready status bit + "?~DORSTAT[12]": + description: DAC channel%s output register status bit +CCR: + _array: + OTRIM[12]: + description: DAC channel%s offset trimming value +MCR: + _array: + MODE[12]: + description: DAC channel%s mode + "?~DMADOUBLE[12]": + description: DAC channel%s DMA double data mode + "?~SINFORMAT[12]": + description: Enable signed format for DAC channel%s +SHHR: + _array: + THOLD[12]: + description: DAC channel%s hold time (only valid in Sample and hold mode) +SHRR: + _array: + TREFRESH[12]: + description: DAC channel%s refresh time (only valid in Sample and hold mode) + +"?~STMODR": + _array: + STRSTTRIGSEL[12]: {} + STINCTRIGSEL[12]: {} diff --git a/devices/collect/dcmi/dcmi.yaml b/devices/collect/dcmi/dcmi.yaml new file mode 100644 index 000000000..8606c9d9e --- /dev/null +++ b/devices/collect/dcmi/dcmi.yaml @@ -0,0 +1,3 @@ +DR: + _array: + BYTE?: {} diff --git a/devices/collect/dfsdm/ch.yaml b/devices/collect/dfsdm/ch.yaml new file mode 100644 index 000000000..f7268200c --- /dev/null +++ b/devices/collect/dfsdm/ch.yaml @@ -0,0 +1,15 @@ +_cluster: + CH%s: + description: "DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers" + CH?CFGR1: + name: CFGR1 + CH?CFGR2: + name: CFGR2 + CH?AWSCDR: + name: AWSCDR + CH?WDATR: + name: WDATR + CH?DATINR: + name: DATINR + "?~CH?DLYR": + name: DLYR diff --git a/devices/collect/dfsdm/f7.yaml b/devices/collect/dfsdm/f7.yaml new file mode 100644 index 000000000..43402d1cb --- /dev/null +++ b/devices/collect/dfsdm/f7.yaml @@ -0,0 +1,64 @@ +DFSDM[0123]_AWHTR: + _array: + BKAWH?: {} + +DFSDM[0123]_AWLTR: + _array: + BKAWL?: {} + +DFSDM[0123]_AWSR: + _array: + AWHTF?: {} + AWLTF?: {} + +DFSDM[0123]_AWCFR: + _array: + CLRAWHTF?: {} + CLRAWLTF?: {} + +_cluster: + CH%s: + description: DFSDM channel configuration cluster + CHCFG?R1: + name: CFGR1 + CHCFG?R2: + name: CFGR2 + AWSCD?R: + name: AWSCDR + CHWDAT?R: + name: WDATR + CHDATIN?R: + name: DATINR + + FLT%s: + description: "DFSDM cluster: CR1, CR2, ISR, ICR, JCHGR, FCR, JDATAR, RDATAR, AWHTR, AWLTR, AWSR, AWCFR, EXMAX, EXMIN, CNVTIMR registers" + "DFSDM[0123]_CR1": + name: CR1 + "DFSDM[0123]_CR2": + name: CR2 + "DFSDM[0123]_ISR": + name: ISR + "DFSDM[0123]_ICR": + name: ICR + "DFSDM[0123]_JCHGR": + name: JCHGR + "DFSDM[0123]_FCR": + name: FCR + "DFSDM[0123]_JDATAR": + name: JDATAR + "DFSDM[0123]_RDATAR": + name: RDATAR + "DFSDM[0123]_AWHTR": + name: AWHTR + "DFSDM[0123]_AWLTR": + name: AWLTR + "DFSDM[0123]_AWSR": + name: AWSR + "DFSDM[0123]_AWCFR": + name: AWCFR + "DFSDM[0123]_EXMAX": + name: EXMAX + "DFSDM[0123]_EXMIN": + name: EXMIN + "DFSDM[0123]_CNVTIMR": + name: CNVTIMR diff --git a/devices/collect/dfsdm/v1.yaml b/devices/collect/dfsdm/v1.yaml new file mode 100644 index 000000000..b30cbdd8f --- /dev/null +++ b/devices/collect/dfsdm/v1.yaml @@ -0,0 +1,53 @@ +_include: + - ch.yaml + +FLT?AWHTR: + _array: + BKAWH?: {} + +FLT?AWLTR: + _array: + BKAWL?: {} + +FLT?AWSR: + _array: + AWHTF?: {} + AWLTF?: {} + +FLT?AWCFR: + _array: + CLRAWHTF?: {} + CLRAWLTF?: {} + +_cluster: + FLT%s: + FLT?CR1: + name: CR1 + FLT?CR2: + name: CR2 + FLT?ISR: + name: ISR + FLT?ICR: + name: ICR + FLT?JCHGR: + name: JCHGR + FLT?FCR: + name: FCR + FLT?JDATAR: + name: JDATAR + FLT?RDATAR: + name: RDATAR + FLT?AWHTR: + name: AWHTR + FLT?AWLTR: + name: AWLTR + FLT?AWSR: + name: AWSR + FLT?AWCFR: + name: AWCFR + FLT?EXMAX: + name: EXMAX + FLT?EXMIN: + name: EXMIN + FLT?CNVTIMR: + name: CNVTIMR diff --git a/devices/collect/dma/bdma.yaml b/devices/collect/dma/bdma.yaml new file mode 100644 index 000000000..38587db8b --- /dev/null +++ b/devices/collect/dma/bdma.yaml @@ -0,0 +1,16 @@ +_cluster: + CH%s: + description: "Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR? registers" + CCR?: + name: CR + CNDTR?: + name: NDTR + CPAR?: + name: PAR + CM0AR?: + name: M0AR + CM1AR?: + name: M1AR + +_include: + - isr_array.yaml diff --git a/devices/collect/dma/dma2d_clut.yaml b/devices/collect/dma/dma2d_clut.yaml new file mode 100644 index 000000000..a1694e82b --- /dev/null +++ b/devices/collect/dma/dma2d_clut.yaml @@ -0,0 +1,3 @@ +_array: + BGCLUT*: {} + FGCLUT*: {} diff --git a/devices/collect/dma/dmamux.yaml b/devices/collect/dma/dmamux.yaml new file mode 100644 index 000000000..8afe1cac5 --- /dev/null +++ b/devices/collect/dma/dmamux.yaml @@ -0,0 +1,23 @@ +_array: + C*CR: + name: CCR%s + description: DMA Multiplexer Channel %s Control register + RG*CR: + name: RGCR%s + +CSR: + _array: + SOF*: + description: Synchronization Overrun Flag %s +"CFR,CCFR": + _array: + CSOF*: + description: Synchronization Clear Overrun Flag %s +RGSR: + _array: + OF?: + description: Generator Overrun Flag %s +RGCFR: + _array: + COF?: + description: Generator Clear Overrun Flag %s diff --git a/devices/collect/dma/gpdma/fields.yaml b/devices/collect/dma/gpdma/fields.yaml new file mode 100644 index 000000000..77c90e390 --- /dev/null +++ b/devices/collect/dma/gpdma/fields.yaml @@ -0,0 +1,19 @@ +PRIVCFGR: + _array: + PRIV*: {} + +MISR: + _array: + MIS*: {} + +"?~SECCFGR": + _array: + SEC*: {} + +"?~RCFGLOCKR": + _array: + LOCK*: {} + +"?~SMISR": + _array: + MIS*: {} diff --git a/devices/collect/dma/gpdma/h5.yaml b/devices/collect/dma/gpdma/h5.yaml new file mode 100644 index 000000000..98c11d397 --- /dev/null +++ b/devices/collect/dma/gpdma/h5.yaml @@ -0,0 +1,72 @@ +_include: fields.yaml + +_cluster: + CH%s: + description: Channel cluster + "C[0-5]LBAR": + name: LBAR + "C[0-5]FCR": + name: FCR + "C[0-5]SR": + name: SR + "C[0-5]CR": + name: CR + "C[0-5]TR1": + name: TR1 + "C[0-5]TR2": + name: TR2 + "C[0-5]BR1": + name: BR1 + "C[0-5]SAR": + name: SAR + "C[0-5]DAR": + name: DAR + "C[0-5]LLR": + name: LLR + + CH2D%s: + description: 2D-addressing channel cluster + "C[6-7]LBAR": + name: LBAR + "C[6-7]FCR": + name: FCR + "C[6-7]SR": + name: SR + "C[6-7]CR": + name: CR + "C[6-7]TR1": + name: TR1 + "C[6-7]TR2": + name: TR2 + "C[6-7]BR1": + name: BR1 + _derive: + BNDT: CH%s.BR1.BNDT + "C[6-7]SAR": + name: SAR + "C[6-7]DAR": + name: DAR + "C[6-7]TR3": + name: TR3 + "C[6-7]BR2": + name: BR2 + "C[6-7]LLR": + name: LLR + _derive: + LA: CH%s.LLR.LA + ULL: CH%s.LLR.ULL + UDA: CH%s.LLR.UDA + USA: CH%s.LLR.USA + UB1: CH%s.LLR.UB1 + UT2: CH%s.LLR.UT2 + UT1: CH%s.LLR.UT1 + + _derive: + LBAR: CH%s.LBAR + FCR: CH%s.FCR + SR: CH%s.SR + CR: CH%s.CR + TR1: CH%s.TR1 + TR2: CH%s.TR2 + SAR: CH%s.SAR + DAR: CH%s.DAR diff --git a/devices/collect/dma/gpdma/h7rs_u5.yaml b/devices/collect/dma/gpdma/h7rs_u5.yaml new file mode 100644 index 000000000..028209aee --- /dev/null +++ b/devices/collect/dma/gpdma/h7rs_u5.yaml @@ -0,0 +1,72 @@ +_include: fields.yaml + +_cluster: + CH%s: + description: Channel cluster + "C?LBAR,C[1][01]LBAR": + name: LBAR + "C?FCR,C[1][01]FCR": + name: FCR + "C?SR,C[1][01]SR": + name: SR + "C?CR,C[1][01]CR": + name: CR + "C?TR1,C[1][01]TR1": + name: TR1 + "C?TR2,C[1][01]TR2": + name: TR2 + "C?BR1,C[1][01]BR1": + name: BR1 + "C?SAR,C[1][01]SAR": + name: SAR + "C?DAR,C[1][01]DAR": + name: DAR + "C?LLR,C[1][01]LLR": + name: LLR + + CH2D%s: + description: Extended channel cluster + "C[1][2-5]LBAR": + name: LBAR + "C[1][2-5]FCR": + name: FCR + "C[1][2-5]SR": + name: SR + "C[1][2-5]CR": + name: CR + "C[1][2-5]TR1": + name: TR1 + "C[1][2-5]TR2": + name: TR2 + "C[1][2-5]BR1": + name: BR1 + _derive: + BNDT: CH%s.BR1.BNDT + "C[1][2-5]SAR": + name: SAR + "C[1][2-5]DAR": + name: DAR + "C[1][2-5]TR3": + name: TR3 + "C[1][2-5]BR2": + name: BR2 + "C[1][2-5]LLR": + name: LLR + _derive: + LA: CH%s.LLR.LA + ULL: CH%s.LLR.ULL + UDA: CH%s.LLR.UDA + USA: CH%s.LLR.USA + UB1: CH%s.LLR.UB1 + UT2: CH%s.LLR.UT2 + UT1: CH%s.LLR.UT1 + + _derive: + LBAR: CH%s.LBAR + FCR: CH%s.FCR + SR: CH%s.SR + CR: CH%s.CR + TR1: CH%s.TR1 + TR2: CH%s.TR2 + SAR: CH%s.SAR + DAR: CH%s.DAR diff --git a/devices/collect/dma/h7_dmamux.yaml b/devices/collect/dma/h7_dmamux.yaml new file mode 100644 index 000000000..d07f549ff --- /dev/null +++ b/devices/collect/dma/h7_dmamux.yaml @@ -0,0 +1,15 @@ +_array: + C*CR: {} + RG*CR: {} +CFR: + _array: + CSOF*: {} +RGSR: + _array: + OF*: {} +RGCFR: + _array: + COF*: {} +CSR: + _array: + SOF*: {} diff --git a/devices/collect/dma/hpdma.yaml b/devices/collect/dma/hpdma.yaml new file mode 100644 index 000000000..a967f6571 --- /dev/null +++ b/devices/collect/dma/hpdma.yaml @@ -0,0 +1,82 @@ +PRIVCFGR: + _array: + PRIV*: {} + +RCFGLOCKR: + _array: + LOCK*: {} + +MISR: + _array: + MIS*: {} + +_cluster: + CH%s: + description: Channel cluster + "C?LBAR,C[1][01]LBAR": + name: LBAR + "C?FCR,C[1][01]FCR": + name: FCR + "C?SR,C[1][01]SR": + name: SR + "C?CR,C[1][01]CR": + name: CR + "C?TR1,C[1][01]TR1": + name: TR1 + "C?TR2,C[1][01]TR2": + name: TR2 + "C?BR1,C[1][01]BR1": + name: BR1 + "C?SAR,C[1][01]SAR": + name: SAR + "C?DAR,C[1][01]DAR": + name: DAR + "C?LLR,C[1][01]LLR": + name: LLR + + CH2D%s: + description: Extended channel cluster + "C[1][2-5]LBAR": + name: LBAR + "C[1][2-5]FCR": + name: FCR + "C[1][2-5]SR": + name: SR + "C[1][2-5]CR": + name: CR + "C[1][2-5]TR1": + name: TR1 + "C[1][2-5]TR2": + name: TR2 + "C[1][2-5]BR1": + name: BR1 + _derive: + BNDT: CH%s.BR1.BNDT + "C[1][2-5]SAR": + name: SAR + "C[1][2-5]DAR": + name: DAR + "C[1][2-5]TR3": + name: TR3 + "C[1][2-5]BR2": + name: BR2 + "C[1][2-5]LLR": + name: LLR + _derive: + LA: CH%s.LLR.LA + ULL: CH%s.LLR.ULL + UDA: CH%s.LLR.UDA + USA: CH%s.LLR.USA + UB1: CH%s.LLR.UB1 + UT2: CH%s.LLR.UT2 + UT1: CH%s.LLR.UT1 + + _derive: + LBAR: CH%s.LBAR + FCR: CH%s.FCR + SR: CH%s.SR + CR: CH%s.CR + TR1: CH%s.TR1 + TR2: CH%s.TR2 + SAR: CH%s.SAR + DAR: CH%s.DAR diff --git a/devices/collect/dma/isr_array.yaml b/devices/collect/dma/isr_array.yaml new file mode 100644 index 000000000..915b87718 --- /dev/null +++ b/devices/collect/dma/isr_array.yaml @@ -0,0 +1,21 @@ +ISR: + _array: + TEIF*: + description: Channel %s Transfer Error flag + HTIF*: + description: Channel %s Half Transfer Complete flag + TCIF*: + description: Channel %s Transfer Complete flag + GIF*: + description: Channel %s Global interrupt flag + +IFCR: + _array: + CTEIF*: + description: Channel %s Transfer Error clear + CHTIF*: + description: Channel %s Half Transfer clear + CTCIF*: + description: Channel %s Transfer Complete clear + CGIF*: + description: Channel %s Global interrupt clear diff --git a/devices/collect/dma/l5.yaml b/devices/collect/dma/l5.yaml new file mode 100644 index 000000000..f4bef208c --- /dev/null +++ b/devices/collect/dma/l5.yaml @@ -0,0 +1,16 @@ +_cluster: + CH%s: + description: "Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR?, and CM1AR? registers" + CCR?: + name: CR + CNDTR?: + name: NDTR + CPAR?: + name: PAR + CM0AR?: + name: M0AR + CM1AR?: + name: M1AR + +_include: + - isr_array.yaml diff --git a/devices/collect/dma/lpdma.yaml b/devices/collect/dma/lpdma.yaml new file mode 100644 index 000000000..f78d43392 --- /dev/null +++ b/devices/collect/dma/lpdma.yaml @@ -0,0 +1,42 @@ +SECCFGR: + _array: + SEC?: {} + +PRIVCFGR: + _array: + PRIV?: {} + +?~RCFGLOCKR: + _array: + LOCK?: {} + +MISR: + _array: + MIS?: {} + +SMISR: + _array: + MIS?: {} + +_cluster: + CH%s: + C?LBAR: + name: LBAR + C?FCR: + name: FCR + C?SR: + name: SR + C?CR: + name: CR + C?TR1: + name: TR1 + C?TR2: + name: TR2 + C?BR1: + name: BR1 + C?SAR: + name: SAR + C?DAR: + name: DAR + C?LLR: + name: LLR diff --git a/devices/collect/dma/mdma.yaml b/devices/collect/dma/mdma.yaml new file mode 100644 index 000000000..45992498f --- /dev/null +++ b/devices/collect/dma/mdma.yaml @@ -0,0 +1,56 @@ +_cluster: + CH%s: + description: "Channel cluster: C?ISR, C?IFCR, C?ESR, C?CR, C?TCR, C?BNDTR, C?SAR, C?DAR, C?BRUR, C?LAR, C?TBR, C?MAR and C?MDR registers" + "C[1][0-5]ISR,C?ISR": + name: ISR + _modify: + TEIF0: + name: TEIF + CTCIF0: + name: CTCIF + BRTIF0: + name: BRTIF + BTIF0: + name: BTIF + TCIF0: + name: TCIF + CRQA0: + name: CRQA + "C[1][0-5]IFCR,C?IFCR": + name: IFCR + _modify: + CTEIF0: + name: CTEIF + CCTCIF0: + name: CCTCIF + CBRTIF0: + name: CBRTIF + CBTIF0: + name: CBTIF + CLTCIF0: + name: CLTCIF + "C[1][0-5]ESR,C?ESR": + name: ESR + "C[1][0-5]CR,C?CR": + name: CR + "C[1][0-5]TCR,C?TCR": + name: TCR + "C[1][0-5]BNDTR,C?BNDTR": + name: BNDTR + "C[1][0-5]SAR,C?SAR": + name: SAR + "C[1][0-5]DAR,C?DAR": + name: DAR + "C[1][0-5]BRUR,C?BRUR": + name: BRUR + "C[1][0-5]LAR,C?LAR": + name: LAR + "C[1][0-5]TBR,C?TBR": + name: TBR + "C[1][0-5]MAR,C?MAR": + name: MAR + "C[1][0-5]MDR,C?MDR": + name: MDR +GISR0: + _array: + GIF*: {} diff --git a/devices/collect/dma/st.yaml b/devices/collect/dma/st.yaml new file mode 100644 index 000000000..57cee615d --- /dev/null +++ b/devices/collect/dma/st.yaml @@ -0,0 +1,18 @@ +S?CR: + _delete: + - ACK +_cluster: + ST%s: + description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers" + S?CR: + name: CR + S?NDTR: + name: NDTR + S?PAR: + name: PAR + S?M0AR: + name: M0AR + S?M1AR: + name: M1AR + S?FCR: + name: FCR diff --git a/devices/collect/dma/v1.yaml b/devices/collect/dma/v1.yaml new file mode 100644 index 000000000..30dcd77ca --- /dev/null +++ b/devices/collect/dma/v1.yaml @@ -0,0 +1,14 @@ +_cluster: + CH%s: + description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" + CCR?: + name: CR + CNDTR?: + name: NDTR + CPAR?: + name: PAR + CMAR?: + name: MAR + +_include: + - isr_array.yaml diff --git a/devices/collect/dsi/isr.yaml b/devices/collect/dsi/isr.yaml new file mode 100644 index 000000000..8fe0fd799 --- /dev/null +++ b/devices/collect/dsi/isr.yaml @@ -0,0 +1,18 @@ +ISR0: + _array: + AE*: + description: Acknowledge error %s + PE*: + description: PHY error %s +IER0: + _array: + AE*IE: + description: Acknowledge error %s interrupt enable + PE*IE: + description: PHY error %s interrupt enable +FIR0: + _array: + FAE*: + description: Force acknowledge error %s + FPE*: + description: Force PHY error %s diff --git a/devices/collect/exti/farray.yaml b/devices/collect/exti/farray.yaml new file mode 100644 index 000000000..c9722aa65 --- /dev/null +++ b/devices/collect/exti/farray.yaml @@ -0,0 +1,21 @@ +IMR: + _array: + "?~IM*": {} + "?~MR*": {} +EMR: + _array: + "?~EM*": {} + "?~MR*": {} +RTSR: + _array: + TR*: {} +FTSR: + _array: + TR*: {} +SWIER: + _array: + SWIER*: + description: Software Interrupt on line %s +PR: + _array: + PR*: {} diff --git a/devices/collect/flash/bank.yaml b/devices/collect/flash/bank.yaml new file mode 100644 index 000000000..102866e75 --- /dev/null +++ b/devices/collect/flash/bank.yaml @@ -0,0 +1,30 @@ +_cluster: + BANK%s: + KEYR?: + name: KEYR + CR?: + name: CR + SR?: + name: SR + CCR?: + name: CCR + PRAR_CUR?: + name: PRAR_CUR + PRAR_PRG?: + name: PRAR_PRG + SCAR_CUR?: + name: SCAR_CUR + SCAR_PRG?: + name: SCAR_PRG + WPSN_CUR?R: + name: WPSN_CURR + WPSN_PRG?R: + name: WPSN_PRGR + CRCCR?: + name: CRCCR + CRCSADD?R: + name: CRCSADDR + CRCEADD?R: + name: CRCEADDR + ECC_FA?R: + name: FAR diff --git a/devices/collect/flash/optcr/nwrp.yaml b/devices/collect/flash/optcr/nwrp.yaml new file mode 100644 index 000000000..392c201c7 --- /dev/null +++ b/devices/collect/flash/optcr/nwrp.yaml @@ -0,0 +1,3 @@ +OPTCR: + _array: + nWRP*: {} diff --git a/devices/collect/flash/optcr1/nwrp.yaml b/devices/collect/flash/optcr1/nwrp.yaml new file mode 100644 index 000000000..30f2b6075 --- /dev/null +++ b/devices/collect/flash/optcr1/nwrp.yaml @@ -0,0 +1,3 @@ +OPTCR1: + _array: + nWRP*: {} diff --git a/devices/collect/flash/optcr2/pcrop.yaml b/devices/collect/flash/optcr2/pcrop.yaml new file mode 100644 index 000000000..8660973ee --- /dev/null +++ b/devices/collect/flash/optcr2/pcrop.yaml @@ -0,0 +1,3 @@ +OPTCR2: + _array: + PCROP?: {} diff --git a/devices/collect/flash/secbbr.yaml b/devices/collect/flash/secbbr.yaml new file mode 100644 index 000000000..259689012 --- /dev/null +++ b/devices/collect/flash/secbbr.yaml @@ -0,0 +1,5 @@ +_array: + SECBB1R?: + description: FLASH secure block based bank 1 + SECBB2R?: + description: FLASH secure block based bank 2 diff --git a/devices/collect/fsmc/nand_v1.yaml b/devices/collect/fsmc/nand_v1.yaml new file mode 100644 index 000000000..a63a1d79d --- /dev/null +++ b/devices/collect/fsmc/nand_v1.yaml @@ -0,0 +1,7 @@ +_array: + PCR?: {} + SR?: {} + + PMEM?: {} + PATT?: {} + ECCR?: {} diff --git a/devices/collect/fsmc/sd.yaml b/devices/collect/fsmc/sd.yaml new file mode 100644 index 000000000..4370ff615 --- /dev/null +++ b/devices/collect/fsmc/sd.yaml @@ -0,0 +1,12 @@ +_array: + SDTR?: {} + +SDCR2: + _derive: + NC: SDCR1.NC + NR: SDCR1.NR + MWID: SDCR1.MWID + NB: SDCR1.NB + CAS: SDCR1.CAS + WP: SDCR1.WP + SDCLK: SDCR1.SDCLK diff --git a/devices/collect/fsmc/sd_derive.yaml b/devices/collect/fsmc/sd_derive.yaml new file mode 100644 index 000000000..ea2afdcb0 --- /dev/null +++ b/devices/collect/fsmc/sd_derive.yaml @@ -0,0 +1,9 @@ +SDCR2: + _derive: + NC: SDCR1.NC + NR: SDCR1.NR + MWID: SDCR1.MWID + NB: SDCR1.NB + CAS: SDCR1.CAS + WP: SDCR1.WP + SDCLK: SDCR1.SDCLK diff --git a/devices/collect/fsmc/sram.yaml b/devices/collect/fsmc/sram.yaml new file mode 100644 index 000000000..9857e3e38 --- /dev/null +++ b/devices/collect/fsmc/sram.yaml @@ -0,0 +1,9 @@ +_array: + BCR[2-4]: {} + BTR?: {} + BWTR?: {} + +"?~PCSCNTR": + _array: + CNTB?EN: + description: Counter Bank %s enable diff --git a/devices/collect/fsmc/sram_derive.yaml b/devices/collect/fsmc/sram_derive.yaml new file mode 100644 index 000000000..0d7c6da34 --- /dev/null +++ b/devices/collect/fsmc/sram_derive.yaml @@ -0,0 +1,17 @@ +BCR%s: + _derive: + MBKEN: BCR1.MBKEN + MUXEN: BCR1.MUXEN + MTYP: BCR1.MTYP + MWID: BCR1.MWID + FACCEN: BCR1.FACCEN + BURSTEN: BCR1.BURSTEN + WAITPOL: BCR1.WAITPOL + "?~WRAPMOD": BCR1.WRAPMOD + WAITCFG: BCR1.WAITCFG + WREN: BCR1.WREN + WAITEN: BCR1.WAITEN + EXTMOD: BCR1.EXTMOD + ASYNCWAIT: BCR1.ASYNCWAIT + "?~CPSIZE": BCR1.CPSIZE + CBURSTRW: BCR1.CBURSTRW diff --git a/devices/collect/gfxmmu/lut.yaml b/devices/collect/gfxmmu/lut.yaml new file mode 100644 index 000000000..c68446c38 --- /dev/null +++ b/devices/collect/gfxmmu/lut.yaml @@ -0,0 +1,6 @@ +_cluster: + LUT%s: + LUT*L: + description: Graphic MMU LUT entry x low + LUT*H: + description: Graphic MMU LUT entry x high diff --git a/devices/collect/gpio/derive.yaml b/devices/collect/gpio/derive.yaml new file mode 100644 index 000000000..8bbb857b0 --- /dev/null +++ b/devices/collect/gpio/derive.yaml @@ -0,0 +1,6 @@ +_derive: + IDR: GPIOA.IDR + ODR: GPIOA.ODR + BSRR: GPIOA.BSRR + "?~BRR": GPIOA.BRR + "?~LCKR": GPIOA.LCKR diff --git a/devices/collect/gpio/f1.yaml b/devices/collect/gpio/f1.yaml new file mode 100644 index 000000000..75030a400 --- /dev/null +++ b/devices/collect/gpio/f1.yaml @@ -0,0 +1,24 @@ +IDR: + _array: + IDR*: {} +ODR: + _array: + ODR*: {} +BSRR: + _array: + BR*: {} + BS*: + description: Set bit %s +BRR: + _array: + BR*: + description: Reset bit %s +LCKR: + _array: + "LCK[0-9],LCK1[0-5]": {} +CR[LH]: + _array: + CNF*: + description: Port n.%s configuration bits + MODE*: + description: Port n.%s mode bits diff --git a/devices/collect/gpio/f1_derive.yaml b/devices/collect/gpio/f1_derive.yaml new file mode 100644 index 000000000..46affb016 --- /dev/null +++ b/devices/collect/gpio/f1_derive.yaml @@ -0,0 +1,4 @@ +CRH: + _derive: + MODE%s: CRL.MODE%s + CNF%s: CRL.CNF%s diff --git a/devices/collect/gpio/gpioa_afr.yaml b/devices/collect/gpio/gpioa_afr.yaml new file mode 100644 index 000000000..4507dc712 --- /dev/null +++ b/devices/collect/gpio/gpioa_afr.yaml @@ -0,0 +1,3 @@ +AFRH: + _derive: + AFR%s: AFRL.AFR%s diff --git a/devices/collect/gpio/v2.yaml b/devices/collect/gpio/v2.yaml new file mode 100644 index 000000000..32c9908d8 --- /dev/null +++ b/devices/collect/gpio/v2.yaml @@ -0,0 +1,41 @@ +MODER: + _array: + MODER*: + description: Port x configuration pin %s +OTYPER: + _array: + OT*: + description: Port x configuration pin %s +OSPEEDR: + _array: + OSPEEDR*: + description: Port x configuration pin %s +PUPDR: + _array: + PUPDR*: + description: Port x configuration pin %s +IDR: + _array: + IDR*: + description: Port input data pin %s +ODR: + _array: + ODR*: + description: Port output data pin %s +BSRR: + _array: + BR*: + description: Port x reset pin %s + BS*: + description: Port x set pin %s +"?~BRR": + _array: + BR*: + description: Port x reset pin %s +"?~LCKR": + _array: + "LCK[0-9],LCK1[0-5]": + description: Port x lock pin %s +AFR[LH]: + _array: + "AFR*,AFSEL*": {} diff --git a/devices/collect/gpio/v2_derive.yaml b/devices/collect/gpio/v2_derive.yaml new file mode 100644 index 000000000..77a000d49 --- /dev/null +++ b/devices/collect/gpio/v2_derive.yaml @@ -0,0 +1,16 @@ +_include: derive.yaml + +_derive: + OTYPER: GPIOA.OTYPER + AFRL: GPIOA.AFRL + AFRH: GPIOA.AFRH + +MODER: + _derive: + MODER%s: GPIOA.MODER.MODER%s +OSPEEDR: + _derive: + OSPEEDR%s: GPIOA.OSPEEDR.OSPEEDR%s +PUPDR: + _derive: + PUPDR%s: GPIOA.PUPDR.PUPDR%s diff --git a/devices/collect/gpio/v2r.yaml b/devices/collect/gpio/v2r.yaml new file mode 100644 index 000000000..eaa224b77 --- /dev/null +++ b/devices/collect/gpio/v2r.yaml @@ -0,0 +1,49 @@ +MODER: + _array: + "MODE[0-9],MODE1[0-5]": + description: Port x configuration pin %s +OTYPER: + _array: + OT*: + description: Port x configuration pin %s +OSPEEDR: + _array: + "OSPEED[0-9],OSPEED1[0-5]": + description: Port x configuration pin %s +PUPDR: + _array: + "PUPD[0-9],PUPD1[0-5]": + description: Port x configuration pin %s +IDR: + _array: + "ID[0-9],ID1[0-5]": + description: Port input data pin %s +ODR: + _array: + "OD[0-9],OD1[0-5]": + description: Port output data pin %s +BSRR: + _array: + BR*: + description: Port x reset pin %s + BS*: + description: Port x set pin %s +BRR: + _array: + BR*: + description: Port x reset pin %s +LCKR: + _array: + "LCK[0-9],LCK1[0-5]": + description: Port x lock pin %s +AFR[LH]: + _array: + "AFR*,AFSEL*": {} + +"?~HSLVR": + _array: + HSLV*: {} + +"?~SECCFGR": + _array: + SEC*: {} diff --git a/devices/collect/gpio/v2r_derive.yaml b/devices/collect/gpio/v2r_derive.yaml new file mode 100644 index 000000000..1920d7e28 --- /dev/null +++ b/devices/collect/gpio/v2r_derive.yaml @@ -0,0 +1,20 @@ +_include: derive.yaml + +_derive: + OTYPER: GPIOA.OTYPER + AFRL: GPIOA.AFRL + "?~AFRH": GPIOA.AFRH + "?~HSLVR": GPIOA.HSLVR + +MODER: + _derive: + MODE%s: GPIOA.MODER.MODE%s +OSPEEDR: + _derive: + OSPEED%s: GPIOA.OSPEEDR.OSPEED%s +PUPDR: + _derive: + PUPD%s: GPIOA.PUPDR.PUPD%s +"?~SECCFGR": + _derive: + SEC%s: GPIOA.SECCFGR.SEC%s diff --git a/devices/collect/gtzc/h5_u5.yaml b/devices/collect/gtzc/h5_u5.yaml new file mode 100644 index 000000000..90595ca4f --- /dev/null +++ b/devices/collect/gtzc/h5_u5.yaml @@ -0,0 +1,13 @@ +_array: + SECCFGR*: + description: MPCBBz security configuration for super-block %s register + _array: + SEC*: {} + PRIVCFGR*: + description: MPCBBz privileged configuration for super-block %s register + _array: + PRIV*: {} + +CFGLOCK,CFGLOCK?,CFGLOCKR?: + _array: + SPLCK*: {} diff --git a/devices/collect/hash/v1.yaml b/devices/collect/hash/v1.yaml new file mode 100644 index 000000000..5acf74caa --- /dev/null +++ b/devices/collect/hash/v1.yaml @@ -0,0 +1,9 @@ +_array: + HR?: + _modify: + H0: + name: H + CSR*: + _modify: + CSR0: + name: CSR diff --git a/devices/collect/hash/v2.yaml b/devices/collect/hash/v2.yaml new file mode 100644 index 000000000..6cd2a5af6 --- /dev/null +++ b/devices/collect/hash/v2.yaml @@ -0,0 +1,14 @@ +_array: + HR?: + _modify: + H0: + name: H + CSR*: + _modify: + CSR0: + name: CSR + HASH_HR?: + description: HASH digest register %s + _modify: + H0: + name: H diff --git a/devices/collect/hash/v3.yaml b/devices/collect/hash/v3.yaml new file mode 100644 index 000000000..c11e5dab5 --- /dev/null +++ b/devices/collect/hash/v3.yaml @@ -0,0 +1,16 @@ +_array: + HRA?: + description: HASH digest register alias %s + _modify: + H0: + name: H + HR*: + description: HASH digest register %s + _modify: + H0: + name: H + CSR*: + description: HASH context swap register %s + _modify: + "CS0,CSR0": + name: CS diff --git a/devices/collect/hrtim/f3.yaml b/devices/collect/hrtim/f3.yaml new file mode 100644 index 000000000..2741332bd --- /dev/null +++ b/devices/collect/hrtim/f3.yaml @@ -0,0 +1,13 @@ +_include: v1.yaml + +"HRTIM_TIM[AB-F]": {} + +"HRTIM_TIM[B-F]": + RSTR: + _derive: + TIM?CMP[1-4]: HRTIM_TIMA.RSTR.TIMBCMP1 + +HRTIM_Common: + EECR3: + _array: + EE*F: {} diff --git a/devices/collect/hrtim/h7.yaml b/devices/collect/hrtim/h7.yaml new file mode 100644 index 000000000..212f07c40 --- /dev/null +++ b/devices/collect/hrtim/h7.yaml @@ -0,0 +1,8 @@ +_include: v1.yaml + +"HRTIM_TIM[AB-F]": {} + +"HRTIM_TIM[B-F]": + RSTR: + _derive: + TIM?CMP[1-4]: HRTIM_TIMA.RSTR.TIMBCMP1 diff --git a/devices/collect/hrtim/v1.yaml b/devices/collect/hrtim/v1.yaml new file mode 100644 index 000000000..025e55f8f --- /dev/null +++ b/devices/collect/hrtim/v1.yaml @@ -0,0 +1,226 @@ +HRTIM_Master: + _derive: + CMP2R: CMP1R + CMP3R: CMP1R + CMP4R: CMP1R + CR: + _array: + T[A-F]CEN: {} + ISR: + _array: + CMP[1-4]: {} + ICR: + _array: + CMP[1-4]C: {} + DIER: + _array: + CMP[1-4]IE: {} + CMP[1-4]DE: {} + +"HRTIM_TIM[AB-F]": + _derive: + CNTR: HRTIM_Master.CNTR + PERR: HRTIM_Master.PERR + REPR: HRTIM_Master.REPR + CMP1R: HRTIM_Master.CMP1R + CMP2R: CMP1R + CMP3R: CMP1R + CMP4R: CMP1R + CPT2R: CPT1R + SET2R: SET1R + RST2R: RST1R + CPT2CR: CPT1CR + CR: + _derive: + CKPSC: HRTIM_Master.CR.CKPSC + CONT: HRTIM_Master.CR.CONT + RETRIG: HRTIM_Master.CR.RETRIG + HALF: HRTIM_Master.CR.HALF + SYNCRST: HRTIM_Master.CR.SYNCRST + SYNCSTRT: HRTIM_Master.CR.SYNCSTRT + DACSYNC: HRTIM_Master.CR.DACSYNC + PREEN: HRTIM_Master.CR.PREEN + ISR: + _array: + CMP[1-4]: {} + CPT[12]: {} + SET[12]: {} + IS[R]: + _derive: + CMP%s: HRTIM_Master.ISR.CMP%s + REP: HRTIM_Master.ISR.REP + UPD: HRTIM_Master.ISR.UPD + ICR: + _array: + CMP[1-4]C: {} + CPT[12]C: {} + SET[12]C: {} + IC[R]: + _derive: + "*C": HRTIM_Master.ICR.CMP%sC + DIER: + _array: + CMP[1-4]IE: {} + CMP[1-4]DE: {} + CPT[12]IE: {} + CPT[12]DE: {} + SET[12]IE: + description: Output %s set interrupt enable + SET[12]DE: + description: Output %s set DMA request enable + DIE[R]: + _derive: + "*DE": HRTIM_Master.DIER.CMP%sDE + "*IE": HRTIM_Master.DIER.CMP%sIE + FLTR: + _array: + FLT[1-6]EN: {} + EEFR[12]: + _array: + EE*LTCH: {} + EE*FLTR: {} + "SET1R,RST1R": + _array: + EXTEVNT*: {} + "MSTCMP[1-4]": {} + "CMP[1-4]": {} + RSTR: + _array: + EXTEVNT*: {} + "MSTCMP[1-4]": {} + CPT1CR: + _array: + EXEV*CPT: {} + +"HRTIM_TIM[B-F]": + _derive: + ISR: HRTIM_TIMA.ISR + ICR: HRTIM_TIMA.ICR + DIER: HRTIM_TIMA.DIER + CMP1CR: HRTIM_TIMA.CMP1CR + DTR: HRTIM_TIMA.DTR + EEFR1: HRTIM_TIMA.EEFR1 + EEFR2: HRTIM_TIMA.EEFR2 + CHPR: HRTIM_TIMA.CHPR + OUTR: HRTIM_TIMA.OUTR + FLTR: HRTIM_TIMA.FLTR + CPT1R: HRTIM_TIMA.CPT1R + + CR: + _derive: + PSHPLL: HRTIM_TIMA.CR.PSHPLL + DELCMP2: HRTIM_TIMA.CR.DELCMP2 + DELCMP4: HRTIM_TIMA.CR.DELCMP4 + TREPU: HRTIM_TIMA.CR.TREPU + TRSTU: HRTIM_TIMA.CR.TRSTU + MSTU: HRTIM_TIMA.CR.MSTU + UPDGAT: HRTIM_TIMA.CR.UPDGAT + + SET1R: + _derive: + SST: HRTIM_TIMA.SET1R.SST + RESYNC: HRTIM_TIMA.SET1R.RESYNC + PER: HRTIM_TIMA.SET1R.PER + CMP%s: HRTIM_TIMA.SET1R.CMP%s + MSTPER: HRTIM_TIMA.SET1R.MSTPER + MSTCMP%s: HRTIM_TIMA.SET1R.MSTCMP%s + TIM?CMP[1-4]: HRTIM_TIMA.SET1R.TIMBCMP1 + EXTEVNT%s: HRTIM_TIMA.SET1R.EXTEVNT%s + UPDATE: HRTIM_TIMA.SET1R.UPDATE + + RST1R: + _derive: + SRT: HRTIM_TIMA.RST1R.SRT + RESYNC: HRTIM_TIMA.RST1R.RESYNC + PER: HRTIM_TIMA.RST1R.PER + CMP%s: HRTIM_TIMA.RST1R.CMP%s + MSTPER: HRTIM_TIMA.RST1R.MSTPER + MSTCMP%s: HRTIM_TIMA.RST1R.MSTCMP%s + TIM?CMP[1-4]: HRTIM_TIMA.RST1R.TIMBCMP1 + EXTEVNT%s: HRTIM_TIMA.RST1R.EXTEVNT%s + UPDATE: HRTIM_TIMA.RST1R.UPDATE + + RSTR: + _derive: + UPDT: HRTIM_TIMA.RSTR.UPDT + CMP[24]: HRTIM_TIMA.RSTR.CMP2 + MSTPER: HRTIM_TIMA.RSTR.MSTPER + MSTCMP%s: HRTIM_TIMA.RSTR.MSTCMP%s + EXTEVNT%s: HRTIM_TIMA.RSTR.EXTEVNT%s + +HRTIM_Common: + _derive: + ADC3R: ADC1R + ADC4R: ADC2R + BDTBUPR: + _from: BDTAUPR + addressOffset: 0x60 + BDTCUPR: + _from: BDTAUPR + addressOffset: 0x64 + BDTDUPR: + _from: BDTAUPR + addressOffset: 0x68 + BDTEUPR: + _from: BDTAUPR + addressOffset: 0x6C + + CR1: + _array: + T[A-F]UDIS: + description: Timer %s Update Disable + AD[1-4]USRC: {} + CR2: + _array: + T[A-F]SWU: + description: Timer %s Software Update + T[A-F]RST: + description: Timer %s counter software reset + + EECR[12]: + _array: + EE*SRC: {} + EE*POL: {} + EE*SNS: {} + EECR1: + _array: + EE*FAST: {} + + FLTINR[12]: + _array: + FLT[1-6]E: + dimIncrement: 8 + FLT[1-6]P: + dimIncrement: 8 + FLT[1-6]SRC: + dimIncrement: 8 + description: Fault %s source + FLT[1-6]F: + dimIncrement: 8 + + BMCR: + _array: + T[A-F]BM: + description: Timer %s Burst Mode + + ADC[1-4]R: + _array: + MC[1-4]: {} + EEV*: {} + + OENR: + _array: + "T[A-F]1OEN": + description: Timer %s Output 1 Enable + "T[A-F]2OEN": + description: Timer %s Output 2 Enable + ODISR: + _array: + "T[A-F]1ODIS": {} + "T[A-F]2ODIS": {} + ODSR: + _array: + "T[A-F]1ODS": + description: Timer %s Output 1 disable status + "T[A-F]2ODS": + description: Timer %s Output 2 disable status diff --git a/devices/collect/hrtim/v2.yaml b/devices/collect/hrtim/v2.yaml new file mode 100644 index 000000000..1ed3fd760 --- /dev/null +++ b/devices/collect/hrtim/v2.yaml @@ -0,0 +1,42 @@ +_include: v1.yaml + +"HRTIM_TIM[AB-F]": {} + +"HRTIM_TIM[B-F]": + _derive: + CR2: HRTIM_TIMA.CR2 + EEFR3: HRTIM_TIMA.EEFR3 + CR: + _derive: + INTLVD: HRTIM_TIMA.CR.INTLVD + RSYNCU: HRTIM_TIMA.CR.RSYNCU + RSTR: + _derive: + TIM?CMP[1-4]: HRTIM_TIMA.RSTR.TIMFCMP1 + +HRTIM_Common: + _derive: + BDTFUPR: BDTAUPR + + CR2: + _array: + SWP[A-F]: {} + + EECR3: + _array: + EE*F: {} + + FLTINR2: + _array: + FLT[1-6]SRC_1: + description: Fault %s source bit 1 + FLTINR[34]: + _array: + FLT[1-6]BLKE: + dimIncrement: 8 + FLT[1-6]BLKS: + dimIncrement: 8 + FLT[1-6]CNT: + dimIncrement: 8 + FLT[1-6]CRES: + dimIncrement: 8 diff --git a/devices/collect/hsem/fields.yaml b/devices/collect/hsem/fields.yaml new file mode 100644 index 000000000..0300dba35 --- /dev/null +++ b/devices/collect/hsem/fields.yaml @@ -0,0 +1,16 @@ +IER,C[12]IER: + _array: + "ISE[0-9]*": + description: Interrupt semaphore %s enable bit +ICR,C[12]ICR: + _array: + "ISC[0-9]*": + description: Interrupt semaphore %s clear bit +ISR,C[12]ISR: + _array: + "ISF[0-9]*": + description: Interrupt semaphore %s status bit before enable (mask) +MISR,C[12]MISR: + _array: + "MISF[0-9]*": + description: Masked interrupt semaphore %s status bit after enable (mask) diff --git a/devices/collect/hsem/r.yaml b/devices/collect/hsem/r.yaml new file mode 100644 index 000000000..1ab561843 --- /dev/null +++ b/devices/collect/hsem/r.yaml @@ -0,0 +1,5 @@ +_array: + RLR*: + description: Semaphore %s read lock register + "R?,R??": + description: HSEM register HSEM_R%s diff --git a/devices/collect/icache/crr.yaml b/devices/collect/icache/crr.yaml new file mode 100644 index 000000000..445c54063 --- /dev/null +++ b/devices/collect/icache/crr.yaml @@ -0,0 +1,3 @@ +ICACHE: + _array: + CRR?: {} diff --git a/devices/collect/jpeg/ram_common.yaml b/devices/collect/jpeg/ram_common.yaml new file mode 100644 index 000000000..4688e0d5c --- /dev/null +++ b/devices/collect/jpeg/ram_common.yaml @@ -0,0 +1,24 @@ +_array: + QMEM0_*: + name: QMEM0%s + QMEM1_*: + name: QMEM1%s + QMEM2_*: + name: QMEM2%s + QMEM3_*: + name: QMEM3%s + HUFFBASE*: {} + HUFFSYMB*: {} + DHTMEM*: {} + HUFFENC_AC0_*: + name: HUFFENC_AC0%s + description: JPEG encoder, AC Huffman table 0 + HUFFENC_AC1_*: + description: JPEG encoder, AC Huffman table 1 + name: HUFFENC_AC1%s + HUFFENC_DC0_*: + name: HUFFENC_DC0%s + description: JPEG encoder, DC Huffman table 0 + HUFFENC_DC1_*: + name: HUFFENC_DC1%s + description: JPEG encoder, DC Huffman table 1 diff --git a/devices/collect/jpeg/ram_f7.yaml b/devices/collect/jpeg/ram_f7.yaml new file mode 100644 index 000000000..bae358d17 --- /dev/null +++ b/devices/collect/jpeg/ram_f7.yaml @@ -0,0 +1,6 @@ +_array: + HUFFMIN_*: + name: HUFFMIN%s + +_include: + - ram_common.yaml diff --git a/devices/collect/jpeg/ram_h7rs.yaml b/devices/collect/jpeg/ram_h7rs.yaml new file mode 100644 index 000000000..ee260dc77 --- /dev/null +++ b/devices/collect/jpeg/ram_h7rs.yaml @@ -0,0 +1,18 @@ +_cluster: + HUFFMIN%s: + description: "HUFFMIN cluster: 100-bit minimum Huffman value" + HUFFMIN?_0: + name: HUFFMIN_0 + description: Bits 0-31 of the minimum Huffman value + HUFFMIN?_1: + name: HUFFMIN_1 + description: Bits 32-63 of the minimum Huffman value + HUFFMIN?_2: + name: HUFFMIN_2 + description: Bits 64-95 of the minimum Huffman value + HUFFMIN?_3: + name: HUFFMIN_3 + description: Bits 96-99 of the minimum Huffman value + +_include: + - ram_common.yaml diff --git a/devices/collect/lpgpio/lp.yaml b/devices/collect/lpgpio/lp.yaml new file mode 100644 index 000000000..34f86bf3d --- /dev/null +++ b/devices/collect/lpgpio/lp.yaml @@ -0,0 +1,16 @@ +MODER: + _array: + MODE*: {} +IDR: + _array: + ID*: {} +ODR: + _array: + OD*: {} +BSRR: + _array: + BS*: {} + BR*: {} +BRR: + _array: + BR*: {} diff --git a/devices/collect/ltdc/layer.yaml b/devices/collect/ltdc/layer.yaml new file mode 100644 index 000000000..3d5c8d03a --- /dev/null +++ b/devices/collect/ltdc/layer.yaml @@ -0,0 +1,26 @@ +_cluster: + LAYER%s: + L?CR: + name: CR + L?WHPCR: + name: WHPCR + L?WVPCR: + name: WVPCR + L?CKCR: + name: CKCR + L?PFCR: + name: PFCR + L?CACR: + name: CACR + L?DCCR: + name: DCCR + L?BFCR: + name: BFCR + L?CFBAR: + name: CFBAR + L?CFBLR: + name: CFBLR + L?CFBLNR: + name: CFBLNR + L?CLUTWR: + name: CLUTWR diff --git a/devices/collect/mce/v1.yaml b/devices/collect/mce/v1.yaml new file mode 100644 index 000000000..e4242953f --- /dev/null +++ b/devices/collect/mce/v1.yaml @@ -0,0 +1,25 @@ +MCE*: + _cluster: + CC%s: + description: Cipher context cluster + CC?CFGR: {} + CC?NR0: {} + CC?NR1: {} + CC?KEYR0: {} + CC?KEYR1: {} + CC?KEYR2: {} + CC?KEYR3: {} + REG%s: + description: Region cluster + REGCR?: + description: Region configuration register + SADDR?: + description: Region start address register + EADDR?: + description: Region end address register + ATTR?: + description: Region attribute register + + _array: + MKEYR?: {} + FMKEYR?: {} diff --git a/devices/collect/mdf/u5.yaml b/devices/collect/mdf/u5.yaml new file mode 100644 index 000000000..4b0030689 --- /dev/null +++ b/devices/collect/mdf/u5.yaml @@ -0,0 +1,18 @@ +_cluster: + FLT%s: + SITF?CR: {} + BSMX?CR: {} + DFLT?CR: {} + DFLT?CICR: {} + DFLT?RSFR: {} + DFLT?INTR: {} + OLD?CR: {} + OLD?THLR: {} + OLD?THHR: {} + DLY?CR: {} + SCD?CR: {} + DFLT?IER: {} + DFLT?ISR: {} + OEC?CR: {} + SNPS?DR: {} + DFLT?DR: {} diff --git a/devices/collect/mdios/dinr_doutr.yaml b/devices/collect/mdios/dinr_doutr.yaml new file mode 100644 index 000000000..f22595706 --- /dev/null +++ b/devices/collect/mdios/dinr_doutr.yaml @@ -0,0 +1,9 @@ +_array: + DINR*: + _modify: + DIN0: + name: DIN + DOUTR*: + _modify: + DOUT0: + name: DOUT diff --git a/devices/collect/ramecc/derive.yaml b/devices/collect/ramecc/derive.yaml new file mode 100644 index 000000000..9b12905e0 --- /dev/null +++ b/devices/collect/ramecc/derive.yaml @@ -0,0 +1,5 @@ +_modify: + M%s: + derivedFrom: RAMECC1.M%s +_derive: + IER: RAMECC1.IER diff --git a/devices/collect/ramecc/m.yaml b/devices/collect/ramecc/m.yaml new file mode 100644 index 000000000..1c71ea686 --- /dev/null +++ b/devices/collect/ramecc/m.yaml @@ -0,0 +1,14 @@ +_cluster: + M%s: + M?CR: + name: CR + M?SR: + name: SR + M?FAR: + name: FAR + M?FDRL: + name: FDRL + M?FDRH: + name: FDRH + M?FECR: + name: FECR diff --git a/devices/collect/rtc/alarm.yaml b/devices/collect/rtc/alarm.yaml new file mode 100644 index 000000000..f587493cc --- /dev/null +++ b/devices/collect/rtc/alarm.yaml @@ -0,0 +1,37 @@ +CR: + _array: + ALR[AB]E: + description: Alarm %s enable + ALR[AB]IE: + description: Alarm %s interrupt enable + +"?~ISR": + _array: + ALR[AB]WF: + description: Alarm %s write flag + ALR[AB]F: + description: Alarm %s flag + +"?~ICSR": + _array: + "?~ALR[AB]WF": + description: Alarm %s write flag + +"?~SR": + _array: + ALR[AB]F: + description: Alarm %s flag + +"?~MISR": + _array: + ALR[AB]MF: + description: Alarm %s masked flag + +_array: + ALRM[AB]R: + description: Alarm %s register + displayName: ALRM%sR + "?~ALRM[AB]SSR": + description: Alarm %s sub-second register + "?~ALR[AB]BINR": + description: Alarm %s binary mode register diff --git a/devices/collect/rtc/bkpr.yaml b/devices/collect/rtc/bkpr.yaml new file mode 100644 index 000000000..a61a05b10 --- /dev/null +++ b/devices/collect/rtc/bkpr.yaml @@ -0,0 +1,2 @@ +_array: + BKP*R: {} diff --git a/devices/collect/rtc/tamp_bkpr.yaml b/devices/collect/rtc/tamp_bkpr.yaml new file mode 100644 index 000000000..a61a05b10 --- /dev/null +++ b/devices/collect/rtc/tamp_bkpr.yaml @@ -0,0 +1,2 @@ +_array: + BKP*R: {} diff --git a/devices/collect/sai/ch.yaml b/devices/collect/sai/ch.yaml new file mode 100644 index 000000000..5f4de8d28 --- /dev/null +++ b/devices/collect/sai/ch.yaml @@ -0,0 +1,10 @@ +_cluster: + CH%s: + "?CR1": {} + "?CR2": {} + "?FRCR": {} + "?SLOTR": {} + "?IM": {} + "?SR": {} + "?CLRFR": {} + "?DR": {} diff --git a/devices/collect/sai/pdm.yaml b/devices/collect/sai/pdm.yaml new file mode 100644 index 000000000..f8f9f3a50 --- /dev/null +++ b/devices/collect/sai/pdm.yaml @@ -0,0 +1,10 @@ +PDMCR: + _array: + CKEN?: + description: Clock enable of bitstream clock number %s +PDMDLY: + _array: + DLYM?L: + description: Delay line adjust for first microphone of pair %s + DLYM?R: + description: Delay line adjust for second microphone of pair %s diff --git a/devices/collect/sdio/fifo.yaml b/devices/collect/sdio/fifo.yaml new file mode 100644 index 000000000..4399c9fb1 --- /dev/null +++ b/devices/collect/sdio/fifo.yaml @@ -0,0 +1,2 @@ +_array: + FIFOR*: {} diff --git a/devices/collect/sdio/resp.yaml b/devices/collect/sdio/resp.yaml new file mode 100644 index 000000000..4d2e5b8d2 --- /dev/null +++ b/devices/collect/sdio/resp.yaml @@ -0,0 +1,3 @@ +_array: + RESP?: + description: SDIO response %s register diff --git a/devices/collect/sdio/respr.yaml b/devices/collect/sdio/respr.yaml new file mode 100644 index 000000000..9ce953302 --- /dev/null +++ b/devices/collect/sdio/respr.yaml @@ -0,0 +1,3 @@ +_array: + RESP?R: + description: SDMMC response %s register diff --git a/devices/collect/sdmmc/fifo.yaml b/devices/collect/sdmmc/fifo.yaml new file mode 100644 index 000000000..4399c9fb1 --- /dev/null +++ b/devices/collect/sdmmc/fifo.yaml @@ -0,0 +1,2 @@ +_array: + FIFOR*: {} diff --git a/devices/collect/tim/ccr.yaml b/devices/collect/tim/ccr.yaml new file mode 100644 index 000000000..f8b960f4b --- /dev/null +++ b/devices/collect/tim/ccr.yaml @@ -0,0 +1,82 @@ +_modify: + CCR?: + description: capture/compare register +CCR?: + _modify: + "?~CCR?": + name: CCR + description: Capture/Compare value + +_array: + "CCR[1-4]": + displayName: CCR%s + +"?~CR2": + _array: + "?~OIS?": + description: Output Idle state (OC%s output) + "?~OIS?N": + description: Output Idle state (OC%sN output) + +CCER: + _array: + CC?E: + description: Capture/Compare %s output enable + CC?P: + description: Capture/Compare %s output Polarity + "?~CC?NP": + description: Capture/Compare %s output Polarity + "?~CC?NE": + description: Capture/Compare %s complementary output enable +"CCMR?_Input": + _array: + IC?PSC: + description: Input capture %s prescaler + IC?F: + description: Input capture %s filter +"?~CCMR2_Input*": + _derive: + IC%sF: CCMR1_Input.IC%sF + IC%sPSC: CCMR1_Input.IC%sPSC +"CCMR[12]_Output": + _array: + CC?S: + description: Capture/Compare %s selection +CCMR?_Output: + _array: + OC?FE: + description: Output compare %s fast enable + OC?PE: + description: Output compare %s preload enable + OC?M: + description: Output compare %s mode + "?~OC?CE": + description: Output compare %s clear enable + "?~OC?M_3": + description: Output compare %s mode, bit 3 +"?~CCMR[23]_Output*": + _derive: + OC%sFE: CCMR1_Output.OC%sFE + OC%sPE: CCMR1_Output.OC%sPE + OC%sM: CCMR1_Output.OC%sM + "?~OC%sCE": CCMR1_Output.OC%sCE + "?~OC%sM_3": CCMR1_Output.OC%sM_3 +"?~CCMR2_Output*": + _derive: + CC%sS: CCMR1_Output.CC%sS +DIER: + _array: + CC?IE: + description: Capture/Compare %s interrupt enable + "?~CC?DE": + description: Capture/Compare %s DMA request enable +SR: + _array: + "CC[1-4]IF": + description: Capture/compare %s interrupt flag + CC?OF: + description: Capture/Compare %s overcapture flag +EGR: + _array: + CC?G: + description: Capture/compare %s generation diff --git a/devices/collect/tim/tim11_derive.yaml b/devices/collect/tim/tim11_derive.yaml new file mode 100644 index 000000000..0429408cc --- /dev/null +++ b/devices/collect/tim/tim11_derive.yaml @@ -0,0 +1,12 @@ +_derive: + CR1: TIM10.CR1 + DIER: TIM10.DIER + SR: TIM10.SR + EGR: TIM10.EGR + CCMR1_Output: TIM10.CCMR1_Output + CCMR1_Input: TIM10.CCMR1_Input + CCER: TIM10.CCER + CNT: TIM10.CNT + PSC: TIM10.PSC + ARR: TIM10.ARR + CCR%s: TIM10.CCR%s diff --git a/devices/collect/tim/tim14_derive.yaml b/devices/collect/tim/tim14_derive.yaml new file mode 100644 index 000000000..b699cf4e2 --- /dev/null +++ b/devices/collect/tim/tim14_derive.yaml @@ -0,0 +1,12 @@ +_derive: + CR1: TIM13.CR1 + DIER: TIM13.DIER + SR: TIM13.SR + EGR: TIM13.EGR + CCMR1_Output: TIM13.CCMR1_Output + CCMR1_Input: TIM13.CCMR1_Input + CCER: TIM13.CCER + CNT: TIM13.CNT + PSC: TIM13.PSC + ARR: TIM13.ARR + CCR%s: TIM13.CCR%s diff --git a/devices/collect/tim/tim17_derive.yaml b/devices/collect/tim/tim17_derive.yaml new file mode 100644 index 000000000..1a1cdbe39 --- /dev/null +++ b/devices/collect/tim/tim17_derive.yaml @@ -0,0 +1,18 @@ +_derive: + CR1: TIM16.CR1 + CR2: TIM16.CR2 + DIER: TIM16.DIER + SR: TIM16.SR + EGR: TIM16.EGR + CCMR1_Output: TIM16.CCMR1_Output + CCMR1_Input: TIM16.CCMR1_Input + CCER: TIM16.CCER + CNT: TIM16.CNT + PSC: TIM16.PSC + ARR: TIM16.ARR + RCR: TIM16.RCR + CCR%s: TIM16.CCR%s + BDTR: TIM16.BDTR + "?~DTR2": TIM16.DTR2 + DCR: TIM16.DCR + DMAR: TIM16.DMAR diff --git a/devices/collect/tim/tim22_derive.yaml b/devices/collect/tim/tim22_derive.yaml new file mode 100644 index 000000000..dde95a687 --- /dev/null +++ b/devices/collect/tim/tim22_derive.yaml @@ -0,0 +1,22 @@ +_derive: + CR1: TIM21.CR1 + CR2: TIM21.CR2 + DIER: TIM21.DIER + SR: TIM21.SR + EGR: TIM21.EGR + CCMR1_Output: TIM21.CCMR1_Output + CCMR1_Input: TIM21.CCMR1_Input + CCER: TIM21.CCER + CNT: TIM21.CNT + PSC: TIM21.PSC + ARR: TIM21.ARR + CCR%s: TIM21.CCR%s + +SMCR: + _derive: + MSM: TIM21.SMCR.MSM + ETF: TIM21.SMCR.ETF + ETPS: TIM21.SMCR.ETPS + ECE: TIM21.SMCR.ECE + ETP: TIM21.SMCR.ETP + SMS: TIM21.SMCR.SMS diff --git a/devices/collect/tim/tim4_derive.yaml b/devices/collect/tim/tim4_derive.yaml new file mode 100644 index 000000000..d729d13ae --- /dev/null +++ b/devices/collect/tim/tim4_derive.yaml @@ -0,0 +1,31 @@ +_derive: + CR1: TIM3.CR1 + CR2: TIM3.CR2 + DIER: TIM3.DIER + SR: TIM3.SR + EGR: TIM3.EGR + CCMR1_Output: TIM3.CCMR1_Output + CCMR1_Input: TIM3.CCMR1_Input + CCMR2_Output: TIM3.CCMR2_Output + CCMR2_Input: TIM3.CCMR2_Input + CCER: TIM3.CCER + CNT: TIM3.CNT + PSC: TIM3.PSC + ARR: TIM3.ARR + CCR%s: TIM3.CCR%s + DCR: TIM3.DCR + DMAR: TIM3.DMAR + "?~ECR": TIM3.ECR + +SMCR: + _derive: + "?~OCCS": TIM3.SMCR.OCCS + MSM: TIM3.SMCR.MSM + ETF: TIM3.SMCR.ETF + ETPS: TIM3.SMCR.ETPS + ECE: TIM3.SMCR.ECE + ETP: TIM3.SMCR.ETP + "?~SMSPE": TIM3.SMCR.SMSPE + "?~SMSPS": TIM3.SMCR.SMSPS + SMS: TIM3.SMCR.SMS + "?~SMS_3": TIM3.SMCR.SMS_3 diff --git a/devices/collect/tim/tim5_derive.yaml b/devices/collect/tim/tim5_derive.yaml new file mode 100644 index 000000000..c22eb457c --- /dev/null +++ b/devices/collect/tim/tim5_derive.yaml @@ -0,0 +1,31 @@ +_derive: + CR1: TIM2.CR1 + CR2: TIM2.CR2 + DIER: TIM2.DIER + SR: TIM2.SR + EGR: TIM2.EGR + CCMR1_Output: TIM2.CCMR1_Output + CCMR1_Input: TIM2.CCMR1_Input + CCMR2_Output: TIM2.CCMR2_Output + CCMR2_Input: TIM2.CCMR2_Input + CCER: TIM2.CCER + CNT: TIM2.CNT + PSC: TIM2.PSC + ARR: TIM2.ARR + CCR%s: TIM2.CCR%s + DCR: TIM2.DCR + DMAR: TIM2.DMAR + "?~ECR": TIM2.ECR + +SMCR: + _derive: + "?~OCCS": TIM2.SMCR.OCCS + MSM: TIM2.SMCR.MSM + ETF: TIM2.SMCR.ETF + ETPS: TIM2.SMCR.ETPS + ECE: TIM2.SMCR.ECE + ETP: TIM2.SMCR.ETP + "?~SMSPE": TIM2.SMCR.SMSPE + "?~SMSPS": TIM2.SMCR.SMSPS + SMS: TIM2.SMCR.SMS + "?~SMS_3": TIM2.SMCR.SMS_3 diff --git a/devices/collect/tim/tim8_derive.yaml b/devices/collect/tim/tim8_derive.yaml new file mode 100644 index 000000000..3942bb052 --- /dev/null +++ b/devices/collect/tim/tim8_derive.yaml @@ -0,0 +1,37 @@ +_derive: + CR1: TIM1.CR1 + CR2: TIM1.CR2 + DIER: TIM1.DIER + SR: TIM1.SR + EGR: TIM1.EGR + CCMR1_Output: TIM1.CCMR1_Output + CCMR1_Input: TIM1.CCMR1_Input + CCMR2_Output: TIM1.CCMR2_Output + CCMR2_Input: TIM1.CCMR2_Input + CCER: TIM1.CCER + CNT: TIM1.CNT + PSC: TIM1.PSC + ARR: TIM1.ARR + RCR: TIM1.RCR + CCR%s: TIM1.CCR%s + BDTR: TIM1.BDTR + DCR: TIM1.DCR + DMAR: TIM1.DMAR + CCMR3_Output: TIM1.CCMR3_Output + "?~DTR2": TIM1.DTR2 + "?~ECR": TIM1.ECR + CCR5: TIM1.CCR5 + CCR6: TIM1.CCR6 + +SMCR: + _derive: + "?~OCCS": TIM1.SMCR.OCCS + MSM: TIM1.SMCR.MSM + ETF: TIM1.SMCR.ETF + ETPS: TIM1.SMCR.ETPS + ECE: TIM1.SMCR.ECE + ETP: TIM1.SMCR.ETP + "?~SMSPE": TIM1.SMCR.SMSPE + "?~SMSPS": TIM1.SMCR.SMSPS + SMS: TIM1.SMCR.SMS + "?~SMS_3": TIM1.SMCR.SMS_3 diff --git a/devices/collect/tsc/iogcr.yaml b/devices/collect/tsc/iogcr.yaml new file mode 100644 index 000000000..3a84cd0d5 --- /dev/null +++ b/devices/collect/tsc/iogcr.yaml @@ -0,0 +1,14 @@ +_array: + IOG?CR: {} + +"IO[HSC]CR,IOASCR": + _array: + G?_IO1: {} + G?_IO2: {} + G?_IO3: {} + G?_IO4: {} + +IOGCSR: + _array: + G?E: {} + G?S: {} diff --git a/devices/collect/usart/v1_v2_derive.yaml b/devices/collect/usart/v1_v2_derive.yaml new file mode 100644 index 000000000..6f40412ef --- /dev/null +++ b/devices/collect/usart/v1_v2_derive.yaml @@ -0,0 +1,34 @@ +_derive: + DR: USART1.DR + BRR: USART1.BRR + CR1: USART1.CR1 +SR: + _derive: + PE: USART1.SR.PE + FE: USART1.SR.FE + "?~NF": USART1.SR.NF + "?~NE": USART1.SR.NE + ORE: USART1.SR.ORE + IDLE: USART1.SR.IDLE + RXNE: USART1.SR.RXNE + TC: USART1.SR.TC + TXE: USART1.SR.TXE + LBD: USART1.SR.LBD +CR2: + _derive: + ADD: USART1.CR2.ADD + LBDL: USART1.CR2.LBDL + LBDIE: USART1.CR2.LBDIE + LINEN: USART1.CR2.LINEN +CR3: + _derive: + EIE: USART1.CR3.EIE + IREN: USART1.CR3.IREN + IRLP: USART1.CR3.IRLP + HDSEL: USART1.CR3.HDSEL + DMAR: USART1.CR3.DMAR + DMAT: USART1.CR3.DMAT + "?~ONEBIT": USART1.CR3.ONEBIT +GTPR: + _derive: + PSC: USART1.GTPR.PSC diff --git a/devices/collect/usb/chepr.yaml b/devices/collect/usb/chepr.yaml new file mode 100644 index 000000000..4caf024f5 --- /dev/null +++ b/devices/collect/usb/chepr.yaml @@ -0,0 +1,2 @@ +_array: + CHEP?R: {} diff --git a/devices/collect/usb/epxr.yaml b/devices/collect/usb/epxr.yaml new file mode 100644 index 000000000..8370b5187 --- /dev/null +++ b/devices/collect/usb/epxr.yaml @@ -0,0 +1,2 @@ +_array: + EP?R: {} diff --git a/devices/collect/usb_otg/fs_device.yaml b/devices/collect/usb_otg/fs_device.yaml new file mode 100644 index 000000000..0bb06ea89 --- /dev/null +++ b/devices/collect/usb_otg/fs_device.yaml @@ -0,0 +1,28 @@ +_cluster: + DIEP0: + description: Device IN endpoint 0 + DIEPCTL[0]: { name: CTL } + DIEPINT[0]: { name: INT } + DIEPTSIZ[0]: { name: TSIZ } + DTXFSTS[0]: { name: TXFSTS } + DIEP%s: + description: Device IN endpoint X + DIEPCTL[1-5]: { name: CTL } + DIEPINT[1-5]: { name: INT } + DIEPTSIZ[1-5]: { name: TSIZ } + DTXFSTS[1-5]: { name: TXFSTS } + _derive: + INT: DIEP0.INT + TXFSTS: DIEP0.TXFSTS + DOEP0: + description: Device OUT endpoint 0 + DOEPCTL[0]: { name: CTL } + DOEPINT[0]: { name: INT } + DOEPTSIZ[0]: { name: TSIZ } + DOEP%s: + description: Device IN endpoint X + DOEPCTL[1-5]: { name: CTL } + DOEPINT[1-5]: { name: INT } + DOEPTSIZ[1-5]: { name: TSIZ } + _derive: + INT: DOEP0.INT diff --git a/devices/collect/usb_otg/fs_global.yaml b/devices/collect/usb_otg/fs_global.yaml new file mode 100644 index 000000000..b8f841577 --- /dev/null +++ b/devices/collect/usb_otg/fs_global.yaml @@ -0,0 +1,4 @@ +_array: + DIEPTXF[1-5]: + displayName: DIEPTXF%s + description: OTG_FS device IN endpoint transmit FIFO size register diff --git a/devices/collect/usb_otg/fs_host.yaml b/devices/collect/usb_otg/fs_host.yaml new file mode 100644 index 000000000..ecdf45b3e --- /dev/null +++ b/devices/collect/usb_otg/fs_host.yaml @@ -0,0 +1,11 @@ +_cluster: + HC%s: + description: Host channel + HCCHAR?,HCCHAR??: + name: CHAR + HCINT?,HCINT??: + name: INT + HCINTMSK?,HCINTMSK??: + name: INTMSK + HCTSIZ?,HCTSIZ??: + name: TSIZ diff --git a/devices/collect/usb_otg/hs_device.yaml b/devices/collect/usb_otg/hs_device.yaml new file mode 100644 index 000000000..0c3c23299 --- /dev/null +++ b/devices/collect/usb_otg/hs_device.yaml @@ -0,0 +1,34 @@ +_cluster: + DIEP0: + description: Device IN endpoint 0 + DIEPCTL[0]: { name: CTL } + DIEPINT[0]: { name: INT } + DIEPTSIZ[0]: { name: TSIZ } + DIEPDMA[0]: { name: DMA } + DTXFSTS[0]: { name: TXFSTS } + DIEP%s: + description: Device IN endpoint X + DIEPCTL[1-8]: { name: CTL } + DIEPINT[1-8]: { name: INT } + DIEPTSIZ[1-8]: { name: TSIZ } + DIEPDMA[1-8]: { name: DMA } + DTXFSTS[1-8]: { name: TXFSTS } + _derive: + INT: DIEP0.INT + TXFSTS: DIEP0.TXFSTS + DMA: DIEP0.DMA + DOEP0: + description: Device OUT endpoint 0 + DOEPCTL[0]: { name: CTL } + DOEPINT[0]: { name: INT } + DOEPTSIZ[0]: { name: TSIZ } + DOEPDMA[0]: { name: DMA } + DOEP%s: + description: Device IN endpoint X + DOEPCTL[1-8]: { name: CTL } + DOEPINT[1-8]: { name: INT } + DOEPDMA[1-8]: { name: DMA } + DOEPTSIZ[1-8]: { name: TSIZ } + _derive: + INT: DIEP0.INT + DMA: DIEP0.DMA diff --git a/devices/collect/usb_otg/hs_global.yaml b/devices/collect/usb_otg/hs_global.yaml new file mode 100644 index 000000000..00fe0dc2d --- /dev/null +++ b/devices/collect/usb_otg/hs_global.yaml @@ -0,0 +1,4 @@ +_array: + DIEPTXF[1-8]: + displayName: DIEPTXF%s + description: OTG_HS device IN endpoint transmit FIFO size register diff --git a/devices/collect/usb_otg/hs_host.yaml b/devices/collect/usb_otg/hs_host.yaml new file mode 100644 index 000000000..4f739ab9d --- /dev/null +++ b/devices/collect/usb_otg/hs_host.yaml @@ -0,0 +1,15 @@ +_cluster: + HC%s: + description: Host channel + HCCHAR?,HCCHAR??: + name: CHAR + HCSPLT?,HCSPLT??: + name: SPLT + HCINT?,HCINT??: + name: INT + HCINTMSK?,HCINTMSK??: + name: INTMSK + HCTSIZ?,HCTSIZ??: + name: TSIZ + HCDMA?,HCDMA??: + name: DMA diff --git a/devices/common_patches/bkp/bkp.yaml b/devices/common_patches/bkp/bkp.yaml deleted file mode 100644 index 7b8801ba2..000000000 --- a/devices/common_patches/bkp/bkp.yaml +++ /dev/null @@ -1,19 +0,0 @@ -_modify: - BKP: - baseAddress: "0x40006C04" - -BKP: - _array: - "DR[1-9],DR1[0]": - _start_from_zero: True - _modify: - D1: - name: D - D: [0, 0xFFFF] - "DR[1][1-9],DR[234][0-9]": - name: BKP_DR%s - _start_from_zero: True - _modify: - DR11: - name: D - D: [0, 0xFFFF] diff --git a/devices/common_patches/can/can.yaml b/devices/common_patches/can/can.yaml deleted file mode 100644 index e6ac77b03..000000000 --- a/devices/common_patches/can/can.yaml +++ /dev/null @@ -1,25 +0,0 @@ -"CAN,CAN?": - _cluster: - "TX%s": - description: "CAN Transmit cluster" - "TI?R": {} - "TDT?R": {} - "TDL?R": {} - "TDH?R": {} - "RX%s": - description: "CAN Receive cluster" - "RI?R": {} - "RDT?R": {} - "RDL?R": {} - "RDH?R": {} - _array: - "RF?R": - _modify: - RFOM0: - name: RFOM - FOVR0: - name: FOVR - FULL0: - name: FULL - FMP0: - name: FMP diff --git a/devices/common_patches/can/can_filter_bank.yaml b/devices/common_patches/can/can_filter_bank.yaml deleted file mode 100644 index 90b84d7fb..000000000 --- a/devices/common_patches/can/can_filter_bank.yaml +++ /dev/null @@ -1,6 +0,0 @@ -"CAN,CAN1": - _cluster: - "FB%s": - description: "CAN Filter Bank cluster" - "F*R1": {} - "F*R2": {} diff --git a/devices/common_patches/can/can_remove_prefix.yaml b/devices/common_patches/can/can_remove_prefix.yaml deleted file mode 100644 index 63d9c101b..000000000 --- a/devices/common_patches/can/can_remove_prefix.yaml +++ /dev/null @@ -1,3 +0,0 @@ -"CAN,CAN?": - _strip: - - CAN_ diff --git a/devices/common_patches/crc/crc_rename_init.yaml b/devices/common_patches/crc/crc_rename_init.yaml deleted file mode 100644 index 80edcea1d..000000000 --- a/devices/common_patches/crc/crc_rename_init.yaml +++ /dev/null @@ -1,5 +0,0 @@ -CRC: - INIT: - _modify: - CRC_INIT: - name: INIT diff --git a/devices/common_patches/cryp/cryp_v1.yaml b/devices/common_patches/cryp/cryp_v1.yaml deleted file mode 100644 index 2bcb9bf29..000000000 --- a/devices/common_patches/cryp/cryp_v1.yaml +++ /dev/null @@ -1,8 +0,0 @@ -CRYP: - _cluster: - "KEY%s": - "K?LR": {} - "K?RR": {} - "INIT%s": - "IV?LR": {} - "IV?RR": {} diff --git a/devices/common_patches/cryp/cryp_v2.yaml b/devices/common_patches/cryp/cryp_v2.yaml deleted file mode 100644 index 5a4b89a0d..000000000 --- a/devices/common_patches/cryp/cryp_v2.yaml +++ /dev/null @@ -1,13 +0,0 @@ -_include: - - ./cryp_v1.yaml - -CRYP: - _array: - "CSGCMCCM?R": - _modify: - CSGCMCCMR0R: - name: CSGCMCCMR - "CSGCM?R": - _modify: - CSGCM0R: - name: CSGCMR diff --git a/devices/common_patches/cryp/l0_aes.yaml b/devices/common_patches/cryp/l0_aes.yaml deleted file mode 100644 index 051841cb4..000000000 --- a/devices/common_patches/cryp/l0_aes.yaml +++ /dev/null @@ -1,43 +0,0 @@ -# Removes the AES_ prefix from all fields in the registers - -AES: - DINR: - _modify: - AES_DINR: - name: DIN - DOUTR: - _modify: - AES_DOUTR: - name: DOUT - KEYR0: - _modify: - AES_KEYR0: - name: KEY0 - KEYR1: - _modify: - AES_KEYR1: - name: KEY1 - KEYR2: - _modify: - AES_KEYR2: - name: KEY2 - KEYR3: - _modify: - AES_KEYR3: - name: KEY3 - IVR0: - _modify: - AES_IVR0: - name: IV0 - IVR1: - _modify: - AES_IVR1: - name: IV1 - IVR2: - _modify: - AES_IVR2: - name: IV2 - IVR3: - _modify: - AES_IVR3: - name: IV3 diff --git a/devices/common_patches/dbgmcu.yaml b/devices/common_patches/dbgmcu.yaml deleted file mode 100644 index a59b8524c..000000000 --- a/devices/common_patches/dbgmcu.yaml +++ /dev/null @@ -1,10 +0,0 @@ -_include: - - dbgmcu_rename.yaml - -DBGMCU: - _strip: - - DBGMCU_ - APB1_FZ: - _modify: - DBG_IWDEG_STOP: - name: DBG_IWDG_STOP diff --git a/devices/common_patches/dfsdm/dfsdm_v1.yaml b/devices/common_patches/dfsdm/dfsdm_v1.yaml deleted file mode 100644 index 9cf14e90c..000000000 --- a/devices/common_patches/dfsdm/dfsdm_v1.yaml +++ /dev/null @@ -1,59 +0,0 @@ -"DFSDM,DFSDM[12]": - CH[1234567]CFGR1: - _add: - DFSDMEN: - description: DFSDMEN - bitOffset: 31 - bitWidth: 1 - CKOUTSRC: - description: CKOUTSRC - bitOffset: 30 - bitWidth: 1 - CKOUTDIV: - description: CKOUTDIV - bitOffset: 16 - bitWidth: 8 - _cluster: - "CH%s": - description: "DFSDM Channel cluster: contains CH?CFGR1, CH?CFGR2, CH?AWSCDR, CH?WDATR and CH?DATINR registers" - "CH?CFGR1": - name: CFGR1 - "CH?CFGR2": - name: CFGR2 - "CH?AWSCDR": - name: AWSCDR - "CH?WDATR": - name: WDATR - "CH?DATINR": - name: DATINR - "FLT%s": - "FLT?CR1": - name: CR1 - "FLT?CR2": - name: CR2 - "FLT?ISR": - name: ISR - "FLT?ICR": - name: ICR - "FLT?JCHGR": - name: JCHGR - "FLT?FCR": - name: FCR - "FLT?JDATAR": - name: JDATAR - "FLT?RDATAR": - name: RDATAR - "FLT?AWHTR": - name: AWHTR - "FLT?AWLTR": - name: AWLTR - "FLT?AWSR": - name: AWSR - "FLT?AWCFR": - name: AWCFR - "FLT?EXMAX": - name: EXMAX - "FLT?EXMIN": - name: EXMIN - "FLT?CNVTIMR": - name: CNVTIMR diff --git a/devices/common_patches/dfsdm/dfsdm_v2.yaml b/devices/common_patches/dfsdm/dfsdm_v2.yaml deleted file mode 100644 index 9b78ad20e..000000000 --- a/devices/common_patches/dfsdm/dfsdm_v2.yaml +++ /dev/null @@ -1,58 +0,0 @@ -"DFSDM,DFSDM1": - CHCFG[1234567]R1: - _add: - DFSDMEN: - description: DFSDMEN - bitOffset: 31 - bitWidth: 1 - CKOUTSRC: - description: CKOUTSRC - bitOffset: 30 - bitWidth: 1 - CKOUTDIV: - description: CKOUTDIV - bitOffset: 16 - bitWidth: 8 - _cluster: - "CH%s": - description: "DFSDM Channel cluster: contains CHCFG?R1, CHCFG?R2, CHAWSCD?R, CHWDAT?R and CHDATIN?R registers" - "CHCFG?R1": - name: CFGR1 - "CHCFG?R2": - name: CFGR2 - "AWSCD?R": {} - "CHWDAT?R": - name: WDATR - "CHDATIN?R": - name: DATINR - "FLT%s": - "DFSDM?_CR1": - name: CR1 - "DFSDM?_CR1": - name: CR2 - "DFSDM?_ISR": - name: ISR - "DFSDM?_ICR": - name: ICR - "DFSDM?_JCHGR": - name: JCHGR - "DFSDM?_FCR": - name: FCR - "DFSDM?_JDATAR": - name: JDATAR - "DFSDM?_RDATAR": - name: RDATAR - "DFSDM?_AWHTR": - name: AWHTR - "DFSDM?_AWLTR": - name: AWLTR - "DFSDM?_AWSR": - name: AWSR - "DFSDM?_AWCFR": - name: AWCFR - "DFSDM?_EXMAX": - name: EXMAX - "DFSDM?_EXMIN": - name: EXMIN - "DFSDM?_CNVTIMR": - name: CNVTIMR diff --git a/devices/common_patches/dma/bdma.yaml b/devices/common_patches/dma/bdma.yaml deleted file mode 100644 index bbe42a96d..000000000 --- a/devices/common_patches/dma/bdma.yaml +++ /dev/null @@ -1,170 +0,0 @@ -"BDMA*": - _add: - CM1AR0: - description: Channel x memory 1 address register - addressOffset: 0x18 - access: read-write - resetValue: 0x00000000 - fields: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - CM1AR1: - description: Channel x memory 1 address register - addressOffset: 0x2C - access: read-write - resetValue: 0x00000000 - fields: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - CM1AR2: - description: Channel x memory 1 address register - addressOffset: 0x40 - access: read-write - resetValue: 0x00000000 - fields: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - CM1AR3: - description: Channel x memory 1 address register - addressOffset: 0x54 - access: read-write - resetValue: 0x00000000 - fields: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - CM1AR4: - description: Channel x memory 1 address register - addressOffset: 0x68 - access: read-write - resetValue: 0x00000000 - fields: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - CM1AR5: - description: Channel x memory 1 address register - addressOffset: 0x7C - access: read-write - resetValue: 0x00000000 - fields: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - CM1AR6: - description: Channel x memory 1 address register - addressOffset: 0x90 - access: read-write - resetValue: 0x00000000 - fields: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - CM1AR7: - description: Channel x memory 1 address register - addressOffset: 0xA4 - access: read-write - resetValue: 0x00000000 - fields: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - _modify: - CMAR1: - name: CM0AR0 - CMAR2: - name: CM0AR1 - CMAR3: - name: CM0AR2 - CMAR4: - name: CM0AR3 - CMAR5: - name: CM0AR4 - CMAR6: - name: CM0AR5 - CMAR7: - name: CM0AR6 - CMAR8: - name: CM0AR7 - CCR1: - name: CCR0 - CCR2: - name: CCR1 - CCR3: - name: CCR2 - CCR4: - name: CCR3 - CCR5: - name: CCR4 - CCR6: - name: CCR5 - CCR7: - name: CCR6 - CCR8: - name: CCR7 - CNDTR1: - name: CNDTR0 - CNDTR2: - name: CNDTR1 - CNDTR3: - name: CNDTR2 - CNDTR4: - name: CNDTR3 - CNDTR5: - name: CNDTR4 - CNDTR6: - name: CNDTR5 - CNDTR7: - name: CNDTR6 - CNDTR8: - name: CNDTR7 - CPAR1: - name: CPAR0 - CPAR2: - name: CPAR1 - CPAR3: - name: CPAR2 - CPAR4: - name: CPAR3 - CPAR5: - name: CPAR4 - CPAR6: - name: CPAR5 - CPAR7: - name: CPAR6 - CPAR8: - name: CPAR7 - "CCR?": - _add: - CT: - description: Current target memory in double-buffer mode - bitOffset: 16 - bitWidth: 1 - DBM: - description: Double-buffer mode - bitOffset: 15 - bitWidth: 1 - _cluster: - "CH%s": - description: "Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR? registers" - "CCR?": - name: CR - "CNDTR?": - name: NDTR - "CPAR?": - name: PAR - "CM0AR?": - name: M0AR - "CM1AR?": - name: M1AR diff --git a/devices/common_patches/dma/bdma_v2.yaml b/devices/common_patches/dma/bdma_v2.yaml deleted file mode 100644 index 7cac6ed6c..000000000 --- a/devices/common_patches/dma/bdma_v2.yaml +++ /dev/null @@ -1,30 +0,0 @@ -"BDMA*": - "CCR?": - _add: - CT: - description: Current target memory in double-buffer mode - bitOffset: 16 - bitWidth: 1 - DBM: - description: Double-buffer mode - bitOffset: 15 - bitWidth: 1 - "CM1AR?": - _add: - MA: - description: Memory address - bitOffset: 0 - bitWidth: 32 - _cluster: - "CH%s": - description: "Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?" - "CCR?": - name: CR - "CNDTR?": - name: NDTR - "CPAR?": - name: PAR - "CM0AR?": - name: M0AR - "CM1AR?": - name: M1AR diff --git a/devices/common_patches/dma/dma2d_v2.yaml b/devices/common_patches/dma/dma2d_v2.yaml deleted file mode 100644 index 37b43698b..000000000 --- a/devices/common_patches/dma/dma2d_v2.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# "Chrom-Art Accelerator" 2D DMA engine -# Version 2 - -"DMA2D*": - "[FB]GOR,OOR": - _modify: - LO: - bitWidth: 16 - OPFCCR: - _add: - SB: - description: Swap Bytes - bitOffset: 8 - bitWidth: 1 diff --git a/devices/common_patches/dma/dma_v1.yaml b/devices/common_patches/dma/dma_v1.yaml deleted file mode 100644 index fd9d3612c..000000000 --- a/devices/common_patches/dma/dma_v1.yaml +++ /dev/null @@ -1,12 +0,0 @@ -"DMA[12]": - _cluster: - "CH%s": - description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" - "CCR?": - name: CR - "CNDTR?": - name: NDTR - "CPAR?": - name: PAR - "CMAR?": - name: MAR diff --git a/devices/common_patches/dma/dma_v2.yaml b/devices/common_patches/dma/dma_v2.yaml deleted file mode 100644 index 51090d7a8..000000000 --- a/devices/common_patches/dma/dma_v2.yaml +++ /dev/null @@ -1,8 +0,0 @@ -_include: - - dma_v3.yaml - -"DMA?": - S?CR: - _modify: - CHSEL: - bitWidth: 3 diff --git a/devices/common_patches/dma/dma_v21.yaml b/devices/common_patches/dma/dma_v21.yaml deleted file mode 100644 index 6ca62c8c6..000000000 --- a/devices/common_patches/dma/dma_v21.yaml +++ /dev/null @@ -1,8 +0,0 @@ -_include: - - dma_v3.yaml - -"DMA?": - S?CR: - _modify: - CHSEL: - bitWidth: 4 diff --git a/devices/common_patches/dma/dma_v3.yaml b/devices/common_patches/dma/dma_v3.yaml deleted file mode 100644 index 1433cc3b0..000000000 --- a/devices/common_patches/dma/dma_v3.yaml +++ /dev/null @@ -1,19 +0,0 @@ -"DMA?": - S?CR: - _delete: - - ACK - _cluster: - "ST%s": - description: "Stream cluster: S?CR, S?NDTR, S?M0AR, S?M1AR and S?FCR registers" - "S?CR": - name: CR - "S?NDTR": - name: NDTR - "S?PAR": - name: PAR - "S?M0AR": - name: M0AR - "S?M1AR": - name: M1AR - "S?FCR": - name: FCR diff --git a/devices/common_patches/dma_fcr_wo.yaml b/devices/common_patches/dma_fcr_wo.yaml deleted file mode 100644 index 84489501c..000000000 --- a/devices/common_patches/dma_fcr_wo.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Many devices have these flag clear registers incorrectly set to read-write - -"DMA?": - _modify: - "[LH]IFCR": - access: write-only diff --git a/devices/common_patches/ethernet_mac_regs.yaml b/devices/common_patches/ethernet_mac_regs.yaml deleted file mode 100644 index efcd89b8f..000000000 --- a/devices/common_patches/ethernet_mac_regs.yaml +++ /dev/null @@ -1,57 +0,0 @@ -Ethernet_MAC: - MACMIIDR: - _modify: - TD: - name: MD - MACDBGR: - _delete: - - "*" - _add: - TFF: - description: Tx FIFO full - bitOffset: 25 - bitWidth: 1 - TFNE: - description: Tx FIFO not empty - bitOffset: 24 - bitWidth: 1 - TFWA: - description: Tx FIFO write active - bitOffset: 22 - bitWidth: 1 - TFRS: - description: Tx FIFO read status - bitOffset: 20 - bitWidth: 2 - MTP: - description: MAC transmitter in pause - bitOffset: 19 - bitWidth: 1 - MTFCS: - description: MAC transmit frame controller status - bitOffset: 17 - bitWidth: 2 - MMTEA: - description: MAC MII transmit engine active - bitOffset: 16 - bitWidth: 1 - RFFL: - description: Rx FIFO fill level - bitOffset: 8 - bitWidth: 2 - RFRCS: - description: Rx FIFO read controller status - bitOffset: 5 - bitWidth: 2 - RFWRA: - description: Rx FIFO write controller active - bitOffset: 4 - bitWidth: 1 - MSFRWCS: - description: MAC small FIFO read/write controllers status - bitOffset: 1 - bitWidth: 2 - MMRPEA: - description: MAC MII receive protocol engine active - bitOffset: 0 - bitWidth: 1 diff --git a/devices/common_patches/f0_adc_cfgr2_ckmode.yaml b/devices/common_patches/f0_adc_cfgr2_ckmode.yaml deleted file mode 100644 index 80d2dc067..000000000 --- a/devices/common_patches/f0_adc_cfgr2_ckmode.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Merge together ADC CFGR2 separated JITOFF_Dx fields -# and properly rename to CKMODE - -"ADC": - CFGR2: - _modify: - JITOFF_D2: - name: CKMODE0 - JITOFF_D4: - name: CKMODE1 - description: "ADC clock mode" - _merge: - - "CKMODE*" diff --git a/devices/common_patches/f0_adc_fixes.yaml b/devices/common_patches/f0_adc_fixes.yaml deleted file mode 100644 index d8528213d..000000000 --- a/devices/common_patches/f0_adc_fixes.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# Renames a few fields in the F0 ADC and adds the WAIT file which was missed - -ADC: - ISR: - _modify: - EOS: - name: "EOSEQ" - IER: - _modify: - EOSIE: - name: "EOSEQIE" - CFGR1: - _add: - WAIT: - bitOffset: 14 - bitWidth: 1 - description: "Wait conversion mode" - SMPR: - _modify: - SMPR: - name: "SMP" diff --git a/devices/common_patches/f0_comp_common.yaml b/devices/common_patches/f0_comp_common.yaml deleted file mode 100644 index e0dd553f0..000000000 --- a/devices/common_patches/f0_comp_common.yaml +++ /dev/null @@ -1,100 +0,0 @@ -_add: - COMP: - description: "General purpose comparators" - baseAddress: 0x40010000 - addressBlock: - offset: 0 - size: 0x400 - usage: registers - registers: - CSR: - description: control and status register - addressOffset: 0x1C - size: 0x20 - resetValue: 0x00000000 - fields: - COMP1EN: - description: Comparator 1 enable - bitOffset: 0 - bitWidth: 1 - access: read-write - COMP1MODE: - description: Comparator 1 mode - bitOffset: 2 - bitWidth: 2 - access: read-write - COMP1INSEL: - description: Comparator 1 inverting input selection - bitOffset: 4 - bitWidth: 3 - access: read-write - COMP1OUTSEL: - description: Comparator 1 output selection - bitOffset: 8 - bitWidth: 3 - access: read-write - COMP1POL: - description: Comparator 1 output polarity - bitOffset: 11 - bitWidth: 1 - access: read-write - COMP1HYST: - description: Comparator 1 hysteresis - bitOffset: 12 - bitWidth: 2 - access: read-write - COMP1OUT: - description: Comparator 1 output - bitOffset: 14 - bitWidth: 1 - access: read-only - COMP1LOCK: - description: Comparator 1 lock - bitOffset: 15 - bitWidth: 1 - access: read-write - COMP2EN: - description: Comparator 2 enable - bitOffset: 16 - bitWidth: 1 - access: read-write - COMP2MODE: - description: Comparator 2 mode - bitOffset: 18 - bitWidth: 2 - access: read-write - COMP2INSEL: - description: Comparator 2 inverting input selection - bitOffset: 20 - bitWidth: 3 - access: read-write - WNDWEN: - description: Window mode enable - bitOffset: 23 - bitWidth: 1 - access: read-write - COMP2OUTSEL: - description: Comparator 2 output selection - bitOffset: 24 - bitWidth: 3 - access: read-write - COMP2POL: - description: Comparator 2 output polarity - bitOffset: 27 - bitWidth: 1 - access: read-write - COMP2HYST: - description: Comparator 2 hysteresis - bitOffset: 28 - bitWidth: 2 - access: read-write - COMP2OUT: - description: Comparator 2 output - bitOffset: 30 - bitWidth: 1 - access: read-only - COMP2LOCK: - description: Comparator 2 lock - bitOffset: 31 - bitWidth: 1 - access: read-write diff --git a/devices/common_patches/f0_crc_init_addr_fix.yaml b/devices/common_patches/f0_crc_init_addr_fix.yaml deleted file mode 100644 index 769abb832..000000000 --- a/devices/common_patches/f0_crc_init_addr_fix.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Corrects the address of the INIT register of the CRC peripheral - -CRC: - _modify: - INIT: - addressOffset: "0x10" diff --git a/devices/common_patches/f0_dmaen.yaml b/devices/common_patches/f0_dmaen.yaml deleted file mode 100644 index 46011b4ad..000000000 --- a/devices/common_patches/f0_dmaen.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - AHBENR: - _add: - DMAEN: - description: DMA clock enable - bitOffset: 0 - bitWidth: 1 diff --git a/devices/common_patches/f0_gpioe.yaml b/devices/common_patches/f0_gpioe.yaml deleted file mode 100644 index b0f78ff69..000000000 --- a/devices/common_patches/f0_gpioe.yaml +++ /dev/null @@ -1,13 +0,0 @@ -RCC: - AHBENR: - _add: - IOPEEN: - description: "I/O port E clock enable" - bitOffset: 21 - bitWidth: 1 - AHBRSTR: - _add: - IOPERST: - description: "I/O port E reset" - bitOffset: 21 - bitWidth: 1 diff --git a/devices/common_patches/f0_hsi48cal.yaml b/devices/common_patches/f0_hsi48cal.yaml deleted file mode 100644 index dcde99f86..000000000 --- a/devices/common_patches/f0_hsi48cal.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CR2: - _modify: - HSI48CAL: - bitWidth: 8 diff --git a/devices/common_patches/f0_no_hdmi_cec.yaml b/devices/common_patches/f0_no_hdmi_cec.yaml deleted file mode 100644 index b56f90372..000000000 --- a/devices/common_patches/f0_no_hdmi_cec.yaml +++ /dev/null @@ -1,4 +0,0 @@ -RCC: - CFGR3: - _delete: - - CECSW diff --git a/devices/common_patches/f0_ram_parity_check.yaml b/devices/common_patches/f0_ram_parity_check.yaml deleted file mode 100644 index 3c8cf96ec..000000000 --- a/devices/common_patches/f0_ram_parity_check.yaml +++ /dev/null @@ -1,5 +0,0 @@ -"Flash": - OBR: - _modify: - RAM_PARITY_CHECK_: - name: "RAM_PARITY_CHECK" diff --git a/devices/common_patches/f0_syscfg.yaml b/devices/common_patches/f0_syscfg.yaml deleted file mode 100644 index f3c45b0b8..000000000 --- a/devices/common_patches/f0_syscfg.yaml +++ /dev/null @@ -1,16 +0,0 @@ -SYSCFG: - CFGR1: - _delete: - - I2C2_FM_plus - - SPI2_DMA_RMP - - USART2_DMA_RMP - - I2C1_DMA_RMP - - TIM1_DMA_RMP - - TIM2_DMA_RMP - - TIM3_DMA_RMP - CFGR2: - _delete: - - PVD_LOCK - -_include: - - ./f0_syscfg_common.yaml diff --git a/devices/common_patches/f0_syscfg_common.yaml b/devices/common_patches/f0_syscfg_common.yaml deleted file mode 100644 index ae96c8588..000000000 --- a/devices/common_patches/f0_syscfg_common.yaml +++ /dev/null @@ -1,30 +0,0 @@ -SYSCFG: - CFGR1: - _add: - PA11_PA12_RMP: - description: "PA11 and PA12 remapping bit for small packages (28 and 20 pins)" - bitOffset: 4 - bitWidth: 1 - I2C_PA9_FMP: - description: "Fast Mode Plus (FM+) driving capability activation bits" - bitOffset: 22 - bitWidth: 1 - I2C_PA10_FMP: - description: "Fast Mode Plus (FM+) driving capability activation bits" - bitOffset: 23 - bitWidth: 1 - _modify: - I2C_PB6_FM: - name: I2C_PB6_FMP - I2C_PB7_FM: - name: I2C_PB7_FMP - I2C_PB8_FM: - name: I2C_PB8_FMP - I2C_PB9_FM: - name: I2C_PB9_FMP - I2C1_FM_plus: - name: I2C1_FMP - CFGR2: - _modify: - LOCUP_LOCK: - name: LOCKUP_LOCK diff --git a/devices/common_patches/f0_syscfg_comp.yaml b/devices/common_patches/f0_syscfg_comp.yaml deleted file mode 100644 index fd412c25d..000000000 --- a/devices/common_patches/f0_syscfg_comp.yaml +++ /dev/null @@ -1,39 +0,0 @@ -_modify: - SYSCFG_COMP: - name: SYSCFG - -SYSCFG: - _strip: - SYSCFG_ - _delete: - - COMP_CSR - CFGR1: - _add: - IR_MOD: - description: "IR Modulation Envelope signal selection" - bitOffset: 6 - bitWidth: 2 - TIM16_DMA_RMP2: - description: "TIM16 alternate DMA request remapping bit" - bitOffset: 13 - bitWidth: 1 - TIM17_DMA_RMP2: - description: "TIM17 alternate DMA request remapping bit" - bitOffset: 14 - bitWidth: 1 - _modify: - I2C2_FM_plus: - name: I2C2_FMP - -_include: - - ./f0_syscfg_common.yaml - - ./f0_comp_common.yaml - -COMP: - CSR: - _add: - COMP1SW1: - description: Comparator 1 non inverting input DAC switch - bitOffset: 1 - bitWidth: 1 - access: read-write diff --git a/devices/common_patches/f0_usart3.yaml b/devices/common_patches/f0_usart3.yaml deleted file mode 100644 index 4a86b5bb7..000000000 --- a/devices/common_patches/f0_usart3.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - CFGR3: - _add: - USART3SW: - description: "USART3 clock source" - bitOffset: 18 - bitWidth: 2 diff --git a/devices/common_patches/f0_usart6.yaml b/devices/common_patches/f0_usart6.yaml deleted file mode 100644 index b04efa0f2..000000000 --- a/devices/common_patches/f0_usart6.yaml +++ /dev/null @@ -1,15 +0,0 @@ -RCC: - APB2RSTR: - _add: - USART6RST: - description: "USART6 reset" - bitOffset: 5 - bitWidth: 1 - APB2ENR: - _delete: - - USART6EN - _add: - USART6EN: - description: "USART6 clock enable" - bitOffset: 5 - bitWidth: 1 diff --git a/devices/common_patches/f0_usart78.yaml b/devices/common_patches/f0_usart78.yaml deleted file mode 100644 index fa73b36d5..000000000 --- a/devices/common_patches/f0_usart78.yaml +++ /dev/null @@ -1,24 +0,0 @@ -RCC: - APB2RSTR: - _add: - USART8RST: - description: "USART8 reset" - bitOffset: 7 - bitWidth: 1 - USART7RST: - description: "USART7 reset" - bitOffset: 6 - bitWidth: 1 - APB2ENR: - _delete: - - USART8EN - - USART7EN - _add: - USART8EN: - description: "USART8 clock enable" - bitOffset: 7 - bitWidth: 1 - USART7EN: - description: "USART7 clock enable" - bitOffset: 6 - bitWidth: 1 diff --git a/devices/common_patches/f0_usben.yaml b/devices/common_patches/f0_usben.yaml deleted file mode 100644 index 235e87758..000000000 --- a/devices/common_patches/f0_usben.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - APB1ENR: - _modify: - USBRST: - name: "USBEN" diff --git a/devices/common_patches/f0_v18pwrrstf.yaml b/devices/common_patches/f0_v18pwrrstf.yaml deleted file mode 100644 index acef8f9d7..000000000 --- a/devices/common_patches/f0_v18pwrrstf.yaml +++ /dev/null @@ -1,8 +0,0 @@ -RCC: - CSR: - _add: - V18PWRRSTF: - description: "1.8 V domain reset flag" - bitOffset: 23 - bitWidth: 1 - access: read-write diff --git a/devices/common_patches/f1_ethernet.yaml b/devices/common_patches/f1_ethernet.yaml deleted file mode 100644 index 91ad5d3db..000000000 --- a/devices/common_patches/f1_ethernet.yaml +++ /dev/null @@ -1,22 +0,0 @@ -Ethernet_MAC: - MACMIIDR: - _modify: - TD: - name: MD - MACFCR: - _modify: - FCB_BPA: - name: FCB - MACA3LR: - _modify: - MBCA3L: - name: MACA3L - MACA2HR: - _modify: - ETH_MACA2HR: - name: MACA2H -Ethernet_DMA: - DMABMR: - _modify: - RTPR: - name: PM \ No newline at end of file diff --git a/devices/common_patches/f1_uart45.yaml b/devices/common_patches/f1_uart45.yaml deleted file mode 100644 index bb8d5897e..000000000 --- a/devices/common_patches/f1_uart45.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - APB1RSTR: - _modify: - USART5RST: - name: UART5RST - USART4RST: - name: UART4RST diff --git a/devices/common_patches/f2_rcc.yaml b/devices/common_patches/f2_rcc.yaml deleted file mode 100644 index 4e510ffc8..000000000 --- a/devices/common_patches/f2_rcc.yaml +++ /dev/null @@ -1,15 +0,0 @@ -RCC: - CFGR: - _merge: - - "MCO1[01]" - - "MCO1PRE[012]" - - "MCO2PRE[012]" - - "MCO2[01]" - - "RTCPRE[01234]" - - "PPRE2[012]" - - "PPRE1[0123]" - - "HPRE[0123]" - PLLI2SCFGR: - _merge: - - "PLLI2SR[012]" - - "PLLI2SN[012345678]" diff --git a/devices/common_patches/f3_adc.yaml b/devices/common_patches/f3_adc.yaml deleted file mode 100644 index 0b5a7a9e3..000000000 --- a/devices/common_patches/f3_adc.yaml +++ /dev/null @@ -1,24 +0,0 @@ -"ADC?": - SQR1: - _modify: - L3: - name: L - DIFSEL: - _merge: - - "DIFSEL*" - CFGR: - _delete: - - AUTOFF - _modify: - AWDCH1CH: - name: AWD1CH - CR: - _delete: - - DEEPPWD - _modify: - ADVREGEN: - bitWidth: 2 - DR: - _modify: - regularDATA: - name: RDATA diff --git a/devices/common_patches/f3_adc_multi_dual.yaml b/devices/common_patches/f3_adc_multi_dual.yaml deleted file mode 100644 index aeecad045..000000000 --- a/devices/common_patches/f3_adc_multi_dual.yaml +++ /dev/null @@ -1,6 +0,0 @@ -ADC1_2: - CCR: - _modify: - MULT: - name: DUAL - description: Dual ADC mode selection diff --git a/devices/common_patches/f3_dbgmcu.yaml b/devices/common_patches/f3_dbgmcu.yaml deleted file mode 100644 index 68600885f..000000000 --- a/devices/common_patches/f3_dbgmcu.yaml +++ /dev/null @@ -1,6 +0,0 @@ -DBGMCU: - _modify: - APB1FZ: - name: APB1_FZ - APB2_FZ: - name: APB2_FZ diff --git a/devices/common_patches/f3_flash.yaml b/devices/common_patches/f3_flash.yaml deleted file mode 100644 index 12f3b038b..000000000 --- a/devices/common_patches/f3_flash.yaml +++ /dev/null @@ -1,21 +0,0 @@ -FLASH: - ACR: - _add: - HLFCYA: - description: Flash half cycle access enable - bitOffset: 3 - bitWidth: 1 - access: read-write - SR: - _modify: - WRPRT: - name: "WRPRTERR" - CR: - _modify: - FORCE_OPTLOAD: - name: "OBL_LAUNCH" - OBR: - _modify: - resetValue: 0xFFFFFF0F - BOOT1: - name: "nBOOT1" diff --git a/devices/common_patches/f3_flash_obr_rdptr.yaml b/devices/common_patches/f3_flash_obr_rdptr.yaml deleted file mode 100644 index ae0c31d5c..000000000 --- a/devices/common_patches/f3_flash_obr_rdptr.yaml +++ /dev/null @@ -1,10 +0,0 @@ -FLASH: - OBR: - _delete: - - LEVEL1_PROT - - LEVEL2_PROT - _add: - RDPRT: - description: Read protection Level status - bitOffset: 1 - bitWidth: 2 diff --git a/devices/common_patches/f3_gpio_reset_values.yaml b/devices/common_patches/f3_gpio_reset_values.yaml deleted file mode 100644 index f77564c22..000000000 --- a/devices/common_patches/f3_gpio_reset_values.yaml +++ /dev/null @@ -1,63 +0,0 @@ -# Some F3 SVDs (stm32f302, stm32f303, stm32f373, stm32f3x8) have wrong reset -# values for some of the GPIO registers. -# -# We want the following reset values (omitted values are 0x0000_0000): -# -# GPIOA: -# MODER: 0xA800_0000 -# OSPEEDR: 0x0C00_0000 -# PUPDR: 0x6400_0000 -# -# GPIOB: -# MODER: 0x0000_0280 -# OSPEEDR: 0x0000_00C0 -# PUPDR: 0x0000_0100 -# -# To this end, this patch ensures there are three different GPIO peripherals, -# GPIOA, GPIOB, and GPIOC. GPIOC has all-zero reset values and all other GPIO -# peripherals derive from that. - -# In some SVDs GPIOC is derived from GPIOB, so we need to delete and re-add -# to be able to modify its reset values. -_delete: - - GPIOC -_copy: - GPIOC: - from: GPIOA -_modify: - GPIOC: - baseAddress: "0x48000800" - -_derive: - GPIOD: GPIOC - GPIOE: GPIOC - GPIOF: GPIOC - GPIOG: GPIOC - GPIOH: GPIOC - -GPIOA: - _modify: - MODER: - resetValue: "0xa8000000" - OSPEEDR: - resetValue: "0x0C000000" - PUPDR: - resetValue: "0x64000000" - -GPIOB: - _modify: - MODER: - resetValue: "0x00000280" - OSPEEDR: - resetValue: "0x000000C0" - PUPDR: - resetValue: "0x00000100" - -GPIOC: - _modify: - MODER: - resetValue: "0x00000000" - OSPEEDR: - resetValue: "0x00000000" - PUPDR: - resetValue: "0x00000000" diff --git a/devices/common_patches/f3_rcc.yaml b/devices/common_patches/f3_rcc.yaml deleted file mode 100644 index a136aa627..000000000 --- a/devices/common_patches/f3_rcc.yaml +++ /dev/null @@ -1,19 +0,0 @@ -RCC: - APB1RSTR: - _modify: - DACRST: - name: DAC1RST - AHBENR: - _modify: - DMAEN: - name: DMA1EN - APB1ENR: - _modify: - DACEN: - name: DAC1EN - CSR: - _add: - V18PWRRSTF: - description: Reset flag of the 1.8 V domain - bitOffset: 23 - bitWidth: 1 diff --git a/devices/common_patches/f3_rcc_cfgr3_tim.yaml b/devices/common_patches/f3_rcc_cfgr3_tim.yaml deleted file mode 100644 index ccf60069a..000000000 --- a/devices/common_patches/f3_rcc_cfgr3_tim.yaml +++ /dev/null @@ -1,23 +0,0 @@ -RCC: - CFGR3: - _add: - TIM15SW: - description: Timer15 clock source selection - bitOffset: 10 - bitWidth: 1 - TIM16SW: - description: Timer16 clock source selection - bitOffset: 11 - bitWidth: 1 - TIM17SW: - description: Timer17 clock source selection - bitOffset: 13 - bitWidth: 1 - TIM2SW: - description: Timer2 clock source selection - bitOffset: 24 - bitWidth: 1 - TIM34SW: - description: Timer34 clock source selection - bitOffset: 25 - bitWidth: 1 diff --git a/devices/common_patches/f3_rcc_dac3_dac2.yaml b/devices/common_patches/f3_rcc_dac3_dac2.yaml deleted file mode 100644 index 4622d49a7..000000000 --- a/devices/common_patches/f3_rcc_dac3_dac2.yaml +++ /dev/null @@ -1,9 +0,0 @@ -RCC: - APB1RSTR: - _modify: - DAC3RST: - name: DAC2RST - APB1ENR: - _modify: - DAC3EN: - name: DAC2EN diff --git a/devices/common_patches/f3_rcc_delete_cec.yaml b/devices/common_patches/f3_rcc_delete_cec.yaml deleted file mode 100644 index 3f31aff1d..000000000 --- a/devices/common_patches/f3_rcc_delete_cec.yaml +++ /dev/null @@ -1,10 +0,0 @@ -RCC: - APB1RSTR: - _delete: - - CECRST - APB1ENR: - _delete: - - CECEN - CFGR3: - _delete: - - CECSW diff --git a/devices/common_patches/f3_rcc_delete_tim8.yaml b/devices/common_patches/f3_rcc_delete_tim8.yaml deleted file mode 100644 index 40acfadc8..000000000 --- a/devices/common_patches/f3_rcc_delete_tim8.yaml +++ /dev/null @@ -1,10 +0,0 @@ -RCC: - APB2RSTR: - _delete: - - TIM8RST - APB2ENR: - _delete: - - TIM8EN - CFGR3: - _delete: - - TIM8SW diff --git a/devices/common_patches/f3_rcc_i2c3.yaml b/devices/common_patches/f3_rcc_i2c3.yaml deleted file mode 100644 index aa9325229..000000000 --- a/devices/common_patches/f3_rcc_i2c3.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Add missing reset/enable bits for I2C 3 -RCC: - APB1RSTR: - _add: - I2C3RST: - description: I2C3 reset - bitOffset: 30 - bitWidth: 1 - APB1ENR: - _add: - I2C3EN: - description: I2C3 clock enable - bitOffset: 30 - bitWidth: 1 - CFGR3: - _add: - I2C3SW: - description: I2C3 clock source selection - bitOffset: 6 - bitWidth: 1 diff --git a/devices/common_patches/f3_rcc_mco.yaml b/devices/common_patches/f3_rcc_mco.yaml deleted file mode 100644 index d81bfa619..000000000 --- a/devices/common_patches/f3_rcc_mco.yaml +++ /dev/null @@ -1,13 +0,0 @@ -RCC: - CFGR: - _delete: - - MCOF - _add: - MCOPRE: - description: Microcontroller Clock Output Prescaler - bitOffset: 28 - bitWidth: 3 - PLLNODIV: - description: Do not divide PLL to MCO - bitOffset: 31 - bitWidth: 1 diff --git a/devices/common_patches/f3_rcc_spi4.yaml b/devices/common_patches/f3_rcc_spi4.yaml deleted file mode 100644 index e303a806f..000000000 --- a/devices/common_patches/f3_rcc_spi4.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# Add missing reset/enable bits for SPI 4 -RCC: - APB2RSTR: - _add: - SPI4RST: - description: SPI4 reset - bitOffset: 15 - bitWidth: 1 - APB2ENR: - _add: - SPI4EN: - description: SPI4 clock enable - bitOffset: 15 - bitWidth: 1 diff --git a/devices/common_patches/f3_rcc_tim20.yaml b/devices/common_patches/f3_rcc_tim20.yaml deleted file mode 100644 index 8ab3ecb9a..000000000 --- a/devices/common_patches/f3_rcc_tim20.yaml +++ /dev/null @@ -1,19 +0,0 @@ -RCC: - APB2RSTR: - _add: - TIM20RST: - description: TIM20 timer reset - bitOffset: 20 - bitWidth: 1 - APB2ENR: - _add: - TIM20EN: - description: TIM20 timer clock enable - bitOffset: 20 - bitWidth: 1 - CFGR3: - _add: - TIM20SW: - description: Timer20 clock source selection - bitOffset: 15 - bitWidth: 1 diff --git a/devices/common_patches/f3_rcc_usb.yaml b/devices/common_patches/f3_rcc_usb.yaml deleted file mode 100644 index 081c61525..000000000 --- a/devices/common_patches/f3_rcc_usb.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CFGR: - _modify: - USBPRES: - name: USBPRE diff --git a/devices/common_patches/f3_syscfg.yaml b/devices/common_patches/f3_syscfg.yaml deleted file mode 100644 index 5ff019878..000000000 --- a/devices/common_patches/f3_syscfg.yaml +++ /dev/null @@ -1,63 +0,0 @@ -_modify: - SYSCFG_COMP_OPAMP: - name: SYSCFG - groupName: SYSCFG - description: System configuration controller - -SYSCFG: - _strip: - - SYSCFG_ - _delete: - - OPAMP* - - COMP* - CFGR1: - _modify: - TIM1_ITR_RMP: - name: TIM1_ITR3_RMP - I2C_PB6_FM: - name: I2C_PB6_FMP - I2C_PB7_FM: - name: I2C_PB7_FMP - I2C_PB8_FM: - name: I2C_PB8_FMP - I2C_PB9_FM: - name: I2C_PB9_FMP - I2C1_FM: - name: I2C1_FMP - I2C2_FM: - name: I2C2_FMP - _delete: - - FPU_IT - _add: - FPU_IE5: - description: Inexact interrupt enable - bitOffset: 31 - bitWidth: 1 - access: read-write - FPU_IE4: - description: Input denormal interrupt enable - bitOffset: 30 - bitWidth: 1 - access: read-write - FPU_IE3: - description: Overflow interrupt enable - bitOffset: 29 - bitWidth: 1 - access: read-write - FPU_IE2: - description: Underflow interrupt enable - bitOffset: 28 - bitWidth: 1 - access: read-write - FPU_IE1: - description: Devide-by-zero interrupt enable - bitOffset: 27 - bitWidth: 1 - access: read-write - FPU_IE0: - description: Invalid operation interrupt enable - bitOffset: 26 - bitWidth: 1 - access: read-write - - diff --git a/devices/common_patches/f3_syscfg_cfgr1_adc2_dac1_rmp.yaml b/devices/common_patches/f3_syscfg_cfgr1_adc2_dac1_rmp.yaml deleted file mode 100644 index b20bf457e..000000000 --- a/devices/common_patches/f3_syscfg_cfgr1_adc2_dac1_rmp.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# Modify names to fit the name in the register documentation -# instead of the register map name. -SYSCFG: - CFGR1: - _modify: - ADC24_DMA_RMP: - name: ADC2_DMA_RMP - DAC_TRIG_RMP: - name: DAC1_TRIG_RMP diff --git a/devices/common_patches/f3_syscfg_cfgr1_dac2_ch1_dma_rmp.yaml b/devices/common_patches/f3_syscfg_cfgr1_dac2_ch1_dma_rmp.yaml deleted file mode 100644 index 1ca337c7d..000000000 --- a/devices/common_patches/f3_syscfg_cfgr1_dac2_ch1_dma_rmp.yaml +++ /dev/null @@ -1,8 +0,0 @@ -SYSCFG: - CFGR1: - _add: - DAC2_CH1_DMA_RMP: - description: DAC2 channel1 DMA remap - bitOffset: 15 - bitWidth: 1 - access: read-write diff --git a/devices/common_patches/f3_syscfg_cfgr1_i2c3_fmp.yaml b/devices/common_patches/f3_syscfg_cfgr1_i2c3_fmp.yaml deleted file mode 100644 index bbbfac5ee..000000000 --- a/devices/common_patches/f3_syscfg_cfgr1_i2c3_fmp.yaml +++ /dev/null @@ -1,8 +0,0 @@ -SYSCFG: - CFGR1: - _add: - I2C3_FMP: - description: I2C3 Fast Mode Plus - bitOffset: 24 - bitWidth: 1 - access: read-write diff --git a/devices/common_patches/f3_syscfg_cfgr1_mem_mode_3.yaml b/devices/common_patches/f3_syscfg_cfgr1_mem_mode_3.yaml deleted file mode 100644 index eaa5ecee2..000000000 --- a/devices/common_patches/f3_syscfg_cfgr1_mem_mode_3.yaml +++ /dev/null @@ -1,5 +0,0 @@ -SYSCFG: - CFGR1: - _modify: - MEM_MODE: - bitWidth: 3 diff --git a/devices/common_patches/f3_syscfg_cfgr1_timx_dacx_chx_dma_rmp.yaml b/devices/common_patches/f3_syscfg_cfgr1_timx_dacx_chx_dma_rmp.yaml deleted file mode 100644 index 87c02d17b..000000000 --- a/devices/common_patches/f3_syscfg_cfgr1_timx_dacx_chx_dma_rmp.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# Modify names to fit the name in the register documentation -# instead of the register map name. -SYSCFG: - CFGR1: - _modify: - TIM7_DAC2_DMA_RMP: - name: TIM7_DAC1_CH2_DMA_RMP - TIM6_DAC1_DMA_RMP: - name: TIM6_DAC1_CH1_DMA_RMP diff --git a/devices/common_patches/f3_syscfg_cfgr2.yaml b/devices/common_patches/f3_syscfg_cfgr2.yaml deleted file mode 100644 index 8c6165a7c..000000000 --- a/devices/common_patches/f3_syscfg_cfgr2.yaml +++ /dev/null @@ -1,7 +0,0 @@ -SYSCFG: - CFGR2: - _modify: - LOCUP_LOCK: - name: LOCKUP_LOCK - BYP_ADD_PAR: - name: BYP_ADDR_PAR diff --git a/devices/common_patches/f3_syscfg_cfgr4.yaml b/devices/common_patches/f3_syscfg_cfgr4.yaml deleted file mode 100644 index c487cb1ef..000000000 --- a/devices/common_patches/f3_syscfg_cfgr4.yaml +++ /dev/null @@ -1,65 +0,0 @@ -SYSCFG: - _add: - CFGR4: - description: configuration register 4 - addressOffset: 0x48 - size: 0x20 - resetValue: 0x00000000 - access: read-write - fields: - ADC12_EXT2_RMP: - description: Controls the Input trigger of ADC12 regular channel EXT2 - bitOffset: 0 - bitWidth: 1 - ADC12_EXT3_RMP: - description: Controls the Input trigger of ADC12 regular channel EXT3 - bitOffset: 1 - bitWidth: 1 - ADC12_EXT5_RMP: - description: Controls the Input trigger of ADC12 regular channel EXT5 - bitOffset: 2 - bitWidth: 1 - ADC12_EXT13_RMP: - description: Controls the Input trigger of ADC12 regular channel EXT13 - bitOffset: 3 - bitWidth: 1 - ADC12_EXT15_RMP: - description: Controls the Input trigger of ADC12 regular channel EXT15 - bitOffset: 4 - bitWidth: 1 - ADC12_JEXT3_RMP: - description: Controls the Input trigger of ADC12 injected channel JEXT3 - bitOffset: 5 - bitWidth: 1 - ADC12_JEXT6_RMP: - description: Controls the Input trigger of ADC12 injected channel JEXT6 - bitOffset: 6 - bitWidth: 1 - ADC12_JEXT13_RMP: - description: Controls the Input trigger of ADC12 injected channel JEXT13 - bitOffset: 7 - bitWidth: 1 - ADC34_EXT5_RMP: - description: Controls the Input trigger of ADC34 regular channel EXT5 - bitOffset: 8 - bitWidth: 1 - ADC34_EXT6_RMP: - description: Controls the Input trigger of ADC34 regular channel EXT6 - bitOffset: 9 - bitWidth: 1 - ADC34_EXT15_RMP: - description: Controls the Input trigger of ADC34 regular channel EXT15 - bitOffset: 10 - bitWidth: 1 - ADC34_JEXT5_RMP: - description: Controls the Input trigger of ADC34 injected channel JEXT5 - bitOffset: 11 - bitWidth: 1 - ADC34_JEXT11_RMP: - description: Controls the Input trigger of ADC34 injected channel JEXT11 - bitOffset: 12 - bitWidth: 1 - ADC34_JEXT14_RMP: - description: Controls the Input trigger of ADC34 injected channel JEXT14 - bitOffset: 13 - bitWidth: 1 diff --git a/devices/common_patches/f3_syscfg_rcr_page8-15.yaml b/devices/common_patches/f3_syscfg_rcr_page8-15.yaml deleted file mode 100644 index ca8155a4c..000000000 --- a/devices/common_patches/f3_syscfg_rcr_page8-15.yaml +++ /dev/null @@ -1,35 +0,0 @@ -SYSCFG: - RCR: - _add: - PAGE8_WP: - description: CCM SRAM page write protection bit - bitOffset: 8 - bitWidth: 1 - PAGE9_WP: - description: CCM SRAM page write protection bit - bitOffset: 9 - bitWidth: 1 - PAGE10_WP: - description: CCM SRAM page write protection bit - bitOffset: 10 - bitWidth: 1 - PAGE11_WP: - description: CCM SRAM page write protection bit - bitOffset: 11 - bitWidth: 1 - PAGE12_WP: - description: CCM SRAM page write protection bit - bitOffset: 12 - bitWidth: 1 - PAGE13_WP: - description: CCM SRAM page write protection bit - bitOffset: 13 - bitWidth: 1 - PAGE14_WP: - description: CCM SRAM page write protection bit - bitOffset: 14 - bitWidth: 1 - PAGE15_WP: - description: CCM SRAM page write protection bit - bitOffset: 15 - bitWidth: 1 diff --git a/devices/common_patches/f4_adc_no_csr.yaml b/devices/common_patches/f4_adc_no_csr.yaml deleted file mode 100644 index 07de884ce..000000000 --- a/devices/common_patches/f4_adc_no_csr.yaml +++ /dev/null @@ -1,3 +0,0 @@ -ADC_Common: - _delete: - - CSR diff --git a/devices/common_patches/f4_adc_single_ccr.yaml b/devices/common_patches/f4_adc_single_ccr.yaml deleted file mode 100644 index 11a362a0b..000000000 --- a/devices/common_patches/f4_adc_single_ccr.yaml +++ /dev/null @@ -1,6 +0,0 @@ -ADC_Common: - CCR: - _delete: - - DMA - - DDS - - DELAY diff --git a/devices/common_patches/f4_adc_single_csr.yaml b/devices/common_patches/f4_adc_single_csr.yaml deleted file mode 100644 index 3a53130d9..000000000 --- a/devices/common_patches/f4_adc_single_csr.yaml +++ /dev/null @@ -1,5 +0,0 @@ -ADC_Common: - CSR: - _delete: - - "*2" - - "*3" diff --git a/devices/common_patches/f4_fmpi2c.yaml b/devices/common_patches/f4_fmpi2c.yaml deleted file mode 100644 index 83085bbac..000000000 --- a/devices/common_patches/f4_fmpi2c.yaml +++ /dev/null @@ -1,35 +0,0 @@ -# Fix incorrect fields names in FMPI2C -FMPI2C*: - CR1: - _modify: - TCDMAEN: - name: TXDMAEN - ADDRE: - name: ADDRIE - CR2: - _merge: - - "SADD*" - OAR2: - _modify: - OA21_7: - name: OA2 - ICR: - _modify: - ALERTC: - name: ALERTCF - -# Rename I2C_BUFOUT to CFGR and I2C4 to FMPI2C1 -SYSCFG: - _modify: - I2C_BUFOUT: - name: CFGR - displayName: CFGR - description: Configuration register - CFGR: - _modify: - I2C4SCL: - name: FMPI2C1_SCL - description: Forces FM+ drive capability on I2CFMP1_SCL pin - I2C4SDA: - name: FMPI2C1_SDA - description: Forces FM+ drive capability on I2CFMP1_SCL pin diff --git a/devices/common_patches/f4_rcc_dckcfgr.yaml b/devices/common_patches/f4_rcc_dckcfgr.yaml deleted file mode 100644 index 7ad2d3637..000000000 --- a/devices/common_patches/f4_rcc_dckcfgr.yaml +++ /dev/null @@ -1,13 +0,0 @@ -RCC: - _add: - DCKCFGR: - description: RCC Dedicated Clock Configuration Register - addressOffset: 0x8C - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - TIMPRE: - description: Timers clocks prescalers selection - bitOffset: 24 - bitWidth: 1 diff --git a/devices/common_patches/f4_rcc_fmpi2c.yaml b/devices/common_patches/f4_rcc_fmpi2c.yaml deleted file mode 100644 index b14e99099..000000000 --- a/devices/common_patches/f4_rcc_fmpi2c.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Rename I2C4 to FMPI2C1 -RCC: - APB1RSTR: - _modify: - I2C4RST,I2CFMP1RST: - name: FMPI2C1RST - description: FMPI2C1 reset - APB1ENR: - _modify: - I2C4EN,I2CFMP1EN: - name: FMPI2C1EN - description: FMPI2C1 clock enable - APB1LPENR: - _modify: - I2C4LPEN,I2CFMP1LPEN: - name: FMPI2C1LPEN - description: FMPI2C1 clock enable during Sleep diff --git a/devices/common_patches/f4_rtc_cr.yaml b/devices/common_patches/f4_rtc_cr.yaml deleted file mode 100644 index e66eadfa2..000000000 --- a/devices/common_patches/f4_rtc_cr.yaml +++ /dev/null @@ -1,13 +0,0 @@ -RTC: - CR: - _add: - BYPSHAD: - description: Bypass the shadow registers - bitOffset: 5 - bitWidth: 1 - access: read-write - COSEL: - description: Calibration output selection - bitOffset: 19 - bitWidth: 1 - access: read-write diff --git a/devices/common_patches/f7_interrupts.yaml b/devices/common_patches/f7_interrupts.yaml deleted file mode 100644 index 60e2d63aa..000000000 --- a/devices/common_patches/f7_interrupts.yaml +++ /dev/null @@ -1,57 +0,0 @@ -# Add the many missing interrupts for the STM32F7x{5,6,7,9} devices. - -PWR: - _add: - _interrupts: - PVD: - description: PVD through EXTI line detection interrupt - value: 1 - -I2C1: - _add: - _interrupts: - I2C2_EV: - description: I2C2 event interrupt - value: 33 - I2C2_ER: - description: I2C2 error interrupt - value: 34 - I2C3_EV: - description: I2C3 event interrupt - value: 72 - I2C3_ER: - description: I2C3 error interrupt - value: 73 - I2C4_EV: - description: I2C4 event interrupt - value: 95 - I2C4_ER: - description: I2C4 error interrupt - value: 96 - -USART1: - _add: - _interrupts: - USART6: - description: USART6 global interrupt - value: 71 - UART4: - description: UART4 global interrupt - value: 52 - UART7: - description: UART7 global interrupt - value: 82 - -SAI1: - _add: - _interrupts: - SAI2: - description: SAI2 global interrupt - value: 91 - -CRC: - _add: - _interrupts: - HDMI_CEC: - description: HDMI-CEC global interrupt - value: 94 \ No newline at end of file diff --git a/devices/common_patches/f7_lptim_interrupt.yaml b/devices/common_patches/f7_lptim_interrupt.yaml deleted file mode 100644 index cd4634f8e..000000000 --- a/devices/common_patches/f7_lptim_interrupt.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Add missing LP_Timer1 interrupt for some STM32F7 devices. - -LPTIM1: - _add: - _interrupts: - LP_Timer1: - description: LP Timer1 global interrupt - value: 93 \ No newline at end of file diff --git a/devices/common_patches/f7_ltdc_interrupts.yaml b/devices/common_patches/f7_ltdc_interrupts.yaml deleted file mode 100644 index 769866338..000000000 --- a/devices/common_patches/f7_ltdc_interrupts.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# The LTDC interrupts are both named "LCD-TFT" in the SVD files and the reference manuals. - -LTDC: - _delete: - _interrupts: - - "*" - - _add: - _interrupts: - LTDC: - description: LTDC global interrupt - value: 88 - LTDC_ER: - description: LTDC global error interrupt - value: 89 \ No newline at end of file diff --git a/devices/common_patches/f7_rcc_apbenr.yaml b/devices/common_patches/f7_rcc_apbenr.yaml deleted file mode 100644 index 1f81e07f7..000000000 --- a/devices/common_patches/f7_rcc_apbenr.yaml +++ /dev/null @@ -1,15 +0,0 @@ -RCC: - APB1ENR: - _modify: - UART7ENR: - name: UART7EN - UART8ENR: - name: UART8EN - APB2ENR: - _modify: - SPI4ENR: - name: SPI4EN - SPI5ENR: - name: SPI5EN - SPI6ENR: - name: SPI6EN diff --git a/devices/common_patches/f7_rcc_dckcfgr.yaml b/devices/common_patches/f7_rcc_dckcfgr.yaml deleted file mode 100644 index 2d2722776..000000000 --- a/devices/common_patches/f7_rcc_dckcfgr.yaml +++ /dev/null @@ -1,9 +0,0 @@ -RCC: - DCKCFGR1: - _modify: - resetValue: 0x00000000 - PLLI2SDIV: - name: PLLI2SDIVQ - DCKCFGR2: - _modify: - resetValue: 0x00000000 diff --git a/devices/common_patches/f7_rcc_dckcfgr_RM0410.yaml b/devices/common_patches/f7_rcc_dckcfgr_RM0410.yaml deleted file mode 100644 index 8f09c48e7..000000000 --- a/devices/common_patches/f7_rcc_dckcfgr_RM0410.yaml +++ /dev/null @@ -1,21 +0,0 @@ -RCC: - DCKCFGR1: - _add: - DFSDM1SEL: - description: DFSDM1 clock source selection - bitOffset: 25 - bitWidth: 1 - ADFSDM1SEL: - description: DFSDM1 AUDIO clock source selection - bitOffset: 26 - bitWidth: 1 - DCKCFGR2: - _add: - SDMMC2SEL: - description: SDMMC2 clock source selection - bitOffset: 29 - bitWidth: 1 - DSISEL: - description: DSI clock source selection - bitOffset: 30 - bitWidth: 1 diff --git a/devices/common_patches/f7_rcc_dckcfgr_sdmmc1.yaml b/devices/common_patches/f7_rcc_dckcfgr_sdmmc1.yaml deleted file mode 100644 index 2ed19e262..000000000 --- a/devices/common_patches/f7_rcc_dckcfgr_sdmmc1.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - DCKCFGR2: - _modify: - SDMMCSEL: - name: SDMMC1SEL diff --git a/devices/common_patches/f7_rcc_lsedrv.yaml b/devices/common_patches/f7_rcc_lsedrv.yaml deleted file mode 100644 index a0eaf7343..000000000 --- a/devices/common_patches/f7_rcc_lsedrv.yaml +++ /dev/null @@ -1,8 +0,0 @@ -RCC: - BDCR: - _add: - LSEDRV: - description: LSE oscillator drive capability - bitOffset: 3 - bitWidth: 2 - access: read-write diff --git a/devices/common_patches/f7_rcc_rename_dckcfgr.yaml b/devices/common_patches/f7_rcc_rename_dckcfgr.yaml deleted file mode 100644 index e6e8e9c5d..000000000 --- a/devices/common_patches/f7_rcc_rename_dckcfgr.yaml +++ /dev/null @@ -1,6 +0,0 @@ -RCC: - _modify: - DKCFGR1: - name: DCKCFGR1 - DKCFGR2: - name: DCKCFGR2 diff --git a/devices/common_patches/f7x23_pllsai.yaml b/devices/common_patches/f7x23_pllsai.yaml deleted file mode 100644 index fb61e5fd2..000000000 --- a/devices/common_patches/f7x23_pllsai.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CR: - _modify: - PLLSAIRDY: - access: read-only diff --git a/devices/common_patches/f7x23_rcc_dckcfgr.yaml b/devices/common_patches/f7x23_rcc_dckcfgr.yaml deleted file mode 100644 index 2114a304a..000000000 --- a/devices/common_patches/f7x23_rcc_dckcfgr.yaml +++ /dev/null @@ -1,11 +0,0 @@ -RCC: - DCKCFGR2: - _modify: - UART1SEL: - name: USART1SEL - UART2SEL: - name: USART2SEL - UART3SEL: - name: USART3SEL - UART6SEL: - name: USART6SEL diff --git a/devices/common_patches/flash/flash_boot0s.yaml b/devices/common_patches/flash/flash_boot0s.yaml deleted file mode 100644 index 616cd30a3..000000000 --- a/devices/common_patches/flash/flash_boot0s.yaml +++ /dev/null @@ -1,12 +0,0 @@ -FLASH: - OPTR: - _add: - nSWBOOT0: - description: Software BOOT0 - bitOffset: 26 - bitWidth: 1 - nBOOT0: - description: nBOOT0 option bit - bitOffset: 27 - bitWidth: 1 - diff --git a/devices/common_patches/flash/flash_dual_bank.yaml b/devices/common_patches/flash/flash_dual_bank.yaml deleted file mode 100644 index e0a4bec01..000000000 --- a/devices/common_patches/flash/flash_dual_bank.yaml +++ /dev/null @@ -1,67 +0,0 @@ -# Cluster bank-specific registers - -"FLASH": - KEYR1: - _strip_end: - - '1' - CR1: - _strip_end: - - '1' - SR1: - _strip_end: - - '1' - CCR1: - _strip_end: - - '1' - PRAR_CUR1: - _strip_end: - - '1' - PRAR_PRG1: - _strip_end: - - '1' - SCAR_CUR1: - _strip_end: - - '1' - SCAR_PRG1: - _strip_end: - - '1' - WPSN_CUR1R: - _strip_end: - - '1' - WPSN_PRG1R: - _strip_end: - - '1' - ECC_FA?R: - _strip_end: - - '1' - - _cluster: - "BANK%s": - "KEYR?": - name: KEYR - "CR?": - name: CR - "SR?": - name: SR - "CCR?": - name: CCR - "PRAR_CUR?": - name: PRAR_CUR - "PRAR_PRG?": - name: PRAR_PRG - "SCAR_CUR?": - name: SCAR_CUR - "SCAR_PRG?": - name: SCAR_PRG - "WPSN_CUR?R": - name: WPSN_CURR - "WPSN_PRG?R": - name: WPSN_PRGR - "CRCCR?": - name: CRCCR - "CRCSADD?R": - name: CRCSADDR - "CRCEADD?R": - name: CRCEADDR - "ECC_FA?R": - name: FAR diff --git a/devices/common_patches/fpu_interrupt.yaml b/devices/common_patches/fpu_interrupt.yaml deleted file mode 100644 index 338d0bcc6..000000000 --- a/devices/common_patches/fpu_interrupt.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# different microcontrollers have duplicated FPU interrupt - -FPU: - _delete: - _interrupts: - - FPU - _add: - _interrupts: - FPU: - description: Floating point unit - value: 81 diff --git a/devices/common_patches/fsmc/fsmc_nand_v1.yaml b/devices/common_patches/fsmc/fsmc_nand_v1.yaml deleted file mode 100644 index 09b05cdf9..000000000 --- a/devices/common_patches/fsmc/fsmc_nand_v1.yaml +++ /dev/null @@ -1,29 +0,0 @@ -"FMC,FSMC": - _array: - "PCR?": {} - "SR?": {} - "PMEM?": - _modify: - MEMHIZx: - name: MEMHIZ - MEMHOLDx: - name: MEMHOLD - MEMWAITx: - name: MEMWAIT - MEMSETx: - name: MEMSET - "PATT?": - _modify: - ATTHIZx: - name: ATTHIZ - ATTHOLDx: - name: ATTHOLD - ATTWAITx: - name: ATTWAIT - ATTSETx: - name: ATTSET - "ECCR?": - _modify: - ECCx: - name: ECC - diff --git a/devices/common_patches/fsmc/fsmc_nand_v2.yaml b/devices/common_patches/fsmc/fsmc_nand_v2.yaml deleted file mode 100644 index 4cefec514..000000000 --- a/devices/common_patches/fsmc/fsmc_nand_v2.yaml +++ /dev/null @@ -1,26 +0,0 @@ -"FMC,FSMC": - "PMEM": - _modify: - MEMHIZx: - name: MEMHIZ - MEMHOLDx: - name: MEMHOLD - MEMWAITx: - name: MEMWAIT - MEMSETx: - name: MEMSET - "PATT": - _modify: - ATTHIZx: - name: ATTHIZ - ATTHOLDx: - name: ATTHOLD - ATTWAITx: - name: ATTWAIT - ATTSETx: - name: ATTSET - "ECCR": - _modify: - ECCx: - name: ECC - diff --git a/devices/common_patches/fsmc/fsmc_sd.yaml b/devices/common_patches/fsmc/fsmc_sd.yaml deleted file mode 100644 index f592b2719..000000000 --- a/devices/common_patches/fsmc/fsmc_sd.yaml +++ /dev/null @@ -1,4 +0,0 @@ -"FMC,FSMC": - _array: - "SDCR?": {} - "SDTR?": {} diff --git a/devices/common_patches/fsmc/fsmc_sdfix.yaml b/devices/common_patches/fsmc/fsmc_sdfix.yaml deleted file mode 100644 index daa1537cf..000000000 --- a/devices/common_patches/fsmc/fsmc_sdfix.yaml +++ /dev/null @@ -1,14 +0,0 @@ - -"FMC,FSMC": - SDCR2: - _add: - RPIPE: - description: Read pipe - bitOffset: 13 - bitWidth: 2 - SDSR: - _add: - RE: - description: Refresh error flag - bitOffset: 0 - bitWidth: 1 diff --git a/devices/common_patches/fsmc/fsmc_sdram_cluster.yaml b/devices/common_patches/fsmc/fsmc_sdram_cluster.yaml deleted file mode 100644 index a97922a2d..000000000 --- a/devices/common_patches/fsmc/fsmc_sdram_cluster.yaml +++ /dev/null @@ -1,7 +0,0 @@ -"FMC,FSMC": - _cluster: - "SDBANK%s": - "SDTR?": - name: SDTR - "SDCR?": - name: SDCR diff --git a/devices/common_patches/fsmc/fsmc_sram.yaml b/devices/common_patches/fsmc/fsmc_sram.yaml deleted file mode 100644 index 2ac4d7a21..000000000 --- a/devices/common_patches/fsmc/fsmc_sram.yaml +++ /dev/null @@ -1,6 +0,0 @@ -"FMC,FSMC": - _array: - "BCR[2-4]": {} - "BTR?": {} - "BWTR?": {} - diff --git a/devices/common_patches/fsmc/fsmc_sramfix.yaml b/devices/common_patches/fsmc/fsmc_sramfix.yaml deleted file mode 100644 index 27b88f266..000000000 --- a/devices/common_patches/fsmc/fsmc_sramfix.yaml +++ /dev/null @@ -1,15 +0,0 @@ -_include: - - ./fsmc_sramfix_common.yaml - -"FMC,FSMC": - BCR1: - _add: - WRAPMOD: - description: WRAPMOD - bitOffset: 10 - bitWidth: 1 - WFDIS: - description: Write FIFO disable - bitOffset: 21 - bitWidth: 1 - access: read-write diff --git a/devices/common_patches/fsmc/fsmc_sramfix_common.yaml b/devices/common_patches/fsmc/fsmc_sramfix_common.yaml deleted file mode 100644 index b26d875b6..000000000 --- a/devices/common_patches/fsmc/fsmc_sramfix_common.yaml +++ /dev/null @@ -1,15 +0,0 @@ -"FMC,FSMC": - BCR?: - _add: - CPSIZE: - description: CRAM page size - bitOffset: 16 - bitWidth: 3 - access: read-write - BWTR?: - _add: - BUSTURN: - description: Bus turnaround phase duration - bitOffset: 16 - bitWidth: 4 - access: read-write diff --git a/devices/common_patches/fsmc/fsmc_sramfix_v3.yaml b/devices/common_patches/fsmc/fsmc_sramfix_v3.yaml deleted file mode 100644 index 696421760..000000000 --- a/devices/common_patches/fsmc/fsmc_sramfix_v3.yaml +++ /dev/null @@ -1,10 +0,0 @@ -_include: - - ./fsmc_sramfix_common.yaml - -"FMC,FSMC": - BCR1: - _add: - WRAPMOD: - description: WRAPMOD - bitOffset: 10 - bitWidth: 1 diff --git a/devices/common_patches/g0_adc_typo.yaml b/devices/common_patches/g0_adc_typo.yaml deleted file mode 100644 index e27f1f2d3..000000000 --- a/devices/common_patches/g0_adc_typo.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# Fixes 0x1F1F1F11F => 0x1F1F1F1F -ADC: - _modify: - HWCFGR6: - resetValue: "0x1F1F1F1F" diff --git a/devices/common_patches/g0_dma_5ch.yaml b/devices/common_patches/g0_dma_5ch.yaml deleted file mode 100644 index 8a9619f3e..000000000 --- a/devices/common_patches/g0_dma_5ch.yaml +++ /dev/null @@ -1,160 +0,0 @@ -# Fixes for STM32G0 devices with 5 DMA channels -# This patch removes register fields for channels 6 and 7 -DMA: - _cluster: - "CH%s": - description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" - "CCR?": - name: CR - "CNDTR?": - name: NDTR - "CPAR?": - name: PAR - "CMAR?": - name: MAR - _modify: - IFCR: - access: write-only - description: DMA interrupt flag clear register - IFCR: - _modify: - CGIF0: - name: CGIF1 - description: Clear channel 1 global interrupt flag - CTCIF1: - name: CTCIF1 - description: Clear channel 1 transfer complete flag - CHTIF2: - name: CHTIF1 - description: Clear channel 1 half transfer flag - CTEIF3: - name: CTEIF1 - description: Clear channel 1 transfer error flag - CGIF4: - name: CGIF2 - description: Clear channel 2 global interrupt flag - CTCIF5: - name: CTCIF2 - description: Clear channel 2 transfer complete flag - CHTIF6: - name: CHTIF2 - description: Clear channel 2 half transfer flag - CTEIF7: - name: CTEIF2 - description: Clear channel 2 transfer error flag - CGIF8: - name: CGIF3 - description: Clear channel 3 global interrupt flag - CTCIF9: - name: CTCIF3 - description: Clear channel 3 transfer complete flag - CHTIF10: - name: CHTIF3 - description: Clear channel 3 half transfer flag - CTEIF11: - name: CTEIF3 - description: Clear channel 3 transfer error flag - CGIF12: - name: CGIF4 - description: Clear channel 4 global interrupt flag - CTCIF13: - name: CTCIF4 - description: Clear channel 4 transfer complete flag - CHTIF14: - name: CHTIF4 - description: Clear channel 4 half transfer flag - CTEIF15: - name: CTEIF4 - description: Clear channel 4 transfer error flag - CGIF16: - name: CGIF5 - description: Clear channel 5 global interrupt flag - CTCIF17: - name: CTCIF5 - description: Clear channel 5 transfer complete flag - CHTIF18: - name: CHTIF5 - description: Clear channel 5 half transfer flag - CTEIF19: - name: CTEIF5 - description: Clear channel 5 transfer error flag - _delete: - - CGIF20 - - CTCIF21 - - CHTIF22 - - CTEIF23 - - CGIF24 - - CTCIF25 - - CHTIF26 - - CTEIF27 - ISR: - _modify: - GIF0: - name: GIF1 - description: Channel 1 global interrupt flag - TCIF1: - name: TCIF1 - description: Channel 1 transfer complete flag - HTIF2: - name: HTIF1 - description: Channel 1 half transfer flag - TEIF3: - name: TEIF1 - description: Channel 1 transfer error flag - GIF4: - name: GIF2 - description: Channel 2 global interrupt flag - TCIF5: - name: TCIF2 - description: Channel 2 transfer complete flag - HTIF6: - name: HTIF2 - description: Channel 2 half transfer flag - TEIF7: - name: TEIF2 - description: Channel 2 transfer error flag - GIF8: - name: GIF3 - description: Channel 3 global interrupt flag - TCIF9: - name: TCIF3 - description: Channel 3 transfer complete flag - HTIF10: - name: HTIF3 - description: Channel 3 half transfer flag - TEIF11: - name: TEIF3 - description: Channel 3 transfer error flag - GIF12: - name: GIF4 - description: Channel 4 global interrupt flag - TCIF13: - name: TCIF4 - description: Channel 4 transfer complete flag - HTIF14: - name: HTIF4 - description: Channel 4 half transfer flag - TEIF15: - name: TEIF4 - description: Channel 4 transfer error flag - GIF16: - name: GIF5 - description: Channel 5 global interrupt flag - TCIF17: - name: TCIF5 - description: Channel 5 transfer complete flag - HTIF18: - name: HTIF5 - description: Channel 5 half transfer flag - TEIF19: - name: TEIF5 - description: Channel 5 transfer error flag - _delete: - - GIF20 - - TCIF21 - - HTIF22 - - TEIF23 - - GIF24 - - TCIF25 - - HTIF26 - - TEIF27 \ No newline at end of file diff --git a/devices/common_patches/g0_dma_7ch.yaml b/devices/common_patches/g0_dma_7ch.yaml deleted file mode 100644 index db80a2465..000000000 --- a/devices/common_patches/g0_dma_7ch.yaml +++ /dev/null @@ -1,189 +0,0 @@ - -# Fixes for STM32G0 devices with 7 DMA channels -DMA: - _cluster: - "CH%s": - description: "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers" - "CCR?": - name: CR - "CNDTR?": - name: NDTR - "CPAR?": - name: PAR - "CMAR?": - name: MAR - _modify: - IFCR: - access: write-only - IFCR: - _modify: - CGIF0: - name: CGIF1 - description: Clear channel 1 global interrupt flag - CTCIF1: - name: CTCIF1 - description: Clear channel 1 transfer complete flag - CHTIF2: - name: CHTIF1 - description: Clear channel 1 half transfer flag - CTEIF3: - name: CTEIF1 - description: Clear channel 1 transfer error flag - CGIF4: - name: CGIF2 - description: Clear channel 2 global interrupt flag - CTCIF5: - name: CTCIF2 - description: Clear channel 2 transfer complete flag - CHTIF6: - name: CHTIF2 - description: Clear channel 2 half transfer flag - CTEIF7: - name: CTEIF2 - description: Clear channel 2 transfer error flag - CGIF8: - name: CGIF3 - description: Clear channel 3 global interrupt flag - CTCIF9: - name: CTCIF3 - description: Clear channel 3 transfer complete flag - CHTIF10: - name: CHTIF3 - description: Clear channel 3 half transfer flag - CTEIF11: - name: CTEIF3 - description: Clear channel 3 transfer error flag - CGIF12: - name: CGIF4 - description: Clear channel 4 global interrupt flag - CTCIF13: - name: CTCIF4 - description: Clear channel 4 transfer complete flag - CHTIF14: - name: CHTIF4 - description: Clear channel 4 half transfer flag - CTEIF15: - name: CTEIF4 - description: Clear channel 4 transfer error flag - CGIF16: - name: CGIF5 - description: Clear channel 5 global interrupt flag - CTCIF17: - name: CTCIF5 - description: Clear channel 5 transfer complete flag - CHTIF18: - name: CHTIF5 - description: Clear channel 5 half transfer flag - CTEIF19: - name: CTEIF5 - description: Clear channel 5 transfer error flag - CGIF20: - name: CGIF6 - description: Clear channel 6 global interrupt flag - CTCIF21: - name: CTCIF6 - description: Clear channel 6 transfer complete flag - CHTIF22: - name: CHTIF6 - description: Clear channel 6 half transfer flag - CTEIF23: - name: CTEIF6 - description: Clear channel 6 transfer error flag - CGIF24: - name: CGIF7 - description: Clear channel 7 global interrupt flag - CTCIF25: - name: CTCIF7 - description: Clear channel 7 transfer complete flag - CHTIF26: - name: CHTIF7 - description: Clear channel 7 half transfer flag - CTEIF27: - name: CTEIF7 - description: Clear channel 7 transfer error flag - ISR: - _modify: - GIF0: - name: GIF1 - description: Channel 1 global interrupt flag - TCIF1: - name: TCIF1 - description: Channel 1 transfer complete flag - HTIF2: - name: HTIF1 - description: Channel 1 half transfer flag - TEIF3: - name: TEIF1 - description: Channel 1 transfer error flag - GIF4: - name: GIF2 - description: Channel 2 global interrupt flag - TCIF5: - name: TCIF2 - description: Channel 2 transfer complete flag - HTIF6: - name: HTIF2 - description: Channel 2 half transfer flag - TEIF7: - name: TEIF2 - description: Channel 2 transfer error flag - GIF8: - name: GIF3 - description: Channel 3 global interrupt flag - TCIF9: - name: TCIF3 - description: Channel 3 transfer complete flag - HTIF10: - name: HTIF3 - description: Channel 3 half transfer flag - TEIF11: - name: TEIF3 - description: Channel 3 transfer error flag - GIF12: - name: GIF4 - description: Channel 4 global interrupt flag - TCIF13: - name: TCIF4 - description: Channel 4 transfer complete flag - HTIF14: - name: HTIF4 - description: Channel 4 half transfer flag - TEIF15: - name: TEIF4 - description: Channel 4 transfer error flag - GIF16: - name: GIF5 - description: Channel 5 global interrupt flag - TCIF17: - name: TCIF5 - description: Channel 5 transfer complete flag - HTIF18: - name: HTIF5 - description: Channel 5 half transfer flag - TEIF19: - name: TEIF5 - description: Channel 5 transfer error flag - GIF20: - name: GIF6 - description: Channel 6 global interrupt flag - TCIF21: - name: TCIF6 - description: Channel 6 transfer complete flag - HTIF22: - name: HTIF6 - description: Channel 6 half transfer flag - TEIF23: - name: TEIF6 - description: Channel 6 transfer error flag - GIF24: - name: GIF7 - description: Channel 7 global interrupt flag - TCIF25: - name: TCIF7 - description: Channel 7 transfer complete flag - HTIF26: - name: HTIF7 - description: Channel 7 half transfer flag - TEIF27: - name: TEIF7 - description: Channel 7 transfer error flag diff --git a/devices/common_patches/g4_adc.yaml b/devices/common_patches/g4_adc.yaml deleted file mode 100644 index de0c4927a..000000000 --- a/devices/common_patches/g4_adc.yaml +++ /dev/null @@ -1,383 +0,0 @@ -ADC?: - ISR: - _modify: - JQOVF: - description: Injected context queue overflow - AWD3: - description: Analog watchdog 3 flag - AWD2: - description: Analog watchdog 2 flag - AWD1: - description: Analog watchdog 1 flag - JEOS: - description: Injected channel end of sequence flag - JEOC: - description: Injected channel end of conversion flag - OVR: - description: ADC overrun - EOS: - description: End of regular sequence flag - EOC: - description: End of conversion flag - EOSMP: - description: End of sampling flag - ADRDY: - description: ADC ready - - IER: - _modify: - JQOVFIE: - description: Injected context queue overflow interrupt enable - AWD3IE: - description: Analog watchdog 3 interrupt enable - AWD2IE: - description: Analog watchdog 2 interrupt enable - AWD1IE: - description: Analog watchdog 1 interrupt enable - JEOSIE: - description: End of injected sequence of conversions interrupt enable - JEOCIE: - description: End of injected conversion interrupt enable - OVRIE: - description: Overrun interrupt enable - EOSIE: - description: End of regular sequence of conversions interrupt enable - EOCIE: - description: End of regular conversion interrupt enable - EOSMPIE: - description: End of sampling flag interrupt enable for regular conversions - ADRDYIE: - description: ADC ready interrupt enable - - CR: - _modify: - ADCAL: - description: ADC calibration - ADCALDIF: - description: Differential mode for calibration - DEEPPWD: - description: Deep-power-down enable - ADVREGEN: - description: ADC voltage regulator enable - JADSTP: - description: ADC stop of injected conversion command - ADSTP: - description: ADC stop of regular conversion command - JADSTART: - description: ADC start of injected conversion - ADSTART: - description: ADC start of regular conversion - ADDIS: - description: ADC disable command - ADEN: - description: ADC enable control - - CFGR: - _delete: - - ALIGN_5 - _modify: - AWDCH1CH: - name: AWD1CH - description: Analog watchdog 1 channel selection - JAUTO: - description: Automatic injected group conversion - JAWD1EN: - description: Analog watchdog 1 enable on injected channels - AWD1EN: - description: Analog watchdog 1 enable on regular channels - AWD1SGL: - description: Enable the watchdog 1 on a single channel or on all channels - JQM: - description: JSQR queue mode - JDISCEN: - description: Discontinuous mode on injected channels - DISCNUM: - description: Discontinuous mode channel count - DISCEN: - description: Discontinuous mode for regular channels - ALIGN: - description: Data alignment - AUTDLY: - description: Delayed conversion mode - CONT: - description: Single / continuous conversion mode for regular conversions - OVRMOD: - description: Overrun mode - EXTEN: - description: External trigger enable and polarity selection for regular channels - EXTSEL: - description: External trigger selection for regular group - bitOffset: 5 - bitWidth: 5 - RES: - description: Data resolution - DMACFG: - description: Direct memory access configuration - DMAEN: - description: Direct memory access enable - - CFGR2: - _modify: - SMPTRIG: - description: Sampling time control trigger mode - BULB: - description: Bulb sampling mode - SWTRIG: - description: Software trigger bit for sampling time control trigger mode - GCOMP: - description: Gain compensation mode - ROVSM: - description: Regular Oversampling mode - TROVS: - description: Triggered Regular Oversampling - OVSS: - description: Oversampling shift - OVSR: - description: Oversampling ratio - JOVSE: - description: Injected Oversampling Enable - ROVSE: - description: Regular Oversampling Enable - - SMPR1: - _modify: - SMPPLUS: - description: Addition of one clock cycle to the sampling time - SMP9: - description: Channel 9 sampling time selection - SMP8: - description: Channel 8 sampling time selection - SMP7: - description: Channel 7 sampling time selection - SMP6: - description: Channel 6 sampling time selection - SMP5: - description: Channel 5 sampling time selection - SMP4: - description: Channel 4 sampling time selection - SMP3: - description: Channel 3 sampling time selection - SMP2: - description: Channel 2 sampling time selection - SMP1: - description: Channel 1 sampling time selection - SMP0: - description: Channel 0 sampling time selection - - SMPR2: - _modify: - SMP18: - description: Channel 18 sampling time selection - SMP17: - description: Channel 17 sampling time selection - SMP16: - description: Channel 16 sampling time selection - SMP15: - description: Channel 15 sampling time selection - SMP14: - description: Channel 14 sampling time selection - SMP13: - description: Channel 13 sampling time selection - SMP11: - description: Channel 12 sampling time selection - SMP12: - description: Channel 11 sampling time selection - SMP10: - description: Channel 10 sampling time selection - - TR1: - _modify: - HT1: - description: Analog watchdog 1 higher threshold - AWDFILT: - description: Analog watchdog filtering parameter - LT1: - description: Analog watchdog 1 lower threshold - - TR2: - _modify: - HT2: - description: Analog watchdog 2 higher threshold - LT2: - description: Analog watchdog 2 lower threshold - - TR3: - _modify: - HT3: - description: Analog watchdog 3 higher threshold - LT3: - description: Analog watchdog 3 lower threshold - - SQR1: - _modify: - SQ4: - description: 4th conversion in regular sequence - SQ3: - description: 3rd conversion in regular sequence - SQ2: - description: 2nd conversion in regular sequence - SQ1: - description: 1st conversion in regular sequence - L: - description: Regular channel sequence length - - SQR2: - _modify: - SQ9: - description: 9th conversion in regular sequence - SQ8: - description: 8th conversion in regular sequence - SQ7: - description: 7th conversion in regular sequence - SQ6: - description: 6th conversion in regular sequence - SQ5: - description: 5th conversion in regular sequence - - SQR3: - _modify: - SQ14: - description: 14th conversion in regular sequence - SQ13: - description: 13th conversion in regular sequence - SQ12: - description: 12th conversion in regular sequence - SQ11: - description: 11th conversion in regular sequence - SQ10: - description: 10th conversion in regular sequence - - SQR4: - _modify: - SQ16: - description: 16th conversion in regular sequence - SQ15: - description: 15th conversion in regular sequence - - JSQR: - _modify: - SQ4: - description: 4th conversion in the injected sequence - JSQ3: - description: 3rd conversion in the injected sequence - JSQ2: - description: 2nd conversion in the injected sequence - JSQ1: - description: 1st conversion in the injected sequence - JEXTEN: - description: External Trigger Enable and Polarity Selection for injected channels - JEXTSEL: - description: External Trigger Selection for injected group - JL: - description: Injected channel sequence length - - OFR1: - _modify: - OFFSET1_EN: - description: Offset 1 Enable - OFFSET1_CH: - description: Channel selection for the data offset 1 - SATEN: - description: Saturation enable - OFFSETPOS: - description: Positive offset - OFFSET1: - description: Data offset 1 for the channel programmed into bits OFFSET1_CH - - OFR2: - _modify: - OFFSET1_EN: - name: OFFSET2_EN - description: Offset 2 Enable - OFFSET1_CH: - name: OFFSET2_CH - description: Channel selection for the data offset 2 - SATEN: - description: Saturation enable - OFFSETPOS: - description: Positive offset - OFFSET1: - name: OFFSET2 - description: Data offset 2 for the channel programmed into bits OFFSET2_CH - - OFR3: - _modify: - OFFSET1_EN: - name: OFFSET3_EN - description: Offset 3 Enable - OFFSET1_CH: - name: OFFSET3_CH - description: Channel selection for the data offset 3 - SATEN: - description: Saturation enable - OFFSETPOS: - description: Positive offset - OFFSET1: - name: OFFSET3 - description: Data offset 3 for the channel programmed into bits OFFSET3_CH - - OFR4: - _modify: - OFFSET1_EN: - name: OFFSET4_EN - description: Offset 4 Enable - OFFSET1_CH: - name: OFFSET4_CH - description: Channel selection for the data offset 4 - SATEN: - description: Saturation enable - OFFSETPOS: - description: Positive offset - OFFSET1: - name: OFFSET4 - description: Data offset 4 for the channel programmed into bits OFFSET4_CH - - JDR1: - _modify: - JDATA1: - name: JDATA - description: Injected data - JDR2: - _modify: - JDATA2: - name: JDATA - description: Injected data - - JDR3: - _modify: - JDATA3: - name: JDATA - description: Injected data - - JDR4: - _modify: - JDATA4: - name: JDATA - description: Injected data - - AWD2CR: - _modify: - AWD2CH: - description: Analog watchdog 2 channel selection - - AWD3CR: - _modify: - AWD3CH: - description: Analog watchdog 3 channel selection - - DIFSEL: - _modify: - DIFSEL: - description: Differential mode for channels 18 to 0 - - CALFACT: - _modify: - CALFACT_D: - description: Calibration Factors in differential mode - CALFACT_S: - description: Calibration Factors In single-ended mode - - GCOMP: - _modify: - GCOMPCOEFF: - description: Gain compensation coefficient diff --git a/devices/common_patches/g4_adc_common.yaml b/devices/common_patches/g4_adc_common.yaml deleted file mode 100644 index 49b120fbb..000000000 --- a/devices/common_patches/g4_adc_common.yaml +++ /dev/null @@ -1,9 +0,0 @@ -ADC*_*: - CCR: - _modify: - CH17SEL: - name: VSENSESEL - description: V_TS temperature sensor channel selection - CH18SEL: - name: VBATSEL - description: V_BAT battery voltage channel selection diff --git a/devices/common_patches/g4_comp.yaml b/devices/common_patches/g4_comp.yaml deleted file mode 100644 index d98de0165..000000000 --- a/devices/common_patches/g4_comp.yaml +++ /dev/null @@ -1,10 +0,0 @@ -COMP: - _modify: - COMP_C4CSR: - addressOffset: '0x0C' - COMP_C5CSR: - addressOffset: '0x10' - COMP_C6CSR: - addressOffset: '0x14' - COMP_C7CSR: - addressOffset: '0x18' diff --git a/devices/common_patches/g4_exti.yaml b/devices/common_patches/g4_exti.yaml deleted file mode 100644 index 18cd95f33..000000000 --- a/devices/common_patches/g4_exti.yaml +++ /dev/null @@ -1,153 +0,0 @@ -EXTI: - RTSR1: - _delete: - - RT18 - _modify: - RT: - name: RT29 - description: Rising trigger event configuration of line 29 - bitOffset: 29 - bitWidth: 1 - _add: - RT17: - description: Rising trigger event configuration of line 17 - bitOffset: 17 - bitWidth: 1 - RT30: - description: Rising trigger event configuration of line 30 - bitOffset: 30 - bitWidth: 1 - RT31: - description: Rising trigger event configuration of line 31 - bitOffset: 31 - bitWidth: 1 - FTSR1: - _delete: - - FT18 - _add: - FT17: - description: Falling trigger event configuration of line 17 - bitOffset: 17 - bitWidth: 1 - FT29: - description: Falling trigger event configuration of line 29 - bitOffset: 29 - bitWidth: 1 - FT30: - description: Falling trigger event configuration of line 30 - bitOffset: 30 - bitWidth: 1 - FT31: - description: Falling trigger event configuration of line 31 - bitOffset: 31 - bitWidth: 1 - SWIER1: - _delete: - - SWI18 - _add: - SWI17: - description: Software Interrupt on line 17 - bitOffset: 17 - bitWidth: 1 - PR1: - _delete: - - PIF18 - _add: - PIF17: - description: Pending bit 17 - bitOffset: 17 - bitWidth: 1 - IMR2: - _delete: - - IM38 - - IM39 - EMR2: - _delete: - - EM38 - - EM39 - _add: - EM41: - description: Event mask on external/internal line 41 - bitOffset: 9 - bitWidth: 1 - EM42: - description: Event mask on external/internal line 42 - bitOffset: 10 - bitWidth: 1 - EM43: - description: Event mask on external/internal line 43 - bitOffset: 11 - bitWidth: 1 - RTSR2: - _delete: - - RT38 - - RT39 - FTSR2: - _delete: - - FT35 - - FT36 - - FT37 - - FT38 - _add: - FT32: - description: Falling trigger event configuration of line 32 - bitOffset: 0 - bitWidth: 1 - FT33: - description: Falling trigger event configuration of line 33 - bitOffset: 1 - bitWidth: 1 - FT40: - description: Falling trigger event configuration of line 40 - bitOffset: 8 - bitWidth: 1 - FT41: - description: Falling trigger event configuration of line 41 - bitOffset: 9 - bitWidth: 1 - SWIER2: - _delete: - - SWI35 - - SWI36 - - SWI37 - - SWI38 - _add: - SWI32: - description: Software interrupt on line 32 - bitOffset: 0 - bitWidth: 1 - SWI33: - description: Software interrupt on line 33 - bitOffset: 1 - bitWidth: 1 - SWI40: - description: Software interrupt on line 40 - bitOffset: 8 - bitWidth: 1 - SWI41: - description: Software interrupt on line 41 - bitOffset: 9 - bitWidth: 1 - PR2: - _delete: - - PIF35 - - PIF36 - - PIF37 - - PIF38 - _add: - PIF32: - description: Pending bit 32 - bitOffset: 0 - bitWidth: 1 - PIF33: - description: Pending bit 33 - bitOffset: 1 - bitWidth: 1 - PIF40: - description: Pending bit 40 - bitOffset: 8 - bitWidth: 1 - PIF41: - description: Pending bit 41 - bitOffset: 9 - bitWidth: 1 diff --git a/devices/common_patches/g4_rcc.yaml b/devices/common_patches/g4_rcc.yaml deleted file mode 100644 index 6410a6e31..000000000 --- a/devices/common_patches/g4_rcc.yaml +++ /dev/null @@ -1,237 +0,0 @@ -# Edits required to match RM0440. -RCC: - _modify: - PLLSYSCFGR: - name: PLLCFGR - CCIPR1: - name: CCIPR - - CR: - _modify: - PLLSYSRDY: - name: PLLRDY - PLLSYSON: - name: PLLON - HSECSSON: - name: CSSON - - PLLCFGR: - _modify: - PLLSYSPDIV: - name: PLLPDIV - PLLSYSR: - name: PLLR - PLLSYSREN: - name: PLLREN - PLLSYSQ: - name: PLLQ - PLLSYSQEN: - name: PLLQEN - PLLSYSP: - name: PLLP - PLLSYSN: - name: PLLN - PLLSYSM: - name: PLLM - - CIER: - _modify: - PLLSYSRDYIE: - name: PLLRDYIE - RC48RDYIE: - name: HSI48RDYIE - - CIFR: - _modify: - PLLSYSRDYF: - name: PLLRDYF - HSECSSF: - name: CSSF - RC48RDYF: - name: HSI48RDYF - - CICR: - _modify: - PLLSYSRDYC: - name: PLLRDYC - HSECSSC: - name: CSSC - RC48RDYC: - name: HSI48RDYC - - AHB1RSTR: - _modify: - MATRIXRST: - name: FMACRST - description: FMAC reset - FLITFRST_: - name: FLASHRST - description: Flash memory interface reset - - AHB2RSTR: - _modify: - ADC345RST_: - name: ADC345RST - DAC1RST_: - name: DAC1RST - CRYPTRST: - name: AESRST - - AHB3RSTR: - _modify: - QUADSPI1RST: - name: QSPIRST - - APB1RSTR1: - _modify: - I2C3: - name: I2C3RST - USBDRST: - name: USBRST - - APB1RSTR2: - _modify: - USBPDRST: - name: UCPD1RST - description: UCPD1 reset - - AHB1ENR: - _modify: - FLITFEN: - name: FLASHEN - description: Flash memory interface clock enable - - AHB2ENR: - _modify: - DAC1: - name: DAC1EN - DAC2: - name: DAC2EN - DAC3: - name: DAC3EN - DAC4: - name: DAC4EN - CRYPTEN: - name: AESEN - description: AES clock enable - - AHB3ENR: - _modify: - QUADSPI1EN: - name: QSPIEN - description: QUADSPI memory interface clock enable - - APB1ENR1: - _modify: - USBDEN: - name: USBEN - description: USB device clock enable - I2C3: - name: I2C3EN - description: I2C3 clock enable - - APB1ENR2: - _modify: - USBPDEN: - name: UCPD1EN - description: UCPD1 clock enable - - APB2ENR: - _modify: - HRTIMEREN: - name: HRTIM1EN - - AHB2SMENR: - # The SRAM fields are mislabeled, we'll delete/re-create here in case - # they fix the SVD in the future. - _delete: - - SRAM2SMEN # Actually points to CCMSRAMSEN. - - SRAM3SMEN # This is the real SRAM2SMEN. - _add: - CCMSRAMSMEN: - description: CCM SRAM interface clocks enable during Sleep and Stop modes - bitOffset: 9 - bitWidth: 1 - SRAM2SMEN: - description: SRAM2 interface clocks enable during Sleep and Stop modes - bitOffset: 10 - bitWidth: 1 - - _modify: - AD12CSMEN: - name: ADC12SMEN - CRYPTSMEN: - name: AESMEN # sic, from RM0440 but likely should be AESSMEN - RNGSMEN: - name: RNGEN # sic, from RM0440 but RNGSMEN seems more correct - - AHB3SMENR: - _modify: - QUADSPI1SMEN: - name: QSPISMEN - description: QUADSPI memory interface clock enable during Sleep and Stop modes - - APB1SMENR1: - # The USBSMEN and I2C3SMEN fields are mislabeled, we'll delete/re-create - # here in case they fix the SVD in the future. - _delete: - - I2C3SMEN # Actually points to USBSMEN. - - I2C3SMEN_3 # Correct, except for name. - _add: - USBSMEN: - description: USB device clocks enable during Sleep and Stop modes - bitOffset: 23 - bitWidth: 1 - I2C3SMEN: - description: I2C3 clocks enable during Sleep and Stop modes - bitOffset: 30 - bitWidth: 1 - - APB1SMENR2: - _modify: - USBPDSMEN: - name: UCPD1SMEN - description: UCPD1 clocks enable during Sleep and Stop modes - - APB2SMENR: - _modify: - HRTIMERSMEN: - name: HRTIM1SMEN - - CCIPR: - _modify: - ADCSEL: - name: ADC12SEL - SPISEL_: - name: I2S23SEL - SAISEL: - name: SAI1SEL - - BDCR: - _modify: - LSCCOEN: - name: LSCOEN - VSWRST: - name: BDRST - description: RTC domain software reset - - CSR: - _modify: - WDGRSTF: - name: IWDGRSTF - PADRSTF: - name: PINRSTF - - CRRCR: - _modify: - RC48ON: - name: HSI48ON - RC48RDY: - name: HSI48RDY - RC48CAL: - name: HSI48CAL - - CCIPR2: - _modify: - QUADSPISEL: - name: QSPISEL diff --git a/devices/common_patches/gpio_with_OSPEEDER.yaml b/devices/common_patches/gpio_with_OSPEEDER.yaml deleted file mode 100644 index 5a792b29c..000000000 --- a/devices/common_patches/gpio_with_OSPEEDER.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# This is a GPIO patch for the OSPEEDER typo - -"GPIO*": - _modify: - OSPEEDER: - name: OSPEEDR - displayName: OSPEEDR \ No newline at end of file diff --git a/devices/common_patches/h7_adc.yaml b/devices/common_patches/h7_adc.yaml deleted file mode 100644 index c75293e56..000000000 --- a/devices/common_patches/h7_adc.yaml +++ /dev/null @@ -1,32 +0,0 @@ -# ADC fields that require modifications on H7 - -ADC?: - _modify: - LHTR1: - name: HTR1 - HTR1: - _modify: - LHTR1: - name: HTR1 - OFR?: - _modify: - SSATE: - description: "Signed saturation enable" - OFR2: - _modify: - OFFSET1: - name: OFFSET2 - OFFSET1_CH: - name: OFFSET2_CH - OFR3: - _modify: - OFFSET1: - name: OFFSET3 - OFFSET1_CH: - name: OFFSET3_CH - OFR4: - _modify: - OFFSET1: - name: OFFSET4 - OFFSET1_CH: - name: OFFSET4_CH diff --git a/devices/common_patches/h7_adc_boost_rev_v.yaml b/devices/common_patches/h7_adc_boost_rev_v.yaml deleted file mode 100644 index 4ffc79549..000000000 --- a/devices/common_patches/h7_adc_boost_rev_v.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# ADC fields different on H7 Rev V - -"ADC?": - CR: - _modify: - # See RM0433 Section 24.6.3 - BOOST: - bitOffset: 8 - bitWidth: 2 diff --git a/devices/common_patches/h7_common_dualcore.yaml b/devices/common_patches/h7_common_dualcore.yaml deleted file mode 100644 index ab54fb777..000000000 --- a/devices/common_patches/h7_common_dualcore.yaml +++ /dev/null @@ -1,763 +0,0 @@ -# Common SVD errors for dual core stm32h7x5/7x7 - -# Rename in accordance with other devices and reference manual. -_modify: - Flash: - name: FLASH - -"GPIO?": - _strip: - # The SVD incorrectly names all the GPIO registers compared to RM0433. - - GPIO_ - -# The SVD is just quite different to the RM for all these registers. -# We'll go with the RM convention even though it is inconsistent too. -"GPIO*": - MODER: - _modify: - MODE0: - name: MODER0 - MODE1: - name: MODER1 - MODE2: - name: MODER2 - MODE3: - name: MODER3 - MODE4: - name: MODER4 - MODE5: - name: MODER5 - MODE6: - name: MODER6 - MODE7: - name: MODER7 - MODE8: - name: MODER8 - MODE9: - name: MODER9 - MODE10: - name: MODER10 - MODE11: - name: MODER11 - MODE12: - name: MODER12 - MODE13: - name: MODER13 - MODE14: - name: MODER14 - MODE15: - name: MODER15 - OSPEEDR: - _modify: - OSPEED0: - name: OSPEEDR0 - OSPEED1: - name: OSPEEDR1 - OSPEED2: - name: OSPEEDR2 - OSPEED3: - name: OSPEEDR3 - OSPEED4: - name: OSPEEDR4 - OSPEED5: - name: OSPEEDR5 - OSPEED6: - name: OSPEEDR6 - OSPEED7: - name: OSPEEDR7 - OSPEED8: - name: OSPEEDR8 - OSPEED9: - name: OSPEEDR9 - OSPEED10: - name: OSPEEDR10 - OSPEED11: - name: OSPEEDR11 - OSPEED12: - name: OSPEEDR12 - OSPEED13: - name: OSPEEDR13 - OSPEED14: - name: OSPEEDR14 - OSPEED15: - name: OSPEEDR15 - PUPDR: - _modify: - PUPD0: - name: PUPDR0 - PUPD1: - name: PUPDR1 - PUPD2: - name: PUPDR2 - PUPD3: - name: PUPDR3 - PUPD4: - name: PUPDR4 - PUPD5: - name: PUPDR5 - PUPD6: - name: PUPDR6 - PUPD7: - name: PUPDR7 - PUPD8: - name: PUPDR8 - PUPD9: - name: PUPDR9 - PUPD10: - name: PUPDR10 - PUPD11: - name: PUPDR11 - PUPD12: - name: PUPDR12 - PUPD13: - name: PUPDR13 - PUPD14: - name: PUPDR14 - PUPD15: - name: PUPDR15 - IDR: - _modify: - ID0: - name: IDR0 - ID1: - name: IDR1 - ID2: - name: IDR2 - ID3: - name: IDR3 - ID4: - name: IDR4 - ID5: - name: IDR5 - ID6: - name: IDR6 - ID7: - name: IDR7 - ID8: - name: IDR8 - ID9: - name: IDR9 - ID10: - name: IDR10 - ID11: - name: IDR11 - ID12: - name: IDR12 - ID13: - name: IDR13 - ID14: - name: IDR14 - ID15: - name: IDR15 - ODR: - _modify: - OD0: - name: ODR0 - OD1: - name: ODR1 - OD2: - name: ODR2 - OD3: - name: ODR3 - OD4: - name: ODR4 - OD5: - name: ODR5 - OD6: - name: ODR6 - OD7: - name: ODR7 - OD8: - name: ODR8 - OD9: - name: ODR9 - OD10: - name: ODR10 - OD11: - name: ODR11 - OD12: - name: ODR12 - OD13: - name: ODR13 - OD14: - name: ODR14 - OD15: - name: ODR15 - AFRL: - _modify: - AFSEL0: - name: AFR0 - AFSEL1: - name: AFR1 - AFSEL2: - name: AFR2 - AFSEL3: - name: AFR3 - AFSEL4: - name: AFR4 - AFSEL5: - name: AFR5 - AFSEL6: - name: AFR6 - AFSEL7: - name: AFR7 - AFRH: - _modify: - AFSEL8: - name: AFR8 - AFSEL9: - name: AFR9 - AFSEL10: - name: AFR10 - AFSEL11: - name: AFR11 - AFSEL12: - name: AFR12 - AFSEL13: - name: AFR13 - AFSEL14: - name: AFR14 - AFSEL15: - name: AFR15 - -"ADC*_Common": - CCR: - _modify: - TSEN: - name: VSENSEEN - -"ADC?": - AWD2CR: - _merge: - - "AWD2CH*" - AWD3CR: - _merge: - - "AWD3CH*" - DIFSEL: - _merge: - - "DIFSEL*" - CFGR2: - _modify: - OSR: - name: OSVR - DR: - _modify: - RDATA: - bitWidth: 32 - SQR1: - _modify: - L3: - name: L - SMPR1: - _add: - SMP0: - description: ADC channel 0 sampling time selection - bitWidth: 3 - bitOffset: 0 - SMPR2: - _modify: - SMP19: - description: ADC channel 19 sampling time selection - - CFGR: - _modify: - AWDCH1CH: - name: AWD1CH - -AXI: - _strip: - - AXI_ - -EXTI: - _modify: - CPUIMR1: - name: C1IMR1 - CPUEMR1: - name: C1EMR1 - CPUPR1: - name: C1PR1 - CPUIMR2: - name: C1IMR2 - CPUEMR2: - name: C1EMR2 - CPUPR2: - name: C1PR2 - CPUIMR3: - name: C1IMR3 - CPUEMR3: - name: C1EMR3 - CPUPR3: - name: C1PR3 - -"SPI*": - CR1: - _modify: - IOLOCK: - access: read-write - CSTART: - access: read-write - TCRCI: - name: TCRCINI - RCRCI: - name: RCRCINI - CR2: - _modify: - TSER: - access: read-write - IER: - _modify: - DPXPIE: - name: DXPIE - access: read-write - TXPIE: - access: read-write - _modify: - CGFR: - name: I2SCFGR - CFG1: - _modify: - FTHVL: - name: FTHLV - -# Work around the DMA_STR? interrupt mess in the SVD. -# Some interrupts are on DMA2 instead on DMA1 and/or called DMA_STR? without -# the numeral. - -_delete: - - DMA2 - - RAMECC? # RAMECC definitions are so terrible - -_add: - DMA2: - baseAddress: 0x40020400 - derivedFrom: DMA1 - interrupts: - DMA2_STR0: - value: 56 - description: DMA2 Stream0 - DMA2_STR1: - value: 57 - description: DMA2 Stream1 - DMA2_STR2: - value: 58 - description: DMA2 Stream2 - DMA2_STR3: - value: 59 - description: DMA2 Stream3 - DMA2_STR4: - value: 60 - description: DMA2 Stream4 - DMA2_STR5: - value: 68 - description: DMA2 Stream5 - DMA2_STR6: - value: 69 - description: DMA2 Stream6 - DMA2_STR7: - value: 70 - description: DMA2 Stream7 - -DMA1: - _add: - _interrupts: - DMA1_STR0: - value: 11 - description: DMA1 Stream0 - DMA1_STR1: - value: 12 - description: DMA1 Stream1 - DMA1_STR2: - value: 13 - description: DMA1 Stream2 - DMA1_STR3: - value: 14 - description: DMA1 Stream3 - DMA1_STR4: - value: 15 - description: DMA1 Stream4 - DMA1_STR5: - value: 16 - description: DMA1 Stream5 - DMA1_STR6: - value: 17 - description: DMA1 Stream6 - # DMA1_STR7 is correct - -Ethernet_MAC: - DMAMR: - _modify: - INTM: - bitWidth: 2 - PR: - access: read-write - TXPR: - access: read-write - DA: - access: read-write - DMASBMR: - _modify: - RB: - access: read-write - MB: - access: read-write - -RCC: - _delete: - - ICSCR - _modify: - CIFR: - access: read-only - - D3CFGR: - _delete: "*" - _add: - D3PPRE: - description: D3 domain APB4 prescaler - bitOffset: 4 - bitWidth: 3 - D1CCIPR: - _add: - DSISEL: - description: kernel clock source selection - bitOffset: 8 - bitWidth: 1 - - CSICFGR: - _modify: - CSICAL: - bitWidth: 10 - CR: - _modify: - RC48ON: - name: HSI48ON - RC48RDY: - name: HSI48RDY - CRRCR: - _modify: - RC48CAL: - name: HSI48CAL - CFGR: - _modify: - MCO1SEL: - name: MCO1 - MCO2SEL: - name: MCO2 - CIER: - _modify: - RC48RDYIE: - name: HSI48RDYIE - CIFR: - _modify: - RC48RDYF: - name: HSI48RDYF - CICR: - _modify: - RC48RDYC: - name: HSI48RDYC - BDCR: - _modify: - VSWRST: - name: BDRST - RTCSRC: - name: RTCSEL - GCR: - _add: - WW2RSC: - description: WWDG2 reset scope control - bitOffset: 1 - bitWidth: 1 - BOOT_C1: - description: Force allow CPU1 to boot - bitOffset: 2 - bitWidth: 1 - BOOT_C2: - description: Force allow CPU2 to boot - bitOffset: 3 - bitWidth: 1 - PLL2DIVR: - _modify: - DIVR1: - name: DIVR2 - DIVQ1: - name: DIVQ2 - DIVP1: - name: DIVP2 - DIVN1: - name: DIVN2 - APB1LRSTR: - _modify: - USART7RST: - name: UART7RST - description: UART7 block reset - USART8RST: - name: UART8RST - description: UART8 block reset - HDMICECRST: - name: CECRST - APB1LENR,C1_APB1LENR: - _add: - WWDG2EN: - description: WWDG2 peripheral clock enable - bitOffset: 11 - bitWidth: 1 - _modify: - USART7EN: - name: UART7EN - description: UART7 Peripheral Clocks Enable - USART8EN: - name: UART8EN - description: UART8 Peripheral Clocks Enable - HDMICECEN: - name: CECEN - APB1LLPENR,C1_APB1LLPENR: - _add: - WWDG2LPEN: - description: WWDG2 peripheral Clocks Enable During CSleep Mode - bitOffset: 11 - bitWidth: 1 - _modify: - USART7LPEN: - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - USART8LPEN: - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - HDMICECLPEN: - name: CECLPEN - C1_APB1LENR: - _modify: - HDMICECEN: - name: CECEN - APB3ENR,C1_APB3ENR: - _add: - DSIEN: - description: DSI Peripheral clocks enable - bitOffset: 4 - bitWidth: 1 - APB3LPENR,C1_APB3LPENR: - _add: - DSILPEN: - description: DSI Peripheral Clock Enable During CSleep Mode - bitOffset: 4 - bitWidth: 1 - APB3RSTR: - _add: - DSIRST: - description: DSI block reset - bitOffset: 4 - bitWidth: 1 - AHB1RSTR: - _add: - ARTRST: - description: ART block reset - bitOffset: 14 - bitWidth: 1 - AHB1ENR,C1_AHB1ENR: - _add: - ARTEN: - description: ART Clock Enable - bitOffset: 14 - bitWidth: 1 - AHB2ENR,C1_AHB2ENR: - _modify: - CAMITFEN: - name: DCMIEN - description: "DCMI peripheral clock" - AHB1LPENR: - _add: - ARTLPEN: - description: ART Clock Enable During CSleep Mode - bitOffset: 14 - bitWidth: 1 - C1_AHB1LPENR: - _add: - ARTLPEN: - description: ART Clock Enable During CSleep Mode - bitOffset: 14 - bitWidth: 1 - AHB2LPENR,C1_AHB2LPENR: - _modify: - CAMITFLPEN: - name: DCMILPEN - description: "DCMI peripheral clock enable during csleep mode" - AHB3ENR: - _add: - DTCM1EN: - description: D1 DTCM1 block enable - bitOffset: 28 - bitWidth: 1 - DTCM2EN: - description: D1 DTCM2 block enable - bitOffset: 29 - bitWidth: 1 - ITCM1EN: - description: D1 ITCM block enable - bitOffset: 30 - bitWidth: 1 - AXISRAMEN: - description: AXISRAM block enable - bitOffset: 31 - bitWidth: 1 - C1_AHB3LPENR: - _modify: - FLITFLPEN: - name: FLASHPREN - description: "Flash interface clock enable during csleep mode" - -TIM1,TIM8: - DMAR: - _modify: - # Amazingly RM0399 Rev 2 is self-inconsistent here, but use the - # register definition in 40.4.22 rather than table 350. - DMAB: - bitWidth: 32 - -HRTIM_Common: - _delete: - _registers: - - BDMADR - _add: - BDMADR: - description: Burst DMA Data register - addressOffset: 0x0070 - resetValue: 0x00000000 - access: read-write - fields: - BDMADR: - description: Burst DMA Data register - bitOffset: 0 - bitWidth: 32 - -Ethernet_MAC: - MACLETR: - _modify: - LPIET: - bitOffset: 3 - -CEC: - _strip: - - CEC_ - -CRS: - _strip: - - CRS_ - -DAC: - _strip: - - DAC_ - -DMA2D: - _strip: - - DMA2D_ - -FMC: - _strip: - - FMC_ - -JPEG: - _strip: - - JPEG_ - -HSEM: - _strip: - - HSEM_ - -MDMA: - _strip: - - MDMA_ - -LPTIM?: - _strip: - - LPTIM_ - -MDIOS: - _strip: - - MDIOS_ - -PWR: - _strip: - - PWR_ - CR3: - _add: - SDEXTRDY: - description: SMPS step-down converter external supply ready - bitOffset: 16 - bitWidth: 1 - SDLEVEL: - description: Step-down converter voltage output level selection - bitOffset: 4 - bitWidth: 2 - SDEXTHP: - description: Step-down converter forced ON and in High Power MR mode - bitOffset: 3 - bitWidth: 1 - -RTC: - _strip: - - RTC_ - -RNG: - _strip: - - RNG_ - -QUADSPI: - _strip: - - QUADSPI_ - -I2C1: - _strip: - - I2C_ - -SAI4: - _strip: - - SAI_ - -"OTG?_HS_*": - _strip: - - OTG_HS_ - -FDCAN1: - _strip: - - FDCAN_ - -WWDG1,WWDG2: - _strip: - - WWDG_ -IWDG1,IWDG2: - _strip: - - IWDG_ - -"USART*": - BRR: - _modify: - BRR_4_15: - name: BRR4 - BRR_0_3: - name: BRR0 - _merge: ["BRR*"] - -# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 - TIM4: - from: TIM2 - TIM12: - from: TIM2 - TIM13: - from: TIM2 - TIM14: - from: TIM2 - -SYSCFG: - _add: - PWRCR: - description: SYSCFG Power Control Register - addressOffset: 0x2C - access: read-write - resetValue: 0x00000000 - fields: - ODEN: - description: Overdrive enable, this bit allows to activate the LDO regulator overdrive mode. This bit must be written only in VOS1 voltage scaling mode - bitOffset: 0 - bitWidth: 1 diff --git a/devices/common_patches/h7_common_highmemory.yaml b/devices/common_patches/h7_common_highmemory.yaml deleted file mode 100644 index 4128ba1fb..000000000 --- a/devices/common_patches/h7_common_highmemory.yaml +++ /dev/null @@ -1,787 +0,0 @@ -# Common SVD errors for high memory density parts h7a3/h7b3/h7b0 -# -# See RM0455 - -# Rename in accordance with other devices and reference manual. -_modify: - Flash: - name: FLASH - TT_FDCAN: - name: FDCAN1 - FDCAN: - name: FDCAN2 - -# The SVD is just quite different to the RM for all these registers. -# We'll go with the RM convention even though it is inconsistent too. -"GPIO*": - MODER: - _modify: - MODE0: - name: MODER0 - MODE1: - name: MODER1 - MODE2: - name: MODER2 - MODE3: - name: MODER3 - MODE4: - name: MODER4 - MODE5: - name: MODER5 - MODE6: - name: MODER6 - MODE7: - name: MODER7 - MODE8: - name: MODER8 - MODE9: - name: MODER9 - MODE10: - name: MODER10 - MODE11: - name: MODER11 - MODE12: - name: MODER12 - MODE13: - name: MODER13 - MODE14: - name: MODER14 - MODE15: - name: MODER15 - OSPEEDR: - _modify: - OSPEED0: - name: OSPEEDR0 - OSPEED1: - name: OSPEEDR1 - OSPEED2: - name: OSPEEDR2 - OSPEED3: - name: OSPEEDR3 - OSPEED4: - name: OSPEEDR4 - OSPEED5: - name: OSPEEDR5 - OSPEED6: - name: OSPEEDR6 - OSPEED7: - name: OSPEEDR7 - OSPEED8: - name: OSPEEDR8 - OSPEED9: - name: OSPEEDR9 - OSPEED10: - name: OSPEEDR10 - OSPEED11: - name: OSPEEDR11 - OSPEED12: - name: OSPEEDR12 - OSPEED13: - name: OSPEEDR13 - OSPEED14: - name: OSPEEDR14 - OSPEED15: - name: OSPEEDR15 - PUPDR: - _modify: - PUPD0: - name: PUPDR0 - PUPD1: - name: PUPDR1 - PUPD2: - name: PUPDR2 - PUPD3: - name: PUPDR3 - PUPD4: - name: PUPDR4 - PUPD5: - name: PUPDR5 - PUPD6: - name: PUPDR6 - PUPD7: - name: PUPDR7 - PUPD8: - name: PUPDR8 - PUPD9: - name: PUPDR9 - PUPD10: - name: PUPDR10 - PUPD11: - name: PUPDR11 - PUPD12: - name: PUPDR12 - PUPD13: - name: PUPDR13 - PUPD14: - name: PUPDR14 - PUPD15: - name: PUPDR15 - IDR: - _modify: - ID0: - name: IDR0 - ID1: - name: IDR1 - ID2: - name: IDR2 - ID3: - name: IDR3 - ID4: - name: IDR4 - ID5: - name: IDR5 - ID6: - name: IDR6 - ID7: - name: IDR7 - ID8: - name: IDR8 - ID9: - name: IDR9 - ID10: - name: IDR10 - ID11: - name: IDR11 - ID12: - name: IDR12 - ID13: - name: IDR13 - ID14: - name: IDR14 - ID15: - name: IDR15 - ODR: - _modify: - OD0: - name: ODR0 - OD1: - name: ODR1 - OD2: - name: ODR2 - OD3: - name: ODR3 - OD4: - name: ODR4 - OD5: - name: ODR5 - OD6: - name: ODR6 - OD7: - name: ODR7 - OD8: - name: ODR8 - OD9: - name: ODR9 - OD10: - name: ODR10 - OD11: - name: ODR11 - OD12: - name: ODR12 - OD13: - name: ODR13 - OD14: - name: ODR14 - OD15: - name: ODR15 - AFRL: - _modify: - AFSEL0: - name: AFR0 - AFSEL1: - name: AFR1 - AFSEL2: - name: AFR2 - AFSEL3: - name: AFR3 - AFSEL4: - name: AFR4 - AFSEL5: - name: AFR5 - AFSEL6: - name: AFR6 - AFSEL7: - name: AFR7 - AFRH: - _modify: - AFSEL8: - name: AFR8 - AFSEL9: - name: AFR9 - AFSEL10: - name: AFR10 - AFSEL11: - name: AFR11 - AFSEL12: - name: AFR12 - AFSEL13: - name: AFR13 - AFSEL14: - name: AFR14 - AFSEL15: - name: AFR15 - -"ADC*_Common": - CCR: - _modify: - TSEN: - name: VSENSEEN - -"ADC?": - AWD2CR: - _merge: - - "AWD2CH*" - AWD3CR: - _merge: - - "AWD3CH*" - DIFSEL: - _merge: - - "DIFSEL*" - CFGR2: - _modify: - OSR: - name: OSVR - DR: - _modify: - RDATA: - bitWidth: 32 - SQR1: - _modify: - L3: - name: L - SMPR1: - _add: - SMP0: - description: ADC channel 0 sampling time selection - bitWidth: 3 - bitOffset: 0 - SMPR2: - _modify: - SMP19: - description: ADC channel 19 sampling time selection - - CFGR: - _modify: - AWDCH1CH: - name: AWD1CH - -AXI: - _strip: - - AXI_ - -"SPI*": - CR1: - _modify: - IOLOCK: - access: read-write - CSTART: - access: read-write - TCRCI: - name: TCRCINI - RCRCI: - name: RCRCINI - CR2: - _modify: - TSER: - access: read-write - IER: - _modify: - DPXPIE: - name: DXPIE - access: read-write - TXPIE: - access: read-write - _modify: - CGFR: - name: I2SCFGR - CFG1: - _modify: - FTHVL: - name: FTHLV - -# Work around the DMA_STR? interrupt mess in the SVD. -# Some interrupts are on DMA2 instead on DMA1 and/or called DMA_STR? without -# the numeral. - -_delete: - - DMA2 - -_add: - DMA2: - baseAddress: 0x40020400 - derivedFrom: DMA1 - interrupts: - DMA2_STR0: - value: 56 - description: DMA2 Stream0 - DMA2_STR1: - value: 57 - description: DMA2 Stream1 - DMA2_STR2: - value: 58 - description: DMA2 Stream2 - DMA2_STR3: - value: 59 - description: DMA2 Stream3 - DMA2_STR4: - value: 60 - description: DMA2 Stream4 - DMA2_STR5: - value: 68 - description: DMA2 Stream5 - DMA2_STR6: - value: 69 - description: DMA2 Stream6 - DMA2_STR7: - value: 70 - description: DMA2 Stream7 - -DMA1: - _add: - _interrupts: - DMA1_STR0: - value: 11 - description: DMA1 Stream0 - DMA1_STR1: - value: 12 - description: DMA1 Stream1 - DMA1_STR2: - value: 13 - description: DMA1 Stream2 - DMA1_STR3: - value: 14 - description: DMA1 Stream3 - DMA1_STR4: - value: 15 - description: DMA1 Stream4 - DMA1_STR5: - value: 16 - description: DMA1 Stream5 - DMA1_STR6: - value: 17 - description: DMA1 Stream6 - # DMA1_STR7 is correct - -RCC: - _delete: - - ICSCR - _modify: - CIFR: - access: read-only - D1CCIPR: - name: CDCCIPR - D2CCIP1R: - name: CDCCIP1R - D2CCIP2R: - name: CDCCIP2R - D3CCIPR: - name: SRDCCIPR - C1_APB1LENR: - name: APB1LENR - C1_APB1LLPENR: - name: APB1LLPENR - C1_APB1HENR: - name: APB1HENR - C1_APB1HLPENR: - name: APB1HLPENR - C1_APB2ENR: - name: APB2ENR - C1_APB2LPENR: - name: APB2LPENR - C1_APB3ENR: - name: APB3ENR - C1_APB3LPENR: - name: APB3LPENR - C1_APB4ENR: - name: APB4ENR - C1_APB4LPENR: - name: APB4LPENR - C1_AHB1ENR: - name: AHB1ENR - C1_AHB2ENR: - name: AHB2ENR - C1_AHB1LPENR: - name: AHB1LPENR - C1_AHB2LPENR: - name: AHB2LPENR - C1_AHB3ENR: - name: AHB3ENR - C1_AHB3LPENR: - name: AHB3LPENR - C1_AHB4ENR: - name: AHB4ENR - C1_AHB4LPENR: - name: AHB4LPENR - - _add: - # This doesn't exist in RM0455 Rev 3, but the WW1RSC field is - # referenced in Section 8.7.42. So we assume it does exist in the same - # place as the other parts in the family. - GCR: - description: Global Control Register - addressOffset: 0x00A0 - resetValue: 0x00000000 - access: read-write - fields: - WW1RSC: - description: WWDG1 reset scope control - bitOffset: 0 - bitWidth: 1 - - CDCCIPR: - _delete: - - "QSPI*" - _add: - OCTOSPISEL: - description: "OCTOSPI kernel clock source selection" - bitOffset: 4 - bitWidth: 2 - _modify: - CKPERSRC: - name: CKPERSEL - SDMMCSRC: - name: SDMMCSEL - FMCSRC: - name: FMCSEL - CDCCIP1R: - _delete: - - "SAI23*" - _add: - SAI2ASEL: - description: "SAI2 kernel clock source A source selection" - bitOffset: 6 - bitWidth: 3 - SAI2BSEL: - description: "SAI2 kernel clock source B source selection" - bitOffset: 9 - bitWidth: 3 - _modify: - SWPSRC: - name: SWPSEL - FDCANSRC: - name: FDCANSEL - DFSDM1SRC: - name: DFSDM1SEL - SPDIFSRC: - name: SPDIFRXSEL - SPI45SRC: - name: SPI45SEL - SPI123SRC: - name: SPI123SEL - SAI1SRC: - name: SAI1SEL - CDCCIP2R: - _modify: - LPTIM1SRC: - name: LPTIM1SEL - CECSRC: - name: CECSEL - USBSRC: - name: USBSEL - I2C123SRC: - name: I2C123SEL - RNGSRC: - name: RNGSEL - USART16SRC: - name: USART16910SEL - description: "USART1, 6, 9 and 10 kernel clock source selection" - USART234578SRC: - name: USART234578SEL - SRDCCIPR: - _delete: - - "SAI4*" - _add: - DFSDM2SEL: - description: "DFSDM2 kernel clock source selection" - bitOffset: 27 - bitWidth: 1 - _modify: - SPI6SRC: - name: SPI6SEL - ADCSRC: - name: ADCSEL - LPTIM345SRC: - name: LPTIM3SEL # LPTIM3 only - LPTIM2SRC: - name: LPTIM2SEL - I2C4SRC: - name: I2C4SEL - LPUART1SRC: - name: LPUART1SEL - - D3CFGR: - _delete: "*" - _add: - D3PPRE: - description: D3 domain APB4 prescaler - bitOffset: 4 - bitWidth: 3 - - CR: - _modify: - RC48ON: - name: HSI48ON - RC48RDY: - name: HSI48RDY - CRRCR: - _modify: - RC48CAL: - name: HSI48CAL - CFGR: - _modify: - MCO1SEL: - name: MCO1 - MCO2SEL: - name: MCO2 - CIER: - _modify: - RC48RDYIE: - name: HSI48RDYIE - CIFR: - _modify: - RC48RDYF: - name: HSI48RDYF - CICR: - _modify: - RC48RDYC: - name: HSI48RDYC - BDCR: - _modify: - VSWRST: - name: BDRST - RTCSRC: - name: RTCSEL - PLL2DIVR: - _modify: - DIVR1: - name: DIVR2 - DIVQ1: - name: DIVQ2 - DIVP1: - name: DIVP2 - DIVN1: - name: DIVN2 - APB1LRSTR: - _modify: - USART7RST: - name: UART7RST - description: UART7 block reset - USART8RST: - name: UART8RST - description: UART8 block reset - HDMICECRST: - name: CECRST - APB1LENR: - _modify: - USART7EN: - name: UART7EN - description: UART7 Peripheral Clocks Enable - USART8EN: - name: UART8EN - description: UART8 Peripheral Clocks Enable - HDMICECEN: - name: CECEN - APB1LLPENR: - _modify: - USART7LPEN: - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - USART8LPEN: - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - HDMICECLPEN: - name: CECLPEN - AHB1ENR: - _delete: # highmemory only has one USB HS - - USB2OTGEN - - USB2ULPIEN - AHB2ENR: - _modify: - CAMITFEN: - name: DCMIEN - description: "DCMI peripheral clock" - AHB1LPENR: - _delete: # highmemory only has one USB HS - - USB2OTGLPEN - - USB2ULPILPEN - AHB2LPENR: - _modify: - CAMITFLPEN: - name: DCMILPEN - description: "DCMI peripheral clock enable during csleep mode" - AHB3ENR: - _add: - DTCM1EN: - description: D1 DTCM1 block enable - bitOffset: 28 - bitWidth: 1 - DTCM2EN: - description: D1 DTCM2 block enable - bitOffset: 29 - bitWidth: 1 - ITCM1EN: - description: D1 ITCM block enable - bitOffset: 30 - bitWidth: 1 - AXISRAMEN: - description: AXISRAM block enable - bitOffset: 31 - bitWidth: 1 - AHB3LPENR: - _modify: - FLITFLPEN: - name: FLASHPREN - description: "Flash interface clock enable during csleep mode" - -TIM1,TIM8: - DMAR: - _modify: - # Amazingly RM0399 Rev 2 is self-inconsistent here, but use the - # register definition in 40.4.22 rather than table 350. - DMAB: - bitWidth: 32 - -HRTIM_Common: - _delete: - _registers: - - BDMADR - _add: - BDMADR: - description: Burst DMA Data register - addressOffset: 0x0070 - resetValue: 0x00000000 - access: read-write - fields: - BDMADR: - description: Burst DMA Data register - bitOffset: 0 - bitWidth: 32 - -BDMA?: - _strip: - - BDMA_ - -CEC: - _strip: - - CEC_ - -CRS: - _strip: - - CRS_ - -DAC: - _strip: - - DAC_ - -DMA2D: - _strip: - - DMA2D_ - -DMAMUX1: - _strip: - - DMAMUX1_ - -DMAMUX2: - _strip: - - DMAMUX2_ - -FMC: - _strip: - - FMC_ - -JPEG: - _strip: - - JPEG_ - -HSEM: - _strip: - - HSEM_ - -MDMA: - _strip: - - MDMA_ - -LPTIM?: - _strip: - - LPTIM_ - -MDIOS: - _strip: - - MDIOS_ - -PWR: - _strip: - - PWR_ - CR3: - # Annoyingly RM0455 names these fields differently to RM0399 whilst - # they have the same function - _add: - SMPSEXTRDY: - description: SMPS step-down converter external supply ready - bitOffset: 16 - bitWidth: 1 - SMPSLEVEL: - description: Step-down converter voltage output level selection - bitOffset: 4 - bitWidth: 2 - SMPSEXTHP: - description: Step-down converter forced ON and in High Power MR mode - bitOffset: 3 - bitWidth: 1 - -RTC: - _strip: - - RTC_ - -RNG: - _strip: - - RNG_ - -I2C3: - _strip: - - I2C_ - -SAI1: - _strip: - - SAI_ - -SDMMC?: - _strip: - - SDMMC_ - -VREFBUF: - _strip: - - VREFBUF_ - -"OTG?_HS_*": - _strip: - - OTG_HS_ - -WWDG: - _strip: - - WWDG_ -IWDG: - _strip: - - IWDG_ - -"USART*": - BRR: - _modify: - BRR_4_15: - name: BRR4 - BRR_0_3: - name: BRR0 - _merge: ["BRR*"] - -# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 - TIM4: - from: TIM2 - TIM12: - from: TIM2 - TIM13: - from: TIM2 - TIM14: - from: TIM2 diff --git a/devices/common_patches/h7_common_singlecore.yaml b/devices/common_patches/h7_common_singlecore.yaml deleted file mode 100644 index 86c81442b..000000000 --- a/devices/common_patches/h7_common_singlecore.yaml +++ /dev/null @@ -1,541 +0,0 @@ -# Common SVD errors for single core stm32h742/742/753/750 - -# Rename in accordance with other devices and reference manual. -_modify: - Flash: - name: FLASH - -"GPIOA": - _strip: - # The SVD incorrectly names all the GPIO registers compared to RM0433. - - GPIOA_ - -# The SVD is just quite different to the RM for all these registers. -# We'll go with the RM convention even though it is inconsistent too. -"GPIO*": - MODER: - _modify: - MODE0: - name: MODER0 - MODE1: - name: MODER1 - MODE2: - name: MODER2 - MODE3: - name: MODER3 - MODE4: - name: MODER4 - MODE5: - name: MODER5 - MODE6: - name: MODER6 - MODE7: - name: MODER7 - MODE8: - name: MODER8 - MODE9: - name: MODER9 - MODE10: - name: MODER10 - MODE11: - name: MODER11 - MODE12: - name: MODER12 - MODE13: - name: MODER13 - MODE14: - name: MODER14 - MODE15: - name: MODER15 - OSPEEDR: - _modify: - OSPEED0: - name: OSPEEDR0 - OSPEED1: - name: OSPEEDR1 - OSPEED2: - name: OSPEEDR2 - OSPEED3: - name: OSPEEDR3 - OSPEED4: - name: OSPEEDR4 - OSPEED5: - name: OSPEEDR5 - OSPEED6: - name: OSPEEDR6 - OSPEED7: - name: OSPEEDR7 - OSPEED8: - name: OSPEEDR8 - OSPEED9: - name: OSPEEDR9 - OSPEED10: - name: OSPEEDR10 - OSPEED11: - name: OSPEEDR11 - OSPEED12: - name: OSPEEDR12 - OSPEED13: - name: OSPEEDR13 - OSPEED14: - name: OSPEEDR14 - OSPEED15: - name: OSPEEDR15 - PUPDR: - _modify: - PUPD0: - name: PUPDR0 - PUPD1: - name: PUPDR1 - PUPD2: - name: PUPDR2 - PUPD3: - name: PUPDR3 - PUPD4: - name: PUPDR4 - PUPD5: - name: PUPDR5 - PUPD6: - name: PUPDR6 - PUPD7: - name: PUPDR7 - PUPD8: - name: PUPDR8 - PUPD9: - name: PUPDR9 - PUPD10: - name: PUPDR10 - PUPD11: - name: PUPDR11 - PUPD12: - name: PUPDR12 - PUPD13: - name: PUPDR13 - PUPD14: - name: PUPDR14 - PUPD15: - name: PUPDR15 - IDR: - _modify: - ID0: - name: IDR0 - ID1: - name: IDR1 - ID2: - name: IDR2 - ID3: - name: IDR3 - ID4: - name: IDR4 - ID5: - name: IDR5 - ID6: - name: IDR6 - ID7: - name: IDR7 - ID8: - name: IDR8 - ID9: - name: IDR9 - ID10: - name: IDR10 - ID11: - name: IDR11 - ID12: - name: IDR12 - ID13: - name: IDR13 - ID14: - name: IDR14 - ID15: - name: IDR15 - ODR: - _modify: - OD0: - name: ODR0 - OD1: - name: ODR1 - OD2: - name: ODR2 - OD3: - name: ODR3 - OD4: - name: ODR4 - OD5: - name: ODR5 - OD6: - name: ODR6 - OD7: - name: ODR7 - OD8: - name: ODR8 - OD9: - name: ODR9 - OD10: - name: ODR10 - OD11: - name: ODR11 - OD12: - name: ODR12 - OD13: - name: ODR13 - OD14: - name: ODR14 - OD15: - name: ODR15 - AFRL: - _modify: - AFSEL0: - name: AFR0 - AFSEL1: - name: AFR1 - AFSEL2: - name: AFR2 - AFSEL3: - name: AFR3 - AFSEL4: - name: AFR4 - AFSEL5: - name: AFR5 - AFSEL6: - name: AFR6 - AFSEL7: - name: AFR7 - AFRH: - _modify: - AFSEL8: - name: AFR8 - AFSEL9: - name: AFR9 - AFSEL10: - name: AFR10 - AFSEL11: - name: AFR11 - AFSEL12: - name: AFR12 - AFSEL13: - name: AFR13 - AFSEL14: - name: AFR14 - AFSEL15: - name: AFR15 - -"ADC*_Common": - CCR: - _modify: - TSEN: - name: VSENSEEN - -"ADC?": - CFGR2: - _modify: - OSR: - name: OSVR - SQR1: - _modify: - L3: - name: L - SMPR1: - _add: - SMP0: - description: ADC channel 0 sampling time - bitOffset: 0 - bitWidth: 3 - access: read-write - SMPR2: - _modify: - SMP19: - description: ADC channel 19 sampling time - - CFGR: - _modify: - AWDCH1CH: - name: AWD1CH - -FLASH: - _modify: - PRAR_PRG2: - addressOffset: "0x12C" - alternateRegister: "" - KEYR[12]: - access: write-only - OPTKEYR_?: - access: write-only - BOOT_PRGR: - access: read-write - -"SPI*": - CR1: - _modify: - CSTART: - access: read-write - TCRCI: - name: TCRCINI - RCRCI: - name: RCRCINI - IER: - _modify: - DPXPIE: - name: DXPIE - access: read-write - TXPIE: - access: read-write - _modify: - CGFR: - name: I2SCFGR - CFG1: - _modify: - FTHVL: - name: FTHLV - -# Work around the DMA_STR? interrupt mess in the SVD. -# Some interrupts are on DMA2 instead on DMA1 and/or called DMA_STR? without -# the numeral. - -_delete: - - DMA2 - -_add: - DMA2: - baseAddress: 0x40020400 - derivedFrom: DMA1 - interrupts: - DMA2_STR0: - value: 56 - description: DMA2 Stream0 - DMA2_STR1: - value: 57 - description: DMA2 Stream1 - DMA2_STR2: - value: 58 - description: DMA2 Stream2 - DMA2_STR3: - value: 59 - description: DMA2 Stream3 - DMA2_STR4: - value: 60 - description: DMA2 Stream4 - DMA2_STR5: - value: 68 - description: DMA2 Stream5 - DMA2_STR6: - value: 69 - description: DMA2 Stream6 - DMA2_STR7: - value: 70 - description: DMA2 Stream7 - -DMA1: - _add: - _interrupts: - DMA1_STR0: - value: 11 - description: DMA1 Stream0 - DMA1_STR1: - value: 12 - description: DMA1 Stream1 - DMA1_STR2: - value: 13 - description: DMA1 Stream2 - DMA1_STR3: - value: 14 - description: DMA1 Stream3 - DMA1_STR4: - value: 15 - description: DMA1 Stream4 - DMA1_STR5: - value: 16 - description: DMA1 Stream5 - DMA1_STR6: - value: 17 - description: DMA1 Stream6 - # DMA1_STR7 is correct - -Ethernet_DMA: - DMAMR: - _modify: - INTM: - bitWidth: 2 - PR: - access: read-write - TXPR: - access: read-write - DA: - access: read-write - DMASBMR: - _modify: - RB: - access: read-write - MB: - access: read-write - -RCC: - _modify: - CIFR: - access: read-only - CR: - _modify: - RC48ON: - name: HSI48ON - RC48RDY: - name: HSI48RDY - CRRCR: - _modify: - RC48CAL: - name: HSI48CAL - CFGR: - _modify: - MCO1SEL: - name: MCO1 - MCO2SEL: - name: MCO2 - CIER: - _modify: - RC48RDYIE: - name: HSI48RDYIE - CIFR: - _modify: - RC48RDYF: - name: HSI48RDYF - CICR: - _modify: - RC48RDYC: - name: HSI48RDYC - BDCR: - _modify: - VSWRST: - name: BDRST - RTCSRC: - name: RTCSEL - PLL2DIVR: - _modify: - DIVP1: - name: DIVP2 - DIVQ1: - name: DIVQ2 - DIVR1: - name: DIVR2 - DIVN1: - name: DIVN2 - APB1LRSTR: - _modify: - USART7RST: - name: UART7RST - description: UART7 block reset - USART8RST: - name: UART8RST - description: UART8 block reset - APB1LENR,C1_APB1LENR: - _modify: - USART7EN: - name: UART7EN - description: UART7 Peripheral Clocks Enable - USART8EN: - name: UART8EN - description: UART8 Peripheral Clocks Enable - APB1LLPENR: - _modify: - USART7LPEN: - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - USART8LPEN: - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - C1_APB1LLPENR: - _modify: - USART7LPEN: - name: UART7LPEN - description: UART7 Peripheral Clocks Enable During CSleep Mode - USART8LPEN: - name: UART8LPEN - description: UART8 Peripheral Clocks Enable During CSleep Mode - C1_APB1LENR: - _modify: - HDMICECEN: - name: CECEN - AHB1ENR,C1_AHB1ENR: - _modify: - USB1OTGHSEN: - name: USB1OTGEN - USB2OTGHSEN: - name: USB2OTGEN - USB1ULPIHSEN: - name: USB1ULPIEN - USB2ULPIHSEN: - name: USB2ULPIEN - AHB2ENR,C1_AHB2ENR: - _modify: - CAMITFEN: - name: DCMIEN - description: "DCMI peripheral clock" - APB1LLPENR,C1_APB1LLPENR: - _modify: - HDMICECLPEN: - name: CECLPEN - AHB1LPENR,C1_AHB1LPENR: - _modify: - USB1OTGHSLPEN: - name: USB1OTGLPEN - USB2OTGHSLPEN: - name: USB2OTGLPEN - USB1ULPIHSLPEN: - name: USB1ULPILPEN - USB2ULPIHSLPEN: - name: USB2ULPILPEN - AHB2LPENR,C1_AHB2LPENR: - _modify: - CAMITFLPEN: - name: DCMILPEN - description: "DCMI peripheral clock enable during csleep mode" - C1_AHB3LPENR: - _modify: - FLITFLPEN: - name: FLASHPREN - description: "Flash interface clock enable during csleep mode" - -Ethernet_MAC: - MACLETR: - _modify: - LPIET: - bitOffset: 3 - -HSEM: - _strip: - - HSEM_ - -MDMA: - _strip: - - MDMA_ - -RTC: - _strip: - - RTC_ - -SAI4: - _strip: - - SAI_ - -AXI: - _strip: - - AXI_ - -"OTG1_HS_*": - _strip: - - OTG_HS_ - -FDCAN1: - _strip: - - FDCAN_ - -# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 - TIM4: - from: TIM2 - TIM12: - from: TIM2 - TIM13: - from: TIM2 - TIM14: - from: TIM2 diff --git a/devices/common_patches/h7_dbgmcu.yaml b/devices/common_patches/h7_dbgmcu.yaml deleted file mode 100644 index 6f5cf93cd..000000000 --- a/devices/common_patches/h7_dbgmcu.yaml +++ /dev/null @@ -1,192 +0,0 @@ -# Add H7 DBGMCU peripheral. From RM0433 rev 7 - -_add: - DBGMCU: - description: Debug support - groupName: DBG - baseAddress: 0x5C001000 - addressBlock: - offset: 0x000 - size: 0x100 - usage: registers - registers: - IDC: - description: Identity code - addressOffset: 0x0 - access: read-only - resetValue: 0x10006480 - fields: - REV_ID: - description: Revision ID - bitOffset: 16 - bitWidth: 16 - DEV_ID: - description: Device ID - bitOffset: 0 - bitWidth: 12 - CR: - description: Configuration register - addressOffset: 0x004 - access: read-write - resetValue: 0x00000000 - fields: - TRGOEN: - description: External trigger output enable - bitOffset: 28 - bitWidth: 1 - D3DBGCKEN: - description: D3 debug clock enable enable - bitOffset: 22 - bitWidth: 1 - D1DBGCKEN: - description: D1 debug clock enable enable - bitOffset: 21 - bitWidth: 1 - TRACECLKEN: - description: Trace clock enable enable - bitOffset: 20 - bitWidth: 1 - DBGSTBY_D1: - description: Allow debug in D1 Standby mode - bitOffset: 2 - bitWidth: 1 - DBGSTOP_D1: - description: Allow debug in D1 Stop mode - bitOffset: 1 - bitWidth: 1 - DBGSLEEP_D1: - description: Allow debug in D1 Sleep mode - bitOffset: 0 - bitWidth: 1 - APB3FZ1: - description: APB3 peripheral freeze register - addressOffset: 0x034 - access: read-write - resetValue: 0x00000000 - fields: - WWDG1: - description: WWDG1 stop in debug mode - bitOffset: 6 - bitWidth: 1 - APB1LFZ1: - description: APB1L peripheral freeze register - addressOffset: 0x03C - access: read-write - resetValue: 0x00000000 - fields: - I2C3: - description: I2C3 SMBUS timeout stop in debug mode - bitOffset: 23 - bitWidth: 1 - I2C2: - description: I2C2 SMBUS timeout stop in debug mode - bitOffset: 22 - bitWidth: 1 - I2C1: - description: I2C1 SMBUS timeout stop in debug mode - bitOffset: 21 - bitWidth: 1 - LPTIM1: - description: LPTIM1 stop in debug mode - bitOffset: 9 - bitWidth: 1 - TIM14: - description: TIM14 stop in debug mode - bitOffset: 8 - bitWidth: 1 - TIM13: - description: TIM13 stop in debug mode - bitOffset: 7 - bitWidth: 1 - TIM12: - description: TIM12 stop in debug mode - bitOffset: 6 - bitWidth: 1 - TIM7: - description: TIM7 stop in debug mode - bitOffset: 5 - bitWidth: 1 - TIM6: - description: TIM6 stop in debug mode - bitOffset: 4 - bitWidth: 1 - TIM5: - description: TIM5 stop in debug mode - bitOffset: 3 - bitWidth: 1 - TIM4: - description: TIM4 stop in debug mode - bitOffset: 2 - bitWidth: 1 - TIM3: - description: TIM3 stop in debug mode - bitOffset: 1 - bitWidth: 1 - TIM2: - description: TIM2 stop in debug mode - bitOffset: 0 - bitWidth: 1 - APB2FZ1: - description: APB2 peripheral freeze register - addressOffset: 0x04C - access: read-write - resetValue: 0x00000000 - fields: - HRTIM: - description: HRTIM stop in debug mode - bitOffset: 29 - bitWidth: 1 - TIM17: - description: TIM17 stop in debug mode - bitOffset: 18 - bitWidth: 1 - TIM16: - description: TIM16 stop in debug mode - bitOffset: 17 - bitWidth: 1 - TIM15: - description: TIM15 stop in debug mode - bitOffset: 16 - bitWidth: 1 - TIM8: - description: TIM8 stop in debug mode - bitOffset: 1 - bitWidth: 1 - TIM1: - description: TIM1 stop in debug mode - bitOffset: 0 - bitWidth: 1 - APB4FZ1: - description: APB4 peripheral freeze register - addressOffset: 0x054 - access: read-write - resetValue: 0x00000000 - fields: - IWDG1: - description: Independent watchdog for D1 stop in debug mode - bitOffset: 18 - bitWidth: 1 - RTC: - description: RTC stop in debug mode - bitOffset: 16 - bitWidth: 1 - LPTIM5: - description: LPTIM5 stop in debug mode - bitOffset: 12 - bitWidth: 1 - LPTIM4: - description: LPTIM4 stop in debug mode - bitOffset: 11 - bitWidth: 1 - LPTIM3: - description: LPTIM3 stop in debug mode - bitOffset: 10 - bitWidth: 1 - LPTIM2: - description: LPTIM2 stop in debug mode - bitOffset: 9 - bitWidth: 1 - I2C4: - description: I2C4 SMBUS timeout stop in debug mode - bitOffset: 7 - bitWidth: 1 diff --git a/devices/common_patches/h7_dbgmcu_dualcore.yaml b/devices/common_patches/h7_dbgmcu_dualcore.yaml deleted file mode 100644 index faf19ba22..000000000 --- a/devices/common_patches/h7_dbgmcu_dualcore.yaml +++ /dev/null @@ -1,170 +0,0 @@ -# Add dualcore parts of DBGMCU periperal. From RM0399 rev 2 - -DBGMCU: - CR: - _add: - DBGSTBY_D2: - description: Allow debug in D2 Standby mode - bitOffset: 5 - bitWidth: 1 - DBGSTOP_D2: - description: Allow debug in D2 Stop mode - bitOffset: 4 - bitWidth: 1 - DBGSLEEP_D2: - description: Allow debug in D2 Sleep mode - bitOffset: 3 - bitWidth: 1 - APB4FZ1: - _add: - IWDG2: - description: Independent watchdog for D2 stop when Cortex-M7 in debug mode - bitOffset: 19 - bitWidth: 1 - APB1LFZ1: - _add: - WWDG2: - description: WWDG2 stop when Cortex-M7 in debug mode - bitOffset: 11 - bitWidth: 1 - _add: - APB3FZ2: - description: APB3 peripheral freeze register CPU2 - addressOffset: 0x038 - access: read-write - resetValue: 0x00000000 - fields: - WWDG1: - description: WWDG1 stop when Cortex-M4 in debug mode - bitOffset: 6 - bitWidth: 1 - APB1LFZ2: - description: APB1L peripheral freeze register CPU2 - addressOffset: 0x040 - access: read-write - resetValue: 0x00000000 - fields: - I2C3: - description: I2C3 SMBUS timeout stop when Cortex-M4 in debug mode - bitOffset: 23 - bitWidth: 1 - I2C2: - description: I2C2 SMBUS timeout stop when Cortex-M4 in debug mode - bitOffset: 22 - bitWidth: 1 - I2C1: - description: I2C1 SMBUS timeout stop when Cortex-M4 in debug mode - bitOffset: 21 - bitWidth: 1 - WWDG2: - description: WWDG2 stop in when Cortex-M4 when Cortex-M4 in debug mode - bitOffset: 11 - bitWidth: 1 - LPTIM1: - description: LPTIM1 stop when Cortex-M4 in debug mode - bitOffset: 9 - bitWidth: 1 - TIM14: - description: TIM14 stop when Cortex-M4 in debug mode - bitOffset: 8 - bitWidth: 1 - TIM13: - description: TIM13 stop when Cortex-M4 in debug mode - bitOffset: 7 - bitWidth: 1 - TIM12: - description: TIM12 stop when Cortex-M4 in debug mode - bitOffset: 6 - bitWidth: 1 - TIM7: - description: TIM7 stop when Cortex-M4 in debug mode - bitOffset: 5 - bitWidth: 1 - TIM6: - description: TIM6 stop when Cortex-M4 in debug mode - bitOffset: 4 - bitWidth: 1 - TIM5: - description: TIM5 stop when Cortex-M4 in debug mode - bitOffset: 3 - bitWidth: 1 - TIM4: - description: TIM4 stop when Cortex-M4 in debug mode - bitOffset: 2 - bitWidth: 1 - TIM3: - description: TIM3 stop when Cortex-M4 in debug mode - bitOffset: 1 - bitWidth: 1 - TIM2: - description: TIM2 stop when Cortex-M4 in debug mode - bitOffset: 0 - bitWidth: 1 - APB2FZ2: - description: APB2 peripheral freeze register CPU2 - addressOffset: 0x048 - access: read-write - resetValue: 0x00000000 - fields: - HRTIM: - description: HRTIM stop when Cortex-M4 in debug mode - bitOffset: 29 - bitWidth: 1 - TIM17: - description: TIM17 stop when Cortex-M4 in debug mode - bitOffset: 18 - bitWidth: 1 - TIM16: - description: TIM16 stop when Cortex-M4 in debug mode - bitOffset: 17 - bitWidth: 1 - TIM15: - description: TIM15 stop when Cortex-M4 in debug mode - bitOffset: 16 - bitWidth: 1 - TIM8: - description: TIM8 stop when Cortex-M4 in debug mode - bitOffset: 1 - bitWidth: 1 - TIM1: - description: TIM1 stop when Cortex-M4 in debug mode - bitOffset: 0 - bitWidth: 1 - APB4FZ2: - description: APB4 peripheral freeze register CPU2 - addressOffset: 0x058 - access: read-write - resetValue: 0x00000000 - fields: - WDGLSD2: - description: LS watchdog for D2 stop when Cortex-M4 in debug mode - bitOffset: 19 - bitWidth: 1 - WDGLSD1: - description: LS watchdog for D1 stop when Cortex-M4 in debug mode - bitOffset: 18 - bitWidth: 1 - RTC: - description: RTC stop when Cortex-M4 in debug mode - bitOffset: 16 - bitWidth: 1 - LPTIM5: - description: LPTIM5 stop when Cortex-M4 in debug mode - bitOffset: 12 - bitWidth: 1 - LPTIM4: - description: LPTIM4 stop when Cortex-M4 in debug mode - bitOffset: 11 - bitWidth: 1 - LPTIM3: - description: LPTIM3 stop when Cortex-M4 in debug mode - bitOffset: 10 - bitWidth: 1 - LPTIM2: - description: LPTIM2 stop when Cortex-M4 in debug mode - bitOffset: 9 - bitWidth: 1 - I2C4: - description: I2C4 SMBUS timeout stop when Cortex-M4 in debug mode - bitOffset: 7 - bitWidth: 1 diff --git a/devices/common_patches/h7_dmacr.yaml b/devices/common_patches/h7_dmacr.yaml deleted file mode 100644 index c31df96b1..000000000 --- a/devices/common_patches/h7_dmacr.yaml +++ /dev/null @@ -1,11 +0,0 @@ -"DMA?": - "*CR": - _add: - TRBUFF: - description: Enable the DMA to handle bufferable transfers - bitOffset: 20 - bitWidth: 1 - access: read-write - TRBUFF: - Disabled: [0, "Bufferable transfers not enabled"] - Enabled: [1, "Bufferable transfers enabled"] diff --git a/devices/common_patches/h7_dmamux.yaml b/devices/common_patches/h7_dmamux.yaml deleted file mode 100644 index 526dbf34f..000000000 --- a/devices/common_patches/h7_dmamux.yaml +++ /dev/null @@ -1,14 +0,0 @@ -"DMAMUX*": - _array: - "C*CR": - name: "CCR%s" - "RG*CR": - name: "RGCR%s" - CFR: - _split: [CSOF] - RGSR: - _split: [OF] - RGCFR: - _split: [COF] - CSR: - _split: [SOF] diff --git a/devices/common_patches/h7_dsi.yaml b/devices/common_patches/h7_dsi.yaml deleted file mode 100644 index ec5e01f87..000000000 --- a/devices/common_patches/h7_dsi.yaml +++ /dev/null @@ -1,1582 +0,0 @@ -# H7 MIPI DSI Host Peripheral - -_add: - DSIHOST: - description: MIPI DSI Host - groupName: DSIHOST - baseAddress: 0x50000000 - addressBlock: - offset: 0x000 - size: 0x500 - usage: registers - registers: - VR: - description: DSI Host version register - addressOffset: 0x0000 - resetValue: 0x3133302A - access: read-only - fields: - VERSION: - description: Version of the DSI Host - bitOffset: 0 - bitWidth: 32 - CR: - description: DSI Host control register - addressOffset: 0x0004 - resetValue: 0x00000000 - fields: - EN: - description: Enable - bitOffset: 0 - bitWidth: 1 - CCR: - description: DSI Host clock control register - addressOffset: 0x0008 - resetValue: 0x00000000 - fields: - TOCKDIV: - description: Timeout clock division - bitOffset: 8 - bitWidth: 8 - TXECKDIV: - description: TX escape clock division - bitOffset: 0 - bitWidth: 8 - LVCIDR: - description: DSI Host LTDC VCID register - addressOffset: 0x000C - resetValue: 0x00000000 - fields: - VCID: - description: Virtual channel ID - bitOffset: 0 - bitWidth: 2 - LCOLCR: - description: DSI Host LTDC color coding register - addressOffset: 0x0010 - resetValue: 0x00000000 - fields: - LPE: - description: Loosely packet enable - bitOffset: 8 - bitWidth: 1 - COLC: - description: Color coding - bitOffset: 0 - bitWidth: 4 - LPCR: - description: DSI Host LTDC polarity configuration register - addressOffset: 0x0014 - resetValue: 0x00000000 - fields: - HSP: - description: HSYNC polarity - bitOffset: 2 - bitWidth: 1 - VSP: - description: VSYNC polarity - bitOffset: 1 - bitWidth: 1 - DEP: - description: Data enable polarity - bitOffset: 0 - bitWidth: 1 - LPMCR: - description: DSI Host low-power mode configuration register - addressOffset: 0x0018 - resetValue: 0x00000000 - fields: - LPSIZE: - description: Largest packet size - bitOffset: 16 - bitWidth: 8 - VLPSIZE: - description: VACT largest packet size - bitOffset: 0 - bitWidth: 8 - PCR: - description: DSI Host protocol configuration register - addressOffset: 0x002C - resetValue: 0x00000000 - fields: - CRCRXE: - description: CRC reception enable - bitOffset: 4 - bitWidth: 1 - ECCRXE: - description: ECC reception enable - bitOffset: 3 - bitWidth: 1 - BTAE: - description: Bus - bitOffset: 2 - bitWidth: 1 - ETRXE: - description: EoTp reception enable - bitOffset: 1 - bitWidth: 1 - ETTXE: - description: EoTp transmission enable - bitOffset: 0 - bitWidth: 1 - GVCIDR: - description: DSI Host generic VCID register - addressOffset: 0x0030 - resetValue: 0x00000000 - fields: - VCID: - description: Virtual channel ID - bitOffset: 0 - bitWidth: 2 - MCR: - description: DSI Host mode configuration register - addressOffset: 0x0034 - resetValue: 0x00000001 - fields: - CMDM: - description: Command mode - bitOffset: 0 - bitWidth: 1 - VMCR: - description: DSI Host video mode configuration register - addressOffset: 0x0038 - resetValue: 0x00000000 - fields: - PGO: - description: Pattern generator orientation - bitOffset: 24 - bitWidth: 1 - PGM: - description: Pattern generator mode - bitOffset: 20 - bitWidth: 1 - PGE: - description: Pattern generator enable - bitOffset: 16 - bitWidth: 1 - LPCE: - description: Low-power command enable - bitOffset: 15 - bitWidth: 1 - FBTAAE: - description: Frame bus-turn-around acknowledge enable - bitOffset: 14 - bitWidth: 1 - LPHFPE: - description: Low-power horizontal front-porch enable - bitOffset: 13 - bitWidth: 1 - LPHBPE: - description: Low-power horizontal back-porch enable - bitOffset: 12 - bitWidth: 1 - LPVAE: - description: Low-power vertical active enable - bitOffset: 11 - bitWidth: 1 - LPVFPE: - description: Low-power vertical front-porch enable - bitOffset: 10 - bitWidth: 1 - LPVBPE: - description: Low-power vertical back-porch enable - bitOffset: 9 - bitWidth: 1 - LPVSAE: - description: Low-power vertical sync active enable - bitOffset: 8 - bitWidth: 1 - VMT: - description: Video mode type - bitOffset: 0 - bitWidth: 2 - VPCR: - description: DSI Host video packet configuration register - addressOffset: 0x003C - resetValue: 0x00000000 - fields: - VPSIZE: - description: Video packet size - bitOffset: 0 - bitWidth: 14 - VCCR: - description: DSI Host video chunks configuration register - addressOffset: 0x0040 - resetValue: 0x00000000 - fields: - NUMC: - description: Number of chunks - bitOffset: 0 - bitWidth: 13 - VNPCR: - description: DSI Host video null packet configuration register - addressOffset: 0x0044 - resetValue: 0x00000000 - fields: - NPSIZE: - description: Null packet size - bitOffset: 0 - bitWidth: 13 - VHSACR: - description: DSI Host video HSA configuration register - addressOffset: 0x0048 - resetValue: 0x00000000 - fields: - HSA: - description: Horizontal synchronism active duration - bitOffset: 0 - bitWidth: 12 - VHBPCR: - description: DSI Host video HBP configuration register - addressOffset: 0x004C - resetValue: 0x00000000 - fields: - HBP: - description: Horizontal back-porch duration - bitOffset: 0 - bitWidth: 12 - VLCR: - description: DSI Host video line configuration register - addressOffset: 0x0050 - resetValue: 0x00000000 - fields: - HLINE: - description: Horizontal line duration - bitOffset: 0 - bitWidth: 15 - VVSACR: - description: DSI Host video VSA configuration register - addressOffset: 0x0054 - resetValue: 0x00000000 - fields: - VSA: - description: Vertical synchronism active duration - bitOffset: 0 - bitWidth: 10 - VVBPCR: - description: DSI Host video VBP configuration register - addressOffset: 0x0058 - resetValue: 0x00000000 - fields: - VBP: - description: Vertical back-porch duration - bitOffset: 0 - bitWidth: 10 - VVFPCR: - description: DSI Host video VFP configuration register - addressOffset: 0x005C - resetValue: 0x00000000 - fields: - VFP: - description: Vertical front-porch duration - bitOffset: 0 - bitWidth: 10 - VVACR: - description: DSI Host video VA configuration register - addressOffset: 0x0060 - resetValue: 0x00000000 - fields: - VA: - description: Vertical active duration - bitOffset: 0 - bitWidth: 14 - LCCR: - description: DSI Host LTDC command configuration register - addressOffset: 0x0064 - resetValue: 0x00000000 - fields: - CMDSIZE: - description: Command size - bitOffset: 0 - bitWidth: 16 - CMCR: - description: DSI Host command mode configuration register - addressOffset: 0x0068 - resetValue: 0x00000000 - fields: - MRDPS: - description: Maximum read packet size - bitOffset: 24 - bitWidth: 1 - DLWTX: - description: DCS long write transmission - bitOffset: 19 - bitWidth: 1 - DSR0TX: - description: DCS short read zero parameter transmission - bitOffset: 18 - bitWidth: 1 - DSW1TX: - description: DCS short read one parameter transmission - bitOffset: 17 - bitWidth: 1 - DSW0TX: - description: DCS short write zero parameter transmission - bitOffset: 16 - bitWidth: 1 - GLWTX: - description: Generic long write transmission - bitOffset: 14 - bitWidth: 1 - GSR2TX: - description: Generic short read two parameters transmission - bitOffset: 13 - bitWidth: 1 - GSR1TX: - description: Generic short read one parameters transmission - bitOffset: 12 - bitWidth: 1 - GSR0TX: - description: Generic short read zero parameters transmission - bitOffset: 11 - bitWidth: 1 - GSW2TX: - description: Generic short write two parameters transmission - bitOffset: 10 - bitWidth: 1 - GSW1TX: - description: Generic short write one parameters transmission - bitOffset: 9 - bitWidth: 1 - GSW0TX: - description: Generic short write zero parameters transmission - bitOffset: 8 - bitWidth: 1 - ARE: - description: Acknowledge request enable - bitOffset: 1 - bitWidth: 1 - TEARE: - description: Tearing effect acknowledge request enable - bitOffset: 0 - bitWidth: 1 - GHCR: - description: DSI Host generic header configuration register - addressOffset: 0x006C - resetValue: 0x00000000 - fields: - WCMSB: - description: WordCount MSB - bitOffset: 16 - bitWidth: 8 - WCLSB: - description: WordCount LSB - bitOffset: 8 - bitWidth: 8 - VCID: - description: Channel - bitOffset: 6 - bitWidth: 2 - DT: - description: Type - bitOffset: 0 - bitWidth: 6 - GPDR: - description: DSI Host generic payload data register - addressOffset: 0x0070 - resetValue: 0x00000000 - fields: - DATA4: - description: Payload byte 4 - bitOffset: 24 - bitWidth: 8 - DATA3: - description: Payload byte 3 - bitOffset: 16 - bitWidth: 8 - DATA2: - description: Payload byte 2 - bitOffset: 8 - bitWidth: 8 - DATA1: - description: Payload byte 1 - bitOffset: 0 - bitWidth: 8 - GPSR: - description: DSI Host generic packet status register - addressOffset: 0x0074 - resetValue: 0x00000015 - fields: - RCB: - description: Read command busy - bitOffset: 6 - bitWidth: 1 - PRDFF: - description: Payload read FIFO full - bitOffset: 5 - bitWidth: 1 - PRDFE: - description: Payload read FIFO empty - bitOffset: 4 - bitWidth: 1 - PWRFF: - description: Payload write FIFO full - bitOffset: 3 - bitWidth: 1 - PWRFE: - description: Payload write FIFO empty - bitOffset: 2 - bitWidth: 1 - CMDFF: - description: Command FIFO full - bitOffset: 1 - bitWidth: 1 - CMDFE: - description: Command FIFO empty - bitOffset: 0 - bitWidth: 1 - TCCR0: - description: DSI Host timeout counter configuration register 0 - addressOffset: 0x0078 - resetValue: 0x00000000 - fields: - HSTX_TOCNT: - description: High-speed transmission timeout counter - bitOffset: 16 - bitWidth: 16 - LPRX_TOCNT: - description: Low-power reception timeout counter - bitOffset: 0 - bitWidth: 16 - TCCR1: - description: DSI Host timeout counter configuration register 1 - addressOffset: 0x007C - resetValue: 0x00000000 - fields: - HSRD_TOCNT: - description: High-speed read timeout counter - bitOffset: 0 - bitWidth: 16 - TCCR2: - description: DSI Host timeout counter configuration register 2 - addressOffset: 0x0080 - resetValue: 0x00000000 - fields: - LPRD_TOCNT: - description: Low-power read timeout counter - bitOffset: 0 - bitWidth: 16 - TCCR3: - description: DSI Host timeout counter configuration register 3 - addressOffset: 0x0084 - resetValue: 0x00000000 - fields: - PM: - description: Presp mode - bitOffset: 24 - bitWidth: 1 - HSWR_TOCNT: - description: High-speed write timeout counter - bitOffset: 0 - bitWidth: 16 - TCCR4: - description: DSI Host timeout counter configuration register 4 - addressOffset: 0x0088 - resetValue: 0x00000000 - fields: - LPWR_TOCNT: - description: Low-power write timeout counter - bitOffset: 0 - bitWidth: 16 - TCCR5: - description: DSI Host timeout counter configuration register 5 - addressOffset: 0x008C - resetValue: 0x00000000 - fields: - BTA_TOCNT: - description: Bus-turn-around timeout counter - bitOffset: 0 - bitWidth: 16 - CLCR: - description: DSI Host clock lane configuration register - addressOffset: 0x0094 - resetValue: 0x00000000 - fields: - ACR: - description: Automatic clock lane control - bitOffset: 1 - bitWidth: 1 - DPCC: - description: D-PHY clock control - bitOffset: 0 - bitWidth: 1 - CLTCR: - description: DSI Host clock lane timer configuration register - addressOffset: 0x0098 - resetValue: 0x00000000 - fields: - HS2LP_TIME: - description: High-speed to low-power time - bitOffset: 16 - bitWidth: 10 - LP2HS_TIME: - description: Low-power to high-speed time - bitOffset: 0 - bitWidth: 10 - DLTCR: - description: DSI Host data lane timer configuration register - addressOffset: 0x009C - resetValue: 0x00000000 - fields: - HS2LP_TIME: - description: High-speed to low-power time - bitOffset: 24 - bitWidth: 8 - LP2HS_TIME: - description: Low-power to high-speed time - bitOffset: 16 - bitWidth: 8 - MRD_TIME: - description: Maximum read time - bitOffset: 0 - bitWidth: 15 - PCTLR: - description: DSI Host PHY control register - addressOffset: 0x00A0 - resetValue: 0x00000000 - fields: - CKE: - description: Clock enable - bitOffset: 2 - bitWidth: 1 - DEN: - description: Digital enable - bitOffset: 1 - bitWidth: 1 - PCONFR: - description: DSI Host PHY configuration register - addressOffset: 0x00A4 - resetValue: 0x00000001 - fields: - SW_TIME: - description: Stop wait time - bitOffset: 8 - bitWidth: 8 - NL: - description: Number of lanes - bitOffset: 0 - bitWidth: 2 - PUCR: - description: DSI Host PHY ULPS control register - addressOffset: 0x00A8 - resetValue: 0x00000000 - fields: - UEDL: - description: ULPS exit on data lane - bitOffset: 3 - bitWidth: 1 - URDL: - description: ULPS request on data lane - bitOffset: 2 - bitWidth: 1 - UECL: - description: ULPS exit on clock lane - bitOffset: 1 - bitWidth: 1 - URCL: - description: ULPS request on clock lane - bitOffset: 0 - bitWidth: 1 - PTTCR: - description: DSI Host PHY TX triggers configuration register - addressOffset: 0x00AC - resetValue: 0x00000000 - fields: - TX_TRIG: - description: Transmission trigger - bitOffset: 0 - bitWidth: 4 - PSR: - description: DSI Host PHY status register - addressOffset: 0x00B0 - resetValue: 0x00001528 - fields: - UAN1: - description: ULPS active not lane 1 - bitOffset: 8 - bitWidth: 1 - PSS1: - description: PHY stop state lane 1 - bitOffset: 7 - bitWidth: 1 - RUE0: - description: RX ULPS escape lane 0 - bitOffset: 6 - bitWidth: 1 - UAN0: - description: ULPS active not lane 1 - bitOffset: 5 - bitWidth: 1 - PSS0: - description: PHY stop state lane 0 - bitOffset: 4 - bitWidth: 1 - UANC: - description: ULPS active not clock lane - bitOffset: 3 - bitWidth: 1 - PSSC: - description: PHY stop state clock lane - bitOffset: 2 - bitWidth: 1 - PD: - description: PHY direction - bitOffset: 1 - bitWidth: 1 - description: DSI Host interrupt and status register 0 - addressOffset: 0x00BC - resetValue: 0x00000000 - fields: - PE4: - description: PHY error 4 - bitOffset: 20 - bitWidth: 1 - PE3: - description: PHY error 3 - bitOffset: 19 - bitWidth: 1 - PE2: - description: PHY error 2 - bitOffset: 18 - bitWidth: 1 - PE1: - description: PHY error 1 - bitOffset: 17 - bitWidth: 1 - PE0: - description: PHY error 0 - bitOffset: 16 - bitWidth: 1 - AE15: - description: Acknowledge error 15 - bitOffset: 15 - bitWidth: 1 - AE14: - description: Acknowledge error 14 - bitOffset: 14 - bitWidth: 1 - AE13: - description: Acknowledge error 13 - bitOffset: 13 - bitWidth: 1 - AE12: - description: Acknowledge error 12 - bitOffset: 12 - bitWidth: 1 - AE11: - description: Acknowledge error 11 - bitOffset: 11 - bitWidth: 1 - AE10: - description: Acknowledge error 10 - bitOffset: 10 - bitWidth: 1 - AE9: - description: Acknowledge error 9 - bitOffset: 9 - bitWidth: 1 - AE8: - description: Acknowledge error 8 - bitOffset: 8 - bitWidth: 1 - AE7: - description: Acknowledge error 7 - bitOffset: 7 - bitWidth: 1 - AE6: - description: Acknowledge error 6 - bitOffset: 6 - bitWidth: 1 - AE5: - description: Acknowledge error 5 - bitOffset: 5 - bitWidth: 1 - AE4: - description: Acknowledge error 4 - bitOffset: 4 - bitWidth: 1 - AE3: - description: Acknowledge error 3 - bitOffset: 3 - bitWidth: 1 - AE2: - description: Acknowledge error 2 - bitOffset: 2 - bitWidth: 1 - AE1: - description: Acknowledge error 1 - bitOffset: 1 - bitWidth: 1 - AE0: - description: Acknowledge error 0 - bitOffset: 0 - bitWidth: 1 - ISR1: - description: DSI Host interrupt and status register 1 - addressOffset: 0x00C0 - resetValue: 0x00000000 - fields: - GPRXE: - description: Generic payload receive error - bitOffset: 12 - bitWidth: 1 - GPRDE: - description: Generic payload read error - bitOffset: 11 - bitWidth: 1 - GPTXE: - description: Generic payload transmit error - bitOffset: 10 - bitWidth: 1 - GPWRE: - description: Generic payload write error - bitOffset: 9 - bitWidth: 1 - GCWRE: - description: Generic command write error - bitOffset: 8 - bitWidth: 1 - LPWRE: - description: LTDC payload write error - bitOffset: 7 - bitWidth: 1 - EOTPE: - description: EoTp error - bitOffset: 6 - bitWidth: 1 - PSE: - description: Packet size error - bitOffset: 5 - bitWidth: 1 - CRCE: - description: CRC error - bitOffset: 4 - bitWidth: 1 - ECCME: - description: ECC multi - bitOffset: 3 - bitWidth: 1 - ECCSE: - description: ECC single - bitOffset: 2 - bitWidth: 1 - TOLPRX: - description: Timeout low - bitOffset: 1 - bitWidth: 1 - TOHSTX: - description: Timeout high - bitOffset: 0 - bitWidth: 1 - IER0: - description: DSI Host interrupt enable register 0 - addressOffset: 0x00C4 - resetValue: 0x00000000 - fields: - PE4IE: - description: PHY error 4 interrupt enable - bitOffset: 20 - bitWidth: 1 - PE3IE: - description: PHY error 3 interrupt enable - bitOffset: 19 - bitWidth: 1 - PE2IE: - description: PHY error 2 interrupt enable - bitOffset: 18 - bitWidth: 1 - PE1IE: - description: PHY error 1 interrupt enable - bitOffset: 17 - bitWidth: 1 - PE0IE: - description: PHY error 0 interrupt enable - bitOffset: 16 - bitWidth: 1 - AE15IE: - description: Acknowledge error 15 interrupt enable - bitOffset: 15 - bitWidth: 1 - AE14IE: - description: Acknowledge error 14 interrupt enable - bitOffset: 14 - bitWidth: 1 - AE13IE: - description: Acknowledge error 13 interrupt enable - bitOffset: 13 - bitWidth: 1 - AE12IE: - description: Acknowledge error 12 interrupt enable - bitOffset: 12 - bitWidth: 1 - AE11IE: - description: Acknowledge error 11 interrupt enable - bitOffset: 11 - bitWidth: 1 - AE10IE: - description: Acknowledge error 10 interrupt enable - bitOffset: 10 - bitWidth: 1 - AE9IE: - description: Acknowledge error 9 interrupt enable - bitOffset: 9 - bitWidth: 1 - AE8IE: - description: Acknowledge error 8 interrupt enable - bitOffset: 8 - bitWidth: 1 - AE7IE: - description: Acknowledge error 7 interrupt enable - bitOffset: 7 - bitWidth: 1 - AE6IE: - description: Acknowledge error 6 interrupt enable - bitOffset: 6 - bitWidth: 1 - AE5IE: - description: Acknowledge error 5 interrupt enable - bitOffset: 5 - bitWidth: 1 - AE4IE: - description: Acknowledge error 4 interrupt enable - bitOffset: 4 - bitWidth: 1 - AE3IE: - description: Acknowledge error 3 interrupt enable - bitOffset: 3 - bitWidth: 1 - AE2IE: - description: Acknowledge error 2 interrupt enable - bitOffset: 2 - bitWidth: 1 - AE1IE: - description: Acknowledge error 1 interrupt enable - bitOffset: 1 - bitWidth: 1 - AE0IE: - description: Acknowledge error 0 interrupt enable - bitOffset: 0 - bitWidth: 1 - IER1: - description: DSI Host interrupt enable register 1 - addressOffset: 0x00C8 - resetValue: 0x00000000 - fields: - GPRXEIE: - description: Generic payload receive error interrupt enable - bitOffset: 12 - bitWidth: 1 - GPRDEIE: - description: Generic payload read error interrupt enable - bitOffset: 11 - bitWidth: 1 - GPTXEIE: - description: Generic payload transmit error interrupt enable - bitOffset: 10 - bitWidth: 1 - GPWREIE: - description: Generic payload write error interrupt enable - bitOffset: 9 - bitWidth: 1 - GCWREIE: - description: Generic command write error interrupt enable - bitOffset: 8 - bitWidth: 1 - LPWREIE: - description: LTDC payload write error interrupt enable - bitOffset: 7 - bitWidth: 1 - EOTPEIE: - description: EoTp error interrupt enable - bitOffset: 6 - bitWidth: 1 - PSEIE: - description: Packet size error interrupt enable - bitOffset: 5 - bitWidth: 1 - CRCEIE: - description: CRC error interrupt enable - bitOffset: 4 - bitWidth: 1 - ECCMEIE: - description: ECC multi - bitOffset: 3 - bitWidth: 1 - ECCSEIE: - description: ECC single - bitOffset: 2 - bitWidth: 1 - TOLPRXIE: - description: Timeout low - bitOffset: 1 - bitWidth: 1 - TOHSTXIE: - description: Timeout high - bitOffset: 0 - bitWidth: 1 - FIR0: - description: DSI Host force interrupt register 0 - addressOffset: 0x00D8 - resetValue: 0x00000000 - fields: - FPE4: - description: Force PHY error 4 - bitOffset: 20 - bitWidth: 1 - FPE3: - description: Force PHY error 3 - bitOffset: 19 - bitWidth: 1 - FPE2: - description: Force PHY error 2 - bitOffset: 18 - bitWidth: 1 - FPE1: - description: Force PHY error 1 - bitOffset: 17 - bitWidth: 1 - FPE0: - description: Force PHY error 0 - bitOffset: 16 - bitWidth: 1 - FAE15: - description: Force acknowledge error 15 - bitOffset: 15 - bitWidth: 1 - FAE14: - description: Force acknowledge error 14 - bitOffset: 14 - bitWidth: 1 - FAE13: - description: Force acknowledge error 13 - bitOffset: 13 - bitWidth: 1 - FAE12: - description: Force acknowledge error 12 - bitOffset: 12 - bitWidth: 1 - FAE11: - description: Force acknowledge error 11 - bitOffset: 11 - bitWidth: 1 - FAE10: - description: Force acknowledge error 10 - bitOffset: 10 - bitWidth: 1 - FAE9: - description: Force acknowledge error 9 - bitOffset: 9 - bitWidth: 1 - FAE8: - description: Force acknowledge error 8 - bitOffset: 8 - bitWidth: 1 - FAE7: - description: Force acknowledge error 7 - bitOffset: 7 - bitWidth: 1 - FAE6: - description: Force acknowledge error 6 - bitOffset: 6 - bitWidth: 1 - FAE5: - description: Force acknowledge error 5 - bitOffset: 5 - bitWidth: 1 - FAE4: - description: Force acknowledge error 4 - bitOffset: 4 - bitWidth: 1 - FAE3: - description: Force acknowledge error 3 - bitOffset: 3 - bitWidth: 1 - FAE2: - description: Force acknowledge error 2 - bitOffset: 2 - bitWidth: 1 - FAE1: - description: Force acknowledge error 1 - bitOffset: 1 - bitWidth: 1 - FAE0: - description: Force acknowledge error 0 - bitOffset: 0 - bitWidth: 1 - FIR1: - description: DSI Host force interrupt register 1 - addressOffset: 0x00DC - resetValue: 0x00000000 - fields: - FGPRXE: - description: Force generic payload receive error - bitOffset: 12 - bitWidth: 1 - FGPRDE: - description: Force generic payload read error - bitOffset: 11 - bitWidth: 1 - FGPTXE: - description: Force generic payload transmit error - bitOffset: 10 - bitWidth: 1 - FGPWRE: - description: Force generic payload write error - bitOffset: 9 - bitWidth: 1 - FGCWRE: - description: Force generic command write error - bitOffset: 8 - bitWidth: 1 - FLPWRE: - description: Force LTDC payload write error - bitOffset: 7 - bitWidth: 1 - FEOTPE: - description: Force EoTp error - bitOffset: 6 - bitWidth: 1 - FPSE: - description: Force packet size error - bitOffset: 5 - bitWidth: 1 - FCRCE: - description: Force CRC error - bitOffset: 4 - bitWidth: 1 - FECCME: - description: Force ECC multi - bitOffset: 3 - bitWidth: 1 - FECCSE: - description: Force ECC single - bitOffset: 2 - bitWidth: 1 - FTOLPRX: - description: Force timeout low - bitOffset: 1 - bitWidth: 1 - FTOHSTX: - description: Force timeout high - bitOffset: 0 - bitWidth: 1 - VSCR: - description: DSI Host video shadow control register - addressOffset: 0x0100 - resetValue: 0x00000000 - fields: - UR: - description: Update register - bitOffset: 8 - bitWidth: 1 - EN: - description: Enable - bitOffset: 0 - bitWidth: 1 - LCVCIDR: - description: DSI Host LTDC current VCID register - addressOffset: 0x010C - resetValue: 0x00000000 - fields: - VCID: - description: Virtual channel ID - bitOffset: 0 - bitWidth: 2 - LCCCR: - description: DSI Host LTDC current color coding register - addressOffset: 0x0110 - resetValue: 0x00000000 - fields: - LPE: - description: Loosely packed enable - bitOffset: 8 - bitWidth: 1 - COLC: - description: Color coding - bitOffset: 0 - bitWidth: 4 - LPMCCR: - description: DSI Host low-power mode current configuration register - addressOffset: 0x0118 - resetValue: 0x00000000 - fields: - LPSIZE: - description: Largest packet size - bitOffset: 16 - bitWidth: 8 - VLPSIZE: - description: VACT largest packet size - bitOffset: 0 - bitWidth: 8 - VMCCR: - description: DSI Host video mode current configuration register - addressOffset: 0x0138 - resetValue: 0x00000000 - fields: - LPCE: - description: Low-power command enable - bitOffset: 9 - bitWidth: 1 - FBTAAE: - description: Frame BTA acknowledge enable - bitOffset: 8 - bitWidth: 1 - LPHFE: - description: Low-power horizontal front-porch enable - bitOffset: 7 - bitWidth: 1 - LPHBPE: - description: Low-power horizontal back-porch enable - bitOffset: 6 - bitWidth: 1 - LPVAE: - description: Low-power vertical active enable - bitOffset: 5 - bitWidth: 1 - LPVFPE: - description: Low-power vertical front-porch enable - bitOffset: 4 - bitWidth: 1 - LPVBPE: - description: Low-power vertical back-porch enable - bitOffset: 3 - bitWidth: 1 - LPVSAE: - description: Low-power vertical sync time enable - bitOffset: 2 - bitWidth: 1 - VMT: - description: Video mode type - bitOffset: 0 - bitWidth: 2 - VPCCR: - description: DSI Host video packet current configuration register - addressOffset: 0x013C - resetValue: 0x00000000 - fields: - VPSIZE: - description: Video packet size - bitOffset: 0 - bitWidth: 14 - VCCCR: - description: DSI Host video chunks current configuration register - addressOffset: 0x0140 - resetValue: 0x00000000 - fields: - NUMC: - description: Number of chunks - bitOffset: 0 - bitWidth: 13 - VNPCCR: - description: DSI Host video null packet current configuration register - addressOffset: 0x0144 - resetValue: 0x00000000 - fields: - NPSIZE: - description: Null packet size - bitOffset: 0 - bitWidth: 13 - VHSACCR: - description: DSI Host video HSA current configuration register - addressOffset: 0x0148 - resetValue: 0x00000000 - fields: - HSA: - description: Horizontal synchronism active duration - bitOffset: 0 - bitWidth: 12 - VHBPCCR: - description: DSI Host video HBP current configuration register - addressOffset: 0x014C - resetValue: 0x00000000 - fields: - HBP: - description: Horizontal back - bitOffset: 0 - bitWidth: 12 - VLCCR: - description: DSI Host video line current configuration register - addressOffset: 0x0150 - resetValue: 0x00000000 - fields: - HLINE: - description: Horizontal line duration - bitOffset: 0 - bitWidth: 15 - VVSACCR: - description: DSI Host video VSA current configuration register - addressOffset: 0x0154 - resetValue: 0x00000000 - fields: - VSA: - description: Vertical synchronism active duration - bitOffset: 0 - bitWidth: 10 - VVPBCCR: - description: DSI Host video VBP current configuration register - addressOffset: 0x0158 - resetValue: 0x00000000 - fields: - VBP: - description: Vertical back - bitOffset: 0 - bitWidth: 10 - VVFPCCR: - description: DSI Host video VFP current configuration register - addressOffset: 0x015C - resetValue: 0x00000000 - fields: - VFP: - description: Vertical front - bitOffset: 0 - bitWidth: 10 - VVACCR: - description: DSI Host video VA current configuration register - addressOffset: 0x0160 - resetValue: 0x00000000 - fields: - VA: - description: Vertical active duration - bitOffset: 0 - bitWidth: 14 - WCFGR: - description: DSI wrapper configuration register - addressOffset: 0x0400 - resetValue: 0x00000000 - fields: - VSPOL: - description: VSync polarity - bitOffset: 7 - bitWidth: 1 - AR: - description: Automatic refresh - bitOffset: 6 - bitWidth: 1 - TEPOL: - description: TE polarity - bitOffset: 5 - bitWidth: 1 - TESRC: - description: TE source - bitOffset: 4 - bitWidth: 1 - COLMUX: - description: Color multiplexing - bitOffset: 1 - bitWidth: 3 - DSIM: - description: DSI mode - bitOffset: 0 - bitWidth: 1 - WCR: - description: DSI wrapper control register - addressOffset: 0x0404 - resetValue: 0x00000000 - fields: - DSIEN: - description: DSI enable - bitOffset: 3 - bitWidth: 1 - LTDCEN: - description: LTDC enable - bitOffset: 2 - bitWidth: 1 - SHTDN: - description: Shutdown - bitOffset: 1 - bitWidth: 1 - COLM: - description: Color mode - bitOffset: 0 - bitWidth: 1 - WIER: - description: DSI wrapper interrupt enable register - addressOffset: 0x0408 - resetValue: 0x00000000 - fields: - RRIE: - description: Regulator ready interrupt enable - bitOffset: 13 - bitWidth: 1 - PLLUIE: - description: PLL unlock interrupt enable - bitOffset: 10 - bitWidth: 1 - PLLLIE: - description: PLL lock interrupt enable - bitOffset: 9 - bitWidth: 1 - ERIE: - description: End of refresh interrupt enable - bitOffset: 1 - bitWidth: 1 - TEIE: - description: Tearing effect interrupt enable - bitOffset: 0 - bitWidth: 1 - WISR: - description: DSI wrapper interrupt and status register - addressOffset: 0x040C - resetValue: 0x00000000 - fields: - RRIF: - description: Regulator ready interrupt flag - bitOffset: 13 - bitWidth: 1 - RRS: - description: Regulator ready status - bitOffset: 12 - bitWidth: 1 - PLLUIF: - description: PLL unlock interrupt flag - bitOffset: 10 - bitWidth: 1 - PLLLIF: - description: PLL lock interrupt flag - bitOffset: 9 - bitWidth: 1 - PLLLS: - description: PLL lock status - bitOffset: 8 - bitWidth: 1 - BUSY: - description: Busy flag - bitOffset: 2 - bitWidth: 1 - ERIF: - description: End of refresh interrupt flag - bitOffset: 1 - bitWidth: 1 - TEIF: - description: Tearing effect interrupt flag - bitOffset: 0 - bitWidth: 1 - WIFCR: - description: DSI wrapper interrupt flag clear register - addressOffset: 0x0410 - resetValue: 0x00000000 - fields: - CRRIF: - description: Clear regulator ready interrupt flag - bitOffset: 13 - bitWidth: 1 - CPLLUIF: - description: Clear PLL unlock interrupt flag - bitOffset: 10 - bitWidth: 1 - CPLLLIF: - description: Clear PLL lock interrupt flag - bitOffset: 9 - bitWidth: 1 - CERIF: - description: Clear end of refresh interrupt flag - bitOffset: 1 - bitWidth: 1 - CTEIF: - description: Clear tearing effect interrupt flag - bitOffset: 0 - bitWidth: 1 - WPCR0: - description: DSI wrapper PHY configuration register 0 - addressOffset: 0x0418 - resetValue: 0x00000000 - fields: - TCLKPOSTEN: - description: Custom time for tCLK - bitOffset: 27 - bitWidth: 1 - TLPXCEN: - description: Custom time for tLPX for clock lane enable - bitOffset: 26 - bitWidth: 1 - THSEXITEN: - description: Custom time for tHS - bitOffset: 25 - bitWidth: 1 - TLPXDEN: - description: Custom time for tLPX for data lanes enable - bitOffset: 24 - bitWidth: 1 - THSZEROEN: - description: Custom time for tHS - bitOffset: 23 - bitWidth: 1 - THSTRAILEN: - description: Custom time for tHS - bitOffset: 22 - bitWidth: 1 - THSPREPEN: - description: Custom time for tHS - bitOffset: 21 - bitWidth: 1 - TCLKZEROEN: - description: Custom time for tCLK - bitOffset: 20 - bitWidth: 1 - TCLKPREPEN: - description: Custom time for tCLK - bitOffset: 19 - bitWidth: 1 - PDEN: - description: Pull-down enable - bitOffset: 18 - bitWidth: 1 - TDDL: - description: Turn disable data lanes - bitOffset: 16 - bitWidth: 1 - CDOFFDL: - description: Contention detection OFF on data lanes - bitOffset: 14 - bitWidth: 1 - FTXSMDL: - description: Force in TX Stop mode the data lanes - bitOffset: 13 - bitWidth: 1 - FTXSMCL: - description: Force in TX Stop mode the clock lane - bitOffset: 12 - bitWidth: 1 - HSIDL1: - description: Invert the high-speed data signal on data lane 1 - bitOffset: 11 - bitWidth: 1 - HSIDL0: - description: Invert the high-speed data signal on data lane 0 - bitOffset: 10 - bitWidth: 1 - HSICL: - description: Invert high - bitOffset: 9 - bitWidth: 1 - SWDL1: - description: Swap data lane 1 pins - bitOffset: 8 - bitWidth: 1 - SWDL0: - description: Swap data lane 0 pins - bitOffset: 7 - bitWidth: 1 - SWCL: - description: Swap clock lane pins - bitOffset: 6 - bitWidth: 1 - UIX4: - description: Unit interval multiplied by 4 - bitOffset: 0 - bitWidth: 6 - WPCR1: - description: DSI wrapper PHY configuration register 1 - addressOffset: 0x041C - resetValue: 0x00000000 - fields: - LPRXFT: - description: Low-power RX low-pass filtering tuning - bitOffset: 25 - bitWidth: 2 - FLPRXLPM: - description: Forces LP receiver in low-power mode - bitOffset: 22 - bitWidth: 1 - HSTXSRCDL: - description: High-speed transmission slew-rate control on data lanes - bitOffset: 18 - bitWidth: 2 - HSTXSRCCL: - description: High-speed transmission slew-rate control on clock lane - bitOffset: 16 - bitWidth: 2 - SDDC: - description: SDD control - bitOffset: 12 - bitWidth: 1 - LPSRCDL: - description: Low-power transmission slew-rate compensation on data lanes - bitOffset: 8 - bitWidth: 2 - LPSRCCL: - description: Low-power transmission slew-rate compensation on clock lane - bitOffset: 6 - bitWidth: 2 - HSTXDDL: - description: High-speed transmission delay on data lanes - bitOffset: 2 - bitWidth: 2 - HSTXDCL: - description: High-speed transmission delay on clock lane - bitOffset: 0 - bitWidth: 2 - WPCR2: - description: DSI wrapper PHY configuration register 2 - addressOffset: 0x0420 - resetValue: 0x00000000 - fields: - THSTRAIL: - description: tHSTRAIL - bitOffset: 24 - bitWidth: 8 - THSPREP: - description: tHS-PREPARE - bitOffset: 16 - bitWidth: 8 - TCLKZERO: - description: tCLK-ZERO - bitOffset: 8 - bitWidth: 8 - TCLKPREP: - description: tCLK-PREPARE - bitOffset: 0 - bitWidth: 8 - description: DSI wrapper PHY configuration register 3 - addressOffset: 0x0424 - resetValue: 0x00000000 - fields: - TLPXC: - description: tLPXC for clock lane - bitOffset: 24 - bitWidth: 8 - THSEXIT: - description: tHSEXIT - bitOffset: 16 - bitWidth: 8 - TLPXD: - description: tLPX for data lanes - bitOffset: 8 - bitWidth: 8 - THSZERO: - description: tHS-ZERO - bitOffset: 0 - bitWidth: 8 - description: DSI wrapper PHY configuration register 4 - addressOffset: 0x0428 - resetValue: 0x00000000 - fields: - TCLKPOST: - description: tCLK-POST - bitOffset: 0 - bitWidth: 8 - WRPCR: - description: DSI wrapper regulator and PLL control register - addressOffset: 0x0430 - resetValue: 0x00000000 - fields: - REGEN: - description: Regulator enable - bitOffset: 24 - bitWidth: 1 - ODF: - description: PLL output division factor - bitOffset: 16 - bitWidth: 2 - IDF: - description: PLL input division factor - bitOffset: 11 - bitWidth: 4 - NDIV: - description: PLL loop division factor - bitOffset: 2 - bitWidth: 7 - PLLEN: - description: PLL enable - bitOffset: 0 - bitWidth: 1 diff --git a/devices/common_patches/h7_dualcore_flash.yaml b/devices/common_patches/h7_dualcore_flash.yaml deleted file mode 100644 index c8729364d..000000000 --- a/devices/common_patches/h7_dualcore_flash.yaml +++ /dev/null @@ -1,1021 +0,0 @@ -# Dual Core H7 Flash Peripheral - -_delete: - - Flash - -_add: - FLASH: - description: Embedded Flash Memory - groupName: FLASH - baseAddress: 0x52002000 - addressBlock: - offset: 0x000 - size: 0x200 - usage: registers - registers: - ACR: - description: FLASH access control register - addressOffset: 0x000 - resetValue: 0x00000037 - fields: - WRHIGHFREQ: - description: Flash signal delay - bitOffset: 4 - bitWidth: 2 - LATENCY: - description: Read latency - bitOffset: 0 - bitWidth: 4 - KEYR1: - description: FLASH key register for bank 1 - addressOffset: 0x004 - resetValue: 0x00000000 - access: write-only - fields: - KEYR: - description: Bank access configuration unlock key - bitOffset: 0 - bitWidth: 32 - OPTKEYR: - description: FLASH option key register - addressOffset: 0x008 - resetValue: 0x00000000 - access: write-only - fields: - OPTKEYR: - description: FLASH option bytes control access unlock key - bitOffset: 0 - bitWidth: 32 - CR1: - description: FLASH control register for bank 1 - addressOffset: 0x00C - resetValue: 0x00000031 - fields: - CRCRDERRIE: - description: Bank 1 CRC read error interrupt enable bit - bitOffset: 28 - bitWidth: 1 - CRCENDIE: - description: Bank 1 CRC end of calculation interrupt enable bit - bitOffset: 27 - bitWidth: 1 - DBECCERRIE: - description: Bank 1 ECC double detection error interrupt enable bit - bitOffset: 26 - bitWidth: 1 - SNECCERRIE: - description: Bank 1 ECC single correction error interrupt enable bit - bitOffset: 25 - bitWidth: 1 - RDSERRIE: - description: Bank 1 secure error interrupt enable bit - bitOffset: 24 - bitWidth: 1 - RDPERRIE: - description: Bank 1 read protection error interrupt enable bit - bitOffset: 23 - bitWidth: 1 - OPERRIE: - description: Bank 1 write - bitOffset: 22 - bitWidth: 1 - INCERRIE: - description: Bank 1 inconsistency error interrupt enable bit - bitOffset: 21 - bitWidth: 1 - STRBERRIE: - description: Bank 1 strobe error interrupt enable bit - bitOffset: 19 - bitWidth: 1 - PGSERRIE: - description: Bank 1 programming sequence error interrupt enable bit - bitOffset: 18 - bitWidth: 1 - WRPERRIE: - description: Bank 1 write protection error interrupt enable bit - bitOffset: 17 - bitWidth: 1 - EOPIE: - description: Bank 1 end-of-program interrupt control bit - bitOffset: 16 - bitWidth: 1 - CRC_EN: - description: Bank 1 CRC control bit - bitOffset: 15 - bitWidth: 1 - SNB: - description: Bank 1 sector erase selection number - bitOffset: 8 - bitWidth: 3 - START: - description: Bank 1 erase start control bit - bitOffset: 7 - bitWidth: 1 - FW: - description: Bank 1 write forcing control bit - bitOffset: 6 - bitWidth: 1 - PSIZE: - description: Bank 1 program size - bitOffset: 4 - bitWidth: 2 - BER: - description: Bank 1 erase request - bitOffset: 3 - bitWidth: 1 - SER: - description: Bank 1 sector erase request - bitOffset: 2 - bitWidth: 1 - PG: - description: Bank 1 internal buffer control bit - bitOffset: 1 - bitWidth: 1 - LOCK: - description: Bank 1 configuration lock bit - bitOffset: 0 - bitWidth: 1 - SR1: - description: FLASH status register for bank 1 - addressOffset: 0x010 - resetValue: 0x00000000 - fields: - CRCRDERR1: - description: Bank 1 CRC read error flag - bitOffset: 28 - bitWidth: 1 - CRCEND1: - description: Bank 1 CRC end of calculation flag - bitOffset: 27 - bitWidth: 1 - DBECCERR1: - description: Bank 1 ECC double detection error flag - bitOffset: 26 - bitWidth: 1 - SNECCERR1: - description: Bank 1 single correction error flag - bitOffset: 25 - bitWidth: 1 - RDSERR1: - description: Bank 1 secure error flag - bitOffset: 24 - bitWidth: 1 - RDPERR1: - description: Bank 1 read protection error flag - bitOffset: 23 - bitWidth: 1 - OPERR1: - description: Bank 1 write - bitOffset: 22 - bitWidth: 1 - INCERR1: - description: Bank 1 inconsistency error flag - bitOffset: 21 - bitWidth: 1 - STRBERR1: - description: Bank 1 strobe error flag - bitOffset: 19 - bitWidth: 1 - PGSERR1: - description: Bank 1 programming sequence error flag - bitOffset: 18 - bitWidth: 1 - WRPERR1: - description: Bank 1 write protection error flag - bitOffset: 17 - bitWidth: 1 - EOP1: - description: Bank 1 end-of-program flag - bitOffset: 16 - bitWidth: 1 - CRC_BUSY1: - description: Bank 1 CRC busy flag - bitOffset: 3 - bitWidth: 1 - QW1: - description: Bank 1 wait queue flag - bitOffset: 2 - bitWidth: 1 - WBNE1: - description: Bank 1 write buffer not empty flag - bitOffset: 1 - bitWidth: 1 - BSY1: - description: Bank 1 busy flag - bitOffset: 0 - bitWidth: 1 - CCR1: - description: FLASH clear control register for bank 1 - addressOffset: 0x014 - resetValue: 0x00000000 - fields: - CLR_CRCRDERR1: - description: Bank 1 CRCRDERR1 flag clear bit - bitOffset: 28 - bitWidth: 1 - CLR_CRCEND1: - description: Bank 1 CRCEND1 flag clear bit - bitOffset: 27 - bitWidth: 1 - CLR_DBECCERR1: - description: Bank 1 DBECCERR1 flag clear bit - bitOffset: 26 - bitWidth: 1 - CLR_SNECCERR1: - description: Bank 1 SNECCERR1 flag clear bit - bitOffset: 25 - bitWidth: 1 - CLR_RDSERR1: - description: Bank 1 RDSERR1 flag clear bit - bitOffset: 24 - bitWidth: 1 - CLR_RDPERR1: - description: Bank 1 RDPERR1 flag clear bit - bitOffset: 23 - bitWidth: 1 - CLR_OPERR1: - description: Bank 1 OPERR1 flag clear bit - bitOffset: 22 - bitWidth: 1 - CLR_INCERR1: - description: Bank 1 INCERR1 flag clear bit - bitOffset: 21 - bitWidth: 1 - CLR_STRBERR1: - description: Bank 1 STRBERR1 flag clear bit - bitOffset: 19 - bitWidth: 1 - CLR_PGSERR1: - description: Bank 1 PGSERR1 flag clear bit - bitOffset: 18 - bitWidth: 1 - CLR_WRPERR1: - description: Bank 1 WRPERR1 flag clear bit - bitOffset: 17 - bitWidth: 1 - CLR_EOP1: - description: Bank 1 EOP1 flag clear bit - bitOffset: 16 - bitWidth: 1 - OPTCR: - description: FLASH option control register - addressOffset: 0x018 - resetValue: 0x00000001 - fields: - SWAP_BANK: - description: Bank swapping option configuration bit - bitOffset: 31 - bitWidth: 1 - OPTCHANGEERRIE: - description: Option byte change error interrupt enable bit - bitOffset: 30 - bitWidth: 1 - MER: - description: mass erase request - bitOffset: 4 - bitWidth: 1 - OPTSTART: - description: Option byte start change option configuration bit - bitOffset: 1 - bitWidth: 1 - OPTLOCK: - description: FLASH - bitOffset: 0 - bitWidth: 1 - OPTSR_CUR: - description: FLASH option status register - addressOffset: 0x01C - resetValue: 0x00000000 - fields: - SWAP_BANK_OPT: - description: Bank swapping option status bit - bitOffset: 31 - bitWidth: 1 - OPTCHANGEERR: - description: Option byte change error flag - bitOffset: 30 - bitWidth: 1 - IO_HSLV: - description: I - bitOffset: 29 - bitWidth: 1 - NRST_STBY_D2: - description: D2 domain DStandby entry reset option status bit - bitOffset: 25 - bitWidth: 1 - NRST_STOP_D2: - description: D2 domain DStop entry reset option status bit - bitOffset: 24 - bitWidth: 1 - BOOT_CM7: - description: Arm Cortex - bitOffset: 23 - bitWidth: 1 - BOOT_CM4: - description: Arm Cortex - bitOffset: 22 - bitWidth: 1 - SECURITY: - description: Security enable option status bit - bitOffset: 21 - bitWidth: 1 - ST_RAM_SIZE: - description: ST RAM size option status - bitOffset: 19 - bitWidth: 2 - IWDG_FZ_SDBY: - description: IWDG Standby mode freeze option status bit - bitOffset: 18 - bitWidth: 1 - IWDG_FZ_STOP: - description: IWDG Stop mode freeze option status bit - bitOffset: 17 - bitWidth: 1 - RDP: - description: Readout protection level option status byte - bitOffset: 8 - bitWidth: 8 - RST_STDY_D1: - description: D1 domain DStandby entry reset option status bit - bitOffset: 7 - bitWidth: 1 - NRST_STOP_D1: - description: D1 domain DStop entry reset option status bit - bitOffset: 6 - bitWidth: 1 - IWDG2_SW: - description: IWDG2 control mode option status bit - bitOffset: 5 - bitWidth: 1 - IWDG_SW: - description: IWDG control mode option status bit - bitOffset: 4 - bitWidth: 1 - BOR_LEV: - description: Brownout level option status bit - bitOffset: 2 - bitWidth: 2 - OPT_BUSY: - description: Option byte change ongoing flag - bitOffset: 0 - bitWidth: 1 - OPTSR_PRG: - description: FLASH option status register - addressOffset: 0x020 - resetValue: 0x00000000 - fields: - SWAP_BANK_OPT: - description: Bank swapping option configuration bit - bitOffset: 31 - bitWidth: 1 - IO_HSLV: - description: I - bitOffset: 29 - bitWidth: 1 - NRST_STBY_D2: - description: D2 domain DStandby entry reset option configuration bit - bitOffset: 25 - bitWidth: 1 - NRST_STOP_D2: - description: D2 domain DStop entry reset option configuration bit - bitOffset: 24 - bitWidth: 1 - BOOT_CM7: - description: Arm Cortex - bitOffset: 23 - bitWidth: 1 - BOOT_CM4: - description: Arm Cortex - bitOffset: 22 - bitWidth: 1 - SECURITY: - description: Security enable option configuration bit - bitOffset: 21 - bitWidth: 1 - ST_RAM_SIZE: - description: ST RAM size option configuration bits - bitOffset: 19 - bitWidth: 2 - IWDG_FZ_SDBY: - description: IWDG Standby mode freeze option configuration bit - bitOffset: 18 - bitWidth: 1 - IWDG_FZ_STOP: - description: IWDG Stop mode freeze option configuration bit - bitOffset: 17 - bitWidth: 1 - RDP: - description: Readout protection level option configuration bits - bitOffset: 8 - bitWidth: 8 - NRST_STDY_D1: - description: D1 domain DStandby entry reset option configuration bit - bitOffset: 7 - bitWidth: 1 - NRST_STOP_D1: - description: D1 domain DStop entry reset option configuration bit - bitOffset: 6 - bitWidth: 1 - IWDG2_SW: - description: IWDG2 control mode option configuration bit - bitOffset: 5 - bitWidth: 1 - IWDG_SW: - description: IWDG control mode option configuration bit - bitOffset: 4 - bitWidth: 1 - BOR_LEV: - description: Brownout level option configuration bit - bitOffset: 2 - bitWidth: 2 - OPTCCR: - description: FLASH option clear control register - addressOffset: 0x024 - resetValue: 0x00000000 - fields: - CLR_OPTCHANGEERR: - description: OPTCHANGEERR reset bit - bitOffset: 30 - bitWidth: 1 - PRAR_CUR1: - description: FLASH protection address for bank 1 - addressOffset: 0x028 - resetValue: 0x00000000 - fields: - DMEP1: - description: Bank 1 PCROP protected erase enable option status bit - bitOffset: 31 - bitWidth: 1 - PROT_AREA_END1: - description: Bank 1 PCROP area end status bits - bitOffset: 16 - bitWidth: 12 - PROT_AREA_START1: - description: Bank 1 PCROP area start status bits - bitOffset: 0 - bitWidth: 12 - PRAR_PRG1: - description: FLASH protection address for bank 1 - addressOffset: 0x02C - resetValue: 0x00000000 - fields: - DMEP1: - description: Bank 1 PCROP protected erase enable option configuration bit - bitOffset: 31 - bitWidth: 1 - PROT_AREA_END1: - description: Bank 1 PCROP area end configuration bits - bitOffset: 16 - bitWidth: 12 - PROT_AREA_START1: - description: Bank 1 PCROP area start configuration bits - bitOffset: 0 - bitWidth: 12 - SCAR_CUR1: - description: FLASH secure address for bank 1 - addressOffset: 0x030 - resetValue: 0x00000000 - fields: - DMES1: - description: Bank 1 secure access protected erase enable option status bit - bitOffset: 31 - bitWidth: 1 - SEC_AREA_END1: - description: Bank 1 secure-only area end status bits - bitOffset: 16 - bitWidth: 12 - SEC_AREA_START1: - description: Bank 1 secure-only area start status bits - bitOffset: 0 - bitWidth: 12 - SCAR_PRG1: - description: FLASH secure address for bank 1 - addressOffset: 0x034 - resetValue: 0x00000000 - fields: - DMES1: - description: Bank 1 secure access protected erase enable option configuration bit - bitOffset: 31 - bitWidth: 1 - SEC_AREA_END1: - description: Bank 1 secure-only area end configuration bits - bitOffset: 16 - bitWidth: 12 - SEC_AREA_START1: - description: Bank 1 secure-only area start configuration bits - bitOffset: 0 - bitWidth: 12 - WPSN_CUR1R: - description: FLASH write sector protection for bank 1 - addressOffset: 0x038 - resetValue: 0x00000000 - fields: - WRPSn1: - description: Bank 1 sector write protection option status byte - bitOffset: 0 - bitWidth: 8 - WPSN_PRG1R: - description: FLASH write sector protection for bank 1 - addressOffset: 0x03C - resetValue: 0x00000000 - fields: - WRPSn1: - description: Bank 1 sector write protection option status byte - bitOffset: 0 - bitWidth: 8 - BOOT7_CURR: - description: FLASH register boot address for Arm Cortex-M7 core - addressOffset: 0x040 - resetValue: 0x00000000 - fields: - BOOT_CM7_ADD1: - description: Arm Cortex-M7 boot address 1 - bitOffset: 16 - bitWidth: 16 - BOOT_CM7_ADD0: - description: Arm Cortex-M7 boot address 0 - bitOffset: 0 - bitWidth: 16 - BOOT7_PRGR: - description: FLASH register boot address for Arm Cortex-M7 core - addressOffset: 0x044 - resetValue: 0x00000000 - fields: - BOOT_CM7_ADD1: - description: Arm Cortex-M7 boot address 1 configuration - bitOffset: 16 - bitWidth: 16 - BOOT_CM7_ADD0: - description: Arm Cortex-M7 boot address 0 configuration - bitOffset: 0 - bitWidth: 16 - BOOT4_CURR: - description: FLASH register boot address for Arm Cortex-M4 core - addressOffset: 0x048 - resetValue: 0x00000000 - fields: - BOOT_CM4_ADD1: - description: Arm Cortex-M4 boot address 1 - bitOffset: 16 - bitWidth: 16 - BOOT_CM4_ADD0: - description: Arm Cortex-M4 boot address 0 - bitOffset: 0 - bitWidth: 16 - BOOT4_PRGR: - description: FLASH register boot address for Arm Cortex-M4 core - addressOffset: 0x04C - resetValue: 0x00000000 - fields: - BOOT_CM4_ADD1: - description: Arm Cortex-M4 boot address 1 configuration - bitOffset: 16 - bitWidth: 16 - BOOT_CM4_ADD0: - description: Arm Cortex-M4 boot address 0 configuration - bitOffset: 0 - bitWidth: 16 - CRCCR1: - description: FLASH CRC control register for bank 1 - addressOffset: 0x050 - resetValue: 0x001C0000 - fields: - ALL_BANK: - description: Bank 1 CRC select bit - bitOffset: 22 - bitWidth: 1 - CRC_BURST: - description: Bank 1 CRC burst size - bitOffset: 20 - bitWidth: 2 - CLEAN_CRC: - description: Bank 1 CRC clear bit - bitOffset: 17 - bitWidth: 1 - START_CRC: - description: Bank 1 CRC start bit - bitOffset: 16 - bitWidth: 1 - CLEAN_SECT: - description: Bank 1 CRC sector list clear bit - bitOffset: 10 - bitWidth: 1 - ADD_SECT: - description: Bank 1 CRC sector select bit - bitOffset: 9 - bitWidth: 1 - CRC_BY_SECT: - description: Bank 1 CRC sector mode select bit - bitOffset: 8 - bitWidth: 1 - CRC_SECT: - description: Bank 1 CRC sector number - bitOffset: 0 - bitWidth: 3 - CRCSADD1R: - description: FLASH CRC start address register for bank 1 - addressOffset: 0x054 - resetValue: 0x00000000 - fields: - CRC_START_ADDR: - description: CRC start address on bank 1 - bitOffset: 2 - bitWidth: 18 - CRCEADD1R: - description: FLASH CRC end address register for bank 1 - addressOffset: 0x058 - resetValue: 0x00000000 - fields: - CRC_END_ADDR: - description: CRC end address on bank 1 - bitOffset: 2 - bitWidth: 18 - CRCDATAR: - description: FLASH CRC data register - addressOffset: 0x05C - resetValue: 0x00000000 - fields: - CRC_DATA: - description: CRC result - bitOffset: 0 - bitWidth: 32 - ECC_FA1R: - description: FLASH ECC fail address for bank 1 - addressOffset: 0x060 - resetValue: 0x00000000 - fields: - FAIL_ECC_ADDR1: - description: Bank 1 ECC error address - bitOffset: 0 - bitWidth: 15 - KEYR2: - description: FLASH key register for bank 2 - addressOffset: 0x104 - resetValue: 0x00000000 - access: write-only - fields: - KEYR: - description: Bank access configuration unlock key - bitOffset: 0 - bitWidth: 32 - CR2: - description: FLASH control register for bank 2 - addressOffset: 0x10C - resetValue: 0x00000031 - fields: - CRCRDERRIE: - description: Bank 2 CRC read error interrupt enable bit - bitOffset: 28 - bitWidth: 1 - CRCENDIE: - description: Bank 2 CRC end of calculation interrupt enable bit - bitOffset: 27 - bitWidth: 1 - DBECCERRIE: - description: Bank 2 ECC double detection error interrupt enable bit - bitOffset: 26 - bitWidth: 1 - SNECCERRIE: - description: Bank 2 ECC single correction error interrupt enable bit - bitOffset: 25 - bitWidth: 1 - RDSERRIE: - description: Bank 2 secure error interrupt enable bit - bitOffset: 24 - bitWidth: 1 - RDPERRIE: - description: Bank 2 read protection error interrupt enable bit - bitOffset: 23 - bitWidth: 1 - OPERRIE: - description: Bank 2 write - bitOffset: 22 - bitWidth: 1 - INCERRIE: - description: Bank 2 inconsistency error interrupt enable bit - bitOffset: 21 - bitWidth: 1 - STRBERRIE: - description: Bank 2 strobe error interrupt enable bit - bitOffset: 19 - bitWidth: 1 - PGSERRIE: - description: Bank 2 programming sequence error interrupt enable bit - bitOffset: 18 - bitWidth: 1 - WRPERRIE: - description: Bank 2 write protection error interrupt enable bit - bitOffset: 17 - bitWidth: 1 - EOPIE: - description: Bank 2 end-of-program interrupt control bit - bitOffset: 16 - bitWidth: 1 - CRC_EN: - description: Bank 2 CRC control bit - bitOffset: 15 - bitWidth: 1 - SNB: - description: Bank 2 sector erase selection number - bitOffset: 8 - bitWidth: 3 - START: - description: Bank 2 erase start control bit - bitOffset: 7 - bitWidth: 1 - FW: - description: Bank 2 write forcing control bit - bitOffset: 6 - bitWidth: 1 - PSIZE: - description: Bank 2 program size - bitOffset: 4 - bitWidth: 2 - BER: - description: Bank 2 erase request - bitOffset: 3 - bitWidth: 1 - SER: - description: Bank 2 sector erase request - bitOffset: 2 - bitWidth: 1 - PG: - description: Bank 2 internal buffer control bit - bitOffset: 1 - bitWidth: 1 - LOCK: - description: Bank 2 configuration lock bit - bitOffset: 0 - bitWidth: 1 - SR2: - description: FLASH status register for bank 2 - addressOffset: 0x110 - resetValue: 0x00000000 - fields: - CRCRDERR2: - description: Bank 2 CRC read error flag - bitOffset: 28 - bitWidth: 1 - CRCEND2: - description: Bank 2 CRC end of calculation flag - bitOffset: 27 - bitWidth: 1 - DBECCERR2: - description: Bank 2 ECC double detection error flag - bitOffset: 26 - bitWidth: 1 - SNECCERR2: - description: Bank 2 single correction error flag - bitOffset: 25 - bitWidth: 1 - RDSERR2: - description: Bank 2 secure error flag - bitOffset: 24 - bitWidth: 1 - RDPERR2: - description: Bank 2 read protection error flag - bitOffset: 23 - bitWidth: 1 - OPERR2: - description: Bank 2 write - bitOffset: 22 - bitWidth: 1 - INCERR2: - description: Bank 2 inconsistency error flag - bitOffset: 21 - bitWidth: 1 - STRBERR2: - description: Bank 2 strobe error flag - bitOffset: 19 - bitWidth: 1 - PGSERR2: - description: Bank 2 programming sequence error flag - bitOffset: 18 - bitWidth: 1 - WRPERR2: - description: Bank 2 write protection error flag - bitOffset: 17 - bitWidth: 1 - EOP2: - description: Bank 2 end-of-program flag - bitOffset: 16 - bitWidth: 1 - CRC_BUSY2: - description: Bank 2 CRC busy flag - bitOffset: 3 - bitWidth: 1 - QW2: - description: Bank 2 wait queue flag - bitOffset: 2 - bitWidth: 1 - WBNE2: - description: Bank 2 write buffer not empty flag - bitOffset: 1 - bitWidth: 1 - BSY2: - description: Bank 2 busy flag - bitOffset: 0 - bitWidth: 1 - CCR2: - description: FLASH clear control register for bank 2 - addressOffset: 0x114 - resetValue: 0x00000000 - fields: - CLR_CRCRDERR2: - description: Bank 2 CRCRDERR2 flag clear bit - bitOffset: 28 - bitWidth: 1 - CLR_CRCEND2: - description: Bank 2 CRCEND2 flag clear bit - bitOffset: 27 - bitWidth: 1 - CLR_DBECCERR2: - description: Bank 2 DBECCERR2 flag clear bit - bitOffset: 26 - bitWidth: 1 - CLR_SNECCERR2: - description: Bank 2 SNECCERR2 flag clear bit - bitOffset: 25 - bitWidth: 1 - CLR_RDSERR2: - description: Bank 2 RDSERR2 flag clear bit - bitOffset: 24 - bitWidth: 1 - CLR_RDPERR2: - description: Bank 2 RDPERR2 flag clear bit - bitOffset: 23 - bitWidth: 1 - CLR_OPERR2: - description: Bank 2 OPERR2 flag clear bit - bitOffset: 22 - bitWidth: 1 - CLR_INCERR2: - description: Bank 2 INCERR2 flag clear bit - bitOffset: 21 - bitWidth: 1 - CLR_STRBERR2: - description: Bank 2 STRBERR2 flag clear bit - bitOffset: 19 - bitWidth: 1 - CLR_PGSERR2: - description: Bank 2 PGSERR2 flag clear bit - bitOffset: 18 - bitWidth: 1 - CLR_WRPERR2: - description: Bank 2 WRPERR2 flag clear bit - bitOffset: 17 - bitWidth: 1 - CLR_EOP2: - description: Bank 2 EOP2 flag clear bit - bitOffset: 16 - bitWidth: 1 - PRAR_CUR2: - description: FLASH protection address for bank 2 - addressOffset: 0x128 - resetValue: 0x00000000 - fields: - DMEP2: - description: Bank 2 PCROP protected erase enable option status bit - bitOffset: 31 - bitWidth: 1 - PROT_AREA_END2: - description: Bank 2 PCROP area end status bits - bitOffset: 16 - bitWidth: 12 - PROT_AREA_START2: - description: Bank 2 PCROP area start status bits - bitOffset: 0 - bitWidth: 12 - PRAR_PRG2: - description: FLASH protection address for bank 2 - addressOffset: 0x12C - resetValue: 0x00000000 - fields: - DMEP2: - description: Bank 2 PCROP protected erase enable option configuration bit - bitOffset: 31 - bitWidth: 1 - PROT_AREA_END2: - description: Bank 2 PCROP area end configuration bits - bitOffset: 16 - bitWidth: 12 - PROT_AREA_START2: - description: Bank 2 PCROP area start configuration bits - bitOffset: 0 - bitWidth: 12 - SCAR_CUR2: - description: FLASH secure address for bank 2 - addressOffset: 0x130 - resetValue: 0x00000000 - fields: - DMES2: - description: Bank 2 secure protected erase enable option status bit - bitOffset: 31 - bitWidth: 1 - SEC_AREA_END2: - description: Bank 2 secure-only area end status bits - bitOffset: 16 - bitWidth: 12 - SEC_AREA_START2: - description: Bank 2 secure-only area start status bits - bitOffset: 0 - bitWidth: 12 - SCAR_PRG2: - description: FLASH secure address for bank 2 - addressOffset: 0x134 - resetValue: 0x00000000 - fields: - DMES2: - description: Bank 2 secure access protected erase enable option configuration bit - bitOffset: 31 - bitWidth: 1 - SEC_AREA_END2: - description: Bank 2 secure-only area end configuration bits - bitOffset: 16 - bitWidth: 12 - SEC_AREA_START2: - description: Bank 2 secure-only area start configuration bits - bitOffset: 0 - bitWidth: 12 - WPSN_CUR2R: - description: FLASH write sector protection for bank 2 - addressOffset: 0x138 - resetValue: 0x00000000 - fields: - WRPSN2: - description: Bank 2 sector write protection option status byte - bitOffset: 0 - bitWidth: 8 - WPSN_PRG2R: - description: FLASH write sector protection for bank 2 - addressOffset: 0x13C - resetValue: 0x00000000 - fields: - WRPSN2: - description: Bank 2 sector write protection option status byte - bitOffset: 0 - bitWidth: 8 - CRCCR2: - description: FLASH CRC control register for bank 2 - addressOffset: 0x150 - resetValue: 0x001C0000 - fields: - ALL_BANK: - description: Bank 2 CRC select bit - bitOffset: 22 - bitWidth: 1 - CRC_BURST: - description: Bank 2 CRC burst size - bitOffset: 20 - bitWidth: 2 - CLEAN_CRC: - description: Bank 2 CRC clear bit - bitOffset: 17 - bitWidth: 1 - START_CRC: - description: Bank 2 CRC start bit - bitOffset: 16 - bitWidth: 1 - CLEAN_SECT: - description: Bank 2 CRC sector list clear bit - bitOffset: 10 - bitWidth: 1 - ADD_SECT: - description: Bank 2 CRC sector select bit - bitOffset: 9 - bitWidth: 1 - CRC_BY_SECT: - description: Bank 2 CRC sector mode select bit - bitOffset: 8 - bitWidth: 1 - CRC_SECT: - description: Bank 2 CRC sector number - bitOffset: 0 - bitWidth: 3 - CRCSADD2R: - description: FLASH CRC start address register for bank 2 - addressOffset: 0x154 - resetValue: 0x00000000 - fields: - CRC_START_ADDR: - description: CRC start address on bank 2 - bitOffset: 2 - bitWidth: 18 - CRCEADD2R: - description: FLASH CRC end address register for bank 2 - addressOffset: 0x158 - resetValue: 0x00000000 - fields: - CRC_END_ADDR: - description: CRC end address on bank 2 - bitOffset: 2 - bitWidth: 18 - ECC_FA2R: - description: FLASH ECC fail address for bank 2 - addressOffset: 0x160 - resetValue: 0x00000000 - fields: - FAIL_ECC_ADDR: - description: Bank 2 ECC error address - bitOffset: 0 - bitWidth: 15 diff --git a/devices/common_patches/h7_ethernet_combined_desc.yaml b/devices/common_patches/h7_ethernet_combined_desc.yaml deleted file mode 100644 index 98bb51a14..000000000 --- a/devices/common_patches/h7_ethernet_combined_desc.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# Applies to H7 where MAC and MTL registers are combined under -# the Ethernet_MAC peripheral - -# Create separate DMA and MTL periperhals -_include: - - ./h7_ethernet_dma.yaml - - ./h7_ethernet_mtl.yaml - -Ethernet_MAC: - # Delete DMA and MTL parts from MAC - _delete: - _registers: - - DMA* - - MTL* - - # Descriptions for MAC - _include: - - ./h7_ethernet_desc_mac.yaml diff --git a/devices/common_patches/h7_ethernet_desc.yaml b/devices/common_patches/h7_ethernet_desc.yaml deleted file mode 100644 index 6c53cd5e4..000000000 --- a/devices/common_patches/h7_ethernet_desc.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# Applies to H7 - -Ethernet_MTL: - _include: - - ./h7_ethernet_desc_mtl.yaml - -Ethernet_MAC: - _include: - - ./h7_ethernet_desc_mac.yaml diff --git a/devices/common_patches/h7_ethernet_desc_mac.yaml b/devices/common_patches/h7_ethernet_desc_mac.yaml deleted file mode 100644 index 673ca79a8..000000000 --- a/devices/common_patches/h7_ethernet_desc_mac.yaml +++ /dev/null @@ -1,828 +0,0 @@ -# Descriptions of H7 Media Access Control module (MAC) registers - -MACCR: - _modify: - RE: - description: Receiver Enable - TE: - description: Transmitter Enable - PRELEN: - description: Preamble Length for Transmit Packets - DC: - description: Deferral Check - BL: - description: Back-Off Limit - DR: - description: Disable Retry - DCRS: - description: Disable Carrier Sense During Transmission - DO: - description: Disable Receive Own - ECRSFD: - description: Enable Carrier Sense Before Transmission in Full-Duplex Mode - LM: - description: Loopback Mode - DM: - description: Duplex Mode - FES: - description: MAC Speed - JE: - description: Jumbo Packet Enable - JD: - description: Jabber Disable - WD: - description: Watchdog Disable - ACS: - description: Automatic Pad or CRC Stripping - CST: - description: CRC stripping for Type packets - S2KP: - description: IEEE 802.3as Support for 2K Packets - GPSLCE: - description: Giant Packet Size Limit Control Enable - IPG: - description: Inter-Packet Gap - IPC: - description: Checksum Offload - SARC: - description: Source Address Insertion or Replacement Control - ARPEN: - description: ARP Offload Enable -MACECR: - _modify: - GPSL: - description: Giant Packet Size Limit - DCRCC: - description: Disable CRC Checking for Received Packets - SPEN: - description: Slow Protocol Detection Enable - USP: - description: Unicast Slow Protocol Packet Detect - EIPGEN: - description: Extended Inter-Packet Gap Enable - EIPG: - description: Extended Inter-Packet Gap -MACPFR: - _modify: - RA: - description: Receive All - DNTU: - description: Drop Non-TCP/UDP over IP Packets - IPFE: - description: Layer 3 and Layer 4 Filter Enable - VTFE: - description: VLAN Tag Filter Enable - HPF: - description: Hash or Perfect Filter - SAF: - description: Source Address Filter Enable - SAIF: - description: SA Inverse Filtering - PCF: - description: Pass Control Packets - DBF: - description: Disable Broadcast Packets - PM: - description: Pass All Multicast - DAIF: - description: DA Inverse Filtering - HMC: - description: Hash Multicast - HUC: - description: Hash Unicast - PR: - description: Promiscuous Mode -MACWTR: - _modify: - WTO: - description: Watchdog Timeout - PWE: - description: Programmable Watchdog Enable -MACHT0R: - _modify: - HT31T0: - description: MAC Hash Table First 32 Bits -MACHT1R: - _modify: - HT63T32: - description: MAC Hash Table Second 32 Bits -MACVTR: - _modify: - EIVLRXS: - description: Enable Inner VLAN Tag in Rx Status - EIVLS: - description: Enable Inner VLAN Tag Stripping on Receive - ERIVLT: - description: Enable Inner VLAN Tag - EDVLP: - description: Enable Double VLAN Processing - VTHM: - description: VLAN Tag Hash Table Match Enable - EVLRXS: - description: Enable VLAN Tag in Rx status - EVLS: - description: Enable VLAN Tag Stripping on Receive - DOVLTC: - description: Disable VLAN Type Check - ERSVLM: - description: Enable Receive S-VLAN Match - ESVL: - description: Enable S-VLAN - VTIM: - description: VLAN Tag Inverse Match Enable - ETV: - description: Enable 12-Bit VLAN Tag Comparison - VL: - description: VLAN Tag Identifier for Receive Packets -MACVHTR: - _modify: - VLHT: - description: VLAN Hash Table -MACVIR: - _modify: - VLTI: - description: VLAN Tag Input - CSVL: - description: C-VLAN or S-VLAN - VLP: - description: VLAN Priority Control - VLC: - description: VLAN Tag Control in Transmit Packets - VLT: - description: VLAN Tag for Transmit Packets -MACIVIR: - _modify: - VLTI: - description: VLAN Tag Input - CSVL: - description: C-VLAN or S-VLAN - VLP: - description: VLAN Priority Control - VLC: - description: VLAN Tag Control in Transmit Packets - VLT: - description: VLAN Tag for Transmit Packets -MACQTxFCR: - _modify: - PT: - description: Pause Time - DZPQ: - description: Disable Zero-Quanta Pause - PLT: - description: Pause Low Threshold - TFE: - description: Transmit Flow Control Enable - FCB_BPA: - description: Flow Control Busy or Backpressure Activate -MACRxFCR: - _modify: - UP: - description: Unicast Pause Packet Detect - RFE: - description: Receive Flow Control Enable -MACISR: - _modify: - RXSTSIS: - description: Receive Status Interrupt - TXSTSIS: - description: Transmit Status Interrupt - TSIS: - description: Timestamp Interrupt Status - MMCTXIS: - description: MMC Transmit Interrupt Status - MMCRXIS: - description: MMC Receive Interrupt Status - MMCIS: - description: MMC Interrupt Status - LPIIS: - description: LPI Interrupt Status - PMTIS: - description: PMT Interrupt Status - PHYIS: - description: PHY Interrupt -MACIER: - _modify: - RXSTSIE: - description: Receive Status Interrupt Enable - TXSTSIE: - description: Transmit Status Interrupt Enable - TSIE: - description: Timestamp Interrupt Enable - LPIIE: - description: LPI Interrupt Enable - PMTIE: - description: PMT Interrupt Enable - PHYIE: - description: PHY Interrupt Enable -MACRxTxSR: - _modify: - RWT: - description: Receive Watchdog Timeout - EXCOL: - description: Excessive Collisions - LCOL: - description: Late Collision - EXDEF: - description: Excessive Deferral - LCARR: - description: Loss of Carrier - NCARR: - description: No Carrier - TJT: - description: Transmit Jabber Timeout -MACPCSR: - _modify: - RWKFILTRST: - description: Remote wakeup Packet Filter Register Pointer Reset - RWKPTR: - description: Remote wakeup FIFO Pointer - RWKPFE: - description: Remote wakeup Packet Forwarding Enable - GLBLUCAST: - description: Global Unicast - RWKPRCVD: - description: Remote wakeup Packet Received - MGKPRCVD: - description: Magic Packet Received - RWKPKTEN: - description: Remote wakeup Packet Enable - MGKPKTEN: - description: Magic Packet Enable - PWRDWN: - description: Power Down -MACRWKPFR: - _modify: - MACRWKPFR: - description: Remote wakeup packet filter -MACLCSR: - _modify: - LPITE: - description: LPI Timer Enable - LPITXA: - description: LPI Tx Automate - PLSEN: - description: PHY Link Status Enable - PLS: - description: PHY Link Status - LPIEN: - description: LPI Enable - RLPIST: - description: Receive LPI State - TLPIST: - description: Transmit LPI State - RLPIEX: - description: Receive LPI Exit - RLPIEN: - description: Receive LPI Entry - TLPIEX: - description: Transmit LPI Exit - TLPIEN: - description: Transmit LPI Entry -MACLTCR: - _modify: - LST: - description: LPI LS Timer - TWT: - description: LPI TW Timer -MACLETR: - _modify: - LPIET: - description: LPI Entry Timer -MAC1USTCR: - _modify: - TIC_1US_CNTR: - description: 1 µs tick Counter -MACVR: - _modify: - USERVER: - description: ST-defined version - SNPSVER: - description: IP version -MACDR: - _modify: - TFCSTS: - description: MAC Transmit Packet Controller Status - TPESTS: - description: MAC MII Transmit Protocol Engine Status - RFCFCSTS: - description: MAC Receive Packet Controller FIFO Status - RPESTS: - description: MAC MII Receive Protocol Engine Status -MACHWF1R: - _modify: - L3L4FNUM: - description: Total number of L3 or L4 Filters - HASHTBLSZ: - description: Hash Table Size - AVSEL: - description: AV Feature Enable - DBGMEMA: - description: DMA Debug Registers Enable - TSOEN: - description: TCP Segmentation Offload Enable - SPHEN: - description: Split Header Feature Enable - DCBEN: - description: DCB Feature Enable - ADDR64: - description: Address width - ADVTHWORD: - description: IEEE 1588 High Word Register Enable - PTOEN: - description: PTP Offload Enable - OSTEN: - description: One-Step Timestamping Enable - TXFIFOSIZE: - description: MTL Transmit FIFO Size - RXFIFOSIZE: - description: MTL Receive FIFO Size -MACHWF2R: - _modify: - AUXSNAPNUM: - description: Number of Auxiliary Snapshot Inputs - PPSOUTNUM: - description: Number of PPS Outputs - TXCHCNT: - description: Number of DMA Transmit Channels - RXCHCNT: - description: Number of DMA Receive Channels - TXQCNT: - description: Number of MTL Transmit Queues - RXQCNT: - description: Number of MTL Receive Queues -MACMDIOAR: - _modify: - PSE: - description: Preamble Suppression Enable - BTB: - description: Back to Back transactions - PA: - description: Physical Layer Address - RDA: - description: Register/Device Address - NTC: - description: Number of Training Clocks - CR: - description: CSR Clock Range - SKAP: - description: Skip Address Packet - GOC: - description: MII Operation Command - C45E: - description: Clause 45 PHY Enable - MB: - description: MII Busy -MACMDIODR: - _modify: - RA: - description: Register Address - MD: - description: MII Data -MACARPAR: - _modify: - # TODO - this might actually be at 0xAE0 - the reference manual says it - # is, but ST's own HAL and where they locate it in the map disagree. - ARPPA: - description: ARP Protocol Address -MACA0HR: - _modify: - AE: - description: Address Enable - ADDRHI: - description: MAC Address0[47:32] -MACA0LR: - _modify: - ADDRLO: - description: MAC Address 0 [31:0] -MACA1LR: - _modify: - ADDRLO: - description: MAC Address 1 [31:0] -MACA2LR: - _modify: - ADDRLO: - description: MAC Address 2 [31:0] -MACA3LR: - _modify: - ADDRLO: - description: MAC Address 3 [31:0] -MACA1HR: - _modify: - AE: - description: Address Enable - SA: - description: Source Address - MBC: - description: Mask Byte Control - ADDRHI: - description: MAC Address1 [47:32] -MACA2HR: - _modify: - AE: - description: Address Enable - SA: - description: Source Address - MBC: - description: Mask Byte Control - ADDRHI: - description: MAC Address2 [47:32] -MACA3HR: - _modify: - AE: - description: Address Enable - SA: - description: Source Address - MBC: - description: Mask Byte Control - ADDRHI: - description: MAC Address3 [47:32] -TX_SINGLE_COLLISION_GOOD_PACKETS: - _modify: - TXSNGLCOLG: - description: Tx Single Collision Good Packets -TX_MULTIPLE_COLLISION_GOOD_PACKETS: - _modify: - TXMULTCOLG: - description: Tx Multiple Collision Good Packets -TX_PACKET_COUNT_GOOD: - _modify: - TXPKTG: - description: Tx Packet Count Good -RX_CRC_ERROR_PACKETS: - _modify: - RXCRCERR: - description: Rx CRC Error Packets -RX_ALIGNMENT_ERROR_PACKETS: - _modify: - RXALGNERR: - description: Rx Alignment Error Packets -RX_UNICAST_PACKETS_GOOD: - _modify: - RXUCASTG: - description: Rx Unicast Packets Good -TX_LPI_USEC_CNTR: - _modify: - TXLPIUSC: - description: Tx LPI Microseconds Counter -TX_LPI_TRAN_CNTR: - _modify: - TXLPITRC: - description: Tx LPI Transition counter -RX_LPI_USEC_CNTR: - _modify: - RXLPIUSC: - description: Rx LPI Microseconds Counter -RX_LPI_TRAN_CNTR: - _modify: - RXLPITRC: - description: Rx LPI Transition counter -MACL3L4C0R: - _modify: - L4DPIM0: - description: Layer 4 Destination Port Inverse Match Enable - L4DPM0: - description: Layer 4 Destination Port Match Enable - L4SPIM0: - description: Layer 4 Source Port Inverse Match Enable - L4SPM0: - description: Layer 4 Source Port Match Enable - L4PEN0: - description: Layer 4 Protocol Enable - L3HDBM0: - description: Layer 3 IP DA Higher Bits Match - L3HSBM0: - description: Layer 3 IP SA Higher Bits Match - L3DAIM0: - description: Layer 3 IP DA Inverse Match Enable - L3DAM0: - description: Layer 3 IP DA Match Enable - L3SAIM0: - description: Layer 3 IP SA Inverse Match Enable - L3SAM0: - description: Layer 3 IP SA Match Enable - L3PEN0: - description: Layer 3 Protocol Enable -MACL4A0R: - _modify: - L4DP0: - description: Layer 4 Destination Port Number Field - L4SP0: - description: Layer 4 Source Port Number Field -MACL3A00R: - _modify: - L3A00: - description: Layer 3 Address 0 Field -MACL3A10R: - _modify: - L3A10: - description: Layer 3 Address 1 Field -MACL3A20: - _modify: - L3A20: - description: Layer 3 Address 2 Field -MACL3A30: - _modify: - L3A30: - description: Layer 3 Address 3 Field -MACL3L4C1R: - _modify: - L4DPIM1: - description: Layer 4 Destination Port Inverse Match Enable - L4DPM1: - description: Layer 4 Destination Port Match Enable - L4SPIM1: - description: Layer 4 Source Port Inverse Match Enable - L4SPM1: - description: Layer 4 Source Port Match Enable - L4PEN1: - description: Layer 4 Protocol Enable - L3HDBM1: - description: Layer 3 IP DA Higher Bits Match - L3HSBM1: - description: Layer 3 IP SA Higher Bits Match - L3DAIM1: - description: Layer 3 IP DA Inverse Match Enable - L3DAM1: - description: Layer 3 IP DA Match Enable - L3SAIM1: - description: Layer 3 IP SA Inverse Match Enable - L3SAM1: - description: Layer 3 IP SA Match Enable - L3PEN1: - description: Layer 3 Protocol Enable -MACL4A1R: - _modify: - L4DP1: - description: Layer 4 Destination Port Number Field - L4SP1: - description: Layer 4 Source Port Number Field -MACL3A01R: - _modify: - L3A01: - description: Layer 3 Address 0 Field -MACL3A11R: - _modify: - L3A11: - description: Layer 3 Address 1 Field -MACL3A21R: - _modify: - L3A21: - description: Layer 3 Address 2 Field -MACL3A31R: - _modify: - L3A31: - description: Layer 3 Address 3 Field -MACTSCR: - _modify: - TXTSSTSM: - description: Transmit Timestamp Status Mode - CSC: - description: Enable checksum correction during OST for PTP over UDP/IPv4 packets - TSENMACADDR: - description: Enable MAC Address for PTP Packet Filtering - SNAPTYPSEL: - description: Select PTP packets for Taking Snapshots - TSMSTRENA: - description: Enable Snapshot for Messages Relevant to Master - TSEVNTENA: - description: Enable Timestamp Snapshot for Event Messages - TSIPV4ENA: - description: Enable Processing of PTP Packets Sent over IPv4-UDP - TSIPV6ENA: - description: Enable Processing of PTP Packets Sent over IPv6-UDP - TSIPENA: - description: Enable Processing of PTP over Ethernet Packets - TSVER2ENA: - description: Enable PTP Packet Processing for Version 2 Format - TSCTRLSSR: - description: Timestamp Digital or Binary Rollover Control - TSENALL: - description: Enable Timestamp for All Packets - TSADDREG: - description: Update Addend Register - TSUPDT: - description: Update Timestamp - TSINIT: - description: Initialize Timestamp - TSCFUPDT: - description: Fine or Coarse Timestamp Update - TSENA: - description: Enable Timestamp -MACSSIR: - _modify: - SSINC: - description: Sub-second Increment Value - SNSINC: - description: Sub-nanosecond Increment Value -MACSTSR: - _modify: - TSS: - description: Timestamp Second -MACSTNR: - _modify: - TSSS: - description: Timestamp Sub-seconds -MACSTSUR: - _modify: - TSS: - description: Timestamp Seconds -MACSTNUR: - _modify: - ADDSUB: - description: Add or Subtract Time - TSSS: - description: Timestamp Sub-seconds -MACTSAR: - _modify: - TSAR: - description: Timestamp Addend Register -MACTSSR: - _modify: - ATSNS: - description: Number of Auxiliary Timestamp Snapshots - ATSSTM: - description: Auxiliary Timestamp Snapshot Trigger Missed - ATSSTN: - description: Auxiliary Timestamp Snapshot Trigger Identifier - TXTSSIS: - description: Tx Timestamp Status Interrupt Status - TSTRGTERR0: - description: Timestamp Target Time Error - AUXTSTRIG: - description: Auxiliary Timestamp Trigger Snapshot - TSTARGT0: - description: Timestamp Target Time Reached - TSSOVF: - description: Timestamp Seconds Overflow -MACTxTSSNR: - _modify: - TXTSSMIS: - description: Transmit Timestamp Status Missed - TXTSSLO: - description: Transmit Timestamp Status Low -MACTxTSSSR: - _modify: - TXTSSHI: - description: Transmit Timestamp Status High -MACACR: - _modify: - ATSEN3: - description: Auxiliary Snapshot 3 Enable - ATSEN2: - description: Auxiliary Snapshot 2 Enable - ATSEN1: - description: Auxiliary Snapshot 1 Enable - ATSEN0: - description: Auxiliary Snapshot 0 Enable - ATSFC: - description: Auxiliary Snapshot FIFO Clear -MACATSNR: - _modify: - AUXTSLO: - description: Auxiliary Timestamp -MACATSSR: - _modify: - AUXTSHI: - description: Auxiliary Timestamp -MACTSIACR: - _modify: - OSTIAC: - description: One-Step Timestamp Ingress Asymmetry Correction -MACTSEACR: - _modify: - OSTEAC: - description: One-Step Timestamp Egress Asymmetry Correction -MACTSICNR: - _modify: - TSIC: - description: Timestamp Ingress Correction -MACTSECNR: - _modify: - TSEC: - description: Timestamp Egress Correction -MACPPSCR: - _modify: - TRGTMODSEL0: - description: Target Time Register Mode for PPS Output - PPSEN0: - description: Flexible PPS Output Mode Enable - PPSCTRL: - description: Flexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS Output Frequency Control if PPSEN0 is cleared -MACPPSTTSR: - _modify: - TSTRH0: - description: PPS Target Time Seconds Register -MACPPSTTNR: - _modify: - TRGTBUSY0: - description: PPS Target Time Register Busy - TTSL0: - description: Target Time Low for PPS Register -MACPPSIR: - _modify: - PPSINT0: - description: PPS Output Signal Interval -MACPPSWR: - _modify: - PPSWIDTH0: - description: PPS Output Signal Width -MACPOCR: - _modify: - DN: - description: Domain Number - DRRDIS: - description: Disable PTO Delay Request/Response response generation - APDREQTRIG: - description: Automatic PTP Pdelay_Req message Trigger - ASYNCTRIG: - description: Automatic PTP SYNC message Trigger - APDREQEN: - description: Automatic PTP Pdelay_Req message Enable - ASYNCEN: - description: Automatic PTP SYNC message Enable - PTOEN: - description: PTP Offload Enable -MACSPI0R: - _modify: - SPI0: - description: Source Port Identity 0 -MACSPI1R: - _modify: - SPI1: - description: Source Port Identity 1 -MACSPI2R: - _modify: - SPI2: - description: Source Port Identity 2 -MACLMIR: - _modify: - LMPDRI: - description: Log Min Pdelay_Req Interval - DRSYNCR: - description: Delay_Req to SYNC Ratio - LSI: - description: Log Sync Interval -MMC_CONTROL: - _modify: - UCDBC: - description: Update MMC Counters for Dropped Broadcast Packets - CNTPRSTLVL: - description: Full-Half Preset - CNTPRST: - description: Counters Preset - CNTFREEZ: - description: MMC Counter Freeze - RSTONRD: - description: Reset on Read - CNTSTOPRO: - description: Counter Stop Rollover - CNTRST: - description: Counters Reset -MMC_RX_INTERRUPT: - _modify: - RXLPITRCIS: - description: MMC Receive LPI transition counter interrupt status - RXLPIUSCIS: - description: MMC Receive LPI microsecond counter interrupt status - RXUCGPIS: - description: MMC Receive Unicast Good Packet Counter Interrupt Status - RXALGNERPIS: - description: MMC Receive Alignment Error Packet Counter Interrupt Status - RXCRCERPIS: - description: MMC Receive CRC Error Packet Counter Interrupt Status -MMC_TX_INTERRUPT: - _modify: - TXLPITRCIS: - description: MMC Transmit LPI transition counter interrupt status - TXLPIUSCIS: - description: MMC Transmit LPI microsecond counter interrupt status - TXGPKTIS: - description: MMC Transmit Good Packet Counter Interrupt Status - TXMCOLGPIS: - description: MMC Transmit Multiple Collision Good Packet Counter Interrupt Status - TXSCOLGPIS: - description: MMC Transmit Single Collision Good Packet Counter Interrupt Status -MMC_RX_INTERRUPT_MASK: - _modify: - RXLPITRCIM: - description: MMC Receive LPI transition counter interrupt Mask - RXLPIUSCIM: - description: MMC Receive LPI microsecond counter interrupt Mask - RXUCGPIM: - description: MMC Receive Unicast Good Packet Counter Interrupt Mask - RXALGNERPIM: - description: MMC Receive Alignment Error Packet Counter Interrupt Mask - RXCRCERPIM: - description: MMC Receive CRC Error Packet Counter Interrupt Mask -MMC_TX_INTERRUPT_MASK: - _modify: - TXLPITRCIM: - description: MMC Transmit LPI transition counter interrupt Mask - TXLPIUSCIM: - description: MMC Transmit LPI microsecond counter interrupt Mask - TXGPKTIM: - description: MMC Transmit Good Packet Counter Interrupt Mask - TXMCOLGPIM: - description: MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask - TXSCOLGPIM: - description: MMC Transmit Single Collision Good Packet Counter Interrupt Mask diff --git a/devices/common_patches/h7_ethernet_dma.yaml b/devices/common_patches/h7_ethernet_dma.yaml deleted file mode 100644 index 95aa6b93c..000000000 --- a/devices/common_patches/h7_ethernet_dma.yaml +++ /dev/null @@ -1,380 +0,0 @@ -# Add H7 Ethernet DMA peripheral - -_add: - Ethernet_DMA: - description: Ethernet DMA - baseAddress: 0x40029000 - registers: - DMAMR: - description: DMA mode register - addressOffset: 0x0000 - resetValue: 0x00000000 - fields: - INTM: - description: Interrupt Mode - bitOffset: 16 - bitWidth: 2 - PR: - description: Priority ratio - bitOffset: 12 - bitWidth: 3 - TXPR: - description: Transmit priority - bitOffset: 11 - bitWidth: 1 - DA: - description: DMA Tx or Rx Arbitration Scheme - bitOffset: 1 - bitWidth: 1 - SWR: - description: Software Reset - bitOffset: 0 - bitWidth: 1 - DMASBMR: - description: System bus mode register - addressOffset: 0x0004 - resetValue: 0x01010000 - fields: - RB: - description: Rebuild INCRx Burst - bitOffset: 15 - bitWidth: 1 - MB: - description: Mixed Burst - bitOffset: 14 - bitWidth: 1 - AAL: - description: Address-Aligned Beats - bitOffset: 12 - bitWidth: 1 - FB: - description: Fixed Burst Length - bitOffset: 0 - bitWidth: 1 - DMAISR: - description: Interrupt status register - addressOffset: 0x0008 - resetValue: 0x00000000 - fields: - MACIS: - description: MAC Interrupt Status - bitOffset: 17 - bitWidth: 1 - MTLIS: - description: MTL Interrupt Status - bitOffset: 16 - bitWidth: 1 - DC0IS: - description: DMA Channel Interrupt Status - bitOffset: 0 - bitWidth: 1 - DMADSR: - description: Debug status register - addressOffset: 0x000C - resetValue: 0x00000000 - fields: - TPS0: - description: DMA Channel Transmit Process State - bitOffset: 12 - bitWidth: 4 - RPS0: - description: DMA Channel Receive Process State - bitOffset: 8 - bitWidth: 4 - AXWHSTS: - description: AHB Master Write Channel - bitOffset: 0 - bitWidth: 1 - DMACCR: - description: Channel control register - addressOffset: 0x0100 - resetValue: 0x00000000 - fields: - DSL: - description: Descriptor Skip Length - bitOffset: 18 - bitWidth: 3 - PBLX8: - description: 8xPBL mode - bitOffset: 16 - bitWidth: 1 - MSS: - description: Maximum Segment Size - bitOffset: 0 - bitWidth: 14 - DMACTxCR: - description: Channel transmit control register - addressOffset: 0x0104 - resetValue: 0x00000000 - fields: - TXPBL: - description: Transmit Programmable Burst Length - bitOffset: 16 - bitWidth: 6 - TSE: - description: TCP Segmentation Enabled - bitOffset: 12 - bitWidth: 1 - OSF: - description: Operate on Second Packet - bitOffset: 4 - bitWidth: 1 - ST: - description: Start or Stop Transmission Command - bitOffset: 0 - bitWidth: 1 - DMACRxCR: - description: Channel receive control register - addressOffset: 0x0108 - resetValue: 0x00000000 - fields: - RPF: - description: DMA Rx Channel Packet Flush - bitOffset: 31 - bitWidth: 1 - RXPBL: - description: Receive Programmable Burst Length - bitOffset: 16 - bitWidth: 6 - RBSZ: - description: Receive Buffer size - bitOffset: 1 - bitWidth: 14 - SR: - description: Start or Stop Receive - bitOffset: 0 - bitWidth: 1 - DMACTxDLAR: - description: Channel Tx descriptor list address register - addressOffset: 0x0114 - resetValue: 0x00000000 - fields: - TDESLA: - description: Start of Transmit List - bitOffset: 2 - bitWidth: 30 - DMACRxDLAR: - description: Channel Rx descriptor list address register - addressOffset: 0x011C - resetValue: 0x00000000 - fields: - RDESLA: - description: Start of Receive List - bitOffset: 2 - bitWidth: 30 - DMACTxDTPR: - description: Channel Tx descriptor tail pointer register - addressOffset: 0x0120 - resetValue: 0x00000000 - fields: - TDT: - description: Transmit Descriptor Tail Pointer - bitOffset: 2 - bitWidth: 30 - DMACRxDTPR: - description: Channel Rx descriptor tail pointer register - addressOffset: 0x0128 - resetValue: 0x00000000 - fields: - RDT: - description: Receive Descriptor Tail Pointer - bitOffset: 2 - bitWidth: 30 - DMACTxRLR: - description: Channel Tx descriptor ring length register - addressOffset: 0x012C - resetValue: 0x00000000 - fields: - TDRL: - description: Transmit Descriptor Ring Length - bitOffset: 0 - bitWidth: 10 - DMACRxRLR: - description: Channel Rx descriptor ring length register - addressOffset: 0x0130 - resetValue: 0x00000000 - fields: - RDRL: - description: Receive Descriptor Ring Length - bitOffset: 0 - bitWidth: 10 - DMACIER: - description: Channel interrupt enable register - addressOffset: 0x0134 - resetValue: 0x00000000 - fields: - NIE: - description: Normal Interrupt Summary Enable - bitOffset: 15 - bitWidth: 1 - AIE: - description: Abnormal Interrupt Summary Enable - bitOffset: 14 - bitWidth: 1 - CDEE: - description: Context Descriptor Error Enable - bitOffset: 13 - bitWidth: 1 - FBEE: - description: Fatal Bus Error Enable - bitOffset: 12 - bitWidth: 1 - ERIE: - description: Early Receive Interrupt Enable - bitOffset: 11 - bitWidth: 1 - ETIE: - description: Early Transmit Interrupt Enable - bitOffset: 10 - bitWidth: 1 - RWTE: - description: Receive Watchdog Timeout Enable - bitOffset: 9 - bitWidth: 1 - RSE: - description: Receive Stopped Enable - bitOffset: 8 - bitWidth: 1 - RBUE: - description: Receive Buffer Unavailable Enable - bitOffset: 7 - bitWidth: 1 - RIE: - description: Receive Interrupt Enable - bitOffset: 6 - bitWidth: 1 - TBUE: - description: Transmit Buffer Unavailable Enable - bitOffset: 2 - bitWidth: 1 - TXSE: - description: Transmit Stopped Enable - bitOffset: 1 - bitWidth: 1 - TIE: - description: Transmit Interrupt Enable - bitOffset: 0 - bitWidth: 1 - DMACRxIWTR: - description: Channel Rx interrupt watchdog timer register - addressOffset: 0x0138 - resetValue: 0x00000000 - fields: - RWT: - description: Receive Interrupt Watchdog Timer Count - bitOffset: 0 - bitWidth: 8 - DMACCATxDR: - description: Channel current application transmit descriptor register - addressOffset: 0x0144 - resetValue: 0x00000000 - fields: - CURTDESAPTR: - description: Application Transmit Descriptor Address Pointer - bitOffset: 0 - bitWidth: 32 - DMACCARxDR: - description: Channel current application receive descriptor register - addressOffset: 0x014C - resetValue: 0x00000000 - fields: - CURRDESAPTR: - description: Application Receive Descriptor Address Pointer - bitOffset: 0 - bitWidth: 32 - DMACCATxBR: - description: Channel current application transmit buffer register - addressOffset: 0x0154 - resetValue: 0x00000000 - fields: - CURTBUFAPTR: - description: Application Transmit Buffer Address Pointer - bitOffset: 0 - bitWidth: 32 - DMACCARxBR: - description: Channel current application receive buffer register - addressOffset: 0x015C - resetValue: 0x00000000 - fields: - CURRBUFAPTR: - description: Application Receive Buffer Address Pointer - bitOffset: 0 - bitWidth: 32 - DMACSR: - description: Channel status register - addressOffset: 0x0160 - resetValue: 0x00000000 - fields: - REB: - description: Rx DMA Error Bits - bitOffset: 19 - bitWidth: 3 - TEB: - description: Tx DMA Error Bits - bitOffset: 16 - bitWidth: 3 - NIS: - description: Normal Interrupt Summary - bitOffset: 15 - bitWidth: 1 - AIS: - description: Abnormal Interrupt Summary - bitOffset: 14 - bitWidth: 1 - CDE: - description: Context Descriptor Error - bitOffset: 13 - bitWidth: 1 - FBE: - description: Fatal Bus Error - bitOffset: 12 - bitWidth: 1 - ERI: - description: Early Receive Interrupt - bitOffset: 11 - bitWidth: 1 - ETI: - description: Early Transmit Interrupt - bitOffset: 10 - bitWidth: 1 - RWT: - description: Receive Watchdog Timeout - bitOffset: 9 - bitWidth: 1 - RPS: - description: Receive Process Stopped - bitOffset: 8 - bitWidth: 1 - RBU: - description: Receive Buffer Unavailable - bitOffset: 7 - bitWidth: 1 - RI: - description: Receive Interrupt - bitOffset: 6 - bitWidth: 1 - TBU: - description: Transmit Buffer Unavailable - bitOffset: 2 - bitWidth: 1 - TPS: - description: Transmit Process Stopped - bitOffset: 1 - bitWidth: 1 - TI: - description: Transmit Interrupt - bitOffset: 0 - bitWidth: 1 - DMACMFCR: - description: Channel missed frame count register - addressOffset: 0x016C - resetValue: 0x00000000 - fields: - MFCO: - description: Overflow status of the MFC Counter - bitOffset: 15 - bitWidth: 1 - MFC: - description: Dropped Packet Counters - bitOffset: 0 - bitWidth: 11 diff --git a/devices/common_patches/h7_exti_dualcore.yaml b/devices/common_patches/h7_exti_dualcore.yaml deleted file mode 100644 index fc591b587..000000000 --- a/devices/common_patches/h7_exti_dualcore.yaml +++ /dev/null @@ -1,853 +0,0 @@ -# H7 EXTI module, for dual core parts - -EXTI: - _modify: - C1PR2,C1IMR3,C1EMR3,C1PR3: - access: read-write - - _add: - C2IMR1: - description: CPU2 EXTI interrupt mask register - addressOffset: 0x00C0 - resetValue: 0xFFC00000 - fields: - MR0: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 0 - bitWidth: 1 - MR1: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 1 - bitWidth: 1 - MR2: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 2 - bitWidth: 1 - MR3: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 3 - bitWidth: 1 - MR4: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 4 - bitWidth: 1 - MR5: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 5 - bitWidth: 1 - MR6: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 6 - bitWidth: 1 - MR7: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 7 - bitWidth: 1 - MR8: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 8 - bitWidth: 1 - MR9: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 9 - bitWidth: 1 - MR10: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 10 - bitWidth: 1 - MR11: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 11 - bitWidth: 1 - MR12: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 12 - bitWidth: 1 - MR13: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 13 - bitWidth: 1 - MR14: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 14 - bitWidth: 1 - MR15: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 15 - bitWidth: 1 - MR16: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 16 - bitWidth: 1 - MR17: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 17 - bitWidth: 1 - MR18: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 18 - bitWidth: 1 - MR19: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 19 - bitWidth: 1 - MR20: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 20 - bitWidth: 1 - MR21: - description: CPU2 interrupt mask on Configurable Event input - bitOffset: 21 - bitWidth: 1 - MR22: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 22 - bitWidth: 1 - MR23: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 23 - bitWidth: 1 - MR24: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 24 - bitWidth: 1 - MR25: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 25 - bitWidth: 1 - MR26: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 26 - bitWidth: 1 - MR27: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 27 - bitWidth: 1 - MR28: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 28 - bitWidth: 1 - MR29: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 29 - bitWidth: 1 - MR30: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 30 - bitWidth: 1 - MR31: - description: CPU2 interrupt mask on Direct Event input - bitOffset: 31 - bitWidth: 1 - C2EMR1: - description: CPU2 EXTI event mask register - addressOffset: 0x00C4 - resetValue: 0x00000000 - fields: - MR0: - description: CPU2 event mask on Event input x - bitOffset: 0 - bitWidth: 1 - MR1: - description: CPU2 event mask on Event input x - bitOffset: 1 - bitWidth: 1 - MR2: - description: CPU2 event mask on Event input x - bitOffset: 2 - bitWidth: 1 - MR3: - description: CPU2 event mask on Event input x - bitOffset: 3 - bitWidth: 1 - MR4: - description: CPU2 event mask on Event input x - bitOffset: 4 - bitWidth: 1 - MR5: - description: CPU2 event mask on Event input x - bitOffset: 5 - bitWidth: 1 - MR6: - description: CPU2 event mask on Event input x - bitOffset: 6 - bitWidth: 1 - MR7: - description: CPU2 event mask on Event input x - bitOffset: 7 - bitWidth: 1 - MR8: - description: CPU2 event mask on Event input x - bitOffset: 8 - bitWidth: 1 - MR9: - description: CPU2 event mask on Event input x - bitOffset: 9 - bitWidth: 1 - MR10: - description: CPU2 event mask on Event input x - bitOffset: 10 - bitWidth: 1 - MR11: - description: CPU2 event mask on Event input x - bitOffset: 11 - bitWidth: 1 - MR12: - description: CPU2 event mask on Event input x - bitOffset: 12 - bitWidth: 1 - MR13: - description: CPU2 event mask on Event input x - bitOffset: 13 - bitWidth: 1 - MR14: - description: CPU2 event mask on Event input x - bitOffset: 14 - bitWidth: 1 - MR15: - description: CPU2 event mask on Event input x - bitOffset: 15 - bitWidth: 1 - MR16: - description: CPU2 event mask on Event input x - bitOffset: 16 - bitWidth: 1 - MR17: - description: CPU2 event mask on Event input x - bitOffset: 17 - bitWidth: 1 - MR18: - description: CPU2 event mask on Event input x - bitOffset: 18 - bitWidth: 1 - MR19: - description: CPU2 event mask on Event input x - bitOffset: 19 - bitWidth: 1 - MR20: - description: CPU2 event mask on Event input x - bitOffset: 20 - bitWidth: 1 - MR21: - description: CPU2 event mask on Event input x - bitOffset: 21 - bitWidth: 1 - MR22: - description: CPU2 event mask on Event input x - bitOffset: 22 - bitWidth: 1 - MR23: - description: CPU2 event mask on Event input x - bitOffset: 23 - bitWidth: 1 - MR24: - description: CPU2 event mask on Event input x - bitOffset: 24 - bitWidth: 1 - MR25: - description: CPU2 event mask on Event input x - bitOffset: 25 - bitWidth: 1 - MR26: - description: CPU2 event mask on Event input x - bitOffset: 26 - bitWidth: 1 - MR27: - description: CPU2 event mask on Event input x - bitOffset: 27 - bitWidth: 1 - MR28: - description: CPU2 event mask on Event input x - bitOffset: 28 - bitWidth: 1 - MR29: - description: CPU2 event mask on Event input x - bitOffset: 29 - bitWidth: 1 - MR30: - description: CPU2 event mask on Event input x - bitOffset: 30 - bitWidth: 1 - MR31: - description: CPU2 event mask on Event input x - bitOffset: 31 - bitWidth: 1 - C2PR1: - description: CPU2 EXTI pending register - addressOffset: 0x00C8 - resetValue: 0x00000000 - fields: - PR0: - description: Configurable event input pending - bitOffset: 0 - bitWidth: 1 - PR1: - description: Configurable event input pending - bitOffset: 1 - bitWidth: 1 - PR2: - description: Configurable event input pending - bitOffset: 2 - bitWidth: 1 - PR3: - description: Configurable event input pending - bitOffset: 3 - bitWidth: 1 - PR4: - description: Configurable event input pending - bitOffset: 4 - bitWidth: 1 - PR5: - description: Configurable event input pending - bitOffset: 5 - bitWidth: 1 - PR6: - description: Configurable event input pending - bitOffset: 6 - bitWidth: 1 - PR7: - description: Configurable event input pending - bitOffset: 7 - bitWidth: 1 - PR8: - description: Configurable event input pending - bitOffset: 8 - bitWidth: 1 - PR9: - description: Configurable event input pending - bitOffset: 9 - bitWidth: 1 - PR10: - description: Configurable event input pending - bitOffset: 10 - bitWidth: 1 - PR11: - description: Configurable event input pending - bitOffset: 11 - bitWidth: 1 - PR12: - description: Configurable event input pending - bitOffset: 12 - bitWidth: 1 - PR13: - description: Configurable event input pending - bitOffset: 13 - bitWidth: 1 - PR14: - description: Configurable event input pending - bitOffset: 14 - bitWidth: 1 - PR15: - description: Configurable event input pending - bitOffset: 15 - bitWidth: 1 - PR16: - description: Configurable event input pending - bitOffset: 16 - bitWidth: 1 - PR17: - description: Configurable event input pending - bitOffset: 17 - bitWidth: 1 - PR18: - description: Configurable event input pending - bitOffset: 18 - bitWidth: 1 - PR19: - description: Configurable event input pending - bitOffset: 19 - bitWidth: 1 - PR20: - description: Configurable event input pending - bitOffset: 20 - bitWidth: 1 - PR21: - description: Configurable event input pending - bitOffset: 21 - bitWidth: 1 - C2IMR2: - description: CPU2 EXTI interrupt mask register - addressOffset: 0x00D0 - resetValue: 0xFFF5FFFF - fields: - MR32: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 0 - bitWidth: 1 - MR33: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 1 - bitWidth: 1 - MR34: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 2 - bitWidth: 1 - MR35: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 3 - bitWidth: 1 - MR36: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 4 - bitWidth: 1 - MR37: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 5 - bitWidth: 1 - MR38: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 6 - bitWidth: 1 - MR39: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 7 - bitWidth: 1 - MR40: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 8 - bitWidth: 1 - MR41: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 9 - bitWidth: 1 - MR42: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 10 - bitWidth: 1 - MR43: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 11 - bitWidth: 1 - MR44: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 12 - bitWidth: 1 - MR46: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 14 - bitWidth: 1 - MR47: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 15 - bitWidth: 1 - MR48: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 16 - bitWidth: 1 - MR49: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 17 - bitWidth: 1 - MR50: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 18 - bitWidth: 1 - MR51: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 19 - bitWidth: 1 - MR52: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 20 - bitWidth: 1 - MR53: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 21 - bitWidth: 1 - MR54: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 22 - bitWidth: 1 - MR55: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 23 - bitWidth: 1 - MR56: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 24 - bitWidth: 1 - MR57: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 25 - bitWidth: 1 - MR58: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 26 - bitWidth: 1 - MR59: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 27 - bitWidth: 1 - MR60: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 28 - bitWidth: 1 - MR61: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 29 - bitWidth: 1 - MR62: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 30 - bitWidth: 1 - MR63: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 31 - bitWidth: 1 - C2EMR2: - description: CPU2 EXTI event mask register - addressOffset: 0x00D4 - resetValue: 0x00000000 - fields: - MR32: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 0 - bitWidth: 1 - MR33: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 1 - bitWidth: 1 - MR34: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 2 - bitWidth: 1 - MR35: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 3 - bitWidth: 1 - MR36: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 4 - bitWidth: 1 - MR37: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 5 - bitWidth: 1 - MR38: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 6 - bitWidth: 1 - MR39: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 7 - bitWidth: 1 - MR40: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 8 - bitWidth: 1 - MR41: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 9 - bitWidth: 1 - MR42: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 10 - bitWidth: 1 - MR43: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 11 - bitWidth: 1 - MR44: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 12 - bitWidth: 1 - MR46: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 14 - bitWidth: 1 - MR47: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 15 - bitWidth: 1 - MR48: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 16 - bitWidth: 1 - MR49: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 17 - bitWidth: 1 - MR50: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 18 - bitWidth: 1 - MR51: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 19 - bitWidth: 1 - MR52: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 20 - bitWidth: 1 - MR53: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 21 - bitWidth: 1 - MR54: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 22 - bitWidth: 1 - MR55: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 23 - bitWidth: 1 - MR56: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 24 - bitWidth: 1 - MR57: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 25 - bitWidth: 1 - MR58: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 26 - bitWidth: 1 - MR59: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 27 - bitWidth: 1 - MR60: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 28 - bitWidth: 1 - MR61: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 29 - bitWidth: 1 - MR62: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 30 - bitWidth: 1 - MR63: - description: CPU2 interrupt Mask on Direct Event input x+32 - bitOffset: 31 - bitWidth: 1 - C2PR2: - description: CPU2 EXTI pending register - addressOffset: 0x00D8 - resetValue: 0x00000000 - fields: - PR49: - description: CPU2 configurable event inputs x+32 Pending bit - bitOffset: 17 - bitWidth: 1 - PR51: - description: CPU2 configurable event inputs x+32 Pending bit - bitOffset: 19 - bitWidth: 1 - C2IMR3: - description: CPU2 EXTI interrupt mask register - addressOffset: 0x00E0 - resetValue: 0x018BFFFF - fields: - MR64: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 0 - bitWidth: 1 - MR65: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 1 - bitWidth: 1 - MR66: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 2 - bitWidth: 1 - MR67: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 3 - bitWidth: 1 - MR68: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 4 - bitWidth: 1 - MR69: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 5 - bitWidth: 1 - MR70: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 6 - bitWidth: 1 - MR71: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 7 - bitWidth: 1 - MR72: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 8 - bitWidth: 1 - MR73: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 9 - bitWidth: 1 - MR74: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 10 - bitWidth: 1 - MR75: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 11 - bitWidth: 1 - MR76: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 12 - bitWidth: 1 - MR77: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 13 - bitWidth: 1 - MR78: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 14 - bitWidth: 1 - MR79: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 15 - bitWidth: 1 - MR80: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 16 - bitWidth: 1 - MR82: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 18 - bitWidth: 1 - MR84: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 20 - bitWidth: 1 - MR85: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 21 - bitWidth: 1 - MR86: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 22 - bitWidth: 1 - MR87: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 23 - bitWidth: 1 - MR88: - description: CPU2 interrupt Mask on Direct Event input x+64 - bitOffset: 24 - bitWidth: 1 - C2EMR3: - description: CPU2 EXTI event mask register - addressOffset: 0x00E4 - resetValue: 0x00000000 - fields: - MR64: - description: CPU2 event mask on Event input x+64 - bitOffset: 0 - bitWidth: 1 - MR65: - description: CPU2 event mask on Event input x+64 - bitOffset: 1 - bitWidth: 1 - MR66: - description: CPU2 event mask on Event input x+64 - bitOffset: 2 - bitWidth: 1 - MR67: - description: CPU2 event mask on Event input x+64 - bitOffset: 3 - bitWidth: 1 - MR68: - description: CPU2 event mask on Event input x+64 - bitOffset: 4 - bitWidth: 1 - MR69: - description: CPU2 event mask on Event input x+64 - bitOffset: 5 - bitWidth: 1 - MR70: - description: CPU2 event mask on Event input x+64 - bitOffset: 6 - bitWidth: 1 - MR71: - description: CPU2 event mask on Event input x+64 - bitOffset: 7 - bitWidth: 1 - MR72: - description: CPU2 event mask on Event input x+64 - bitOffset: 8 - bitWidth: 1 - MR73: - description: CPU2 event mask on Event input x+64 - bitOffset: 9 - bitWidth: 1 - MR74: - description: CPU2 event mask on Event input x+64 - bitOffset: 10 - bitWidth: 1 - MR75: - description: CPU2 event mask on Event input x+64 - bitOffset: 11 - bitWidth: 1 - MR76: - description: CPU2 event mask on Event input x+64 - bitOffset: 12 - bitWidth: 1 - MR77: - description: CPU2 event mask on Event input x+64 - bitOffset: 13 - bitWidth: 1 - MR78: - description: CPU2 event mask on Event input x+64 - bitOffset: 14 - bitWidth: 1 - MR79: - description: CPU2 event mask on Event input x+64 - bitOffset: 15 - bitWidth: 1 - MR80: - description: CPU2 event mask on Event input x+64 - bitOffset: 16 - bitWidth: 1 - MR82: - description: CPU2 event mask on Event input x+64 - bitOffset: 18 - bitWidth: 1 - MR84: - description: CPU2 event mask on Event input x+64 - bitOffset: 20 - bitWidth: 1 - MR85: - description: CPU2 event mask on Event input x+64 - bitOffset: 21 - bitWidth: 1 - MR86: - description: CPU2 event mask on Event input x+64 - bitOffset: 22 - bitWidth: 1 - MR87: - description: CPU2 event mask on Event input x+64 - bitOffset: 23 - bitWidth: 1 - MR88: - description: CPU2 event mask on Event input x+64 - bitOffset: 24 - bitWidth: 1 - C2PR3: - description: CPU2 EXTI pending register - addressOffset: 0x00E8 - resetValue: 0x00000000 - fields: - PR82: - description: CPU2 configurable event inputs x+64 Pending bit - bitOffset: 18 - bitWidth: 1 - PR84: - description: CPU2 configurable event inputs x+64 Pending bit - bitOffset: 20 - bitWidth: 1 - PR85: - description: CPU2 configurable event inputs x+64 Pending bit - bitOffset: 21 - bitWidth: 1 - PR86: - description: CPU2 configurable event inputs x+64 Pending bit - bitOffset: 22 - bitWidth: 1 diff --git a/devices/common_patches/h7_exti_singlecore.yaml b/devices/common_patches/h7_exti_singlecore.yaml deleted file mode 100644 index 0b369d6cc..000000000 --- a/devices/common_patches/h7_exti_singlecore.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# H7 EXTI module, for single core parts - -EXTI: - _modify: - CPUPR2,CPUIMR3,CPUEMR3,CPUPR3: - access: read-write diff --git a/devices/common_patches/h7_hsicfgr_csicfgr_rev_v.yaml b/devices/common_patches/h7_hsicfgr_csicfgr_rev_v.yaml deleted file mode 100644 index 4b073545b..000000000 --- a/devices/common_patches/h7_hsicfgr_csicfgr_rev_v.yaml +++ /dev/null @@ -1,30 +0,0 @@ -RCC: - _delete: - ICSCR - _add: - HSICFGR: - description: RCC HSI configuration register - addressOffset: 0x0004 - access: read-write - fields: - HSITRIM: - description: HSI clock trimming - bitOffset: 24 - bitWidth: 7 - HSICAL: - description: HSI clock calibration - bitOffset: 0 - bitWidth: 12 - CSICFGR: - description: RCC CSI configuration register - addressOffset: 0x000C - access: read-write - fields: - CSITRIM: - description: CSI clock trimming - bitOffset: 24 - bitWidth: 6 - CSICAL: - description: CSI clock calibration - bitOffset: 0 - bitWidth: 9 diff --git a/devices/common_patches/h7_otg.yaml b/devices/common_patches/h7_otg.yaml deleted file mode 100644 index cd764d72a..000000000 --- a/devices/common_patches/h7_otg.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# A handful of registers have alternateRegister entries -# with extra whitespace, which is not allowed by the SVD spec. - -OTG1_HS_GLOBAL: - _modify: - DIEPTXF0_Device: - alternateRegister: HNPTXFSIZ_Host - GRXSTSR_Device: - alternateRegister: GRXSTSR_Host - GRXSTSP_Device: - alternateRegister: GRXSTSP_Host diff --git a/devices/common_patches/h7_rcc_src_sel.yaml b/devices/common_patches/h7_rcc_src_sel.yaml deleted file mode 100644 index 6a364d612..000000000 --- a/devices/common_patches/h7_rcc_src_sel.yaml +++ /dev/null @@ -1,67 +0,0 @@ -# Rename *SRC to *SEL in H7 domain kernel clock configuration registers (DxCCIPR) - -# Applies only to RM0433 and RM0399 parts - -RCC: - D1CCIPR: - _modify: - CKPERSRC: - name: CKPERSEL - SDMMCSRC: - name: SDMMCSEL - QSPISRC: - name: QSPISEL - FMCSRC: - name: FMCSEL - D2CCIP1R: - _modify: - SWPSRC: - name: SWPSEL - FDCANSRC: - name: FDCANSEL - DFSDM1SRC: - name: DFSDM1SEL - SPDIFSRC: - name: SPDIFSEL - SPI45SRC: - name: SPI45SEL - SPI123SRC: - name: SPI123SEL - SAI23SRC: - name: SAI23SEL - SAI1SRC: - name: SAI1SEL - D2CCIP2R: - _modify: - LPTIM1SRC: - name: LPTIM1SEL - CECSRC: - name: CECSEL - USBSRC: - name: USBSEL - I2C123SRC: - name: I2C123SEL - RNGSRC: - name: RNGSEL - USART16SRC: - name: USART16SEL - USART234578SRC: - name: USART234578SEL - D3CCIPR: - _modify: - SPI6SRC: - name: SPI6SEL - SAI4BSRC: - name: SAI4BSEL - SAI4ASRC: - name: SAI4ASEL - ADCSRC: - name: ADCSEL - LPTIM345SRC: - name: LPTIM345SEL - LPTIM2SRC: - name: LPTIM2SEL - I2C4SRC: - name: I2C4SEL - LPUART1SRC: - name: LPUART1SEL diff --git a/devices/common_patches/h7_sai.yaml b/devices/common_patches/h7_sai.yaml deleted file mode 100644 index 1af651592..000000000 --- a/devices/common_patches/h7_sai.yaml +++ /dev/null @@ -1,31 +0,0 @@ -"SAI*": - ACR1: - _modify: - MCKDIV: - bitWidth: 6 - NOMCK: - name: NODIV - _add: - MCKEN: - description: Master clock generation enable - bitOffset: 27 - bitWidth: 1 - AFRCR: - _modify: - FSDEF: - access: read-write - BCR1: - _modify: - MCKDIV: - bitWidth: 6 - NOMCK: - name: NODIV - _add: - MCKEN: - description: Master clock generation enable - bitOffset: 27 - bitWidth: 1 - BFRCR: - _modify: - FSDEF: - access: read-write diff --git a/devices/common_patches/hash/hash.yaml b/devices/common_patches/hash/hash.yaml deleted file mode 100644 index 57149583c..000000000 --- a/devices/common_patches/hash/hash.yaml +++ /dev/null @@ -1,14 +0,0 @@ -HASH: - _array: - "HR?": - _modify: - H0: - name: H - "CSR*": - _modify: - CSR0: - name: CSR - "HASH_HR?": - _modify: - H0: - name: H diff --git a/devices/common_patches/hash/hash_v1.yaml b/devices/common_patches/hash/hash_v1.yaml deleted file mode 100644 index 082aa2dc0..000000000 --- a/devices/common_patches/hash/hash_v1.yaml +++ /dev/null @@ -1,10 +0,0 @@ -HASH: - _array: - "HR?": - _modify: - H0: - name: H - "CSR*": - _modify: - CSR0: - name: CSR diff --git a/devices/common_patches/l0_firewall.yaml b/devices/common_patches/l0_firewall.yaml deleted file mode 100644 index de8c7a55f..000000000 --- a/devices/common_patches/l0_firewall.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# Renames the stm32l0xx firewall to "FW" and removes register prefixes - -_modify: - Firewall: - name: FW - -FW: - _strip: - - FIREWALL_ diff --git a/devices/common_patches/l0_flash.yaml b/devices/common_patches/l0_flash.yaml deleted file mode 100644 index 0eca7fa9d..000000000 --- a/devices/common_patches/l0_flash.yaml +++ /dev/null @@ -1,32 +0,0 @@ -"FLASH": - # Fix Write Protection for L0 Flash - _delete: - - WRPR - _add: - WRPROT1: - description: Write Protection Register 1 - addressOffset: 0x20 - size: 32 - access: read-only - resetValue: 0x00000000 - fields: - WRPROT1: - description: Write Protection - bitOffset: 0 - bitWidth: 32 - WRPROT2: - description: Write Protection Register 2 - addressOffset: 0x80 - size: 32 - access: read-only - resetValue: 0x00000000 - fields: - WRPROT2: - description: Write Protection - bitOffset: 0 - bitWidth: 16 - # Fix write permissions of EOP field - SR: - _modify: - EOP: - access: read-write diff --git a/devices/common_patches/l0_pwr_mode.yaml b/devices/common_patches/l0_pwr_mode.yaml deleted file mode 100644 index 1b32088dc..000000000 --- a/devices/common_patches/l0_pwr_mode.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# Fix low power mode bits for L0 - -PWR: - CR: - _modify: - LPDS: - description: Regulator in Low-power deepsleep mode - bitWidth: 1 - bitOffset: 16 - _add: - LPSDSR: - description: Low-power deepsleep/Sleep/Low-power run - bitWidth: 1 - bitOffset: 0 \ No newline at end of file diff --git a/devices/common_patches/l0_pwr_wakeup.yaml b/devices/common_patches/l0_pwr_wakeup.yaml deleted file mode 100644 index 5088b01d0..000000000 --- a/devices/common_patches/l0_pwr_wakeup.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# Fix wakeup bits in PWR_CSR, and rename one more flag -PWR: - CSR: - _modify: - EWUP: - name: EWUP1 - description: Enable WKUP pin 1 - BRE: - name: EWUP2 - description: Enable WKUP pin 2 - BRR: - name: VREFINTRDYF - description: Internal voltage reference ready flag - _add: - EWUP3: - description: Enable WKUP pin 3 - bitOffset: 10 - bitWidth: 1 diff --git a/devices/common_patches/l0_rtc.yaml b/devices/common_patches/l0_rtc.yaml deleted file mode 100644 index 2d6bdc48c..000000000 --- a/devices/common_patches/l0_rtc.yaml +++ /dev/null @@ -1,38 +0,0 @@ -# Fix RTC bits for L0 - -RTC: - ISR: - _add: - RECALPF: - description: Recalibration pending flag - bitWidth: 1 - bitOffset: 16 - TAMP3F: - description: RTC_TAMP3 detection flag - bitWidth: 1 - bitOffset: 15 - TAMPCR: - _modify: - TAMP2_TRG: - name: TAMP2TRG - _add: - TAMP3MF: - description: Tamper 3 mask flag - bitWidth: 1 - bitOffset: 24 - TAMP3NOERASE: - description: Tamper 3 no erase - bitWidth: 1 - bitOffset: 23 - TAMP3IE: - description: Tamper 3 interrupt enable - bitWidth: 1 - bitOffset: 22 - TAMP3TRG: - description: Active level for RTC_TAMP3 input - bitWidth: 1 - bitOffset: 6 - TAMP3E: - description: RTC_TAMP3 detection enable - bitWidth: 1 - bitOffset: 5 diff --git a/devices/common_patches/l0_syscfg_cfgr.yaml b/devices/common_patches/l0_syscfg_cfgr.yaml deleted file mode 100644 index 9898d2f50..000000000 --- a/devices/common_patches/l0_syscfg_cfgr.yaml +++ /dev/null @@ -1,56 +0,0 @@ -# Add SYSCFG registers -SYSCFG: - _modify: - COMP1_CTRL: - name: COMP1_CSR - COMP2_CTRL: - name: COMP2_CSR - CFGR1: - _add: - UFB: - description: "User bank swapping" - bitOffset: 3 - bitWidth: 1 - CFGR2: - _add: - I2C3_FMP: - description: I2C3 Fm+ drive capability enable bit - bitOffset: 14 - bitWidth: 1 - FWDIS: - description: Firewall disable bit - bitOffset: 0 - bitWidth: 1 - _delete: - - CAPA - - FWDISEN - CFGR3: - _delete: - - REF_LOCK - - VREFINT_COMP_RDYF - - VREFINT_ADC_RDYF - - SENSOR_ADC_RDYF - - REF_RC48MHz_RDYF - - ENREF_RC48MHz - - ENBUF_VREFINT_COMP - - ENBUF_BGAP_ADC - - EN_BGAP - _add: - # REF_LOCK is wrongly marked as write-only, but it's "rs" - read/set - REF_LOCK: - description: SYSCFG_CFGR3 lock bit - bitOffset: 31 - bitWidth: 1 - access: read-write - ENBUF_VREFINT_COMP2: - description: VREFINT reference for COMP2 scaler enable bit - bitOffset: 12 - bitWidth: 1 - ENBUF_VREFINT_ADC: - description: VREFINT reference for ADC enable bit - bitOffset: 8 - bitWidth: 1 - EN_VREFINT: - description: VREFINT enable and scaler control for COMP2 enable bit - bitOffset: 0 - bitWidth: 1 diff --git a/devices/common_patches/l0_tim.yaml b/devices/common_patches/l0_tim.yaml deleted file mode 100644 index 14bdcf894..000000000 --- a/devices/common_patches/l0_tim.yaml +++ /dev/null @@ -1,70 +0,0 @@ -# Fix Timers for L0 Flash -"TIM[23]": - _delete: - - CNT - - ARR - - CCR1 - - CCR2 - - CCR3 - - CCR4 - _add: - CNT: - description: TIMx counter - addressOffset: 0x24 - size: 16 - resetValue: 0x0000 - fields: - CNT: - description: Low counter value - bitOffset: 0 - bitWidth: 16 - ARR: - description: TIMx auto-reload register - addressOffset: 0x2C - size: 16 - resetValue: 0xFFFF - fields: - ARR: - description: Low Auto-reload value - bitOffset: 0 - bitWidth: 16 - CCR1: - description: TIMx capture/compare register 1 - addressOffset: 0x34 - size: 16 - resetValue: 0x0000 - fields: - CCR1: - description: Low Capture/Compare 1 value - bitOffset: 0 - bitWidth: 16 - CCR2: - description: TIMx capture/compare register 2 - addressOffset: 0x38 - size: 16 - resetValue: 0x00000000 - fields: - CCR2: - description: Low Capture/Compare 2 value - bitOffset: 0 - bitWidth: 16 - CCR3: - description: TIMx capture/compare register 3 - addressOffset: 0x3C - size: 16 - resetValue: 0x00000000 - fields: - CCR3: - description: Low Capture/Compare 3 value - bitOffset: 0 - bitWidth: 16 - CCR4: - description: TIMx capture/compare register 4 - addressOffset: 0x40 - size: 16 - resetValue: 0x00000000 - fields: - CCR4: - description: Low Capture/Compare 4 value - bitOffset: 0 - bitWidth: 16 \ No newline at end of file diff --git a/devices/common_patches/l4_crrcr.yaml b/devices/common_patches/l4_crrcr.yaml deleted file mode 100644 index d7bae9595..000000000 --- a/devices/common_patches/l4_crrcr.yaml +++ /dev/null @@ -1,21 +0,0 @@ -RCC: - _add: - CRRCR: - description: Clock recovery RC register - addressOffset: 0x98 - fields: - HSI48CAL: - description: These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. - access: read-only - bitOffset: 7 - bitWidth: 9 - HSI48RDY: - description: Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. - access: read-only - bitOffset: 1 - bitWidth: 1 - HSI48ON: - description: Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. - access: read-write - bitOffset: 0 - bitWidth: 1 diff --git a/devices/common_patches/ltdc/ltdc.yaml b/devices/common_patches/ltdc/ltdc.yaml deleted file mode 100644 index 68dc2e6bc..000000000 --- a/devices/common_patches/ltdc/ltdc.yaml +++ /dev/null @@ -1,32 +0,0 @@ -LTDC: - AWCR: - _modify: - AAV: - name: AAW - description: Accumulated Active Width (in units of pixel clock period) - _cluster: - "LAYER%s": - "L?CR": - name: CR - "L?WHPCR": - name: WHPCR - "L?WVPCR": - name: WVPCR - "L?CKCR": - name: CKCR - "L?PFCR": - name: PFCR - "L?CACR": - name: CACR - "L?DCCR": - name: DCCR - "L?BFCR": - name: BFCR - "L?CFBAR": - name: CFBAR - "L?CFBLR": - name: CFBLR - "L?CFBLNR": - name: CFBLNR - "L?CLUTWR": - name: CLUTWR diff --git a/devices/common_patches/mdios/mdios.yaml b/devices/common_patches/mdios/mdios.yaml deleted file mode 100644 index bec9b78fd..000000000 --- a/devices/common_patches/mdios/mdios.yaml +++ /dev/null @@ -1,13 +0,0 @@ -MDIOS: - _strip: - - MDIOS_ - _array: - DINR*: - _modify: - DIN0: - name: DIN - DOUTR*: - _modify: - DOUT0: - name: DOUT - diff --git a/devices/common_patches/merge_I2C_CR2_SADDx_fields.yaml b/devices/common_patches/merge_I2C_CR2_SADDx_fields.yaml deleted file mode 100644 index 6442ea7ca..000000000 --- a/devices/common_patches/merge_I2C_CR2_SADDx_fields.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Merge together I2C CR2 wrongly separated SADDx fields - -"I2C*": - CR2: - _merge: - - "SADD*" diff --git a/devices/common_patches/merge_I2C_OAR1_ADDx_fields.yaml b/devices/common_patches/merge_I2C_OAR1_ADDx_fields.yaml deleted file mode 100644 index 1bc6852a3..000000000 --- a/devices/common_patches/merge_I2C_OAR1_ADDx_fields.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# Merge together I2C OAR1 wrongly separated ADDx fields -# -# Some devices have ADD_0 ADD_1_7 and ADD_8_9 so they need to be renamed before merging. -# Some devices have ADD0 ADD7 ADD10 (example F4 family) -# -# We can't use ADD* to merge the fields because the register has an ADDMODE -# field and I haven't find a way to merge ADD0, ADD7, ADD10 so I rename ADD10 -# to ADD9 as a workaround. -# - -"I2C*": - OAR1: - _modify: - ADD_0: - name: ADD0 - ADD_1_7: - name: ADD7 - ADD_8_9: - name: ADD9 - ADD10: # On purpose, see comment - name: ADD9 - _merge: - - "ADD[079]" diff --git a/devices/common_patches/merge_I2C_OAR1_OA1x_fields.yaml b/devices/common_patches/merge_I2C_OAR1_OA1x_fields.yaml deleted file mode 100644 index 1bc884dee..000000000 --- a/devices/common_patches/merge_I2C_OAR1_OA1x_fields.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Merge together I2C OAR1 wrongly separated 0A1x fields - -"I2C*": - OAR1: - _modify: - OA1_0: - name: OA10 - OA1_1: - name: OA11 - OA1_8: - name: OA18 - _merge: - - "OA1[018]" diff --git a/devices/common_patches/merge_LPUART_CR1_DEATx_fields.yaml b/devices/common_patches/merge_LPUART_CR1_DEATx_fields.yaml deleted file mode 100644 index 9b9977019..000000000 --- a/devices/common_patches/merge_LPUART_CR1_DEATx_fields.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Merge LPUART CR1 DEATx fields - -"LPUART*": - CR1: - _merge: - - "DEAT*" diff --git a/devices/common_patches/merge_LPUART_CR1_DEDTx_fields.yaml b/devices/common_patches/merge_LPUART_CR1_DEDTx_fields.yaml deleted file mode 100644 index 2d0356124..000000000 --- a/devices/common_patches/merge_LPUART_CR1_DEDTx_fields.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Merge LPUART CR1 DEDTx fields - -"LPUART*": - CR1: - _merge: - - "DEDT*" diff --git a/devices/common_patches/merge_LPUART_CR2_ADDx_fields.yaml b/devices/common_patches/merge_LPUART_CR2_ADDx_fields.yaml deleted file mode 100644 index 5a373acaf..000000000 --- a/devices/common_patches/merge_LPUART_CR2_ADDx_fields.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Merge LPUART CR2 ADDx fields - -"LPUART*": - CR2: - _modify: - "ADD0_3": - name: ADD0 - "ADD4_7": - name: ADD4 - _merge: - - "ADD[04]" diff --git a/devices/common_patches/merge_USART_BRR_fields.yaml b/devices/common_patches/merge_USART_BRR_fields.yaml deleted file mode 100644 index cf06121cc..000000000 --- a/devices/common_patches/merge_USART_BRR_fields.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# Merge BRR fields together -"USART*": - BRR: - _modify: - BRR_0_3: - name: BRR0 - BRR_4_15: - name: BRR1 - DIV_Mantissa: - name: BRR0 - DIV_Fraction: - name: BRR1 - _merge: - - "BRR*" diff --git a/devices/common_patches/merge_USART_CR1_DEATx_fields.yaml b/devices/common_patches/merge_USART_CR1_DEATx_fields.yaml deleted file mode 100644 index 49e2380a2..000000000 --- a/devices/common_patches/merge_USART_CR1_DEATx_fields.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Merge USART CR1 DEATx fields - -"USART*": - CR1: - _merge: - - "DEAT*" diff --git a/devices/common_patches/merge_USART_CR1_DEDTx_fields.yaml b/devices/common_patches/merge_USART_CR1_DEDTx_fields.yaml deleted file mode 100644 index bfff16d0c..000000000 --- a/devices/common_patches/merge_USART_CR1_DEDTx_fields.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Merge USART CR1 DEDTx fields - -"USART*": - CR1: - _merge: - - "DEDT*" diff --git a/devices/common_patches/merge_USART_CR2_ABRMODx_fields.yaml b/devices/common_patches/merge_USART_CR2_ABRMODx_fields.yaml deleted file mode 100644 index cc7232145..000000000 --- a/devices/common_patches/merge_USART_CR2_ABRMODx_fields.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Merge USART CR2 ABRMODx fields - -"USART*": - CR2: - _merge: - - "ABRMOD*" diff --git a/devices/common_patches/merge_USART_CR2_ADDx_fields.yaml b/devices/common_patches/merge_USART_CR2_ADDx_fields.yaml deleted file mode 100644 index cae73e873..000000000 --- a/devices/common_patches/merge_USART_CR2_ADDx_fields.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Merge USART CR2 ADDx fields - -"USART*": - CR2: - _modify: - "ADD0_3": - name: ADD0 - "ADD4_7": - name: ADD4 - _merge: - - "ADD[04]" diff --git a/devices/common_patches/pllsai.yaml b/devices/common_patches/pllsai.yaml deleted file mode 100644 index 99d5cda62..000000000 --- a/devices/common_patches/pllsai.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# Add missing PLLSAIRDY, PLLSAION bits to RCC_CR -RCC: - CR: - _add: - PLLSAIRDY: - description: PLLSAI clock ready flag - bitOffset: 29 - bitWidth: 1 - access: read-only - PLLSAION: - description: PLLSAI enable - bitOffset: 28 - bitWidth: 1 - access: read-write diff --git a/devices/common_patches/ramecc/ramecc.yaml b/devices/common_patches/ramecc/ramecc.yaml deleted file mode 100644 index cbf15f189..000000000 --- a/devices/common_patches/ramecc/ramecc.yaml +++ /dev/null @@ -1,83 +0,0 @@ -# RAMECC -# Strip all monitor registers of their fields, then add the correct fields - -"RAMECC,RAMECC?": - "M?CR": - _delete: - ?*: - _add: - ECCELEN: - description: ECC error context latching enable - bitOffset: 5 - bitWidth: 1 - access: read-write - ECCDEBWIE: - description: ECC double error on byte write interrupt enable - bitOffset: 4 - bitWidth: 1 - access: read-write - ECCDEIE: - description: ECC double error interrupt enable - bitOffset: 3 - bitWidth: 1 - access: read-write - ECCSEIE: - description: ECC single error interrupt enable - bitOffset: 2 - bitWidth: 1 - access: read-write - "M?SR": - _delete: - ?*: - _add: - DEBWDF: - description: ECC double error on byte write flag - bitOffset: 2 - bitWidth: 1 - access: read-write - DEDF: - description: ECC double error detected flag - bitOffset: 1 - bitWidth: 1 - access: read-write - SEDCF: - description: ECC single error detected flag - bitOffset: 0 - bitWidth: 1 - access: read-write - "M?FAR": - _delete: - ?*: - _add: - FADD: - description: ECC failing address - bitOffset: 0 - bitWidth: 32 - access: read-only - "M?FDRL": - _delete: - ?*: - _add: - FDATAL: - description: ECC failing data low - bitOffset: 0 - bitWidth: 32 - access: read-only - "M?FDRH": - _delete: - ?*: - _add: - FDATAH: - description: ECC failing data high - bitOffset: 0 - bitWidth: 32 - access: read-only - "M?FECR": - _delete: - ?*: - _add: - FEC: - description: ECC failing code - bitOffset: 0 - bitWidth: 32 - access: read-only diff --git a/devices/common_patches/ramecc/ramecc_new.yaml b/devices/common_patches/ramecc/ramecc_new.yaml deleted file mode 100644 index f39a8de3d..000000000 --- a/devices/common_patches/ramecc/ramecc_new.yaml +++ /dev/null @@ -1,286 +0,0 @@ -# RAMECC peripheral from scratch - -# ramecc.yaml adds monitor fields -_include: - - ramecc.yaml - -_add: - RAMECC1: - description: RAM ECC monitoring - groupName: RAMECC - baseAddress: 0x52009000 - interrupts: - RAMECC: - description: ECC diagnostic global interrupt for all RAMECC controllers - value: 145 - registers: - IER: - description: RAMECC interrupt enable register - addressOffset: 0x0 - access: read-write - resetValue: 0x00000000 - fields: - GECCDEBWIE: - description: Global ECC double error on byte write interrupt enable - bitOffset: 3 - bitWidth: 1 - access: read-write - GECCDEIE: - description: Global ECC double error interrupt enable - bitOffset: 2 - bitWidth: 1 - access: read-write - GECCSEIE: - description: Global ECC single error interrupt enable - bitOffset: 1 - bitWidth: 1 - access: read-write - GIE: - description: Global interrupt enable - bitOffset: 0 - bitWidth: 1 - access: read-write - M1CR: - description: RAMECC monitor 1 configuration register - addressOffset: 0x20 - access: read-write - resetValue: 0x00000000 - M1SR: - description: RAMECC monitor 1 status register - addressOffset: 0x24 - access: read-write - resetValue: 0x00000000 - M1FAR: - description: RAMECC monitor 1 failing address register - addressOffset: 0x28 - access: read-write - resetValue: 0x00000000 - M1FDRL: - description: RAMECC monitor 1 failing data low register - addressOffset: 0x2C - access: read-write - resetValue: 0x00000000 - M1FDRH: - description: RAMECC monitor 1 failing data high register - addressOffset: 0x30 - access: read-write - resetValue: 0x00000000 - M1FECR: - description: RAMECC monitor 1 failing error code register - addressOffset: 0x34 - access: read-write - resetValue: 0x00000000 - M2CR: - description: RAMECC monitor 2 configuration register - addressOffset: 0x40 - access: read-write - resetValue: 0x00000000 - M2SR: - description: RAMECC monitor 2 status register - addressOffset: 0x44 - access: read-write - resetValue: 0x00000000 - M2FAR: - description: RAMECC monitor 2 failing address register - addressOffset: 0x48 - access: read-write - resetValue: 0x00000000 - M2FDRL: - description: RAMECC monitor 2 failing data low register - addressOffset: 0x4C - access: read-write - resetValue: 0x00000000 - M2FDRH: - description: RAMECC monitor 2 failing data high register - addressOffset: 0x50 - access: read-write - resetValue: 0x00000000 - M2FECR: - description: RAMECC monitor 2 failing error code register - addressOffset: 0x54 - access: read-write - resetValue: 0x00000000 - M3CR: - description: RAMECC monitor 3 configuration register - addressOffset: 0x60 - access: read-write - resetValue: 0x00000000 - M3SR: - description: RAMECC monitor 3 status register - addressOffset: 0x64 - access: read-write - resetValue: 0x00000000 - M3FAR: - description: RAMECC monitor 3 failing address register - addressOffset: 0x68 - access: read-write - resetValue: 0x00000000 - M3FDRL: - description: RAMECC monitor 3 failing data low register - addressOffset: 0x6C - access: read-write - resetValue: 0x00000000 - M3FDRH: - description: RAMECC monitor 3 failing data high register - addressOffset: 0x70 - access: read-write - resetValue: 0x00000000 - M3FECR: - description: RAMECC monitor 3 failing error code register - addressOffset: 0x74 - access: read-write - resetValue: 0x00000000 - M4CR: - description: RAMECC monitor 4 configuration register - addressOffset: 0x80 - access: read-write - resetValue: 0x00000000 - M4SR: - description: RAMECC monitor 4 status register - addressOffset: 0x84 - access: read-write - resetValue: 0x00000000 - M4FAR: - description: RAMECC monitor 4 failing address register - addressOffset: 0x88 - access: read-write - resetValue: 0x00000000 - M4FDRL: - description: RAMECC monitor 4 failing data low register - addressOffset: 0x8C - access: read-write - resetValue: 0x00000000 - M4FDRH: - description: RAMECC monitor 4 failing data high register - addressOffset: 0x90 - access: read-write - resetValue: 0x00000000 - M4FECR: - description: RAMECC monitor 4 failing error code register - addressOffset: 0x94 - access: read-write - resetValue: 0x00000000 - M5CR: - description: RAMECC monitor 5 configuration register - addressOffset: 0xA0 - access: read-write - resetValue: 0x00000000 - M5SR: - description: RAMECC monitor 5 status register - addressOffset: 0xA4 - access: read-write - resetValue: 0x00000000 - M5FAR: - description: RAMECC monitor 5 failing address register - addressOffset: 0xA8 - access: read-write - resetValue: 0x00000000 - M5FDRL: - description: RAMECC monitor 5 failing data low register - addressOffset: 0xAC - access: read-write - resetValue: 0x00000000 - M5FDRH: - description: RAMECC monitor 5 failing data high register - addressOffset: 0xB0 - access: read-write - resetValue: 0x00000000 - M5FECR: - description: RAMECC monitor 5 failing error code register - addressOffset: 0xB4 - access: read-write - resetValue: 0x00000000 - RAMECC2: - derivedFrom: RAMECC1 - baseAddress: 0x48023000 - RAMECC3: - description: RAM ECC monitoring - groupName: RAMECC - baseAddress: 0x58027000 - registers: - IER: - description: RAMECC interrupt enable register - addressOffset: 0x0 - access: read-write - resetValue: 0x00000000 - fields: - GECCDEBWIE: - description: Global ECC double error on byte write interrupt enable - bitOffset: 3 - bitWidth: 1 - access: read-write - GECCDEIE: - description: Global ECC double error interrupt enable - bitOffset: 2 - bitWidth: 1 - access: read-write - GECCSEIE: - description: Global ECC single error interrupt enable - bitOffset: 1 - bitWidth: 1 - access: read-write - GIE: - description: Global interrupt enable - bitOffset: 0 - bitWidth: 1 - access: read-write - M1CR: - description: RAMECC monitor 1 configuration register - addressOffset: 0x20 - access: read-write - resetValue: 0x00000000 - M1SR: - description: RAMECC monitor 1 status register - addressOffset: 0x24 - access: read-write - resetValue: 0x00000000 - M1FAR: - description: RAMECC monitor 1 failing address register - addressOffset: 0x28 - access: read-write - resetValue: 0x00000000 - M1FDRL: - description: RAMECC monitor 1 failing data low register - addressOffset: 0x2C - access: read-write - resetValue: 0x00000000 - M1FDRH: - description: RAMECC monitor 1 failing data high register - addressOffset: 0x30 - access: read-write - resetValue: 0x00000000 - M1FECR: - description: RAMECC monitor 1 failing error code register - addressOffset: 0x34 - access: read-write - resetValue: 0x00000000 - M2CR: - description: RAMECC monitor 2 configuration register - addressOffset: 0x40 - access: read-write - resetValue: 0x00000000 - M2SR: - description: RAMECC monitor 2 status register - addressOffset: 0x44 - access: read-write - resetValue: 0x00000000 - M2FAR: - description: RAMECC monitor 2 failing address register - addressOffset: 0x48 - access: read-write - resetValue: 0x00000000 - M2FDRL: - description: RAMECC monitor 2 failing data low register - addressOffset: 0x4C - access: read-write - resetValue: 0x00000000 - M2FDRH: - description: RAMECC monitor 2 failing data high register - addressOffset: 0x50 - access: read-write - resetValue: 0x00000000 - M2FECR: - description: RAMECC monitor 2 failing error code register - addressOffset: 0x54 - access: read-write - resetValue: 0x00000000 diff --git a/devices/common_patches/rcc_LSECSSC_LSECSSF.yaml b/devices/common_patches/rcc_LSECSSC_LSECSSF.yaml deleted file mode 100644 index f0b2e1fd7..000000000 --- a/devices/common_patches/rcc_LSECSSC_LSECSSF.yaml +++ /dev/null @@ -1,16 +0,0 @@ -RCC: - CIR: - _add: - LSECSSC: - description: "LSE Clock security system interrupt clear" - bitOffset: 22 - bitWidth: 1 - access: write-only - LSECSSF: - description: "LSE Clock security system interrupt flag" - bitOffset: 6 - bitWidth: 1 - LSECSSIE: - description: "LSE clock security system interrupt enable" - bitOffset: 14 - bitWidth: 1 diff --git a/devices/common_patches/rcc_add_gpiojk.yaml b/devices/common_patches/rcc_add_gpiojk.yaml deleted file mode 100644 index f75572cff..000000000 --- a/devices/common_patches/rcc_add_gpiojk.yaml +++ /dev/null @@ -1,31 +0,0 @@ -RCC: - AHB1RSTR: - _add: - GPIOJRST: - description: IO port J reset - bitOffset: 9 - bitWidth: 1 - GPIOKRST: - description: IO port K reset - bitOffset: 10 - bitWidth: 1 - AHB1ENR: - _add: - GPIOJEN: - description: IO port J clock enable - bitOffset: 9 - bitWidth: 1 - GPIOKEN: - description: IO port K clock enable - bitOffset: 10 - bitWidth: 1 - AHB1LPENR: - _add: - GPIOJLPEN: - description: IO port J clock enable during Sleep mode - bitOffset: 9 - bitWidth: 1 - GPIOKLPEN: - description: IO port K clock enable during Sleep mode - bitOffset: 10 - bitWidth: 1 diff --git a/devices/common_patches/rcc_add_plli2sm.yaml b/devices/common_patches/rcc_add_plli2sm.yaml deleted file mode 100644 index 785b336f9..000000000 --- a/devices/common_patches/rcc_add_plli2sm.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - PLLI2SCFGR: - _add: - PLLI2SM: - description: "Division factor for the audio PLL (PLLI2S) input clock" - bitOffset: 0 - bitWidth: 6 diff --git a/devices/common_patches/rcc_add_plli2sp.yaml b/devices/common_patches/rcc_add_plli2sp.yaml deleted file mode 100644 index dcf689ea6..000000000 --- a/devices/common_patches/rcc_add_plli2sp.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - PLLI2SCFGR: - _add: - PLLI2SP: - description: "PLLI2S division factor for SPDIFRX clock" - bitOffset: 16 - bitWidth: 2 diff --git a/devices/common_patches/rcc_add_plli2sq_sai.yaml b/devices/common_patches/rcc_add_plli2sq_sai.yaml deleted file mode 100644 index 1bdb14195..000000000 --- a/devices/common_patches/rcc_add_plli2sq_sai.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - PLLI2SCFGR: - _add: - PLLI2SQ: - description: "PLLI2S division factor for SAI1 clock" - bitOffset: 24 - bitWidth: 4 diff --git a/devices/common_patches/rcc_add_plli2sq_usb.yaml b/devices/common_patches/rcc_add_plli2sq_usb.yaml deleted file mode 100644 index 8f1760a25..000000000 --- a/devices/common_patches/rcc_add_plli2sq_usb.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - PLLI2SCFGR: - _add: - PLLI2SQ: - description: "PLLI2S division factor for USB OTG FS/SDIO/RNG clock" - bitOffset: 24 - bitWidth: 4 diff --git a/devices/common_patches/rcc_dma2d_ltdc.yaml b/devices/common_patches/rcc_dma2d_ltdc.yaml deleted file mode 100644 index f777c4537..000000000 --- a/devices/common_patches/rcc_dma2d_ltdc.yaml +++ /dev/null @@ -1,38 +0,0 @@ -# Add missing reset/enable bits for the LCD controller and 2D-DMA -RCC: - AHB1RSTR: - _add: - DMA2DRST: - description: DMA2D reset - bitOffset: 23 - bitWidth: 1 - APB2RSTR: - _add: - LTDCRST: - description: LTDC reset - bitOffset: 26 - bitWidth: 1 - AHB1ENR: - _add: - DMA2DEN: - description: DMA2D clock enable - bitOffset: 23 - bitWidth: 1 - APB2ENR: - _add: - LTDCEN: - description: LTDC clock enable - bitOffset: 26 - bitWidth: 1 - AHB1LPENR: - _add: - DMA2DLPEN: - description: DMA2D clock enable during Sleep mode - bitOffset: 23 - bitWidth: 1 - APB2LPENR: - _add: - LTDCLPEN: - description: LTDC clock enable during Sleep mode - bitOffset: 26 - bitWidth: 1 diff --git a/devices/common_patches/rcc_rename_plli2scfgr.yaml b/devices/common_patches/rcc_rename_plli2scfgr.yaml deleted file mode 100644 index cbb8c7f0c..000000000 --- a/devices/common_patches/rcc_rename_plli2scfgr.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - PLLI2SCFGR: - _modify: - PLLI2SRx: - name: PLLI2SR - PLLI2SNx: - name: PLLI2SN diff --git a/devices/common_patches/rcc_sai.yaml b/devices/common_patches/rcc_sai.yaml deleted file mode 100644 index 964a21e4b..000000000 --- a/devices/common_patches/rcc_sai.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# Add missing reset/enable bits for the SAI clock and PLL -_include: - - ./pllsai.yaml - -RCC: - APB2RSTR: - _add: - SAI1RST: - description: SAI1 reset - bitOffset: 22 - bitWidth: 1 - APB2ENR: - _add: - SAI1EN: - description: SAI1 clock enable - bitOffset: 22 - bitWidth: 1 - APB2LPENR: - _add: - SAI1LPEN: - description: SAI1 clock enable during Sleep mode - bitOffset: 22 - bitWidth: 1 diff --git a/devices/common_patches/rcc_spi4.yaml b/devices/common_patches/rcc_spi4.yaml deleted file mode 100644 index a040fa485..000000000 --- a/devices/common_patches/rcc_spi4.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Add missing reset/enable bits for SPI 4 -RCC: - APB2RSTR: - _add: - SPI4RST: - description: SPI4 reset - bitOffset: 13 - bitWidth: 1 - APB2ENR: - _add: - SPI4EN: - description: SPI4 clock enable - bitOffset: 13 - bitWidth: 1 - APB2LPENR: - _add: - SPI4LPEN: - description: SPI4 clock enable during Sleep mode - bitOffset: 13 - bitWidth: 1 diff --git a/devices/common_patches/rcc_spi5.yaml b/devices/common_patches/rcc_spi5.yaml deleted file mode 100644 index 864c2ab29..000000000 --- a/devices/common_patches/rcc_spi5.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# Add missing reset/enable bits for SPI 5 -RCC: - APB2RSTR: - _add: - SPI5RST: - description: SPI5 reset - bitOffset: 20 - bitWidth: 1 - APB2ENR: - _add: - SPI5EN: - description: SPI5 clock enable - bitOffset: 20 - bitWidth: 1 - APB2LPENR: - _add: - SPI5LPEN: - description: SPI5 clock enable during Sleep mode - bitOffset: 20 - bitWidth: 1 diff --git a/devices/common_patches/remove_l0_mpu.yaml b/devices/common_patches/remove_l0_mpu.yaml deleted file mode 100644 index 5f4c423fb..000000000 --- a/devices/common_patches/remove_l0_mpu.yaml +++ /dev/null @@ -1,3 +0,0 @@ -# Remove MPU from L0 Family -_delete: - - MPU \ No newline at end of file diff --git a/devices/common_patches/remove_l0_scb.yaml b/devices/common_patches/remove_l0_scb.yaml deleted file mode 100644 index df3458776..000000000 --- a/devices/common_patches/remove_l0_scb.yaml +++ /dev/null @@ -1,3 +0,0 @@ -# Delete STK from L0 Family -_delete: - - STK \ No newline at end of file diff --git a/devices/common_patches/remove_l0_stk.yaml b/devices/common_patches/remove_l0_stk.yaml deleted file mode 100644 index 5f519c596..000000000 --- a/devices/common_patches/remove_l0_stk.yaml +++ /dev/null @@ -1,3 +0,0 @@ -# Delete SCB from L0 Family -_delete: - - SCB \ No newline at end of file diff --git a/devices/common_patches/rename_LPUART_CR2_DATAINV_field.yaml b/devices/common_patches/rename_LPUART_CR2_DATAINV_field.yaml deleted file mode 100644 index 34b76e4d1..000000000 --- a/devices/common_patches/rename_LPUART_CR2_DATAINV_field.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Rename LPUART CR2 DATAINV field -# Other families has it. - -"LPUART*": - CR2: - _modify: - TAINV: - name: DATAINV diff --git a/devices/common_patches/rename_RCC_CIR_HSI14RDYIE_field.yaml b/devices/common_patches/rename_RCC_CIR_HSI14RDYIE_field.yaml deleted file mode 100644 index 02ff16ae5..000000000 --- a/devices/common_patches/rename_RCC_CIR_HSI14RDYIE_field.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CIR: - _modify: - HSI14RDYE: - name: HSI14RDYIE diff --git a/devices/common_patches/rename_TIM2_CCR3_CCR3.yaml b/devices/common_patches/rename_TIM2_CCR3_CCR3.yaml deleted file mode 100644 index a8cbc1a02..000000000 --- a/devices/common_patches/rename_TIM2_CCR3_CCR3.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Rename badly named - -"TIM[23]": - CCR3: - _modify: - CCR1: - name: CCR3 diff --git a/devices/common_patches/rename_USART_CR1_M0_field.yaml b/devices/common_patches/rename_USART_CR1_M0_field.yaml deleted file mode 100644 index fe772732a..000000000 --- a/devices/common_patches/rename_USART_CR1_M0_field.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Rename USART CR1 M to M0 - -"USART*": - CR1: - _modify: - M: - name: M0 diff --git a/devices/common_patches/rename_USART_CR2_DATAINV_field.yaml b/devices/common_patches/rename_USART_CR2_DATAINV_field.yaml deleted file mode 100644 index 1564f40c3..000000000 --- a/devices/common_patches/rename_USART_CR2_DATAINV_field.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Rename USART CR2 DATAINV field -# Other families has it. - -"USART*": - CR2: - _modify: - TAINV: - name: DATAINV diff --git a/devices/common_patches/rename_USB_EPxR_EPTYPE_field.yaml b/devices/common_patches/rename_USB_EPxR_EPTYPE_field.yaml deleted file mode 100644 index ee4e0705a..000000000 --- a/devices/common_patches/rename_USB_EPxR_EPTYPE_field.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Rename EPTYPE to EP_TYPE - -USB: - "EP*R": - _modify: - EPTYPE: - name: EP_TYPE diff --git a/devices/common_patches/rename_USB_FS_peripheral_to_USB.yaml b/devices/common_patches/rename_USB_FS_peripheral_to_USB.yaml deleted file mode 100644 index 5b8d7c2c4..000000000 --- a/devices/common_patches/rename_USB_FS_peripheral_to_USB.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Rename USB_FS peripheral to USB peripheral -# Allow all devices with USB to have same peripheral name - -_modify: - _peripherals: - USB_FS: - name: USB diff --git a/devices/common_patches/rename_f0_SPI_registers.yaml b/devices/common_patches/rename_f0_SPI_registers.yaml deleted file mode 100644 index 0695d6fa3..000000000 --- a/devices/common_patches/rename_f0_SPI_registers.yaml +++ /dev/null @@ -1,13 +0,0 @@ -#RM0360 & RM0091 for STM32f0x0, stm32f0x1, stm32f0x2, stm32f0x8 indicate these register names - -"SPI*": - CR1: - _modify: - DFF: - name: CRCL - description: "CRC length" - SR: - _modify: - TIFRFE: - name: FRE - description: "Frame format error" diff --git a/devices/common_patches/rename_ltcd.yaml b/devices/common_patches/rename_ltcd.yaml deleted file mode 100644 index 603a22002..000000000 --- a/devices/common_patches/rename_ltcd.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# Several devices have the LTDC peripheral misnamed as LTCD. - -_modify: - _peripherals: - LTCD: - name: LTDC diff --git a/devices/common_patches/rtc/rtc_bkpr.yaml b/devices/common_patches/rtc/rtc_bkpr.yaml deleted file mode 100644 index 14052b933..000000000 --- a/devices/common_patches/rtc/rtc_bkpr.yaml +++ /dev/null @@ -1,3 +0,0 @@ -RTC: - _array: - "BKP*R": {} diff --git a/devices/common_patches/rtc/rtc_cr.yaml b/devices/common_patches/rtc/rtc_cr.yaml deleted file mode 100644 index 1a2f9943a..000000000 --- a/devices/common_patches/rtc/rtc_cr.yaml +++ /dev/null @@ -1,6 +0,0 @@ -RTC: - CR: - _modify: - WCKSEL: - name: WUCKSEL - diff --git a/devices/common_patches/sai/sai_v1.yaml b/devices/common_patches/sai/sai_v1.yaml deleted file mode 100644 index 84d3a879d..000000000 --- a/devices/common_patches/sai/sai_v1.yaml +++ /dev/null @@ -1,41 +0,0 @@ -"SAI,SAI?": - _cluster: - "CH%s": - "?CR1": {} - "?CR2": {} - "?FRCR": {} - "?SLOTR": {} - "?IM": {} - "?SR": {} - "?CLRFR": {} - "?DR": {} - "?CR1": - _modify: - OutDri: - name: OUTDRIV - SAI?EN: - name: SAIEN - "?CR2": - _modify: - FFLUS: - name: FFLUSH - "?IM": - _modify: - WCKCFG: - name: WCKCFGIE - MUTEDET: - name: MUTEDETIE - LFSDET: - name: LFSDETIE - "?CLRFR": - _modify: - LFSDET: - name: CLFSDET - CNRDY: - name: CCNRDY - WCKCFG: - name: CWCKCFG - MUTEDET: - name: CMUTEDET - OVRUDR: - name: COVRUDR diff --git a/devices/common_patches/sai/sai_v2.yaml b/devices/common_patches/sai/sai_v2.yaml deleted file mode 100644 index 050bd2c77..000000000 --- a/devices/common_patches/sai/sai_v2.yaml +++ /dev/null @@ -1,19 +0,0 @@ -"SAI?": - _strip: - - SAI_ - _cluster: - "CH%s": - "?CR1": - _modify: - SAIAEN: - name: SAIEN - "?CR2": {} - "?FRCR": {} - "?SLOTR": {} - "?IM": {} - "?SR": - _modify: - FLTH: - name: FLVL - "?CLRFR": {} - "?DR": {} diff --git a/devices/common_patches/sdio_f446.yaml b/devices/common_patches/sdio_f446.yaml deleted file mode 100644 index bbd1d7abf..000000000 --- a/devices/common_patches/sdio_f446.yaml +++ /dev/null @@ -1,233 +0,0 @@ -_modify: - SDMMC: - name: SDIO - description: 'Secure digital input/output SD/SDIO MMC card host interface' - groupName: SDIO - addressBlock: - size: "0x400" - -SDIO: - _strip: SDMMC_ - _delete: - - '*ACKTIMER' - - '*IDMA*' - - '*VER' - - '*ID' - _modify: - SDMMC_POWER: - description: 'SDIO power control register' - SDMMC_CLKCR: - description: 'CLKCR register controls the SDIO_CK output clock.' - SDMMC_CMDR: - name: "SDMMC_CMD" - SDMMC_RESP4R: - addressOffset: "0x20" - name: RESP4 - SDMMC_RESP3R: - addressOffset: "0x1C" - name: RESP3 - SDMMC_RESP2R: - addressOffset: "0x18" - name: RESP2 - SDMMC_RESP1R: - addressOffset: "0x14" - name: RESP1 - SDMMC_ARGR: - name: ARG - SDMMC_RESPCMDR: - name: RESPCMD - addressOffset: "0x10" - SDMMC_DLENR: - name: "SDMMC_DLEN" - SDMMC_DCNTR: - name: 'SDMMC_DCOUNT' - SDMMC_STAR: - name: SDMMC_STA - SDMMC_MASKR: - name: SDMMC_MASK - SDMMC_FIFOR: - addressOffset: "0x80" - name: SDMMC_FIFO - - _add: - _interrupts: - SDIO: - description: SDIO global interrupt - value: 49 - FIFOCNT: - description: 'The SDIO_FIFOCNT register contains the remaining number of words to be written to or read from the FIFO. The FIFO counter loads the value from the data length register (see SDIO_DLEN) when the data transfer enable bit, DTEN, is set in the data control register (SDIO_DCTRL register) and the DPSM is at the Idle state. If the data length is not word-aligned (multiple of 4), the remaining 1 to 3 bytes are regarded as a word.' - addressOffset: "0x48" - size: "0x20" - resetValue: "0x00000000" - access: read-only - fields: - FIFOCOUNT: - description: 'Remaining number of words to be written to or read from the FIFO' - bitOffset: 0 - bitWidth: 24 - access: read-only - - POWER: - description: 'SDIO power control register' - _delete: - - VSWITCH - - VSWITCHEN - - DIRPOL - _modify: - PWRCTRL: - description: 'Power supply control bits. These bits are used to define the current functional state of the card clock' - - CLKCR: - _modify: - CLKDIV: - bitWidth: 8 - description: 'Clock divide factor. This field defines the divide factor between the input clock (SDIOCLK) and the output clock (SDIO_CK): SDIO_CK frequency = SDIOCLK / [CLKDIV + 2]. While the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK frequency must be less than 400 kHz. The clock frequency can be changed to the maximum card bus frequency when relative card addresses are assigned to all cards' - PWRSAV: - bitOffset: 9 - description: 'Power saving configuration bit. For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting PWRSAV' - WIDBUS: - bitOffset: 11 - NEGEDGE: - bitOffset: 13 - description: 'SDIO_CK dephasing selection bit. When BYPASS is active, the data and the command change on SDIOCLK falling edge whatever NEGEDGE value' - HWFC_EN: - bitOffset: 14 - description: 'HW Flow Control enable. When HW Flow Control is enabled, the meaning of the TXFIFOE and RXFIFOF interrupt signals, see SDIO Status register definition in Section 29.8.11' - _delete: - - SELCLKRX - - BUSSPEED - - DDR - _add: - CLKEN: - bitWidth: 1 - bitOffset: 8 - description: 'Clock enable bit' - access: read-write - BYPASS: - bitWidth: 1 - bitOffset: 10 - description: 'Clock divider bypass enable bit' - access: read-write - - CMD: - _delete: - - CMDTRANS - - CMDSTOP - - DTHOLD - - BOOTMODE - - BOOTEN - _modify: - WAITRESP: - bitOffset: 6 - WAITINT: - bitOffset: 8 - WAITPEND: - bitOffset: 9 - description: 'PSM Waits for ends of data transfer (CmdPend internal signal). If this bit is set, the CPSM waits for the end of data transfer before it starts sending a command. This feature is available only with Stream data transfer mode SDIO_DCTRL[2] = 1.' - CPSMEN: - bitOffset: 10 - CMDSUSPEND: - name: SDIOSuspend - bitOffset: 11 - description: 'SD I/O suspend command. If this bit is set, the command to be sent is a suspend command (to be used only with SDIO card)' - - DCTRL: - _delete: - - FIFORST - - BOOTACKEN - _modify: - DTMODE: - bitWidth: 1 - DBLOCKSIZE: - description: 'Data block size. Define the data block length when the block data transfer mode is selected, block length = 2^(DBLOCKSIZE) bytes' - _add: - DMAEN: - bitWidth: 1 - bitOffset: 3 - description: 'DMA enable' - access: read-write - DBLOCKSIZE: [0, 14] - - DCOUNT: - _modify: - DATACOUNT: - bitWidth: 25 - - STA: - # Note: RM0390 has a little erroneous description [bit 23 is none] - _delete: - - IDMABTC - - IDMATE - - CKSTOP - - VSWEND - - ACKTIMEOUT - - ACKFAIL - - DHOLD - _modify: - BUSYD0END: - name: RXDAVL - BUSYD0: - name: TXDAVL - CPSMACT: - name: RXACT - DPSMACT: - name: TXACT - DABORT: - name: CMDACT - - ICR: - _delete: - - IDMABTCC - - IDMATECC - - CKSTOPC - - VSWENDC - - ACKTIMEOUTC - - ACKFAILC - - BUSYD0ENDC - - DABORTC - - DHOLDC - - FIFO: - _modify: - FIFODATA: - name: FIFOData - - MASK: - _delete: - - IDMABTCIE - - CKSTOPIE - - VSWENDIE - - ACKTIMEOUTIE - - ACKFAILIE - - DHOLDIE - _modify: - BUSYD0ENDIE: - name: RXDAVLIE - DABORTIE: - name: CMDACTIE - _add: - TXDAVLIE: - bitOffset: 20 - bitWidth: 1 - access: read-write - description: 'Data available in Tx FIFO interrupt enable. Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Tx FIFO' - RXFIFOEIE: - bitOffset: 19 - bitWidth: 1 - access: read-write - description: 'Rx FIFO empty interrupt enable. Set and cleared by software to enable/disable interrupt caused by Rx FIFO empty' - TXFIFOFIE: - bitOffset: 16 - bitWidth: 1 - access: read-write - description: 'Tx FIFO full interrupt enable. Set and cleared by software to enable/disable interrupt caused by Tx FIFO full' - RXACTIE: - bitOffset: 13 - bitWidth: 1 - access: read-write - description: 'Data receive acting interrupt enable. Set and cleared by software to enable/disable interrupt caused by data being received (data receive acting)' - TXACTIE: - bitOffset: 12 - bitWidth: 1 - access: read-write - description: 'Data transmit acting interrupt enable. Set and cleared by software to enable/disable interrupt caused by data being transferred (data transmit acting)' diff --git a/devices/common_patches/split_exti.yaml b/devices/common_patches/split_exti.yaml deleted file mode 100644 index 2f2b2d53b..000000000 --- a/devices/common_patches/split_exti.yaml +++ /dev/null @@ -1,13 +0,0 @@ -EXTI: - IMR: - _split: [MR] - EMR: - _split: [MR] - RTSR: - _split: [TR] - FTSR: - _split: [TR] - SWIER: - _split: [SWIER] - PR: - _split: [PR] diff --git a/devices/common_patches/tim/tim14_16bit_l.yaml b/devices/common_patches/tim/tim14_16bit_l.yaml deleted file mode 100644 index 6752a50ab..000000000 --- a/devices/common_patches/tim/tim14_16bit_l.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# TIM14 is 16 bit -# tim2_common_16bit assumes four channels; TIM14 only has one - -# For devices where the SVD names 16bit timer fields ending "L" or "_L" - -TIM14: - _include: - - ./tim_1ch_16bit_l.yaml diff --git a/devices/common_patches/tim/tim15_16bit_l.yaml b/devices/common_patches/tim/tim15_16bit_l.yaml deleted file mode 100644 index 8c20e79a5..000000000 --- a/devices/common_patches/tim/tim15_16bit_l.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# TIM15 is 16 bit -# tim2_common_16bit assumes four channels; TIM15 only has two - -# For devices where the SVD names 16bit timer fields ending "L" or "_L" - -TIM15: - _include: - - ./tim_2ch_16bit_l.yaml diff --git a/devices/common_patches/tim/tim16_16bit_l.yaml b/devices/common_patches/tim/tim16_16bit_l.yaml deleted file mode 100644 index 7667d1d7a..000000000 --- a/devices/common_patches/tim/tim16_16bit_l.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# TIM16 is 16 bit -# tim2_common_16bit assumes four channels; TIM16 only has one - -# For devices where the SVD names 16bit timer fields ending "L" or "_L" - -TIM16: - _include: - - ./tim_1ch_16bit_l.yaml diff --git a/devices/common_patches/tim/tim1_16bit_l.yaml b/devices/common_patches/tim/tim1_16bit_l.yaml deleted file mode 100644 index edfc2af25..000000000 --- a/devices/common_patches/tim/tim1_16bit_l.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# TIM1 is 16 bit - -# For devices where the SVD names 16bit timer fields ending "L" or "_L" - -TIM1: - _include: - - ./tim2_common_16bit_l.yaml diff --git a/devices/common_patches/tim/tim2345_16bit_l.yaml b/devices/common_patches/tim/tim2345_16bit_l.yaml deleted file mode 100644 index 4729961a4..000000000 --- a/devices/common_patches/tim/tim2345_16bit_l.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# General-purpose timers -# TIM2/TIM3/TIM4/TIM5 are 16 bit - -# For devices where the SVD names 16bit timer fields ending "L" or "_L" - -"TIM[2345]": - _include: - - ./tim2_common_16bit_l.yaml diff --git a/devices/common_patches/tim/tim2345_mixed.yaml b/devices/common_patches/tim/tim2345_mixed.yaml deleted file mode 100644 index e3dbf7fef..000000000 --- a/devices/common_patches/tim/tim2345_mixed.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# General-purpose timers on F0, F3, F4, F7, H7 (at least) -# TIM2/TIM5 are 32 bit, TIM3/TIM4 are 16 bit - -"TIM[25]": - _include: - - ./tim2_common_32bit.yaml diff --git a/devices/common_patches/tim/tim2345_mixed_l.yaml b/devices/common_patches/tim/tim2345_mixed_l.yaml deleted file mode 100644 index 5787d317d..000000000 --- a/devices/common_patches/tim/tim2345_mixed_l.yaml +++ /dev/null @@ -1,12 +0,0 @@ -# General-purpose timers on F0, F3, F4, F7, H7 (at least) -# TIM2/TIM5 are 32 bit, TIM3/TIM4 are 16 bit - -# For devices where the SVD names 16bit timer fields ending "L" or "_L" - -"TIM[34]": - _include: - - ./tim2_common_16bit_l.yaml - -"TIM[25]": - _include: - - ./tim2_common_32bit.yaml diff --git a/devices/common_patches/tim/tim2_32bit.yaml b/devices/common_patches/tim/tim2_32bit.yaml deleted file mode 100644 index 99fd3a0f9..000000000 --- a/devices/common_patches/tim/tim2_32bit.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# General-purpose timer where there is only a single 32-bit timer in -# the TIM[2-5] set. -# -# See tim2345* for when there are other timers - -"TIM2": - _include: - - ./tim2_common_32bit.yaml diff --git a/devices/common_patches/tim/tim2_common_16bit_l.yaml b/devices/common_patches/tim/tim2_common_16bit_l.yaml deleted file mode 100644 index 886337930..000000000 --- a/devices/common_patches/tim/tim2_common_16bit_l.yaml +++ /dev/null @@ -1,34 +0,0 @@ -# 16bit TIM2 peripheral -# For 16bit timers where the SVD names fields ending "L" or "_L" -# Applies to Advanced-control (ac) and General-purpose (gp) timers - -CNT: - _modify: - "CNT_L,CNTL": - name: CNT - description: Counter value -ARR: - _modify: - "ARR_L,ARRL": - name: ARR - description: "Auto-reload value" -CCR1: - _modify: - "CCR1_L,CCR1L": - name: CCR1 - description: "Capture/Compare 1 value" -CCR2: - _modify: - "CCR2_L,CCR2L": - name: CCR2 - description: "Capture/Compare 2 value" -CCR3: - _modify: - "CCR3_L,CCR3L": - name: CCR3 - description: "Capture/Compare 3 value" -CCR4: - _modify: - "CCR4_L,CCR4L": - name: CCR4 - description: "Capture/Compare 4 value" diff --git a/devices/common_patches/tim/tim2_common_32bit.yaml b/devices/common_patches/tim/tim2_common_32bit.yaml deleted file mode 100644 index 339314703..000000000 --- a/devices/common_patches/tim/tim2_common_32bit.yaml +++ /dev/null @@ -1,64 +0,0 @@ -# 32bit TIM2 peripheral -# Applies to Advanced-control (ac) and General-purpose (gp) timers - -# TIM2 is present on all devices except stm32f410 and stm32f0x0. -# TIM2 is 16bit on STM32F1 family. -# TIM3 is present on all devices with TIM2 except STML4x3 family. -# TIM3 is present on stm32f0x0. - -CNT: - # Actualy a 32bit register - _modify: - CNT_H: - name: CNTH - description: Counter value - CNT_L: - name: CNTL - _merge: - - "CNT*" -ARR: - # Actualy a 32bit register - _modify: - ARR_H: - name: ARRH - description: "Auto-reload value" - ARR_L: - name: ARRL - _merge: - - "ARR*" -CCR1: - _modify: - CCR1_H: - name: CCR1H - description: "Capture/Compare 1 value" - CCR1_L: - name: CCR1L - _merge: - - "CCR1*" -CCR2: - _modify: - CCR2_H: - name: CCR2H - description: "Capture/Compare 2 value" - CCR2_L: - name: CCR2L - _merge: - - "CCR2*" -CCR3: - _modify: - CCR3_H: - name: CCR3H - description: "Capture/Compare 3 value" - CCR3_L: - name: CCR3L - _merge: - - "CCR3*" -CCR4: - _modify: - CCR4_H: - name: CCR4H - description: "Capture/Compare 4 value" - CCR4_L: - name: CCR4L - _merge: - - "CCR4*" diff --git a/devices/common_patches/tim/tim_1ch_16bit_l.yaml b/devices/common_patches/tim/tim_1ch_16bit_l.yaml deleted file mode 100644 index 67d45c047..000000000 --- a/devices/common_patches/tim/tim_1ch_16bit_l.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# 16bit timer peripheral with one channel -# For 16bit timers where the SVD names fields ending "L" or "_L" -# Applies to Advanced-control (ac) and General-purpose (gp) timers - -CNT: - _modify: - "CNT_L,CNTL": - name: CNT - description: Counter value -ARR: - _modify: - "ARR_L,ARRL": - name: ARR - description: "Auto-reload value" -CCR1: - _modify: - "CCR1_L,CCR1L": - name: CCR1 - description: "Capture/Compare 1 value" diff --git a/devices/common_patches/tim/tim_2ch_16bit_l.yaml b/devices/common_patches/tim/tim_2ch_16bit_l.yaml deleted file mode 100644 index 60c0f39fb..000000000 --- a/devices/common_patches/tim/tim_2ch_16bit_l.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# 16bit timer peripheral with two channels -# For 16bit timers where the SVD names fields ending "L" or "_L" -# Applies to Advanced-control (ac) and General-purpose (gp) timers - -CNT: - _modify: - "CNT_L,CNTL": - name: CNT - description: Counter value -ARR: - _modify: - "ARR_L,ARRL": - name: ARR - description: "Auto-reload value" -CCR1: - _modify: - "CCR1_L,CCR1L": - name: CCR1 - description: "Capture/Compare 1 value" -CCR2: - _modify: - "CCR2_L,CCR2L": - name: CCR2 - description: "Capture/Compare 2 value" diff --git a/devices/common_patches/tim/tim_ccr.yaml b/devices/common_patches/tim/tim_ccr.yaml deleted file mode 100644 index 0377f5c85..000000000 --- a/devices/common_patches/tim/tim_ccr.yaml +++ /dev/null @@ -1,7 +0,0 @@ -"TIM[1234589],TIM10,TIM11,TIM12,TIM13,TIM14,TIM21,TIM22": - "CCR?": - _modify: - "CCR?": - name: CCR - _array: - "CCR[1234]": {} diff --git a/devices/common_patches/tim/tim_h7.yaml b/devices/common_patches/tim/tim_h7.yaml deleted file mode 100644 index 295fb67c2..000000000 --- a/devices/common_patches/tim/tim_h7.yaml +++ /dev/null @@ -1,40 +0,0 @@ -# Additonal general-purpose timers on H7 (at least) -# TIM12/TIM13/TIM14/TIM15/TIM16/TIM17 are 16 bit - -# These have fewer capture/compare registers - -# TIM12-14 -# For 16bit timers where the SVD names fields ending "L" or "_L" -"TIM1[2-4]": - CNT: - _modify: - "CNT_L,CNTL": - name: CNT - description: Counter value - ARR: - _modify: - "ARR_L,ARRL": - name: ARR - description: "Auto-reload value" - CCR1: - _modify: - "CCR1_L,CCR1L": - name: CCR - description: "Capture/Compare 1 value" - -# TIM15-17 -# For 16bit timers where the SVD names fields ending "L" or "_L" -"TIM1[5-7]": - CCR1: - _modify: - "CCR1,CCR1_L,CCR1L": - name: CCR - description: "Capture/Compare 1 value" - -# Dual channel timers -"TIM1[25]": - CCR2: - _modify: - "CCR2,CCR2_L,CCR2L": - name: CCR - description: "Capture/Compare 2 value" diff --git a/devices/common_patches/tim/tim_o24ce.yaml b/devices/common_patches/tim/tim_o24ce.yaml deleted file mode 100644 index 079c3abe9..000000000 --- a/devices/common_patches/tim/tim_o24ce.yaml +++ /dev/null @@ -1,5 +0,0 @@ -"TIM[2345]": - CCMR2_Output: - _modify: - O24CE: - name: OC4CE diff --git a/devices/common_patches/tsc/tsc.yaml b/devices/common_patches/tsc/tsc.yaml deleted file mode 100644 index 5149438d4..000000000 --- a/devices/common_patches/tsc/tsc.yaml +++ /dev/null @@ -1,3 +0,0 @@ -TSC: - _array: - IOG?CR: {} diff --git a/devices/common_patches/unprefix_USB_registers.yaml b/devices/common_patches/unprefix_USB_registers.yaml deleted file mode 100644 index 6cde080f3..000000000 --- a/devices/common_patches/unprefix_USB_registers.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# Remove USB_ prefix on some USB registers - -USB: - _modify: - USB_EP0R: - name: EP0R - USB_EP1R: - name: EP1R - USB_EP2R: - name: EP2R - USB_EP3R: - name: EP3R - USB_EP4R: - name: EP4R - USB_EP5R: - name: EP5R - USB_EP6R: - name: EP6R - USB_EP7R: - name: EP7R - USB_CNTR: - name: CNTR diff --git a/devices/common_patches/usb_otg/otg_fs_fixes_107.yaml b/devices/common_patches/usb_otg/otg_fs_fixes_107.yaml deleted file mode 100644 index 42b63961f..000000000 --- a/devices/common_patches/usb_otg/otg_fs_fixes_107.yaml +++ /dev/null @@ -1,7 +0,0 @@ -_modify: - USB_OTG_GLOBAL: - name: OTG_FS_GLOBAL - USB_OTG_DEVICE: - name: OTG_FS_DEVICE - USB_OTG_PWRCLK: - name: OTG_FS_PWRCLK diff --git a/devices/common_patches/usb_otg/otg_fs_fixes_v1.yaml b/devices/common_patches/usb_otg/otg_fs_fixes_v1.yaml deleted file mode 100644 index 39f4380be..000000000 --- a/devices/common_patches/usb_otg/otg_fs_fixes_v1.yaml +++ /dev/null @@ -1,108 +0,0 @@ -# For F401, F411 - -OTG_FS_GLOBAL: - _add: - GRXSTSP_Device: - description: OTG status read and pop (device mode) - addressOffset: 0x20 - size: 32 - resetValue: 0x00000000 - access: read-only - fields: - STSPHST: - description: Status phase start - bitOffset: 27 - bitWidth: 1 - FRMNUM: - description: Frame number - bitOffset: 21 - bitWidth: 4 - PKTSTS: - description: Packet status - bitOffset: 17 - bitWidth: 4 - DPID: - description: Data PID - bitOffset: 15 - bitWidth: 2 - BCNT: - description: Byte count - bitOffset: 4 - bitWidth: 11 - EPNUM: - description: Endpoint number - bitOffset: 0 - bitWidth: 4 - - GRXSTSP_Host: - description: OTG status read and pop (host mode) - addressOffset: 0x20 - size: 32 - resetValue: 0x00000000 - access: read-only - alternateRegister: GRXSTSP_Device - fields: - PKTSTS: - description: Packet status - bitOffset: 17 - bitWidth: 4 - DPID: - description: Data PID - bitOffset: 15 - bitWidth: 2 - BCNT: - description: Byte count - bitOffset: 4 - bitWidth: 11 - CHNUM: - description: Channel number - bitOffset: 0 - bitWidth: 4 - - _modify: - GNPTXFSIZ_Device: - name: DIEPTXF0 - displayName: DIEPTXF0 - - GNPTXFSIZ_Host: - name: HNPTXFSIZ - displayName: HNPTXFSIZ - alternateRegister: DIEPTXF0 - - _array: - DIEPTXF[123]: - displayName: DIEPTXF%s - description: OTF_FS device IN endpoint transmit FIFO size register - - -OTG_FS_DEVICE: - _array: - DIEPCTL[123]: - displayName: DIEPCTL%s - description: OTG_FS device endpoint %s IN control register - DOEPCTL[123]: - displayName: DOEPCTL%s - description: OTG_FS device endpoint %s OUT control register - - DIEPCTL0: - _modify: - EPENA: - access: read-write - - DIEPCTL*: - _modify: - Stall: - name: STALL - description: STALL - - DOEPCTL*: - _modify: - Stall: - name: STALL - description: STALL - - DAINTMSK: - _modify: - OEPINT: - name: OEPM - description: OUT EP interrupt mask bits \ No newline at end of file diff --git a/devices/common_patches/usb_otg/otg_fs_fixes_v1_446_469.yaml b/devices/common_patches/usb_otg/otg_fs_fixes_v1_446_469.yaml deleted file mode 100644 index 445d766c3..000000000 --- a/devices/common_patches/usb_otg/otg_fs_fixes_v1_446_469.yaml +++ /dev/null @@ -1,173 +0,0 @@ -# For F446, F469, F479 - -OTG_FS_GLOBAL: - _derive: - DIEPTXF4: - _from: DIEPTXF1 - addressOffset: 0x110 - DIEPTXF5: - _from: DIEPTXF1 - addressOffset: 0x114 - - _add: - GRXSTSP_Device: - description: OTG status read and pop (device mode) - addressOffset: 0x20 - size: 32 - resetValue: 0x00000000 - access: read-only - fields: - STSPHST: - description: Status phase start - bitOffset: 27 - bitWidth: 1 - FRMNUM: - description: Frame number - bitOffset: 21 - bitWidth: 4 - PKTSTS: - description: Packet status - bitOffset: 17 - bitWidth: 4 - DPID: - description: Data PID - bitOffset: 15 - bitWidth: 2 - BCNT: - description: Byte count - bitOffset: 4 - bitWidth: 11 - EPNUM: - description: Endpoint number - bitOffset: 0 - bitWidth: 4 - - GRXSTSP_Host: - description: OTG status read and pop (host mode) - addressOffset: 0x20 - size: 32 - resetValue: 0x00000000 - access: read-only - alternateRegister: GRXSTSP_Device - fields: - PKTSTS: - description: Packet status - bitOffset: 17 - bitWidth: 4 - DPID: - description: Data PID - bitOffset: 15 - bitWidth: 2 - BCNT: - description: Byte count - bitOffset: 4 - bitWidth: 11 - CHNUM: - description: Channel number - bitOffset: 0 - bitWidth: 4 - - GLPMCFG: - addressOffset: 0x54 - # TODO - - _modify: - CID: - name: OTG_CID - resetValue: 0x00002000 - - GNPTXFSIZ_Device: - name: DIEPTXF0 - displayName: DIEPTXF0 - - GNPTXFSIZ_Host: - name: HNPTXFSIZ - displayName: HNPTXFSIZ - alternateRegister: DIEPTXF0 - - _array: - DIEPTXF[12345]: - displayName: DIEPTXF%s - description: OTF_FS device IN endpoint transmit FIFO size register - - -OTG_FS_DEVICE: - _derive: - DIEPCTL4: - _from: DIEPCTL1 - addressOffset: 0x180 - description: OTG device endpoint-4 control register - DIEPCTL5: - _from: DIEPCTL1 - addressOffset: 0x1A0 - description: OTG device endpoint-5 control register - DIEPINT4: - _from: DIEPINT1 - addressOffset: 0x188 - description: device endpoint-4 interrupt register - DIEPINT5: - _from: DIEPINT1 - addressOffset: 0x1A8 - description: device endpoint-5 interrupt register - DTXFSTS4: - _from: DTXFSTS1 - addressOffset: 0x198 - DTXFSTS5: - _from: DTXFSTS1 - addressOffset: 0x1B8 - DIEPTSIZ4: - _from: DIEPTSIZ1 - addressOffset: 0x190 - DIEPTSIZ5: - _from: DIEPTSIZ1 - addressOffset: 0x1b0 - DOEPCTL4: - _from: DOEPCTL1 - addressOffset: 0x380 - DOEPCTL5: - _from: DOEPCTL1 - addressOffset: 0x3a0 - DOEPINT4: - _from: DOEPINT1 - addressOffset: 0x388 - DOEPINT5: - _from: DOEPINT1 - addressOffset: 0x3a8 - DOEPTSIZ4: - _from: DOEPTSIZ1 - addressOffset: 0x390 - DOEPTSIZ5: - _from: DOEPTSIZ1 - addressOffset: 0x3b0 - - DIEPCTL0: - _modify: - EPENA: - access: read-write - - DIEPCTL*: - _modify: - Stall: - name: STALL - description: STALL - - DOEPCTL*: - _modify: - Stall: - name: STALL - description: STALL - - DAINTMSK: - _modify: - OEPINT: - name: OEPM - description: OUT EP interrupt mask bits - - _array: - DIEPCTL[12345]: {} - DIEPINT[12345]: {} - DIEPTSIZ[12345]: {} - DOEPCTL[12345]: {} - DOEPINT[12345]: {} - DOEPTSIZ[12345]: {} - DTXFSTS[12345]: {} diff --git a/devices/common_patches/usb_otg/otg_fs_remove_prefix.yaml b/devices/common_patches/usb_otg/otg_fs_remove_prefix.yaml deleted file mode 100644 index 7b9c60adb..000000000 --- a/devices/common_patches/usb_otg/otg_fs_remove_prefix.yaml +++ /dev/null @@ -1,2 +0,0 @@ -"OTG_FS_GLOBAL,OTG_FS_DEVICE,OTG_FS_HOST,OTG_FS_PWRCLK": - _strip: FS_ diff --git a/devices/common_patches/usb_otg/otg_hs_fixes_v1.yaml b/devices/common_patches/usb_otg/otg_hs_fixes_v1.yaml deleted file mode 100644 index 4eafc8af6..000000000 --- a/devices/common_patches/usb_otg/otg_hs_fixes_v1.yaml +++ /dev/null @@ -1,220 +0,0 @@ -# For F405, F407, F427, F429, F446, F469 - -# TODO: Support devices with different number of endpoints -# eg. 405, 407, 427, 429 -> 6 endpoints total -# eg. 446, 469, 479 -> 9 endpoints total - -# Fix power and clock gating control register name -OTG_HS_PWRCLK: - _modify: - PCGCR: - name: PCGCCTL - displayName: PCGCCTL - -OTG_HS_GLOBAL: - GINTSTS: - _modify: - WKUINT: - name: WKUPINT - description: Resume/remote wakeup detected interrupt - - _delete: - _registers: - - DIEPTXF6 - - DIEPTXF7 - - _modify: - GNPTXFSIZ_Host: - name: GNPTXFSIZ - displayName: GNPTXFSIZ - - TX0FSIZ_Peripheral: - name: TX0FSIZ - displayName: TX0FSIZ - alternateRegister: GNPTXFSIZ - - DIEPTXF3: - addressOffset: '0x10C' - DIEPTXF4: - addressOffset: '0x110' - DIEPTXF5: - addressOffset: '0x114' - - _array: - DIEPTXF[12345]: {} - -OTG_HS_DEVICE: - _delete: - _registers: - - DIEPCTL6 - - DIEPCTL7 - - DIEPINT6 - - DIEPINT7 - - DOEPINT6 - - DOEPINT7 - - # Rename Stall to uppercase - DIEPCTL*: - _modify: - Stall: - name: STALL - description: STALL handshake - - DOEPCTL*: - _modify: - Stall: - name: STALL - description: STALL handshake - - _add: - # Add missing device OUT EP control registers - DOEPCTL4: - description: device endpoint-4 control register - addressOffset: 0x380 - size: 0x20 - resetValue: 0x0 - fields: - EPENA: - bitOffset: 31 - bitWidth: 1 - access: read-write - EPDIS: - bitOffset: 30 - bitWidth: 1 - access: read-write - SODDFRM: - bitOffset: 29 - bitWidth: 1 - access: write-only - SD0PID_SEVNFRM: - bitOffset: 28 - bitWidth: 1 - access: write-only - SNAK: - bitOffset: 27 - bitWidth: 1 - access: write-only - CNAK: - bitOffset: 26 - bitWidth: 1 - access: write-only - STALL: - bitOffset: 21 - bitWidth: 1 - access: read-write - description: STALL handshake - SNPM: - bitOffset: 20 - bitWidth: 1 - access: read-write - EPTYP: - bitOffset: 18 - bitWidth: 2 - access: read-write - NAKSTS: - bitOffset: 17 - bitWidth: 1 - access: read-only - EONUM_DPID: - bitOffset: 16 - bitWidth: 1 - access: read-only - USBAEP: - bitOffset: 15 - bitWidth: 1 - access: read-write - MPSIZ: - bitOffset: 0 - bitWidth: 11 - access: read-write - - DOEPCTL5: - description: device endpoint-5 control register - addressOffset: 0x3A0 - size: 0x20 - resetValue: 0x0 - fields: - EPENA: - bitOffset: 31 - bitWidth: 1 - access: read-write - EPDIS: - bitOffset: 30 - bitWidth: 1 - access: read-write - SODDFRM: - bitOffset: 29 - bitWidth: 1 - access: write-only - SD0PID_SEVNFRM: - bitOffset: 28 - bitWidth: 1 - access: write-only - SNAK: - bitOffset: 27 - bitWidth: 1 - access: write-only - CNAK: - bitOffset: 26 - bitWidth: 1 - access: write-only - STALL: - bitOffset: 21 - bitWidth: 1 - access: read-write - description: STALL handshake - SNPM: - bitOffset: 20 - bitWidth: 1 - access: read-write - EPTYP: - bitOffset: 18 - bitWidth: 2 - access: read-write - NAKSTS: - bitOffset: 17 - bitWidth: 1 - access: read-only - EONUM_DPID: - bitOffset: 16 - bitWidth: 1 - access: read-only - USBAEP: - bitOffset: 15 - bitWidth: 1 - access: read-write - MPSIZ: - bitOffset: 0 - bitWidth: 11 - access: read-write - - # Add missing device OUT EP 5 transfer size register - DOEPTSIZ5: - description: OTG_HS device endpoint-5 transfer size register - addressOffset: 0x3B0 - size: 0x20 - access: read-write - resetValue: 0x0 - fields: - XFRSIZ: - description: Transfer size - bitOffset: 0 - bitWidth: 19 - PKTCNT: - description: Packet count - bitOffset: 19 - bitWidth: 10 - RXDPID_STUPCNT: - description: Received data PID/SETUP packet count - bitOffset: 29 - bitWidth: 2 - - _array: - DIEPCTL[12345]: {} - DOEPCTL[12345]: {} - DIEPTSIZ[12345]: {} - DOEPTSIZ[12345]: {} - DIEPINT[012345]: {} - DOEPINT[012345]: {} - DTXFSTS[012345]: {} - \ No newline at end of file diff --git a/devices/common_patches/usb_otg/otg_hs_remove_prefix.yaml b/devices/common_patches/usb_otg/otg_hs_remove_prefix.yaml deleted file mode 100644 index 2503bde47..000000000 --- a/devices/common_patches/usb_otg/otg_hs_remove_prefix.yaml +++ /dev/null @@ -1,2 +0,0 @@ -"OTG_HS_GLOBAL,OTG_HS_DEVICE,OTG_HS_HOST,OTG_HS_PWRCLK": - _strip: OTG_HS_ \ No newline at end of file diff --git a/devices/fields/adc/adc1_f1.yaml b/devices/fields/adc/adc1_f1.yaml new file mode 100644 index 000000000..b50acbe6c --- /dev/null +++ b/devices/fields/adc/adc1_f1.yaml @@ -0,0 +1,12 @@ +CR1: + DUALMOD: + Independent: [0, Independent mode] + RegularInjected: [1, "Combined regular simultaneous + injected simultaneous mode"] + RegularAlternateTrigger: [2, "Combined regular simultaneous + alternate trigger mode"] + InjectedFastInterleaved: [3, "Combined injected simultaneous + fast interleaved mode"] + InjectedSlowInterleaved: [4, "Combined injected simultaneous + slow interleaved mode"] + Injected: [5, Injected simultaneous mode only] + Regular: [6, Regular simultaneous mode only] + FastInterleaved: [7, Fast interleaved mode only] + SlowInterleaved: [8, Slow interleaved mode only] + AlternateTrigger: [9, Alternate trigger mode only] diff --git a/devices/fields/adc/adc3_f1.yaml b/devices/fields/adc/adc3_f1.yaml new file mode 100644 index 000000000..aa50f34d3 --- /dev/null +++ b/devices/fields/adc/adc3_f1.yaml @@ -0,0 +1,19 @@ +CR2: + EXTSEL: + Tim3Cc1: [0, Timer 3 CC1 event] + Tim2Cc3: [1, Timer 2 CC3 event] + Tim1Cc3: [2, Timer 1 CC3 event] + Tim8Cc1: [3, Timer 8 CC1 event] + Tim8Trgo: [4, Timer 8 TRGO event] + Tim5Cc1: [5, Timer 5 CC1 event] + Tim5Cc3: [6, Timer 5 CC3 event] + Swstart: [7, SWSTART] + JEXTSEL: + Tim1Trgo: [0, Timer 1 TRGO event] + Tim1Cc4: [1, Timer 1 CC4 event] + Tim4Cc3: [2, Timer 4 CC3 event] + Tim8Cc2: [3, Timer 8 CC2 event] + Tim8Cc4: [4, Timer 8 CC4 event] + Tim5Trgo: [5, Timer 5 TRGO event] + Tim5Cc4: [6, Timer 5 CC4 event] + Jswstart: [7, JSWSTART] diff --git a/devices/fields/adc/adc_aditf4_v1_1.yaml b/devices/fields/adc/adc_aditf4_v1_1.yaml new file mode 100644 index 000000000..eb5ed82f0 --- /dev/null +++ b/devices/fields/adc/adc_aditf4_v1_1.yaml @@ -0,0 +1,163 @@ +# ADC common as used on F0x0, F0x1, F0x2 and F0x8 + +ISR: + AWD: + _read: + NoEvent: [0, No analog watchdog event occurred] + Event: [1, Analog watchdog event occurred] + _W1C: + Clear: [1, Clear the analog watchdog event flag] + OVR: + _read: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + _W1C: + Clear: [1, Clear the overrun flag] + EOSEQ: + _read: + NotComplete: [0, Conversion sequence is not complete] + Complete: [1, Conversion sequence complete] + _W1C: + Clear: [1, Clear the conversion sequence flag] + EOC: + _read: + NotComplete: [0, Channel conversion is not complete] + Complete: [1, Channel conversion complete] + _W1C: + Clear: [1, Clear the channel conversion flag] + EOSMP: + _read: + NotAtEnd: [0, Not at the end of the samplings phase] + AtEnd: [1, End of sampling phase reached] + _W1C: + Clear: [1, Clear the sampling phase flag] + ADRDY: + _read: + NotReady: [0, ADC not yet ready to start conversion] + Ready: [1, ADC ready to start conversion] + _W1C: + Clear: [1, Clear the ADC ready flag] +IER: + AWDIE: + Disabled: [0, Analog watchdog interrupt disabled] + Enabled: [1, Analog watchdog interrupt enabled] + OVRIE: + Disabled: [0, Overrun interrupt disabled] + Enabled: [1, Overrun interrupt enabled] + EOSEQIE: + Disabled: [0, End of conversion sequence interrupt disabled] + Enabled: [1, End of conversion sequence interrupt enabled] + EOCIE: + Disabled: [0, End of conversion interrupt disabled] + Enabled: [1, End of conversion interrupt enabled] + EOSMPIE: + Disabled: [0, End of sampling interrupt disabled] + Enabled: [1, End of sampling interrupt enabled] + ADRDYIE: + Disabled: [0, ADC ready interrupt disabled] + Enabled: [1, ADC ready interrupt enabled] +CR: + ADCAL: + _read: + NotCalibrating: [0, ADC calibration either not yet performed or completed] + Calibrating: [1, ADC calibration in progress] + _W1S: + StartCalibration: [1, Start the ADC calibration sequence] + ADSTP: + _read: + NotStopping: [0, No stop command active] + Stopping: [1, ADC stopping conversion] + _W1S: + StopConversion: [1, Stop the active conversion] + ADSTART: + _read: + NotActive: [0, No conversion ongoing] + Active: [1, ADC operating and may be converting] + _W1S: + StartConversion: [1, Start the ADC conversion (may be delayed for hardware triggers)] + ADDIS: + _read: + NotDisabling: [0, No disable command active] + Disabling: [1, ADC disabling] + _W1S: + Disable: [1, Disable the ADC] + ADEN: + _read: + Disabled: [0, ADC disabled] + Enabled: [1, ADC enabled] + _W1S: + Enabled: [1, Enable the ADC] +CFGR1: + AWDCH: [0, 18] + AWDEN: + Disabled: [0, Analog watchdog disabled on regular channels] + Enabled: [1, Analog watchdog enabled on regular channels] + AWDSGL: + AllChannels: [0, Analog watchdog enabled on all channels] + SingleChannel: [1, Analog watchdog enabled on a single channel] + DISCEN: + Disabled: [0, Discontinuous mode on regular channels disabled] + Enabled: [1, Discontinuous mode on regular channels enabled] + AUTOFF: + Disabled: [0, Auto-off mode disabled] + Enabled: [1, Auto-off mode enabled] + WAIT: + Disabled: [0, Wait conversion mode off] + Enabled: [1, Wait conversion mode on] + CONT: + Single: [0, Single conversion mode] + Continuous: [1, Continuous conversion mode] + OVRMOD: + Preserved: [0, ADC_DR register is preserved with the old data when an overrun is detected] + Overwritten: [1, ADC_DR register is overwritten with the last conversion result when an overrun is detected] + EXTEN: + Disabled: [0, Trigger detection disabled] + RisingEdge: [1, Trigger detection on the rising edge] + FallingEdge: [2, Trigger detection on the falling edge] + BothEdges: [3, Trigger detection on both the rising and falling edges] + ALIGN: + Right: [0, Right alignment] + Left: [1, Left alignment] + RES: + TwelveBit: [0, 12-bit (14 ADCCLK cycles)] + TenBit: [1, 10-bit (13 ADCCLK cycles)] + EightBit: [2, 8-bit (11 ADCCLK cycles)] + SixBit: [3, 6-bit (9 ADCCLK cycles)] + SCANDIR: + Upward: [0, Upward scan (from CHSEL0 to CHSEL18)] + Backward: [1, Backward scan (from CHSEL18 to CHSEL0)] + DMACFG: + OneShot: [0, DMA one shot mode] + Circular: [1, DMA circular mode] + DMAEN: + Disabled: [0, DMA mode disabled] + Enabled: [1, DMA mode enabled] +CFGR2: + CKMODE: + ADCCLK: [0, Asynchronous clock mode] + PCLK_Div2: [1, Synchronous clock mode (PCLK/2)] + PCLK_Div4: [2, Sychronous clock mode (PCLK/4)] +SMPR: + SMP: + Cycles1_5: [0, 1.5 cycles] + Cycles7_5: [1, 7.5 cycles] + Cycles13_5: [2, 13.5 cycles] + Cycles28_5: [3, 28.5 cycles] + Cycles41_5: [4, 41.5 cycles] + Cycles55_5: [5, 55.5 cycles] + Cycles71_5: [6, 71.5 cycles] + Cycles239_5: [7, 239.5 cycles] +TR: + HT: [0, 4095] + LT: [0, 4095] +CHSELR: + CHSEL*: + NotSelected: [0, Input Channel is not selected for conversion] + Selected: [1, Input Channel is selected for conversion] +CCR: + TSEN: + Disabled: [0, Temperature sensor disabled] + Enabled: [1, Temperature sensor enabled] + VREFEN: + Disabled: [0, V_REFINT channel disabled] + Enabled: [1, V_REFINT channel enabled] diff --git a/devices/fields/adc/adc_aditf4_v1_1_RM0091.yaml b/devices/fields/adc/adc_aditf4_v1_1_RM0091.yaml new file mode 100644 index 000000000..37b1e94fa --- /dev/null +++ b/devices/fields/adc/adc_aditf4_v1_1_RM0091.yaml @@ -0,0 +1,16 @@ +# ADC as used on F0x1, F0x2 and F0x8 + +_include: + - adc_aditf4_v1_1.yaml + +CFGR1: + EXTSEL: + TIM1_TRGO: [0, Timer 1 TRGO Event] + TIM1_CC4: [1, Timer 1 CC4 event] + TIM3_TRGO: [3, Timer 3 TRGO event] + TIM15_TRGO: [4, Timer 15 TRGO event] + TIM2_TRGO: [2, Timer 2 TRGO event] +CCR: + VBATEN: + Disabled: [0, V_BAT channel disabled] + Enabled: [1, V_BAT channel enabled] diff --git a/devices/fields/adc/adc_f1_common.yaml b/devices/fields/adc/adc_f1_common.yaml new file mode 100644 index 000000000..3b266defd --- /dev/null +++ b/devices/fields/adc/adc_f1_common.yaml @@ -0,0 +1,19 @@ +CR2: + EXTSEL: + Tim1Cc1: [0, Timer 1 CC1 event] + Tim1Cc2: [1, Timer 1 CC2 event] + Tim1Cc3: [2, Timer 1 CC3 event] + Tim2Cc2: [3, Timer 2 CC2 event] + Tim3Trgo: [4, Timer 3 TRGO event] + Tim4Cc4: [5, Timer 4 CC4 event] + Exti11: [6, EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)] + Swstart: [7, SWSTART] + JEXTSEL: + Tim1Trgo: [0, Timer 1 TRGO event] + Tim1Cc4: [1, Timer 1 CC4 event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim2Cc1: [3, Timer 2 CC1 event] + Tim3Cc4: [4, Timer 3 CC4 event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti15: [6, EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)] + Jswstart: [7, JSWSTART] diff --git a/devices/fields/adc/adc_f1_f37x.yaml b/devices/fields/adc/adc_f1_f37x.yaml new file mode 100644 index 000000000..113fcc1bb --- /dev/null +++ b/devices/fields/adc/adc_f1_f37x.yaml @@ -0,0 +1,133 @@ +SR: + STRT: + _read: + NotStarted: [0, No regular channel conversion started] + Started: [1, Regular channel conversion has started] + _W0C: + Clear: [0, Clear the Regular channel Start flag] + JSTRT: + _read: + NotStarted: [0, No injected group conversion started] + Started: [1, Injected group conversion has started] + _W0C: + Clear: [0, Clear Injected channel Start flag] + JEOC: + _read: + NotComplete: [0, Conversion is not complete] + Complete: [1, Conversion complete] + _W0C: + Clear: [0, Clear Injected channel end of conversion flag] + EOC: + _read: + NotComplete: [0, Conversion is not complete] + Complete: [1, Conversion complete] + _W0C: + Clear: [0, Clear End of conversion flag] + AWD: + _read: + NoEvent: [0, No analog watchdog event occurred] + Event: [1, Analog watchdog event occurred] + _W0C: + Clear: [0, Clear the analog watchdog event flag] + +CR1: + AWDEN: + Disabled: [0, Analog watchdog disabled on regular channels] + Enabled: [1, Analog watchdog enabled on regular channels] + JAWDEN: + Disabled: [0, Analog watchdog disabled on injected channels] + Enabled: [1, Analog watchdog enabled on injected channels] + DISCNUM: [0, 7] + JDISCEN: + Disabled: [0, Discontinuous mode on injected channels disabled] + Enabled: [1, Discontinuous mode on injected channels enabled] + DISCEN: + Disabled: [0, Discontinuous mode on regular channels disabled] + Enabled: [1, Discontinuous mode on regular channels enabled] + JAUTO: + Disabled: [0, Automatic injected group conversion disabled] + Enabled: [1, Automatic injected group conversion enabled] + AWDSGL: + All: [0, Analog watchdog enabled on all channels] + Single: [1, Analog watchdog enabled on a single channel] + SCAN: + Disabled: [0, Scan mode disabled] + Enabled: [1, Scan mode enabled] + JEOCIE: + Disabled: [0, JEOC interrupt disabled] + Enabled: [1, JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set] + AWDIE: + Disabled: [0, Analog watchdog interrupt disabled] + Enabled: [1, Analog watchdog interrupt enabled] + EOCIE: + Disabled: [0, EOC interrupt disabled] + Enabled: [1, EOC interrupt enabled. An interrupt is generated when the EOC bit is set] + AWDCH: [0, 17] + +CR2: + TSVREFE: + Disabled: [0, Temperature sensor and V_REFINT channel disabled] + Enabled: [1, Temperature sensor and V_REFINT channel enabled] + SWSTART: + _read: + Started: [0, Reset state] + NotStarted: [1, Starting conversion of regular channels] + _write: + Start: [1, Start conversion of regular channels] + JSWSTART: + _read: + Started: [0, Reset state] + NotStarted: [1, Starting conversion of injected channels] + _write: + Start: [1, Start conversion of injected channels] + EXTTRIG: + Disabled: [0, Conversion on external event disabled] + Enabled: [1, Conversion on external event enabled] + JEXTTRIG: + Disabled: [0, Conversion on external event disabled] + Enabled: [1, Conversion on external event enabled] + ALIGN: + Right: [0, Right Alignment] + Left: [1, Left Alignment] + RSTCAL: + _read: + Initialized: [0, Calibration register initialized] + NotInitialized: [1, Initializing calibration register] + _write: + Initialize: [1, Initialize calibration register] + CAL: + _read: + Complete: [0, Calibration completed] + NotComplete: [1, Calibrating] + _write: + Start: [1, Enable calibration] + CONT: + Single: [0, Single conversion mode] + Continuous: [1, Continuous conversion mode] + ADON: + Disabled: [0, Disable ADC conversion/calibration and go to power down mode] + Enabled: [1, Enable ADC and to start conversion] + DMA: + Disabled: [0, DMA mode disabled] + Enabled: [1, DMA mode enabled] + +SMPR?: + SMP*: + Cycles1_5: [0, 1.5 ADC clock cycles] + Cycles7_5: [1, 7.5 ADC clock cycles] + Cycles13_5: [2, 13.5 ADC clock cycles] + Cycles28_5: [3, 28.5 ADC clock cycles] + Cycles41_5: [4, 41.5 ADC clock cycles] + Cycles55_5: [5, 55.5 ADC clock cycles] + Cycles71_5: [6, 71.5 ADC clock cycles] + Cycles239_5: [7, 239.5 ADC clock cycles] +HTR: + HT: [0, 4095] +LTR: + LT: [0, 4095] +"*SQR*": + "*SQ*": [0, 17] +SQR1: + L: [0, 15] +JSQR: + JL: [0, 3] diff --git a/devices/fields/adc/adc_h5.yaml b/devices/fields/adc/adc_h5.yaml new file mode 100644 index 000000000..cdde3a3ad --- /dev/null +++ b/devices/fields/adc/adc_h5.yaml @@ -0,0 +1,13 @@ +# ADC v3 with H5 specific fields + +_include: adc_v3_l4.yaml +CFGR2: + SMPTRIG: + Disabled: [0, Sampling time control trigger mode disabled] + Enabled: [1, Sampling time control trigger mode enabled] + BULB: + Disabled: [0, Bulb sampling mode disabled] + Enabled: [1, Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion] + SWTRIG: + Conversion: [0, Software trigger starts the conversion for sampling time control trigger mode] + Sampling: [1, Software trigger starts the sampling for sampling time control trigger mode] diff --git a/devices/fields/adc/adc_h7_revision_v.yaml b/devices/fields/adc/adc_h7_revision_v.yaml new file mode 100644 index 000000000..5a6924f99 --- /dev/null +++ b/devices/fields/adc/adc_h7_revision_v.yaml @@ -0,0 +1,20 @@ +# ADC features specific to H7 Rev V + +CFGR: + _modify: + RES: + bitWidth: 3 + RES: + SixteenBit: [0, 16-bit resolution] + FourteenBit: [1, 14-bit resolution in legacy mode (not optimized power consumption)] + TwelveBit: [2, 12-bit resolution in legacy mode (not optimized power consumption)] + TenBit: [3, 10-bit resolution] + FourteenBitV: [5, 14-bit resolution] + TwelveBitV: [6, 12-bit resolution] + EightBit: [7, 8-bit resolution] +CR: + "?~BOOST": + LT6_25: [0, "Boost mode used when ADC clock ≤ 6.25 MHz"] + LT12_5: [1, "Boost mode used when 6.25 MHz < ADC clock ≤ 12.5 MHz"] + LT25: [2, "Boost mode used when 12.5 MHz < ADC clock ≤ 25.0 MHz"] + LT50: [3, "Boost mode used when 25.0 MHz < ADC clock ≤ 50.0 MHz"] diff --git a/devices/fields/adc/adc_h7_revision_y.yaml b/devices/fields/adc/adc_h7_revision_y.yaml new file mode 100644 index 000000000..b39f26928 --- /dev/null +++ b/devices/fields/adc/adc_h7_revision_y.yaml @@ -0,0 +1,13 @@ +# ADC features specific to H742/743/753/750 Rev Y + +CFGR: + RES: + SixteenBit: [0, 16-bit resolution] + FourteenBit: [1, 14-bit resolution] + TwelveBit: [2, 12-bit resolution] + TenBit: [3, 10-bit resolution] + EightBit: [4, 8-bit resolution] +CR: + BOOST: + "Off": [0, "Boost mode off. Used when ADC clock < 20MHz"] + "On": [1, "Boost mode on. Used when ADC clock > 20MHz"] diff --git a/devices/fields/adc/adc_l0.yaml b/devices/fields/adc/adc_l0.yaml new file mode 100644 index 000000000..fd37acf7c --- /dev/null +++ b/devices/fields/adc/adc_l0.yaml @@ -0,0 +1,218 @@ +# ADC as used on L0 + +ISR: + EOCAL: + _read: + NotComplete: [0, Calibration is not complete] + Complete: [1, Calibration complete] + _W1C: + Clear: [1, Clear the calibration flag] + AWD: + _read: + NoEvent: [0, No analog watchdog event occurred] + Event: [1, Analog watchdog event occurred] + _W1C: + Clear: [1, Clear the analog watchdog event flag] + OVR: + _read: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + _W1C: + Clear: [1, Clear the overrun flag] + EOS: + _read: + NotComplete: [0, Conversion sequence is not complete] + Complete: [1, Conversion sequence complete] + _W1C: + Clear: [1, Clear the conversion sequence flag] + EOC: + _read: + NotComplete: [0, Channel conversion is not complete] + Complete: [1, Channel conversion complete] + _W1C: + Clear: [1, Clear the channel conversion flag] + EOSMP: + _read: + NotAtEnd: [0, Not at the end of the samplings phase] + AtEnd: [1, End of sampling phase reached] + _W1C: + Clear: [1, Clear the sampling phase flag] + ADRDY: + _read: + NotReady: [0, ADC not yet ready to start conversion] + Ready: [1, ADC ready to start conversion] + _W1C: + Clear: [1, Clear the ADC ready flag] +IER: + EOCALIE: + Disabled: [0, End of calibration interrupt disabled] + Enabled: [1, End of calibration interrupt enabled] + AWDIE: + Disabled: [0, Analog watchdog interrupt disabled] + Enabled: [1, Analog watchdog interrupt enabled] + OVRIE: + Disabled: [0, Overrun interrupt disabled] + Enabled: [1, Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.] + EOSIE: + Disabled: [0, EOS interrupt disabled] + Enabled: [1, EOS interrupt enabled. An interrupt is generated when the EOS bit is set.] + EOCIE: + Disabled: [0, EOC interrupt disabled] + Enabled: [1, EOC interrupt enabled. An interrupt is generated when the EOC bit is set.] + EOSMPIE: + Disabled: [0, EOSMP interrupt disabled] + Enabled: [1, EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.] + ADRDYIE: + Disabled: [0, ADRDY interrupt disabled] + Enabled: [1, ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.] +CR: + ADCAL: + _read: + NotCalibrating: [0, ADC calibration either not yet performed or completed] + Calibrating: [1, ADC calibration in progress] + _W1S: + StartCalibration: [1, Start the ADC calibration sequence] + ADVREGEN: + Disabled: [0, ADC voltage regulator disabled] + Enabled: [1, ADC voltage regulator enabled] + ADSTP: + _read: + NotStopping: [0, No stop command active] + Stopping: [1, ADC stopping conversion] + _W1S: + StopConversion: [1, Stop the active conversion] + ADSTART: + _read: + NotActive: [0, No conversion ongoing] + Active: [1, ADC operating and may be converting] + _W1S: + StartConversion: [1, Start the ADC conversion (may be delayed for hardware triggers)] + ADDIS: + _read: + NotDisabling: [0, No disable command active] + Disabling: [1, ADC disabling] + _W1S: + Disable: [1, Disable the ADC] + ADEN: + _read: + Disabled: [0, ADC disabled] + Enabled: [1, ADC enabled] + _W1S: + Enabled: [1, Enable the ADC] +CFGR1: + AWDCH: [0, 18] + AWDEN: + Disabled: [0, Analog watchdog disabled] + Enabled: [1, Analog watchdog enabled] + AWDSGL: + AllChannels: [0, Analog watchdog enabled on all channels] + SingleChannel: [1, Analog watchdog enabled on a single channel] + DISCEN: + Disabled: [0, Discontinuous mode disabled] + Enabled: [1, Discontinuous mode enabled] + AUTOFF: + Disabled: [0, Auto-off mode disabled] + Enabled: [1, Auto-off mode enabled] + WAIT: + Disabled: [0, Wait conversion mode off] + Enabled: [1, Wait conversion mode on] + CONT: + Single: [0, Single conversion mode] + Continuous: [1, Continuous conversion mode] + OVRMOD: + Preserve: [0, ADC_DR register is preserved with the old data when an overrun is detected] + Overwrite: [1, ADC_DR register is overwritten with the last conversion result when an overrun is detected] + EXTEN: + Disabled: [0, Hardware trigger detection disabled] + RisingEdge: [1, Hardware trigger detection on the rising edge] + FallingEdge: [2, Hardware trigger detection on the falling edge] + BothEdges: [3, Hardware trigger detection on both the rising and falling edges] + EXTSEL: + TIM6_TRGO: [0, Timer 6 TRGO event] + TIM21_CH2: [1, Timer 21 CH2 event] + TIM2_TRGO: [2, Timer 2 TRGO event] + TIM2_CH4: [3, Timer 2 CH4 event] + TIM22_TRGO: [4, "Timer 22 TRGO, Timer 21 TRGO event"] + TIM2_CH3: [5, Timer 2 CH3 event] + TIM3_TRGO: [6, Timer 3 TRGO event] + EXTI_LINE11: [7, EXTI line 11 event] + ALIGN: + Right: [0, Right alignment] + Left: [1, Left alignment] + RES: + TwelveBit: [0, 12 bits] + TenBit: [1, 10 bits] + EightBit: [2, 8 bits] + SixBit: [3, 6 bits] + SCANDIR: + Upward: [0, Upward scan (from CHSEL0 to CHSEL18)] + Backward: [1, Backward scan (from CHSEL18 to CHSEL0)] + DMACFG: + OneShot: [0, DMA one shot mode selected] + Circular: [1, DMA circular mode selected] + DMAEN: + Disabled: [0, DMA disabled] + Enabled: [1, DMA enabled] +CFGR2: + CKMODE: + ADCLK: [0, ADCCLK (Asynchronous clock mode)] + PCLK_Div2: [1, PCLK/2 (Synchronous clock mode)] + PCLK_Div4: [2, PCLK/4 (Synchronous clock mode)] + PCLK: [3, PCLK (Synchronous clock mode)] + TOVS: + TriggerAll: [0, All oversampled conversions for a channel are done consecutively after a trigger] + TriggerEach: [1, Each oversampled conversion for a channel needs a trigger] + OVSS: [0, 8] + OVSR: + Mul2: [0, 2x] + Mul4: [1, 4x] + Mul8: [2, 8x] + Mul16: [3, 16x] + Mul32: [4, 32x] + Mul64: [5, 64x] + Mul128: [6, 128x] + Mul256: [7, 256x] + OVSE: + Disabled: [0, Oversampler disabled] + Enabled: [1, Oversampler enabled] +SMPR: + SMP: + Cycles1_5: [0, 1.5 ADC clock cycles] + Cycles3_5: [1, 3.5 ADC clock cycles] + Cycles7_5: [2, 7.5 ADC clock cycles] + Cycles12_5: [3, 12.5 ADC clock cycles] + Cycles19_5: [4, 19.5 ADC clock cycles] + Cycles39_5: [5, 39.5 ADC clock cycles] + Cycles79_5: [6, 79.5 ADC clock cycles] + Cycles160_5: [7, 160.5 ADC clock cycles] +TR: + HT: [0, 2047] + LT: [0, 2047] +CHSELR: + CHSEL*: + NotSelected: [0, Input Channel is not selected for conversion] + Selected: [1, Input Channel is selected for conversion] +DR: + DATA: [0, 65535] +CALFACT: + CALFACT: [0, 127] +CCR: + LFMEN: + Disabled: [0, Low Frequency Mode disabled] + Enabled: [1, Low Frequency Mode enabled] + "TSEN,VREFEN": + Disabled: [0, The selected ADC channel disabled] + Enabled: [1, The selected ADC channel enabled] + PRESC: + Div1: [0, Input ADC clock not divided] + Div2: [1, Input ADC clock divided by 2] + Div4: [2, Input ADC clock divided by 4] + Div6: [3, Input ADC clock divided by 6] + Div8: [4, Input ADC clock divided by 8] + Div10: [5, Input ADC clock divided by 10] + Div12: [6, Input ADC clock divided by 12] + Div16: [7, Input ADC clock divided by 16] + Div32: [8, Input ADC clock divided by 32] + Div64: [9, Input ADC clock divided by 64] + Div128: [10, Input ADC clock divided by 128] + Div256: [11, Input ADC clock divided by 256] diff --git a/devices/fields/adc/adc_u5.yaml b/devices/fields/adc/adc_u5.yaml new file mode 100644 index 000000000..9c3d36cb3 --- /dev/null +++ b/devices/fields/adc/adc_u5.yaml @@ -0,0 +1,140 @@ +# ADC as used on U5 + +ISR: + LDORDY: + _read: + Disabled: [0, ADC voltage regulator disabled] + Enabled: [1, ADC voltage regulator enabled] + AWD?: + _read: + NoEvent: + [0, No analog watchdog x event occurred (or the flag event was already acknowledged and cleared by software)] + Event: [1, Analog watchdog x event occurred] + _write: + Clear: [1, Clear the analog watchdog x event flag] + OVR: + _read: + NoOverrun: [0, No overrun occurred (or the flag event was already acknowledged and cleared by software)] + Overrun: [1, Overrun has occurred] + _write: + Clear: [1, Clear the overrun flag] + EOS: + _read: + NotComplete: + [ + 0, + Regular conversions sequence not complete (or the flag event was already acknowledged and cleared by software), + ] + Complete: [1, Regular conversions sequence complete] + _write: + Clear: [1, Clear the regular conversion sequence flag] + EOC: + _read: + NotComplete: + [ + 0, + Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software), + ] + Complete: [1, Regular channel conversion complete] + _write: + Clear: [1, Clear the regular channel conversion flag] + EOSMP: + _read: + NotAtEnd: + [0, Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)] + AtEnd: [1, End of sampling phase reached] + _write: + Clear: [1, Clear the sampling phase flag] + ADRDY: + _read: + NotReady: + [0, ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)] + Ready: [1, ADC is ready to start conversion] + _write: + Clear: [1, Clear the ADC ready flag] +IER: + AWD?IE: + Disabled: [0, Analog watchdog x interrupt disabled] + Enabled: [1, Analog watchdog x interrupt enabled] + OVRIE: + Disabled: [0, Overrun interrupt disabled] + Enabled: [1, Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.] + EOSIE: + Disabled: [0, EOS interrupt disabled] + Enabled: [1, EOS interrupt enabled. An interrupt is generated when the EOS bit is set.] + EOCIE: + Disabled: [0, EOC interrupt disabled] + Enabled: [1, EOC interrupt enabled. An interrupt is generated when the EOC bit is set.] + EOSMPIE: + Disabled: [0, EOSMP interrupt disabled] + Enabled: [1, EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.] + ADRDYIE: + Disabled: [0, ADRDY interrupt disabled] + Enabled: [1, ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.] +CR: + ADCAL: + _read: + NotCalibrating: [0, Calibration complete] + Calibrating: [1, Calibration in progress] + _write: + StartCalibration: [1, Calibrate the ADC] + ADVREGEN: + Disabled: [0, ADC voltage regulator disabled] + Enabled: [1, ADC voltage regulator enabled] + ADSTP: + _read: + NotStopping: [0, No ADC stop regular conversion command ongoing] + Stopping: [1, ADSTP command is in progress] + _write: + StopConversion: [1, Stop regular conversions ongoing] + ADSTART: + _read: + NotActive: [0, No ADC regular conversion is ongoing] + Active: [1, ADC is operating and eventually converting a regular channel] + _write: + Start: [1, Start regular conversions] + ADDIS: + _read: + NotOngoing: [0, No ADDIS command ongoing] + InProgress: [1, An ADDIS command is in progress] + _write: + Disable: [1, Disable the ADC] + ADEN: + _read: + Disabled: [0, ADC is disabled] + Enabled: [1, ADC is enabled] + _write: + Enabled: [1, Enable the ADC] +CFGR1: + AWD1CH: [0, 19] + AWD1EN: + Disabled: [0, Analog watchdog 1 disabled on regular channels] + Enabled: [1, Analog watchdog 1 enabled on regular channels] + AWD1SGL: + AllChannels: [0, Analog watchdog 1 enabled on all channels] + SingleChannel: [1, Analog watchdog 1 enabled on a single channel] + DISCEN: + Disabled: [0, Discontinuous mode for regular channels disabled] + Enabled: [1, Discontinuous mode for regular channels enabled] + CONT: + Single: [0, Single conversion mode] + Continuous: [1, Continuous conversion mode] + OVRMOD: + Preserve: [0, ADC_DR register is preserved with the old data when an overrun is detected] + Overwrite: [1, ADC_DR register is overwritten with the last conversion result when an overrun is detected] + EXTEN: + Disabled: [0, Hardware trigger detection disabled (conversions can be launched by software)] + RisingEdge: [1, Hardware trigger detection on the rising edge] + FallingEdge: [2, Hardware trigger detection on the falling edge] + BothEdges: [3, Hardware trigger detection on both the rising and falling edges] +CFGR2: + LFTRIG: + Disabled: [0, Low-frequency trigger mode disabled] + Enabled: [1, Low-frequency trigger mode enabled] + TROVS,TOVS: + Automatic: [0, All oversampled conversions for a channel are done consecutively following a trigger] + Triggered: [1, Each oversampled conversion for a channel needs a new trigger] +AWD?CR: + AWD?CH*: + Disabled: [0, ADC analog input channel x is not monitored by AWDy] + Enabled: [1, ADC analog input channel x is monitored by AWDy] diff --git a/devices/fields/adc/adc_u5_12.yaml b/devices/fields/adc/adc_u5_12.yaml new file mode 100644 index 000000000..5ae99b0d3 --- /dev/null +++ b/devices/fields/adc/adc_u5_12.yaml @@ -0,0 +1,255 @@ +# ADC as used on U5 + +ISR: + JEOS: + _read: + NotComplete: + [ + 0, + Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software), + ] + Complete: [1, Injected conversions sequence complete] + _write: + Clear: [1, Clear the injected conversion sequence flag] + JEOC: + _read: + NotComplete: + [ + 0, + Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software), + ] + Complete: [1, Injected channel conversion complete] + _write: + Clear: [1, Clear the injected channel conversion flag] +IER: + JEOSIE: + Disabled: [0, JEOS interrupt disabled] + Enabled: [1, JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.] + JEOCIE: + Disabled: [0, JEOC interrupt disable] + Enabled: [1, JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.] +CR: + DEEPPWD: + Disabled: [0, ADC not in deep-power down] + Enabled: [1, ADC in deep-power down] + CALINDEX: + OffsetCalFactor: [0, Offset calibration factor] + CalFactor1: [1, Calibration factor 1] + CalFactor2: [2, Calibration factor 2] + CalFactor3: [3, Calibration factor 3] + CalFactor4: [4, Calibration factor 4] + CalFactor5: [5, Calibration factor 5] + CalFactor6: [6, Calibration factor 6] + CalFactor7: [7, Calibration factor 7 and (write access only) internal offset] + InternalOffset: [8, Internal offset (read access only)] + CalibrationMode: [9, Calibration mode selection] + ADCALLIN: + Disabled: [0, Writing ADCAL launches a calibration without the linearity calibration] + Enabled: [1, Writing ADCAL launches a calibration with he linearity calibration] + JADSTP: + _read: + NotStopped: [0, No ADC stop injected conversion command ongoing] + Stopped: [1, ADSTP command is in progress] + _write: + Stop: [1, Stop injected conversions ongoing] + JADSTART: + _read: + NotActive: [0, No ADC injected conversion is ongoing] + Active: [1, ADC is operating and eventually converting an injected channel] + _write: + Start: [1, Start injected conversions] +CFGR1: + JAUTO: + Disabled: [0, Automatic injected group conversion disabled] + Enabled: [1, Automatic injected group conversion enabled] + JAWD1EN: + Disabled: [0, Analog watchdog 1 disabled on injected channels] + Enabled: [1, Analog watchdog 1 enabled on injected channels] + JDISCEN: + Disabled: [0, Discontinuous mode on injected channels disabled] + Enabled: [1, Discontinuous mode on injected channels enabled] + DISCNUM: + n1: [0, 1 channel] + n2: [1, 2 channels] + n3: [2, 3 channels] + n4: [3, 4 channels] + n5: [4, 5 channels] + n6: [5, 6 channels] + n7: [6, 7 channels] + n8: [7, 8 channels] + AUTDLY: + Disabled: [0, Auto-delayed conversion mode off] + Enabled: [1, Auto-delayed conversion mode on] + DMNGT: + DR: [0, Store output data in DR only] + DMA_OneShot: [1, DMA One Shot Mode selected] + DFSDM: [2, DFSDM mode selected] + DMA_Circular: [3, DMA Circular Mode selected] + EXTSEL: + TIM1_OC1: [0, tim1_oc1] + TIM1_OC2: [1, tim1_oc2] + TIM1_OC3: [2, tim1_oc3] + TIM2_OC2: [3, tim2_oc2] + TIM3_TRGO: [4, tim3_trgo] + TIM4_OC4: [5, tim4_oc4] + EXTI11: [6, exti11] + TIM8_TRGO: [7, tim8_trgo] + TIM8_TRGO2: [8, tim8_trgo2] + TIM1_TRGO: [9, tim1_trgo] + TIM1_TRGO2: [10, tim1_trgo2] + TIM2_TRGO: [11, tim2_trgo] + TIM4_TRGO: [12, tim4_trgo] + TIM6_TRGO: [13, tim6_trgo] + TIM15_TRGO: [14, tim15_trgo] + TIM3_OC4: [15, tim3_oc4] + EXTI15: [16, exti15] + LPTIM1_CH1: [18, lptim1_ch1] + LPTIM2_CH1: [19, lptim2_ch1] + LPTIM3_CH1: [20, lptim3_ch1] + LPTIM4_OUT: [21, lptim4_out] + RES: + FourteenBit: [0, 14 bits] + TwelveBit: [1, 12 bits] + TenBit: [2, 10 bits] + EightBit: [3, 8 bits] +CFGR2: + LSHIFT: [0, 15] + OSR: [0, 1023] + SMPTRIG: + Disabled: [0, Sampling time control trigger mode disabled] + Enabled: [1, Sampling time control trigger mode enabled] + SWTRIG: + Disabled: [0, Software trigger starts the conversion for sampling time control trigger mode] + Enabled: [1, Software trigger starts the sampling for sampling time control trigger mode] + BULB: + Disabled: [0, Bulb sampling mode disabled] + Enabled: [1, Bulb sampling mode enabled. The sampling period starts just after the previous end of the conversion.] + ROVSM: + Continued: + [ + 0, + "When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)", + ] + Resumed: + [ + 1, + "When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)", + ] + OVSS: [0, 11] + JOVSE: + Disabled: [0, Injected oversampling disabled] + Enabled: [1, Injected oversampling enabled] + ROVSE: + Disabled: [0, Regular oversampling disabled] + Enabled: [1, Regular oversampling enabled] +SMPR?: + SMP*: + Cycles5: [0, 5 ADC clock cycles] + Cycles6: [1, 6 ADC clock cycles] + Cycles12: [2, 12 ADC clock cycles] + Cycles20: [3, 20 ADC clock cycles] + Cycles36: [4, 36 ADC clock cycles] + Cycles68: [5, 68 ADC clock cycles] + Cycles391: [6, 391 ADC clock cycles] + Cycles814: [7, 814 ADC clock cycles] +PCSEL: + PCSEL*: + NotPreselected: + [0, "Input channel x is not preselected for conversion, the ADC conversion of this channel shows a wrong result."] + Preselected: [1, Input channel x is preselected for conversion] +SQR?,JSQR: + SQ*,JSQ*: [0, 31] +SQR1: + L: [0, 15] +JSQR: + JEXTEN: + Disabled: [0, Hardware trigger detection disabled (conversions can be launched by software)] + RisingEdge: [1, Hardware trigger detection on the rising edge] + FallingEdge: [2, Hardware trigger detection on the falling edge] + BothEdges: [3, Hardware trigger detection on both the rising and falling edges] + JEXTSEL: + TIM1_TRGO: [0, tim1_trgo] + TIM1_OC4: [1, tim1_oc4] + TIM2_TRGO: [2, tim2_trgo] + TIM2_OC1: [3, tim2_oc1] + TIM3_OC4: [4, tim3_oc4] + TIM4_TRGO: [5, tim4_trgo] + EXTI15: [6, exti15] + TIM8_OC4: [7, tim8_oc4] + TIM1_TRGO2: [8, tim1_trgo2] + TIM8_TRGO: [9, tim8_trgo] + TIM8_TRGO2: [10, tim8_trgo2] + TIM3_OC3: [11, tim3_oc3] + TIM3_TRGO: [12, tim3_trgo] + TIM3_OC1: [13, tim3_oc1] + TIM6_TRGO: [14, tim6_trgo] + TIM15_TRGO: [15, tim15_trgo] + LPTIM1_CH2: [16, lptim1_ch2] + LPTIM2_CH2: [17, lptim2_ch2] + LPTIM3_CH1: [18, lptim3_ch1] + LPTIM4_OUT1: [19, lptim4_out1] + JL: [0, 3] +OFR?: + OFFSET_CH: [0, 0x1F] + SSAT: + Disabled: + [ + 0, + Offset is subtracted maintaining data integrity and extending converted data size (9-bit and 15-bit signed format), + ] + Enabled: [1, Offset is subtracted and result is saturated to maintain converted data size] + USAT: + Disabled: [0, Offset is subtracted maintaining data integrity and keeping converted data size] + Enabled: [1, Offset is subtracted and result is saturated to maintain converted data size] + POSOFF: + Negative: [0, Negative offset] + Positive: [1, Positive offset] + OFFSET: [0, 0xFFFFFF] +GCOMP: + GCOMP: + Disabled: [0, Regular ADC operating mode] + Enabled: [1, Gain compensation enabled and applied to all channels] + GCOMPCOEFF: [0, 0x3FFF] +JDR?: + JDATA: [0, 0xFFFFFFFF] +LTR?: + LTR?: [0, 0x1FFFFFF] +HTR?: + HTR?: [0, 0x1FFFFFF] +HTR1: + AWDFILT1: + NoFiltering: [0, No filtering] + Detections2: [1, Two consecutive detections generates an AWDx flag or an interrupt] + Detections3: [2, Three consecutive detections generates an AWDx flag or an interrupt] + Detections4: [3, Four consecutive detections generates an AWDx flag or an interrupt] + Detections5: [4, Five consecutive detections generates an AWDx flag or an interrupt] + Detections6: [5, Six consecutive detections generates an AWDx flag or an interrupt] + Detections7: [6, Seven consecutive detections generates an AWDx flag or an interrupt] + Detections8: [7, Eight consecutive detections generates an AWDx flag or an interrupt] +DIFSEL: + DIFSEL*: + SingleEnded: [0, ADC analog input channel x is configured in single-ended mode] + Differential: [1, ADC analog input channel x is configured in differential mode] +CALFACT: + CAPTURE_COEF: + Disabled: [0, Calibration factor not captured] + Enabled: + [ + 1, + "Calibration factor available in CALFACT[31:0] bits, the calibration factor index being defined by CALINDEX[3:0] bits", + ] + LATCH_COEF: + NoEffect: [0, No effect] + Latch: + [ + 1, + "Calibration factor latched in the analog block on LATCH_COEF bit transition from 0 to 1. Prior to latching the calibration factor, CALFACT[31:0] bits must be programmed with the content of CALINDEX[3:0] bits.", + ] + VALIDITY: + _read: + InProgress: [0, Operation still in progress] + Complete: [1, Operation complete] + I_APB_DATA: [0, 0xFF] + I_APB_ADDR: [0, 0xFF] +CALFACT2: + CALFACT: [0, 0xFFFFFFFF] diff --git a/devices/fields/adc/adc_u5_4.yaml b/devices/fields/adc/adc_u5_4.yaml new file mode 100644 index 000000000..fc6e1dd71 --- /dev/null +++ b/devices/fields/adc/adc_u5_4.yaml @@ -0,0 +1,113 @@ +# ADC as used on U5 + +ISR: + EOCAL: + _read: + NotComplete: [0, Calibration is not complete] + Complete: [1, Calibration is complete] + _write: + Clear: [1, Clear the end of calibration flag] +IER: + LDORDYIE: + Disabled: [0, LDO ready interrupt disabled] + Enabled: [1, LDO ready interrupt enabled. An interrupt is generated when the LDO output is ready.] + EOCALIE: + Disabled: [0, End of calibration interrupt disabled] + Enabled: [1, End of calibration interrupt enabled] +CFGR1: + CHSELRMOD: + BitPerInput: [0, Each bit of the ADC_CHSELR register enables an input] + Sequence: [1, ADC_CHSELR register is able to sequence up to 8 channels] + WAIT: + Disabled: [0, Wait conversion mode off] + Enabled: [1, Wait conversion mode on] + EXTSEL: + TIM1_TRGO2: [0, tim1_trgo2] + TIM1_OC4: [1, tim1_oc4] + TIM2_TRGO: [2, tim2_trgo] + TIM15_TRGO: [3, tim15_trgo] + TIM6_TRGO: [4, tim6_trgo] + LPTIM1_CH1: [5, lptim1_ch1] + LPTIM3_CH2: [6, lptim3_ch2] + EXTI15: [7, exti15] + ALIGN: + Right: [0, Right alignment] + Left: [1, Left alignment] + SCANDIR: + Upward: [0, Upward scan sequence (from CHSEL0 to CHSEL23)] + Downward: [1, Downward scan sequence (from CHSEL23 to CHSEL0)] + RES: + TwelveBit: [0, 12 bits] + TenBit: [1, 10 bits] + EightBit: [2, 8 bits] + SixBit: [3, 6 bits] + DMACFG: + OneShot: [0, One-shot mode selected] + Circular: [1, Circular mode selected] + DMAEN: + Disabled: [0, DMA disabled] + Enabled: [1, DMA enabled] +CFGR2: + OVSS: [0, 8] + OVSR: [0, 7] + OVSE: + Disabled: [0, Oversampler disabled] + Enabled: [1, Oversampler enabled] +SMPR: + SMPSEL*: + SMP1: [0, Sampling time of channel x uses the setting of SMP1 register.] + SMP2: [1, Sampling time of channel x uses the setting of SMP2 register.] + SMP1,SMP2: + Cycles1_5: [0, 1.5 ADC clock cycles] + Cycles3_5: [1, 3.5 ADC clock cycles] + Cycles7_5: [2, 7.5 ADC clock cycles] + Cycles12_5: [3, 12.5 ADC clock cycles] + Cycles19_5: [4, 19.5 ADC clock cycles] + Cycles39_5: [5, 39.5 ADC clock cycles] + Cycles79_5: [6, 79.5 ADC clock cycles] + Cycles814_5: [7, 814.5 ADC clock cycles] +AWD?TR: + HT?: [0, 0xFFF] + LT?: [0, 0xFFF] +CHSELR0: + _split: [CHSEL] + CHSEL*: + Disabled: [0, Input channel x is not selected for conversion] + Enabled: [1, Input channel x is selected for conversion] +CHSELR1: + SQ*: + Channel0: [0, CH0] + Channel1: [1, CH1] + Channel2: [2, CH2] + Channel3: [3, CH3] + Channel4: [4, CH4] + Channel5: [5, CH5] + Channel6: [6, CH6] + Channel7: [7, CH7] + Channel8: [8, CH8] + Channel9: [9, CH9] + Channel10: [10, CH10] + Channel11: [11, CH11] + Channel12: [12, CH12] + Channel13: [13, CH13] + Channel14: [14, CH14] + NoChannel: [15, No channel selected (End of sequence)] +PWRR: + VREFSECSMP: + Disabled: [0, "VREF+ second sample disabled"] + Enabled: [1, "VREF+ second sample enabled"] + VREFPROT: + Disabled: [0, "VREF+ protection disabled"] + Enabled: [1, "VREF+ protection enabled"] + DPD: + Disabled: [0, Deep-power-down mode disabled] + Enabled: [1, Deep-power-down mode enabled] + AUTOFF: + Disabled: [0, Auto-off mode disabled] + Enabled: [1, Auto-off mode enabled] +CALFACT: + CALFACT: [0, 0x7F] +OR: + CHN21SEL: + Out1: [0, dac1_out1 selected] + Out2: [1, dac1_out2 selected] diff --git a/devices/fields/adc/adc_u5_common.yaml b/devices/fields/adc/adc_u5_common.yaml new file mode 100644 index 000000000..09175f77c --- /dev/null +++ b/devices/fields/adc/adc_u5_common.yaml @@ -0,0 +1,25 @@ +# ADC as used on U5 + +CCR: + VBATEN: + Disabled: [0, VBAT channel disabled] + Enabled: [1, VBAT channel enabled] + VSENSESEL: + Disabled: [0, Temperature sensor channel disabled] + Enabled: [1, Temperature sensor channel enabled] + VREFEN: + Disabled: [0, VREFINT channel disabled] + Enabled: [1, VREFINT channel enabled] + PRESC: + Div1: [0, Input ADC clock not divided] + Div2: [1, Input ADC clock divided by 2] + Div4: [2, Input ADC clock divided by 4] + Div6: [3, Input ADC clock divided by 6] + Div8: [4, Input ADC clock divided by 8] + Div10: [5, Input ADC clock divided by 10] + Div12: [6, Input ADC clock divided by 12] + Div16: [7, Input ADC clock divided by 16] + Div32: [8, Input ADC clock divided by 32] + Div64: [9, Input ADC clock divided by 64] + Div128: [10, Input ADC clock divided by 128] + Div256: [11, Input ADC clock divided by 256] diff --git a/devices/fields/adc/adc_u5_dual.yaml b/devices/fields/adc/adc_u5_dual.yaml new file mode 100644 index 000000000..54fa085bc --- /dev/null +++ b/devices/fields/adc/adc_u5_dual.yaml @@ -0,0 +1,17 @@ +# only on U59x, U5Ax, U5Fx, U5Gx + +CCR: + DAMDF: + NoPacking: [0, Dual ADC mode without data packing] + Format32_to_10: [2, Data formatting mode for 32 down to 10-bit resolution] + Format8: [3, Data formatting mode for 8-bit resolution] + DELAY: [0, 0xF] + DUAL: + Independent: [0, Independent mode] + RegularSimultaneousInjectedSimultaneous: [1, "Combined regular simultaneous + injected simultaneous mode"] + RegularSimultaneousAlternateTrigger: [2, "Combined regular simultaneous + alternate trigger mode"] + InterleavedInjectedSimultaneous: [3, "Combined interleaved mode + injected simultaneous mode"] + InjectedSimultaneous: [5, Injected simultaneous mode only] + RegularSimultaneous: [6, Regular simultaneous mode only] + Interleaved: [7, Interleaved mode only] + AlternateTrigger: [9, Alternate trigger mode only] diff --git a/devices/fields/adc/adc_v2.yaml b/devices/fields/adc/adc_v2.yaml new file mode 100644 index 000000000..b879c081b --- /dev/null +++ b/devices/fields/adc/adc_v2.yaml @@ -0,0 +1,137 @@ +# ADC as used on F2, F4 and F7 + +SR: + OVR: + _read: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + _W0C: + Clear: [0, Clear flag] + STRT: + _read: + NotStarted: [0, No regular channel conversion started] + Started: [1, Regular channel conversion has started] + _W0C: + Clear: [0, Clear flag] + JSTRT: + _read: + NotStarted: [0, No injected channel conversion started] + Started: [1, Injected channel conversion has started] + _W0C: + Clear: [0, Clear flag] + JEOC: + _read: + NotComplete: [0, Conversion is not complete] + Complete: [1, Conversion complete] + _W0C: + Clear: [0, Clear flag] + EOC: + _read: + NotComplete: [0, Conversion is not complete] + Complete: [1, Conversion complete] + _W0C: + Clear: [0, Clear flag] + AWD: + _read: + NoEvent: [0, No analog watchdog event occurred] + Event: [1, Analog watchdog event occurred] + _W0C: + Clear: [0, Clear flag] +CR1: + OVRIE: + Disabled: [0, Overrun interrupt disabled] + Enabled: [1, Overrun interrupt enabled] + RES: + TwelveBit: [0, 12-bit (15 ADCCLK cycles)] + TenBit: [1, 10-bit (13 ADCCLK cycles)] + EightBit: [2, 8-bit (11 ADCCLK cycles)] + SixBit: [3, 6-bit (9 ADCCLK cycles)] + AWDEN: + Disabled: [0, Analog watchdog disabled on regular channels] + Enabled: [1, Analog watchdog enabled on regular channels] + JAWDEN: + Disabled: [0, Analog watchdog disabled on injected channels] + Enabled: [1, Analog watchdog enabled on injected channels] + DISCNUM: [0, 7] + JDISCEN: + Disabled: [0, Discontinuous mode on injected channels disabled] + Enabled: [1, Discontinuous mode on injected channels enabled] + DISCEN: + Disabled: [0, Discontinuous mode on regular channels disabled] + Enabled: [1, Discontinuous mode on regular channels enabled] + JAUTO: + Disabled: [0, Automatic injected group conversion disabled] + Enabled: [1, Automatic injected group conversion enabled] + AWDSGL: + AllChannels: [0, Analog watchdog enabled on all channels] + SingleChannel: [1, Analog watchdog enabled on a single channel] + SCAN: + Disabled: [0, Scan mode disabled] + Enabled: [1, Scan mode enabled] + JEOCIE: + Disabled: [0, JEOC interrupt disabled] + Enabled: [1, JEOC interrupt enabled] + AWDIE: + Disabled: [0, Analogue watchdog interrupt disabled] + Enabled: [1, Analogue watchdog interrupt enabled] + EOCIE: + Disabled: [0, EOC interrupt disabled] + Enabled: [1, EOC interrupt enabled] + AWDCH: [0, 18] +CR2: + SWSTART: + _write: + Start: [1, Starts conversion of regular channels] + EXTEN: + Disabled: [0, Trigger detection disabled] + RisingEdge: [1, Trigger detection on the rising edge] + FallingEdge: [2, Trigger detection on the falling edge] + BothEdges: [3, Trigger detection on both the rising and falling edges] + # xEXTSEL is now handled in the adc_v2_extsel_x.yaml + JSWSTART: + _write: + Start: [1, Starts conversion of injected channels] + JEXTEN: + Disabled: [0, Trigger detection disabled] + RisingEdge: [1, Trigger detection on the rising edge] + FallingEdge: [2, Trigger detection on the falling edge] + BothEdges: [3, Trigger detection on both the rising and falling edges] + ALIGN: + Right: [0, Right alignment] + Left: [1, Left alignment] + EOCS: + EachSequence: [0, The EOC bit is set at the end of each sequence of regular conversions] + EachConversion: [1, The EOC bit is set at the end of each regular conversion] + DDS: + Single: [0, No new DMA request is issued after the last transfer] + Continuous: [1, "DMA requests are issued as long as data are converted and DMA=1"] + DMA: + Disabled: [0, DMA mode disabled] + Enabled: [1, DMA mode enabled] + CONT: + Single: [0, Single conversion mode] + Continuous: [1, Continuous conversion mode] + ADON: + Disabled: [0, Disable ADC conversion and go to power down mode] + Enabled: [1, Enable ADC] +SMPR?: + SMP*: + Cycles3: [0, 3 cycles] + Cycles15: [1, 15 cycles] + Cycles28: [2, 28 cycles] + Cycles56: [3, 56 cycles] + Cycles84: [4, 84 cycles] + Cycles112: [5, 112 cycles] + Cycles144: [6, 144 cycles] + Cycles480: [7, 480 cycles] +HTR: + HT: [0, 4095] +LTR: + LT: [0, 4095] +SQR1: + L: [0, 15] +SQR?: + SQ*: [0, 18] +JSQR: + JL: [0, 3] + JSQ?: [0, 18] diff --git a/devices/fields/adc/adc_v2/adc_v2_extsel_a.yaml b/devices/fields/adc/adc_v2/adc_v2_extsel_a.yaml new file mode 100644 index 000000000..c23357604 --- /dev/null +++ b/devices/fields/adc/adc_v2/adc_v2_extsel_a.yaml @@ -0,0 +1,17 @@ +# As specified by the STM32F410 + +CR2: + EXTSEL: + TIM1CC1: [0, Timer 1 CC1 event] + TIM1CC2: [1, Timer 1 CC2 event] + TIM1CC3: [2, Timer 1 CC3 event] + TIM5CC1: [10, Timer 5 CC1 event] + TIM5CC2: [11, Timer 5 CC2 event] + TIM5CC3: [12, Timer 5 CC3 event] + EXTI11: [15, EXTI line 11] + JEXTSEL: + TIM1CC4: [0, Timer 1 CC4 event] + TIM1TRGO: [1, Timer 1 TRGO event] + TIM5CC4: [10, Timer 5 CC4 event] + TIM5TRGO: [11, Timer 5 TRGO event] + EXTI15: [15, EXTI line 15] diff --git a/devices/fields/adc/adc_v2/adc_v2_extsel_b.yaml b/devices/fields/adc/adc_v2/adc_v2_extsel_b.yaml new file mode 100644 index 000000000..d67e6a224 --- /dev/null +++ b/devices/fields/adc/adc_v2/adc_v2_extsel_b.yaml @@ -0,0 +1,30 @@ +CR2: + EXTSEL: + TIM1CC1: [0, Timer 1 CC1 event] + TIM1CC2: [1, Timer 1 CC2 event] + TIM1CC3: [2, Timer 1 CC3 event] + TIM2CC2: [3, Timer 2 CC2 event] + TIM2CC3: [4, Timer 2 CC3 event] + TIM2CC4: [5, Timer 2 CC4 event] + TIM2TRGO: [6, Timer 2 TRGO event] + TIM3CC1: [7, Timer 3 CC1 event] + TIM3TRGO: [8, Timer 3 TRGO event] + TIM4CC4: [9, Timer 4 CC4 event] + TIM5CC1: [10, Timer 5 CC1 event] + TIM5CC2: [11, Timer 5 CC2 event] + TIM5CC3: [12, Timer 5 CC3 event] + EXTI11: [15, EXTI line 11] + JEXTSEL: + TIM1CC4: [0, Timer 1 CC4 event] + TIM1TRGO: [1, Timer 1 TRGO event] + TIM2CC1: [2, Timer 2 CC1 event] + TIM2TRGO: [3, Timer 2 TRGO event] + TIM3CC2: [4, Timer 3 CC2 event] + TIM3CC4: [5, Timer 3 CC4 event] + TIM4CC1: [6, Timer 4 CC1 event] + TIM4CC2: [7, Timer 4 CC2 event] + TIM4CC3: [8, Timer 4 CC3 event] + TIM4TRGO: [9, Timer 4 TRGO event] + TIM5CC4: [10, Timer 5 CC4 event] + TIM5TRGO: [11, Timer 5 TRGO event] + EXTI15: [15, EXTI line 15] diff --git a/devices/fields/adc/adc_v2/adc_v2_extsel_c.yaml b/devices/fields/adc/adc_v2/adc_v2_extsel_c.yaml new file mode 100644 index 000000000..b7d4791a6 --- /dev/null +++ b/devices/fields/adc/adc_v2/adc_v2_extsel_c.yaml @@ -0,0 +1,35 @@ +CR2: + EXTSEL: + TIM1CC1: [0, Timer 1 CC1 event] + TIM1CC2: [1, Timer 1 CC2 event] + TIM1CC3: [2, Timer 1 CC3 event] + TIM2CC2: [3, Timer 2 CC2 event] + TIM2CC3: [4, Timer 2 CC3 event] + TIM2CC4: [5, Timer 2 CC4 event] + TIM2TRGO: [6, Timer 2 TRGO event] + TIM3CC1: [7, Timer 3 CC1 event] + TIM3TRGO: [8, Timer 3 TRGO event] + TIM4CC4: [9, Timer 4 CC4 event] + TIM5CC1: [10, Timer 5 CC1 event] + TIM5CC2: [11, Timer 5 CC2 event] + TIM5CC3: [12, Timer 5 CC3 event] + TIM8CC1: [13, Timer 8 CC1 event] + TIM8TRGO: [14, Timer 8 TRGO event] + EXTI11: [15, EXTI line 11] + JEXTSEL: + TIM1CC4: [0, Timer 1 CC4 event] + TIM1TRGO: [1, Timer 1 TRGO event] + TIM2CC1: [2, Timer 2 CC1 event] + TIM2TRGO: [3, Timer 2 TRGO event] + TIM3CC2: [4, Timer 3 CC2 event] + TIM3CC4: [5, Timer 3 CC4 event] + TIM4CC1: [6, Timer 4 CC1 event] + TIM4CC2: [7, Timer 4 CC2 event] + TIM4CC3: [8, Timer 4 CC3 event] + TIM4TRGO: [9, Timer 4 TRGO event] + TIM5CC4: [10, Timer 5 CC4 event] + TIM5TRGO: [11, Timer 5 TRGO event] + TIM8CC2: [12, Timer 8 CC2 event] + TIM8CC3: [13, Timer 8 CC3 event] + TIM8CC4: [14, Timer 8 CC4 event] + EXTI15: [15, EXTI line 15] diff --git a/devices/fields/adc/adc_v2/adc_v2_extsel_d.yaml b/devices/fields/adc/adc_v2/adc_v2_extsel_d.yaml new file mode 100644 index 000000000..f6943b74a --- /dev/null +++ b/devices/fields/adc/adc_v2/adc_v2_extsel_d.yaml @@ -0,0 +1,32 @@ +CR2: + EXTSEL: + TIM1CH1: [0, Timer 1 CH1] + TIM1CH2: [1, Timer 1 CH2] + TIM1CH3: [2, Timer 1 CH3] + TIM2CH2: [3, Timer 2 CH2] + TIM5TRGO: [4, Timer 5 TRGO] + TIM4CH4: [5, Timer 4 CH4] + TIM3CH4: [6, Timer 3 CH4] + TIM8TRGO: [7, Timer 8 TRGO] + TIM8TRGO2: [8, Timer 8 TRGO(2)] + TIM1TRGO: [9, Timer 1 TRGO] + TIM1TRGO2: [10, Timer 1 TRGO(2)] + TIM2TRGO: [11, Timer 2 TRGO] + TIM4TRGO: [12, Timer 4 TRGO] + TIM6TRGO: [13, Timer 6 TRGO] + EXTI11: [15, EXTI line 11] + JEXTSEL: + TIM1TRGO: [0, Timer 1 TRGO] + TIM1CH4: [1, Timer 1 CH4] + TIM2TRGO: [2, Timer 2 TRGO] + TIM2CH1: [3, Timer 2 CH1] + TIM3CH4: [4, Timer 3 CH4] + TIM4TRGO: [5, Timer 4 TRGO] + TIM8CH4: [7, Timer 8 CH4] + TIM1TRGO2: [8, Timer 1 TRGO(2)] + TIM8TRGO: [9, Timer 8 TRGO] + TIM8TRGO2: [10, Timer 8 TRGO(2)] + TIM3CH3: [11, Timer 3 CH3] + TIM5TRGO: [12, Timer 5 TRGO] + TIM3CH1: [13, Timer 3 CH1] + TIM6TRGO: [14, Timer 6 TRGO] diff --git a/devices/fields/adc/adc_v2_common.yaml b/devices/fields/adc/adc_v2_common.yaml new file mode 100644 index 000000000..078a5416e --- /dev/null +++ b/devices/fields/adc/adc_v2_common.yaml @@ -0,0 +1,14 @@ +# ADC as used on F2, F4 and F7 + +CCR: + TSVREFE: + Disabled: [0, Temperature sensor and V_REFINT channel disabled] + Enabled: [1, Temperature sensor and V_REFINT channel enabled] + VBATE: + Disabled: [0, V_BAT channel disabled] + Enabled: [1, V_BAT channel enabled] + ADCPRE: + Div2: [0, PCLK2 divided by 2] + Div4: [1, PCLK2 divided by 4] + Div6: [2, PCLK2 divided by 6] + Div8: [3, PCLK2 divided by 8] diff --git a/devices/fields/adc/adc_v2_common_single.yaml b/devices/fields/adc/adc_v2_common_single.yaml new file mode 100644 index 000000000..3ae03789f --- /dev/null +++ b/devices/fields/adc/adc_v2_common_single.yaml @@ -0,0 +1,23 @@ +# ADC_Common as used on F4 with single ADC and a CSR register + +_include: + - adc_v2_common.yaml +CSR: + OVR?: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + STRT?: + NotStarted: [0, No regular channel conversion started] + Started: [1, Regular channel conversion has started] + JSTRT?: + NotStarted: [0, No injected channel conversion started] + Started: [1, Injected channel conversion has started] + JEOC?: + NotComplete: [0, Conversion is not complete] + Complete: [1, Conversion complete] + EOC?: + NotComplete: [0, Conversion is not complete] + Complete: [1, Conversion complete] + AWD?: + NoEvent: [0, No analog watchdog event occurred] + Event: [1, Analog watchdog event occurred] diff --git a/devices/fields/adc/adc_v2_multi.yaml b/devices/fields/adc/adc_v2_multi.yaml new file mode 100644 index 000000000..2fb149795 --- /dev/null +++ b/devices/fields/adc/adc_v2_multi.yaml @@ -0,0 +1,28 @@ +# ADC_Common as used on F2, F4 and F7 with multiple ADCs + +_include: + - adc_v2_common_single.yaml +CCR: + DMA: + Disabled: [0, DMA mode disabled] + Mode1: [1, DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)] + Mode2: [2, "DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)"] + Mode3: [3, "DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)"] + DDS: + Single: [0, No new DMA request is issued after the last transfer] + Continuous: [1, "DMA requests are issued as long as data are converted and DMA=01, 10 or 11"] + DELAY: [0, 15] + MULTI: + Independent: [0, "All the ADCs independent: independent mode"] + DualRJ: [1, "Dual ADC1 and ADC2, combined regular and injected simultaneous mode"] + DualRA: [2, "Dual ADC1 and ADC2, combined regular and alternate trigger mode"] + DualJ: [5, "Dual ADC1 and ADC2, injected simultaneous mode only"] + DualR: [6, "Dual ADC1 and ADC2, regular simultaneous mode only"] + DualI: [7, "Dual ADC1 and ADC2, interleaved mode only"] + DualA: [9, "Dual ADC1 and ADC2, alternate trigger mode only"] + TripleRJ: [17, "Triple ADC, regular and injected simultaneous mode"] + TripleRA: [18, "Triple ADC, regular and alternate trigger mode"] + TripleJ: [21, "Triple ADC, injected simultaneous mode only"] + TripleR: [22, "Triple ADC, regular simultaneous mode only"] + TripleI: [23, "Triple ADC, interleaved mode only"] + TripleA: [24, "Triple ADC, alternate trigger mode only"] diff --git a/devices/fields/adc/adc_v3.yaml b/devices/fields/adc/adc_v3.yaml new file mode 100644 index 000000000..692a135b1 --- /dev/null +++ b/devices/fields/adc/adc_v3.yaml @@ -0,0 +1,182 @@ +# ADC as used on H7 and F3 + +ISR: + JQOVF: + _read: + NoOverflow: [0, No injected context queue overflow has occurred] + Overflow: [1, Injected context queue overflow has occurred] + _W1C: + Clear: [1, Clear injected context queue overflow flag] + AWD?: + _read: + NoEvent: [0, No analog watchdog event occurred] + Event: [1, Analog watchdog event occurred] + _W1C: + Clear: [1, Clear analog watchdog event occurred flag] + OVR: + _read: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + _W1C: + Clear: [1, Clear overrun occurred flag] + JEOS: + _read: + NotComplete: [0, Injected sequence is not complete] + Complete: [1, Injected sequence complete] + _W1C: + Clear: [1, Clear Injected sequence complete flag] + EOS: + _read: + NotComplete: [0, Regular sequence is not complete] + Complete: [1, Regular sequence complete] + _W1C: + Clear: [1, Clear regular sequence complete flag] + JEOC: + _read: + NotComplete: [0, Injected conversion is not complete] + Complete: [1, Injected conversion complete] + _W1C: + Clear: [1, Clear injected conversion complete flag] + EOC: + _read: + NotComplete: [0, Regular conversion is not complete] + Complete: [1, Regular conversion complete] + _W1C: + Clear: [1, Clear regular conversion complete flag] + EOSMP: + _read: + NotEnded: [0, End of sampling phase no yet reached] + Ended: [1, End of sampling phase reached] + _W1C: + Clear: [1, Clear end of sampling phase reached flag] + ADRDY: + _read: + NotReady: [0, ADC is not ready to start conversion] + Ready: [1, ADC is ready to start conversion] + _W1C: + Clear: [1, Clear ADC is ready to start conversion flag] +IER: + JQOVFIE: + Disabled: [0, Injected context queue overflow interrupt disabled] + Enabled: [1, Injected context queue overflow interrupt enabled] + AWD?IE: + Disabled: [0, Analog watchdog interrupt disabled] + Enabled: [1, Analog watchdog interrupt enabled] + JEOSIE: + Disabled: [0, End of injected sequence interrupt disabled] + Enabled: [1, End of injected sequence interrupt enabled] + EOSIE: + Disabled: [0, End of regular sequence interrupt disabled] + Enabled: [1, End of regular sequence interrupt enabled] + JEOCIE: + Disabled: [0, End of injected conversion interrupt disabled] + Enabled: [1, End of injected conversion interrupt enabled] + EOCIE: + Disabled: [0, End of regular conversion interrupt disabled] + Enabled: [1, End of regular conversion interrupt enabled] + OVRIE: + Disabled: [0, Overrun interrupt disabled] + Enabled: [1, Overrun interrupt enabled] + EOSMPIE: + Disabled: [0, End of regular conversion sampling phase interrupt disabled] + Enabled: [1, End of regular conversion sampling phase interrupt enabled] + ADRDYIE: + Disabled: [0, ADC ready interrupt disabled] + Enabled: [1, ADC ready interrupt enabled] +CR: + ADCAL: + _read: + NotCalibrating: [0, ADC calibration either not yet performed or completed] + Calibrating: [1, ADC calibration in progress] + _W1S: + StartCalibration: [1, Start the ADC calibration sequence] + ADCALDIF: + SingleEnded: [0, Calibration for single-ended mode] + Differential: [1, Calibration for differential mode] + JADSTP,ADSTP: + _read: + NotStopping: [0, No stop command active] + Stopping: [1, ADC stopping conversion] + _W1S: + StopConversion: [1, Stop the active conversion] + JADSTART,ADSTART: + _read: + NotActive: [0, No conversion ongoing] + Active: [1, ADC operating and may be converting] + _W1S: + StartConversion: [1, Start the ADC conversion (may be delayed for hardware triggers)] + ADDIS: + _read: + NotDisabling: [0, No disable command active] + Disabling: [1, ADC disabling] + _W1S: + Disable: [1, Disable the ADC] + ADEN: + _read: + Disabled: [0, ADC disabled] + Enabled: [1, ADC enabled] + _W1S: + Enabled: [1, Enable the ADC] +CFGR: + JAUTO: + Disabled: [0, Automatic injected group conversion disabled] + Enabled: [1, Automatic injected group conversion enabled] + JAWD1EN: + Disabled: [0, Analog watchdog 1 disabled on injected channels] + Enabled: [1, Analog watchdog 1 enabled on injected channels] + AWD1EN: + Disabled: [0, Analog watchdog 1 disabled on regular channels] + Enabled: [1, Analog watchdog 1 enabled on regular channels] + AWD1SGL: + All: [0, Analog watchdog 1 enabled on all channels] + Single: [1, Analog watchdog 1 enabled on single channel selected in AWD1CH] + JQM: + Mode0: [0, "JSQR Mode 0: Queue maintains the last written configuration into JSQR"] + Mode1: [1, "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"] + JDISCEN: + Disabled: [0, Discontinuous mode on injected channels disabled] + Enabled: [1, Discontinuous mode on injected channels enabled] + DISCNUM: [0, 7] + DISCEN: + Disabled: [0, Discontinuous mode on regular channels disabled] + Enabled: [1, Discontinuous mode on regular channels enabled] + AUTDLY: + "Off": [0, Auto delayed conversion mode off] + "On": [1, Auto delayed conversion mode on] + CONT: + Single: [0, Single conversion mode] + Continuous: [1, Continuous conversion mode] + OVRMOD: + Preserve: [0, Preserve DR register when an overrun is detected] + Overwrite: [1, Overwrite DR register when an overrun is detected] +CFGR,JSQR: + EXTEN,JEXTEN: + Disabled: [0, Trigger detection disabled] + RisingEdge: [1, Trigger detection on the rising edge] + FallingEdge: [2, Trigger detection on the falling edge] + BothEdges: [3, Trigger detection on both the rising and falling edges] +JSQR: + JL: [0, 3] # Total number of conversions in injected sequence + JSQ?: [0, 19] # Channel number for Nth item in injected sequence +AWD2CR: + AWD2CH*: + NotMonitored: [0, Input channel not monitored by AWDx] + Monitored: [1, Input channel monitored by AWDx] +AWD3CR: + AWD3CH*: + NotMonitored: [0, Input channel not monitored by AWDx] + Monitored: [1, Input channel monitored by AWDx] +# Sequences +SQR1: + L: [0, 15] # Total number of conversions in regular sequence +# Differential mode +DIFSEL: + DIFSEL*: + SingleEnded: [0, Input channel is configured in single-ended mode] + Differential: [1, Input channel is configured in differential mode] + +SMPR1: + "?~SMPPLUS": + KeepCycles: [0, The sampling time remains set to 2.5 ADC clock cycles remains] + Add1Cycle: + [1, 2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers] diff --git a/devices/fields/adc/adc_v3_common.yaml b/devices/fields/adc/adc_v3_common.yaml new file mode 100644 index 000000000..ea7165112 --- /dev/null +++ b/devices/fields/adc/adc_v3_common.yaml @@ -0,0 +1,14 @@ +# ADC_Common as used on H7 and F3 + +_include: adc_v3_common_single.yaml +CCR: + DELAY: [0, 15] + DUAL: + Independent: [0, Independent mode] + DualRJ: [1, "Dual, combined regular simultaneous + injected simultaneous mode"] + DualRA: [2, "Dual, combined regular simultaneous + alternate trigger mode"] + DualIJ: [3, "Dual, combined interleaved mode + injected simultaneous mode"] + DualJ: [5, "Dual, injected simultaneous mode only"] + DualR: [6, "Dual, regular simultaneous mode only"] + DualI: [7, "Dual, interleaved mode only"] + DualA: [9, "Dual, alternate trigger mode only"] diff --git a/devices/fields/adc/adc_v3_common_f3.yaml b/devices/fields/adc/adc_v3_common_f3.yaml new file mode 100644 index 000000000..9c4a2befb --- /dev/null +++ b/devices/fields/adc/adc_v3_common_f3.yaml @@ -0,0 +1,13 @@ +# ADC_Common with F3 specific fields + +_include: + - adc_v3_common_f3_single.yaml + - adc_v3_common.yaml +CCR: + MDMA: + Disabled: [0, MDMA mode disabled] + Bits12_10: [2, MDMA mode enabled for 12 and 10-bit resolution] + Bits8_6: [3, MDMA mode enabled for 8 and 6-bit resolution] + DMACFG: + OneShot: [0, DMA one shot mode selected] + Circulator: [1, DMA circular mode selected] diff --git a/devices/fields/adc/adc_v3_common_f3_single.yaml b/devices/fields/adc/adc_v3_common_f3_single.yaml new file mode 100644 index 000000000..634918a27 --- /dev/null +++ b/devices/fields/adc/adc_v3_common_f3_single.yaml @@ -0,0 +1,10 @@ +# ADC_Common with F3 specific fields +# limited to fields available even on parts with a single ADC + +CCR: + VBATEN: + Disabled: [0, V_BAT channel disabled] + Enabled: [1, V_BAT channel enabled] + TSEN: + Disabled: [0, Temperature sensor channel disabled] + Enabled: [1, Temperature sensor channel enabled] diff --git a/devices/fields/adc/adc_v3_common_g4.yaml b/devices/fields/adc/adc_v3_common_g4.yaml new file mode 100644 index 000000000..475651674 --- /dev/null +++ b/devices/fields/adc/adc_v3_common_g4.yaml @@ -0,0 +1,10 @@ +# ADC_Common with G4 specific fields + +_include: adc_v3_common.yaml +CCR: + VBATSEL: + Disabled: [0, V_BAT channel disabled] + Enabled: [1, V_BAT channel enabled] + VSENSESEL: + Disabled: [0, Temperature sensor channel disabled] + Enabled: [1, Temperature sensor channel enabled] diff --git a/devices/fields/adc/adc_v3_common_h7.yaml b/devices/fields/adc/adc_v3_common_h7.yaml new file mode 100644 index 000000000..2ba9f29a2 --- /dev/null +++ b/devices/fields/adc/adc_v3_common_h7.yaml @@ -0,0 +1,24 @@ +# ADC_Common with H7 specific fields + +_include: adc_v3_common.yaml +CCR: + "VSENSEEN,VBATEN": + Disabled: [0, The selected ADC channel disabled] + Enabled: [1, The selected ADC channel enabled] + PRESC: + Div1: [0, adc_ker_ck_input not divided] + Div2: [1, adc_ker_ck_input divided by 2] + Div4: [2, adc_ker_ck_input divided by 4] + Div6: [3, adc_ker_ck_input divided by 6] + Div8: [4, adc_ker_ck_input divided by 8] + Div10: [5, adc_ker_ck_input divided by 10] + Div12: [6, adc_ker_ck_input divided by 12] + Div16: [7, adc_ker_ck_input divided by 16] + Div32: [8, adc_ker_ck_input divided by 32] + Div64: [9, adc_ker_ck_input divided by 64] + Div128: [10, adc_ker_ck_input divided by 128] + Div256: [11, adc_ker_ck_input divided by 256] + "?~DAMDF": + NoPack: [0, "Without data packing, CDR/CDR2 not used"] + Format32to10: [2, CDR formatted for 32-bit down to 10-bit resolution] + Format8: [3, CDR formatted for 8-bit resolution] diff --git a/devices/fields/adc/adc_v3_common_l4+.yaml b/devices/fields/adc/adc_v3_common_l4+.yaml new file mode 100644 index 000000000..cad7964a0 --- /dev/null +++ b/devices/fields/adc/adc_v3_common_l4+.yaml @@ -0,0 +1,34 @@ +# ADC_Common with L4/L4+/L5 specific fields + +CCR: + DMACFG: + OneShotMode: [0, DMA One Shot mode selected] + CircularMode: [1, DMA Circular mode selected] + MDMA: + Disabled: [0, MDMA mode disabled] + Interleaved: + [ + 1, + Enable dual interleaved mode to output to the master channel of DFSDM interface both Master and the Slave result (16-bit data width), + ] + Bits12_10: [2, MDMA mode enabled for 12 and 10-bit resolution] + Bits8_6: [3, MDMA mode enabled for 8 and 6-bit resolution] + "VBATEN,VSENSEEN": + Disabled: [0, The selected ADC channel disabled] + Enabled: [1, The selected ADC channel enabled] + PRESC: + Div1: [0b0000, Input ADC clock not divided] + Div2: [0b0001, Input ADC clock divided by 2] + Div4: [0b0010, Input ADC clock divided by 4] + Div6: [0b0011, Input ADC clock divided by 6] + Div8: [0b0100, Input ADC clock divided by 8] + Div10: [0b0101, Input ADC clock divided by 10] + Div12: [0b0110, Input ADC clock divided by 12] + Div16: [0b0111, Input ADC clock divided by 16] + Div32: [0b1000, Input ADC clock divided by 32] + Div64: [0b1001, Input ADC clock divided by 64] + Div128: [0b1010, Input ADC clock divided by 128] + Div256: [0b1011, Input ADC clock divided by 256] + +CDR: + RDATA*: [0, 0xFFFF] diff --git a/devices/fields/adc/adc_v3_common_single.yaml b/devices/fields/adc/adc_v3_common_single.yaml new file mode 100644 index 000000000..40d93a6dc --- /dev/null +++ b/devices/fields/adc/adc_v3_common_single.yaml @@ -0,0 +1,40 @@ +# ADC_Common as used on H7 and F3 +# limited to fields available even on parts with a single ADC + +CSR: + JQOVF_MST,JQOVF_SLV: + NoOverflow: [0, No injected context queue overflow has occurred] + Overflow: [1, Injected context queue overflow has occurred] + "AWD?_MST,AWD?_SLV": + NoEvent: [0, No analog watchdog event occurred] + Event: [1, Analog watchdog event occurred] + OVR_MST,OVR_SLV: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + JEOS_MST,JEOS_SLV: + NotComplete: [0, Injected sequence is not complete] + Complete: [1, Injected sequence complete] + EOS_MST,EOS_SLV: + NotComplete: [0, Regular sequence is not complete] + Complete: [1, Regular sequence complete] + JEOC_MST,JEOC_SLV: + NotComplete: [0, Injected conversion is not complete] + Complete: [1, Injected conversion complete] + EOC_MST,EOC_SLV: + NotComplete: [0, Regular conversion is not complete] + Complete: [1, Regular conversion complete] + EOSMP_MST,EOSMP_SLV: + NotEnded: [0, End of sampling phase no yet reached] + Ended: [1, End of sampling phase reached] + ADRDY_MST,ADRDY_SLV: + NotReady: [0, ADC is not ready to start conversion] + Ready: [1, ADC is ready to start conversion] +CCR: + VREFEN: + Disabled: [0, V_REFINT channel disabled] + Enabled: [1, V_REFINT channel enabled] + CKMODE: + Asynchronous: [0, Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock] + SyncDiv1: [1, Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck] + SyncDiv2: [2, Use AHB clock rcc_hclk3 divided by 2] + SyncDiv4: [3, Use AHB clock rcc_hclk3 divided by 4] diff --git a/devices/fields/adc/adc_v3_f3.yaml b/devices/fields/adc/adc_v3_f3.yaml new file mode 100644 index 000000000..30c2c2cef --- /dev/null +++ b/devices/fields/adc/adc_v3_f3.yaml @@ -0,0 +1,77 @@ +# ADC v3 with F3 specific fields + +_include: + - adc_v3.yaml +CR: + ADVREGEN: + Intermediate: [0, Intermediate state required when moving the ADC voltage regulator between states] + Enabled: [1, ADC voltage regulator enabled] + Disabled: [2, ADC voltage regulator disabled] +CFGR: + EXTSEL: + TIM1_CC1: [0, Timer 1 CC1 event] + TIM1_CC2: [1, Timer 1 CC2 event] + TIM1_CC3: [2, Timer 1 CC3 event] + TIM2_CC2: [3, Timer 2 CC2 event] + TIM3_TRGO: [4, Timer 3 TRGO event] + EXTI11: [6, EXTI line 11] + HRTIM_ADCTRG1: [7, HRTIM_ADCTRG1 event] + HRTIM_ADCTRG3: [8, HRTIM_ADCTRG3 event] + TIM1_TRGO: [9, Timer 1 TRGO event] + TIM1_TRGO2: [10, Timer 1 TRGO2 event] + TIM2_TRGO: [11, Timer 2 TRGO event] + TIM6_TRGO: [13, Timer 6 TRGO event] + TIM15_TRGO: [14, Timer 15 TRGO event] + TIM3_CC4: [15, Timer 3 CC4 event] + ALIGN: + Right: [0, Right alignment] + Left: [1, Left alignment] + RES: + Bits12: [0, 12-bit] + Bits10: [1, 10-bit] + Bits8: [2, 8-bit] + Bits6: [3, 6-bit] + DMACFG: + OneShot: [0, DMA One Shot Mode selected] + Circular: [1, DMA circular mode selected] + DMAEN: + Disabled: [0, DMA disabled] + Enabled: [1, DMA enabled] +JSQR: + JEXTSEL: + TIM1_TRGO: [0, Timer 1 TRGO event] + TIM1_CC4: [1, Timer 1 CC4 event] + TIM2_TRGO: [2, Timer 2 TRGO event] + TIM2_CC1: [3, Timer 2 CC1 event] + TIM3_CC4: [4, Timer 3 CC4 event] + EXTI15: [6, EXTI line 15] + TIM1_TRGO2: [8, Timer 1 TRGO2 event] + HRTIM_ADCTRG2: [9, HRTIM_ADCTRG2 event] + HRTIM_ADCTRG4: [10, HRTIM_ADCTRG4 event] + TIM3_CC3: [11, Timer 3 CC3 event] + TIM3_TRGO: [12, Timer 3 TRGO event] + TIM3_CC1: [13, Timer 3 CC1 event] + TIM6_TRGO: [14, Timer 6 TRGO event] + TIM15_TRGO: [15, Timer 15 TRGO event] +SMPR?: + SMP*: + Cycles1_5: [0, 1.5 ADC clock cycles] + Cycles2_5: [1, 2.5 ADC clock cycles] + Cycles4_5: [2, 4.5 ADC clock cycles] + Cycles7_5: [3, 7.5 ADC clock cycles] + Cycles19_5: [4, 19.5 ADC clock cycles] + Cycles61_5: [5, 61.5 ADC clock cycles] + Cycles181_5: [6, 181.5 ADC clock cycles] + Cycles601_5: [7, 601.5 ADC clock cycles] +TR1: + "[HL]T1": [0, 0xFFF] +"TR[23]": + "[HL]T?": [0, 0xFF] +OFR?: + OFFSET_EN: + Disabled: [0, Offset disabled] + Enabled: [1, Offset enabled] + OFFSET_CH: [0, 31] + OFFSET: [0, 0xFFF] +CALFACT: + CALFACT_?: [0, 0x7F] diff --git a/devices/fields/adc/adc_v3_g4.yaml b/devices/fields/adc/adc_v3_g4.yaml new file mode 100644 index 000000000..557968c44 --- /dev/null +++ b/devices/fields/adc/adc_v3_g4.yaml @@ -0,0 +1,131 @@ +# ADC v3 with G4 specific fields + +_include: + - ../../patches/adc/split.yaml + - adc_v3.yaml +DIFSEL: + _merge: + DIFSEL: DIFSEL* +CR: + ADVREGEN: + Disabled: [0, ADC voltage regulator disabled] + Enabled: [1, ADC voltage regulator enabled] + DEEPPWD: + Disabled: [0, ADC not in Deep-power down] + Enabled: [1, ADC in Deep-power-down (default reset state)] + +CFGR: + JQDIS: + Enabled: [0, Injected Queue enabled] + Disabled: [1, Injected Queue disabled] + AWD1CH: [0, 18] + EXTSEL: + TIM1_CC1: [0, Timer 1 CC1 event] + TIM1_CC2: [1, Timer 1 CC2 event] + TIM1_CC3: [2, Timer 1 CC3 event] + TIM2_CC2: [3, Timer 2 CC2 event] + TIM3_TRGO: [4, Timer 3 TRGO event] + EXTI11: [6, EXTI line 11] + HRTIM_ADCTRG1: [7, HRTIM_ADCTRG1 event] + HRTIM_ADCTRG3: [8, HRTIM_ADCTRG3 event] + TIM1_TRGO: [9, Timer 1 TRGO event] + TIM1_TRGO2: [10, Timer 1 TRGO2 event] + TIM2_TRGO: [11, Timer 2 TRGO event] + TIM6_TRGO: [13, Timer 6 TRGO event] + TIM15_TRGO: [14, Timer 15 TRGO event] + TIM3_CC4: [15, Timer 3 CC4 event] + ALIGN: + Right: [0, Right alignment] + Left: [1, Left alignment] + RES: + Bits12: [0, 12-bit] + Bits10: [1, 10-bit] + Bits8: [2, 8-bit] + Bits6: [3, 6-bit] + DMACFG: + OneShot: [0, DMA One Shot Mode selected] + Circular: [1, DMA circular mode selected] + DMAEN: + Disabled: [0, DMA disabled] + Enabled: [1, DMA enabled] +CFGR2: + SMPTRIG: + Disabled: [0, Sampling time control trigger mode disabled] + Enabled: [1, Sampling time control trigger mode enabled] + BULB: + Disabled: [0, Bulb sampling mode disabled] + Enabled: [1, Bulb sampling mode enabled. Immediately start sampling after last conversion finishes.] + SWTRIG: + Disabled: [0, End sampling period and start conversion] + Enabled: [1, Start sampling period] + GCOMP: + Disabled: [0, Regular ADC operating mode] + Enabled: [1, Gain compensation enabled and applies to all channels] + ROVSM: + Continued: [0, Oversampling is temporary stopped and continued after injection sequence] + Resumed: [1, Oversampling is aborted and resumed from start after injection sequence] + TROVS: + Automatic: [0, All oversampled conversions for a channel are run following a trigger] + Triggered: [1, Each oversampled conversion for a channel needs a new trigger] + OVSS: + NoShift: [0, No right shift applied to oversampling result] + Shift1: [1, Shift oversampling result right by 1 bit] + Shift2: [2, Shift oversampling result right by 2 bits] + Shift3: [3, Shift oversampling result right by 3 bits] + Shift4: [4, Shift oversampling result right by 4 bits] + Shift5: [5, Shift oversampling result right by 5 bits] + Shift6: [6, Shift oversampling result right by 6 bits] + Shift7: [7, Shift oversampling result right by 7 bits] + Shift8: [8, Shift oversampling result right by 8 bits] + OVSR: + OS2: [0, Oversampling ratio of 2] + OS4: [1, Oversampling ratio of 4] + OS8: [2, Oversampling ratio of 8] + OS16: [3, Oversampling ratio of 16] + OS32: [4, Oversampling ratio of 32] + OS64: [5, Oversampling ratio of 64] + OS128: [6, Oversampling ratio of 128] + OS256: [7, Oversampling ratio of 256] + JOVSE: + Disabled: [0, Injected oversampling disabled] + Enabled: [1, Injected oversampling enabled] + ROVSE: + Disabled: [0, Regular oversampling disabled] + Enabled: [1, Regular oversampling enabled] +SMPR?: + "SMP?,SMP??": + Cycles2_5: [0, 2.5 ADC clock cycles] + Cycles6_5: [1, 6.5 ADC clock cycles] + Cycles12_5: [2, 12.5 ADC clock cycles] + Cycles24_5: [3, 24.5 ADC clock cycles] + Cycles47_5: [4, 47.5 ADC clock cycles] + Cycles92_5: [5, 92.5 ADC clock cycles] + Cycles247_5: [6, 247.5 ADC clock cycles] + Cycles640_5: [7, 640.5 ADC clock cycles] +TR1: + "[HL]T1": [0, 0xFFF] +"TR[23]": + "[HL]T?": [0, 0xFF] +OFR?: + OFFSET_EN: + Disabled: [0, Offset disabled] + Enabled: [1, Offset enabled] + OFFSET_CH: [0, 31] + OFFSET: [0, 0xFFF] +CALFACT: + CALFACT_?: [0, 0x7F] + +JSQR: + JEXTSEL: + TIM1_TRGO: [0, Timer 1 TRGO event] + TIM1_CC4: [1, Timer 1 CC4 event] + TIM2_TRGO: [2, Timer 2 TRGO event] + TIM2_CC1: [3, Timer 2 CC1 event] + TIM3_CC4: [4, Timer 3 CC4 event] + EXTI15: [6, EXTI line 15] + TIM1_TRGO2: [8, Timer 1 TRGO2 event] + TIM3_CC3: [11, Timer 3 CC3 event] + TIM3_TRGO: [12, Timer 3 TRGO event] + TIM3_CC1: [13, Timer 3 CC1 event] + TIM6_TRGO: [14, Timer 6 TRGO event] + TIM15_TRGO: [15, Timer 15 TRGO event] diff --git a/devices/fields/adc/adc_v3_h7.yaml b/devices/fields/adc/adc_v3_h7.yaml new file mode 100644 index 000000000..47e2cb467 --- /dev/null +++ b/devices/fields/adc/adc_v3_h7.yaml @@ -0,0 +1,121 @@ +# ADC v3 with H7 specific fields + +_include: + - ../../patches/adc/split.yaml + - adc_v3.yaml + - awd0_19.yaml +CR: + ADVREGEN: + Disabled: [0, ADC voltage regulator disabled] + Enabled: [1, ADC voltage regulator enabled] + DEEPPWD: + PowerUp: [0, ADC not in deep power down] + PowerDown: [1, ADC in deep power down] + LINCALRDYW?: + Reset: [0, LINCALFACT Word Read] + Set: [1, LINCALFACT Word Write] + ADCALLIN: + NoLinearity: [0, ADC calibration without linearaity calibration] + Linearity: [1, ADC calibration with linearaity calibration] +CFGR: + EXTSEL: + TIM1_CC1: [0, Timer 1 CC1 event] + TIM1_CC2: [1, Timer 1 CC2 event] + TIM1_CC3: [2, Timer 1 CC3 event] + TIM2_CC2: [3, Timer 2 CC2 event] + TIM3_TRGO: [4, Timer 3 TRGO event] + TIM4_CC4: [5, Timer 4 CC4 event] + EXTI11: [6, EXTI line 11] + TIM8_TRGO: [7, Timer 8 TRGO event] + TIM8_TRGO2: [8, Timer 8 TRGO2 event] + TIM1_TRGO: [9, Timer 1 TRGO event] + TIM1_TRGO2: [10, Timer 1 TRGO2 event] + TIM2_TRGO: [11, Timer 2 TRGO event] + TIM4_TRGO: [12, Timer 4 TRGO event] + TIM6_TRGO: [13, Timer 6 TRGO event] + TIM15_TRGO: [14, Timer 15 TRGO event] + TIM3_CC4: [15, Timer 3 CC4 event] + HRTIM1_ADCTRG1: [16, HRTIM1_ADCTRG1 event] + HRTIM1_ADCTRG3: [17, HRTIM1_ADCTRG3 event] + LPTIM1_OUT: [18, LPTIM1_OUT event] + LPTIM2_OUT: [19, LPTIM2_OUT event] + LPTIM3_OUT: [20, LPTIM3_OUT event] + JQDIS: + Enabled: [0, Injected Queue enabled] + Disabled: [1, Injected Queue disabled] + DMNGT: + DR: [0, Store output data in DR only] + DMA_OneShot: [1, DMA One Shot Mode selected] + DFSDM: [2, DFSDM mode selected] + DMA_Circular: [3, DMA Circular Mode selected] +CFGR2: + LSHIFT: [0, 15] + OSVR: [0, 1023] + RSHIFT?: + Disabled: [0, Right-shifting disabled] + Enabled: [1, Data is right-shifted 1-bit] + ROVSM: + Continued: [0, Oversampling is temporary stopped and continued after injection sequence] + Resumed: [1, Oversampling is aborted and resumed from start after injection sequence] + TROVS: + Automatic: [0, All oversampled conversions for a channel are run following a trigger] + Triggered: [1, Each oversampled conversion for a channel needs a new trigger] + OVSS: [0, 11] + JOVSE: + Disabled: [0, Injected oversampling disabled] + Enabled: [1, Injected oversampling enabled] + ROVSE: + Disabled: [0, Regular oversampling disabled] + Enabled: [1, Regular oversampling enabled] +SMPR?: + SMP*: + Cycles1_5: [0, 1.5 ADC clock cycles] + Cycles2_5: [1, 2.5 ADC clock cycles] + Cycles8_5: [2, 8.5 ADC clock cycles] + Cycles16_5: [3, 16.5 ADC clock cycles] + Cycles32_5: [4, 32.5 ADC clock cycles] + Cycles64_5: [5, 64.5 ADC clock cycles] + Cycles387_5: [6, 387.5 ADC clock cycles] + Cycles810_5: [7, 810.5 ADC clock cycles] +HTR?: + HTR?: [0, 0x03FF_FFFF] +LTR?: + LTR?: [0, 0x03FF_FFFF] +JSQR: + JEXTSEL: + TIM1_TRGO: [0, Timer 1 TRGO event] + TIM1_CC4: [1, Timer 1 CC4 event] + TIM2_TRGO: [2, Timer 2 TRGO event] + TIM2_CC1: [3, Timer 2 CC1 event] + TIM3_CC4: [4, Timer 3 CC4 event] + TIM4_TRGO: [5, Timer 4 TRGO event] + EXTI15: [6, EXTI line 15] + TIM8_CC4: [7, Timer 8 CC4 event] + TIM1_TRGO2: [8, Timer 1 TRGO2 event] + TIM8_TRGO: [9, Timer 8 TRGO event] + TIM8_TRGO2: [10, Timer 8 TRGO2 event] + TIM3_CC3: [11, Timer 3 CC3 event] + TIM3_TRGO: [12, Timer 3 TRGO event] + TIM3_CC1: [13, Timer 3 CC1 event] + TIM6_TRGO: [14, Timer 6 TRGO event] + TIM15_TRGO: [15, Timer 15 TRGO event] + HRTIM1_ADCTRG2: [16, HRTIM1_ADCTRG2 event] + HRTIM1_ADCTRG4: [17, HRTIM1_ADCTRG4 event] + LPTIM1_OUT: [18, LPTIM1_OUT event] + LPTIM2_OUT: [19, LPTIM2_OUT event] + LPTIM3_OUT: [20, LPTIM3_OUT event] +OFR?: + SSATE: + Disabled: + [0, Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)] + Enabled: [1, Offset is subtracted and result is saturated to maintain result size] + OFFSET_CH: [0, 31] + OFFSET: [0, 0x3FFFFFF] +PCSEL: + PCSEL*: + NotPreselected: [0, Input channel x is not pre-selected] + Preselected: [1, Pre-select input channel x] +CALFACT: + CALFACT_?: [0, 2047] +CALFACT2: + LINCALFACT: [0, 0x3FFFFFFF] diff --git a/devices/fields/adc/adc_v3_l4.yaml b/devices/fields/adc/adc_v3_l4.yaml new file mode 100644 index 000000000..89ae719d3 --- /dev/null +++ b/devices/fields/adc/adc_v3_l4.yaml @@ -0,0 +1,137 @@ +# ADC v3 with L4/L4+/L5 specific fields + +CR: + DEEPPWD: + NotDeepPowerDown: [0, ADC not in Deep-power down] + DeepPowerDown: [1, ADC in Deep-power-down (default reset state)] + ADVREGEN: + Disabled: [0, ADC Voltage regulator disabled] + Enabled: [1, ADC Voltage regulator enabled] + +CFGR: + EXTSEL: + TIM1_CC1: [0, Timer 1 CC1 event] + TIM1_CC2: [1, Timer 1 CC2 event] + TIM1_CC3: [2, Timer 1 CC3 event] + TIM2_CC2: [3, Timer 2 CC2 event] + TIM3_TRGO: [4, Timer 3 TRGO event] + EXTI11: [6, EXTI line 11] + TIM1_TRGO: [9, Timer 1 TRGO event] + TIM1_TRGO2: [10, Timer 1 TRGO2 event] + TIM2_TRGO: [11, Timer 2 TRGO event] + TIM6_TRGO: [13, Timer 6 TRGO event] + TIM15_TRGO: [14, Timer 15 TRGO event] + TIM3_CC4: [15, Timer 3 CC4 event] + ALIGN: + Right: [0, Right alignment] + Left: [1, Left alignment] + RES: + Bits12: [0, 12-bit] + Bits10: [1, 10-bit] + Bits8: [2, 8-bit] + Bits6: [3, 6-bit] + #DFSDMCFG: + # Disabled: [ 0, DFSDM mode disabled] + # Enabled: [ 1, DFSDM mode enabled] + DMACFG: + OneShot: [0, DMA One Shot mode selected] + Circular: [1, DMA Circular mode selected] + DMAEN: + Disabled: [0, DMA disabled] + Enabled: [1, DMA enabled] + +CFGR2: + ROVSM: + ContinuedMode: + [ + 0, + "When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)", + ] + ResumedMode: + [ + 1, + "When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)", + ] + TOVS,TROVS: + All: [0, All oversampled conversions for a channel are done consecutively following a trigger] + Single: [1, Each oversampled conversion for a channel needs a new trigger] + OVSS: + NoShift: [0, No Shift] + Shift1Bit: [1, Shift 1-bit] + Shift2Bit: [2, Shift 2-bit] + Shift3Bit: [3, Shift 3-bit] + Shift4Bit: [4, Shift 4-bit] + Shift5Bit: [5, Shift 5-bit] + Shift6Bit: [6, Shift 6-bit] + Shift7Bit: [7, Shift 7-bit] + Shift8Bit: [8, Shift 8-bit] + OVSR: + Ratio2: [0, 2x] + Ratio4: [1, 4x] + Ratio8: [2, 8x] + Ratio16: [3, 16x] + Ratio32: [4, 32x] + Ratio64: [5, 64x] + Ratio128: [6, 128x] + Ratio256: [7, 256x] + JOVSE: + Disabled: [0, Injected Oversampling disabled] + Enabled: [1, Injected Oversampling enabled] + ROVSE: + Disabled: [0, Regular Oversampling disabled] + Enabled: [1, Regular Oversampling enabled] + +SMPR?: + SMP?,SMP??: + Cycles2_5: [0, 2.5 ADC clock cycles] + Cycles6_5: [1, 6.5 ADC clock cycles] + Cycles12_5: [2, 12.5 ADC clock cycles] + Cycles24_5: [3, 24.5 ADC clock cycles] + Cycles47_5: [4, 47.5 ADC clock cycles] + Cycles92_5: [5, 92.5 ADC clock cycles] + Cycles247_5: [6, 247.5 ADC clock cycles] + Cycles640_5: [7, 640.5 ADC clock cycles] + +TR1: + HT1: [0, 0xFFF] + LT1: [0, 0xFFF] + +TR2: + HT2: [0, 0xFF] + LT2: [0, 0xFF] + +TR3: + HT3: [0, 0xFF] + LT3: [0, 0xFF] + +DR: + RDATA: [0, 0xFFFF] + +OFR?: + "OFFSET?_EN,OFFSET_EN": + Disabled: [0, "This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]"] + Enabled: [1, "This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0]"] + "OFFSET?_CH,OFFSET_CH": [0, 0x1F] + "OFFSET?,OFFSET": [0, 0xFFF] + +JDR?: + JDATA: [0, 0xFFFF] + +CALFACT: + CALFACT_D: [0, 0x7F] + CALFACT_S: [0, 0x7F] + +JSQR: + JEXTSEL: + TIM1_TRGO: [0, Timer 1 TRGO event] + TIM1_CC4: [1, Timer 1 CC4 event] + TIM2_TRGO: [2, Timer 2 TRGO event] + TIM2_CC1: [3, Timer 2 CC1 event] + TIM3_CC4: [4, Timer 3 CC4 event] + EXTI15: [6, EXTI line 15] + TIM1_TRGO2: [8, Timer 1 TRGO2 event] + TIM3_CC3: [11, Timer 3 CC3 event] + TIM3_TRGO: [12, Timer 3 TRGO event] + TIM3_CC1: [13, Timer 3 CC1 event] + TIM6_TRGO: [14, Timer 6 TRGO event] + TIM15_TRGO: [15, Timer 15 TRGO event] diff --git a/devices/fields/adc/awd0_18.yaml b/devices/fields/adc/awd0_18.yaml new file mode 100644 index 000000000..cad5c6b26 --- /dev/null +++ b/devices/fields/adc/awd0_18.yaml @@ -0,0 +1,2 @@ +CFGR: + AWD1CH: [0, 18] diff --git a/devices/fields/adc/awd0_19.yaml b/devices/fields/adc/awd0_19.yaml new file mode 100644 index 000000000..9adf2a1b0 --- /dev/null +++ b/devices/fields/adc/awd0_19.yaml @@ -0,0 +1,2 @@ +CFGR: + AWD1CH: [0, 19] diff --git a/devices/fields/adc/c0_g0_wl.yaml b/devices/fields/adc/c0_g0_wl.yaml new file mode 100644 index 000000000..10325be33 --- /dev/null +++ b/devices/fields/adc/c0_g0_wl.yaml @@ -0,0 +1,269 @@ +# ADC as used on the WL family + +ISR: + CCRDY: + _read: + NotComplete: [0, Channel configuration update not applied] + Complete: [1, Channel configuration update is applied] + _W1C: + Clear: [1, Clear the channel configuration flag] + EOCAL: + _read: + NotComplete: [0, Calibration is not complete] + Complete: [1, Calibration complete] + _W1C: + Clear: [1, Clear the calibration flag] + "AWD[123]": + _read: + NoEvent: [0, No analog watchdog event occurred] + Event: [1, Analog watchdog event occurred] + _W1C: + Clear: [1, Clear the analog watchdog event flag] + OVR: + _read: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + _W1C: + Clear: [1, Clear the overrun flag] + EOS: + _read: + NotComplete: [0, Conversion sequence is not complete] + Complete: [1, Conversion sequence complete] + _W1C: + Clear: [1, Clear the conversion sequence flag] + EOC: + _read: + NotComplete: [0, Channel conversion is not complete] + Complete: [1, Channel conversion complete] + _W1C: + Clear: [1, Clear the channel conversion flag] + EOSMP: + _read: + NotAtEnd: [0, Not at the end of the samplings phase] + AtEnd: [1, End of sampling phase reached] + _W1C: + Clear: [1, Clear the sampling phase flag] + ADRDY: + _read: + NotReady: [0, ADC not yet ready to start conversion] + Ready: [1, ADC ready to start conversion] + _W1C: + Clear: [1, Clear the ADC ready flag] +IER: + CCRDYIE: + Disabled: [0, Channel configuration ready interrupt disabled] + Enabled: [1, Channel configuration ready interrupt enabled] + EOCALIE: + Disabled: [0, End of calibration interrupt disabled] + Enabled: [1, End of calibration interrupt enabled] + "AWD[123]IE": + Disabled: [0, Analog watchdog interrupt disabled] + Enabled: [1, Analog watchdog interrupt enabled] + OVRIE: + Disabled: [0, Overrun interrupt disabled] + Enabled: [1, Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.] + EOSIE: + Disabled: [0, EOS interrupt disabled] + Enabled: [1, EOS interrupt enabled. An interrupt is generated when the EOS bit is set.] + EOCIE: + Disabled: [0, EOC interrupt disabled] + Enabled: [1, EOC interrupt enabled. An interrupt is generated when the EOC bit is set.] + EOSMPIE: + Disabled: [0, EOSMP interrupt disabled] + Enabled: [1, EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.] + ADRDYIE: + Disabled: [0, ADRDY interrupt disabled] + Enabled: [1, ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.] +CR: + ADCAL: + _read: + NotCalibrating: [0, ADC calibration either not yet performed or completed] + Calibrating: [1, ADC calibration in progress] + _W1S: + StartCalibration: [1, Start the ADC calibration sequence] + ADVREGEN: + Disabled: [0, ADC voltage regulator disabled] + Enabled: [1, ADC voltage regulator enabled] + ADSTP: + _read: + NotStopping: [0, No stop command active] + Stopping: [1, ADC stopping conversion] + _W1S: + StopConversion: [1, Stop the active conversion] + ADSTART: + _read: + NotActive: [0, No conversion ongoing] + Active: [1, ADC operating and may be converting] + _W1S: + StartConversion: [1, Start the ADC conversion (may be delayed for hardware triggers)] + ADDIS: + _read: + NotDisabling: [0, No disable command active] + Disabling: [1, ADC disabling] + _W1S: + Disable: [1, Disable the ADC] + ADEN: + _read: + Disabled: [0, ADC disabled] + Enabled: [1, ADC enabled] + _W1S: + Enabled: [1, Enable the ADC] +CFGR1: + AWD1CH: [0, 17] + AWD1EN: + Disabled: [0, Analog watchdog 1 disabled] + Enabled: [1, Analog watchdog 1 enabled] + AWD1SGL: + AllChannels: [0, Analog watchdog 1 enabled on all channels] + SingleChannel: [1, Analog watchdog 1 enabled on a single channel] + CHSELRMOD: + BitPerInput: [0, Each bit of the ADC_CHSELR register enables an input] + Sequence: [1, ADC_CHSELR register is able to sequence up to 8 channels] + DISCEN: + Disabled: [0, Discontinuous mode disabled] + Enabled: [1, Discontinuous mode enabled] + AUTOFF: + Disabled: [0, Auto-off mode disabled] + Enabled: [1, Auto-off mode enabled] + WAIT: + Disabled: [0, Wait conversion mode off] + Enabled: [1, Wait conversion mode on] + CONT: + Single: [0, Single conversion mode] + Continuous: [1, Continuous conversion mode] + OVRMOD: + Preserve: [0, ADC_DR register is preserved with the old data when an overrun is detected] + Overwrite: [1, ADC_DR register is overwritten with the last conversion result when an overrun is detected] + EXTEN: + Disabled: [0, Hardware trigger detection disabled] + RisingEdge: [1, Hardware trigger detection on the rising edge] + FallingEdge: [2, Hardware trigger detection on the falling edge] + BothEdges: [3, Hardware trigger detection on both the rising and falling edges] + EXTSEL: + TIM1_TRGO: [0, Timer 1 TRGO event] + TIM1_CC4: [1, Timer 1 CC4 event] + TIM2_TRGO: [2, Timer 2 TRGO event] + TIM2_CH4: [3, Timer 2 CH4 event] + #Reserved1: [4, Reserved - not forbidden but it has no effect] + TIM2_CH3: [5, Timer 2 CH3 event] + #Reserved2: [6, Reserved - not forbidden but it has no effect] + EXTI_LINE11: [7, EXTI line 11 event] + ALIGN: + Right: [0, Right alignment] + Left: [1, Left alignment] + RES: + Bits12: [0, 12 bits] + Bits10: [1, 10 bits] + Bits8: [2, 8 bits] + Bits6: [3, 6 bits] + SCANDIR: + Upward: [0, Upward scan (from CHSEL0 to CHSEL17)] + Backward: [1, Backward scan (from CHSEL17 to CHSEL0)] + DMACFG: + OneShot: [0, DMA one shot mode selected] + Circular: [1, DMA circular mode selected] + DMAEN: + Disabled: [0, DMA disabled] + Enabled: [1, DMA enabled] +CFGR2: + CKMODE: + ADCLK: [0, ADCCLK (Asynchronous clock mode)] + PCLK_Div2: [1, PCLK/2 (Synchronous clock mode)] + PCLK_Div4: [2, PCLK/4 (Synchronous clock mode)] + PCLK: [3, PCLK (Synchronous clock mode)] + LFTRIG: + Disabled: [0, Low Frequency Trigger Mode disabled] + Enabled: [1, Low Frequency Trigger Mode enabled] + TOVS: + TriggerAll: [0, All oversampled conversions for a channel are done consecutively after a trigger] + TriggerEach: [1, Each oversampled conversion for a channel needs a trigger] + OVSS: + NoShift: [0, No shift] + Shift1: [1, Shift 1-bit] + Shift2: [2, Shift 2-bits] + Shift3: [3, Shift 3-bits] + Shift4: [4, Shift 4-bits] + Shift5: [5, Shift 5-bits] + Shift6: [6, Shift 6-bits] + Shift7: [7, Shift 7-bits] + Shift8: [8, Shift 8-bits] + OVSR: + Mul2: [0, 2x] + Mul4: [1, 4x] + Mul8: [2, 8x] + Mul16: [3, 16x] + Mul32: [4, 32x] + Mul64: [5, 64x] + Mul128: [6, 128x] + Mul256: [7, 256x] + OVSE: + Disabled: [0, Oversampler disabled] + Enabled: [1, Oversampler enabled] +SMPR: + SMPSEL*: + Smp1: [0, Sampling time of CHANNELx use the setting of SMP1 register] + Smp2: [1, Sampling time of CHANNELx use the setting of SMP2 register] + SMP?: + Cycles1_5: [0, 1.5 ADC clock cycles] + Cycles3_5: [1, 3.5 ADC clock cycles] + Cycles7_5: [2, 7.5 ADC clock cycles] + Cycles12_5: [3, 12.5 ADC clock cycles] + Cycles19_5: [4, 19.5 ADC clock cycles] + Cycles39_5: [5, 39.5 ADC clock cycles] + Cycles79_5: [6, 79.5 ADC clock cycles] + Cycles160_5: [7, 160.5 ADC clock cycles] +AWD?TR: + HT?: [0, 4095] + LT?: [0, 4095] +CHSELR0: + CHSEL*: + NotSelected: [0, Input Channel is not selected for conversion] + Selected: [1, Input Channel is selected for conversion] +CHSELR1: + SQ*: + Ch0: [0, Channel 0 selected for the Nth conversion] + Ch1: [1, Channel 1 selected for the Nth conversion] + Ch2: [2, Channel 2 selected for the Nth conversion] + Ch3: [3, Channel 3 selected for the Nth conversion] + Ch4: [4, Channel 4 selected for the Nth conversion] + Ch5: [5, Channel 5 selected for the Nth conversion] + Ch6: [6, Channel 6 selected for the Nth conversion] + Ch7: [7, Channel 7 selected for the Nth conversion] + Ch8: [8, Channel 8 selected for the Nth conversion] + Ch9: [9, Channel 9 selected for the Nth conversion] + Ch10: [10, Channel 10 selected for the Nth conversion] + Ch11: [11, Channel 11 selected for the Nth conversion] + Ch12: [12, Channel 12 selected for the Nth conversion] + Ch13: [13, Channel 13 selected for the Nth conversion] + Ch14: [14, Channel 14 selected for the Nth conversion] + EOS: [15, End of sequence] + +DR: + DATA: [0, 65535] +CALFACT: + CALFACT: [0, 127] +AWD2CR: + AWD2CH*: + NotMonitored: [0, ADC analog channel-x is not monitored by AWD2] + Monitored: [1, ADC analog channel-x is monitored by AWD2] +AWD3CR: + AWD3CH*: + NotMonitored: [0, ADC analog channel-x is not monitored by AWD3] + Monitored: [1, ADC analog channel-x is monitored by AWD3] +CCR: + VBATEN,TSEN,VREFEN: + Disabled: [0, The selected ADC channel disabled] + Enabled: [1, The selected ADC channel enabled] + PRESC: + Div1: [0, Input ADC clock not divided] + Div2: [1, Input ADC clock divided by 2] + Div4: [2, Input ADC clock divided by 4] + Div6: [3, Input ADC clock divided by 6] + Div8: [4, Input ADC clock divided by 8] + Div10: [5, Input ADC clock divided by 10] + Div12: [6, Input ADC clock divided by 12] + Div16: [7, Input ADC clock divided by 16] + Div32: [8, Input ADC clock divided by 32] + Div64: [9, Input ADC clock divided by 64] + Div128: [10, Input ADC clock divided by 128] + Div256: [11, Input ADC clock divided by 256] diff --git a/devices/fields/aes/aes256.yaml b/devices/fields/aes/aes256.yaml new file mode 100644 index 000000000..f98ae3cc4 --- /dev/null +++ b/devices/fields/aes/aes256.yaml @@ -0,0 +1,17 @@ +CR: + "?~NPBLB": [0, 0xF] + KEYSIZE: + AES128: [0, "128"] + AES256: [1, "256"] + GCMPH: + Init: [0, Init phase] + Header: [1, Header phase] + Payload: [2, Payload phase] + Final: [3, Final Phase] +SR: + BUSY: + Idle: [0, Idle] + Busy: [1, Busy] + +SUSP?R: + SUSP: [0, 0xFFFFFFFF] diff --git a/devices/fields/aes/chmod2b.yaml b/devices/fields/aes/chmod2b.yaml new file mode 100644 index 000000000..d00a07a25 --- /dev/null +++ b/devices/fields/aes/chmod2b.yaml @@ -0,0 +1,5 @@ +CR: + CHMOD: + ECB: [0, Electronic codebook (ECB)] + CBC: [1, Cipher-Block Chaining (CBC)] + CTR: [2, Counter Mode (CTR)] diff --git a/devices/fields/aes/chmod3b.yaml b/devices/fields/aes/chmod3b.yaml new file mode 100644 index 000000000..e4bf605a8 --- /dev/null +++ b/devices/fields/aes/chmod3b.yaml @@ -0,0 +1,9 @@ +CR: + "CHMOD,CHMOD1,CHMOD10": + ECB: [0, Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1] + CBC: [1, Cipher-block chaining (CBC)] + CTR: [2, Counter mode (CTR)] + GCM: [3, Galois counter mode (GCM) and Galois message authentication code (GMAC)] + "CHMOD2,CHMOD_2": + CHMOD: [0, "Mode as per CHMOD (ECB, CBC, CTR, GCM)"] + CCM: [1, Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)] diff --git a/devices/fields/aes/common.yaml b/devices/fields/aes/common.yaml new file mode 100644 index 000000000..be4ac26ef --- /dev/null +++ b/devices/fields/aes/common.yaml @@ -0,0 +1,43 @@ +CR: + DMAOUTEN: + Disabled: [0, Disable DMA Output] + Enabled: [1, Enabled DMA Output] + DMAINEN: + Disabled: [0, Disable DMA Input] + Enabled: [1, Enable DMA Input] + MODE: + Mode1: [0, "Mode 1: encryption"] + Mode2: [1, "Mode 2: key derivation (or key preparation for ECB/CBC decryption)"] + Mode3: [2, "Mode 3: decryption"] + Mode4: [3, "Mode 4: key derivation then single decryption"] + DATATYPE: + None: [0, Word] + HalfWord: [1, Half-word (16-bit)] + Byte: [2, Byte (8-bit)] + Bit: [3, Bit] + EN: + Disabled: [0, Disable AES] + Enabled: [1, Enable AES] + +SR: + WRERR: + NoError: [0, Write error not detected] + Error: [1, Write error detected] + RDERR: + NoError: [0, Read error not detected] + Error: [1, Read error detected] + CCF: + Complete: [0, Computation complete] + NotComplete: [1, Computation not complete] + +DINR: + DIN: [0, 0xFFFFFFFF] + +DOUTR: + DOUT: [0, 0xFFFFFFFF] + +"KEYR[01234567]": + "KEY*,AES_KEYR*": [0, 0xFFFFFFFF] + +"IVR[0123]": + "IVI*,AES_IVR*": [0, 0xFFFFFFFF] diff --git a/devices/fields/aes/cr_irq.yaml b/devices/fields/aes/cr_irq.yaml new file mode 100644 index 000000000..043483898 --- /dev/null +++ b/devices/fields/aes/cr_irq.yaml @@ -0,0 +1,13 @@ +CR: + ERRIE: + Disabled: [0, Disable (mask) error interrupt] + Enabled: [1, Enable error interrupt] + CCFIE: + Disabled: [0, Disable (mask) CCF interrupt] + Enabled: [1, Enable CCF interrupt] + ERRC: + _write: + Clear: [1, Clear RDERR and WRERR flags] + CCFC: + _write: + Clear: [1, Clear computation complete flag] diff --git a/devices/fields/aes/v1.yaml b/devices/fields/aes/v1.yaml new file mode 100644 index 000000000..1dac27bf4 --- /dev/null +++ b/devices/fields/aes/v1.yaml @@ -0,0 +1,4 @@ +_include: + - common.yaml + - cr_irq.yaml + - chmod2b.yaml diff --git a/devices/fields/aes/v2.yaml b/devices/fields/aes/v2.yaml new file mode 100644 index 000000000..cd21603da --- /dev/null +++ b/devices/fields/aes/v2.yaml @@ -0,0 +1,5 @@ +_include: + - common.yaml + - cr_irq.yaml + - chmod3b.yaml + - aes256.yaml diff --git a/devices/fields/aes/v3.yaml b/devices/fields/aes/v3.yaml new file mode 100644 index 000000000..7e5a2ba82 --- /dev/null +++ b/devices/fields/aes/v3.yaml @@ -0,0 +1,28 @@ +_include: + - common.yaml + - chmod3b.yaml + - aes256.yaml + +CR: + KMOD: + NormalKey: [0, Normal key mode. Key registers are freely usable] + SharedKey: + [ + 2, + "Shared key mode. If shared key mode is properly initialized in SAES peripheral, the AES peripheral automatically loads its key registers with the data stored in the SAES key registers. The key value is available in AES key registers when BUSY bit is cleared and KEYVALID is set in the AES_SR register. Key error flag KEIF is set otherwise in the AES_ISR register", + ] +IER: + "*IE": + Disabled: [0, Interrupt is disabled (masked)] + Enabled: [1, Interrupt is enabled (not masked)] +ISR: + "*IF": + NoError: [0, No error detected] + Error: [1, The error detected] + CCF: + NotCompleted: [0, Computation not completed] + Completed: [1, Computation completed] +ICR: + "*": + _write: + Clear: [1, Setting this bit clears corresponding interrupt status bit] diff --git a/devices/fields/axi/axi_v1.yaml b/devices/fields/axi/axi_v1.yaml new file mode 100644 index 000000000..9540f7814 --- /dev/null +++ b/devices/fields/axi/axi_v1.yaml @@ -0,0 +1,13 @@ +# Advanced eXtensible Interface (AXI) management on H7 + +INI?_FN_MOD: + WRITE_ISS_OVERRIDE: + Normal: [0, Normal ASIB write issuing capability] + Force1: [1, Force ASIB write issuing capability to 1] + READ_ISS_OVERRIDE: + Normal: [0, Normal ASIB read issuing capability] + Force1: [1, Force ASIB read issuing capability to 1] +INI?_READ_QOS: + AR_QOS: [0, 0xF] +INI?_WRITE_QOS: + AW_QOS: [0, 0xF] diff --git a/devices/fields/bkp/bkp.yaml b/devices/fields/bkp/bkp.yaml new file mode 100644 index 000000000..9e101f9c6 --- /dev/null +++ b/devices/fields/bkp/bkp.yaml @@ -0,0 +1,29 @@ +RTCCR: + ASOS: + Alarm: [0, RTC Alarm pulse output selected] + Second: [1, RTC Second pulse output selected] + ASOE: + Disabled: [0, Disabled] + Enabled: + [ + 1, + Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit, + ] + CAL: [0, 121] +CR: + TPAL: + High: [0, A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)] + Low: [1, A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)] + TPE: + General: [0, The TAMPER pin is free for general purpose I/O] + Alternate: [1, Tamper alternate I/O function is activated] +CSR: + TPIE: + Disabled: [0, Tamper interrupt disabled] + Enabled: [1, Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register] + CTI: + _write: + Clear: [1, Clear the Tamper interrupt and the TIF Tamper interrupt flag] + CTE: + _write: + Reset: [1, Reset the TEF Tamper event flag (and the Tamper detector)] diff --git a/devices/fields/can/can.yaml b/devices/fields/can/can.yaml new file mode 100644 index 000000000..280d54a05 --- /dev/null +++ b/devices/fields/can/can.yaml @@ -0,0 +1,133 @@ +#MCR: + +#MSR: + +#TSR: + +RF?R: + RFOM?: + _write: + Release: [1, Set by software to release the output mailbox of the FIFO] + FOVR?: + _read: + NoOverrun: [0, No FIFO x overrun] + Overrun: [1, FIFO x overrun] + _write: + Clear: [1, Clear flag] + FULL?: + _read: + NotFull: [0, FIFO x is not full] + Full: [1, FIFO x is full] + _write: + Clear: [1, Clear flag] + #FMP?: + +IER: + SLKIE: + Disabled: [0, No interrupt when SLAKI bit is set] + Enabled: [1, Interrupt generated when SLAKI bit is set] + WKUIE: + Disabled: [0, No interrupt when WKUI is set] + Enabled: [1, Interrupt generated when WKUI bit is set] + ERRIE: + Disabled: [0, No interrupt will be generated when an error condition is pending in the CAN_ESR] + Enabled: [1, An interrupt will be generation when an error condition is pending in the CAN_ESR] + LECIE: + Disabled: [0, "ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection"] + Enabled: [1, "ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection"] + BOFIE: + Disabled: [0, ERRI bit will not be set when BOFF is set] + Enabled: [1, ERRI bit will be set when BOFF is set] + EPVIE: + Disabled: [0, ERRI bit will not be set when EPVF is set] + Enabled: [1, ERRI bit will be set when EPVF is set] + EWGIE: + Disabled: [0, ERRI bit will not be set when EWGF is set] + Enabled: [1, ERRI bit will be set when EWGF is set] + FOVIE1: + Disabled: [0, No interrupt when FOVR is set] + Enabled: [1, Interrupt generation when FOVR is set] + FFIE1: + Disabled: [0, No interrupt when FULL bit is set] + Enabled: [1, Interrupt generated when FULL bit is set] + FMPIE1: + Disabled: [0, "No interrupt generated when state of FMP[1:0] bits are not 00b"] + Enabled: [1, "Interrupt generated when state of FMP[1:0] bits are not 00b"] + FOVIE0: + Disabled: [0, No interrupt when FOVR bit is set] + Enabled: [1, Interrupt generated when FOVR bit is set] + FFIE0: + Disabled: [0, No interrupt when FULL bit is set] + Enabled: [1, Interrupt generated when FULL bit is set] + FMPIE0: + Disabled: [0, "No interrupt generated when state of FMP[1:0] bits are not 00"] + Enabled: [1, "Interrupt generated when state of FMP[1:0] bits are not 00b"] + TMEIE: + Disabled: [0, No interrupt when RQCPx bit is set] + Enabled: [1, Interrupt generated when RQCPx bit is set] + +ESR: + #REC: + #TEC: + LEC: + NoError: [0, No Error] + Stuff: [1, Stuff Error] + Form: [2, Form Error] + Ack: [3, Acknowledgment Error] + BitRecessive: [4, Bit recessive Error] + BitDominant: [5, Bit dominant Error] + Crc: [6, CRC Error] + Custom: [7, Set by software] + #BOFF: + #EPVF: + #EWGF: + +BTR: + SILM: + Normal: [0, Normal operation] + Silent: [1, Silent Mode] + LBKM: + Disabled: [0, Loop Back Mode disabled] + Enabled: [1, Loop Back Mode enabled] + #SJW: + #TS2: + #TS1: + #BRP: + +TI?R: + #STID: + #EXID: + IDE: + Standard: [0, Standard identifier] + Extended: [1, Extended identifier] + RTR: + Data: [0, Data frame] + Remote: [1, Remote frame] + #TXRQ: + +TDT?R: + #TIME: + #TGT: + DLC: [0, 8] + +#TDL?R: + +#TDH?R: + +RI?R: + #STID: + #EXID: + IDE: + Standard: [0, Standard identifier] + Extended: [1, Extended identifier] + RTR: + Data: [0, Data frame] + Remote: [1, Remote frame] + +RDT?R: + #TIME: + #FMI: + DLC: [0, 8] +#RDL?R: + +#RDH?R: diff --git a/devices/fields/comp/comp_f0.yaml b/devices/fields/comp/comp_f0.yaml new file mode 100644 index 000000000..8fa52d1ad --- /dev/null +++ b/devices/fields/comp/comp_f0.yaml @@ -0,0 +1,86 @@ +COMP: + CSR: + COMP1EN: + Disabled: [0, Comparator 1 disabled] + Enabled: [1, Comparator 1 enabled] + COMP1SW1: + Open: [0, Switch open] + Closed: [1, Switch closed] + COMP1MODE: + HighSpeed: [0, High speed / full power] + MediumSpeed: [1, Medium speed / medium power] + LowSpeed: [2, Low speed / low power] + VeryLowSpeed: [3, Very-low speed / ultra-low power] + COMP1INSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + Comp1_INM4: [4, COMP1_INM4 (PA4 with DAC_OUT1 if enabled)] + Comp1_INM5: [5, COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)] + Comp1_INM6: [6, COMP1_INM6 (PA0)] + COMP1OUTSEL: + NoSelection: [0, No selection] + Timer1BreakInput: [1, Timer 1 break input] + Timer1InputCapture1: [2, Timer 1 Input capture 1] + Timer1OCRefClearInput: [3, Timer 1 OCrefclear input] + Timer2InputCapture4: [4, Timer 2 input capture 4] + Timer2OCRefClearInput: [5, Timer 2 OCrefclear input] + Timer3InputCapture1: [6, Timer 3 input capture 1] + Timer3OCRefClearInput: [7, Timer 3 OCrefclear input] + COMP1POL: + NotInverted: [0, Output is not inverted] + Inverted: [1, Output is inverted] + COMP1HYST: + NoHysteresis: [0, No hysteresis] + LowHysteresis: [1, Low hysteresis] + MediumHysteresis: [2, Medium hysteresis] + HighHysteresis: [3, High hysteresis] + COMP1OUT: + Low: [0, Non-inverting input below inverting input] + High: [1, Non-inverting input above inverting input] + COMP1LOCK: + Unlocked: [0, "Comparator 1 CSR bits (CSR[15:0]) are read-write"] + Locked: [1, "Comparator 1 CSR bits (CSR[15:0]) are read-only"] + COMP2EN: + Disabled: [0, Comparator 2 disabled] + Enabled: [1, Comparator 2 enabled] + COMP2MODE: + HighSpeed: [0, High speed / full power] + MediumSpeed: [1, Medium speed / medium power] + LowSpeed: [2, Low speed / low power] + VeryLowSpeed: [3, Very-low speed / ultra-low power] + COMP2INSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + Comp2_INM4: [4, COMP1_INM4 (PA4 with DAC_OUT1 if enabled)] + Comp2_INM5: [5, COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)] + Comp2_INM6: [6, COMP1_INM6 (PA2)] + WNDWEN: + Disabled: [0, Window mode disabled] + Enabled: [1, Window mode enabled] + COMP2OUTSEL: + NoSelection: [0, No selection] + Timer1BreakInput: [1, Timer 1 break input] + Timer1InputCapture1: [2, Timer 1 Input capture 1] + Timer1OCRefClearInput: [3, Timer 1 OCrefclear input] + Timer2InputCapture4: [4, Timer 2 input capture 4] + Timer2OCRefClearInput: [5, Timer 2 OCrefclear input] + Timer3InputCapture1: [6, Timer 3 input capture 1] + Timer3OCRefClearInput: [7, Timer 3 OCrefclear input] + COMP2POL: + NotInverted: [0, Output is not inverted] + Inverted: [1, Output is inverted] + COMP2HYST: + NoHysteresis: [0, No hysteresis] + LowHysteresis: [1, Low hysteresis] + MediumHysteresis: [2, Medium hysteresis] + HighHysteresis: [3, High hysteresis] + COMP2OUT: + Low: [0, Non-inverting input below inverting input] + High: [1, Non-inverting input above inverting input] + COMP2LOCK: + Unlocked: [0, "Comparator 2 CSR bits (CSR[31:16]) are read-write"] + Locked: [1, "Comparator 2 CSR bits (CSR[31:16]) are read-only"] diff --git a/devices/fields/comp/comp_f3.yaml b/devices/fields/comp/comp_f3.yaml new file mode 100644 index 000000000..a2b804e20 --- /dev/null +++ b/devices/fields/comp/comp_f3.yaml @@ -0,0 +1,83 @@ +COMP: + COMP[246]_CSR: + COMP[246]EN: + Disabled: [0, Comparator disabled] + Enabled: [1, Comparator enabled] + COMP[246]POL: + NotInverted: [0, Output is not inverted] + Inverted: [1, Output is inverted] + COMP[246]OUT: + Low: [0, Non-inverting input below inverting input] + High: [1, Non-inverting input above inverting input] + COMP[246]LOCK: + Unlocked: [0, Comparator CSR bits are read-write] + Locked: [1, Comparator CSR bits are read-only] + + COMP2_CSR: + COMP2INMSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + PA4_DAC1_CH1: [4, PA4 or DAC1_CH1 output if enabled] + DAC1_CH2: [5, DAC1_CH2] + PA2: [6, PA2] + COMP2OUTSEL: + NoSelection: [0, No selection] + Timer1BreakInput: [1, Timer 1 break input] + Timer1BreakInput2: [2, Timer 1 break input 2] + Timer1OCRefClearInput: [6, Timer 1 OCREF_CLR input] + Timer1InputCapture1: [7, Timer 1 input capture 1] + Timer2InputCapture4: [8, Timer 2 input capture 4] + Timer2OCRefClearInput: [9, Timer 2 OCREF_CLR input] + Timer3InputCapture1: [10, Timer 3 input capture 1] + Timer3OCRefClearInput: [11, Timer 3 OCREF_CLR input] + COMP2_BLANKING: + NoBlanking: [0, No blanking] + TIM1OC5: [1, TIM1 OC5 selected as blanking source] + TIM2OC3: [2, TIM2 OC3 selected as blanking source] + TIM3OC3: [3, TIM3 OC3 selected as blanking source] + + COMP4_CSR: + COMP4INMSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + PA4_DAC1_CH1: [4, PA4 or DAC1_CH1 output if enabled] + DAC1_CH2: [5, DAC1_CH2] + PB2: [7, PB2] + COMP4OUTSEL: + NoSelection: [0, No selection] + Timer1BreakInput: [1, Timer 1 break input] + Timer1BreakInput2: [2, Timer 1 break input 2] + Timer3InputCapture3: [6, Timer 3 input capture 3] + Timer15InputCapture2: [8, Timer 15 input capture 2] + Timer15OCRefClearInput: [10, Timer 15 OCREF_CLR input] + Timer3OCRefClearInput: [11, Timer 3 OCREF_CLR input] + COMP4_BLANKING: + NoBlanking: [0, No blanking] + TIM3OC4: [1, TIM3 OC4 selected as blanking source] + TIM15OC1: [3, TIM15 OC1 selected as blanking source] + + COMP6_CSR: + COMP6INMSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + PA4_DAC1_CH1: [4, PA4 or DAC1_CH1 output if enabled] + DAC1_CH2: [5, DAC1_CH2] + PB15: [7, PB15] + COMP6OUTSEL: + NoSelection: [0, No selection] + Timer1BreakInput: [1, Timer 1 break input] + Timer1BreakInput2: [2, Timer 1 break input 2] + Timer2InputCapture2: [6, Timer 2 input capture 2] + Timer2OCRefClearInput: [8, Timer 2 OCREF_CLR input] + Timer16OCRefClearInput: [9, Timer 16 OCREF_CLR input] + Timer16InputCapture1: [10, Timer 16 input capture 1] + COMP6_BLANKING: + NoBlanking: [0, No blanking] + TIM2OC4: [3, TIM2 OC4 selected as blanking source] + TIM15OC2: [4, TIM15 OC2 selected as blanking source] diff --git a/devices/fields/comp/comp_l4+.yaml b/devices/fields/comp/comp_l4+.yaml new file mode 100644 index 000000000..015e3dbf0 --- /dev/null +++ b/devices/fields/comp/comp_l4+.yaml @@ -0,0 +1,46 @@ +COMP: + COMP?_CSR: + LOCK: + Unlocked: [0, "COMPx_CSR[31:0] for comparator x are read/write"] + Locked: [1, "COMPx_CSR[31:0] for comparator x are read-only"] + SCALEN: + Disabled: [0, Bandgap scaler disabled (if SCALEN bit of COMP2_CSR register is also reset)] + Enabled: [1, Bandgap scaler enabled] + BRGEN: + Disabled: [0, Scaler resistor bridge disabled (if BRGEN bit of COMP2_CSR register is also reset)] + Enabled: [1, Scaler resistor bridge enabled] + HYST: + None: [0, No hysteresis] + Low: [1, Low hysteresis] + Medium: [2, Medium hysteresis] + High: [3, High hysteresis] + POLARITY: + Normal: [0, Comparator x output value not inverted] + Inverted: [1, Comparator x output value inverted] + PWRMODE: + High: [0, High speed] + Medium: [1, Medium speed] + Low: [3, Ultra low power] + EN: + Disabled: [0, Comparator x switched OFF] + Enabled: [1, Comparator x switched ON] + + COMP1_CSR: + BLANKING: + Disabled: [0, No blanking] + TIM1OC5: [1, TIM1 OC5 selected as blanking source] + TIM2OC3: [2, TIM2 OC3 selected as blanking source] + INPSEL: + External: [0, external IO - PC5] + PB2: [1, PB2] + + COMP2_CSR: + BLANKING: + Disabled: [0, No blanking] + TIM15OC1: [4, TIM15 OC1 selected as blanking source] + WINMODE: + Disabled: [0, Input plus of Comparator 2 is not connected to Comparator 1] + Enabled: [1, Input plus of Comparator 2 is connected with input plus of Comparator 1] + INPSEL: + PB4: [0, PB4] + PB6: [1, PB6] diff --git a/devices/fields/comp/comp_l4x1.yaml b/devices/fields/comp/comp_l4x1.yaml new file mode 100644 index 000000000..e2b331c32 --- /dev/null +++ b/devices/fields/comp/comp_l4x1.yaml @@ -0,0 +1,75 @@ +COMP: + COMP?_CSR: + # LOCK: + # Unlocked: [0, Comparator CSR bits are read-write] + # Locked: [1, Comparator CSR bits are read-only] + #COMP?_VALUE: + VALUE: + Low: [0, Comparator output is low] + High: [1, Comparator output is high] + SCALEN: + Disabled: [0, Voltage scaler disabled] + Enabled: [1, Voltage scaler enabled] + BRGEN: + Disabled: [0, Scaler resistor bridge disabled] + Enabled: [1, Scaler resistor bridge enabled] + BLANKING: + NoBlanking: [0, No blanking] + TIM1OC5: [4, TIM15 OC1 selected as blanking source] + HYST: + NoHysteresis: [0, No hysteresis] + LowHysteresis: [1, Low hysteresis] + MediumHysteresis: [2, Medium hysteresis] + HighHysteresis: [3, High hysteresis] + POLARITY: + NotInverted: [0, Output is not inverted] + Inverted: [1, Output is inverted] + PWRMODE: + HighSpeed: [0, High speed / full power] + MediumSpeed: [1, Medium speed / medium power] + LowSpeed: [3, Low speed / ultra-low power] + EN: + Disabled: [0, Comparator 1 disabled] + Enabled: [1, Comparator 1 enabled] + + COMP1_CSR: + INPSEL: + PC5: [0, PC5 connected to input plus] + PB2: [1, PB2 connected to input plus] + PA3: [2, PA3 connected to input plus] + INMSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + DAC_CH1: [4, DAC Channel 1] + DAC_CH2: [5, DAC Channel 2] + GPIOx: [6, GPIO selected with INMESEL] + INMESEL: + PC4: [0, PC4] + PA0: [1, PA0] + PA4: [2, PA4] + PA5: [3, PA5] + + COMP2_CSR: + WINMODE: + Disabled: [0, COMP2 input plus is not connected to COMP1] + Enabled: [1, COMP2 input plus is connected to COMP1 plus] + INPSEL: + PB4: [0, PB4 connected to input plus] + PB6: [1, PB6 connected to input plus] + PA3: [2, PA3 connected to input plus] + INMSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + DAC_CH1: [4, DAC Channel 1] + DAC_CH2: [5, DAC Channel 2] + PB3: [6, PB3] + GPIOx: [7, GPIO selected by INMESEL] + INMESEL: + PB7: [0, PB7] + PA2: [1, PA2] + PA4: [2, PA4] + PA5: [3, PA5] diff --git a/devices/fields/comp/comp_l4x6.yaml b/devices/fields/comp/comp_l4x6.yaml new file mode 100644 index 000000000..c52732e81 --- /dev/null +++ b/devices/fields/comp/comp_l4x6.yaml @@ -0,0 +1,63 @@ +COMP: + COMP?_CSR: + # LOCK: + # Unlocked: [0, Comparator CSR bits are read-write] + # Locked: [1, Comparator CSR bits are read-only] + #COMP?_VALUE: + VALUE: + Low: [0, Comparator output is low] + High: [1, Comparator output is high] + SCALEN: + Disabled: [0, Voltage scaler disabled] + Enabled: [1, Voltage scaler enabled] + BRGEN: + Disabled: [0, Scaler resistor bridge disabled] + Enabled: [1, Scaler resistor bridge enabled] + BLANKING: + NoBlanking: [0, No blanking] + TIM1OC5: [4, TIM15 OC1 selected as blanking source] + HYST: + NoHysteresis: [0, No hysteresis] + LowHysteresis: [1, Low hysteresis] + MediumHysteresis: [2, Medium hysteresis] + HighHysteresis: [3, High hysteresis] + POLARITY: + NotInverted: [0, Output is not inverted] + Inverted: [1, Output is inverted] + PWRMODE: + HighSpeed: [0, High speed / full power] + MediumSpeed: [1, Medium speed / medium power] + LowSpeed: [3, Low speed / ultra-low power] + EN: + Disabled: [0, Comparator 1 disabled] + Enabled: [1, Comparator 1 enabled] + + COMP1_CSR: + INPSEL: + PC5: [0, PC5 connected to input plus] + PB2: [1, PB2 connected to input plus] + INMSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + DAC_CH1: [4, DAC Channel 1] + DAC_CH2: [5, DAC Channel 2] + PC4: [6, PC4] + + COMP2_CSR: + WINMODE: + Disabled: [0, COMP2 input plus is not connected to COMP1] + Enabled: [1, COMP2 input plus is connected to COMP1 plus] + INPSEL: + PB4: [0, PB4 connected to input plus] + PB6: [1, PB6 connected to input plus] + INMSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + DAC_CH1: [4, DAC Channel 1] + DAC_CH2: [5, DAC Channel 2] + PB3: [6, PB3] + PB7: [7, PB7] diff --git a/devices/fields/comp/comp_wl.yaml b/devices/fields/comp/comp_wl.yaml new file mode 100644 index 000000000..c6efc1828 --- /dev/null +++ b/devices/fields/comp/comp_wl.yaml @@ -0,0 +1,64 @@ +COMP: + COMP?_CSR: + LOCK: + Unlocked: [0, Comparator CSR bits are read-write] + Locked: [1, Comparator CSR bits are read-only] + VALUE: + Low: [0, Comparator output is low] + High: [1, Comparator output is high] + SCALEN: + Disabled: [0, Voltage scaler disabled] + Enabled: [1, Voltage scaler enabled] + BRGEN: + Disabled: [0, Scaler resistor bridge disabled] + Enabled: [1, Scaler resistor bridge enabled] + BLANKING: + NoBlanking: [0, No blanking] + TIM1OC5: [1, TIM1 OC5 selected as blanking source] + TIM2OC3: [2, TIM2 OC3 selected as blanking source] + HYST: + NoHysteresis: [0, No hysteresis] + LowHysteresis: [1, Low hysteresis] + MediumHysteresis: [2, Medium hysteresis] + HighHysteresis: [3, High hysteresis] + POLARITY: + NotInverted: [0, Output is not inverted] + Inverted: [1, Output is inverted] + INMSEL: + OneQuarterVRef: [0, 1/4 of VRefint] + OneHalfVRef: [1, 1/2 of VRefint] + ThreeQuarterVRef: [2, 3/4 of VRefint] + VRef: [3, VRefint] + DAC_CH1: [4, DAC Channel 1] + PB3: [6, PB3] + GPIO: [7, GPIO pin selected by INMESEL] + PWRMODE: + HighSpeed: [0, High speed / full power] + MediumSpeed: [1, Medium speed / medium power] + LowSpeed: [2, Low speed / low power] + VeryLowSpeed: [3, Very-low speed / ultra-low power] + EN: + Disabled: [0, Comparator 1 disabled] + Enabled: [1, Comparator 1 enabled] + + COMP1_CSR: + INMESEL: + PA10: [0, PA10 connected to input minus] + PA11: [1, PA11 connected to input minus] + PA15: [2, PA15 connected to input minus] + INPSEL: + PB4: [0, PB4 connected to input plus] + PB2: [1, PB2 connected to input plus] + + COMP2_CSR: + INMESEL: + PB2: [0, PB2 connected to input minus] + PA10: [1, PA10 connected to input minus] + PA11: [2, PA11 connected to input minus] + WINMODE: + Disabled: [0, COMP2 input plus is not connected to COMP1] + Enabled: [1, COMP2 input plus is connected to COMP1] + INPSEL: + PB4: [0, PB4 connected to input plus] + PB1: [1, PB1 connected to input plus] + PA15: [2, PA15 connected to input plus] diff --git a/devices/fields/cordic/v1.yaml b/devices/fields/cordic/v1.yaml new file mode 100644 index 000000000..b6977e3a8 --- /dev/null +++ b/devices/fields/cordic/v1.yaml @@ -0,0 +1,62 @@ +# CORDIC co-processor provides hardware acceleration +# for computing (mainly trigonometric) math functions + +CSR: + RRDY: + _read: + NotReady: [0, Results from computation are not read] + Ready: [1, "Results are ready, this flag will be automatically cleared once value is read"] + ARGSIZE: + Bits32: [0, Use 32 bit input values] + Bits16: [1, Use 16 bit input values] + RESSIZE: + Bits32: [0, Use 32 bit output values] + Bits16: [1, Use 16 bit output values] + NARGS: + Num1: [0, Only single argument write is needed for next calculation] + Num2: [1, Two argument writes need to be performed for next calculation] + NRES: + Num1: [0, Only single result value will be returned. After a single read RRDY will be automatically cleared] + Num2: [1, Two return reads need to be performed. After two reads RRDY will be automatically cleared] + DMAWEN: + Disabled: [0, No DMA channel writes are generated] + Enabled: [1, Write requests are generated on the DMA channel when no operation is pending] + DMAREN: + Disabled: [0, No DMA channel reads are generated] + Enabled: [1, Read requests are generated on the DMA channel when RRDY flag is set] + IEN: + Disabled: [0, Disable interrupt request generation] + Enabled: [1, Enable interrupt request generation] + SCALE: [0, 7] + PRECISION: + Iters4: [1, 4 iterations] + Iters8: [2, 8 iterations] + Iters12: [3, 12 iterations] + Iters16: [4, 16 iterations] + Iters20: [5, 20 iterations] + Iters24: [6, 24 iterations] + Iters28: [7, 28 iterations] + Iters32: [8, 32 iterations] + Iters36: [9, 36 iterations] + Iters40: [10, 40 iterations] + Iters44: [11, 44 iterations] + Iters48: [12, 48 iterations] + Iters52: [13, 52 iterations] + Iters56: [14, 56 iterations] + Iters60: [15, 60 iterations] + FUNC: + Cosine: [0, Cosine function] + Sine: [1, Sine function] + Phase: [2, Phase function] + Modulus: [3, Modulus function] + Arctangent: [4, Arctangent function] + HyperbolicCosine: [5, Hyperbolic Cosine function] + HyperbolicSine: [6, Hyperbolic Sine function] + Arctanh: [7, Arctanh function] + NaturalLogarithm: [8, Natural Logarithm function] + SquareRoot: [9, Square Root function] +WDATA: + ARG: [0, 0xFFFFFFFF] + +RDATA: + RES: [0, 0xFFFFFFFF] diff --git a/devices/fields/crc/crc_idr_32bit.yaml b/devices/fields/crc/crc_idr_32bit.yaml new file mode 100644 index 000000000..888e504ef --- /dev/null +++ b/devices/fields/crc/crc_idr_32bit.yaml @@ -0,0 +1,8 @@ +# Independent data register allowing 32-bit usage. +# Some STM32 CRC units have this. + +IDR: + IDR: [0, 0xFFFFFFFF] + _modify: + IDR: + bitWidth: 32 diff --git a/devices/fields/crc/crc_idr_8bit.yaml b/devices/fields/crc/crc_idr_8bit.yaml new file mode 100644 index 000000000..3b237bf0b --- /dev/null +++ b/devices/fields/crc/crc_idr_8bit.yaml @@ -0,0 +1,8 @@ +# Independent data register allowing 8-bit usage only. +# Most STM32 CRC units have this. + +IDR: + IDR: [0, 0xFF] + _modify: + IDR: + bitWidth: 8 diff --git a/devices/fields/crc/crc_pol.yaml b/devices/fields/crc/crc_pol.yaml new file mode 100644 index 000000000..8f0e91ec1 --- /dev/null +++ b/devices/fields/crc/crc_pol.yaml @@ -0,0 +1,9 @@ +CR: + POLYSIZE: + Polysize32: [0, 32-bit polynomial] + Polysize16: [1, 16-bit polynomial] + Polysize8: [2, 8-bit polynomial] + Polysize7: [3, 7-bit polynomial] + +POL: + POL: [0, 0xFFFFFFFF] diff --git a/devices/fields/crc/crc_rev.yaml b/devices/fields/crc/crc_rev.yaml new file mode 100644 index 000000000..dbd6ae789 --- /dev/null +++ b/devices/fields/crc/crc_rev.yaml @@ -0,0 +1,9 @@ +CR: + REV_IN: + Normal: [0, Bit order not affected] + Byte: [1, Bit reversal done by byte] + HalfWord: [2, Bit reversal done by half-word] + Word: [3, Bit reversal done by word] + REV_OUT: + Normal: [0, Bit order not affected] + Reversed: [1, Bit reversed output] diff --git a/devices/fields/crc/v1.yaml b/devices/fields/crc/v1.yaml new file mode 100644 index 000000000..98b11f085 --- /dev/null +++ b/devices/fields/crc/v1.yaml @@ -0,0 +1,11 @@ +# CRC peripheral. Details specifically from RM0090 but widely applicable. +# This covers the basic features - DR and CR. For the more sophisticated +# CRC available on some STM32s, use v3.yaml. +# Additionally use crc_idr_8bit.yaml or crc_idr_32bit.yaml as appropriate. + +DR: + DR: [0, 4294967295] +CR: + RESET: + _write: + Reset: [1, Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF] diff --git a/devices/fields/crc/v2.yaml b/devices/fields/crc/v2.yaml new file mode 100644 index 000000000..9908f34af --- /dev/null +++ b/devices/fields/crc/v2.yaml @@ -0,0 +1,16 @@ +# CRC peripheral with reversal features. +# Documented from STM32F0xx reference manual. +# Additionally use crc_idr_8bit.yaml or crc_idr_32bit.yaml as appropriate. + +_include: + - v1.yaml + - crc_rev.yaml + +DR8: + DR8: [0, 255] + +DR16: + DR16: [0, 65535] + +INIT: + INIT: [0, 4294967295] diff --git a/devices/fields/crc/v3_idr32.yaml b/devices/fields/crc/v3_idr32.yaml new file mode 100644 index 000000000..48aca3f8a --- /dev/null +++ b/devices/fields/crc/v3_idr32.yaml @@ -0,0 +1,4 @@ +_include: + - v2.yaml + - crc_pol.yaml + - crc_idr_32bit.yaml diff --git a/devices/fields/crc/v3_idr8.yaml b/devices/fields/crc/v3_idr8.yaml new file mode 100644 index 000000000..17a80ca04 --- /dev/null +++ b/devices/fields/crc/v3_idr8.yaml @@ -0,0 +1,4 @@ +_include: + - v2.yaml + - crc_pol.yaml + - crc_idr_8bit.yaml diff --git a/devices/fields/crs/crs.yaml b/devices/fields/crs/crs.yaml new file mode 100644 index 000000000..f89e14e7b --- /dev/null +++ b/devices/fields/crs/crs.yaml @@ -0,0 +1,46 @@ +CR: + TRIM: [0, 0x3F] + SWSYNC: + Sync: [1, A software sync is generated] + AUTOTRIMEN: + Disabled: [0, Automatic trimming disabled] + Enabled: [1, Automatic trimming enabled] + CEN: + Disabled: [0, Frequency error counter disabled] + Enabled: [1, Frequency error counter enabled] + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + +CFGR: + SYNCPOL: + RisingEdge: [0, SYNC active on rising edge] + FallingEdge: [1, SYNC active on falling edge] + SYNCSRC: + GPIO_AF: [0, GPIO AF (crs_sync_in_1) selected as SYNC signal source] + LSE: [1, LSE (crs_sync_in_2) selected as SYNC signal source] + USB_SOF: [2, USB SOF (crs_sync_in_3) selected as SYNC signal source] + SYNCDIV: + Div1: [0, SYNC not divided] + Div2: [1, SYNC divided by 2] + Div4: [2, SYNC divided by 4] + Div8: [3, SYNC divided by 8] + Div16: [4, SYNC divided by 16] + Div32: [5, SYNC divided by 32] + Div64: [6, SYNC divided by 64] + Div128: [7, SYNC divided by 128] + FELIM: [0, 0xFF] + RELOAD: [0, 0xFFFF] + +ISR: + FECAP: [0, 0xFFFF] + FEDIR: + UpCounting: [0, Error in up-counting direction] + DownCounting: [1, Error in down-counting direction] + "SYNC*,*F": + NotSignaled: [0, Signal not set] + Signaled: [1, Signal set] + +ICR: + "*C": + Clear: [1, Clear flag] diff --git a/devices/fields/dac/12bit.yaml b/devices/fields/dac/12bit.yaml new file mode 100644 index 000000000..407a92ecf --- /dev/null +++ b/devices/fields/dac/12bit.yaml @@ -0,0 +1,2 @@ +DHR12[RL]?: + DACC?DHR: [0, 4095] diff --git a/devices/fields/dac/8bit.yaml b/devices/fields/dac/8bit.yaml new file mode 100644 index 000000000..ff4a03f6a --- /dev/null +++ b/devices/fields/dac/8bit.yaml @@ -0,0 +1,2 @@ +DHR8R?: + DACC?DHR: [0, 255] diff --git a/devices/fields/dac/dmaudr.yaml b/devices/fields/dac/dmaudr.yaml new file mode 100644 index 000000000..0057668e3 --- /dev/null +++ b/devices/fields/dac/dmaudr.yaml @@ -0,0 +1,12 @@ +CR: + DMAUDRIE?: + Disabled: [0, DAC channel X DMA Underrun Interrupt disabled] + Enabled: [1, DAC channel X DMA Underrun Interrupt enabled] +SR: + DMAUDR?: + NoUnderrun: [0, No DMA underrun error condition occurred for DAC channel x] + Underrun: + [ + 1, + DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate), + ] diff --git a/devices/fields/dac/f0.yaml b/devices/fields/dac/f0.yaml new file mode 100644 index 000000000..a4685d621 --- /dev/null +++ b/devices/fields/dac/f0.yaml @@ -0,0 +1,11 @@ +_include: + - v2.yaml +CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: [1, Timer 3 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim15Trgo: [3, Timer 15 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Exti9: [6, EXTI line 9] + Swtrig: [7, Software trigger] diff --git a/devices/fields/dac/f1.yaml b/devices/fields/dac/f1.yaml new file mode 100644 index 000000000..fbb455cae --- /dev/null +++ b/devices/fields/dac/f1.yaml @@ -0,0 +1,13 @@ +_include: + - v1.yaml + +CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim8Trgo: [1, Timer 8 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim5Trgo: [3, Timer 5 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Swtrig: [7, Software trigger] diff --git a/devices/fields/dac/f2_4_7.yaml b/devices/fields/dac/f2_4_7.yaml new file mode 100644 index 000000000..7b95d2a43 --- /dev/null +++ b/devices/fields/dac/f2_4_7.yaml @@ -0,0 +1,13 @@ +_include: + - v2.yaml + +CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim8Trgo: [1, Timer 8 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim5Trgo: [3, Timer 5 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Swtrig: [7, Software trigger] diff --git a/devices/fields/dac/g0.yaml b/devices/fields/dac/g0.yaml new file mode 100644 index 000000000..8a200e3c1 --- /dev/null +++ b/devices/fields/dac/g0.yaml @@ -0,0 +1,15 @@ +_include: + - v3.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim3Trgo: [3, Timer 3 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Lptim1Out: [11, LPTIM1 OUT event] + Lptim2Out: [12, LPTIM2 OUT event] + Exti9: [13, EXTI line 9] diff --git a/devices/fields/dac/g4.yaml b/devices/fields/dac/g4.yaml new file mode 100644 index 000000000..5c1afabde --- /dev/null +++ b/devices/fields/dac/g4.yaml @@ -0,0 +1,51 @@ +_include: + - v6.yaml + +SWTRGR: + SWTRIGB[12]: + NoTrigger: [0, No trigger] + Trigger: [1, Trigger for sawtooth increment] + +STR[12]: + STRSTDATA[12]: [0, 0xFFF] + STDIR[12]: + Decrement: [0, Decrement] + Increment: [1, Increment] + STINCDATA[12]: [0, 0xFFFF] + +CR,STMODR: + TSEL?,STRSTTRIGSEL?: + Swtrig: [0, Software trigger] + Tim1or8Trgo: [1, Timer 8 (DAC1, DAC2, DAC4) or Timer 1 (DAC3) TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim15Trgo: [3, Timer 15 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Tim6Trgo: [7, Timer 6 TRGO event] + Tim3Trgo: [8, Timer 3 TRGO event] + HrtimDacReset1: [9, hrtim_dac_reset_trg1] + HrtimDacReset2: [10, hrtim_dac_reset_trg2] + HrtimDacReset3: [11, hrtim_dac_reset_trg3] + HrtimDacReset4: [12, hrtim_dac_reset_trg4] + HrtimDacReset5: [13, hrtim_dac_reset_trg5] + HrtimDacReset6: [14, hrtim_dac_reset_trg6] + HrtimDacX: [15, hrtim_dac_trg1 (DAC1, DAC4), hrtim_dac_trg2 (DAC2), hrtim_dac_trg3 (DAC3)] + +STMODR: + STINCTRIGSEL?: + Swtrig: [0, Software sawtooth increment trigger] + Tim1or8Trgo: [1, Timer 8 (DAC1, DAC2, DAC4) or Timer 1 (DAC3) TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim15Trgo: [3, Timer 15 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti10: [6, EXTI line 10] + Tim6Trgo: [7, Timer 6 TRGO event] + Tim3Trgo: [8, Timer 3 TRGO event] + HrtimDacStep1: [9, hrtim_dac_step_trg1] + HrtimDacStep2: [10, hrtim_dac_step_trg2] + HrtimDacStep3: [11, hrtim_dac_step_trg3] + HrtimDacStep4: [12, hrtim_dac_step_trg4] + HrtimDacStep5: [13, hrtim_dac_step_trg5] + HrtimDacStep6: [14, hrtim_dac_step_trg6] diff --git a/devices/fields/dac/h5.yaml b/devices/fields/dac/h5.yaml new file mode 100644 index 000000000..56e3ce58c --- /dev/null +++ b/devices/fields/dac/h5.yaml @@ -0,0 +1,17 @@ +_include: + - v6.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim4Trgo: [3, Timer 4 TRGO event] + Tim5Trgo: [4, Timer 5 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim8Trgo: [7, Timer 8 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Lptim1Ch1: [11, LPTIM1 CH1 event] + Lptim2Ch1: [12, LPTIM2 CH1 event] + Exti9: [13, EXTI line 9] diff --git a/devices/fields/dac/h73x.yaml b/devices/fields/dac/h73x.yaml new file mode 100644 index 000000000..1e933800f --- /dev/null +++ b/devices/fields/dac/h73x.yaml @@ -0,0 +1,19 @@ +_include: + - v3.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim4Trgo: [3, Timer 4 TRGO event] + Tim5Trgo: [4, Timer 5 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim8Trgo: [7, Timer 8 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Lptim1Out: [11, LPTIM1 OUT event] + Lptim2Out: [12, LPTIM2 OUT event] + Exti9: [13, EXTI line 9] + Tim23Trgo: [14, Timer 23 TRGO event] + Tim24Trgo: [15, Timer 24 TRGO event] diff --git a/devices/fields/dac/h75x.yaml b/devices/fields/dac/h75x.yaml new file mode 100644 index 000000000..c53b008f3 --- /dev/null +++ b/devices/fields/dac/h75x.yaml @@ -0,0 +1,19 @@ +_include: + - v3.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim4Trgo: [3, Timer 4 TRGO event] + Tim5Trgo: [4, Timer 5 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim8Trgo: [7, Timer 8 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Hrtim1Dac1: [9, hrtim1_dactrg1] + Hrtim1Dac2: [10, hrtim1_dactrg2] + Lptim1Out: [11, LPTIM1 OUT event] + Lptim2Out: [12, LPTIM2 OUT event] + Exti9: [13, EXTI line 9] diff --git a/devices/fields/dac/h7_high.yaml b/devices/fields/dac/h7_high.yaml new file mode 100644 index 000000000..49a3dbe3e --- /dev/null +++ b/devices/fields/dac/h7_high.yaml @@ -0,0 +1,18 @@ +_include: + - v3.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim4Trgo: [3, Timer 4 TRGO event] + Tim5Trgo: [4, Timer 5 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim8Trgo: [7, Timer 8 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Lptim1Out: [11, LPTIM1 OUT event] + Lptim2Out: [12, LPTIM2 OUT event] + Exti9: [13, EXTI line 9] + Lptim2or3Out: [14, LPTIM2 (DAC1)/ LPTIM3 (DAC2) OUT event] diff --git a/devices/fields/dac/hfsel.yaml b/devices/fields/dac/hfsel.yaml new file mode 100644 index 000000000..4633dae45 --- /dev/null +++ b/devices/fields/dac/hfsel.yaml @@ -0,0 +1,4 @@ +CR: + HFSEL: + Disabled: [0, High frequency interface mode disabled] + Enabled: [1, High frequency interface mode enabled] diff --git a/devices/fields/dac/l0.yaml b/devices/fields/dac/l0.yaml new file mode 100644 index 000000000..5463c4b85 --- /dev/null +++ b/devices/fields/dac/l0.yaml @@ -0,0 +1,12 @@ +_include: + - v2.yaml +CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: [1, Timer 3 TRGO event] + Tim3Ch3: [2, Timer 3 CH3 event] + Tim21Trgo: [3, Timer 21 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim7Trgo: [5, Timer 7 TRGO event] + Exti9: [6, EXTI line 9] + Swtrig: [7, Software trigger] diff --git a/devices/fields/dac/l1.yaml b/devices/fields/dac/l1.yaml new file mode 100644 index 000000000..e83e89cdb --- /dev/null +++ b/devices/fields/dac/l1.yaml @@ -0,0 +1,12 @@ +_include: + - v2.yaml + +CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim9Trgo: [3, Timer 9 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Swtrig: [7, Software trigger] diff --git a/devices/fields/dac/l4+.yaml b/devices/fields/dac/l4+.yaml new file mode 100644 index 000000000..876d25346 --- /dev/null +++ b/devices/fields/dac/l4+.yaml @@ -0,0 +1,18 @@ +_include: + - v3.yaml + - hfsel.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim4Trgo: [3, Timer 4 TRGO event] + Tim5Trgo: [4, Timer 5 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim8Trgo: [7, Timer 8 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Lptim1Out: [11, LPTIM1 OUT event] + Lptim2Out: [12, LPTIM2 OUT event] + Exti9: [13, External pin] diff --git a/devices/fields/dac/l4.yaml b/devices/fields/dac/l4.yaml new file mode 100644 index 000000000..2d41c7895 --- /dev/null +++ b/devices/fields/dac/l4.yaml @@ -0,0 +1,13 @@ +_include: + - v3.yaml + +CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim8Trgo: [1, Timer 8 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim5Trgo: [3, Timer 5 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, External pin] + Swtrig: [7, Software triger] diff --git a/devices/fields/dac/l45x.yaml b/devices/fields/dac/l45x.yaml new file mode 100644 index 000000000..669589286 --- /dev/null +++ b/devices/fields/dac/l45x.yaml @@ -0,0 +1,12 @@ +_include: + - v3.yaml + +CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim8Trgo: [1, Timer 8 TRGO event] + Tim5Trgo: [3, Timer 5 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, External pin] + Swtrig: [7, Software triger] diff --git a/devices/fields/dac/l5.yaml b/devices/fields/dac/l5.yaml new file mode 100644 index 000000000..d32f43054 --- /dev/null +++ b/devices/fields/dac/l5.yaml @@ -0,0 +1,18 @@ +_include: + - v3.yaml + - hfsel.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim4Trgo: [3, Timer 4 TRGO event] + Tim5Trgo: [4, Timer 5 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim8Trgo: [7, Timer 8 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Lptim1Out: [11, LPTIM1 OUT event] + Lptim2Out: [12, LPTIM2 OUT event] + Exti9: [13, EXTI line 9] diff --git a/devices/fields/dac/u0.yaml b/devices/fields/dac/u0.yaml new file mode 100644 index 000000000..1102b39cd --- /dev/null +++ b/devices/fields/dac/u0.yaml @@ -0,0 +1,15 @@ +_include: + - v3.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim3Trgo: [3, Timer 3 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Lptim1Out: [11, LPTIM1 OUT event] + Lptim2Out: [12, LPTIM2 OUT event] + Exti9: [14, EXTI line 9] diff --git a/devices/fields/dac/u5.yaml b/devices/fields/dac/u5.yaml new file mode 100644 index 000000000..0f8d541b7 --- /dev/null +++ b/devices/fields/dac/u5.yaml @@ -0,0 +1,17 @@ +_include: + - v6.yaml + +CR: + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim4Trgo: [3, Timer 4 TRGO event] + Tim5Trgo: [4, Timer 5 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim8Trgo: [7, Timer 8 TRGO event] + Tim15Trgo: [8, Timer 15 TRGO event] + Lptim1Ch1: [11, LPTIM1 CH1 event] + Lptim3Ch1: [12, LPTIM3 CH1 event] + Exti9: [13, EXTI line 9] diff --git a/devices/fields/dac/v1.yaml b/devices/fields/dac/v1.yaml new file mode 100644 index 000000000..1fab702d2 --- /dev/null +++ b/devices/fields/dac/v1.yaml @@ -0,0 +1,22 @@ +_include: + - 8bit.yaml + - 12bit.yaml + - wavegen.yaml + +CR: + EN?: + Disabled: [0, DAC channel X disabled] + Enabled: [1, DAC channel X enabled] + BOFF?: + Enabled: [0, DAC channel X output buffer enabled] + Disabled: [1, DAC channel X output buffer disabled] + TEN?: + Disabled: [0, DAC channel X trigger disabled] + Enabled: [1, DAC channel X trigger enabled] + DMAEN?: + Disabled: [0, DAC channel X DMA mode disabled] + Enabled: [1, DAC channel X DMA mode enabled] +SWTRIGR: + SWTRIG?: + Disabled: [0, DAC channel X software trigger disabled] + Enabled: [1, DAC channel X software trigger enabled] diff --git a/devices/fields/dac/v2.yaml b/devices/fields/dac/v2.yaml new file mode 100644 index 000000000..bfa5fecaa --- /dev/null +++ b/devices/fields/dac/v2.yaml @@ -0,0 +1,3 @@ +_include: + - v1.yaml + - dmaudr.yaml diff --git a/devices/fields/dac/v3.yaml b/devices/fields/dac/v3.yaml new file mode 100644 index 000000000..f838bd58c --- /dev/null +++ b/devices/fields/dac/v3.yaml @@ -0,0 +1,61 @@ +_include: + - 8bit.yaml + - 12bit.yaml + - wavegen.yaml + - dmaudr.yaml + +CR: + CEN?: + Normal: [0, DAC Channel X Normal operating mode] + Calibration: [1, DAC Channel X calibration mode] + DMAEN?: + Disabled: [0, DAC Channel X DMA mode disabled] + Enabled: [1, DAC Channel X DMA mode enabled] + TEN?: + Disabled: [0, DAC Channel X trigger disabled] + Enabled: [1, DAC Channel X trigger enabled] + EN?: + Disabled: [0, DAC Channel X disabled] + Enabled: [1, DAC Channel X enabled] + +"SWTRGR,SWTRIGR": + SWTRIG?: + NoTrigger: [0, No trigger] + Trigger: [1, Trigger] + +DOR?: + DACC?DOR: [0, 4095] + +SR: + BWST?: + Idle: [0, "There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written"] + Busy: [1, "There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written"] + CAL_FLAG?: + Lower: [0, Calibration trimming value is lower than the offset correction value] + Equal_Higher: [1, Calibration trimming value is equal or greater than the offset correction value] + +CCR: + OTRIM?: [0, 0x1F] + +MCR: + MODE?: + NormalPinBuffer: [0b000, Normal mode - DAC channelx is connected to external pin with Buffer enabled] + NormalPinChipBuffer: + [0b001, Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled] + NormalPinNoBuffer: [0b010, Normal mode - DAC channelx is connected to external pin with Buffer disabled] + NormalChipNoBuffer: [0b011, Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled] + SHPinBuffer: [0b100, "S&H mode - DAC channelx is connected to external pin with Buffer enabled"] + SHPinChipBuffer: + [0b101, "S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled"] + SHPinNoBuffer: + [0b110, "S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled"] + SHChipNoBuffer: [0b111, "S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled"] + +SHSR?: + TSAMPLE?: [0, 1023] + +SHHR: + THOLD?: [0, 1023] + +SHRR: + TREFRESH?: [0, 255] diff --git a/devices/fields/dac/v6.yaml b/devices/fields/dac/v6.yaml new file mode 100644 index 000000000..a0c3bd3c0 --- /dev/null +++ b/devices/fields/dac/v6.yaml @@ -0,0 +1,36 @@ +_include: + - v3.yaml + +DHR12[RL][12]: + DACC?DHRB: [0, 4095] + +DHR8R[12]: + DACC?DHRB: [0, 255] + +DOR?: + DACC?DORB: [0, 4095] + +SR: + DAC[12]RDY: + NotReady: [0, DAC channelX is not yet ready to accept the trigger nor output data] + Ready: [1, DAC channelX is ready to accept the trigger or output data] + DORSTAT[12]: + Dor: [0, "DOR[11:0] is used actual DAC output"] + Dorb: [1, "DORB[11:0] is used actual DAC output"] + +MCR: + DMADOUBLE[12]: + Normal: [0, DMA Normal mode selected] + DoubleData: [1, DMA Double data mode selected] + SINFORMAT[12]: + Unsigned: [0, Input data is in unsigned format] + Signed: [1, "Input data is in signed format (2's complement). The MSB bit represents the sign."] + HFSEL: + Disabled: [0, High frequency interface mode disabled] + More80Mhz: [1, High frequency interface mode enabled for AHB clock frequency > 80 MHz] + More160Mhz: [2, High frequency interface mode enabled for AHB clock frequency >160 MHz] + +"?~AUTOCR": + AUTOMODE: + Disabled: [0, DAC Autonomous mode disabled] + Enabled: [1, DAC Autonomous mode enabled] diff --git a/devices/fields/dac/wavegen.yaml b/devices/fields/dac/wavegen.yaml new file mode 100644 index 000000000..590ead76a --- /dev/null +++ b/devices/fields/dac/wavegen.yaml @@ -0,0 +1,20 @@ +# These are the extra DAC features on fancier devices. + +CR: + WAVE?: + Disabled: [0, Wave generation disabled] + Noise: [1, Noise wave generation enabled] + Triangle: [-1, Triangle wave generation enabled] + MAMP?: + Amp1: [0b0000, Unmask bit0 of LFSR/ triangle amplitude equal to 1] + Amp3: [0b0001, "Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3"] + Amp7: [0b0010, "Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7"] + Amp15: [0b0011, "Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15"] + Amp31: [0b0100, "Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31"] + Amp63: [0b0101, "Unmask bits[5:0] of LFSR/ triangle amplitude equal 63"] + Amp127: [0b0110, "Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127"] + Amp255: [0b0111, "Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255"] + Amp511: [0b1000, "Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511"] + Amp1023: [0b1001, "Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023"] + Amp2047: [0b1010, "Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047"] + Amp4095: [-1, "Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095"] diff --git a/devices/fields/dac/wl.yaml b/devices/fields/dac/wl.yaml new file mode 100644 index 000000000..1e82c8bf4 --- /dev/null +++ b/devices/fields/dac/wl.yaml @@ -0,0 +1,12 @@ +_include: + - v3.yaml + +"CR,CR?": + TSEL?: + Swtrig: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Lptim1Out: [11, LPTIM1 OUT event] + Lptim2Out: [12, LPTIM2 OUT event] + Lptim3Out: [13, LPTIM3 OUT event] + EXTI9: [14, dac_chx_trg14] diff --git a/devices/fields/dbg/dbg_common.yaml b/devices/fields/dbg/dbg_common.yaml new file mode 100644 index 000000000..19226b14f --- /dev/null +++ b/devices/fields/dbg/dbg_common.yaml @@ -0,0 +1,35 @@ +DBGMCU: + CR: + DBG_STANDBY: + Disabled: [0, Debug Standby Mode Disabled] + Enabled: [1, Debug Standby Mode Enabled] + DBG_STOP: + Disabled: [0, Debug Stop Mode Disabled] + Enabled: [1, Debug Stop Mode Enabled] + DBG_SLEEP: + Disabled: [0, Debug Sleep Mode Disabled] + Enabled: [1, Debug Sleep Mode Enabled] + + APB1FZR1: + DBG_IWDG_STOP: + Continue: [0, The independent watchdog counter clock continues even if the core is halted] + Stop: [1, The independent watchdog counter clock is stopped when the core is halted] + DBG_WWDG_STOP: + Continue: [0, The window watchdog counter clock continues even if the core is halted] + Stop: [1, The window watchdog counter clock is stopped when the core is halted] + DBG_RTC_STOP: + Continue: [0, The clock of the RTC counter is fed even if the core is halted] + Stop: [1, The clock of the RTC counter is stopped when the core is halted] + DBG_TIM*_STOP: + Continue: [0, The counter clock of TIMx is fed even if the core is halted] + Stop: [1, The counter clock of TIMx is stopped when the core is halted] + + APB1FZR?: + DBG_LPTIM?_STOP: + Continue: [0, LPTIMx counter clock is fed even if the core is halted] + Stop: [1, LPTIMx counter clock is stopped when the core is halted] + + APB2FZR: + DBG_TIM*_STOP: + Continue: [0, The counter clock of TIMx is fed even if the core is halted] + Stop: [1, The counter clock of TIMx is stopped when the core is halted] diff --git a/devices/fields/dbg/dbg_l0.yaml b/devices/fields/dbg/dbg_l0.yaml new file mode 100644 index 000000000..b4e2f523d --- /dev/null +++ b/devices/fields/dbg/dbg_l0.yaml @@ -0,0 +1,35 @@ +# Debug registers for L0 + +CR: + DBG_STANDBY: + Disabled: [0, Debug Standby Mode Disabled] + Enabled: [1, Debug Standby Mode Enabled] + DBG_STOP: + Disabled: [0, Debug Stop Mode Disabled] + Enabled: [1, Debug Stop Mode Enabled] + DBG_SLEEP: + Disabled: [0, Debug Sleep Mode Disabled] + Enabled: [1, Debug Sleep Mode Enabled] +APB1_FZ: + DBG_LPTIMER_STOP: + Continue: [0, LPTIM1 counter clock is fed even if the core is halted] + Stop: [1, LPTIM1 counter clock is stopped when the core is halted] + DBG_I2C*_STOP: + NormalMode: [0, Same behavior as in normal mode] + SMBusTimeoutFrozen: [1, I2C3 SMBUS timeout is frozen] + DBG_IWDG_STOP: + Continue: [0, The independent watchdog counter clock continues even if the core is halted] + Stop: [1, The independent watchdog counter clock is stopped when the core is halted] + DBG_WWDG_STOP: + Continue: [0, The window watchdog counter clock continues even if the core is halted] + Stop: [1, The window watchdog counter clock is stopped when the core is halted] + DBG_RTC_STOP: + Continue: [0, The clock of the RTC counter is fed even if the core is halted] + Stop: [1, The clock of the RTC counter is stopped when the core is halted] + DBG_TIM*_STOP: + Continue: [0, The counter clock of TIMx is fed even if the core is halted] + Stop: [1, The counter clock of TIMx is stopped when the core is halted] +APB2_FZ: + DBG_TIM*_STOP: + Continue: [0, The counter clock of TIMx is fed even if the core is halted] + Stop: [1, The counter clock of TIMx is stopped when the core is halted] diff --git a/devices/fields/dbg/dbg_l4+.yaml b/devices/fields/dbg/dbg_l4+.yaml new file mode 100644 index 000000000..7c4ccbac6 --- /dev/null +++ b/devices/fields/dbg/dbg_l4+.yaml @@ -0,0 +1,16 @@ +# Debug registers for L4+ series + +_include: + - dbg_trace.yaml + - dbg_common.yaml + +DBGMCU: + APB1FZR1: + DBG_CAN1_STOP: + NormalMode: [0, Same behavior as in normal mode] + ReceiveRegistersFrozen: [1, The bxCAN1 receive registers are frozen] + + APB1FZR?: + DBG_I2C*_STOP: + NormalMode: [0, Same behavior as in normal mode] + SMBusTimeoutFrozen: [1, I2Cx SMBUS timeout is frozen] diff --git a/devices/fields/dbg/dbg_trace.yaml b/devices/fields/dbg/dbg_trace.yaml new file mode 100644 index 000000000..e5f2f4389 --- /dev/null +++ b/devices/fields/dbg/dbg_trace.yaml @@ -0,0 +1,10 @@ +DBGMCU: + CR: + TRACE_MODE: + Asynchronous: [0, TRACE pin assignment for Asynchronous Mode] + Size1: [1, TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1] + Size2: [2, TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2] + Size4: [3, TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4] + TRACE_IOEN: + Disabled: [0, Trace pins not assigned (default state)] + Enabled: [1, Trace pins assigned] diff --git a/devices/fields/dbg/dbg_wl.yaml b/devices/fields/dbg/dbg_wl.yaml new file mode 100644 index 000000000..6544b5bf8 --- /dev/null +++ b/devices/fields/dbg/dbg_wl.yaml @@ -0,0 +1,10 @@ +# Debug registers for WL + +_include: + - dbg_common.yaml + +DBGMCU: + APB1FZR1: + DBG_I2C*_STOP: + NormalMode: [0, Same behavior as in normal mode] + SMBusTimeoutFrozen: [1, I2Cx SMBUS timeout is frozen] diff --git a/devices/fields/dcmi/v1.yaml b/devices/fields/dcmi/v1.yaml new file mode 100644 index 000000000..072559f94 --- /dev/null +++ b/devices/fields/dcmi/v1.yaml @@ -0,0 +1,184 @@ +CR: + ENABLE: + Disabled: [0, DCMI disabled] + Enabled: [1, DCMI enabled] + EDM: + BitWidth8: [0, Interface captures 8-bit data on every pixel clock] + BitWidth10: [1, Interface captures 10-bit data on every pixel clock] + BitWidth12: [2, Interface captures 12-bit data on every pixel clock] + BitWidth14: [3, Interface captures 14-bit data on every pixel clock] + FCRC: + All: [0, All frames are captured] + Alternate: [1, Every alternate frame captured (50% bandwidth reduction)] + OneOfFour: [2, One frame out of four captured (75% bandwidth reduction)] + VSPOL: + ActiveLow: [0, DCMI_VSYNC active low] + ActiveHigh: [1, DCMI_VSYNC active high] + HSPOL: + ActiveLow: [0, DCMI_HSYNC active low] + ActiveHigh: [1, DCMI_HSYNC active high] + PCKPOL: + FallingEdge: [0, Falling edge active] + RisingEdge: [1, Rising edge active] + ESS: + Hardware: + [ + 0, + Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals, + ] + Embedded: + [1, Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow] + JPEG: + Uncompressed: [0, Uncompressed video format] + JPEG: + [ + 1, + This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode, + ] + CROP: + Full: + [ + 0, + The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four, + ] + Cropped: + [ + 1, + "Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured", + ] + CM: + Continuous: + [ + 0, + Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA, + ] + Snapshot: + [ + 1, + "Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset", + ] + CAPTURE: + Disabled: [0, Capture disabled] + Enabled: [1, Capture enabled] + +SR: + FNE: + NotEmpty: [0, FIFO contains valid data] + Empty: [1, FIFO empty] + VSYNC: + ActiveFrame: [0, Active frame] + BetweenFrames: [1, Synchronization between frames] + HSYNC: + ActiveLine: [0, Active line] + BetweenLines: [1, Synchronization between lines] + +RIS: + LINE_RIS: + Set: [1, Interrupt set] + Cleared: [0, Interrupt cleared] + VSYNC_RIS: + Set: [1, Interrupt set] + Cleared: [0, Interrupt cleared] + ERR_RIS: + SynchronizationError: [1, Embedded synchronization characters are not received in the correct order] + NoError: [0, No synchronization error detected] + OVR_RIS: + OverrunOccured: + [ + 1, + A data buffer overrun occurred and the data FIFO is corrupted. The bit is cleared by setting the OVR_ISC bit of the DCMI_ICR register, + ] + NoOverrun: [0, No data buffer overrun occurred] + FRAME_RIS: + FrameCaptured: [1, A frame has been captured] + NoNewCapture: [0, No new capture] + +IER: + LINE_IE: + Disabled: [0, No interrupt generation when the line is received] + Enabled: [1, An Interrupt is generated when a line has been completely received] + VSYNC_IE: + Disabled: [0, No interrupt generation] + Enabled: [1, An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state] + ERR_IE: + Disabled: [0, No interrupt generation] + Enabled: [1, An interrupt is generated if the embedded synchronization codes are not received in the correct order] + OVR_IE: + Disabled: [0, No interrupt generation] + Enabled: + [ + 1, + An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received, + ] + FRAME_IE: + Disabled: [0, No interrupt generation] + Enabled: [1, An interrupt is generated at the end of each received frame/crop window (in crop mode)] + +MIS: + LINE_MIS: + Disabled: [0, No interrupt generation when the line is received] + Enabled: + [1, An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER] + VSYNC_MIS: + Disabled: [0, No interrupt is generated on DCMI_VSYNC transitions] + Enabled: + [ + 1, + An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER, + ] + ERR_MIS: + Disabled: [0, No interrupt is generated on a synchronization error] + Enabled: + [ + 1, + An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set, + ] + OVR_MIS: + Disabled: [0, No interrupt is generated on overrun] + Enabled: + [ + 1, + An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER, + ] + FRAME_MIS: + Disabled: [0, No interrupt is generated after a complete capture] + Enabled: + [ + 1, + An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER, + ] + +ICR: + LINE_ISC: + Clear: [1, Setting this bit clears the LINE_RIS flag in the DCMI_RIS register] + VSYNC_ISC: + Clear: [1, Setting this bit clears the VSYNC_RIS flag in the DCMI_RIS register] + ERR_ISC: + Clear: [1, Setting this bit clears the ERR_RIS flag in the DCMI_RIS register] + OVR_ISC: + Clear: [1, Setting this bit clears the OVR_RIS flag in the DCMI_RIS register] + FRAME_ISC: + Clear: [1, Setting this bit clears the FRAME_RIS flag in the DCMI_RIS register] + +ESCR: + FEC: + LEC: + LSC: + FSC: + +ESUR: + FEU: + LEU: + LSU: + FSU: + +CWSTRT: + VST: [0, 0x1FFF] + HOFFCNT: [0, 0x3FFF] + +CWSIZE: + VLINE: [0, 0x3FFF] + CAPCNT: [0, 0x3FFF] + +DR: + BYTE?: [0, 0xFF] diff --git a/devices/fields/dcmi/v2.yaml b/devices/fields/dcmi/v2.yaml new file mode 100644 index 000000000..02f91a929 --- /dev/null +++ b/devices/fields/dcmi/v2.yaml @@ -0,0 +1,19 @@ +_include: + - v1.yaml + +CR: + OELS: + Odd: [0, "Interface captures first line after the frame start, second one being dropped"] + Even: [1, "Interface captures second line from the frame start, first one being dropped"] + LSM: + All: [0, Interface captures all received lines] + Half: [1, Interface captures one line out of two] + OEBS: + Odd: [0, "Interface captures first data (byte or double byte) from the frame/line start, second one being dropped"] + Even: + [1, " Interface captures second data (byte or double byte) from the frame/line start, first one being dropped"] + BSM: + All: [0, Interface captures all received data] + EveryOther: [1, Interface captures every other byte from the received data] + Fourth: [2, Interface captures one byte out of four] + TwoOfFour: [3, Interface captures two bytes out of four] diff --git a/devices/fields/dfsdm/f7.yaml b/devices/fields/dfsdm/f7.yaml new file mode 100644 index 000000000..2e157527f --- /dev/null +++ b/devices/fields/dfsdm/f7.yaml @@ -0,0 +1,328 @@ +CHCFG0R1: + DFSDMEN: + Disabled: [0, DFSDM interface disabled] + Enabled: [1, DFSDM interface enabled] + CKOUTSRC: + SYSCLK: [0, Source for output clock is from system clock] + AUDCLK: [1, Source for output clock is from audio clock] + CKOUTDIV: [0, 0xFF] +CHCFG?R1: + DATPACK: + Standard: + [ + 0, + "Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y", + ] + Interleaved: + [ + 1, + ": Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)", + ] + Dual: + [ + 2, + "Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)", + ] + DATMPX: + External: + [ + 0, + Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected, + ] + ADC: + [ + 1, + "Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register", + ] + Internal: + [ + 2, + "Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting", + ] + CHINSEL: + SameChannel: [0, Channel inputs are taken from pins of the same channel y] + FollowingChannel: [1, "Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)"] + CHEN: + Disabled: [0, Channel y disabled] + Enabled: [1, Channel y enabled] + CKABEN: + Disabled: [0, Clock absence detector disabled on channel y] + Enabled: [1, Clock absence detector enabled on channel y] + SCDEN: + Disabled: [0, Input channel y will not be guarded by the short-circuit detector] + Enabled: [1, Input channel y will be continuously guarded by the short-circuit detector] + SPICKSEL: + CKIN: [0, "Clock coming from external CKINy input - sampling point according SITP[1:0]"] + CKOUT: [1, "Clock coming from internal CKOUT output - sampling point according SITP[1:0]"] + CKOUTSecondFalling: + [ + 2, + Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge), + ] + CKOUTSecondRising: + [ + 3, + Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge), + ] + SITP: + SPIRisingEdge: [0, SPI with rising edge to strobe data] + SPIFallingEdge: [1, SPI with falling edge to strobe data] + Manchester: [2, "Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1"] + ManchesterInverted: [3, "Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0"] + +CHCFG?R2: + OFFSET: [0, 0xFFFFFF] + DTRBS: [0, 0x1F] + +AWSCD?R: + AWFORD: + FastSinc: [0, FastSinc filter type] + Sinc1: [1, Sinc1 filter type] + Sinc2: [2, Sinc2 filter type] + Sinc3: [3, Sinc3 filter type] + AWFOSR: [0, 0x1F] + BKSCD: [0, 0xF] + SCDT: [0, 0xFF] + +CHWDAT?R: + WDATA: [0, 0xFFFF] + +CHDATIN?R: + INDAT1: [0, 0xFFFF] + INDAT0: [0, 0xFFFF] + +DFSDM[0123]_CR1: + AWFSEL: + Output: + [ + 0, + Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift, + ] + Transceiver: [1, Analog watchdog on channel transceivers value (after watchdog filter)] + FAST: + Disabled: [0, Fast conversion mode disabled] + Enabled: [1, Fast conversion mode enabled] + RCH: + Channel0: [0, Channel 0 is selected as regular channel] + Channel1: [1, Channel 1 is selected as regular channel] + Channel2: [2, Channel 2 is selected as regular channel] + Channel3: [3, Channel 3 is selected as regular channel] + Channel4: [4, Channel 4 is selected as regular channel] + Channel5: [5, Channel 5 is selected as regular channel] + Channel6: [6, Channel 6 is selected as regular channel] + Channel7: [7, Channel 7 is selected as regular channel] + RDMAEN: + Disabled: [0, The DMA channel is not enabled to read regular data] + Enabled: [1, The DMA channel is enabled to read regular data] + RSYNC: + NoLaunch: [0, Do not launch a regular conversion synchronously with DFSDM_FLT0] + Launch: + [ + 1, + Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0, + ] + RCONT: + Once: [0, The regular channel is converted just once for each conversion request] + Continuous: [1, The regular channel is converted repeatedly after each conversion request] + RSWSTART: + _write: + Start: + [ + 1, + "Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1", + ] + JEXTEN: + Disabled: [0, Trigger detection is disabled] + RisingEdge: [1, Each rising edge on the selected trigger makes a request to launch an injected conversion] + FallingEdge: [2, Each falling edge on the selected trigger makes a request to launch an injected conversion] + BothEdges: + [3, Both rising edges and falling edges on the selected trigger make requests to launch injected conversions] + JDMAEN: + Disabled: [0, The DMA channel is not enabled to read injected data] + Enabled: [1, The DMA channel is enabled to read injected data] + JSCAN: + Single: + [ + 0, + One channel conversion is performed from the injected channel group and next the selected channel from this group is selected, + ] + Series: + [ + 1, + "The series of conversions for the injected group channels is executed, starting over with the lowest selected channel", + ] + JSYNC: + Disabled: [0, Do not launch an injected conversion synchronously with DFSDM_FLT0] + Enabled: + [ + 1, + Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger, + ] + JSWSTART: + _write: + Start: + [ + 1, + "Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1", + ] + DFEN: + Disabled: + [ + 0, + DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped, + ] + Enabled: + [1, "DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting"] + +DFSDM0_CR2: + CKABIE: + Disabled: [0, Detection of channel input clock absence interrupt is disabled] + Enabled: [1, Detection of channel input clock absence interrupt is enabled] + SCDIE: + Disabled: [0, Short-circuit detector interrupt is disabled] + Enabled: [1, Short-circuit detector interrupt is enabled] + +DFSDM[0123]_CR2: + AWDCH: + Disabled: [0, Analog watchdog is disabled on channel y] + Enabled: [1, Analog watchdog is enabled on channel y] + EXCH: + Disabled: [0, Extremes detector does not accept data from channel y] + Enabled: [1, Extremes detector accepts data from channel y] + AWDIE: + Disabled: [0, Analog watchdog interrupt is disabled] + Enabled: [1, Analog watchdog interrupt is enabled] + ROVRIE: + Disabled: [0, Regular data overrun interrupt is disabled] + Enabled: [1, Regular data overrun interrupt is enabled] + JOVRIE: + Disabled: [0, Injected data overrun interrupt is disabled] + Enabled: [1, Injected data overrun interrupt is enabled] + REOCIE: + Disabled: [0, Regular end of conversion interrupt is disabled] + Enabled: [1, Regular end of conversion interrupt is enabled] + JEOCIE: + Disabled: [0, Injected end of conversion interrupt is disabled] + Enabled: [1, Injected end of conversion interrupt is enabled] + +DFSDM[0123]_ISR: + SCDF: + Clear: [0, No short-circuit detector event occurred on channel y] + Set: + [ + 1, + "The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers", + ] + CKABF: + Clear: [0, Clock signal on channel y is present.] + Set: [1, Clock signal on channel y is not present] + RCIP: + NotInProgress: [0, No request to convert the regular channel has been issued] + InProgress: + [1, The conversion of the regular channel is in progress or a request for a regular conversion is pending] + JCIP: + NotInProgress: + [0, No request to convert the injected channel group (neither by software nor by trigger) has been issued] + InProgress: + [ + 1, + "The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection", + ] + AWDF: + Clear: [0, No Analog watchdog event occurred] + Set: + [ + 1, + The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers, + ] + ROVRF: + Clear: [0, No regular conversion overrun has occurred] + Set: + [ + 1, + "A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns", + ] + JOVRF: + Clear: [0, No injected conversion overrun has occurred] + Set: + [ + 1, + "An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns", + ] + REOCF: + Clear: [0, No regular conversion has completed] + Set: [1, A regular conversion has completed and its data may be read] + JEOCF: + Clear: [0, No injected conversion has completed] + Set: [1, An injected conversion has completed and its data may be read] + +DFSDM[0123]_ICR: + CLRSCDF: [0, 0xFF] + CLRCKABF: [0, 0xFF] + CLRROVRF: + _write: + Clear: [1, "Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register"] + CLRJOVRF: + _write: + Clear: [1, "Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register"] + +DFSDM[0123]_JCHGR: + JCHG: [0, 0xFF] + +DFSDM[0123]_FCR: + FORD: + FastSinc: [0, FastSinc filter type] + Sinc1: [1, Sinc1 filter type] + Sinc2: [2, Sinc2 filter type] + Sinc3: [3, Sinc3 filter type] + Sinc4: [4, Sinc4 filter type] + Sinc5: [5, Sinc5 filter type] + FOSR: [0, 1023] + IOSR: [0, 255] + +DFSDM[0123]_JDATAR: + JDATA: [0, 0xFFFFFF] + JDATACH: [0, 0x7] + +DFSDM[0123]_RDATAR: + RDATA: [0, 0xFFFFFF] + RDATACH: [0, 7] + +DFSDM[0123]_AWHTR: + AWHT: [0, 0xFFFFFF] + BKAWH?: + NotAssigned: [0, Break i signal is not assigned to an analog watchdog high threshold event] + Assigned: [1, Break i signal is assigned to an analog watchdog high threshold event] + +DFSDM[0123]_AWLTR: + AWLT: [0, 0xFFFFFF] + BKAWL?: + NotAssigned: [0, Break i signal is not assigned to an analog watchdog low threshold event] + Assigned: [1, Break i signal is assigned to an analog watchdog low threshold event] + +DFSDM[0123]_AWSR: + AWHTF?: + NoError: [0, No high threshold error] + Error: [1, A high threshold error on channel y] + AWLTF?: + NoError: [0, No low threshold error] + Error: [1, A low threshold error on channel y] + +DFSDM[0123]_AWCFR: + CLRAWHTF?: + _W1C: + Clear: [1, "Clear the corresponding AWHTF[y] bit"] + CLRAWLTF?: + _W1C: + Clear: [1, "Clear the corresponding AWLTF[y] bit"] + +DFSDM[0123]_EXMAX: + EXMAX: [0, 0xFFFFFF] + EXMAXCH: [0, 0x7] + +DFSDM[0123]_EXMIN: + EXMIN: [0, 0xFFFFFF] + EXMINCH: [0, 0x7] + +DFSDM[0123]_CNVTIMR: + CNVCNT: [0, 0xFFFFFFF] diff --git a/devices/fields/dfsdm/v1+.yaml b/devices/fields/dfsdm/v1+.yaml new file mode 100644 index 000000000..6b03825ba --- /dev/null +++ b/devices/fields/dfsdm/v1+.yaml @@ -0,0 +1,5 @@ +_include: + - v1.yaml + +FLT?CR1: + JEXTSEL: [0, 0x1F] diff --git a/devices/fields/dfsdm/v1.yaml b/devices/fields/dfsdm/v1.yaml new file mode 100644 index 000000000..211a7d8bf --- /dev/null +++ b/devices/fields/dfsdm/v1.yaml @@ -0,0 +1,331 @@ +CH0CFGR1: + DFSDMEN: + Disabled: [0, DFSDM interface disabled] + Enabled: [1, DFSDM interface enabled] + CKOUTSRC: + SYSCLK: [0, Source for output clock is from system clock] + AUDCLK: [1, Source for output clock is from audio clock] + CKOUTDIV: [0, 0xFF] +CH?CFGR1: + DATPACK: + Standard: + [ + 0, + "Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y", + ] + Interleaved: + [ + 1, + ": Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample in INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y)", + ] + Dual: + [ + 2, + "Dual: input data in DFSDM_CHyDATINR register are stored as two samples: –first sample INDAT0[15:0] (assigned to channel y) –second sample INDAT1[15:0] (assigned to channel y+1)", + ] + DATMPX: + External: + [ + 0, + Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR register is write protected, + ] + ADC: + [ + 1, + "Data to channel y are taken from internal analog to digital converter ADCy+1 output register update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0] part of DFSDM_CHyDATINR register", + ] + Internal: + [ + 2, + "Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write. There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting", + ] + CHINSEL: + SameChannel: [0, Channel inputs are taken from pins of the same channel y] + FollowingChannel: [1, "Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8)"] + CHEN: + Disabled: [0, Channel y disabled] + Enabled: [1, Channel y enabled] + CKABEN: + Disabled: [0, Clock absence detector disabled on channel y] + Enabled: [1, Clock absence detector enabled on channel y] + SCDEN: + Disabled: [0, Input channel y will not be guarded by the short-circuit detector] + Enabled: [1, Input channel y will be continuously guarded by the short-circuit detector] + SPICKSEL: + CKIN: [0, "Clock coming from external CKINy input - sampling point according SITP[1:0]"] + CKOUT: [1, "Clock coming from internal CKOUT output - sampling point according SITP[1:0]"] + CKOUTSecondFalling: + [ + 2, + Clock coming from internal CKOUT - sampling point on each second CKOUT falling edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input rising edge), + ] + CKOUTSecondRising: + [ + 3, + Clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge. For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to generate its output serial communication clock (and this output clock change is active on each clock input falling edge), + ] + SITP: + SPIRisingEdge: [0, SPI with rising edge to strobe data] + SPIFallingEdge: [1, SPI with falling edge to strobe data] + Manchester: [2, "Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1"] + ManchesterInverted: [3, "Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0"] + +CH?CFGR2: + OFFSET: [0, 0xFFFFFF] + DTRBS: [0, 0x1F] + +CH?AWSCDR: + AWFORD: + FastSinc: [0, FastSinc filter type] + Sinc1: [1, Sinc1 filter type] + Sinc2: [2, Sinc2 filter type] + Sinc3: [3, Sinc3 filter type] + AWFOSR: [0, 0x1F] + BKSCD: [0, 0xF] + SCDT: [0, 0xFF] + +CH?WDATR: + WDATA: [0, 0xFFFF] + +CH?DATINR: + INDAT1: [0, 0xFFFF] + INDAT0: [0, 0xFFFF] + +"?~CH?DLYR": + PLSSKP: [0, 0x3F] + +FLT?CR1: + AWFSEL: + Output: + [ + 0, + Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift, + ] + Transceiver: [1, Analog watchdog on channel transceivers value (after watchdog filter)] + FAST: + Disabled: [0, Fast conversion mode disabled] + Enabled: [1, Fast conversion mode enabled] + RCH: + Channel0: [0, Channel 0 is selected as regular channel] + Channel1: [1, Channel 1 is selected as regular channel] + Channel2: [2, Channel 2 is selected as regular channel] + Channel3: [3, Channel 3 is selected as regular channel] + Channel4: [4, Channel 4 is selected as regular channel] + Channel5: [5, Channel 5 is selected as regular channel] + Channel6: [6, Channel 6 is selected as regular channel] + Channel7: [7, Channel 7 is selected as regular channel] + RDMAEN: + Disabled: [0, The DMA channel is not enabled to read regular data] + Enabled: [1, The DMA channel is enabled to read regular data] + RSYNC: + NoLaunch: [0, Do not launch a regular conversion synchronously with DFSDM_FLT0] + Launch: + [ + 1, + Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion is launched in DFSDM_FLT0, + ] + RCONT: + Once: [0, The regular channel is converted just once for each conversion request] + Continuous: [1, The regular channel is converted repeatedly after each conversion request] + RSWSTART: + _write: + Start: + [ + 1, + "Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if RSYNC=1", + ] + JEXTEN: + Disabled: [0, Trigger detection is disabled] + RisingEdge: [1, Each rising edge on the selected trigger makes a request to launch an injected conversion] + FallingEdge: [2, Each falling edge on the selected trigger makes a request to launch an injected conversion] + BothEdges: + [3, Both rising edges and falling edges on the selected trigger make requests to launch injected conversions] + JDMAEN: + Disabled: [0, The DMA channel is not enabled to read injected data] + Enabled: [1, The DMA channel is enabled to read injected data] + JSCAN: + Single: + [ + 0, + One channel conversion is performed from the injected channel group and next the selected channel from this group is selected, + ] + Series: + [ + 1, + "The series of conversions for the injected group channels is executed, starting over with the lowest selected channel", + ] + JSYNC: + Disabled: [0, Do not launch an injected conversion synchronously with DFSDM_FLT0] + Enabled: + [ + 1, + Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected conversion is launched in DFSDM_FLT0 by its JSWSTART trigger, + ] + JSWSTART: + _write: + Start: + [ + 1, + "Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect. Writing ‘1’ has no effect if JSYNC=1", + ] + DFEN: + Disabled: + [ + 0, + DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and all DFSDM_FLTx functions are stopped, + ] + Enabled: + [1, "DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating according to its setting"] + +FLT0CR2: + CKABIE: + Disabled: [0, Detection of channel input clock absence interrupt is disabled] + Enabled: [1, Detection of channel input clock absence interrupt is enabled] + SCDIE: + Disabled: [0, Short-circuit detector interrupt is disabled] + Enabled: [1, Short-circuit detector interrupt is enabled] + +FLT?CR2: + AWDCH: + Disabled: [0, Analog watchdog is disabled on channel y] + Enabled: [1, Analog watchdog is enabled on channel y] + EXCH: + Disabled: [0, Extremes detector does not accept data from channel y] + Enabled: [1, Extremes detector accepts data from channel y] + AWDIE: + Disabled: [0, Analog watchdog interrupt is disabled] + Enabled: [1, Analog watchdog interrupt is enabled] + ROVRIE: + Disabled: [0, Regular data overrun interrupt is disabled] + Enabled: [1, Regular data overrun interrupt is enabled] + JOVRIE: + Disabled: [0, Injected data overrun interrupt is disabled] + Enabled: [1, Injected data overrun interrupt is enabled] + REOCIE: + Disabled: [0, Regular end of conversion interrupt is disabled] + Enabled: [1, Regular end of conversion interrupt is enabled] + JEOCIE: + Disabled: [0, Injected end of conversion interrupt is disabled] + Enabled: [1, Injected end of conversion interrupt is enabled] + +FLT?ISR: + SCDF: + Clear: [0, No short-circuit detector event occurred on channel y] + Set: + [ + 1, + "The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_CHyAWSCDR registers", + ] + CKABF: + Clear: [0, Clock signal on channel y is present.] + Set: [1, Clock signal on channel y is not present] + RCIP: + NotInProgress: [0, No request to convert the regular channel has been issued] + InProgress: + [1, The conversion of the regular channel is in progress or a request for a regular conversion is pending] + JCIP: + NotInProgress: + [0, No request to convert the injected channel group (neither by software nor by trigger) has been issued] + InProgress: + [ + 1, + "The conversion of the injected channel group is in progress or a request for a injected conversion is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection", + ] + AWDF: + Clear: [0, No Analog watchdog event occurred] + Set: + [ + 1, + The analog watchdog block detected voltage which crosses the value programmed in the DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers, + ] + ROVRF: + Clear: [0, No regular conversion overrun has occurred] + Set: + [ + 1, + "A regular conversion overrun has occurred, which means that a regular conversion finished while REOCF was already ‘1’. RDATAR is not affected by overruns", + ] + JOVRF: + Clear: [0, No injected conversion overrun has occurred] + Set: + [ + 1, + "An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns", + ] + REOCF: + Clear: [0, No regular conversion has completed] + Set: [1, A regular conversion has completed and its data may be read] + JEOCF: + Clear: [0, No injected conversion has completed] + Set: [1, An injected conversion has completed and its data may be read] + +FLT?ICR: + CLRSCDF: [0, 0xFF] + CLRCKABF: [0, 0xFF] + CLRROVRF: + _write: + Clear: [1, "Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register"] + CLRJOVRF: + _write: + Clear: [1, "Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register"] + +FLT?JCHGR: + JCHG: [0, 0xFF] + +FLT?FCR: + FORD: + FastSinc: [0, FastSinc filter type] + Sinc1: [1, Sinc1 filter type] + Sinc2: [2, Sinc2 filter type] + Sinc3: [3, Sinc3 filter type] + Sinc4: [4, Sinc4 filter type] + Sinc5: [5, Sinc5 filter type] + FOSR: [0, 1023] + IOSR: [0, 255] + +FLT?JDATAR: + JDATA: [0, 0xFFFFFF] + JDATACH: [0, 0x7] + +FLT?RDATAR: + RDATA: [0, 0xFFFFFF] + RDATACH: [0, 7] + +FLT?AWHTR: + AWHT: [0, 0xFFFFFF] + BKAWH?: + NotAssigned: [0, Break i signal is not assigned to an analog watchdog high threshold event] + Assigned: [1, Break i signal is assigned to an analog watchdog high threshold event] + +FLT?AWLTR: + AWLT: [0, 0xFFFFFF] + BKAWL?: + NotAssigned: [0, Break i signal is not assigned to an analog watchdog low threshold event] + Assigned: [1, Break i signal is assigned to an analog watchdog low threshold event] + +FLT?AWSR: + AWHTF?: + NoError: [0, No high threshold error] + Error: [1, A high threshold error on channel y] + AWLTF?: + NoError: [0, No low threshold error] + Error: [1, A low threshold error on channel y] + +FLT?AWCFR: + CLRAWHTF?: + _W1C: + Clear: [1, "Clear the corresponding AWHTF[y] bit"] + CLRAWLTF?: + _W1C: + Clear: [1, "Clear the corresponding AWLTF[y] bit"] + +FLT?EXMAX: + EXMAX: [0, 0xFFFFFF] + EXMAXCH: [0, 0x7] + +FLT?EXMIN: + EXMIN: [0, 0xFFFFFF] + EXMINCH: [0, 0x7] + +FLT?CNVTIMR: + CNVCNT: [0, 0xFFFFFFF] diff --git a/devices/fields/dma/bdma.yaml b/devices/fields/dma/bdma.yaml new file mode 100644 index 000000000..2d84c0863 --- /dev/null +++ b/devices/fields/dma/bdma.yaml @@ -0,0 +1,66 @@ +# Basic DMA as found on H7, .. + +ISR: + TCIF?: + NotComplete: [0, No transfer complete event on channel x] + Complete: [1, A transfer complete event occurred on channel x] + HTIF?: + NotHalf: [0, No half transfer event on channel x] + Half: [1, A half transfer event occurred on channel x] + TEIF?: + NoError: [0, No transfer error on channel x] + Error: [1, A transfer error occurred on channel x] + GIF?: + NoEvent: [0, "No TE, HT or TC event on channel x"] + Event: [1, "A TE, HT or TC event occurred on channel x"] +IFCR: + CTCIF?: + Clear: [1, Clear the corresponding TCIFx flag] + CHTIF?: + Clear: [1, Clear the corresponding HTIFx flag] + CTEIF?: + Clear: [1, Clear the corresponding TEIFx flag] + CGIF?: + Clear: [1, Clear the corresponding CGIFx flag] +CCR?: + CT: + Memory0: [0, The current target memory is Memory 0] + Memory1: [1, The current target memory is Memory 1] + DBM: + Disabled: [0, No buffer switching at the end of transfer] + Enabled: [1, Memory target switched at the end of the DMA transfer] + MEM2MEM: + Disabled: [0, Memory-to-memory mode disabled] + Enabled: [1, Memory-to-memory mode enabled] + PL: + Low: [0, Low] + Medium: [1, Medium] + High: [2, High] + VeryHigh: [3, Very high] + "[MP]SIZE": + Bits8: [0, Byte (8-bit)] + Bits16: [1, Half-word (16-bit)] + Bits32: [2, Word (32-bit)] + "[MP]INC": + Fixed: [0, Address pointer is fixed] + Incremented: [1, Address pointer is incremented after each data transfer] + CIRC: + Disabled: [0, Circular mode disabled] + Enabled: [1, Circular mode enabled] + DIR: + PeripheralToMemory: [0, Peripheral-to-memory] + MemoryToPeripheral: [1, Memory-to-peripheral] + TCIE: + Disabled: [0, TC interrupt disabled] + Enabled: [1, TC interrupt enabled] + HTIE: + Disabled: [0, HT interrupt disabled] + Enabled: [1, HT interrupt enabled] + TEIE: + Disabled: [0, TE interrupt disabled] + Enabled: [1, TE interrupt enabled] + EN: + Disabled: [0, Channel disabled] + Enabled: [1, Channel enabled] +CNDTR?: + NDT: [0, 65535] diff --git a/devices/fields/dma/common.yaml b/devices/fields/dma/common.yaml new file mode 100644 index 000000000..049ef5f77 --- /dev/null +++ b/devices/fields/dma/common.yaml @@ -0,0 +1,57 @@ +ISR: + TEIF*: + NoError: [0, No transfer error] + Error: [1, A transfer error has occured] + HTIF*: + NotHalf: [0, No half transfer event] + Half: [1, A half transfer event has occured] + TCIF*: + NotComplete: [0, No transfer complete event] + Complete: [1, A transfer complete event has occured] + GIF*: + NoEvent: [0, "No transfer error, half event, complete event"] + Event: [1, "A transfer error, half event or complete event has occured"] +IFCR: + CTEIF*: + Clear: [1, Clears the TEIF flag in the ISR register] + CHTIF*: + Clear: [1, Clears the HTIF flag in the ISR register] + CTCIF*: + Clear: [1, Clears the TCIF flag in the ISR register] + CGIF*: + Clear: [1, "Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register"] + +CCR*: + MEM2MEM: + Disabled: [0, Memory to memory mode disabled] + Enabled: [1, Memory to memory mode enabled] + PL: + Low: [0, Low priority] + Medium: [1, Medium priority] + High: [2, High priority] + VeryHigh: [3, Very high priority] + "[MP]SIZE": + Bits8: [0, 8-bit size] # or Byte + Bits16: [1, 16-bit size] # or HalfWord + Bits32: [2, 32-bit size] # or Word + "[MP]INC": + Disabled: [0, Increment mode disabled] + Enabled: [1, Increment mode enabled] + CIRC: + Disabled: [0, Circular buffer disabled] + Enabled: [1, Circular buffer enabled] + DIR: + FromPeripheral: [0, Read from peripheral] + FromMemory: [1, Read from memory] + TEIE: + Disabled: [0, Transfer Error interrupt disabled] + Enabled: [1, Transfer Error interrupt enabled] + HTIE: + Disabled: [0, Half Transfer interrupt disabled] + Enabled: [1, Half Transfer interrupt enabled] + TCIE: + Disabled: [0, Transfer Complete interrupt disabled] + Enabled: [1, Transfer Complete interrupt enabled] + EN: + Disabled: [0, Channel disabled] + Enabled: [1, Channel enabled] diff --git a/devices/fields/dma/dma2d_common.yaml b/devices/fields/dma/dma2d_common.yaml new file mode 100644 index 000000000..50ce9a077 --- /dev/null +++ b/devices/fields/dma/dma2d_common.yaml @@ -0,0 +1,78 @@ +# "Chrom-Art Accelerator" 2D DMA engine +# Common fields + +CR: + MODE: + MemoryToMemory: [0, Memory-to-memory (FG fetch only)] + MemoryToMemoryPFC: [1, Memory-to-memory with PFC (FG fetch only with FG PFC active)] + MemoryToMemoryPFCBlending: [2, Memory-to-memory with blending (FG and BG fetch with PFC and blending)] + RegisterToMemory: [3, Register-to-memory] + CEIE: + Disabled: [0, CE interrupt disabled] + Enabled: [1, CE interrupt enabled] + CTCIE: + Disabled: [0, CTC interrupt disabled] + Enabled: [1, CTC interrupt enabled] + CAEIE: + Disabled: [0, CAE interrupt disabled] + Enabled: [1, CAE interrupt enabled] + TWIE: + Disabled: [0, TW interrupt disabled] + Enabled: [1, TW interrupt enabled] + TCIE: + Disabled: [0, TC interrupt disabled] + Enabled: [1, TC interrupt enabled] + TEIE: + Disabled: [0, TE interrupt disabled] + Enabled: [1, TE interrupt enabled] + ABORT: + AbortRequest: [1, Transfer abort requested] + SUSP: + NotSuspended: [0, Transfer not suspended] + Suspended: [1, Transfer suspended] + START: + Start: [1, Launch the DMA2D] +IFCR: + CCEIF: + Clear: [1, Clear the CEIF flag in the ISR register] + CCTCIF: + Clear: [1, Clear the CTCIF flag in the ISR register] + CAECIF: + Clear: [1, Clear the CAEIF flag in the ISR register] + CTWIF: + Clear: [1, Clear the TWIF flag in the ISR register] + CTCIF: + Clear: [1, Clear the TCIF flag in the ISR register] + CTEIF: + Clear: [1, Clear the TEIF flag in the ISR register] +"[FB]GPFCCR": + ALPHA: [0, 255] + AM: + NoModify: [0, No modification of alpha channel] + Replace: [1, "Replace with value in ALPHA[7:0]"] + Multiply: [2, "Multiply with value in ALPHA[7:0]"] + CS: [0, 255] + START: + Start: [1, Start the automatic loading of the CLUT] + CCM: + ARGB8888: [0, CLUT color format ARGB8888] + RGB888: [1, CLUT color format RGB888] +"[FB]GCOLR": + RED: [0, 255] + GREEN: [0, 255] + BLUE: [0, 255] +OPFCCR: + CM: + ARGB8888: [0, ARGB8888] + RGB888: [1, RGB888] + RGB565: [2, RGB565] + ARGB1555: [3, ARGB1555] + ARGB4444: [4, ARGB4444] +NLR: + PL: [0, 16383] + NL: [0, 65535] +AMTCR: + DT: [0, 255] + EN: + Disabled: [0, Disabled AHB/AXI dead-time functionality] + Enabled: [1, Enabled AHB/AXI dead-time functionality] diff --git a/devices/fields/dma/dma2d_v1.yaml b/devices/fields/dma/dma2d_v1.yaml new file mode 100644 index 000000000..ac8c71966 --- /dev/null +++ b/devices/fields/dma/dma2d_v1.yaml @@ -0,0 +1,20 @@ +# "Chrom-Art Accelerator" 2D DMA engine +# Version 1 found on F4 + +_include: dma2d_common.yaml + +"[FB]GOR,OOR": + LO: [0, 16383] +"[FB]GPFCCR": + CM: + ARGB8888: [0, Color mode ARGB8888] + RGB888: [1, Color mode RGB888] + RGB565: [2, Color mode RGB565] + ARGB1555: [3, Color mode ARGB1555] + ARGB4444: [4, Color mode ARGB4444] + L8: [5, Color mode L8] + AL44: [6, Color mode AL44] + AL88: [7, Color mode AL88] + L4: [8, Color mode L4] + A8: [9, Color mode A8] + A4: [10, Color mode A4] diff --git a/devices/fields/dma/dma2d_v2.yaml b/devices/fields/dma/dma2d_v2.yaml new file mode 100644 index 000000000..52775f035 --- /dev/null +++ b/devices/fields/dma/dma2d_v2.yaml @@ -0,0 +1,45 @@ +# "Chrom-Art Accelerator" 2D DMA engine +# Version 2 found on H7 + +_include: dma2d_common.yaml + +"[FB]GPFCCR,OPFCCR": + RBS: + Regular: [0, No Red Blue Swap (RGB or ARGB)] + Swap: [1, Red Blue Swap (BGR or ABGR)] + AI: + RegularAlpha: [0, Regular alpha] + InvertedAlpha: [1, Inverted alpha] +FGPFCCR: + CM: + ARGB8888: [0, Color mode ARGB8888] + RGB888: [1, Color mode RGB888] + RGB565: [2, Color mode RGB565] + ARGB1555: [3, Color mode ARGB1555] + ARGB4444: [4, Color mode ARGB4444] + L8: [5, Color mode L8] + AL44: [6, Color mode AL44] + AL88: [7, Color mode AL88] + L4: [8, Color mode L4] + A8: [9, Color mode A8] + A4: [10, Color mode A4] + YCbCr: [11, Color mode YCbCr] +BGPFCCR: + CM: + ARGB8888: [0, Color mode ARGB8888] + RGB888: [1, Color mode RGB888] + RGB565: [2, Color mode RGB565] + ARGB1555: [3, Color mode ARGB1555] + ARGB4444: [4, Color mode ARGB4444] + L8: [5, Color mode L8] + AL44: [6, Color mode AL44] + AL88: [7, Color mode AL88] + L4: [8, Color mode L4] + A8: [9, Color mode A8] + A4: [10, Color mode A4] +OPFCCR: + SB: + Regular: [0, Regular byte order] + SwapBytes: [1, Bytes are swapped two by two] +"[FB]GOR,OOR": + LO: [0, 65535] diff --git a/devices/fields/dma/dma_v1_with_remapping.yaml b/devices/fields/dma/dma_v1_with_remapping.yaml new file mode 100644 index 000000000..08d16ea35 --- /dev/null +++ b/devices/fields/dma/dma_v1_with_remapping.yaml @@ -0,0 +1,23 @@ +# DMA v1 with remapping functionnality +# Found on F0 and F4 family and on specific devices (stm32f09x). + +_include: v1.yaml + +CSELR: + C*S: + NoMapping: [0, Default mapping] + Map1: [1, Mapping 1] + Map2: [2, Mapping 2] + Map3: [3, Mapping 3] + Map4: [4, Mapping 4] + Map5: [5, Mapping 5] + Map6: [6, Mapping 6] + Map7: [7, Mapping 7] + Map8: [8, Mapping 8] + Map9: [9, Mapping 9] + Map10: [10, Mapping 10] + Map11: [11, Mapping 11] + Map12: [12, Mapping 12] + Map13: [13, Mapping 13] + Map14: [14, Mapping 14] + Map15: [15, Mapping 15] diff --git a/devices/fields/dma/dma_v2.yaml b/devices/fields/dma/dma_v2.yaml new file mode 100644 index 000000000..b2a3813e7 --- /dev/null +++ b/devices/fields/dma/dma_v2.yaml @@ -0,0 +1,6 @@ +# DMA as used on F4 and F7 + +_include: + - dma_v3.yaml +S?CR: + CHSEL: [0, 7] diff --git a/devices/fields/dma/dma_v21.yaml b/devices/fields/dma/dma_v21.yaml new file mode 100644 index 000000000..405be730f --- /dev/null +++ b/devices/fields/dma/dma_v21.yaml @@ -0,0 +1,6 @@ +# DMA as used on F4 and F7 + +_include: + - dma_v3.yaml +S?CR: + CHSEL: [0, 15] diff --git a/devices/fields/dma/dma_v3.yaml b/devices/fields/dma/dma_v3.yaml new file mode 100644 index 000000000..4f5c9917d --- /dev/null +++ b/devices/fields/dma/dma_v3.yaml @@ -0,0 +1,102 @@ +# DMA as used on H7 + +"[LH]ISR": + TCIF?: + NotComplete: [0, No transfer complete event on stream x] + Complete: [1, A transfer complete event occurred on stream x] + HTIF?: + NotHalf: [0, No half transfer event on stream x] + Half: [1, A half transfer event occurred on stream x] + TEIF?: + NoError: [0, No transfer error on stream x] + Error: [1, A transfer error occurred on stream x] + DMEIF?: + NoError: [0, No Direct Mode error on stream x] + Error: [1, A Direct Mode error occurred on stream x] + FEIF?: + NoError: [0, No FIFO error event on stream x] + Error: [1, A FIFO error event occurred on stream x] +"[LH]IFCR": + CTCIF?: + Clear: [1, Clear the corresponding TCIFx flag] + CHTIF?: + Clear: [1, Clear the corresponding HTIFx flag] + CTEIF?: + Clear: [1, Clear the corresponding TEIFx flag] + CDMEIF?: + Clear: [1, Clear the corresponding DMEIFx flag] + CFEIF?: + Clear: [1, Clear the corresponding CFEIFx flag] +S?CR: + "[MP]BURST": + Single: [0, Single transfer] + INCR4: [1, Incremental burst of 4 beats] + INCR8: [2, Incremental burst of 8 beats] + INCR16: [3, Incremental burst of 16 beats] + CT: + Memory0: [0, The current target memory is Memory 0] + Memory1: [1, The current target memory is Memory 1] + DBM: + Disabled: [0, No buffer switching at the end of transfer] + Enabled: [1, Memory target switched at the end of the DMA transfer] + PL: + Low: [0, Low] + Medium: [1, Medium] + High: [2, High] + VeryHigh: [3, Very high] + PINCOS: + PSIZE: [0, The offset size for the peripheral address calculation is linked to the PSIZE] + Fixed4: [1, The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)] + "[MP]SIZE": + Bits8: [0, Byte (8-bit)] + Bits16: [1, Half-word (16-bit)] + Bits32: [2, Word (32-bit)] + "[MP]INC": + Fixed: [0, Address pointer is fixed] + Incremented: [1, Address pointer is incremented after each data transfer] + CIRC: + Disabled: [0, Circular mode disabled] + Enabled: [1, Circular mode enabled] + DIR: + PeripheralToMemory: [0, Peripheral-to-memory] + MemoryToPeripheral: [1, Memory-to-peripheral] + MemoryToMemory: [2, Memory-to-memory] + PFCTRL: + DMA: [0, The DMA is the flow controller] + Peripheral: [1, The peripheral is the flow controller] + TCIE: + Disabled: [0, TC interrupt disabled] + Enabled: [1, TC interrupt enabled] + HTIE: + Disabled: [0, HT interrupt disabled] + Enabled: [1, HT interrupt enabled] + TEIE: + Disabled: [0, TE interrupt disabled] + Enabled: [1, TE interrupt enabled] + DMEIE: + Disabled: [0, DME interrupt disabled] + Enabled: [1, DME interrupt enabled] + EN: + Disabled: [0, Stream disabled] + Enabled: [1, Stream enabled] +S?NDTR: + NDT: [0, 65535] +S?FCR: + FEIE: + Disabled: [0, FE interrupt disabled] + Enabled: [1, FE interrupt enabled] + FS: + Quarter1: [0, "0 < fifo_level < 1/4"] + Quarter2: [1, "1/4 <= fifo_level < 1/2"] + Quarter3: [2, "1/2 <= fifo_level < 3/4"] + Quarter4: [3, "3/4 <= fifo_level < full"] + Empty: [4, FIFO is empty] + Full: [5, FIFO is full] + DMDIS: + Enabled: [0, Direct mode is enabled] + Disabled: [1, Direct mode is disabled] + FTH: + Quarter: [0, 1/4 full FIFO] + Half: [1, 1/2 full FIFO] + ThreeQuarters: [2, 3/4 full FIFO] + Full: [3, Full FIFO] diff --git a/devices/fields/dma/dma_wl.yaml b/devices/fields/dma/dma_wl.yaml new file mode 100644 index 000000000..1ce702efd --- /dev/null +++ b/devices/fields/dma/dma_wl.yaml @@ -0,0 +1,10 @@ +_include: + - common.yaml + +CCR?: + PRIV: + Disabled: [0, Disabled] + Enabled: [1, Enabled] + +CNDTR?: + NDT: [0, 0x3FFFF] diff --git a/devices/fields/dma/dmamux1_v1.yaml b/devices/fields/dma/dmamux1_v1.yaml new file mode 100644 index 000000000..f3fbceb15 --- /dev/null +++ b/devices/fields/dma/dmamux1_v1.yaml @@ -0,0 +1,136 @@ +C*CR: + SYNC_ID: + dmamux1_evt0: [0, "Signal `dmamux1_evt0` selected as synchronization input"] + dmamux1_evt1: [1, "Signal `dmamux1_evt1` selected as synchronization input"] + dmamux1_evt2: [2, "Signal `dmamux1_evt2` selected as synchronization input"] + lptim1_out: [3, "Signal `lptim1_out` selected as synchronization input"] + lptim2_out: [4, "Signal `lptim2_out` selected as synchronization input"] + lptim3_out: [5, "Signal `lptim3_out` selected as synchronization input"] + extit0: [6, "Signal `extit0` selected as synchronization input"] + tim12_trgo: [7, "Signal `tim12_trgo` selected as synchronization input"] + DMAREQ_ID: + none: [0, No signal selected as request input] + dmamux1_req_gen0: [1, "Signal `dmamux1_req_gen0` selected as request input"] + dmamux1_req_gen1: [2, "Signal `dmamux1_req_gen1` selected as request input"] + dmamux1_req_gen2: [3, "Signal `dmamux1_req_gen2` selected as request input"] + dmamux1_req_gen3: [4, "Signal `dmamux1_req_gen3` selected as request input"] + dmamux1_req_gen4: [5, "Signal `dmamux1_req_gen4` selected as request input"] + dmamux1_req_gen5: [6, "Signal `dmamux1_req_gen5` selected as request input"] + dmamux1_req_gen6: [7, "Signal `dmamux1_req_gen6` selected as request input"] + dmamux1_req_gen7: [8, "Signal `dmamux1_req_gen7` selected as request input"] + adc1_dma: [9, "Signal `adc1_dma` selected as request input"] + adc2_dma: [10, "Signal `adc2_dma` selected as request input"] + tim1_ch1: [11, "Signal `tim1_ch1` selected as request input"] + tim1_ch2: [12, "Signal `tim1_ch2` selected as request input"] + tim1_ch3: [13, "Signal `tim1_ch3` selected as request input"] + tim1_ch4: [14, "Signal `tim1_ch4` selected as request input"] + tim1_up: [15, "Signal `tim1_up` selected as request input"] + tim1_trig: [16, "Signal `tim1_trig` selected as request input"] + tim1_com: [17, "Signal `tim1_com` selected as request input"] + tim2_ch1: [18, "Signal `tim2_ch1` selected as request input"] + tim2_ch2: [19, "Signal `tim2_ch2` selected as request input"] + tim2_ch3: [20, "Signal `tim2_ch3` selected as request input"] + tim2_ch4: [21, "Signal `tim2_ch4` selected as request input"] + tim2_up: [22, "Signal `tim2_up` selected as request input"] + tim3_ch1: [23, "Signal `tim3_ch1` selected as request input"] + tim3_ch2: [24, "Signal `tim3_ch2` selected as request input"] + tim3_ch3: [25, "Signal `tim3_ch3` selected as request input"] + tim3_ch4: [26, "Signal `tim3_ch4` selected as request input"] + tim3_up: [27, "Signal `tim3_up` selected as request input"] + tim3_trig: [28, "Signal `tim3_trig` selected as request input"] + tim4_ch1: [29, "Signal `tim4_ch1` selected as request input"] + tim4_ch2: [30, "Signal `tim4_ch2` selected as request input"] + tim4_ch3: [31, "Signal `tim4_ch3` selected as request input"] + tim4_up: [32, "Signal `tim4_up` selected as request input"] + i2c1_rx_dma: [33, "Signal `i2c1_rx_dma` selected as request input"] + i2c1_tx_dma: [34, "Signal `i2c1_tx_dma` selected as request input"] + i2c2_rx_dma: [35, "Signal `i2c2_rx_dma` selected as request input"] + i2c2_tx_dma: [36, "Signal `i2c2_tx_dma` selected as request input"] + spi1_rx_dma: [37, "Signal `spi1_rx_dma` selected as request input"] + spi1_tx_dma: [38, "Signal `spi1_tx_dma` selected as request input"] + spi2_rx_dma: [39, "Signal `spi2_rx_dma` selected as request input"] + spi2_tx_dma: [40, "Signal `spi2_tx_dma` selected as request input"] + usart1_rx_dma: [41, "Signal `usart1_rx_dma` selected as request input"] + usart1_tx_dma: [42, "Signal `usart1_tx_dma` selected as request input"] + usart2_rx_dma: [43, "Signal `usart2_rx_dma` selected as request input"] + usart2_tx_dma: [44, "Signal `usart2_tx_dma` selected as request input"] + usart3_rx_dma: [45, "Signal `usart3_rx_dma` selected as request input"] + usart3_tx_dma: [46, "Signal `usart3_tx_dma` selected as request input"] + tim8_ch1: [47, "Signal `tim8_ch1` selected as request input"] + tim8_ch2: [48, "Signal `tim8_ch2` selected as request input"] + tim8_ch3: [49, "Signal `tim8_ch3` selected as request input"] + tim8_ch4: [50, "Signal `tim8_ch4` selected as request input"] + tim8_up: [51, "Signal `tim8_up` selected as request input"] + tim8_trig: [52, "Signal `tim8_trig` selected as request input"] + tim8_com: [53, "Signal `tim8_com` selected as request input"] + tim5_ch1: [55, "Signal `tim5_ch1` selected as request input"] + tim5_ch2: [56, "Signal `tim5_ch2` selected as request input"] + tim5_ch3: [57, "Signal `tim5_ch3` selected as request input"] + tim5_ch4: [58, "Signal `tim5_ch4` selected as request input"] + tim5_up: [59, "Signal `tim5_up` selected as request input"] + tim5_trig: [60, "Signal `tim5_trig` selected as request input"] + spi3_rx_dma: [61, "Signal `spi3_rx_dma` selected as request input"] + spi3_tx_dma: [62, "Signal `spi3_tx_dma` selected as request input"] + uart4_rx_dma: [63, "Signal `uart4_rx_dma` selected as request input"] + uart4_tx_dma: [64, "Signal `uart4_tx_dma` selected as request input"] + uart5_rx_dma: [65, "Signal `uart5_rx_dma` selected as request input"] + uart5_tx_dma: [66, "Signal `uart5_tx_dma` selected as request input"] + dac_ch1_dma: [67, "Signal `dac_ch1_dma` selected as request input"] + dac_ch2_dma: [68, "Signal `dac_ch2_dma` selected as request input"] + tim6_up: [69, "Signal `tim6_up` selected as request input"] + tim7_up: [70, "Signal `tim7_up` selected as request input"] + usart6_rx_dma: [71, "Signal `usart6_rx_dma` selected as request input"] + usart6_tx_dma: [72, "Signal `usart6_tx_dma` selected as request input"] + i2c3_rx_dma: [73, "Signal `i2c3_rx_dma` selected as request input"] + i2c3_tx_dma: [74, "Signal `i2c3_tx_dma` selected as request input"] + dcmi_dma: [75, "Signal `dcmi_dma` selected as request input"] + cryp_in_dma: [76, "Signal `cryp_in_dma` selected as request input"] + cryp_out_dma: [77, "Signal `cryp_out_dma` selected as request input"] + hash_in_dma: [78, "Signal `hash_in_dma` selected as request input"] + uart7_rx_dma: [79, "Signal `uart7_rx_dma` selected as request input"] + uart7_tx_dma: [80, "Signal `uart7_tx_dma` selected as request input"] + uart8_rx_dma: [81, "Signal `uart8_rx_dma` selected as request input"] + uart8_tx_dma: [82, "Signal `uart8_tx_dma` selected as request input"] + spi4_rx_dma: [83, "Signal `spi4_rx_dma` selected as request input"] + spi4_tx_dma: [84, "Signal `spi4_tx_dma` selected as request input"] + spi5_rx_dma: [85, "Signal `spi5_rx_dma` selected as request input"] + spi5_tx_dma: [86, "Signal `spi5_tx_dma` selected as request input"] + sai1a_dma: [87, "Signal `sai1a_dma` selected as request input"] + sai1b_dma: [88, "Signal `sai1b_dma` selected as request input"] + sai2a_dma: [89, "Signal `sai2a_dma` selected as request input"] + sai2b_dma: [90, "Signal `sai2b_dma` selected as request input"] + swpmi_rx_dma: [91, "Signal `swpmi_rx_dma` selected as request input"] + swpmi_tx_dma: [92, "Signal `swpmi_tx_dma` selected as request input"] + spdifrx_dat_dma: [93, "Signal `spdifrx_dat_dma` selected as request input"] + spdifrx_ctrl_dma: [94, "Signal `spdifrx_ctrl_dma` selected as request input"] + hr_req1: [95, "Signal `hr_req(1)` selected as request input"] + hr_req2: [96, "Signal `hr_req(2)` selected as request input"] + hr_req3: [97, "Signal `hr_req(3)` selected as request input"] + hr_req4: [98, "Signal `hr_req(4)` selected as request input"] + hr_req5: [99, "Signal `hr_req(5)` selected as request input"] + hr_req6: [100, "Signal `hr_req(6)` selected as request input"] + dfsdm1_dma0: [101, "Signal `dfsdm1_dma0` selected as request input"] + dfsdm1_dma1: [102, "Signal `dfsdm1_dma1` selected as request input"] + dfsdm1_dma2: [103, "Signal `dfsdm1_dma2` selected as request input"] + dfsdm1_dma3: [104, "Signal `dfsdm1_dma3` selected as request input"] + tim15_ch1: [105, "Signal `tim15_ch1` selected as request input"] + tim15_up: [106, "Signal `tim15_up` selected as request input"] + tim15_trig: [107, "Signal `tim15_trig` selected as request input"] + tim15_com: [108, "Signal `tim15_com` selected as request input"] + tim16_ch1: [109, "Signal `tim16_ch1` selected as request input"] + tim16_up: [110, "Signal `tim16_up` selected as request input"] + tim17_ch1: [111, "Signal `tim17_ch1` selected as request input"] + tim17_up: [112, "Signal `tim17_up` selected as request input"] + sai3_a_dma: [113, "Signal `sai3_a_dma` selected as request input"] + sai3_b_dma: [114, "Signal `sai3_b_dma` selected as request input"] + adc3_dma: [115, "Signal `adc3_dma` selected as request input"] +RG*CR: + SIG_ID: + dmamux1_evt0: [0, "Signal `dmamux1_evt0` selected as trigger input"] + dmamux1_evt1: [1, "Signal `dmamux1_evt1` selected as trigger input"] + dmamux1_evt2: [2, "Signal `dmamux1_evt2` selected as trigger input"] + lptim1_out: [3, "Signal `lptim1_out` selected as trigger input"] + lptim2_out: [4, "Signal `lptim2_out` selected as trigger input"] + lptim3_out: [5, "Signal `lptim3_out` selected as trigger input"] + extit0: [6, "Signal `extit0` selected as trigger input"] + tim12_trgo: [7, "Signal `tim12_trgo` selected as trigger input"] diff --git a/devices/fields/dma/dmamux2_v1.yaml b/devices/fields/dma/dmamux2_v1.yaml new file mode 100644 index 000000000..a84426948 --- /dev/null +++ b/devices/fields/dma/dmamux2_v1.yaml @@ -0,0 +1,69 @@ +C*CR: + SYNC_ID: + dmamux2_evt0: [0, "Signal `dmamux2_evt0` selected as synchronization input"] + dmamux2_evt1: [1, "Signal `dmamux2_evt1` selected as synchronization input"] + dmamux2_evt2: [2, "Signal `dmamux2_evt2` selected as synchronization input"] + dmamux2_evt3: [3, "Signal `dmamux2_evt3` selected as synchronization input"] + dmamux2_evt4: [4, "Signal `dmamux2_evt4` selected as synchronization input"] + dmamux2_evt5: [5, "Signal `dmamux2_evt5` selected as synchronization input"] + lpuart1_rx_wkup: [6, "Signal `lpuart1_rx_wkup` selected as synchronization input"] + lpuart1_tx_wkup: [7, "Signal `lpuart1_tx_wkup` selected as synchronization input"] + lptim2_out: [8, "Signal `lptim2_out` selected as synchronization input"] + lptim3_out: [9, "Signal `lptim3_out` selected as synchronization input"] + i2c4_wkup: [10, "Signal `i2c4_wkup` selected as synchronization input"] + spi6_wkup: [11, "Signal `spi6_wkup` selected as synchronization input"] + comp1_out: [12, "Signal `comp1_out` selected as synchronization input"] + rtc_wkup: [13, "Signal `rtc_wkup` selected as synchronization input"] + syscfg_exti0_mux: [14, "Signal `syscfg_exti0_mux` selected as synchronization input"] + syscfg_exti2_mux: [15, "Signal `syscfg_exti2_mux` selected as synchronization input"] + DMAREQ_ID: + none: [0, No signal selected as request input] + dmamux2_req_gen0: [1, "Signal `dmamux2_req_gen0` selected as request input"] + dmamux2_req_gen1: [2, "Signal `dmamux2_req_gen1` selected as request input"] + dmamux2_req_gen2: [3, "Signal `dmamux2_req_gen2` selected as request input"] + dmamux2_req_gen3: [4, "Signal `dmamux2_req_gen3` selected as request input"] + dmamux2_req_gen4: [5, "Signal `dmamux2_req_gen4` selected as request input"] + dmamux2_req_gen5: [6, "Signal `dmamux2_req_gen5` selected as request input"] + dmamux2_req_gen6: [7, "Signal `dmamux2_req_gen6` selected as request input"] + dmamux2_req_gen7: [8, "Signal `dmamux2_req_gen7` selected as request input"] + lpuart1_rx_dma: [9, "Signal `lpuart1_rx_dma` selected as request input"] + lpuart1_tx_dma: [10, "Signal `lpuart1_tx_dma` selected as request input"] + spi6_rx_dma: [11, "Signal `spi6_rx_dma` selected as request input"] + spi6_tx_dma: [12, "Signal `spi6_tx_dma` selected as request input"] + i2c4_rx_dma: [13, "Signal `i2c4_rx_dma` selected as request input"] + i2c4_tx_dma: [14, "Signal `i2c4_tx_dma` selected as request input"] + sai4_a_dma: [15, "Signal `sai4_a_dma` selected as request input"] + sai4_b_dma: [16, "Signal `sai4_b_dma` selected as request input"] + adc3_dma: [17, "Signal `adc3_dma` selected as request input"] +RG*CR: + SIG_ID: + dmamux2_evt0: [0, "Signal `dmamux2_evt0` selected as trigger input"] + dmamux2_evt1: [1, "Signal `dmamux2_evt1` selected as trigger input"] + dmamux2_evt2: [2, "Signal `dmamux2_evt2` selected as trigger input"] + dmamux2_evt3: [3, "Signal `dmamux2_evt3` selected as trigger input"] + dmamux2_evt4: [4, "Signal `dmamux2_evt4` selected as trigger input"] + dmamux2_evt5: [5, "Signal `dmamux2_evt5` selected as trigger input"] + dmamux2_evt6: [6, "Signal `dmamux2_evt6` selected as trigger input"] + lpuart_rx_wkup: [7, "Signal `lpuart_rx_wkup` selected as trigger input"] + lpuart_tx_wkup: [8, "Signal `lpuart_tx_wkup` selected as trigger input"] + lptim2_wkup: [9, "Signal `lptim2_wkup` selected as trigger input"] + lptim2_out: [10, "Signal `lptim2_out` selected as trigger input"] + lptim3_wkup: [11, "Signal `lptim3_wkup` selected as trigger input"] + lptim3_out: [12, "Signal `lptim3_out` selected as trigger input"] + lptim4_ait: [13, "Signal `lptim4_ait` selected as trigger input"] + lptim5_ait: [14, "Signal `lptim5_ait` selected as trigger input"] + i2c4_wkup: [15, "Signal `i2c4_wkup` selected as trigger input"] + spi6_wkup: [16, "Signal `spi6_wkup` selected as trigger input"] + comp1_out: [17, "Signal `comp1_out` selected as trigger input"] + comp2_out: [18, "Signal `comp2_out` selected as trigger input"] + rtc_wkup: [19, "Signal `rtc_wkup` selected as trigger input"] + syscfg_exti0_mux: [20, "Signal `syscfg_exti0_mux` selected as trigger input"] + syscfg_exti2_mux: [21, "Signal `syscfg_exti2_mux` selected as trigger input"] + i2c4_event_it: [22, "Signal `i2c4_event_it` selected as trigger input"] + spi6_it: [23, "Signal `spi6_it` selected as trigger input"] + lpuart1_it_t: [24, "Signal `lpuart1_it_t` selected as trigger input"] + lpuart1_it_r: [25, "Signal `lpuart1_it_r` selected as trigger input"] + adc3_it: [26, "Signal `adc3_it` selected as trigger input"] + adc3_awd1: [27, "Signal `adc3_awd1` selected as trigger input"] + bdma_ch0_it: [28, "Signal `bdma_ch0_it` selected as trigger input"] + bdma_ch1_it: [29, "Signal `bdma_ch1_it` selected as trigger input"] diff --git a/devices/fields/dma/dmamux_v1.yaml b/devices/fields/dma/dmamux_v1.yaml new file mode 100644 index 000000000..9b5b0420b --- /dev/null +++ b/devices/fields/dma/dmamux_v1.yaml @@ -0,0 +1,54 @@ +C*CR: + NBREQ: [0, 31] + SPOL: + NoEdge: [0, "No event, i.e. no synchronization nor detection"] + RisingEdge: [1, Rising edge] + FallingEdge: [2, Falling edge] + BothEdges: [3, Rising and falling edges] + SE: + Disabled: [0, Synchronization disabled] + Enabled: [1, Synchronization enabled] + EGE: + Disabled: [0, Event generation disabled] + Enabled: [1, Event generation enabled] + SOIE: + Disabled: [0, Synchronization overrun interrupt disabled] + Enabled: [1, Synchronization overrun interrupt enabled] +RG?CR: + GNBREQ: [0, 31] + GPOL: + NoEdge: [0, "No event, i.e. no detection nor generation"] + RisingEdge: [1, Rising edge] + FallingEdge: [2, Falling edge] + BothEdges: [3, Rising and falling edges] + GE: + Disabled: [0, DMA request generation disabled] + Enabled: [1, DMA request enabled] + OIE: + Disabled: [0, Trigger overrun interrupt disabled] + Enabled: [1, Trigger overrun interrupt enabled] +CSR: + SOF*: + NoSyncEvent: + [ + 0, + "No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ", + ] + SyncEvent: + [ + 1, + "Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ", + ] +"CFR,CCFR": + CSOF*: + _W1C: + Clear: [1, Clear synchronization flag] +RGSR: + "OF?": + NoTrigger: + [0, "No new trigger event occured on DMA request generator channel x, before the request counter underrun"] + Trigger: [1, "New trigger event occured on DMA request generator channel x, before the request counter underrun"] +RGCFR: + COF?: + _W1C: + Clear: [1, Clear overrun flag] diff --git a/devices/fields/dma/dmamux_wl.yaml b/devices/fields/dma/dmamux_wl.yaml new file mode 100644 index 000000000..e3a927d3c --- /dev/null +++ b/devices/fields/dma/dmamux_wl.yaml @@ -0,0 +1,90 @@ +C?CR: + SYNC_ID: + exti0: [0, "Signal `EXTIx` selected as synchronization input"] + exti1: [1, "Signal `EXTIx` selected as synchronization input"] + exti2: [2, "Signal `EXTIx` selected as synchronization input"] + exti3: [3, "Signal `EXTIx` selected as synchronization input"] + exti4: [4, "Signal `EXTIx` selected as synchronization input"] + exti5: [5, "Signal `EXTIx` selected as synchronization input"] + exti6: [6, "Signal `EXTIx` selected as synchronization input"] + exti7: [7, "Signal `EXTIx` selected as synchronization input"] + exti8: [8, "Signal `EXTIx` selected as synchronization input"] + exti9: [9, "Signal `EXTIx` selected as synchronization input"] + exti10: [10, "Signal `EXTIx` selected as synchronization input"] + exti11: [11, "Signal `EXTIx` selected as synchronization input"] + exti12: [12, "Signal `EXTIx` selected as synchronization input"] + exti13: [13, "Signal `EXTIx` selected as synchronization input"] + exti14: [14, "Signal `EXTIx` selected as synchronization input"] + exti15: [15, "Signal `EXTIx` selected as synchronization input"] + dmamux1_evt0: [16, "Signal `dmamux1_evt0` selected as synchronization input"] + dmamux1_evt1: [17, "Signal `dmamux1_evt1` selected as synchronization input"] + lptim1_out: [18, "Signal `lptim1_out` selected as synchronization input"] + lptim2_out: [19, "Signal `lptim2_out` selected as synchronization input"] + lptim3_out: [20, "Signal `lptim3_out` selected as synchronization input"] + DMAREQ_ID: + none: [0, No signal selected as request input] + dmamux1_req_gen0: [1, "Signal `dmamux1_req_gen0` selected as request input"] + dmamux1_req_gen1: [2, "Signal `dmamux1_req_gen1` selected as request input"] + dmamux1_req_gen2: [3, "Signal `dmamux1_req_gen2` selected as request input"] + dmamux1_req_gen3: [4, "Signal `dmamux1_req_gen3` selected as request input"] + adc: [5, "Signal `adc1_dma` selected as request input"] + dat_out1: [6, "Signal `dac_out1_dma` selected as request input"] + spi1_rx_dma: [7, "Signal `spi1_rx_dma` selected as request input"] + spi1_tx_dma: [8, "Signal `spi1_tx_dma` selected as request input"] + spi2_rx_dma: [9, "Signal `spi2_rx_dma` selected as request input"] + spi2_tx_dma: [10, "Signal `spi2_tx_dma` selected as request input"] + i2c1_rx_dma: [11, "Signal `i2c1_rx_dma` selected as request input"] + i2c1_tx_dma: [12, "Signal `i2c1_tx_dma` selected as request input"] + i2c2_rx_dma: [13, "Signal `i2c2_rx_dma` selected as request input"] + i2c2_tx_dma: [14, "Signal `i2c2_tx_dma` selected as request input"] + i2c3_rx_dma: [15, "Signal `i2c3_rx_dma` selected as request input"] + i2c3_tx_dma: [16, "Signal `i2c3_tx_dma` selected as request input"] + usart1_rx_dma: [17, "Signal `usart1_rx_dma` selected as request input"] + usart1_tx_dma: [18, "Signal `usart1_tx_dma` selected as request input"] + usart2_rx_dma: [19, "Signal `usart2_rx_dma` selected as request input"] + usart2_tx_dma: [20, "Signal `usart2_tx_dma` selected as request input"] + lpuart1_rx_dma: [21, "Signal `lpuart1_rx_dma` selected as request input"] + lpuart1_tx_dma: [22, "Signal `lpuart1_tx_dma` selected as request input"] + tim1_ch1: [23, "Signal `tim1_ch1` selected as request input"] + tim1_ch2: [24, "Signal `tim1_ch2` selected as request input"] + tim1_ch3: [25, "Signal `tim1_ch3` selected as request input"] + tim1_ch4: [26, "Signal `tim1_ch4` selected as request input"] + tim1_up: [27, "Signal `tim1_up` selected as request input"] + tim1_trig: [28, "Signal `tim1_trig` selected as request input"] + tim1_com: [29, "Signal `tim1_com` selected as request input"] + tim2_ch1: [30, "Signal `tim2_ch1` selected as request input"] + tim2_ch2: [31, "Signal `tim2_ch2` selected as request input"] + tim2_ch3: [32, "Signal `tim2_ch3` selected as request input"] + tim2_ch4: [33, "Signal `tim2_ch4` selected as request input"] + tim2_up: [34, "Signal `tim2_up` selected as request input"] + tim16_ch1: [35, "Signal `tim16_ch1` selected as request input"] + tim16_up: [36, "Signal `tim16_up` selected as request input"] + tim17_ch1: [37, "Signal `tim17_ch1` selected as request input"] + tim17_up: [38, "Signal `tim17_up` selected as request input"] + aes_in: [39, "Signal `aes_in` selected as request input"] + aes_out: [40, "Signal `aes_out` selected as request input"] + subghzspi_rx: [41, "Signal `subghzspi_rx` selected as request input"] + subghzspi_tx: [42, "Signal `subghzspi_tx` selected as request input"] +RG?CR: + SIG_ID: + exti0: [0, "Signal `EXTIx` selected as synchronization input"] + exti1: [1, "Signal `EXTIx` selected as synchronization input"] + exti2: [2, "Signal `EXTIx` selected as synchronization input"] + exti3: [3, "Signal `EXTIx` selected as synchronization input"] + exti4: [4, "Signal `EXTIx` selected as synchronization input"] + exti5: [5, "Signal `EXTIx` selected as synchronization input"] + exti6: [6, "Signal `EXTIx` selected as synchronization input"] + exti7: [7, "Signal `EXTIx` selected as synchronization input"] + exti8: [8, "Signal `EXTIx` selected as synchronization input"] + exti9: [9, "Signal `EXTIx` selected as synchronization input"] + exti10: [10, "Signal `EXTIx` selected as synchronization input"] + exti11: [11, "Signal `EXTIx` selected as synchronization input"] + exti12: [12, "Signal `EXTIx` selected as synchronization input"] + exti13: [13, "Signal `EXTIx` selected as synchronization input"] + exti14: [14, "Signal `EXTIx` selected as synchronization input"] + exti15: [15, "Signal `EXTIx` selected as synchronization input"] + dmamux1_evt0: [16, "Signal `dmamux1_evt0` selected as synchronization input"] + dmamux1_evt1: [17, "Signal `dmamux1_evt1` selected as synchronization input"] + lptim1_out: [18, "Signal `lptim1_out` selected as synchronization input"] + lptim2_out: [19, "Signal `lptim2_out` selected as synchronization input"] + lptim3_out: [20, "Signal `lptim3_out` selected as synchronization input"] diff --git a/devices/fields/dma/gpdma/h5.yaml b/devices/fields/dma/gpdma/h5.yaml new file mode 100644 index 000000000..6dc80ea95 --- /dev/null +++ b/devices/fields/dma/gpdma/h5.yaml @@ -0,0 +1,415 @@ +# The GPDMA peripheral used on the H5 family, at least + +PRIVCFGR: + PRIV?: + Unprivileged: [0, Channel is unprivileged] + Privileged: [1, Channel is privileged] + +MISR: + MIS?: + _read: + NoTrigger: [0, No interrupt has occurred on channel] + Trigger: [1, An interrupt has occurred on channel] + +C?LBAR: + LBA: [0, 0xFFFF] + +C?FCR: + "*F": + _write: + Clear: [1, Clear flag] + +C?SR: + FIFOL: [0, 0xFF] + "*F": + _read: + NoTrigger: [0, Event not triggered] + Trigger: [1, Event triggered] + +C?CR: + PRIO: + LowPrioLowWeight: [0, "Low priority, low weight"] + LowPrioMidWeight: [1, "Low priority, mid weight"] + LowPrioHighWeight: [2, "Low priority, high weight"] + HighPrio: [3, High priority] + LAP: + Port0: [0, Port 0 (AHB) allocated] + Port1: [1, Port 1 (AHB) allocated] + LSM: + FullLinkedList: [0, Channel executed for full linked list] + Once: [1, Channel executed once for current linked list] + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + SUSP: + NotSuspended: [0, Channel operation not suspended] + Suspended: [1, Channel operation suspended] + RESET: + _write: + Reset: [1, Reset channel] + EN: + Disabled: [0, Channel disabled] + Enabled: [1, Channel enabled] + +C?TR1: + "?AP": + Port0: [0, Port 0 (AHB) allocated] + Port1: [1, Port 1 (AHB) allocated] + DHX: + NotExchanged: [0, No halfword-based exchange within word] + Exchanged: [1, The two consecutive (post PAM) half-words are exchanged in each destination word] + "?BX": + NotExchanged: [0, No byte-based exchanged within word] + Exchanged: [1, The two consecutive (post PAM) bytes are exchanged in each destination half-word] + "?BL_1": [0, 63] + "?INC": + FixedBurst: [0, Fixed burst] + Contiguous: [1, Contiguously incremented burst] + "?DW_LOG2": + _write: + Byte: [0, Byte] + HalfWord: [1, Half-word (2 bytes)] + Word: [2, Word (4 bytes)] + _read: + Byte: [0, Byte] + HalfWord: [1, Half-word (2 bytes)] + Word: [2, Word (4 bytes)] + Error: [3, User setting error] + PAM: [0, 3] + #PAM_1: + # RightAlignedZeroPadded: + # [0, "Source data is transferred as right aligned, padded with 0s up to the destination data width"] + # RightAlignedSignExtended: + # [1, "Source data is transferred as right aligned, sign extended up to the destination data width"] + # Fifo: + # [ + # 2, + # "Source data are FIFO queued and packed at the destination data width, in little endian order, before a destination transfer", + # ] + #PAM_2: + # RightAlignedLeftTruncated: + # [0, "Source data is transferred as right aligned, left-truncated down to the destination data width"] + # LeftAlignedRightTruncated: + # [1, "Source data is transferred as left-aligned, right-truncated down to the destination data width"] + # Fifo: [2, "Source data are FIFO queued and unpacked at the destination data width, in little endian order"] + +C[0-5]TR2: + TCEM: + BlockLevel: + [ + 0, + "At block level: the complete (and the half) transfer event is generated at the (respectively half of the) end of a block", + ] + LliLevel: + [ + 2, + "At LLI level: the complete transfer event is generated at the end of the LLI transfer. The half transfer event is generated at the half of the LLI data transfer", + ] + ChannelLevel: + [ + 3, + "At channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI", + ] + TRIGM: + BlockLevel: [0, "At block level: the first burst read of each block transfer is conditioned by one hit trigger"] + LinkLevel: [2, "At link level: a LLI link transfer is conditioned by one hit trigger"] + ProgrammedBurstLevel: [3, "At programmed burst level: programmed burst read is conditioned by one hit trigger. "] + +C[67]TR2: + TCEM: + BlockLevel: + [ + 0, + "At block level: the complete (and the half) transfer event is generated at the (respectively half of the) end of a block", + ] + RepeatedBlockLevel: + [ + 1, + "At repeated block level: the complete (and the half) transfer event is generated at the end (respectively half of the end) of the 2D/repeated block.", + ] + LliLevel: + [ + 2, + "At LLI level: the complete transfer event is generated at the end of the LLI transfer. The half transfer event is generated at the half of the LLI data transfer", + ] + ChannelLevel: + [ + 3, + "At channel level: the complete transfer event is generated at the end of the last LLI transfer. The half transfer event is generated at the half of the data transfer of the last LLI", + ] + TRIGM: + BlockLevel: [0, "At block level: the first burst read of each block transfer is conditioned by one hit trigger"] + RepeatedBlockLevel: + [ + 1, + "At repeated block level: the first burst read of a 2D/repeated block transfer is conditioned by one hit trigger", + ] + LinkLevel: [2, "At link level: a LLI link transfer is conditioned by one hit trigger"] + ProgrammedBurstLevel: [3, "At programmed burst level: programmed burst read is conditioned by one hit trigger. "] + +C?TR2: + TRIGPOL: + NoTrigger: [0, No trigger] + RisingEdge: [1, Trigger on rising edge] + FallingEdge: [2, Trigger on falling edge] + TRIGSEL: + EXTI0: [0, exti0 is trigger input] + EXTI1: [1, exti1 is trigger input] + EXTI2: [2, exti2 is trigger input] + EXTI3: [3, exti3 is trigger input] + EXTI4: [4, exti4 is trigger input] + EXTI5: [5, exti5 is trigger input] + EXTI6: [6, exti6 is trigger input] + EXTI7: [7, exti7 is trigger input] + TAMP_TRG1: [8, tamp_trg1 is trigger input] + TAMP_TRG2: [9, tamp_trg2 is trigger input] + LPTIM1_CH1: [11, lptim1_ch1 is trigger input] + LPTIM1_CH2: [12, lptim1_ch2 is trigger input] + LPTIM2_CH1: [13, lptim2_ch1 is trigger input] + LPTIM2_CH2: [14, lptim2_ch2 is trigger input] + RTC_ALRA_TRG: [15, rtc_alra_trg is trigger input] + RTC_ALRB_TRG: [16, rtc_alrb_trg is trigger input] + RTC_WUT_TRG: [17, rtc_wut_trg is trigger input] + GPDMA1_CH0_TC: [18, gpdma1_ch0_tc is trigger input] + GPDMA1_CH1_TC: [19, gpdma1_ch1_tc is trigger input] + GPDMA1_CH2_TC: [20, gpdma1_ch2_tc is trigger input] + GPDMA1_CH3_TC: [21, gpdma1_ch3_tc is trigger input] + GPDMA1_CH4_TC: [22, gpdma1_ch4_tc is trigger input] + GPDMA1_CH5_TC: [23, gpdma1_ch5_tc is trigger input] + GPDMA1_CH6_TC: [24, gpdma1_ch6_tc is trigger input] + GPDMA1_CH7_TC: [25, gpdma1_ch7_tc is trigger input] + GPDMA2_CH0_TC: [26, gpdma2_ch0_tc is trigger input] + GPDMA2_CH1_TC: [27, gpdma2_ch1_tc is trigger input] + GPDMA2_CH2_TC: [28, gpdma2_ch2_tc is trigger input] + GPDMA2_CH3_TC: [29, gpdma2_ch3_tc is trigger input] + GPDMA2_CH4_TC: [30, gpdma2_ch4_tc is trigger input] + GPDMA2_CH5_TC: [31, gpdma2_ch5_tc is trigger input] + GPDMA2_CH6_TC: [32, gpdma2_ch6_tc is trigger input] + GPDMA2_CH7_TC: [33, gpdma2_ch7_tc is trigger input] + TIM2_TRG0: [34, tim2_trgo is trigger input] + COMP1_OUT: [44, comp1_out is trigger input] + PFREQ: + GpdmaControlMode: + [ + 0, + The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in GPDMA control mode, + ] + PeripheralControlMode: + [ + 1, + The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol in peripheral control mode., + ] + BREQ: + Burst: + [ + 0, + The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a burst level, + ] + Block: + [ + 1, + The selected hardware request is driven by a peripheral with a hardware request/acknowledge protocol at a block level, + ] + DREQ: + Source: [0, Selected hardware request driven by a source peripheral] + Destination: [1, Selected hardware request driven by a destination peripheral] + SWREQ: + Hardware: [0, "No software request. The selected hardware request REQSEL[7:0] is taken into account"] + Software: [1, Software request for memory-to-memory transfer] + REQSEL: + ADC1_DMA: [0, adc1_dma selected] + DAC1_CH1_DMA: [2, dac1_ch1_dma selected] + DAC1_CH2_DMA: [3, dac1_ch2_dma selected] + TIM6_UPD_DMA: [4, tim6_upd_dma selected] + TIM7_UPD_DMA: [5, tim7_upd_dma selected] + SPI1_RX_DMA: [6, spi1_rx_dma selected] + SPI1_TX_DMA: [7, spi1_tx_dma selected] + SPI2_RX_DMA: [8, spi2_rx_dma selected] + SPI2_TX_DMA: [9, spi2_tx_dma selected] + SPI3_RX_DMA: [10, spi3_rx_dma selected] + SPI3_TX_DMA: [11, spi3_tx_dma selected] + I2C1_RX_DMA: [12, i2c1_rx_dma selected] + I2C1_TX_DMA: [13, i2c1_tx_dma selected] + I2C2_RX_DMA: [15, i2c2_rx_dma selected] + I2C2_TX_DMA: [16, i2c2_tx_dma selected] + I2C3_RX_DMA: [18, i2c3_rx_dma selected] + I2C3_TX_DMA: [19, i2c3_tx_dma selected] + USART1_RX_DMA: [21, usart1_rx_dma selected] + USART1_TX_DMA: [22, usart1_tx_dma selected] + USART2_RX_DMA: [23, usart2_rx_dma selected] + USART2_TX_DMA: [24, usart2_tx_dma selected] + USART3_RX_DMA: [25, usart3_rx_dma selected] + USART3_TX_DMA: [26, usart3_tx_dma selected] + UART4_RX_DMA: [27, uart4_rx_dma selected] + UART4_TX_DMA: [28, uart4_tx_dma selected] + UART5_RX_DMA: [29, uart5_rx_dma selected] + UART5_TX_DMA: [30, uart5_tx_dma selected] + USART6_RX_DMA: [31, usart6_rx_dma selected] + USART6_TX_DMA: [32, usart6_tx_dma selected] + UART7_RX_DMA: [33, uart7_rx_dma selected] + UART7_TX_DMA: [34, uart7_tx_dma selected] + UART8_RX_DMA: [35, uart8_rx_dma selected] + UART8_TX_DMA: [36, uart8_tx_dma selected] + UART9_RX_DMA: [37, uart9_rx_dma selected] + UART9_TX_DMA: [38, uart9_tx_dma selected] + UART10_RX_DMA: [39, uart10_rx_dma selected] + UART10_TX_DMA: [40, uart10_tx_dma selected] + UART11_RX_DMA: [41, uart11_rx_dma selected] + UART11_TX_DMA: [42, uart11_tx_dma selected] + UART12_RX_DMA: [43, uart12_rx_dma selected] + UART12_TX_DMA: [44, uart12_tx_dma selected] + LPUART1_RX_DMA: [45, lpuart1_rx_dma selected] + LPUART1_TX_DMA: [46, lpuart1_tx_dma selected] + SPI4_RX_DMA: [47, spi4_rx_dma selected] + SPI4_TX_DMA: [48, spi4_tx_dma selected] + SPI5_RX_DMA: [49, spi5_rx_dma selected] + SPI5_TX_DMA: [50, spi5_tx_dma selected] + SPI6_RX_DMA: [51, spi6_rx_dma selected] + SPI6_TX_DMA: [52, spi6_tx_dma selected] + SAI1_A_DMA: [53, sai1_a_dma selected] + SAI1_B_DMA: [54, sai1_b_dma selected] + SAI2_A_DMA: [55, sai2_a_dma selected] + SAI2_B_DMA: [56, sai2_b_dma selected] + OSPI1_DMA: [57, ospi1_dma selected] + TIM1_CC1_DMA: [58, tim1_cc1_dma selected] + TIM1_CC2_DMA: [59, tim1_cc2_dma selected] + TIM1_CC3_DMA: [60, tim1_cc3_dma selected] + TIM1_CC4_DMA: [61, tim1_cc4_dma selected] + TIM1_UPD_DMA: [62, tim1_upd_dma selected] + TIM1_TRG_DMA: [63, tim1_trg_dma selected] + TIM1_COM_DMA: [64, tim1_com_dma selected] + TIM8_CC1_DMA: [65, tim8_cc1_dma selected] + TIM8_CC2_DMA: [66, tim8_cc2_dma selected] + TIM8_CC3_DMA: [67, tim8_cc3_dma selected] + TIM8_CC4_DMA: [68, tim8_cc4_dma selected] + TIM8_UPD_DMA: [69, tim8_upd_dma selected] + TIM8_TIG_DMA: [70, tim8_tig_dma selected] + TIM8_COM_DMA: [71, tim8_com_dma selected] + TIM2_CC1_DMA: [72, tim2_cc1_dma selected] + TIM2_CC2_DMA: [73, tim2_cc2_dma selected] + TIM2_CC3_DMA: [74, tim2_cc3_dma selected] + TIM2_CC4_DMA: [75, tim2_cc4_dma selected] + TIM2_UPD_DMA: [76, tim2_upd_dma selected] + TIM3_CC1_DMA: [77, tim3_cc1_dma selected] + TIM3_CC2_DMA: [78, tim3_cc2_dma selected] + TIM3_CC3_DMA: [79, tim3_cc3_dma selected] + TIM3_CC4_DMA: [80, tim3_cc4_dma selected] + TIM3_UPD_DMA: [81, tim3_upd_dma selected] + TIM3_TRG_DMA: [82, tim3_trg_dma selected] + TIM4_CC1_DMA: [83, tim4_cc1_dma selected] + TIM4_CC2_DMA: [84, tim4_cc2_dma selected] + TIM4_CC3_DMA: [85, tim4_cc3_dma selected] + TIM4_CC4_DMA: [86, tim4_cc4_dma selected] + TIM4_UPD_DMA: [87, tim4_upd_dma selected] + TIM5_CC1_DMA: [88, tim5_cc1_dma selected] + TIM5_CC2_DMA: [89, tim5_cc2_dma selected] + TIM5_CC3_DMA: [90, tim5_cc3_dma selected] + TIM5_CC4_DMA: [91, tim5_cc4_dma selected] + TIM5_UPD_DMA: [92, tim5_upd_dma selected] + TIM5_TRG_DMA: [93, tim5_trg_dma selected] + TIM15_CC1_DMA: [94, tim15_cc1_dma selected] + TIM15_UPD_DMA: [95, tim15_upd_dma selected] + TIM15_TRG_DMA: [96, tim15_trg_dma selected] + TIM15_COM_DMA: [97, tim15_com_dma selected] + TIM16_CC1_DMA: [98, tim16_cc1_dma selected] + TIM16_UPD_DMA: [99, tim16_upd_dma selected] + TIM17_CC1_DMA: [100, tim17_cc1_dma selected] + TIM17_UPD_DMA: [101, tim17_upd_dma selected] + LPTIM1_IC1_DMA: [102, lptim1_ic1_dma selected] + LPTIM1_IC2_DMA: [103, lptim1_ic2_dma selected] + LPTIM1_UE_DMA: [104, lptim1_ue_dma selected] + LPTIM2_IC1_DMA: [105, lptim2_ic1_dma selected] + LPTIM2_IC2_DMA: [106, lptim2_ic2_dma selected] + LPTIM2_UE_DMA: [107, lptim2_ue_dma selected] + DCMI_PSSI_DMA: [108, dcmi_dma or pssi_dma(1) selected] + AES_OUT_DMA: [109, aes_out_dma selected] + AES_IN_DMA: [110, aes_in_dma selected] + HASH_IN_DMA: [111, hash_in_dma selected] + UCPD1_RX_DMA: [112, ucpd1_rx_dma selected] + UCPD1_TX_DMA: [113, ucpd1_tx_dma selected] + CORDIC_READ_DMA: [114, cordic_read_dma selected] + CORDIC_WRITE_DMA: [115, cordic_write_dma selected] + FMAC_READ_DMA: [116, fmac_read_dma selected] + FMAC_WRITE_DMA: [117, fmac_write_dma selected] + SAES_OUT_DMA: [118, saes_out_dma selected] + SAES_IN_DMA: [119, saes_in_dma selected] + I3C1_RX_DMA: [120, i3c1_rx_dma selected] + I3C1_TX_DMA: [121, i3c1_tx_dma selected] + I3C1_TC_DMA: [122, i3c1_tc_dma selected] + I3C1_RS_DMA: [123, i3c1_rs_dma selected] + I2C4_RX_DMA: [124, i2c4_rx_dma selected] + I2C4_TX_DMA: [125, i2c4_tx_dma selected] + LPTIM3_IC1_DMA: [127, lptim3_ic1_dma selected] + LPTIM3_IC2_DMA: [128, lptim3_ic2_dma selected] + LPTIM3_UE_DMA: [129, lptim3_ue_dma selected] + LPTIM5_IC1_DMA: [130, lptim5_ic1_dma selected] + LPTIM5_IC2_DMA: [131, lptim5_ic2_dma selected] + LPTIM5_UE_DMA: [132, lptim5_ue_dma selected] + LPTIM6_IC1_DMA: [133, lptim6_ic1_dma selected] + LPTIM6_IC2_DMA: [134, lptim6_ic2_dma selected] + LPTIM6_UE_DMA: [135, lptim6_ue_dma selected] + I3C2_RX: [136, i3c2_rx selected] + I3C2_TX: [137, i3c2_tx selected] + I3C2_TC: [138, i3c2_tc selected] + I3C2_RS: [139, i3c2_rs selected] + +C?BR1: + BNDT: [0, 0xFFFF] + +C[67]BR1: + BRDDEC: + Increment: [0, Block repeat destination address incremented] + Decrement: [1, Block repeat destination address decremented] + BRSDEC: + Increment: [0, Block repeat source address incremented] + Decrement: [1, Block repeat source address decremented] + DDEC: + Increment: [0, Destination address incremented] + Decrement: [1, Destination address decremented] + SDEC: + Increment: [0, Source address incremented] + Decrement: [1, Source address decremented] + BRC: [0, 2047] + +C?SAR: + SA: [0, 0xFFFFFFFF] + +C?DAR: + DA: [0, 0xFFFFFFFF] + +C[67]TR3: + DAO: [0, 0xFFF] + SAO: [0, 0xFFF] + +C[67]BR2: + BRDAO: [0, 0xFFFF] + BRSAO: [0, 0xFFFF] + +C?LLR: + UT1: + NoUpdate: [0, No CxTR1 update] + Update: [1, CxTR1 updated from memory during link transfer] + UT2: + NoUpdate: [0, No CxTR2 update] + Update: [1, CxTR2 updated from memory during link transfer] + UB1: + NoUpdate: [0, No CxBR1 update] + Update: [1, CxBR1 updated from memory during link transfer] + USA: + NoUpdate: [0, No CxSAR update] + Update: [1, CxSAR updated from memory during link transfer] + UDA: + NoUpdate: [0, No CxDAR update] + Update: [1, CxDAR updated from memory during link transfer] + ULL: + NoUpdate: [0, No CxLLR update] + Update: [1, CxLLR updated from memory during link transfer] + LA: [0, 0x3FFF] + +C[67]LLR: + UT3: + NoUpdate: [0, No CxTR3 update] + Update: [1, CxTR3 updated from memory during link transfer] + UB2: + NoUpdate: [0, No CxBR2 update] + Update: [1, CxBR2 updated from memory during link transfer] diff --git a/devices/fields/dma/v1.yaml b/devices/fields/dma/v1.yaml new file mode 100644 index 000000000..904a30d13 --- /dev/null +++ b/devices/fields/dma/v1.yaml @@ -0,0 +1,5 @@ +_include: + - common.yaml + +CNDTR*: + NDT: [0, 0xFFFF] diff --git a/devices/fields/eth/eth_dma_common.yaml b/devices/fields/eth/eth_dma_common.yaml new file mode 100644 index 000000000..bb95fbfb1 --- /dev/null +++ b/devices/fields/eth/eth_dma_common.yaml @@ -0,0 +1,276 @@ +Ethernet_DMA: + DMABMR: + AAB: + Unaligned: [0, Bursts are not aligned] + Aligned: [1, Align bursts to start address LS bits. First burst alignment depends on FB bit] + FPM: + x1: [0, PBL values used as-is] + x4: [1, PBL values multiplied by 4] + USP: + Combined: [0, PBL value used for both Rx and Tx DMA] + Separate: [1, "RxDMA uses RDP value, TxDMA uses PBL value"] + RDP: + RDP1: [1, 1 beat per RxDMA transaction] + RDP2: [2, 2 beats per RxDMA transaction] + RDP4: [4, 4 beats per RxDMA transaction] + RDP8: [8, 8 beats per RxDMA transaction] + RDP16: [16, 16 beats per RxDMA transaction] + RDP32: [32, 32 beats per RxDMA transaction] + FB: + Variable: [0, AHB uses SINGLE and INCR burst transfers] + Fixed: [1, AHB uses only fixed burst transfers] + PM: + OneToOne: [0, "RxDMA priority over TxDMA is 1:1"] + TwoToOne: [1, "RxDMA priority over TxDMA is 2:1"] + ThreeToOne: [2, "RxDMA priority over TxDMA is 3:1"] + FourToOne: [3, "RxDMA priority over TxDMA is 4:1"] + PBL: + PBL1: [1, Maximum of 1 beat per DMA transaction] + PBL2: [2, Maximum of 2 beats per DMA transaction] + PBL4: [4, Maximum of 4 beats per DMA transaction] + PBL8: [8, Maximum of 8 beats per DMA transaction] + PBL16: [16, Maximum of 16 beats per DMA transaction] + PBL32: [32, Maximum of 32 beats per DMA transaction] + DSL: [0, 0x1F] + DA: + RoundRobin: [0, "Round-robin with Rx:Tx priority given by PM"] + RxPriority: [1, Rx has priority over Tx] + SR: + Reset: [1, Reset all MAC subsystem internal registers and logic. Cleared automatically] + _modify: + "?~MB": + description: Mixed burst + AAB: + description: Address-aligned beats + FPM: + description: 4xPBL mode + USP: + description: Use separate PBL + RDP: + description: Rx DMA PBL + FB: + description: Fixed burst + PM: + description: Rx-Tx priority ratio + PBL: + description: Programmable burst length + "?~EDFE": + description: Enhanced descriptor format enable + DSL: + description: Descriptor skip length + DA: + description: DMA arbitration + SR: + description: Software reset + + DMATPDR: + TPD: + Poll: [0, Poll the transmit descriptor list] + _modify: + TPD: + description: Transmit poll demand + + DMARPDR: + RPD: + Poll: [0, Poll the receive descriptor list] + _modify: + RPD: + description: Receive poll demand + + DMARDLAR: + _modify: + SRL: + description: Start of receive list + + DMATDLAR: + _modify: + STL: + description: Start of transmit list + + DMASR: + TPS: + Stopped: [0, "Stopped, Reset or Stop Transmit command issued"] + RunningFetching: [1, "Running, fetching transmit transfer descriptor"] + RunningWaiting: [2, "Running, waiting for status"] + RunningReading: [3, "Running, reading data from host memory buffer"] + Suspended: [6, "Suspended, transmit descriptor unavailable or transmit buffer underflow"] + Running: [7, "Running, closing transmit descriptor"] + RPS: + Stopped: [0, "Stopped, reset or Stop Receive command issued"] + RunningFetching: [1, "Running, fetching receive transfer descriptor"] + RunningWaiting: [3, "Running, waiting for receive packet"] + Suspended: [4, "Suspended, receive descriptor unavailable"] + RunningWriting: [7, "Running, writing data to host memory buffer"] + _modify: + TSTS: + description: Time stamp trigger status + PMTS: + description: PMT status + MMCS: + description: MMC status + EBS: + description: Error bits status + TPS: + description: Transmit process state + RPS: + description: Receive process state + NIS: + description: Normal interrupt summary + AIS: + description: Abnormal interrupt summary + ERS: + description: Early receive status + FBES: + description: Fatal bus error status + ETS: + description: Early transmit status + "?~RWTS": + description: Receive watchdog timeout status + RPSS: + description: Receive process stopped status + RBUS: + description: Receive buffer unavailable status + RS: + description: Receive status + TUS: + description: Transmit underflow status + ROS: + description: Receive overflow status + TJTS: + description: Transmit jabber timeout status + TBUS: + description: Transmit buffer unavailable status + TPSS: + description: Transmit process stopped status + TS: + description: Transmit status + + DMAOMR: + DTCEFD: + Enabled: [0, Drop frames with errors only in the receive checksum offload engine] + Disabled: [1, Do not drop frames that only have errors in the receive checksum offload engine] + RSF: + CutThrough: [0, "Rx FIFO operates in cut-through mode, subject to RTC bits"] + StoreForward: [1, Frames are read from Rx FIFO after complete frame has been written] + DFRF: + TSF: + CutThrough: [0, Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold] + StoreForward: [1, Transmission starts when a full frame is in the Tx FIFO] + FTF: + Flush: [1, Transmit FIFO controller logic is reset to its default values. Cleared automatically] + TTC: + TTC64: [0, 64 bytes] + TTC128: [1, 128 bytes] + TTC192: [2, 192 bytes] + TTC256: [3, 256 bytes] + TTC40: [4, 40 bytes] + TTC32: [5, 32 bytes] + TTC24: [6, 24 bytes] + TTC16: [7, 16 bytes] + ST: + Stopped: [0, Transmission is placed in the Stopped state] + Started: [1, Transmission is placed in Running state] + FEF: + Drop: [0, Rx FIFO drops frames with error status] + Forward: [1, All frames except runt error frames are forwarded to the DMA] + FUGF: + Drop: [0, Rx FIFO drops all frames of less than 64 bytes] + Forward: [1, Rx FIFO forwards undersized frames] + RTC: + RTC64: [0, 64 bytes] + RTC32: [1, 32 bytes] + RTC96: [2, 96 bytes] + RTC128: [3, 128 bytes] + OSF: + SR: + Stopped: [0, Reception is stopped after transfer of the current frame] + Started: [1, Reception is placed in the Running state] + _modify: + DTCEFD: + description: Dropping of TCP/IP checksum error frames disable + RSF: + description: Receive store and forward + DFRF: + description: Disable flushing of received frames + TSF: + description: Transmit store and forward + FTF: + description: Flush transmit FIFO + TTC: + description: Transmit threshold control + ST: + description: Start/stop transmission + FEF: + description: Forward error frames + FUGF: + description: Forward undersized good frames + RTC: + description: Receive threshold control + OSF: + description: Operate on second frame + SR: + description: Start/stop receive + + DMAIER: + _modify: + NISE: + description: Normal interrupt summary enable + AISE: + description: Abnormal interrupt summary enable + ERIE: + description: Early receive interrupt enable + FBEIE: + description: Fatal bus error interrupt enable + ETIE: + description: Early transmit interrupt enable + RWTIE: + description: Receive watchdog timeout interrupt enable + RPSIE: + description: Receive process stopped interrupt enable + RBUIE: + description: Receive buffer unavailable interrupt enable + RIE: + description: Receive interrupt enable + TUIE: + description: Transmit underflow interrupt enable + ROIE: + description: Receive overflow interrupt enable + TJTIE: + description: Transmit jabber timeout interrupt enable + TBUIE: + description: Transmit buffer unavailable interrupt enable + TPSIE: + description: Transmit process stopped interrupt enable + TIE: + description: Transmit interrupt enable + + DMAMFBOCR: + _modify: + OFOC: + description: Overflow bit for FIFO overflow counter + MFA: + description: Missed frames by the application + OMFC: + description: Overflow bit for missed frame counter + MFC: + description: Missed frames by the controller + + DMACHTDR: + _modify: + HTDAP: + description: Host transmit descriptor address pointer + + DMACHRDR: + _modify: + HRDAP: + description: Host receive descriptor address pointer + + DMACHTBAR: + _modify: + HTBAP: + description: Host transmit buffer address pointer + + DMACHRBAR: + _modify: + HRBAP: + description: Host receive buffer address pointer diff --git a/devices/fields/eth/eth_dma_mb_edfe_dmarswtr.yaml b/devices/fields/eth/eth_dma_mb_edfe_dmarswtr.yaml new file mode 100644 index 000000000..b644b5ffc --- /dev/null +++ b/devices/fields/eth/eth_dma_mb_edfe_dmarswtr.yaml @@ -0,0 +1,14 @@ +Ethernet_DMA: + DMABMR: + MB: + Normal: [0, Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below] + Mixed: [1, "If FB is low, start all bursts greater than 16 with INCR (undefined burst)"] + EDFE: + Disabled: [0, Normal descriptor format] + Enabled: [1, "Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload"] + + DMARSWTR: + RSWTC: [0, 0xFF] + _modify: + RSWTC: + description: Receive status watchdog timer count diff --git a/devices/fields/eth/eth_mac_common.yaml b/devices/fields/eth/eth_mac_common.yaml new file mode 100644 index 000000000..20d7092f0 --- /dev/null +++ b/devices/fields/eth/eth_mac_common.yaml @@ -0,0 +1,316 @@ +Ethernet_MAC: + MACCR: + WD: + Enabled: [0, "Watchdog enabled, receive frames limited to 2048 bytes"] + Disabled: [1, "Watchdog disabled, receive frames may be up to to 16384 bytes"] + JD: + Enabled: [0, "Jabber enabled, transmit frames up to 2048 bytes"] + Disabled: [1, "Jabber disabled, transmit frames up to 16384 bytes"] + IFG: + IFG96: [0, 96 bit times] + IFG88: [1, 88 bit times] + IFG80: [2, 80 bit times] + IFG72: [3, 72 bit times] + IFG64: [4, 64 bit times] + IFG56: [5, 56 bit times] + IFG48: [6, 48 bit times] + IFG40: [7, 40 bit times] + CSD: + Enabled: [0, Errors generated due to loss of carrier] + Disabled: [1, No error generated due to loss of carrier] + FES: + FES10: [0, 10 Mbit/s] + FES100: [1, 100 Mbit/s] + ROD: + Enabled: [0, MAC receives all packets from PHY while transmitting] + Disabled: [1, MAC disables reception of frames in half-duplex mode] + LM: + Normal: [0, Normal mode] + Loopback: [1, MAC operates in loopback mode at the MII] + DM: + HalfDuplex: [0, MAC operates in half-duplex mode] + FullDuplex: [1, MAC operates in full-duplex mode] + IPCO: + Disabled: [0, IPv4 checksum offload disabled] + Offload: [1, IPv4 checksums are checked in received frames] + RD: + Enabled: [0, MAC attempts retries based on the settings of BL] + Disabled: [1, MAC attempts only 1 transmission] + APCS: + Disabled: [0, MAC passes all incoming frames unmodified] + Strip: [1, MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes] + BL: + BL10: [0, "For retransmission n, wait up to 2^min(n, 10) time slots"] + BL8: [1, "For retransmission n, wait up to 2^min(n, 8) time slots"] + BL4: [2, "For retransmission n, wait up to 2^min(n, 4) time slots"] + BL1: [3, "For retransmission n, wait up to 2^min(n, 1) time slots"] + DC: + Disabled: [0, MAC defers until CRS signal goes inactive] + Enabled: [1, Deferral check function enabled] + TE: + Disabled: [0, MAC transmit state machine is disabled after completion of the transmission of the current frame] + Enabled: [1, MAC transmit state machine is enabled] + RE: + Disabled: [0, MAC receive state machine is disabled after the completion of the reception of the current frame] + Enabled: [1, MAC receive state machine is enabled] + _modify: + "?~CSTF": + description: CRC stripping for type frames + WD: + description: Watchdog disable + JD: + description: Jabber disable + IFG: + description: Interframe gap + CSD: + description: Carrier sense disable + FES: + description: Fast Ethernet speed + ROD: + description: Receive own disable + LM: + description: Loopback mode + DM: + description: Duplex mode + IPCO: + description: IPv4 checksum offload + RD: + description: Retry disable + APCS: + description: Automatic pad/CRC stripping + BL: + description: Back-off limit + DC: + description: Deferral check + TE: + description: Transmitter enable + RE: + description: Receiver enable + + MACFFR: + RA: + Disabled: [0, MAC receiver passes on to the application only those frames that have passed the SA/DA address file] + Enabled: [1, MAC receiver passes oll received frames on to the application] + HPF: + HashOnly: [0, "If HM or HU is set, only frames that match the Hash filter are passed"] + HashOrPerfect: + [1, "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed"] + SAF: + Disabled: [0, Source address ignored] + Enabled: [1, MAC drops frames that fail the source address filter] + SAIF: + Normal: [0, Source address filter operates normally] + Invert: [1, Source address filter operation inverted] + PCF: + PreventAll: [0, MAC prevents all control frames from reaching the application] + ForwardAllExceptPause: [1, MAC forwards all control frames to application except Pause] + ForwardAll: [2, MAC forwards all control frames to application even if they fail the address filter] + ForwardAllFiltered: [3, MAC forwards control frames that pass the address filter] + BFD: + Enabled: [0, Address filters pass all received broadcast frames] + Disabled: [1, Address filters filter all incoming broadcast frames] + PAM: + Disabled: [0, Filtering of multicast frames depends on HM] + Enabled: [1, All received frames with a multicast destination address are passed] + DAIF: + Normal: [0, Normal filtering of frames] + Invert: [1, Address check block operates in inverse filtering mode for the DA address comparison] + HM: + Perfect: [0, MAC performs a perfect destination address filtering for multicast frames] + Hash: [1, MAC performs destination address filtering of received multicast frames according to the hash table] + HU: + Perfect: [0, MAC performs a perfect destination address filtering for unicast frames] + Hash: [1, MAC performs destination address filtering of received unicast frames according to the hash table] + PM: + Disabled: [0, Normal address filtering] + Enabled: [1, Address filters pass all incoming frames regardless of their destination or source address] + _modify: + RA: + description: Receive all + HPF: + description: Hash or perfect filter + SAF: + description: Source address filter + SAIF: + description: Source address inverse filtering + PCF: + description: Pass control frames + BFD: + description: Broadcast frames disable + "RAM,PAM": + name: PAM + description: Pass all multicast + DAIF: + description: Destination address unique filtering + HM: + description: Hash multicast + HU: + description: Hash unicast + PM: + description: Promiscuous mode + + MACHTHR: + HTH: [0, 0xFFFFFFFF] + _modify: + HTH: + description: Upper 32 bits of hash table + + MACHTLR: + HTL: [0, 0xFFFFFFFF] + _modify: + HTL: + description: Lower 32 bits of hash table + + MACMIIAR: + PA: [0, 0x1F] + MR: [0, 0x1F] + CR: + CR_60_100: [0, 60-100MHz HCLK/42] + CR_100_150: [1, 100-150 MHz HCLK/62] + CR_20_35: [2, 20-35MHz HCLK/16] + CR_35_60: [3, 35-60MHz HCLK/16] + CR_150_168: [4, 150-168MHz HCLK/102] + MW: + Read: [0, Read operation] + Write: [1, Write operation] + MB: + Busy: [1, This bit is set to 1 by the application to indicate that a read or write access is in progress] + _modify: + PA: + description: PHY address - select which of possible 32 PHYs is being accessed + MR: + description: MII register - select the desired MII register in the PHY device + CR: + description: Clock range + MW: + description: MII write + MB: + description: MII busy + + MACMIIDR: + MD: [0, 0xFFFF] + _modify: + MD: + description: MII data read from/written to the PHY + + MACFCR: + PT: [0, 0xFFFF] + ZQPD: + Enabled: [0, Normal operation with automatic zero-quanta pause control frame generation] + Disabled: [1, Automatic generation of zero-quanta pause control frames is disabled] + PLT: + PLT4: [0, Pause time minus 4 slot times] + PLT28: [1, Pause time minus 28 slot times] + PLT144: [2, Pause time minus 144 slot times] + PLT256: [3, Pause time minus 256 slot times] + UPFD: + Disabled: [0, MAC detects only a Pause frame with the multicast address specified in the 802.3x standard] + Enabled: [1, MAC additionally detects Pause frames with the station's unicast address] + RFCE: + Disabled: [0, Pause frames are not decoded] + Enabled: [1, MAC decodes received Pause frames and disables its transmitted for a specified time] + TFCE: + Disabled: [0, "In full duplex, flow control is disabled. In half duplex, back pressure is disabled"] + Enabled: [1, "In full duplex, flow control is enabled. In half duplex, back pressure is enabled"] + FCB: + PauseOrBackPressure: [1, "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure"] + DisableBackPressure: [0, "In half duplex only, deasserts back pressure"] + _modify: + PT: + description: Pause time + ZQPD: + description: Zero-quanta pause disable + PLT: + description: Pause low threshold + UPFD: + description: Unicast pause frame detect + RFCE: + description: Receive flow control enable + TFCE: + description: Transmit flow control enable + FCB: + description: Flow control busy/back pressure activate + + MACVLANTR: + VLANTC: + VLANTC16: [0, Full 16 bit VLAN identifiers are used for comparison and filtering] + VLANTC12: [1, 12 bit VLAN identifies are used for comparison and filtering] + VLANTI: [0, 0xFFFF] + _modify: + VLANTC: + description: 12-bit VLAN tag comparison + VLANTI: + description: VLAN tag identifier (for receive frames) + + MACPMTCSR: + WFFRPR: + Reset: [1, Reset wakeup frame filter register point to 0b000. Automatically cleared] + GU: + Disabled: [0, Normal operation] + Enabled: [1, Any unicast packet filtered by the MAC address recognition may be a wakeup frame] + WFE: + Disabled: [0, No power management event generated due to wakeup frame reception] + Enabled: [1, Enable generation of a power management event due to wakeup frame reception] + MPE: + Disabled: [0, No power management event generated due to Magic Packet reception] + Enabled: [1, Enable generation of a power management event due to Magic Packet reception] + PD: + Enabled: + [1, All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received] + _modify: + WFFRPR: + description: Wakeup frame filter register pointer reset + GU: + description: Global unicast + WFR: + description: Wakeup frame received + MPR: + description: Magic packet received + WFE: + description: Wakeup frame enable + MPE: + description: Magic packet enable + PD: + description: Power down + + MACSR: + _modify: + TSTS: + description: Time stamp trigger status + MMCTS: + description: MMC transmit status + MMCRS: + description: MMC receive status + MMCS: + description: MMC status + PMTS: + description: PMT status + + MACIMR: + TSTIM: + Unmasked: [0, Time stamp interrupt generation enabled] + Masked: [1, Time stamp interrupt generation disabled] + PMTIM: + Unmasked: [0, PMT Status interrupt generation enabled] + Masked: [1, PMT Status interrupt generation disabled] + _modify: + TSTIM: + description: Time stamp trigger interrupt mask + PMTIM: + description: PMT interrupt mask + + MACA0HR: + MACA0H: [0, 0xFFFF] + + MACA?LR: + MACA?L: [0, 0xFFFFFFFF] + + "MACA[123]HR": + AE: + Disabled: [0, Address filters ignore this address] + Enabled: [1, Address filters use this address] + SA: + Destination: [0, This address is used for comparison with DA fields of the received frame] + Source: [1, This address is used for comparison with SA fields of received frames] + MBC: [0, 0x3F] + MACA?H: [0, 0xFFFF] diff --git a/devices/fields/eth/eth_mac_cstf.yaml b/devices/fields/eth/eth_mac_cstf.yaml new file mode 100644 index 000000000..fc49bb72f --- /dev/null +++ b/devices/fields/eth/eth_mac_cstf.yaml @@ -0,0 +1,5 @@ +Ethernet_MAC: + MACCR: + CSTF: + Disabled: [0, CRC not stripped] + Enabled: [1, CRC stripped] diff --git a/devices/fields/eth/eth_mmc_common.yaml b/devices/fields/eth/eth_mmc_common.yaml new file mode 100644 index 000000000..4b40f9fac --- /dev/null +++ b/devices/fields/eth/eth_mmc_common.yaml @@ -0,0 +1,85 @@ +Ethernet_MMC: + MMCCR: + MCF: + Unfrozen: [0, All MMC counters update normally] + Frozen: [1, All MMC counters frozen to their current value] + ROR: + Disabled: [0, MMC counters do not reset on read] + Enabled: [1, MMC counters reset to zero after read] + CSR: + Disabled: [0, Counters roll over to zero after reaching the maximum value] + Enabled: [1, Counters do not roll over to zero after reaching the maximum value] + CR: + Reset: [1, Reset all counters. Cleared automatically] + _modify: + "?~MCFHP": + description: MMC counter Full-Half preset + "?~MCP": + description: MMC counter preset + MCF: + description: MMC counter freeze + ROR: + description: Reset on read + CSR: + description: Counter stop rollover + CR: + description: Counter reset + + MMCRIR: + _modify: + RGUFS: + description: Received good Unicast frames status + RFAES: + description: Received frames alignment error status + RFCES: + description: Received frames CRC error status + + MMCTIR: + _modify: + TGFS: + description: Transmitted good frames status + TGFMSCS: + description: Transmitted good frames more than single collision status + TGFSCS: + description: Transmitted good frames single collision status + + MMCRIMR: + RGUFM: + Unmasked: [0, Received-good-unicast counter half-full interrupt enabled] + Masked: [1, Received-good-unicast counter half-full interrupt disabled] + RFAEM: + Unmasked: [0, Received-alignment-error counter half-full interrupt enabled] + Masked: [1, Received-alignment-error counter half-full interrupt disabled] + RFCEM: + Unmasked: [0, Received-crc-error counter half-full interrupt enabled] + Masked: [1, Received-crc-error counter half-full interrupt disabled] + _modify: + RGUFM: + description: Received good Unicast frames mask + RFAEM: + description: Received frames alignment error mask + RFCEM: + description: Received frame CRC error mask + + MMCTIMR: + TGFM: + Unmasked: [0, Transmitted-good counter half-full interrupt enabled] + Masked: [1, Transmitted-good counter half-full interrupt disabled] + TGFMSCM: + Unmasked: [0, Transmitted-good-multiple-collision half-full interrupt enabled] + Masked: [1, Transmitted-good-multiple-collision half-full interrupt disabled] + TGFSCM: + Unmasked: [0, Transmitted-good-single-collision half-full interrupt enabled] + Masked: [1, Transmitted-good-single-collision half-full interrupt disabled] + _modify: + TGFM: + description: Transmitted good frames mask + TGFMSCM: + description: Transmitted good frames more than single collision mask + TGFSCM: + description: Transmitted good frames single collision mask + + MMCTGFSCCR: + _modify: + TGFSCC: + description: Transmitted good frames single collision counter diff --git a/devices/fields/eth/eth_mmc_mcfhp_mcp.yaml b/devices/fields/eth/eth_mmc_mcfhp_mcp.yaml new file mode 100644 index 000000000..6177d2bca --- /dev/null +++ b/devices/fields/eth/eth_mmc_mcfhp_mcp.yaml @@ -0,0 +1,7 @@ +Ethernet_MMC: + MMCCR: + MCFHP: + AlmostHalf: [0, "When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0"] + AlmostFull: [1, "When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0"] + MCP: + Preset: [1, MMC counters will be preset to almost full or almost half. Cleared automatically] diff --git a/devices/fields/eth/eth_ptp_ppsfreq.yaml b/devices/fields/eth/eth_ptp_ppsfreq.yaml new file mode 100644 index 000000000..e8a1d0db3 --- /dev/null +++ b/devices/fields/eth/eth_ptp_ppsfreq.yaml @@ -0,0 +1,19 @@ +Ethernet_PTP: + PTPPPSCR: + PPSFREQ: + Hz_1: [0, 1 Hz with a pulse width of 125 ms for binary rollover and of 100 ms for digital rollover] + Hz_2: [1, 2 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_4: [2, 4 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_8: [3, 8 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_16: [4, 16 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_32: [5, 32 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_64: [6, 64 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_128: [7, 128 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_256: [8, 256 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_512: [9, 512 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_1024: [10, 1024 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_2048: [11, 2048 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_4096: [12, 4096 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_8192: [13, 8192 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_16384: [14, 16384 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] + Hz_32768: [15, 32768 Hz with 50% duty cycle for binary rollover (digital rollover not recommended)] diff --git a/devices/fields/exti/abcdefg.yaml b/devices/fields/exti/abcdefg.yaml new file mode 100644 index 000000000..f8edb5b6c --- /dev/null +++ b/devices/fields/exti/abcdefg.yaml @@ -0,0 +1,9 @@ +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] diff --git a/devices/fields/exti/common.yaml b/devices/fields/exti/common.yaml new file mode 100644 index 000000000..2fd7efa1f --- /dev/null +++ b/devices/fields/exti/common.yaml @@ -0,0 +1,32 @@ +IMR,IMR?,CPUIMR?,C?IMR?,D3PMR?: + "MR*,IM*": + _name: InterruptMask + Masked: [0, Interrupt request line is masked] + Unmasked: [1, Interrupt request line is unmasked] +EMR,EMR?,CPUEMR?,C?EMR?: + "MR*,EM*": + _name: EventMask + Masked: [0, Event request line is masked] + Unmasked: [1, Event request line is unmasked] +RTSR,RTSR?: + "TR*,RT*": + _name: RisingTrigger + Disabled: [0, Rising edge trigger is disabled] + Enabled: [1, Rising edge trigger is enabled] +FTSR,FTSR?: + "TR*,FT*": + _name: FallingTrigger + Disabled: [0, Falling edge trigger is disabled] + Enabled: [1, Falling edge trigger is enabled] +SWIER,SWIER?: + "SWIER*,SWI*": + _write: + _name: SoftwareInterrupt + Pend: [1, Generates an interrupt request] +PR,PR?,?PR?,CPUPR?,C?PR?: + "PR*,PIF*,?PIF*": + _W1C: + Clear: [1, Clears pending bit] + _read: + NotPending: [0, No trigger request occurred] + Pending: [1, Selected trigger request occurred] diff --git a/devices/fields/exti/derive.yaml b/devices/fields/exti/derive.yaml new file mode 100644 index 000000000..83bc01964 --- /dev/null +++ b/devices/fields/exti/derive.yaml @@ -0,0 +1,6 @@ +EXTICR1: + _derive: + EXTI[1-3]: EXTI0 +EXTICR[2-4]: + _derive: + "EXTI?,EXTI1?": EXTICR1.EXTI0 diff --git a/devices/fields/exti/exti_g0.yaml b/devices/fields/exti/exti_g0.yaml new file mode 100644 index 000000000..d9248eeb9 --- /dev/null +++ b/devices/fields/exti/exti_g0.yaml @@ -0,0 +1,11 @@ +_include: + - common.yaml + - derive.yaml + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] diff --git a/devices/fields/exti/exti_h7.yaml b/devices/fields/exti/exti_h7.yaml new file mode 100644 index 000000000..89751f35b --- /dev/null +++ b/devices/fields/exti/exti_h7.yaml @@ -0,0 +1,8 @@ +_include: + - common.yaml +D3PCR??: + PCS*: + DMA_CH6: [0, DMA ch6 event selected as D3 domain pendclear source] + DMA_CH7: [1, DMA ch7 event selected as D3 domain pendclear source] + LPTIM4: [2, LPTIM4 out selected as D3 domain pendclear source] + LPTIM5: [3, LPTIM5 out selected as D3 domain pendclear source] diff --git a/devices/fields/exti/exti_priv.yaml b/devices/fields/exti/exti_priv.yaml new file mode 100644 index 000000000..381373c6c --- /dev/null +++ b/devices/fields/exti/exti_priv.yaml @@ -0,0 +1,5 @@ +PRIVCFGR?: + PRIV*: + _name: EventPrivilege + Unprivileged: [0, Event privilege disabled] + Privileged: [1, Event privilege enabled] diff --git a/devices/fields/exti/exti_u5.yaml b/devices/fields/exti/exti_u5.yaml new file mode 100644 index 000000000..3bc83cd31 --- /dev/null +++ b/devices/fields/exti/exti_u5.yaml @@ -0,0 +1,16 @@ +_include: + - derive.yaml + - common.yaml + - exti_priv.yaml +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + PI: [8, Select PIx as the source input for the EXTIx external interrupt] + PJ: [9, Select PJx as the source input for the EXTIx external interrupt] diff --git a/devices/fields/flash/acr/common_f2_f4.yaml b/devices/fields/flash/acr/common_f2_f4.yaml new file mode 100644 index 000000000..5560ecb9f --- /dev/null +++ b/devices/fields/flash/acr/common_f2_f4.yaml @@ -0,0 +1,16 @@ +ACR: + DCRST: + NoReset: [0, Data cache is not reset] + Reset: [1, Data cache is reset] + ICRST: + NoReset: [0, Instruction cache is not reset] + Reset: [1, Instruction cache is reset] + DCEN: + Disabled: [0, Data cache is disabled] + Enabled: [1, Data cache is enabled] + ICEN: + Disabled: [0, Instruction cache is disabled] + Enabled: [1, Instruction cache is enabled] + PRFTEN: + Disabled: [0, Prefetch is disabled] + Enabled: [1, Prefetch is enabled] diff --git a/devices/fields/flash/acr/common_f7.yaml b/devices/fields/flash/acr/common_f7.yaml new file mode 100644 index 000000000..fbdff756a --- /dev/null +++ b/devices/fields/flash/acr/common_f7.yaml @@ -0,0 +1,11 @@ + +ACR: + ARTRST: + NoReset: [0, Accelerator is not reset] + Reset: [1, Accelerator is reset] + ARTEN: + Disabled: [0, ART Accelerator is disabled] + Enabled: [1, ART Accelerator is enabled] + PRFTEN: + Disabled: [0, Prefetch is disabled] + Enabled: [1, Prefetch is enabled] diff --git a/devices/fields/flash/acr/hlfcya.yaml b/devices/fields/flash/acr/hlfcya.yaml new file mode 100644 index 000000000..2dfcef2c7 --- /dev/null +++ b/devices/fields/flash/acr/hlfcya.yaml @@ -0,0 +1,4 @@ +ACR: + HLFCYA: + Disabled: [0, Half cycle is disabled] + Enabled: [1, Half cycle is enabled] diff --git a/devices/fields/flash/acr/latency_16_states.yaml b/devices/fields/flash/acr/latency_16_states.yaml new file mode 100644 index 000000000..d34b17589 --- /dev/null +++ b/devices/fields/flash/acr/latency_16_states.yaml @@ -0,0 +1,18 @@ +ACR: + LATENCY: + WS0: [0, 0 wait states] + WS1: [1, 1 wait states] + WS2: [2, 2 wait states] + WS3: [3, 3 wait states] + WS4: [4, 4 wait states] + WS5: [5, 5 wait states] + WS6: [6, 6 wait states] + WS7: [7, 7 wait states] + WS8: [8, 8 wait states] + WS9: [9, 9 wait states] + WS10: [10, 10 wait states] + WS11: [11, 11 wait states] + WS12: [12, 12 wait states] + WS13: [13, 13 wait states] + WS14: [14, 14 wait states] + WS15: [15, 15 wait states] diff --git a/devices/fields/flash/acr/latency_8_states.yaml b/devices/fields/flash/acr/latency_8_states.yaml new file mode 100644 index 000000000..230fea48d --- /dev/null +++ b/devices/fields/flash/acr/latency_8_states.yaml @@ -0,0 +1,10 @@ +ACR: + LATENCY: + WS0: [0, 0 wait states] + WS1: [1, 1 wait states] + WS2: [2, 2 wait states] + WS3: [3, 3 wait states] + WS4: [4, 4 wait states] + WS5: [5, 5 wait states] + WS6: [6, 6 wait states] + WS7: [7, 7 wait states] diff --git a/devices/fields/flash/cr/common_f2_f4_f7.yaml b/devices/fields/flash/cr/common_f2_f4_f7.yaml new file mode 100644 index 000000000..05d1d00ff --- /dev/null +++ b/devices/fields/flash/cr/common_f2_f4_f7.yaml @@ -0,0 +1,20 @@ + +CR: + LOCK: + Unlocked: [0, FLASH_CR register is unlocked] + Locked: [1, FLASH_CR register is locked] + EOPIE: + Disabled: [0, End of operation interrupt disabled] + Enabled: [1, End of operation interrupt enabled] + STRT: + Start: [1, Trigger an erase operation] + PSIZE: + PSIZE8: [0, Program x8] + PSIZE16: [1, Program x16] + PSIZE32: [2, Program x32] + PSIZE64: [3, Program x64] + SNB: [0, 11] # TODO: this depends on device + SER: + SectorErase: [1, Erase activated for selected sector] + PG: + Program: [1, Flash programming activated] diff --git a/devices/fields/flash/cr/errie.yaml b/devices/fields/flash/cr/errie.yaml new file mode 100644 index 000000000..4186dff8e --- /dev/null +++ b/devices/fields/flash/cr/errie.yaml @@ -0,0 +1,4 @@ +CR: + ERRIE: + Disabled: [0, Error interrupt generation disabled] + Enabled: [1, Error interrupt generation enabled] diff --git a/devices/fields/flash/cr/mer.yaml b/devices/fields/flash/cr/mer.yaml new file mode 100644 index 000000000..925f10e52 --- /dev/null +++ b/devices/fields/flash/cr/mer.yaml @@ -0,0 +1,3 @@ +CR: + MER: + MassErase: [1, Erase activated for all user sectors] diff --git a/devices/fields/flash/cr/mer1_mer2.yaml b/devices/fields/flash/cr/mer1_mer2.yaml new file mode 100644 index 000000000..a10ef566f --- /dev/null +++ b/devices/fields/flash/cr/mer1_mer2.yaml @@ -0,0 +1,5 @@ +CR: + MER1: + MassErase: [1, Erase activated for all user sectors or bank 1 in dual bank mode] + MER2: + MassErase: [1, Erase activated for bank 2 in dual bank mode] diff --git a/devices/fields/flash/cr/mer_mer1.yaml b/devices/fields/flash/cr/mer_mer1.yaml new file mode 100644 index 000000000..99a645629 --- /dev/null +++ b/devices/fields/flash/cr/mer_mer1.yaml @@ -0,0 +1,5 @@ +CR: + MER: + MassErase: [1, Erase activated for bank 1 sectors] + MER1: + MassErase: [1, Erase activated for bank 2 sectors] diff --git a/devices/fields/flash/cr/rderrie.yaml b/devices/fields/flash/cr/rderrie.yaml new file mode 100644 index 000000000..3da4d70fd --- /dev/null +++ b/devices/fields/flash/cr/rderrie.yaml @@ -0,0 +1,4 @@ +CR: + RDERRIE: + Disabled: [0, PCROP error interrupt generation disabled] + Enabled: [1, PCROP error interrupt generation enabled] diff --git a/devices/fields/flash/flash_f0.yaml b/devices/fields/flash/flash_f0.yaml new file mode 100644 index 000000000..fc0f180a6 --- /dev/null +++ b/devices/fields/flash/flash_f0.yaml @@ -0,0 +1,99 @@ +# Flash peripheral +# Applicable to STM32F0 +# OBR->BOOT_SEL and OBR->nBOOT0 available only on STM32F04x and STM32F09x + +ACR: + PRFTBS: + _read: + Disabled: [0, Prefetch buffer is disabled] + Enabled: [1, Prefetch buffer is enabled] + PRFTBE: + Disabled: [0, Prefetch is disabled] + Enabled: [1, Prefetch is enabled] + LATENCY: + WS0: [0, 0 wait states] + WS1: [1, 1 wait state] + +KEYR: + FKEYR: [0, 0xFFFFFFFF] + +OPTKEYR: + OPTKEYR: [0, 0xFFFFFFFF] + +SR: + EOP: + NoEvent: [0, No EOP operation occurred] + Event: [1, An EOP event occurred] + WRPRT: + NoError: [0, No write protection error occurred] + Error: [1, A write protection error occurred] + PGERR: + NoError: [0, No programming error occurred] + Error: [1, A programming error occurred] + BSY: + _read: + Inactive: [0, No write/erase operation is in progress] + Active: [1, A write/erase operation is in progress] + +CR: + FORCE_OPTLOAD: + Inactive: [0, Force option byte loading inactive] + Active: [1, Force option byte loading active] + EOPIE: + Disabled: [0, End of operation interrupt disabled] + Enabled: [1, End of operation interrupt enabled] + ERRIE: + Disabled: [0, Error interrupt generation disabled] + Enabled: [1, Error interrupt generation enabled] + OPTWRE: + Disabled: [0, Option byte write disabled] + Enabled: [1, Option byte write enabled] + LOCK: + Unlocked: [0, FLASH_CR register is unlocked] + Locked: [1, FLASH_CR register is locked] + STRT: + Start: [1, Trigger an erase operation] + OPTER: + OptionByteErase: [1, Erase option byte activated] + OPTPG: + OptionByteProgramming: [1, Program option byte activated] + MER: + MassErase: [1, Erase activated for all user sectors] + PER: + PageErase: [1, Erase activated for selected page] + PG: + Program: [1, Flash programming activated] + +AR: + FAR: [0, 0xFFFFFFFF] + +OBR: + Data1: [0, 0xFF] + Data0: [0, 0xFF] + RAM_PARITY_CHECK: + Disabled: [1, RAM parity check disabled] + Enabled: [0, RAM parity check enabled] + VDDA_MONITOR: + Disabled: [0, VDDA power supply supervisor disabled] + Enabled: [1, VDDA power supply supervisor enabled] + nBOOT1: + Disabled: [0, "Together with BOOT0, select the device boot mode"] + Enabled: [1, "Together with BOOT0, select the device boot mode"] + nRST_STDBY: + Reset: [0, Reset generated when entering Standby mode] + NoReset: [1, No reset generated] + nRST_STOP: + Reset: [0, Reset generated when entering Stop mode] + NoReset: [1, No reset generated] + WDG_SW: + Hardware: [0, Hardware watchdog] + Software: [1, Software watchdog] + RDPRT: + Level0: [0, Level 0] + Level1: [1, Level 1] + Level2: [3, Level 2] + OPTERR: + OptionByteError: [1, The loaded option byte and its complement do not match] + +WRPR: + WRP: [0, 0xFFFFFFFF] diff --git a/devices/fields/flash/flash_f04x_f09x.yaml b/devices/fields/flash/flash_f04x_f09x.yaml new file mode 100644 index 000000000..337929670 --- /dev/null +++ b/devices/fields/flash/flash_f04x_f09x.yaml @@ -0,0 +1,10 @@ +_include: + - ./flash_f0.yaml + +OBR: + BOOT_SEL: + nBOOT0: [0, BOOT0 signal is defined by nBOOT0 option bit] + BOOT0: [1, BOOT0 signal is defined by BOOT0 pin value (legacy mode)] + nBOOT0: + Disabled: [0, "When BOOT_SEL is cleared, select the device boot mode"] + Enabled: [1, "When BOOT_SEL is cleared, select the device boot mode"] diff --git a/devices/fields/flash/flash_f1.yaml b/devices/fields/flash/flash_f1.yaml new file mode 100644 index 000000000..926800729 --- /dev/null +++ b/devices/fields/flash/flash_f1.yaml @@ -0,0 +1,5 @@ +ACR: + LATENCY: + WS0: [0, "Zero wait state, if 0 < SYSCLK≤ 24 MHz"] + WS1: [1, "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"] + WS2: [2, "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"] diff --git a/devices/fields/flash/flash_f3_common.yaml b/devices/fields/flash/flash_f3_common.yaml new file mode 100644 index 000000000..64938061f --- /dev/null +++ b/devices/fields/flash/flash_f3_common.yaml @@ -0,0 +1,107 @@ +# Flash peripheral +# Applicable to STM32F3 + +ACR: + PRFTBS: + Disabled: [0, Prefetch buffer is disabled] + Enabled: [1, Prefetch buffer is enabled] + PRFTBE: + Disabled: [0, Prefetch is disabled] + Enabled: [1, Prefetch is enabled] + LATENCY: + WS0: [0, "0 wait states, if 0 < HCLK <= 24 MHz"] + WS1: [1, "1 wait state, if 24 < HCLK <= 48 MHz"] + WS2: [2, "2 wait states, if 48 < HCLK <= 72 MHz"] + +KEYR: + FKEYR: [0, 0xFFFFFFFF] + +OPTKEYR: + OPTKEYR: [0, 0xFFFFFFFF] + +SR: + EOP: + _read: + NoEvent: [0, No EOP event occurred] + Event: [1, An EOP event occurred] + _write: + Reset: [1, Reset EOP event] + WRPRTERR: + _read: + NoError: [0, No write protection error occurred] + Error: [1, A write protection error occurred] + _write: + Reset: [1, Reset write protection error] + PGERR: + _read: + NoError: [0, No programming error occurred] + Error: [1, A programming error occurred] + _write: + Reset: [1, Reset programming error] + BSY: + _read: + Inactive: [0, No write/erase operation is in progress] + Active: [1, No write/erase operation is in progress] + +CR: + OBL_LAUNCH: + Inactive: [0, Force option byte loading inactive] + Active: [1, Force option byte loading active] + EOPIE: + Disabled: [0, End of operation interrupt disabled] + Enabled: [1, End of operation interrupt enabled] + ERRIE: + Disabled: [0, Error interrupt generation disabled] + Enabled: [1, Error interrupt generation enabled] + OPTWRE: + Disabled: [0, Option byte write enabled] + Enabled: [1, Option byte write disabled] + LOCK: + _read: + Unlocked: [0, FLASH_CR register is unlocked] + Locked: [1, FLASH_CR register is locked] + _write: + Lock: [1, Lock the FLASH_CR register] + STRT: + Start: [1, Trigger an erase operation] + OPTER: + OptionByteErase: [1, Erase option byte activated] + OPTPG: + OptionByteProgramming: [1, Program option byte activated] + MER: + MassErase: [1, Erase activated for all user sectors] + PER: + PageErase: [1, Erase activated for selected page] + PG: + Program: [1, Flash programming activated] + +AR: + FAR: [0, 0xFFFFFFFF] + +OBR: + Data1: [0, 0xFF] + Data0: [0, 0xFF] + VDDA_MONITOR: + Disabled: [0, VDDA power supply supervisor disabled] + Enabled: [1, VDDA power supply supervisor enabled] + nBOOT1: + Disabled: [0, "Together with BOOT0, select the device boot mode"] + Enabled: [1, "Together with BOOT0, select the device boot mode"] + nRST_STDBY: + Reset: [0, Reset generated when entering Standby mode] + NoReset: [1, No reset generated] + nRST_STOP: + Reset: [0, Reset generated when entering Stop mode] + NoReset: [1, No reset generated] + WDG_SW: + Hardware: [0, Hardware watchdog] + Software: [1, Software watchdog] + RDPRT: + Level0: [0, Level 0] + Level1: [1, Level 1] + Level2: [3, Level 2] + OPTERR: + OptionByteError: [1, The loaded option byte and its complement do not match] + +WRPR: + WRP: [0, 0xFFFFFFFF] diff --git a/devices/fields/flash/flash_f3_obr_sram_parity_check.yaml b/devices/fields/flash/flash_f3_obr_sram_parity_check.yaml new file mode 100644 index 000000000..701907220 --- /dev/null +++ b/devices/fields/flash/flash_f3_obr_sram_parity_check.yaml @@ -0,0 +1,5 @@ +OBR: + # Only avaliable for f302, f303 and f37x + SRAM_PARITY_CHECK: + Disabled: [0, RAM parity check disabled] + Enabled: [1, RAM parity check enabled] diff --git a/devices/fields/flash/flash_f3_obr_vdd_monitor.yaml b/devices/fields/flash/flash_f3_obr_vdd_monitor.yaml new file mode 100644 index 000000000..7e6be7d23 --- /dev/null +++ b/devices/fields/flash/flash_f3_obr_vdd_monitor.yaml @@ -0,0 +1,5 @@ +OBR: + # This flag does only exist for stm32f37x devices + SDADC12_VDD_MONITOR: + Disabled: [0, VDDSD12 monitoring disabled] + Enabled: [1, VDDSD12 monitoring enabled] diff --git a/devices/fields/flash/flash_g4.yaml b/devices/fields/flash/flash_g4.yaml new file mode 100644 index 000000000..74f6e297e --- /dev/null +++ b/devices/fields/flash/flash_g4.yaml @@ -0,0 +1,11 @@ +# Flash Peripheral +# Applicable to STM32G4 + +ACR: + LATENCY: + Wait0: [0, "Zero Wait States (Vcore Boost 1 (<= 34MHz), Vcore Normal 1 (<= 30MHz), Vcore 2 (<= 12MHz)"] + Wait1: [1, "One Wait State (Vcore Boost 1 (<= 68MHz), Vcore Normal 1 (<= 60MHz), Vcore 2 (<= 24MHz)"] + Wait2: [2, "Two Wait States (Vcore Boost 1 (<= 102MHz), Vcore Normal 1 (<= 90MHz), Vcore 2 (<= 26MHz)"] + Wait3: [3, "Three Wait States (Vcore Boost 1 (<= 136MHz), Vcore Normal 1 (<= 120MHz)"] + Wait4: [4, "Four Wait States (Vcore Boost 1 (<= 170MHz), Vcore Normal 1 (<= 150MHz)"] + # This can technically be set up to 15 however 4 is the max needed for the 170MHz operation. diff --git a/devices/fields/flash/flash_g4_dual_bank.yaml b/devices/fields/flash/flash_g4_dual_bank.yaml new file mode 100644 index 000000000..464c7893a --- /dev/null +++ b/devices/fields/flash/flash_g4_dual_bank.yaml @@ -0,0 +1,14 @@ +# Flash Peripheral +# Applicable to STM32G4 category 3 devices only + +OPTR: + DBANK: + SingleBankMode: [0, Single-bank mode with 128 bits data read width] + DualBankMode: [1, Dual-bank mode with 64 bits data] + BFB2: + Disabled: [0, Boot from memory bank 1] + Enabled: [1, Boot from memory bank 2] +CR: + BKER: + Bank1: [0, Bank 1 is selected for page erase] + Bank2: [1, Bank 2 is selected for page erase] diff --git a/devices/fields/flash/flash_l0.yaml b/devices/fields/flash/flash_l0.yaml new file mode 100644 index 000000000..db290f282 --- /dev/null +++ b/devices/fields/flash/flash_l0.yaml @@ -0,0 +1,148 @@ +# This FLASH is used on the STM32L0 families. + +ACR: + PRE_READ: + Disabled: [0, The pre-read is disabled] + Enabled: [1, The pre-read is enabled] + DISAB_BUF: + Enabled: [0, The buffers are enabled] + Disabled: [1, The buffers are disabled] + RUN_PD: + NVMIdleMode: [0, "When the device is in Run mode, the NVM is in Idle mode"] + NVMPwrDownMode: [1, "When the device is in Run mode, the NVM is in power-down mode"] + SLEEP_PD: + NVMIdleMode: [0, "When the device is in Sleep mode, the NVM is in Idle mode"] + NVMPwrDownMode: [1, "When the device is in Sleep mode, the NVM is in power-down mode"] + PRFTEN: + Disabled: [0, Prefetch is disabled] + Enabled: [1, Prefetch is enabled] + LATENCY: + WS0: [0, Zero wait state is used to read a word in the NVM] + WS1: [1, One wait state is used to read a word in the NVM] +PECR: + OBL_LAUNCH: + _read: + Complete: [0, Option byte loaded] + NotComplete: [1, Option byte loading to be done] + _write: + Reload: [1, Reload option byte] + ERRIE: + Disabled: [0, Error interrupt disable] + Enabled: [1, Error interrupt enable] + EOPIE: + Disabled: [0, End of program interrupt disable] + Enabled: [1, End of program interrupt enable] + PARALLELBANK: + Disabled: [0, Parallel bank mode disabled] + Enabled: [1, Parallel bank mode enabled] + FPRG: + Disabled: [0, Half Page programming disabled] + Enabled: [1, Half Page programming enabled] + ERASE: + NoErase: [0, No erase operation requested] + Erase: [1, Erase operation requested] + FIX: + AutoErase: [0, An erase phase is automatically performed] + PrelimErase: [1, The program operation is always performed with a preliminary erase] + DATA: + NotSelected: [0, Data EEPROM not selected] + Selected: [1, Data memory selected] + PROG: + NotSelected: [0, The Flash program memory is not selected] + Selected: [1, The Flash program memory is selected] + OPTLOCK: + Unlocked: [0, The write and erase operations in the Option bytes area are disabled] + Locked: [1, The write and erase operations in the Option bytes area are enabled] + PRGLOCK: + Unlocked: [0, The write and erase operations in the Flash program memory are disabled] + Locked: [1, The write and erase operations in the Flash program memory are enabled] + PELOCK: + Unlocked: [0, The FLASH_PECR register is unlocked] + Locked: [1, The FLASH_PECR register is locked and no write/erase operation can start] +PDKEYR: + PDKEYR: [0, 0xFFFFFFFF] +PEKEYR: + PEKEYR: [0, 0xFFFFFFFF] +PRGKEYR: + PRGKEYR: [0, 0xFFFFFFFF] +OPTKEYR: + OPTKEYR: [0, 0xFFFFFFFF] +SR: + FWWERR: + _read: + NoError: [0, No write/erase operation aborted to perform a fetch] + Error: [1, A write/erase operation aborted to perform a fetch] + _write: + Clear: [1, Clear the flag] + NOTZEROERR: + _read: + NoEvent: + [0, The write operation is done in an erased region or the memory interface can apply an erase before a write] + Event: + [ + 1, + The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write, + ] + _write: + Clear: [1, Clear the flag] + RDERR: + _read: + NoError: [0, No read protection error happened.] + Error: [1, One read protection error happened] + _write: + Clear: [1, Clear the flag] + OPTVERR: + _read: + NoError: [0, No error happened during the Option bytes loading] + Error: [1, One or more errors happened during the Option bytes loading] + _write: + Clear: [1, Clear the flag] + SIZERR: + _read: + NoError: [0, No size error happened] + Error: [1, One size error happened] + _write: + Clear: [1, Clear the flag] + PGAERR: + _read: + NoError: [0, No alignment error happened] + Error: [1, One alignment error happened] + _write: + Clear: [1, Clear the flag] + WRPERR: + _read: + NoError: [0, No protection error happened] + Error: [1, One protection error happened] + _write: + Clear: [1, Clear the flag] + READY: + NotReady: [0, The NVM is not ready] + Ready: [1, The NVM is ready] + ENDHV: + Active: [0, High voltage is executing a write/erase operation in the NVM] + Inactive: [1, "High voltage is off, no write/erase operation is ongoing"] + EOP: + NoEvent: [0, No EOP operation occurred] + Event: [1, An EOP event occurred] + BSY: + Inactive: [0, No write/erase operation is in progress] + Active: [1, No write/erase operation is in progress] +OPTR: + BOR_LEV: + BOR_Off: [0, This is the reset threshold level for the 1.45 V - 1.55 V voltage range (power-down only)] + BOR_Level1: [1, Reset threshold level for VBOR0 (around 1.8 V)] + BOR_Level2: [2, Reset threshold level for VBOR1 (around 2.0 V)] + BOR_Level3: [3, Reset threshold level for VBOR2 (around 2.5 V)] + BOR_Level4: [4, Reset threshold level for VBOR3 (around 2.7 V)] + BOR_Level5: [5, Reset threshold level for VBOR4 (around 3.0 V)] + WPRMOD: + Disabled: [0, PCROP disabled. The WRPROT bits are used as a write protection on a sector.] + Enabled: [1, PCROP enabled. The WRPROT bits are used as a read protection on a sector.] + RDPROT: + Level0: [0xAA, Level 0] + Level1: [0, Level 1] + Level2: [0xCC, Level 2] +WRPROT1: + WRPROT1: [0, 0xFFFFFFFF] +WRPROT2: + WRPROT2: [0, 0xFFFF] diff --git a/devices/fields/flash/flash_l4+.yaml b/devices/fields/flash/flash_l4+.yaml new file mode 100644 index 000000000..f2dd61046 --- /dev/null +++ b/devices/fields/flash/flash_l4+.yaml @@ -0,0 +1,325 @@ +ACR: + SLEEP_PD: + Idle: [0, Flash in idle mode during Sleep and Low-power sleep modes] + PowerDown: [1, Flash in Power-down mode during Sleep and Low-power sleep modes] + RUN_PD: + Idle: [0, Flash in idle mode] + PowerDown: [1, Flash in Power-down mode] + DCRST: + NotReset: [0, Data cache is not reset] + Reset: [1, Data cache is reset] + ICRST: + NotReset: [0, Instruction cache is not reset] + Reset: [1, Instruction cache is reset] + DCEN: + Disabled: [0, Data cache is disabled] + Enabled: [1, Data cache is enabled] + ICEN: + Disabled: [0, Instruction cache is disabled] + Enabled: [1, Instruction cache is enabled] + PRFTEN: + Disabled: [0, Prefetch is disabled] + Enabled: [1, Prefetch is enabled] + LATENCY: + WS0: [0, 0 wait states] + WS1: [1, 1 wait states] + WS2: [2, 2 wait states] + WS3: [3, 3 wait states] + WS4: [4, 4 wait states] + WS5: [5, 5 wait states] + WS6: [6, 6 wait states] + WS7: [7, 7 wait states] + WS8: [8, 8 wait states] + WS9: [9, 9 wait states] + WS10: [10, 10 wait states] + WS11: [11, 11 wait states] + WS12: [12, 12 wait states] + WS13: [13, 13 wait states] + WS14: [14, 14 wait states] + WS15: [15, 15 wait states] + +PDKEYR: + PDKEYR: [0, 0xFFFFFFFF] + +KEYR: + KEYR: [0, 0xFFFFFFFF] + +OPTKEYR: + OPTKEYR: [0, 0xFFFFFFFF] + +SR: + PEMPTY: + Toggling: [0, The bit value is toggling] + NoEffect: [1, No effect] + BSY: + NotBusy: [0, Not busy] + Busy: [1, Busy] + OPTVERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + "Set by hardware when the options read may not be the one configured by the user. If option haven’t been properly loaded, OPTVERR is set again after each system reset", + ] + NoError: [0, No error] + RDERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + Set by hardware when an address to be read through the D-bus belongs to a read protected area of the Flash (PCROP protection), + ] + NoError: [0, No error] + FASTERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + "Set by hardware when a fast programming sequence (activated by FSTPG) is interrupted due to an error (alignment, size, write protection or data miss). The corresponding status bit (PGAERR, SIZERR, WRPERR or MISSERR) is set at the same time", + ] + NoError: [0, No error] + MISERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + "In fast programming mode, 32 double words must be sent to Flash successively, and the new data must be sent to the Flash logic control before the current data is fully programmed. MISSERR is set by hardware when the new data is not present in time", + ] + NoError: [0, No error] + PGSERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + "Set by hardware when a write access to the Flash memory is performed by the code while PG or FSTPG have not been set previously. Set also by hardware when PROGERR, SIZERR, PGAERR, WRPERR, MISSERR or FASTERR is set due to a previous programming error. Set also when trying to perform bank erase when DBANK=0 (or DB1M = 0)", + ] + NoError: [0, No error] + SIZERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + "Set by hardware when the size of the access is a byte or half-word during a program or a fast program sequence. Only double word programming is allowed (consequently: word access)", + ] + NoError: [0, No error] + PGAERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + "Set by hardware when the data to program cannot be contained in the same 64-bit Flash memory row in case of standard programming, or if there is a change of page during fast programming", + ] + NoError: [0, No error] + WRPERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + "Set by hardware when an address to be erased/programmed belongs to a writeprotected part (by WRP, PCROP or RDP level 1) of the Flash memory", + ] + NoError: [0, No error] + PROGERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + "Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'", + ] + NoError: [0, No error] + OPERR: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: [1, Set by hardware when a Flash memory operation (program / erase) completes unsuccessfully] + NoError: [0, No error] + EOP: + _write: + Clear: [1, Cleared by writing 1] + _read: + Error: + [ + 1, + Set by hardware when one or more Flash memory operation (programming / erase) has been completed successfully, + ] + NoError: [0, No error] + +CR: + LOCK: + _write: + Set: [1, "This bit is set only. When set, the FLASH_CR register is locked"] + _read: + Unlocked: [0, FLASH_CR register is unlocked] + Locked: [1, FLASH_CR register is locked] + OPTLOCK: + _write: + Set: + [ + 1, + "This bit is set only. When set, all bits concerning user option in FLASH_CR register and so option page are locked", + ] + _read: + Unlocked: [0, Option page is unlocked] + Locked: [1, All bits concerning user option in FLASH_CR register and so option page are locked] + OBL_LAUNCH: + _write: + Set: [1, Force option byte reloading] + _read: + Complete: [0, Option byte loading complete] + Requested: [1, " Option byte loading requested"] + RDERRIE: + Disabled: [0, PCROP read error interrupt disabled] + Enabled: [1, PCROP read error interrupt enabled] + ERRIE: + Disabled: [0, Error interrupt generation disabled] + Enabled: [1, Error interrupt generation enabled] + EOPIE: + Disabled: [0, End of operation interrupt disabled] + Enabled: [1, End of operation interrupt enabled] + FSTPG: + Disabled: [0, Fast programming disabled] + Enabled: [1, Fast programming enabled] + OPTSTRT: + _write: + Set: [1, This bit triggers an options operation when set] + _read: + Complete: [0, Cleared when BSY bit is cleared in SR] + Requested: [1, Options modification requested] + START: + _write: + Start: [1, Trigger an erase operation] + _read: + Complete: [0, Cleared when BSY bit is cleared in SR] + Requested: [1, Erase operation requested] + MER2: + _write: + MassErase: [1, This bit triggers the bank 2 mass erase (all bank 2 user pages) when set] + BKER: + Bank1: [0, Bank 1 is selected for page erase] + Bank2: [1, Bank 2 is selected for page erase] + PNB: [0, 255] + MER1: + _write: + MassErase: [1, This bit triggers the bank 1 mass erase (all bank 1 user pages) when set] + PER: + Disabled: [0, Page erase disabled] + Enabled: [1, Page erase enabled] + PG: + Disabled: [0, Flash programming disabled] + Enabled: [1, Flash programming enabled] + +ECCR: + ECCD: + _write: + Clear: [1, Cleared by writing 1] + _read: + NoError: [0, No double ECC errors detected on LSB] + Error: [1, Set by hardware when two ECC errors have been detected on LSB] + ECCC: + _write: + Clear: [1, Cleared by writing 1] + _read: + NoError: [0, No ECC error detected on LSB] + Error: [1, Set by hardware when one ECC errors have been detected and corrected on LSB] + ECCD2: + _write: + Clear: [1, Cleared by writing 1] + _read: + NoError: [0, No double ECC errors detected on MSB] + Error: [1, Set by hardware when two ECC errors have been detected on MSB] + ECCC2: + _write: + Clear: [1, Cleared by writing 1] + _read: + NoError: [0, No ECC error detected on MSB] + Error: [1, Set by hardware when one ECC errors have been detected and corrected on MSB] + ECCIE: + Disabled: [0, ECCC interrupt disabled] + Enabled: [1, ECCC interrupt enabled] + SYSF_ECC: + InSystemFlash: + [1, This bit indicates that the ECC error correction or double ECC error detection is located in the System Flash] + BK_ECC: + Bank1: [0, Bank 1] + Bank2: [1, Bank 2] + ADDR_ECC: [0, 0x1FFFFF] + +OPTR: + nBOOT0: + Disabled: [0, "nBOOT0 = 0"] + Enabled: [1, "nBOOT0 = 1"] + nSWBOOT0: + OptionBit: [0, BOOT0 taken from the option bit nBOOT0] + Pin: [1, BOOT0 taken from PH3/BOOT0 pin] + SRAM2_RST: + Enabled: [0, SRAM2 erased when a system reset occurs] + Disabled: [1, SRAM2 is not erased when a system reset occurs] + SRAM2_PE: + Enabled: [0, " SRAM2 parity check enabled"] + Disabled: [1, " SRAM2 parity check disabled"] + DBANK: + SingleBankMode: [0, Single-bank mode with 128 bits data read width] + DualBankMode: [1, Dual-bank mode with 64 bits data] + DB1M: + SingleBank: [0, Single Flash contiguous address in Bank 1] + DualBank: [1, Dual-bank Flash with contiguous addresses] + BFB2: + Disabled: [0, Dual-bank boot disabled] + Enabled: [1, Dual-bank boot enabled] + WWDG_SW: + Hardware: [0, Hardware window watchdog] + Software: [1, Software window watchdog] + IWDG_STDBY: + Frozen: [0, Independent watchdog counter is frozen in Standby mode] + Running: [1, Independent watchdog counter is running in Standby mode] + IWDG_STOP: + Frozen: [0, Independent watchdog counter is frozen in Stop mode] + Running: [1, Independent watchdog counter is running in Stop mode] + IWDG_SW: + Hardware: [0, Hardware independent watchdog] + Software: [1, Software independent watchdog] + +PCROP1SR: + PCROP1_STRT: [0, 0x1FFFF] + +PCROP1ER: + PCROP_RDP: + Disabled: [0, PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0] + Enabled: [1, PCROP area is erased when the RDP level is decreased from Level 1 to Level 0] + PCROP1_END: [0, 0x1FFFF] + +PCROP2SR: + PCROP2_STRT: [0, 0x1FFFF] + +PCROP2ER: + PCROP2_END: [0, 0x1FFFF] + +WRP1BR: + WRP1B_END: [0, 0xFF] + WRP1B_STRT: [0, 0xFF] + +WRP2BR: + WRP2B_END: [0, 0xFF] + WRP2B_STRT: [0, 0xFF] + +CFGR: + LVEN: + Disabled: [0, Flash low voltage disabled] + Enabled: [1, Flash low voltage enabled] diff --git a/devices/fields/flash/flash_wl.yaml b/devices/fields/flash/flash_wl.yaml new file mode 100644 index 000000000..1182e84fb --- /dev/null +++ b/devices/fields/flash/flash_wl.yaml @@ -0,0 +1,262 @@ +ACR: + EMPTY: + Programmed: [0, User Flash programmend] + Empty: [1, User Flash empty] + PES: + Granted: [0, Flash program and erase operations granted] + Suspended: + [ + 1, + Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_SR is set when PES bit in FLASH_ACR is set, + ] + DCRST: + NotReset: [0, Data cache is not reset] + Reset: [1, Data cache is reset] + ICRST: + NotReset: [0, Instruction cache is not reset] + Reset: [1, Instruction cache is reset] + DCEN: + Disabled: [0, Data cache is disabled] + Enabled: [1, Data cache is enabled] + ICEN: + Disabled: [0, Instruction cache is disabled] + Enabled: [1, Instruction cache is enabled] + PRFTEN: + Disabled: [0, Prefetch is disabled] + Enabled: [1, Prefetch is enabled] + LATENCY: + WS0: [0, 0 wait states] + WS1: [1, 1 wait states] + WS2: [2, 2 wait states] + +KEYR: + KEY: [0, 0xFFFFFFFF] + +OPTKEYR: + OPTKEY: [0, 0xFFFFFFFF] + +SR: + _modify: + OPTVN: + name: OPTNV + MISERR: + name: MISSERR + PESD: + Granted: [0, Flash program and erase operations granted] + Suspended: + [ + 1, + Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when the PES bit in FLASH_ACR is set, + ] + CFGBSY: + Free: [0, "PG, PNB, PER, MER bits available for writing"] + Busy: [1, "PG, PNB, PER, MER bits not available for writing (operation ongoing)"] + BSY: + Inactive: [0, No write/erase operation is in progress] + Active: [1, No write/erase operation is in progress] + OPTVERR: + _read: + NoError: [0, No error in option and engineering bits] + Error: [1, Error in option and engineering bits] + _write: + Clear: [1, Clear the flag] + RDERR: + _read: + NoError: [0, No read-only error happened] + Error: [1, Read-only error happened] + _write: + Clear: [1, Clear the flag] + OPTNV: + Valid: [0, 'The OBL user option OPTVAL indicates "valid"'] + Invalid: [1, 'The OBL user option OPTVAL indicates "invalid"'] + FASTERR: + _read: + NoError: [0, No fast programming error happened] + Error: [1, Fast programming error happened] + _write: + Clear: [1, Clear the flag] + MISSERR: + _read: + NoError: [0, No fast programming data miss error happened] + Error: [1, Fast programming data miss error happened] + _write: + Clear: [1, Clear the flag] + PGSERR: + _read: + NoError: [0, No fast programming sequence error happened] + Error: [1, Fast programming sequence error happened] + _write: + Clear: [1, Clear the flag] + SIZERR: + _read: + NoError: [0, No size error happened] + Error: [1, Size error happened] + _write: + Clear: [1, Clear the flag] + PGAERR: + _read: + NoError: [0, No programming alignment error happened] + Error: [1, Programming alignment error happened] + _write: + Clear: [1, Clear the flag] + WRPERR: + _read: + NoError: [0, No write protection error happened] + Error: [1, Write protection error happened] + _write: + Clear: [1, Clear the flag] + PROGERR: + _read: + NoError: [0, No size programming error happened] + Error: [1, Programming error happened] + _write: + Clear: [1, Clear the flag] + OPERR: + _read: + NoError: [0, No memory opreation error happened] + Error: [1, Memory operation error happened] + _write: + Clear: [1, Clear the flag] + EOP: + _read: + NoEvent: [0, No EOP operation occurred] + Event: [1, An EOP event occurred] + _write: + Clear: [1, Clear the flag] +CR: + LOCK: + _read: + Unlocked: [0, FLASH_CR is unlocked] + _write: + Locked: [1, FLASH_CR is locked] + OPTLOCK: + _read: + Unlocked: [0, FLASH_CR options are unlocked] + _write: + Locked: [1, FLASH_CR options are locked] + OBL_LAUNCH: + _read: + Complete: [0, Option byte loaded] + NotComplete: [1, Option byte loading to be done] + _write: + Reload: [1, Reload option byte] + RDERRIE: + Disabled: [0, PCROP read error interrupt disable] + Enabled: [1, PCROP read error interrupt enable] + ERRIE: + Disabled: [0, OPERR Error interrupt disable] + Enabled: [1, OPERR Error interrupt enable] + EOPIE: + Disabled: [0, End of program interrupt disable] + Enabled: [1, End of program interrupt enable] + FSTPG: + Disabled: [0, Fast programming disabled] + Enabled: [1, Fast programming enabled] + OPTSTRT: + _read: + Done: [0, Options modification completed or idle] + _write: + Start: [1, Trigger options programming operation] + STRT: + _read: + Done: [0, Options modification completed or idle] + _write: + Start: [1, Trigger options programming operation] + PNB: [0, 0x7F] + MER: + NoErase: [0, No mass erase] + MassErase: [1, Trigger mass erase] + PER: + Disabled: [0, Page erase disabled] + Enabled: [1, Page erase enabled] + PG: + Disabled: [0, Flash programming disabled] + Enabled: [1, Flash programming enabled] + +ECCR: + ECCD: + _read: + NoEvent: [0, Two ECC errors detected] + Event: [1, No two ECC errors detected] + _write: + Clear: [1, Clear the flag] + ECCC: + _read: + NoEvent: [0, ECC error corrected] + Event: [1, No ECC error corrected] + _write: + Clear: [1, Clear the flag] + ECCCIE: + Disabled: [0, ECCC interrupt disabled] + Enabled: [1, ECCC interrupt enabled] + SYSF_ECC: + NotInFlash: [0, No System Flash memory ECC fail] + InFlash: [1, System Flash memory ECC fail] + ADDR_ECC: [0, 0x1FFFF] +OPTR: + _modify: + SRAM2_RST: + name: SRAM_RST + BOOT_LOCK: + Disabled: [0, Boot lock is disabled] + Enabled: [1, Boot lock is enabled] + nBOOT0: + Clear: [0, "When nSWBOOT0 is cleared, select boot mode together with nBOOT1"] + Set: [1, "When nSWBOOT0 is cleared, select boot mode together with nBOOT1"] + nSWBOOT0: + Bit: [0, BOOT0 taken from nBOOT0 in this register] + Pin: [1, BOOT0 taken from GPIO PH3/BOOT0] + SRAM_RST: + Reset: [0, SRAM1 and SRAM2 erased when a system reset occurs] + NotReset: [1, SRAM1 and SRAM2 not erased when a system reset occurs] + SRAM2_PE: + Enabled: [0, SRAM2 Parity check enabled] + Disabled: [1, SRAM2 Parity check disabled] + nBOOT1: + Clear: [0, "When nSWBOOT0 is cleared, select boot mode together with nBOOT0"] + Set: [1, "When nSWBOOT0 is cleared, select boot mode together with nBOOT0"] + WWDG_SW: + Hardware: [0, Hardware window watchdog] + Software: [1, Software window watchdog] + IWDG_STDBY: + Frozen: [0, Independent watchdog counter frozen in Standby mode] + Running: [1, Independent watchdog counter running in Standby mode] + IWDG_STOP: + Frozen: [0, Independent watchdog counter frozen in Stop mode] + Running: [1, Independent watchdog counter running in Stop mode] + IWDG_SW: + Hardware: [0, Hardware independent watchdog] + Software: [1, Software independent watchdog] + nRST_SHDW: + Enabled: [0, Reset generated when entering the Shutdown mode] + Disabled: [1, No reset generated when entering the Shutdown mode] + nRST_STDBY: + Enabled: [0, Reset generated when entering the Standby mode] + Disabled: [1, No reset generated when entering the Standby mode] + nRST_STOP: + Enabled: [0, Reset generated when entering the Standby mode] + Disabled: [1, No reset generated when entering the Standby mode] + BOR_LEV: + Level0: [0, BOR level 0. Reset level threshold is around 1.7 V] + Level1: [1, BOR level 1. Reset level threshold is around 2.0 V] + Level2: [2, BOR level 2. Reset level threshold is around 2.2 V] + Level3: [3, BOR level 3. Reset level threshold is around 2.5 V] + Level4: [4, BOR level 4. Reset level threshold is around 2.8 V] + ESE: + Disabled: [0, Security disabled] + Enabled: [1, Security enabled] + RDP: + Level0: [0xAA, "Level 0, readout protection not active"] + Level2: [0xCC, "Level 2, chip readout protection active"] + # The manual specifies "Others" for Level 1, 0x88 is arbitrary + # Since the reset value is AA, the value for Level 1 needs to be written + # so there is no conflict reading other values (unless unsafe is used) + Level1: [0x88, "Level 1, memories readout protection active (writes 0x88)"] + +PCROP1?SR: + PCROP1?_STRT: [0, 0xFF] +PCROP1?ER: + PCROP1?_END: [0, 0xFF] +WRP1?R: + WRP1?_END: [0, 0x7F] + WRP1?_STRT: [0, 0x7F] diff --git a/devices/fields/flash/flash_wl_c2.yaml b/devices/fields/flash/flash_wl_c2.yaml new file mode 100644 index 000000000..6294ce396 --- /dev/null +++ b/devices/fields/flash/flash_wl_c2.yaml @@ -0,0 +1,164 @@ +IPCCBR: + IPCCDBA: [0, 0x3FFF] +C2ACR: + PES: + Granted: [0, Flash program and erase operations granted] + Suspended: + [ + 1, + Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_C2SR is set when PES bit in FLASH_C2ACR is set, + ] + ICRST: + NotReset: [0, CPU2 instruction cache is not reset] + Reset: [1, CPU2 instruction cache is reset] + ICEN: + Disabled: [0, CPU2 instruction cache is disabled] + Enabled: [1, CPU2 instruction cache is enabled] + PRFTEN: + Disabled: [0, CPU2 prefetch is disabled] + Enabled: [1, CPU2 prefetch is enabled] +C2SR: + _modify: + MISERR: + name: MISSERR + PESD: + Granted: [0, Flash program and erase operations granted] + Suspended: + [ + 1, + Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when at least one PES bit in FLASH_ACR or FLASH_C2ACR is set., + ] + CFGBSY: + Free: [0, "PG, PNB, PER, MER bits available for writing"] + Busy: [1, "PG, PNB, PER, MER bits not available for writing (operation ongoing)"] + BSY: + Inactive: [0, No write/erase operation is in progress] + Active: [1, No write/erase operation is in progress] + RDERR: + _read: + NoError: [0, No read-only error happened] + Error: [1, Read-only error happened] + _write: + Clear: [1, Clear the flag] + FASTERR: + _read: + NoError: [0, No fast programming error happened] + Error: [1, Fast programming error happened] + _write: + Clear: [1, Clear the flag] + MISSERR: + _read: + NoError: [0, No fast programming data miss error happened] + Error: [1, Fast programming data miss error happened] + _write: + Clear: [1, Clear the flag] + PGSERR: + _read: + NoError: [0, No fast programming sequence error happened] + Error: [1, Fast programming sequence error happened] + _write: + Clear: [1, Clear the flag] + SIZERR: + _read: + NoError: [0, No size error happened] + Error: [1, Size error happened] + _write: + Clear: [1, Clear the flag] + PGAERR: + _read: + NoError: [0, No programming alignment error happened] + Error: [1, Programming alignment error happened] + _write: + Clear: [1, Clear the flag] + WRPERR: + _read: + NoError: [0, No write protection error happened] + Error: [1, Write protection error happened] + _write: + Clear: [1, Clear the flag] + PROGERR: + _read: + NoError: [0, No size programming error happened] + Error: [1, Programming error happened] + _write: + Clear: [1, Clear the flag] + OPERR: + _read: + NoError: [0, No memory opreation error happened] + Error: [1, Memory operation error happened] + _write: + Clear: [1, Clear the flag] + EOP: + _read: + NoEvent: [0, No EOP operation occurred] + Event: [1, An EOP event occurred] + _write: + Clear: [1, Clear the flag] +C2CR: + RDERRIE: + Disabled: [0, PCROP read error interrupt disable] + Enabled: [1, PCROP read error interrupt enable] + ERRIE: + Disabled: [0, OPERR Error interrupt disable] + Enabled: [1, OPERR Error interrupt enable] + EOPIE: + Disabled: [0, End of program interrupt disable] + Enabled: [1, End of program interrupt enable] + FSTPG: + Disabled: [0, Fast programming disabled] + Enabled: [1, Fast programming enabled] + STRT: + _read: + Done: [0, Options modification completed or idle] + _write: + Start: [1, Trigger options programming operation] + PNB: [0, 0x7F] + MER: + NoErase: [0, No mass erase] + MassErase: [1, Trigger mass erase] + PER: + Disabled: [0, Page erase disabled] + Enabled: [1, Page erase enabled] + PG: + Disabled: [0, Flash programming disabled] + Enabled: [1, Flash programming enabled] +SFR: + SUBGHSPISD: + Enabled: [0, sub-GHz radio SPI security enabled] + Disabled: [1, sub-GHz radio SPI security disabled] + HDPAD: + Enabled: + [ + 0, + "User Flash memory hide protection area enabled. HDPSA[6:0] contains the start address of the first 2-Kbyte page of the user Flash memory hide protection area", + ] + Disabled: [1, User Flash memory hide protection area disabled] + HDPSA: [0, 0x7F] + DDS: + Enabled: [0, CPU2 debug access enabled] + Disabled: [1, CPU2 debug access disabled] + FSD: + Secure: [0, System and Flash memory secure] + NonSecure: [1, System and Flash memory non-secure] + SFSA: [0, 0x7F] +SRRVR: + C2OPT: + SRAM: [0, "SBRV offset addresses SRAM1 or SRAM2, from start address 0x2000_0000 + SBRV"] + Flash: [1, "SBRV offset addresses the Flash memory, from start address 0x0800_0000 + SBRV"] + NBRSD: + Secure: + [ + 0, + "SRAM1 is secure. SNBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure non-backup SRAM1 area", + ] + NonSecure: [1, SRAM1 is non-secure] + SNBRSA: [0, 0x1F] + BRSD: + Secure: + [ + 0, + "SRAM2 is secure. SNBRSA[4:0] contains the start address of the first 1-Kbyte page of the secure backup SRAM2 area", + ] + NonSecure: [1, SRAM2 is non-secure] + SBRSA: [0, 0x1F] + SBRV: [0, 0xFFFF] diff --git a/devices/fields/flash/keyr/common.yaml b/devices/fields/flash/keyr/common.yaml new file mode 100644 index 000000000..9706a2c32 --- /dev/null +++ b/devices/fields/flash/keyr/common.yaml @@ -0,0 +1,2 @@ +KEYR: + KEY: [0, 0xFFFFFFFF] diff --git a/devices/fields/flash/optcr/bfb2.yaml b/devices/fields/flash/optcr/bfb2.yaml new file mode 100644 index 000000000..905c4d4c4 --- /dev/null +++ b/devices/fields/flash/optcr/bfb2.yaml @@ -0,0 +1,4 @@ +OPTCR: + BFB2: + Disabled: [0, Dual-bank boot disabled] + Enabled: [1, Dual-bank boot enabled] diff --git a/devices/fields/flash/optcr/common.yaml b/devices/fields/flash/optcr/common.yaml new file mode 100644 index 000000000..2b46bb980 --- /dev/null +++ b/devices/fields/flash/optcr/common.yaml @@ -0,0 +1,32 @@ +# Description of OPTCR register with nWRP only. +OPTCR: + nWRP*: + Active: [0, Write protection active on sector %s] + Inactive: [1, Write protection inactive on sector %s] + RDP: + Level0: [0xAA, Read protection not active] + Level2: [0xCC, Chip read protection active] + Level1: [-1, Read protection of memories active] + nRST_STDBY: + Reset: [0, Reset generated when entering Standby mode] + NoReset: [1, No reset generated] + nRST_STOP: + Reset: [0, Reset generated when entering Stop mode] + NoReset: [1, No reset generated] + BOR_LEV: + BOR_Off: [0, Reset threshold level for POR/PDR (around 1.7V)] + BOR_Level1: [1, Reset threshold level for VBOR1 (around 2.2 V)] + BOR_Level2: [2, Reset threshold level for VBOR2 (around 2.5 V)] + BOR_Level3: [3, Reset threshold level for VBOR3 (around 2.8 V)] + OPTSTRT: + _write: + Set: [1, This bit triggers an options operation when set] + _read: + Complete: [0, Cleared when BSY bit is cleared in SR] + Requested: [1, Options modification requested] + OPTLOCK: + _write: + Set: [1, Lock the FLASH_OPTCR register] + _read: + Unlocked: [0, The write and erase operations in the Option bytes area are disabled] + Locked: [1, The write and erase operations in the Option bytes area are enabled] diff --git a/devices/fields/flash/optcr/db1m.yaml b/devices/fields/flash/optcr/db1m.yaml new file mode 100644 index 000000000..7ae48324a --- /dev/null +++ b/devices/fields/flash/optcr/db1m.yaml @@ -0,0 +1,4 @@ +OPTCR: + DB1M: + SingleBank: [0, Single bank with contiguous addresses in bank 1] + DualBank: [1, Dual bank with two banks of 512kB] diff --git a/devices/fields/flash/optcr/iwdg_wwdg.yaml b/devices/fields/flash/optcr/iwdg_wwdg.yaml new file mode 100644 index 000000000..e7b610d7b --- /dev/null +++ b/devices/fields/flash/optcr/iwdg_wwdg.yaml @@ -0,0 +1,13 @@ +OPTCR: + IWDG_STOP: + Inactive: [0, IWDG counter frozen in Stop mode] + Active: [1, IWDG counter active in Stop mode] + IWDG_STDBY: + Inactive: [0, IWDG counter frozen in Standby mode] + Active: [1, IWDG counter active in Standby mode] + IWDG_SW: + Hardware: [0, Hardware independant watchdog] + Software: [1, Software independant watchdog] + WWDG_SW: + Hardware: [0, Hardware window watchdog] + Software: [1, Software window watchdog] diff --git a/devices/fields/flash/optcr/ndbank_ndboot.yaml b/devices/fields/flash/optcr/ndbank_ndboot.yaml new file mode 100644 index 000000000..ecd0c7f0d --- /dev/null +++ b/devices/fields/flash/optcr/ndbank_ndboot.yaml @@ -0,0 +1,7 @@ +OPTCR: + nDBANK: + DualBank: [0, The Flash user area is seen as a single bank with 256 bits read access] + SingleBank: [1, The Flash user area is seen as a dual bank with 128 bits read access (dual bank mode feature active)] + nDBOOT: + Enabled: [0, "Boot always from system memory if boot address is in flash (Dual bank Boot mode), or RAM if Boot address option in RAM"] + Disabled: [1, Boot according to boot address option] diff --git a/devices/fields/flash/optcr/sprmod.yaml b/devices/fields/flash/optcr/sprmod.yaml new file mode 100644 index 000000000..edfdcf406 --- /dev/null +++ b/devices/fields/flash/optcr/sprmod.yaml @@ -0,0 +1,4 @@ +OPTCR: + SPRMOD: + Disabled: [0, nWPRi bits used for Write protection on sector i] + Enabled: [1, nWPRi bits used for PCROP protection on sector i] diff --git a/devices/fields/flash/optcr/wdg.yaml b/devices/fields/flash/optcr/wdg.yaml new file mode 100644 index 000000000..bf894b27b --- /dev/null +++ b/devices/fields/flash/optcr/wdg.yaml @@ -0,0 +1,4 @@ +OPTCR: + WDG_SW: + Hardware: [0, Hardware watchdog] + Software: [1, Software watchdog] diff --git a/devices/fields/flash/optcr1/boot.yaml b/devices/fields/flash/optcr1/boot.yaml new file mode 100644 index 000000000..d5edd0e0c --- /dev/null +++ b/devices/fields/flash/optcr1/boot.yaml @@ -0,0 +1,19 @@ +OPTCR1: + BOOT_ADD1: + ItcmRam: [0x0000, Boot from ITCM RAM (0x0000 0000)] + SystemMemoryBootloader: [0x0040, Boot from System memory bootloader (0x0010 0000)] + FlashItcmInterface: [0x0080, Boot from Flash on ITCM interface (0x0020 0000)] + FlashAximInterface: [0x2000, Boot from Flash on AXIM interface (0x0800 0000)] + DtcmRam: [0x8000, Boot from DTCM RAM (0x2000 0000)] + Sram1: [0x8004, Boot from SRAM1 (0x2001 0000)] + Sram2: [0x8013, Boot from SRAM2 (0x2003 C000)] + BootAddress: [-1, Boot from specified address (granularity of 16KB)] + BOOT_ADD0: + ItcmRam: [0x0000, Boot from ITCM RAM (0x0000 0000)] + SystemMemoryBootloader: [0x0040, Boot from System memory bootloader (0x0010 0000)] + FlashItcmInterface: [0x0080, Boot from Flash on ITCM interface (0x0020 0000)] + FlashAximInterface: [0x2000, Boot from Flash on AXIM interface (0x0800 0000)] + DtcmRam: [0x8000, Boot from DTCM RAM (0x2000 0000)] + Sram1: [0x8004, Boot from SRAM1 (0x2001 0000)] + Sram2: [0x8013, Boot from SRAM2 (0x2003 C000)] + BootAddress: [-1, Boot from specified address (granularity of 16KB)] diff --git a/devices/fields/flash/optcr1/nwrp.yaml b/devices/fields/flash/optcr1/nwrp.yaml new file mode 100644 index 000000000..896e34bc2 --- /dev/null +++ b/devices/fields/flash/optcr1/nwrp.yaml @@ -0,0 +1,5 @@ +# Description of OPTCR1 register with nWRP only. +OPTCR1: + nWRP*: + Active: [0, Write protection active on sector %s (bank 2)] + Inactive: [1, Write protection inactive on sector %s (bank 2)] diff --git a/devices/fields/flash/optcr2/common.yaml b/devices/fields/flash/optcr2/common.yaml new file mode 100644 index 000000000..8ec19f4b6 --- /dev/null +++ b/devices/fields/flash/optcr2/common.yaml @@ -0,0 +1,7 @@ +OPTCR2: + PCROP_RDP: + PcropKept: [0, "PCROP zone is kept when RDP is decreased: Partial mass erase is done"] + PcropErased: [1, "PCROP zone is erased when RDP is decreased: Full mass erase is done"] + PCROP*: + Inactive: [0, PCROP protection inactive on sector %s] + Active: [1, PCROP protection active on sector %s] diff --git a/devices/fields/flash/optkeyr/common.yaml b/devices/fields/flash/optkeyr/common.yaml new file mode 100644 index 000000000..4c4938a36 --- /dev/null +++ b/devices/fields/flash/optkeyr/common.yaml @@ -0,0 +1,2 @@ +OPTKEYR: + OPTKEYR: [0, 0xFFFFFFFF] diff --git a/devices/fields/flash/sr/common_f2_f4_f7.yaml b/devices/fields/flash/sr/common_f2_f4_f7.yaml new file mode 100644 index 000000000..787e7f269 --- /dev/null +++ b/devices/fields/flash/sr/common_f2_f4_f7.yaml @@ -0,0 +1,35 @@ +SR: + BSY: + _read: + NotBusy: [0, No Flash memory operation ongoing] + Busy: [1, Flash memory operation ongoing] + PGPERR: + _read: + Inactive: [0, No error] + Active: [1, The size of the access during the program sequence doesn't correspond to the parallelism configuration PSIZE] + _W1C: + Clear: [1, Clear error flag] + PGAERR: + _read: + Inactive: [0, No error] + Active: [1, The data to program cannot be contained in the same 128-bit Flash memory row] + _W1C: + Clear: [1, Clear error flag] + WRPERR: + _read: + Inactive: [0, No error] + Active: [1, The address to be erased/programmed belongs to a write-protected part of the Flash memory] + _W1C: + Clear: [1, Clear error flag] + OPERR: + _read: + Inactive: [0, No error] + Active: [1, A Flash operation request is detected and cannot be run because of parallelism, alignment, sequence or write protection error] + _W1C: + Clear: [1, Clear error flag] + EOP: + _read: + Inactive: [0, No error] + Active: [1, One or more Flash operations has/have completed successfully] + _W1C: + Clear: [1, Clear error flag] diff --git a/devices/fields/flash/sr/erserr.yaml b/devices/fields/flash/sr/erserr.yaml new file mode 100644 index 000000000..57111216a --- /dev/null +++ b/devices/fields/flash/sr/erserr.yaml @@ -0,0 +1,7 @@ +SR: + ERSERR: + _read: + Inactive: [0, No error] + Active: [1, A write access to the Flash memory is performed by the code while the control register has not been correctly configured] + _W1C: + Clear: [1, Clear error flag] diff --git a/devices/fields/flash/sr/pgserr.yaml b/devices/fields/flash/sr/pgserr.yaml new file mode 100644 index 000000000..3363e3cd5 --- /dev/null +++ b/devices/fields/flash/sr/pgserr.yaml @@ -0,0 +1,7 @@ +SR: + PGSERR: + _read: + Inactive: [0, No error] + Active: [1, A write access to the Flash memory is performed by the code while the control register has not been correctly configured] + _W1C: + Clear: [1, Clear error flag] diff --git a/devices/fields/flash/sr/rderr.yaml b/devices/fields/flash/sr/rderr.yaml new file mode 100644 index 000000000..9dbed6398 --- /dev/null +++ b/devices/fields/flash/sr/rderr.yaml @@ -0,0 +1,7 @@ +SR: + RDERR: + _read: + Inactive: [0, No error] + Active: [1, A read access through the D-bus is performed to an address belonging to a proprietary readout protected Flash sector] + _W1C: + Clear: [1, Clear error flag] diff --git a/devices/fields/fsmc/bcr1.yaml b/devices/fields/fsmc/bcr1.yaml new file mode 100644 index 000000000..d93439005 --- /dev/null +++ b/devices/fields/fsmc/bcr1.yaml @@ -0,0 +1,16 @@ +BCR1: + "?~FMCEN": + Disabled: [0, Disable the FMC controller] + Enabled: [1, Enable the FMC controller] + "?~BMAP": + Default: [0, Default mapping] + Swapped: [1, NOR/PSRAM bank and SDRAM bank 1/bank2 are swapped] + Remapped: [2, SDRAM Bank2 remapped on FMC bank2 and still accessible at default mapping] + WFDIS: + Enabled: [0, Write FIFO enabled] + Disabled: [1, Write FIFO disabled] + CCLKEN: + Disabled: + - 0 + - The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set + Enabled: [1, The FMC_CLK is only generated during the synchronous memory access (read/write transaction)] diff --git a/devices/fields/fsmc/nand.yaml b/devices/fields/fsmc/nand.yaml new file mode 100644 index 000000000..2895e3436 --- /dev/null +++ b/devices/fields/fsmc/nand.yaml @@ -0,0 +1,68 @@ +"PCR,PCR?": + ECCPS: + Bytes256: [0, ECC page size 256 bytes] + Bytes512: [1, ECC page size 512 bytes] + Bytes1024: [2, ECC page size 1024 bytes] + Bytes2048: [3, ECC page size 2048 bytes] + Bytes4096: [4, ECC page size 4096 bytes] + Bytes8192: [5, ECC page size 8192 bytes] + TAR: [0, 15] + TCLR: [0, 15] + ECCEN: + Disabled: [0, ECC logic is disabled and reset] + Enabled: [1, ECC logic is enabled] + PWID: + Bits8: [0, External memory device width 8 bits] + Bits16: [1, External memory device width 16 bits] + "?~PTYP": + NANDFlash: [1, NAND Flash] + PBKEN: + Disabled: [0, Corresponding memory bank is disabled] + Enabled: [1, Corresponding memory bank is enabled] + PWAITEN: + Disabled: [0, Wait feature disabled] + Enabled: [1, Wait feature enabled] + +"SR,SR?": + FEMPT: + NotEmpty: [0, FIFO not empty] + Empty: [1, FIFO empty] + IFEN: + Disabled: [0, Interrupt falling edge detection request disabled] + Enabled: [1, Interrupt falling edge detection request enabled] + ILEN: + Disabled: [0, Interrupt high-level detection request disabled] + Enabled: [1, Interrupt high-level detection request enabled] + IREN: + Disabled: [0, Interrupt rising edge detection request disabled] + Enabled: [1, Interrupt rising edge detection request enabled] + IFS: + DidNotOccur: [0, Interrupt falling edge did not occur] + Occurred: [1, Interrupt falling edge occurred] + ILS: + DidNotOccur: [0, Interrupt high-level did not occur] + Occurred: [1, Interrupt high-level occurred] + IRS: + DidNotOccur: [0, Interrupt rising edge did not occur] + Occurred: [1, Interrupt rising edge occurred] + +"PMEM,PMEM?": + MEMHIZ: [0, 254] + MEMHOLD: [1, 254] + MEMWAIT: [1, 254] + MEMSET: [0, 254] + +"PATT,PATT?": + ATTHIZ: [0, 254] + ATTHOLD: [1, 254] + ATTWAIT: [1, 254] + ATTSET: [0, 254] + +"ECCR,ECCR?": + ECC: [0, 0xFFFFFFFF] + +"?~PIO?": + IOHIZ: [0, 255] + IOHOLD: [1, 255] + IOWAIT: [1, 255] + IOSET: [0, 255] diff --git a/devices/fields/fsmc/sd.yaml b/devices/fields/fsmc/sd.yaml new file mode 100644 index 000000000..be1d03fb8 --- /dev/null +++ b/devices/fields/fsmc/sd.yaml @@ -0,0 +1,81 @@ +# FMC as used in STM32F7 + +SDCR?: + "?~RPIPE": + NoDelay: [0, No clock cycle delay] + Clocks1: [1, One clock cycle delay] + Clocks2: [2, Two clock cycles delay] + "?~RBURST": + Disabled: [0, Single read requests are not managed as bursts] + Enabled: [1, Single read requests are always managed as bursts] + "SDCLK,CLK": + Disabled: [0, SDCLK clock disabled] + Div2: [2, "SDCLK period = 2 x HCLK period"] + Div3: [3, "SDCLK period = 3 x HCLK period"] + WP: + Disabled: [0, Write accesses allowed] + Enabled: [1, Write accesses ignored] + CAS: + Clocks1: [1, 1 cycle] + Clocks2: [2, 2 cycles] + Clocks3: [3, 3 cycles] + NB: + NB2: [0, Two internal Banks] + NB4: [1, Four internal Banks] + MWID: + Bits8: [0, Memory data bus width 8 bits] + Bits16: [1, Memory data bus width 16 bits] + Bits32: [2, Memory data bus width 32 bits] + NR: + Bits11: [0, 11 bits] + Bits12: [1, 12 bits] + Bits13: [2, 13 bits] + NC: + Bits8: [0, 8 bits] + Bits9: [1, 9 bits] + Bits10: [2, 10 bits] + Bits11: [3, 11 bits] + +SDTR?: + TRCD: [0, 15] + TRP: [0, 15] + TWR: [0, 15] + TRC: [0, 15] + TRAS: [0, 15] + TXSR: [0, 15] + TMRD: [0, 15] + +SDCMR: + MRD: [0, 8191] + NRFS: [0, 15] + CTB?: + NotIssued: [0, Command not issued to SDRAM Bank 1] + Issued: [1, Command issued to SDRAM Bank 1] + MODE: + Normal: [0, Normal Mode] + ClockConfigurationEnable: [1, Clock Configuration Enable] + PALL: [2, PALL (All Bank Precharge) command] + AutoRefreshCommand: [3, Auto-refresh command] + LoadModeRegister: [4, Load Mode Resgier] + SelfRefreshCommand: [5, Self-refresh command] + PowerDownCommand: [6, Power-down command] + +SDRTR: + REIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated if RE = 1"] + COUNT: [0, 8191] + CRE: + Clear: [1, Refresh Error Flag is cleared] + +SDSR: + "?~BUSY": + NotBusy: [0, SDRAM Controller is ready to accept a new request] + Busy: [1, SDRAM Controller is not ready to accept a new request] + MODES?: + Normal: [0, Normal Mode] + SelfRefresh: [1, Self-refresh mode] + PowerDown: [2, Power-down mode] + RE: + NoError: [0, No refresh error has been detected] + Error: [1, A refresh error has been detected] diff --git a/devices/fields/fsmc/sram.yaml b/devices/fields/fsmc/sram.yaml new file mode 100644 index 000000000..873d3e410 --- /dev/null +++ b/devices/fields/fsmc/sram.yaml @@ -0,0 +1,76 @@ +BCR?: + CBURSTRW: + Enabled: [1, Write operations are performed in synchronous mode] + Disabled: [0, Write operations are always performed in asynchronous mode] + "?~CPSIZE": + NoBurstSplit: [0, No burst split when crossing page boundary] + Bytes128: [1, 128 bytes CRAM page size] + Bytes256: [2, 256 bytes CRAM page size] + Bytes512: [3, 512 bytes CRAM page size] + Bytes1024: [4, 1024 bytes CRAM page size] + ASYNCWAIT: + Disabled: [0, Wait signal not used in asynchronous mode] + Enabled: [1, Wait signal used even in asynchronous mode] + EXTMOD: + Disabled: [0, Values inside the FMC_BWTR are not taken into account] + Enabled: [1, Values inside the FMC_BWTR are taken into account] + WAITEN: + Disabled: [0, Values inside the FMC_BWTR are taken into account] + Enabled: [1, NWAIT signal enabled] + WREN: + Disabled: [0, Write operations disabled for the bank by the FMC] + Enabled: [1, Write operations enabled for the bank by the FMC] + WAITCFG: + BeforeWaitState: [0, NWAIT signal is active one data cycle before wait state] + DuringWaitState: [1, NWAIT signal is active during wait state] + "?~WRAPMOD": + Disabled: [0, Direct wrapped burst is not enabled] + Enabled: [1, Direct wrapped burst is enabled] + WAITPOL: + ActiveLow: [0, NWAIT active low] + ActiveHigh: [1, NWAIT active high] + BURSTEN: + Disabled: [0, Burst mode disabled] + Enabled: [1, Burst mode enabled] + FACCEN: + Disabled: [0, Corresponding NOR Flash memory access is disabled] + Enabled: [1, Corresponding NOR Flash memory access is enabled] + # TODO: fix + MWID: + Bits8: [0, Memory data bus width 8 bits] + Bits16: [1, Memory data bus width 16 bits] + Bits32: [2, Memory data bus width 32 bits] + MTYP: + SRAM: [0, SRAM memory type] + PSRAM: [1, PSRAM (CRAM) memory type] + Flash: [2, NOR Flash/OneNAND Flash] + MUXEN: + Disabled: [0, Address/Data non-multiplexed] + Enabled: [1, Address/Data multiplexed on databus] + MBKEN: + Disabled: [0, Corresponding memory bank is disabled] + Enabled: [1, Corresponding memory bank is enabled] + +BTR?: + ACCMOD: + A: [0, Access mode A] + B: [1, Access mode B] + C: [2, Access mode C] + D: [3, Access mode D] + DATLAT: [0, 15] + CLKDIV: [1, 15] + BUSTURN: [0, 15] + DATAST: [1, 255] + ADDHLD: [1, 15] + ADDSET: [0, 15] + +BWTR?: + ACCMOD: + A: [0, Access mode A] + B: [1, Access mode B] + C: [2, Access mode C] + D: [3, Access mode D] + BUSTURN: [0, 15] + DATAST: [1, 255] + ADDHLD: [1, 15] + ADDSET: [0, 15] diff --git a/devices/fields/fw/fw_l0_l4.yaml b/devices/fields/fw/fw_l0_l4.yaml new file mode 100644 index 000000000..545dd4f96 --- /dev/null +++ b/devices/fields/fw/fw_l0_l4.yaml @@ -0,0 +1,36 @@ +# This FW is used on the STM32L0/L4 families. + +CSSA: + ADD: [0, 0xFFFF] +CSL: + LENG: [0, 0x3FFF] +NVDSSA: + ADD: [0, 0xFFFF] +NVDSL: + LENG: [0, 0x3FFF] +VDSSA: + ADD: [0, 0x3FF] +VDSL: + LENG: [0, 0x3FF] +CR: + VDE: + _write: + Reset: [0, Resets volatile data execution bit] + _read: + NotExecutable: [0, "Volatile data segment cannot be executed if VDS = 0"] + Executable: [1, Volatile data segment is declared executable whatever VDS bit value] + VDS: + _write: + Reset: [0, Resets volatile data shared bit] + _read: + NotShared: + [ + 0, + Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed, + ] + Shared: [1, Volatile data segment is shared with non protected application code] + FPA: + _write: + PreArmReset: + [0, Any code executed outside the protected segment when the Firewall is opened will generate a system reset] + PreArmSet: [1, Any code executed outside the protected segment will close the Firewall] diff --git a/devices/fields/gpio/gpio_g0_l0.yaml b/devices/fields/gpio/gpio_g0_l0.yaml new file mode 100644 index 000000000..70ee9b1f7 --- /dev/null +++ b/devices/fields/gpio/gpio_g0_l0.yaml @@ -0,0 +1,5 @@ +# This GPIO is used on the STM32G0 and L0 families. + +_include: + - v3/common.yaml + - v3/af0-7.yaml diff --git a/devices/fields/gpio/gpio_l5_u5.yaml b/devices/fields/gpio/gpio_l5_u5.yaml new file mode 100644 index 000000000..68ffa77e2 --- /dev/null +++ b/devices/fields/gpio/gpio_l5_u5.yaml @@ -0,0 +1,16 @@ +# This GPIO is used on the STM32L5 and U5 families. + +_include: + - v3/common.yaml + - v3/af0-15.yaml + +"?~HSLVR": + HSLV*: + _name: HighSpeedLowVoltage + Disabled: [0, I/O speed optimization disabled] + Enabled: [1, I/O speed optimization enabled] +"?~SECCFGR": + SEC*: + _name: SecurePin + NonSecure: [0, The I/O pin is non-secure] + Secure: [1, The I/O pin is secure] diff --git a/devices/fields/gpio/v1/common.yaml b/devices/fields/gpio/v1/common.yaml new file mode 100644 index 000000000..9ecdccffa --- /dev/null +++ b/devices/fields/gpio/v1/common.yaml @@ -0,0 +1,49 @@ +# This GPIO is used on the STM32F1 family. + +IDR: + IDR*: + _name: InputData + High: [1, Input is logic high] + Low: [0, Input is logic low] +ODR: + ODR*: + _name: OutputData + High: [1, Set output to logic high] + Low: [0, Set output to logic low] +BSRR: + BR*: + _write: + _name: BitReset + Reset: [1, Resets the corresponding ODRx bit] + BS*: + _write: + _name: BitSet + Set: [1, Sets the corresponding ODRx bit] +BRR: + BR*: + _write: + _name: BitReset + NoAction: [0, No action on the corresponding ODx bit] + Reset: [1, Reset the ODx bit] +LCKR: + "LCK[0-9],LCK1[0-5]": + _name: Lock + Unlocked: [0, Port configuration not locked] + Locked: [1, Port configuration locked] + LCKK: + _name: LockKey + NotActive: [0, Port configuration lock key not active] + Active: [1, Port configuration lock key active] +CR[LH]: + CNF*: + _name: Config + PushPull: [0, Analog mode / Push-Pull mode] + OpenDrain: [1, Floating input (reset state) / Open Drain-Mode] + AltPushPull: [2, Input with pull-up/pull-down / Alternate Function Push-Pull Mode] + AltOpenDrain: [3, Alternate Function Open-Drain Mode] + MODE*: + _name: Mode + Input: [0, Input mode (reset state)] + Output: [1, Output mode 10 MHz] + Output2: [2, Output mode 2 MHz] + Output50: [3, Output mode 50 MHz] diff --git a/devices/fields/gpio/v2/common.yaml b/devices/fields/gpio/v2/common.yaml new file mode 100644 index 000000000..14ac43b10 --- /dev/null +++ b/devices/fields/gpio/v2/common.yaml @@ -0,0 +1,11 @@ +# This GPIO is used on the STM32F0, F4, F7 and WL families. + +_include: no_speed.yaml + +OSPEEDR: + OSPEEDR*: + _name: OutputSpeed + LowSpeed: [0, Low speed] + MediumSpeed: [1, Medium speed] + HighSpeed: [2, High speed] + VeryHighSpeed: [3, Very high speed] diff --git a/devices/fields/gpio/v2/f3.yaml b/devices/fields/gpio/v2/f3.yaml new file mode 100644 index 000000000..54033dbc7 --- /dev/null +++ b/devices/fields/gpio/v2/f3.yaml @@ -0,0 +1,18 @@ +# This GPIO is used on the STM32F3 family. + +# F3 mcus does not support very high speed mode. +# +# | value | F3 | others | +# |-------|--------|-----------| +# | 0b00 | Low | Low | +# | 0b01 | Medium | Medium | +# | 0b10 | Low | High | +# | 0b11 | High | Very high | + +_include: no_speed.yaml +OSPEEDR: + OSPEEDR*: + _name: OutputSpeed + LowSpeed: [0, Low speed] + MediumSpeed: [1, Medium speed] + HighSpeed: [3, High speed] diff --git a/devices/fields/gpio/v2/no_speed.yaml b/devices/fields/gpio/v2/no_speed.yaml new file mode 100644 index 000000000..759a95e28 --- /dev/null +++ b/devices/fields/gpio/v2/no_speed.yaml @@ -0,0 +1,89 @@ +MODER: + MODER*: + _name: Mode + Input: [0, Input mode (reset state)] + Output: [1, General purpose output mode] + Alternate: [2, Alternate function mode] + Analog: [3, Analog mode] +OTYPER: + OT*: + _name: OutputType + PushPull: [0, Output push-pull (reset state)] + OpenDrain: [1, Output open-drain] +PUPDR: + PUPDR*: + _name: Pull + Floating: [0, "No pull-up, pull-down"] + PullUp: [1, Pull-up] + PullDown: [2, Pull-down] +IDR: + IDR*: + _name: InputData + High: [1, Input is logic high] + Low: [0, Input is logic low] +ODR: + ODR*: + _name: OutputData + High: [1, Set output to logic high] + Low: [0, Set output to logic low] +BSRR: + BR*: + _write: + _name: BitReset + Reset: [1, Resets the corresponding ODRx bit] + BS*: + _write: + _name: BitSet + Set: [1, Sets the corresponding ODRx bit] +"AFR[LH]": + "?~AFR*": + _name: AlternateFunction + AF0: [0, AF0] + AF1: [1, AF1] + AF2: [2, AF2] + AF3: [3, AF3] + AF4: [4, AF4] + AF5: [5, AF5] + AF6: [6, AF6] + AF7: [7, AF7] + AF8: [8, AF8] + AF9: [9, AF9] + AF10: [10, AF10] + AF11: [11, AF11] + AF12: [12, AF12] + AF13: [13, AF13] + AF14: [14, AF14] + AF15: [15, AF15] + "?~AFRSEL*": + _name: AlternateFunction + AF0: [0, AF0] + AF1: [1, AF1] + AF2: [2, AF2] + AF3: [3, AF3] + AF4: [4, AF4] + AF5: [5, AF5] + AF6: [6, AF6] + AF7: [7, AF7] + AF8: [8, AF8] + AF9: [9, AF9] + AF10: [10, AF10] + AF11: [11, AF11] + AF12: [12, AF12] + AF13: [13, AF13] + AF14: [14, AF14] + AF15: [15, AF15] +"?~BRR": + BR*: + _write: + _name: BitReset + NoAction: [0, No action on the corresponding ODx bit] + Reset: [1, Reset the ODx bit] +"?~LCKR": + "LCK[0-9],LCK1[0-5]": + _name: Lock + Unlocked: [0, Port configuration not locked] + Locked: [1, Port configuration locked] + LCKK: + _name: LockKey + NotActive: [0, Port configuration lock key not active] + Active: [1, Port configuration lock key active] diff --git a/devices/fields/gpio/v3/af0-15.yaml b/devices/fields/gpio/v3/af0-15.yaml new file mode 100644 index 000000000..31badfe6f --- /dev/null +++ b/devices/fields/gpio/v3/af0-15.yaml @@ -0,0 +1,19 @@ +"AFR[LH]": + AFSEL*: + _name: AlternateFunction + AF0: [0, AF0] + AF1: [1, AF1] + AF2: [2, AF2] + AF3: [3, AF3] + AF4: [4, AF4] + AF5: [5, AF5] + AF6: [6, AF6] + AF7: [7, AF7] + AF8: [8, AF8] + AF9: [9, AF9] + AF10: [10, AF10] + AF11: [11, AF11] + AF12: [12, AF12] + AF13: [13, AF13] + AF14: [14, AF14] + AF15: [15, AF15] diff --git a/devices/fields/gpio/v3/af0-7.yaml b/devices/fields/gpio/v3/af0-7.yaml new file mode 100644 index 000000000..d26787235 --- /dev/null +++ b/devices/fields/gpio/v3/af0-7.yaml @@ -0,0 +1,11 @@ +"AFR[LH]": + AFSEL*: + _name: AlternateFunction + AF0: [0, AF0] + AF1: [1, AF1] + AF2: [2, AF2] + AF3: [3, AF3] + AF4: [4, AF4] + AF5: [5, AF5] + AF6: [6, AF6] + AF7: [7, AF7] diff --git a/devices/fields/gpio/v3/common.yaml b/devices/fields/gpio/v3/common.yaml new file mode 100644 index 000000000..b1cdfca79 --- /dev/null +++ b/devices/fields/gpio/v3/common.yaml @@ -0,0 +1,61 @@ +# This GPIO is used on the STM32G0, L0, L5, H5 and U5 families. + +MODER: + MODE*: + _name: Mode + Input: [0, Input mode] + Output: [1, General purpose output mode] + Alternate: [2, Alternate function mode] + Analog: [3, Analog mode] +OTYPER: + OT*: + _name: OutputType + PushPull: [0, Output push-pull (reset state)] + OpenDrain: [1, Output open-drain] +OSPEEDR: + OSPEED*: + _name: OutputSpeed + LowSpeed: [0, Low speed] + MediumSpeed: [1, Medium speed] + HighSpeed: [2, High speed] + VeryHighSpeed: [3, Very high speed] +PUPDR: + PUPD*: + _name: Pull + Floating: [0, "No pull-up, pull-down"] + PullUp: [1, Pull-up] + PullDown: [2, Pull-down] +IDR: + ID*: + _name: InputData + High: [1, Input is logic high] + Low: [0, Input is logic low] +ODR: + OD*: + _name: OutputData + High: [1, Set output to logic high] + Low: [0, Set output to logic low] +"?~BRR": + BR*: + _write: + _name: BitReset + NoAction: [0, No action on the corresponding ODx bit] + Reset: [1, Reset the ODx bit] +BSRR: + BR*: + _write: + _name: BitReset + Reset: [1, Resets the corresponding ODx bit] + BS*: + _write: + _name: BitSet + Set: [1, Sets the corresponding ODx bit] +LCKR: + "LCK[0-9],LCK1[0-5]": + _name: Lock + Unlocked: [0, Port configuration not locked] + Locked: [1, Port configuration locked] + LCKK: + _name: LockKey + NotActive: [0, Port configuration lock key not active] + Active: [1, Port configuration lock key active] diff --git a/devices/fields/hdmi_cec.yaml b/devices/fields/hdmi_cec.yaml new file mode 100644 index 000000000..048424a9b --- /dev/null +++ b/devices/fields/hdmi_cec.yaml @@ -0,0 +1,5 @@ +CFGR: + OAR: [0, 0x7FFF] + SFT: [0, 0x7] +TXDR: + TXD: [0, 0xFF] diff --git a/devices/fields/hrtim/common.yaml b/devices/fields/hrtim/common.yaml new file mode 100644 index 000000000..5a82f7892 --- /dev/null +++ b/devices/fields/hrtim/common.yaml @@ -0,0 +1,250 @@ +CR1: + "T?UDIS,MUDIS": + Enabled: [0, Timer update enabled] + Disabled: [1, Timer update disabled] +CR2: + "T?RST,MRST": + Reset: [1, Reset timer] + "T?SWU,MSWU": + Update: [1, Force immediate update] +ISR: + BMPER: + _read: + NoEvent: [0, No burst mode period interrupt occurred] + Event: [1, Burst mode period interrupt occured] + "?~DLLRDY": + _read: + NoEvent: [0, No DLL calibration ready interrupt occurred] + Event: [1, DLL calibration ready interrupt occurred] + SYSFLT: + _read: + NoEvent: [0, No fault interrupt occurred] + Event: [1, Fault interrupt occurred] + "FLT[1-6]": + _read: + NoEvent: [0, No fault interrupt occurred] + Event: [1, Fault interrupt occurred] +ICR: + "*C": + _W1C: + Clear: [1, Clears associated flag in ISR register] +IER: + BMPERIE: + Disabled: [0, Burst mode period interrupt disabled] + Enabled: [1, Burst mode period interrupt enabled] + "?~DLLRDYIE": + Disabled: [0, DLL ready interrupt disabled] + Enabled: [1, DLL Ready interrupt enabled] + "SYSFLTIE,FLT?IE": + Disabled: [0, Fault interrupt disabled] + Enabled: [1, Fault interrupt enabled] +OENR: + "T[A-F][12]OEN": + _read: + _name: TOENR + Disabled: [0, Output disabled] + Enabled: [1, Output enabled] + _W1S: + _name: TORNW + Enable: [1, Enable output] +ODISR: + "T[A-F][12]ODIS": + _W1S: + _name: TODIS + Disable: [1, Disable output] +ODSR: + "T[A-F][12]ODS": + _name: TODS + Idle: [0, Output disabled in idle state] + Fault: [1, Output disabled in fault state] +BMCR: + BMSTAT: + _read: + Normal: [0, Normal operation] + Burst: [1, Burst operation ongoing] + _W0C: + Cancel: [0, Terminate burst mode] + "T[A-F]BM,MTBM": + Normal: [0, Counter clock is maintained and timer operates normally] + Stopped: [1, Counter clock is stopped and counter is reset] + BMPREN: + Disabled: [0, "Preload disabled: the write access is directly done into active registers"] + Enabled: [1, "Preload enabled: the write access is done into preload registers"] + BMPRSC: + Div1: [0, Clock not divided] + Div2: [1, Division by 2] + Div4: [2, Division by 4] + Div8: [3, Division by 8] + Div16: [4, Division by 16] + Div32: [5, Division by 32] + Div64: [6, Division by 64] + Div128: [7, Division by 128] + Div256: [8, Division by 256] + Div512: [9, Division by 512] + Div1024: [10, Division by 1024] + Div2048: [11, Division by 2048] + Div4096: [12, Division by 4096] + Div8192: [13, Division by 8192] + Div16384: [14, Division by 16384] + Div32768: [15, Division by 32768] + BMCLK: + Master: [0, Master timer reset/roll-over] + TimerA: [1, Timer A counter reset/roll-over] + TimerB: [2, Timer B counter reset/roll-over] + TimerC: [3, Timer C counter reset/roll-over] + TimerD: [4, Timer D counter reset/roll-over] + TimerE: [5, Timer E counter reset/roll-over] + Event1: [6, "On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock"] + Event2: [7, "On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock"] + Event3: [8, "On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock"] + Event4: [9, "On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock"] + Clock: [10, "Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting"] + BMOM: + SingleShot: [0, Single-shot mode] + Continuous: [1, Continuous operation] + BME: + Disabled: [0, Burst mode disabled] + Enabled: [1, Burst mode enabled] +BMTRGR: + OCHPEV: + NoEffect: [0, Rising edge on an on-chip event has no effect] + Trigger: [1, Rising edge on an on-chip event triggers a burst mode entry] + "T[A-F]CMP[12]": + NoEffect: [0, Timer X compare Y event has no effect] + Trigger: [1, Timer X compare Y event triggers a burst mode entry] + "T[A-F]REP": + NoEffect: [0, Timer X repetition event has no effect] + Trigger: [1, Timer X repetition event triggers a burst mode entry] + "T[A-F]RST": + NoEffect: [0, Timer X reset/roll-over event has no effect] + Trigger: [1, Timer X reset/roll-over event triggers a burst mode entry] + "MSTCMP[1-4]": + NoEffect: [0, Master timer compare X event has no effect] + Trigger: [1, Master timer compare X event triggers a burst mode entry] + MSTREP: + NoEffect: [0, Master timer repetition event has no effect] + Trigger: [1, Master timer repetition event triggers a burst mode entry] + MSTRST: + NoEffect: [0, Master timer reset/roll-over event has no effect] + Trigger: [1, Master timer reset/roll-over event triggers a burst mode entry] + SW: + NoEffect: [0, No effect] + Trigger: [1, Trigger immediate burst mode operation] +BMCMPR: + BMCMP: [0, 0xFFFF] +BMPER: + BMPER: [0, 0xFFFF] +EECR1: + EE*FAST: + Resynchronized: [0, External event is re-synchronised by the HRTIM logic before acting on outputs] + Asynchronous: [1, External event is acting asynchronously on outputs (low-latency mode)] +"EECR[12]": + EE*SNS: + Active: [0, On active level defined by EExPOL bit] + Rising: [1, Rising edge] + Falling: [2, Falling edge] + Both: [3, Both edges] + EE*POL: + ActiveHigh: [0, External event is active high] + ActiveLow: [1, External event is active low] + EE*SRC: + Src1: [0, Source 1] + Src2: [1, Source 2] + Src3: [2, Source 3] + Src4: [3, Source 4] +EECR3: + EEVSD: + Div1: [0, "f_EEVS=f_HRTIM"] + Div2: [1, "f_EEVS=f_HRTIM/2"] + Div4: [2, "f_EEVS=f_HRTIM/4"] + Div8: [3, "f_EEVS=f_HRTIM/8"] + EE*F: + Disabled: [0, Filter disabled] + Div1_N2: [1, "f_SAMPLING=f_HRTIM, N=2"] + Div1_N4: [2, "f_SAMPLING=f_HRTIM, N=4"] + Div1_N8: [3, "f_SAMPLING=f_HRTIM, N=8"] + Div2_N6: [4, "f_SAMPLING=f_EEVS/2, N=6"] + Div2_N8: [5, "f_SAMPLING=f_EEVS/2, N=8"] + Div4_N6: [6, "f_SAMPLING=f_EEVS/4, N=6"] + Div4_N8: [7, "f_SAMPLING=f_EEVS/4, N=8"] + Div8_N6: [8, "f_SAMPLING=f_EEVS/8, N=6"] + Div8_N8: [9, "f_SAMPLING=f_EEVS/8, N=8"] + Div16_N5: [10, "f_SAMPLING=f_EEVS/16, N=5"] + Div16_N6: [11, "f_SAMPLING=f_EEVS/16, N=6"] + Div16_N8: [12, "f_SAMPLING=f_EEVS/16, N=8"] + Div32_N5: [13, "f_SAMPLING=f_EEVS/32, N=5"] + Div32_N6: [14, "f_SAMPLING=f_EEVS/32, N=6"] + Div32_N8: [15, "f_SAMPLING=f_EEVS/32, N=8"] +"ADC[1234]R": + "*RST": + Disabled: [0, No generation of ADC trigger on timer reset and roll-over] + Enabled: [1, Generation of ADC trigger on timer reset and roll-over] + "*PER": + Disabled: [0, No generation of ADC trigger on timer period event] + Enabled: [1, Generation of ADC trigger on timer period event] + "[A-F]C[234]": + Disabled: [0, No generation of ADC trigger on timer compare event] + Enabled: [1, Generation of ADC trigger on timer compare event] + EEV*: + Disabled: [0, No generation of ADC trigger on external event] + Enabled: [1, Generation of ADC trigger on external event] + MC*: + Disabled: [0, No generation of ADC trigger on master compare event] + Enabled: [1, Generation of ADC trigger on master compare event] +"?~DLLCR": + CALRTE: + Clk1048576: [0, 1048576*t_HRTIM (6.168 ms for fHRTIM = 170 MHz)] + Clk131072: [1, 131072*t_HRTIM (771 µs for f_HRTIM = 170 MHz)] + Clk16384: [2, 16384*t_HRTIM (96 µs for f_HRTIM = 170 MHz)] + Clk2048: [3, 2048*t_HRTIM (12 µs for f_HRTIM = 170 MHz)] + CALEN: + Disabled: [0, Periodic calibration disabled] + Enabled: [1, "Calibration is performed periodically, as per CALRTE setting"] + CAL: + Start: [1, Calibration start] +"FLTINR[12]": + "FLT[123456]LCK": + _read: + Unlocked: [0, Fault bits are read/write] + Locked: [1, Fault bits are read-only] + _write: + Lock: [1, Lock corresponding fault bits] + "FLT[123456]F": + Disabled: [0, "No filter, FLTx acts asynchronously"] + Div1_N2: [1, "f_SAMPLING=f_HRTIM, N=2"] + Div1_N4: [2, "f_SAMPLING=f_HRTIM, N=4"] + Div1_N8: [3, "f_SAMPLING=f_HRTIM, N=8"] + Div2_N6: [4, "f_SAMPLING=f_HRTIM/2, N=6"] + Div2_N8: [5, "f_SAMPLING=f_HRTIM/2, N=8"] + Div4_N6: [6, "f_SAMPLING=f_HRTIM/4, N=6"] + Div4_N8: [7, "f_SAMPLING=f_HRTIM/4, N=8"] + Div8_N6: [8, "f_SAMPLING=f_HRTIM/8, N=6"] + Div8_N8: [9, "f_SAMPLING=f_HRTIM/8, N=8"] + Div16_N5: [10, "f_SAMPLING=f_HRTIM/16, N=5"] + Div16_N6: [11, "f_SAMPLING=f_HRTIM/16, N=6"] + Div16_N8: [12, "f_SAMPLING=f_HRTIM/16, N=8"] + Div32_N5: [13, "f_SAMPLING=f_HRTIM/32, N=5"] + Div32_N6: [14, "f_SAMPLING=f_HRTIM/32, N=6"] + Div32_N8: [15, "f_SAMPLING=f_HRTIM/32, N=8"] + "FLT[123456]P": + ActiveLow: [0, Fault input is active low] + ActiveHigh: [1, Fault input is active high] + "FLT[123456]E": + Disabled: [0, Fault input disabled] + Enabled: [1, Fault input enabled] +FLTINR2: + FLTSD: + Div1: [0, "f_FLTS=f_HRTIM"] + Div2: [1, "f_FLTS=f_HRTIM/2"] + Div4: [2, "f_FLTS=f_HRTIM/4"] + Div8: [3, "f_FLTS=f_HRTIM/8"] +BDMUPR: + M*: + NotUpdated: [0, Register not updated by burst DMA access] + Updated: [1, Register updated by burst DMA access] +"BDT[A-F]UPR": + "*": + NotUpdated: [0, Register not updated by burst DMA access] + Updated: [1, Register updated by burst DMA access] +BDMADR: + BDMADR: [0, 0xFFFFFFFF] diff --git a/devices/fields/hrtim/common_f3.yaml b/devices/fields/hrtim/common_f3.yaml new file mode 100644 index 000000000..c2b493e73 --- /dev/null +++ b/devices/fields/hrtim/common_f3.yaml @@ -0,0 +1,9 @@ +HRTIM_Common: + _include: common_v1.yaml + BMTRGR: + "EEV[78]": + NoEffect: [0, External event X has no effect] + Trigger: [1, External event X triggers a burst mode entry] + "TDEEV8,TAEEV7": + NoEffect: [0, Timer X period following external event Y has no effect] + Trigger: [1, Timer X period following external event Y triggers a burst mode entry] diff --git a/devices/fields/hrtim/common_h7.yaml b/devices/fields/hrtim/common_h7.yaml new file mode 100644 index 000000000..320e3e30b --- /dev/null +++ b/devices/fields/hrtim/common_h7.yaml @@ -0,0 +1,2 @@ +HRTIM_Common: + _include: common_v1.yaml diff --git a/devices/fields/hrtim/common_v1.yaml b/devices/fields/hrtim/common_v1.yaml new file mode 100644 index 000000000..b41dd8ff4 --- /dev/null +++ b/devices/fields/hrtim/common_v1.yaml @@ -0,0 +1,13 @@ +_include: common.yaml +CR1: + AD?USRC: + Master: [0, ADC trigger update from master timer] + TimerA: [1, ADC trigger update from timer A] + TimerB: [2, ADC trigger update from timer B] + TimerC: [3, ADC trigger update from timer C] + TimerD: [4, ADC trigger update from timer D] + TimerE: [5, ADC trigger update from timer E] +"FLTINR[12]": + "FLT[1-6]SRC": + Input: [0, Fault input is FLTx input pin] + Internal: [1, Fault input is FLTn_Int signal] diff --git a/devices/fields/hrtim/common_v2.yaml b/devices/fields/hrtim/common_v2.yaml new file mode 100644 index 000000000..c3e45bc63 --- /dev/null +++ b/devices/fields/hrtim/common_v2.yaml @@ -0,0 +1,39 @@ +HRTIM_Common: + _include: common.yaml + CR1: + AD?USRC: + Master: [0, ADC trigger update from master timer] + TimerA: [1, ADC trigger update from timer A] + TimerB: [2, ADC trigger update from timer B] + TimerC: [3, ADC trigger update from timer C] + TimerD: [4, ADC trigger update from timer D] + TimerE: [5, ADC trigger update from timer E] + TimerF: [6, ADC trigger update from timer F] + "FLTINR[12]": + "FLT[1-6]SRC": + Input: [0, Fault input is FLTx input pin] + CompOutput: [1, Fault input is connected to a COMPx output] + FLTINR2: + "FLT[1-6]SRC_1": + Default: [0, As described in FLTxSRC] + Eev: [1, "Fault input is EEV5_muxout input pin (when FLTxSRC == 0) / reserved"] + BMTRGR: + "EEV[78]": + NoEffect: [0, External event X has no effect] + Trigger: [1, External event X triggers a burst mode entry] + "TDEEV8,TAEEV7": + NoEffect: [0, Timer X period following external event Y has no effect] + Trigger: [1, Timer X period following external event Y triggers a burst mode entry] + OENR: + TF1OEN: + _read: + Disabled: [0, Output disabled] + Enabled: [1, Output enabled] + _write: + Enable: [1, Enable output] + TF2OEN: + _read: + Disabled: [0, Output disabled] + Enabled: [1, Output enabled] + _write: + Enable: [1, Enable output] diff --git a/devices/fields/hrtim/hrtim.yaml b/devices/fields/hrtim/hrtim.yaml new file mode 100644 index 000000000..e865a801a --- /dev/null +++ b/devices/fields/hrtim/hrtim.yaml @@ -0,0 +1,415 @@ +# HRTIM as found on STM32F3x4 and STM32H7 + +HRTIM_Master: + CR: + BRSTDMA: + Independent: [0, Update done independently from the DMA burst transfer completion] + Completion: [1, Update done when the DMA burst transfer is completed] + Rollover: [2, Update done on master timer roll-over following a DMA burst transfer completion] + MREPU: + Disabled: [0, Update on repetition disabled] + Enabled: [1, Update on repetition enabled] + PREEN: + Disabled: [0, "Preload disabled: the write access is directly done into the active register"] + Enabled: [1, "Preload enabled: the write access is done into the preload register"] + DACSYNC: + Disabled: [0, No DAC trigger generated] + DACSync1: [1, Trigger generated on DACSync1] + DACSync2: [2, Trigger generated on DACSync2] + DACSync3: [3, Trigger generated on DACSync3] + "T[A-F]CEN": + Disabled: [0, Timer counter disabled] + Enabled: [1, Timer counter enabled] + MCEN: + Disabled: [0, Master timer counter disabled] + Enabled: [1, Master timer counter enabled] + SYNCSRC: + MasterStart: [0, Master timer Start] + MasterCompare1: [1, Master timer Compare 1 event] + TimerAStart: [2, Timer A start/reset] + TimerACompare1: [3, Timer A Compare 1 event] + SYNCOUT: + Disabled: [0, Disabled] + PositivePulse: [2, Positive pulse on SCOUT output (16x f_HRTIM clock cycles)] + NegativePulse: [3, Negative pulse on SCOUT output (16x f_HRTIM clock cycles)] + SYNCSTRT: + Disabled: [0, No effect on the master timer] + Start: [1, A synchroniation input event starts the master timer] + SYNCRST: + Disabled: [0, No effect on the master timer] + Reset: [1, A synchroniation input event resets the master timer] + SYNCIN: + Disabled: [0, Disabled. HRTIM is not synchronized and runs in standalone mode] + Internal: [2, "Internal event: the HRTIM is synchronized with the on-chip timer"] + External: [3, "External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM"] + HALF: + Disabled: [0, Half mode disabled] + Enabled: [1, Half mode enabled] + RETRIG: + Disabled: [0, "The timer is not re-triggerable: a counter reset can be done only if the counter is stopped"] + Enabled: [1, "The timer is retriggerable: a counter reset is done whatever the counter state"] + CONT: + SingleShot: [0, The timer operates in single-shot mode and stops when it reaches the MPER value] + Continuous: + [1, The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value] + CKPSC: [0, 7] + ISR: + UPD: + NoEvent: [0, No timer update interrupt occurred] + Event: [1, Timer update interrupt occurred] + SYNC: + NoEvent: [0, No sync input interrupt occurred] + Event: [1, Sync input interrupt occurred] + REP: + NoEvent: [0, No timer repetition interrupt occurred] + Event: [1, Timer repetition interrupt occurred] + "CMP[1-4]": + NoEvent: [0, No compare interrupt occurred] + Event: [1, Compare interrupt occurred] + ICR: + "*C": + _W1C: + Clear: [1, Clears associated flag in ISR register] + DIER: + "*DE": + Disabled: [0, DMA request disabled] + Enabled: [1, DMA request enabled] + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + CNTR: + CNT: [0, 0xFFFF] + PERR: + PER: [0, 0xFFFF] + REPR: + REP: [0, 0xFF] + "CMP[1-4]R": + CMP: [0, 0xFFFF] + +"HRTIM_TIM[A-F]": + CR: + UPDGAT: + Independent: [0, Update occurs independently from the DMA burst transfer] + DMABurst: [1, Update occurs when the DMA burst transfer is completed] + DMABurst_Update: [2, Update occurs on the update event following DMA burst transfer completion] + Input1: [3, Update occurs on a rising edge of HRTIM update enable input 1] + Input2: [4, Update occurs on a rising edge of HRTIM update enable input 2] + Input3: [5, Update occurs on a rising edge of HRTIM update enable input 3] + Input1_Update: [6, Update occurs on the update event following a rising edge of HRTIM update enable input 1] + Input2_Update: [7, Update occurs on the update event following a rising edge of HRTIM update enable input 2] + Input3_Update: [8, Update occurs on the update event following a rising edge of HRTIM update enable input 3] + PREEN: + Disabled: [0, "Preload disabled: the write access is directly done into the active register"] + Enabled: [1, "Preload enabled: the write access is done into the preload register"] + DACSYNC: + Disabled: [0, No DAC trigger generated] + DACSync1: [1, Trigger generated on DACSync1] + DACSync2: [2, Trigger generated on DACSync2] + DACSync3: [3, Trigger generated on DACSync3] + MSTU: + Disabled: [0, Update by master timer disabled] + Enabled: [1, Update by master timer enabled] + "T[A-F]U": + Disabled: [0, Update by timer x disabled] + Enabled: [1, Update by timer x enabled] + TRSTU: + Disabled: [0, Update by timer x reset/roll-over disabled] + Enabled: [1, Update by timer x reset/roll-over enabled] + TREPU: + Disabled: [0, Update by timer x repetition disabled] + Enabled: [1, Update by timer x repetition enabled] + DELCMP4: + Standard: [0, CMP4 register is always active (standard compare mode)] + Capture2: [1, CMP4 is recomputed and is active following a capture 2 event] + Capture2_Compare1: [2, CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match] + Capture_Compare3: [3, CMP4 is recomputed and is active following a capture event or a Compare 3 match] + DELCMP2: + Standard: [0, CMP2 register is always active (standard compare mode)] + Capture1: [1, CMP2 is recomputed and is active following a capture 1 event] + Capture1_Compare1: [2, CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match] + Capture1_Compare3: [3, CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match] + SYNCSTRT: + Disabled: [0, Synchronization event has no effect on Timer x] + Start: [1, Synchronization event starts Timer x] + SYNCRST: + Disabled: [0, Synchronization event has no effect on Timer x] + Reset: [1, Synchronization event resets Timer x] + PSHPLL: + Disabled: [0, Push-pull mode disabled] + Enabled: [1, Push-pull mode enabled] + HALF: + Disabled: [0, Half mode disabled] + Enabled: [1, Half mode enabled] + RETRIG: + Disabled: [0, "The timer is not re-triggerable: a counter reset can be done only if the counter is stopped"] + Enabled: [1, "The timer is retriggerable: a counter reset is done whatever the counter state"] + CONT: + SingleShot: [0, The timer operates in single-shot mode and stops when it reaches the TIMxPER value] + Continuous: + [ + 1, + The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the TIMxPER value, + ] + CKPSC: [0, 7] + ISR: + "?~O[12]CPY": + Inactive: [0, Output is inactive] + Active: [1, Output is active] + "O[12]STAT": + Inactive: [0, Output was inactive] + Active: [1, Output was active] + IPPSTAT: + Output1Active: [0, Protection occurred when the output 1 was active and output 2 forced inactive] + Output2Active: [1, Protection occurred when the output 2 was active and output 1 forced inactive] + CPPSTAT: + Output1Active: [0, Signal applied on output 1 and output 2 forced inactive] + Output2Active: [1, Signal applied on output 2 and output 1 forced inactive] + DLYPRT: + Inactive: [0, Not in delayed idle or balanced idle mode] + Active: [1, Delayed idle or balanced idle mode entry] + RST: + NoEvent: [0, No TIMx counter reset/roll-over interrupt occurred] + Event: [1, TIMx counter reset/roll-over interrupt occurred] + "RST[12]": + NoEvent: [0, No Tx output reset interrupt occurred] + Event: [1, Tx output reset interrupt occurred] + "SET[12]": + NoEvent: [0, No Tx output set interrupt occurred] + Event: [1, Tx output set interrupt occurred] + "CPT[12]": + NoEvent: [0, No timer x capture reset interrupt occurred] + Event: [1, Timer x capture reset interrupt occurred] + UPD: + NoEvent: [0, No timer update interrupt occurred] + Event: [1, Timer update interrupt occurred] + REP: + NoEvent: [0, No timer repetition interrupt occurred] + Event: [1, Timer repetition interrupt occurred] + "CMP[1-4]": + NoEvent: [0, No compare interrupt occurred] + Event: [1, Compare interrupt occurred] + ICR: + "*C": + _W1C: + Clear: [1, Clears associated flag in ISR register] + DIER: + "*DE": + Disabled: [0, DMA request disabled] + Enabled: [1, DMA request enabled] + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + CNTR: + CNT: [0, 0xFFFF] + PERR: + PER: [0, 0xFFFF] + REPR: + REP: [0, 0xFF] + "CMP[1-4]R": + CMP: [0, 0xFFFF] + CMP1CR: + CMP1: [0, 0xFFFF] + REP: [0, 0xFF] + "CPT[12]R": + CPT: [0, 0xFFFF] + DTR: + DTFLK: + Unlocked: [0, Deadtime falling value and sign is writable] + Locked: [1, Deadtime falling value and sign is read-only] + DTFSLK: + Unlocked: [0, Deadtime falling sign is writable] + Locked: [1, Deadtime falling sign is read-only] + SDTF: + Positive: [0, Positive deadtime on falling edge] + Negative: [1, Negative deadtime on falling edge] + DTF: [0, 0x1FF] + DTRLK: + Unlocked: [0, Deadtime rising value and sign is writable] + Locked: [1, Deadtime rising value and sign is read-only] + DTRSLK: + Unlocked: [0, Deadtime rising sign is writable] + Locked: [1, Deadtime rising sign is read-only] + DTPRSC: [0, 7] + SDTR: + Positive: [0, Positive deadtime on rising edge] + Negative: [1, Negative deadtime on rising edge] + DTR: [0, 0x1FF] + "SET[12]R": + UPDATE: + NoEffect: [0, Register update event has no effect] + SetActive: [1, Register update event forces the output to its active state] + EXTEVNT*: + NoEffect: [0, External event has no effect] + SetActive: [1, External event forces the output to its active state] + "TIM[A-F]CMP[1-4]": + NoEffect: [0, Timer event has no effect] + SetActive: [1, Timer event forces the output to its active state] + "MSTCMP[1-4]": + NoEffect: [0, Master timer compare event has no effect] + SetActive: [1, Master timer compare event forces the output to its active state] + MSTPER: + NoEffect: [0, Master timer counter roll-over/reset has no effect] + SetActive: [1, Master timer counter roll-over/reset forces the output to its active state] + "CMP[1-4]": + NoEffect: [0, Timer compare event has no effect] + SetActive: [1, Timer compare event forces the output to its active state] + PER: + NoEffect: [0, Timer period event has no effect] + SetActive: [1, Timer period event forces the output to its active state] + RESYNC: + NoEffect: [0, Timer reset event coming solely from software or SYNC input event has no effect] + SetActive: + [1, Timer reset event coming solely from software or SYNC input event forces the output to its active state] + SST: + NoEffect: [0, No effect] + SetActive: [1, Force output to its active state] + "RST[12]R": + UPDATE: + NoEffect: [0, Register update event has no effect] + SetInactive: [1, Register update event forces the output to its inactive state] + EXTEVNT*: + NoEffect: [0, External event has no effect] + SetInactive: [1, External event forces the output to its inactive state] + "TIM[A-F]CMP[1-4]": + NoEffect: [0, Timer event has no effect] + SetInactive: [1, Timer event forces the output to its inactive state] + "MSTCMP[1-4]": + NoEffect: [0, Master timer compare event has no effect] + SetInactive: [1, Master timer compare event forces the output to its inactive state] + MSTPER: + NoEffect: [0, Master timer counter roll-over/reset has no effect] + SetInactive: [1, Master timer counter roll-over/reset forces the output to its inactive state] + "CMP[1-4]": + NoEffect: [0, Timer compare event has no effect] + SetInactive: [1, Timer compare event forces the output to its inactive state] + PER: + NoEffect: [0, Timer period event has no effect] + SetInactive: [1, Timer period event forces the output to its inactive state] + RESYNC: + NoEffect: [0, Timer reset event coming solely from software or SYNC input event has no effect] + SetInactive: + [1, Timer reset event coming solely from software or SYNC input event forces the output to its inactive state] + SRT: + NoEffect: [0, No effect] + SetInactive: [1, Force output to its inactive state] + "EEFR[12]": + EE*FLTR: + Disabled: [0, No filtering] + BlankResetToCompare1: [1, Blanking from counter reset/roll-over to Compare 1] + BlankResetToCompare2: [2, Blanking from counter reset/roll-over to Compare 2] + BlankResetToCompare3: [3, Blanking from counter reset/roll-over to Compare 3] + BlankResetToCompare4: [4, Blanking from counter reset/roll-over to Compare 4] + BlankTIMFLTR1: [5, "Blanking from another timing unit: TIMFLTR1 source"] + BlankTIMFLTR2: [6, "Blanking from another timing unit: TIMFLTR2 source"] + BlankTIMFLTR3: [7, "Blanking from another timing unit: TIMFLTR3 source"] + BlankTIMFLTR4: [8, "Blanking from another timing unit: TIMFLTR4 source"] + BlankTIMFLTR5: [9, "Blanking from another timing unit: TIMFLTR5 source"] + BlankTIMFLTR6: [10, "Blanking from another timing unit: TIMFLTR6 source"] + BlankTIMFLTR7: [11, "Blanking from another timing unit: TIMFLTR7 source"] + BlankTIMFLTR8: [12, "Blanking from another timing unit: TIMFLTR8 source"] + WindowResetToCompare2: [13, Windowing from counter reset/roll-over to compare 2] + WindowResetToCompare3: [14, Windowing from counter reset/roll-over to compare 3] + WindowTIMWIN: [15, "Windowing from another timing unit: TIMWIN source"] + EE*LTCH: + Disabled: [0, "Event is ignored if it happens during a blank, or passed through during a window"] + Enabled: [1, Event is latched and delayed till the end of the blanking or windowing period] + RSTR: + "TIM[A-F]CMP[1-4]": + NoEffect: [0, Timer Y compare Z event has no effect] + ResetCounter: [1, Timer X counter is reset upon timer Y compare Z event] + EXTEVNT*: + NoEffect: [0, External event Z has no effect] + ResetCounter: [1, Timer X counter is reset upon external event Z] + "MSTCMP[1-4]": + NoEffect: [0, Master timer compare Z event has no effect] + ResetCounter: [1, Timer X counter is reset upon master timer compare Z event] + MSTPER: + NoEffect: [0, Master timer period event has no effect] + ResetCounter: [1, Timer X counter is reset upon master timer period event] + "CMP[24]": + NoEffect: [0, Timer X compare Z event has no effect] + ResetCounter: [1, Timer X counter is reset upon timer X compare Z event] + UPDT: + NoEffect: [0, Update event has no effect] + ResetCounter: [1, Timer X counter is reset upon update event] + CHPR: + STRTPW: [0, 0xF] + CARDTY: [0, 7] + CARFRQ: [0, 0xF] + "CPT[12]CR": + "T[A-F]CMP[12]": + NoEffect: [0, Timer X compare Y has no effect] + TriggerCapture: [1, Timer X compare Y triggers capture Z] + "T[A-F]1RST": + NoEffect: [0, Timer X output Y active to inactive transition has no effect] + TriggerCapture: [1, Timer X output Y active to inactive transition triggers capture Z] + "T[A-F]1SET": + NoEffect: [0, Timer X output Y inactive to active transition has no effect] + TriggerCapture: [1, Timer X output Y inactive to active transition triggers capture Z] + EXEV*CPT: + NoEffect: [0, External event Y has no effect] + TriggerCapture: [1, External event Y triggers capture Z] + UPDCPT: + NoEffect: [0, Update event has no effect] + TriggerCapture: [1, Update event triggers capture Z] + SWCPT: + NoEffect: [0, No effect] + TriggerCapture: [1, Force capture Z] + OUTR: + "DIDL[12]": + Disabled: [0, The programmed idle state is applied immediately to the output] + Enabled: [1, Deadtime (inactive level) is inserted on output before entering the idle mode] + "CHP[12]": + Disabled: [0, Output signal not altered] + Enabled: [1, Output signal is chopped by a carrier signal] + "FAULT[12]": + Disabled: [0, "No action: the output is not affected by the fault input and stays in run mode"] + SetActive: [1, Output goes to active state after a fault event] + SetInactive: [2, Output goes to inactive state after a fault event] + SetHighZ: [3, Output goes to high-z state after a fault event] + "IDLES[12]": + Inactive: [0, Output idle state is inactive] + Active: [1, Output idle state is active] + "IDLEM[12]": + NoEffect: [0, "No action: the output is not affected by the burst mode operation"] + SetIdle: [1, The output is in idle state when requested by the burst mode controller] + "POL[12]": + ActiveHigh: [0, Positive polarity (output active high)] + ActiveLow: [1, Negative polarity (output active low)] + DLYPRTEN: + Disabled: [0, No action] + Enabled: [1, "Delayed protection is enabled, as per DLYPRT bits"] + DTEN: + Disabled: [0, Output 1 and 2 signals are independent] + Enabled: [1, Deadtime is inserted between output 1 and output 2] + FLTR: + FLTLCK: + Unlocked: [0, FLT1EN..FLT5EN bits are read/write] + Locked: [1, FLT1EN..FLT5EN bits are read only] + "FLT[123456]EN": + Ignored: [0, Fault input ignored] + Active: [1, Fault input is active and can disable HRTIM outputs] + +"HRTIM_TIM[ABC]": + OUTR: + DLYPRT: + Output1_EE6: [0, Output 1 delayed idle on external event 6] + Output2_EE6: [1, Output 2 delayed idle on external event 6] + Output1_2_EE6: [2, Output 1 and 2 delayed idle on external event 6] + Balanced_EE6: [3, Balanced idle on external event 6] + Output1_EE7: [4, Output 1 delayed idle on external event 7] + Output2_EE7: [5, Output 2 delayed idle on external event 7] + Output1_2_EE7: [6, Output 1 and 2 delayed idle on external event 7] + Balanced_EE7: [7, Balanced idle on external event 7] + +"HRTIM_TIM[DE]": + OUTR: + DLYPRT: + Output1_EE8: [0, Output 1 delayed idle on external event 8] + Output2_EE8: [1, Output 2 delayed idle on external event 8] + Output1_2_EE8: [2, Output 1 and 2 delayed idle on external event 8] + Balanced_EE8: [3, Balanced idle on external event 8] + Output1_EE9: [4, Output 1 delayed idle on external event 9] + Output2_EE9: [5, Output 2 delayed idle on external event 9] + Output1_2_EE9: [6, Output 1 and 2 delayed idle on external event 9] + Balanced_EE9: [7, Balanced idle on external event 9] diff --git a/devices/fields/hsem/common.yaml b/devices/fields/hsem/common.yaml new file mode 100644 index 000000000..82fbf64aa --- /dev/null +++ b/devices/fields/hsem/common.yaml @@ -0,0 +1,41 @@ +"R[0-9],R1[0-5]": + LOCK: + _read: + Free: [0, Semaphore is free] + Locked: [1, Semaphore is locked] + _write: + Free: [0, Free semaphore] + TryLock: [1, Try to lock semaphore] + "COREID,MASTERID": [0, 0xF] + PROCID: [0, 0xFF] +"RLR[0-9],RLR1[0-5]": + LOCK: + _read: + Free: [0, Semaphore is free] + Locked: [1, Semaphore is locked] + "COREID,MASTERID": [0, 0xF] + PROCID: [0, 0xFF] +"C[12]IER,IER": + ISE[0-9]*: + Disabled: [0, Interrupt generation disabled] + Enabled: [1, Interrupt generation enabled] +"C[12]ICR,ICR": + ISC[0-9]*: + _read: + NoEffect: [0, Always reads 0] + _write: + NoEffect: [0, Interrupt semaphore x status ISFx and masked status MISFx not affected] + Clear: [1, Interrupt semaphore x status ISFx and masked status MISFx cleared] +"C[12]ISR,ISR": + ISF[0-9]*: + NotPending: [0, No interrupt pending] + Pending: [1, Interrupt pending] +"C[12]MISR,MISR": + MISF[0-9]*: + NotPending: [0, No interrupt pending after masking] + Pending: [1, Interrupt pending after masking] +CR: + KEY: [0, 0xFFFF] + "COREID,MASTERID": [0, 0xF] +KEYR: + KEY: [0, 0xFFFF] diff --git a/devices/fields/i2c/u0.yaml b/devices/fields/i2c/u0.yaml new file mode 100644 index 000000000..1a512afa1 --- /dev/null +++ b/devices/fields/i2c/u0.yaml @@ -0,0 +1,3 @@ +_include: + - v2/common.yaml + - v2/fast.yaml diff --git a/devices/fields/i2c/v1.yaml b/devices/fields/i2c/v1.yaml new file mode 100644 index 000000000..00e3e9446 --- /dev/null +++ b/devices/fields/i2c/v1.yaml @@ -0,0 +1,177 @@ +# I2C peripheral used in STM32F1, F4, and L1 families + +CR1: + SWRST: + NotReset: [0, I2C peripheral not under reset] + Reset: [1, I2C peripheral under reset] + ALERT: + Release: [0, SMBA pin released high] + Drive: [1, SMBA pin driven low] + PEC: + Disabled: [0, No PEC transfer] + Enabled: [1, PEC transfer] + POS: + Current: [0, ACK bit controls the (N)ACK of the current byte being received] + Next: [1, ACK bit controls the (N)ACK of the next byte to be received] + ACK: + NAK: [0, No acknowledge returned] + ACK: [1, Acknowledge returned after a byte is received] + STOP: + NoStop: [0, No Stop generation] + Stop: + [ + 1, + "In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte", + ] + START: + NoStart: [0, No Start generation] + Start: [1, "In master mode: repeated start generation, in slave mode: start generation when bus is free"] + NOSTRETCH: + Enabled: [0, Clock stretching enabled] + Disabled: [1, Clock stretching disabled] + ENGC: + Disabled: [0, General call disabled] + Enabled: [1, General call enabled] + ENPEC: + Disabled: [0, PEC calculation disabled] + Enabled: [1, PEC calculation enabled] + ENARP: + Disabled: [0, ARP disabled] + Enabled: [1, ARP enabled] + SMBTYPE: + Device: [0, SMBus Device] + Host: [1, SMBus Host] + SMBUS: + I2C: [0, I2C Mode] + SMBus: [1, SMBus] + PE: + Disabled: [0, Peripheral disabled] + Enabled: [1, Peripheral enabled] + +CR2: + LAST: + NotLast: [0, Next DMA EOT is not the last transfer] + Last: [1, Next DMA EOT is the last transfer] + DMAEN: + Disabled: [0, DMA requests disabled] + Enabled: [1, "DMA request enabled when TxE=1 or RxNE=1"] + ITBUFEN: + Disabled: [0, "TxE=1 or RxNE=1 does not generate any interrupt"] + Enabled: [1, "TxE=1 or RxNE=1 generates Event interrupt"] + ITEVTEN: + Disabled: [0, Event interrupt disabled] + Enabled: [1, Event interrupt enabled] + ITERREN: + Disabled: [0, Error interrupt disabled] + Enabled: [1, Error interrupt enabled] + FREQ: [2, 50] + +OAR1: + ADDMODE: + ADD7: [0, 7-bit slave address] + ADD10: [1, 10-bit slave address] + ADD: [0, 1023] + +OAR2: + ADD2: [0, 0x7F] + ENDUAL: + Single: [0, Single addressing mode] + Dual: [1, Dual addressing mode] + +DR: + DR: [0, 0xFF] + +SR1: + SMBALERT: + _read: + NoAlert: [0, No SMBALERT occured] + Alert: [1, SMBALERT occurred] + _W0C: + Clear: [0, Clear flag] + TIMEOUT: + _read: + NoTimeout: [0, No Timeout error] + Timeout: [1, SCL remained LOW for 25 ms] + _W0C: + Clear: [0, Clear flag] + PECERR: + _read: + NoError: [0, "no PEC error: receiver returns ACK after PEC reception (if ACK=1)"] + Error: [1, "PEC error: receiver returns NACK after PEC reception (whatever ACK)"] + _W0C: + Clear: [0, Clear flag] + OVR: + _read: + NoOverrun: [0, No overrun/underrun occured] + Overrun: [1, Overrun/underrun occured] + _W0C: + Clear: [0, Clear flag] + AF: + _read: + NoFailure: [0, No acknowledge failure] + Failure: [1, Acknowledge failure] + _W0C: + Clear: [0, Clear flag] + ARLO: + _read: + NoLost: [0, No Arbitration Lost detected] + Lost: [1, Arbitration Lost detected] + _W0C: + Clear: [0, Clear flag] + BERR: + _read: + NoError: [0, No misplaced Start or Stop condition] + Error: [1, Misplaced Start or Stop condition] + _W0C: + Clear: [0, Clear flag] + TxE: + NotEmpty: [0, Data register not empty] + Empty: [1, Data register empty] + RxNE: + Empty: [0, Data register empty] + NotEmpty: [1, Data register not empty] + STOPF: + NoStop: [0, No Stop condition detected] + Stop: [1, Stop condition detected] + BTF: + NotFinished: [0, Data byte transfer not done] + Finished: [1, Data byte transfer successful] + ADDR: + NotMatch: [0, Adress mismatched or not received] + Match: [1, Received slave address matched with one of the enabled slave addresses] + SB: + NoStart: [0, No Start condition] + Start: [1, Start condition generated] +CCR: + F_S: + Standard: [0, Standard mode I2C] + Fast: [1, Fast mode I2C] + DUTY: + Duty2_1: [0, "Duty cycle t_low/t_high = 2/1"] + Duty16_9: [1, "Duty cycle t_low/t_high = 16/9"] + CCR: [1, 0xFFF] + +TRISE: + TRISE: [0, 0x3F] + +"?~FLTR": + ANOFF: + Enabled: [0, Analog noise filter enabled] + Disabled: [1, Analog noise filter disabled] + DNF: + NoFilter: [0, Digital filter disabled] + Filter1: [1, Digital filter enabled and filtering capability up to 1 tI2CCLK] + Filter2: [2, Digital filter enabled and filtering capability up to 2 tI2CCLK] + Filter3: [3, Digital filter enabled and filtering capability up to 3 tI2CCLK] + Filter4: [4, Digital filter enabled and filtering capability up to 4 tI2CCLK] + Filter5: [5, Digital filter enabled and filtering capability up to 5 tI2CCLK] + Filter6: [6, Digital filter enabled and filtering capability up to 6 tI2CCLK] + Filter7: [7, Digital filter enabled and filtering capability up to 7 tI2CCLK] + Filter8: [8, Digital filter enabled and filtering capability up to 8 tI2CCLK] + Filter9: [9, Digital filter enabled and filtering capability up to 9 tI2CCLK] + Filter10: [10, Digital filter enabled and filtering capability up to 10 tI2CCLK] + Filter11: [11, Digital filter enabled and filtering capability up to 11 tI2CCLK] + Filter12: [12, Digital filter enabled and filtering capability up to 12 tI2CCLK] + Filter13: [13, Digital filter enabled and filtering capability up to 13 tI2CCLK] + Filter14: [14, Digital filter enabled and filtering capability up to 14 tI2CCLK] + Filter15: [15, Digital filter enabled and filtering capability up to 15 tI2CCLK] diff --git a/devices/fields/i2c/v2.yaml b/devices/fields/i2c/v2.yaml new file mode 100644 index 000000000..9ad60848c --- /dev/null +++ b/devices/fields/i2c/v2.yaml @@ -0,0 +1,5 @@ +# Base for `i2c_v2.yaml`. + +_include: + - v2/common.yaml + - v2/smbus.yaml diff --git a/devices/fields/i2c/v2/common.yaml b/devices/fields/i2c/v2/common.yaml new file mode 100644 index 000000000..c4e67d478 --- /dev/null +++ b/devices/fields/i2c/v2/common.yaml @@ -0,0 +1,215 @@ +# Base for `i2c_v2.yaml`. + +CR1: + GCEN: + Disabled: [0, General call disabled. Address 0b00000000 is NACKed] + Enabled: [1, General call enabled. Address 0b00000000 is ACKed] + NOSTRETCH: + Enabled: [0, Clock stretching enabled] + Disabled: [1, Clock stretching disabled] + SBC: + Disabled: [0, Slave byte control disabled] + Enabled: [1, Slave byte control enabled] + RXDMAEN: + Disabled: [0, DMA mode disabled for reception] + Enabled: [1, DMA mode enabled for reception] + TXDMAEN: + Disabled: [0, DMA mode disabled for transmission] + Enabled: [1, DMA mode enabled for transmission] + ANFOFF: + Enabled: [0, Analog noise filter enabled] + Disabled: [1, Analog noise filter disabled] + DNF: + NoFilter: [0, Digital filter disabled] + Filter1: [1, Digital filter enabled and filtering capability up to 1 tI2CCLK] + Filter2: [2, Digital filter enabled and filtering capability up to 2 tI2CCLK] + Filter3: [3, Digital filter enabled and filtering capability up to 3 tI2CCLK] + Filter4: [4, Digital filter enabled and filtering capability up to 4 tI2CCLK] + Filter5: [5, Digital filter enabled and filtering capability up to 5 tI2CCLK] + Filter6: [6, Digital filter enabled and filtering capability up to 6 tI2CCLK] + Filter7: [7, Digital filter enabled and filtering capability up to 7 tI2CCLK] + Filter8: [8, Digital filter enabled and filtering capability up to 8 tI2CCLK] + Filter9: [9, Digital filter enabled and filtering capability up to 9 tI2CCLK] + Filter10: [10, Digital filter enabled and filtering capability up to 10 tI2CCLK] + Filter11: [11, Digital filter enabled and filtering capability up to 11 tI2CCLK] + Filter12: [12, Digital filter enabled and filtering capability up to 12 tI2CCLK] + Filter13: [13, Digital filter enabled and filtering capability up to 13 tI2CCLK] + Filter14: [14, Digital filter enabled and filtering capability up to 14 tI2CCLK] + Filter15: [15, Digital filter enabled and filtering capability up to 15 tI2CCLK] + ERRIE: + Disabled: [0, Error detection interrupts disabled] + Enabled: [1, Error detection interrupts enabled] + TCIE: + Disabled: [0, Transfer Complete interrupt disabled] + Enabled: [1, Transfer Complete interrupt enabled] + STOPIE: + Disabled: [0, Stop detection (STOPF) interrupt disabled] + Enabled: [1, Stop detection (STOPF) interrupt enabled] + NACKIE: + Disabled: [0, Not acknowledge (NACKF) received interrupts disabled] + Enabled: [1, Not acknowledge (NACKF) received interrupts enabled] + ADDRIE: + Disabled: [0, Address match (ADDR) interrupts disabled] + Enabled: [1, Address match (ADDR) interrupts enabled] + RXIE: + Disabled: [0, Receive (RXNE) interrupt disabled] + Enabled: [1, Receive (RXNE) interrupt enabled] + TXIE: + Disabled: [0, Transmit (TXIS) interrupt disabled] + Enabled: [1, Transmit (TXIS) interrupt enabled] + PE: + Disabled: [0, Peripheral disabled] + Enabled: [1, Peripheral enabled] + "?~WUPEN": + Disabled: [0, Wakeup from Stop mode disabled] + Enabled: [1, Wakeup from Stop mode enabled] + +CR2: + AUTOEND: + Software: [0, "Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low"] + Automatic: [1, "Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred"] + RELOAD: + Completed: [0, The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)] + NotCompleted: [1, The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)] + NACK: + _read: + Ack: [0, an ACK is sent after current received byte] + Nack: [1, a NACK is sent after current received byte] + _W1S: + Nack: [1, a NACK is sent after current received byte] + STOP: + _read: + NoStop: [0, No Stop generation] + Stop: [1, Stop generation after current byte transfer] + _W1S: + Stop: [1, Stop generation after current byte transfer] + START: + _read: + NoStart: [0, No Start generation] + Start: [1, Restart/Start generation] + _W1S: + Start: [1, Restart/Start generation] + HEAD10R: + Complete: [0, The master sends the complete 10 bit slave address read sequence] + Partial: [1, "The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction"] + ADD10: + Bit7: [0, The master operates in 7-bit addressing mode] + Bit10: [1, The master operates in 10-bit addressing mode] + RD_WRN: + Write: [0, Master requests a write transfer] + Read: [1, Master requests a read transfer] + NBYTES: [0, 255] + SADD: [0, 1023] +OAR1: + OA1EN: + Disabled: [0, Own address 1 disabled. The received slave address OA1 is NACKed] + Enabled: [1, Own address 1 enabled. The received slave address OA1 is ACKed] + OA1MODE: + Bit7: [0, Own address 1 is a 7-bit address] + Bit10: [1, Own address 1 is a 10-bit address] + OA1: [0, 1023] +OAR2: + OA2EN: + Disabled: [0, Own address 2 disabled. The received slave address OA2 is NACKed] + Enabled: [1, Own address 2 enabled. The received slave address OA2 is ACKed] + OA2MSK: + NoMask: [0, No mask] + Mask1: [1, "OA2[1] is masked and don’t care. Only OA2[7:2] are compared"] + Mask2: [2, "OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared"] + Mask3: [3, "OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared"] + Mask4: [4, "OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared"] + Mask5: [5, "OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared"] + Mask6: [6, "OA2[6:1] are masked and don’t care. Only OA2[7] is compared."] + Mask7: + [ + 7, + "OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged", + ] + OA2: [0, 127] +TIMINGR: + PRESC: [0, 15] + SCLDEL: [0, 15] + SDADEL: [0, 15] + SCLH: [0, 255] + SCLL: [0, 255] +TIMEOUTR: + TEXTEN: + Disabled: [0, Extended clock timeout detection is disabled] + Enabled: [1, Extended clock timeout detection is enabled] + TIMEOUTB: [0, 4095] + TIMOUTEN: + Disabled: [0, SCL timeout detection is disabled] + Enabled: [1, SCL timeout detection is enabled] + TIDLE: + Disabled: [0, TIMEOUTA is used to detect SCL low timeout] + Enabled: [1, TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)] + TIMEOUTA: [0, 4095] +ISR: + ADDCODE: [0, 127] + DIR: + Write: [0, "Write transfer, slave enters receiver mode"] + Read: [1, "Read transfer, slave enters transmitter mode"] + BUSY: + NotBusy: [0, No communication is in progress on the bus] + Busy: [1, A communication is in progress on the bus] + OVR: + NoOverrun: [0, No overrun/underrun error occurs] + Overrun: [1, "slave mode with NOSTRETCH=1, when an overrun/underrun error occurs"] + ARLO: + NotLost: [0, No arbitration lost] + Lost: [1, Arbitration lost] + BERR: + NoError: [0, No bus error] + Error: [1, Misplaced Start and Stop condition is detected] + TCR: + NotComplete: [0, Transfer is not complete] + Complete: [1, NBYTES has been transfered] + TC: + NotComplete: [0, Transfer is not complete] + Complete: [1, NBYTES has been transfered] + STOPF: + NoStop: [0, No Stop condition detected] + Stop: [1, Stop condition detected] + NACKF: + NoNack: [0, No NACK has been received] + Nack: [1, NACK has been received] + ADDR: + NotMatch: [0, Adress mismatched or not received] + Match: [1, Received slave address matched with one of the enabled slave addresses] + RXNE: + Empty: [0, The RXDR register is empty] + NotEmpty: [1, "Received data is copied into the RXDR register, and is ready to be read"] + TXIS: + _read: + NotEmpty: [0, The TXDR register is not empty] + Empty: [1, The TXDR register is empty and the data to be transmitted must be written in the TXDR register] + _W1S: + Trigger: [1, Generate a TXIS event] + TXE: + _read: + NotEmpty: [0, TXDR register not empty] + Empty: [1, TXDR register empty] + _W1S: + Flush: [1, Flush the transmit data register] + +ICR: + "*": + _W1C: {} + OVRCF: + Clear: [1, Clears the OVR flag in ISR register] + ARLOCF: + Clear: [1, Clears the ARLO flag in ISR register] + BERRCF: + Clear: [1, Clears the BERR flag in ISR register] + STOPCF: + Clear: [1, Clears the STOP flag in ISR register] + NACKCF: + Clear: [1, Clears the NACK flag in ISR register] + ADDRCF: + Clear: [1, Clears the ADDR flag in ISR register] +PECR: + PEC: [0, 255] +RXDR: + RXDATA: [0, 255] +TXDR: + TXDATA: [0, 255] diff --git a/devices/fields/i2c/v2/fast.yaml b/devices/fields/i2c/v2/fast.yaml new file mode 100644 index 000000000..08997906d --- /dev/null +++ b/devices/fields/i2c/v2/fast.yaml @@ -0,0 +1,10 @@ +CR1: + FMP: + Disabled: [0, 20 mA I/O drive disabled] + Enabled: [1, 20 mA I/O drive enabled] + ADDRACLR: + Disabled: [0, "ADDR flag is set by hardware, cleared by software"] + Enabled: [1, ADDR flag remains cleared by hardware] + STOPFACLR: + Disabled: [0, "STOPF flag is set by hardware, cleared by software"] + Enabled: [1, STOPF flag remains cleared by hardware] diff --git a/devices/fields/i2c/v2/smbus.yaml b/devices/fields/i2c/v2/smbus.yaml new file mode 100644 index 000000000..28f6ab063 --- /dev/null +++ b/devices/fields/i2c/v2/smbus.yaml @@ -0,0 +1,48 @@ +CR1: + PECEN: + Disabled: [0, PEC calculation disabled] + Enabled: [1, PEC calculation enabled] + ALERTEN: + Disabled: + [ + 0, + "In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported", + ] + Enabled: + [ + 1, + "In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported", + ] + SMBDEN: + Disabled: [0, Device default address disabled. Address 0b1100001x is NACKed] + Enabled: [1, Device default address enabled. Address 0b1100001x is ACKed] + SMBHEN: + Disabled: [0, Host address disabled. Address 0b0001000x is NACKed] + Enabled: [1, Host address enabled. Address 0b0001000x is ACKed] + +CR2: + PECBYTE: + _read: + NoPec: [0, No PEC transfer] + Pec: [1, PEC transmission/reception is requested] + _W1S: + Pec: [1, PEC transmission/reception is requested] + +ISR: + ALERT: + NoAlert: [0, SMBA alert is not detected] + Alert: [1, SMBA alert event is detected on SMBA pin] + TIMEOUT: + NoTimeout: [0, No timeout occured] + Timeout: [1, Timeout occured] + PECERR: + Match: [0, Received PEC does match with PEC register] + NoMatch: [1, Received PEC does not match with PEC register] + +ICR: + ALERTCF: + Clear: [1, Clears the ALERT flag in ISR register] + TIMOUTCF: + Clear: [1, Clears the TIMOUT flag in ISR register] + PECCF: + Clear: [1, Clears the PEC flag in ISR register] diff --git a/devices/fields/i2c/v3.yaml b/devices/fields/i2c/v3.yaml new file mode 100644 index 000000000..8d586ea6d --- /dev/null +++ b/devices/fields/i2c/v3.yaml @@ -0,0 +1,4 @@ +_include: + - v2/common.yaml + - v2/smbus.yaml + - v2/fast.yaml diff --git a/devices/fields/ipcc/ipcc_wl.yaml b/devices/fields/ipcc/ipcc_wl.yaml new file mode 100644 index 000000000..4bce7d9a0 --- /dev/null +++ b/devices/fields/ipcc/ipcc_wl.yaml @@ -0,0 +1,33 @@ +"C[12]CR": + TXFIE: + Enabled: [1, Enable an unmasked processor transmit channel free to generate a TX free interrupt] + Disabled: [0, Processor TX free interrupt disabled] + RXOIE: + Enabled: [1, Enable an unmasked processor receive channel occupied to generate an RX occupied interrupt] + Disabled: [0, Processor RX occupied interrupt disabled] +"C[12]MR": + "CH[1-6]FM": + Masked: [1, Transmit channel n free interrupt masked] + Unmasked: [0, Transmit channel n free interrupt not masked] + "CH[1-6]OM": + Masked: [1, Receive channel n occupied interrupt masked] + Unmasked: [0, Receive channel n occupied interrupt not masked] +"C[12]SCR": + "CH[1-6]S": + Set: [1, Processor transmit channel n status bit set] + NoAction: [0, No action] + "CH[1-6]C": + Clear: [1, Processor receive channel n status bit clear] + NoAction: [0, No action] +"C[12]TOC[12]SR": + "CH[1-5]F": + Occupied: + [ + 1, + "Channel occupied, data can be read by the receiving processor. Generates a channel RX occupied interrupt to the other processor, when unmasked", + ] + Free: + [ + 0, + "Channel free, data can be written by the sending processor. Generates a channel TX free interrupt to the current processor, when unmasked", + ] diff --git a/devices/fields/iwdg/h5.yaml b/devices/fields/iwdg/h5.yaml new file mode 100644 index 000000000..1b7bc5c5b --- /dev/null +++ b/devices/fields/iwdg/h5.yaml @@ -0,0 +1,32 @@ +KR: + KEY: + Unlock: [0x5555, "Enable access to PR, RLR and WINR registers"] + Feed: [0xAAAA, Feed watchdog with RLR register value] + Start: [0xCCCC, Start the watchdog] +PR: + PR: + DivideBy4: [0, Divider /4] + DivideBy8: [1, Divider /8] + DivideBy16: [2, Divider /16] + DivideBy32: [3, Divider /32] + DivideBy64: [4, Divider /64] + DivideBy128: [5, Divider /128] + DivideBy256: [6, Divider /256] + DivideBy512: [7, Divider /512] + DivideBy1024: [-1, Divider /1024] +RLR: + RL: [0, 4095] +SR: + "*U": + Idle: [0, No update on-going] + Busy: [1, Update on-going] + "*IF": + _read: + NotPending: [0, No pending interrupt] + Pending: [1, Interrupt pending] + ONF: + _read: + NotActivated: [0, IWDG is not activated] + Activated: [1, IWDG is activated] +WINR: + WIN: [0, 4095] diff --git a/devices/fields/iwdg/iwdg.yaml b/devices/fields/iwdg/iwdg.yaml new file mode 100644 index 000000000..b180d523f --- /dev/null +++ b/devices/fields/iwdg/iwdg.yaml @@ -0,0 +1,20 @@ +# IWDG peripheral +# Present on F1, F2, F4 and L1 families. +# Base for `iwdg_with_window.yaml`. + +KR: + KEY: + Unlock: [0x5555, "Enable access to PR, RLR and WINR registers"] + Feed: [0xAAAA, Feed watchdog with RLR register value] + Start: [0xCCCC, Start the watchdog] +PR: + PR: + DivideBy4: [0, Divider /4] + DivideBy8: [1, Divider /8] + DivideBy16: [2, Divider /16] + DivideBy32: [3, Divider /32] + DivideBy64: [4, Divider /64] + DivideBy128: [5, Divider /128] + DivideBy256: [-1, Divider /256] +RLR: + RL: [0, 4095] diff --git a/devices/fields/iwdg/iwdg_sr.yaml b/devices/fields/iwdg/iwdg_sr.yaml new file mode 100644 index 000000000..9afcb3660 --- /dev/null +++ b/devices/fields/iwdg/iwdg_sr.yaml @@ -0,0 +1,4 @@ +SR: + "*U": + Idle: [0, No update on-going] + Busy: [1, Update on-going] diff --git a/devices/fields/iwdg/iwdg_with_WINR.yaml b/devices/fields/iwdg/iwdg_with_WINR.yaml new file mode 100644 index 000000000..721b056ff --- /dev/null +++ b/devices/fields/iwdg/iwdg_with_WINR.yaml @@ -0,0 +1,9 @@ +# IWDG peripheral with window register +# Present on F0, F3, F7, H7, L0 and L4 families. +# Extend `iwdg.yaml`. + +_include: + - iwdg.yaml + +WINR: + WIN: [0, 4095] diff --git a/devices/fields/lptim/lptim1_wl.yaml b/devices/fields/lptim/lptim1_wl.yaml new file mode 100644 index 000000000..cd760ceb4 --- /dev/null +++ b/devices/fields/lptim/lptim1_wl.yaml @@ -0,0 +1,7 @@ +OR: + OR_1: + IO: [0, LPTIM1 input 2 is connected to I/O] + COMP2_OUT: [1, LPTIM1 input 2 is connected to COMP2_OUT] + OR_0: + IO: [0, LPTIM1 input 1 is connected to I/O] + COMP1_OUT: [1, LPTIM1 input 1 is connected to COMP1_OUT] diff --git a/devices/fields/lptim/lptim2_wl.yaml b/devices/fields/lptim/lptim2_wl.yaml new file mode 100644 index 000000000..6f33a02a0 --- /dev/null +++ b/devices/fields/lptim/lptim2_wl.yaml @@ -0,0 +1,6 @@ +OR: + OR_: + IO: [0, Input 1 is connected to I/O] + COMP1_OUT: [1, Input 1 is connected to COMP1_OUT] + COMP2_OUT: [2, Input 1 is connected to COMP2_OUT] + OR_COMP1_COMP2: [3, Input 1 is connected to COMP1_OUT OR COMP2_OUT] diff --git a/devices/fields/lptim/v1.yaml b/devices/fields/lptim/v1.yaml new file mode 100644 index 000000000..fd9482022 --- /dev/null +++ b/devices/fields/lptim/v1.yaml @@ -0,0 +1,176 @@ +# Low Power Timers used on at least L0, H7 + +ISR: + DOWN: + _read: + Set: [1, Counter direction change up to down] + UP: + _read: + Set: [1, Counter direction change down to up] + ARROK: + _read: + Set: [1, Autoreload register update OK] + CMPOK: + _read: + Set: [1, Compare register update OK] + EXTTRIG: + _read: + Set: [1, External trigger edge event] + ARRM: + _read: + Set: [1, Autoreload match] + CMPM: + _read: + Set: [1, Compare match] +ICR: + DOWNCF: + _write: + Clear: [1, Direction change to down Clear Flag] + UPCF: + _write: + Clear: [1, Direction change to up Clear Flag] + ARROKCF: + _write: + Clear: [1, Autoreload register update OK Clear Flag] + CMPOKCF: + _write: + Clear: [1, Compare register update OK Clear Flag] + EXTTRIGCF: + _write: + Clear: [1, External trigger valid edge Clear Flag] + ARRMCF: + _write: + Clear: [1, Autoreload match Clear Flag] + CMPMCF: + _write: + Clear: [1, Compare match Clear Flag] +IER: + DOWNIE: + Disabled: [0, DOWN interrupt disabled] + Enabled: [1, DOWN interrupt enabled] + UPIE: + Disabled: [0, UP interrupt disabled] + Enabled: [1, UP interrupt enabled] + ARROKIE: + Disabled: [0, ARROK interrupt disabled] + Enabled: [1, ARROK interrupt enabled] + CMPOKIE: + Disabled: [0, CMPOK interrupt disabled] + Enabled: [1, CMPOK interrupt enabled] + EXTTRIGIE: + Disabled: [0, EXTTRIG interrupt disabled] + Enabled: [1, EXTTRIG interrupt enabled] + ARRMIE: + Disabled: [0, ARRM interrupt disabled] + Enabled: [1, ARRM interrupt enabled] + CMPMIE: + Disabled: [0, CMPM interrupt disabled] + Enabled: [1, CMPM interrupt enabled] +CFGR: + ENC: + Disabled: [0, Encoder mode disabled] + Enabled: [1, Encoder mode enabled] + COUNTMODE: + Internal: [0, The counter is incremented following each internal clock pulse] + External: [1, The counter is incremented following each valid clock pulse on the LPTIM external Input1] + PRELOAD: + Immediate: [0, Registers are updated after each APB bus write access] + EndOfPeriod: [1, Registers are updated at the end of the current LPTIM period] + WAVPOL: + Positive: [0, The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers] + Negative: + [1, The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers] + WAVE: + Inactive: [0, "Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)"] + Active: [1, Activate the Set-once mode] + TIMOUT: + Disabled: [0, A trigger event arriving when the timer is already started will be ignored] + Enabled: [1, A trigger event arriving when the timer is already started will reset and restart the counter] + TRIGEN: + SW: [0, Software trigger (counting start is initiated by software)] + RisingEdge: [1, Rising edge is the active edge] + FallingEdge: [2, Falling edge is the active edge] + BothEdges: [3, Both edges are active edges] + TRIGSEL: + Trig0: [0, lptim_ext_trig0] + Trig1: [1, lptim_ext_trig1] + Trig2: [2, lptim_ext_trig2] + Trig3: [3, lptim_ext_trig3] + Trig4: [4, lptim_ext_trig4] + Trig5: [5, lptim_ext_trig5] + Trig6: [6, lptim_ext_trig6] + Trig7: [7, lptim_ext_trig7] + PRESC: + Div1: [0, "/1"] + Div2: [1, "/2"] + Div4: [2, "/4"] + Div8: [3, "/8"] + Div16: [4, "/16"] + Div32: [5, "/32"] + Div64: [6, "/64"] + Div128: [7, "/128"] + TRGFLT: + Immediate: [0, Any trigger active level change is considered as a valid trigger] + Clocks2: + [ + 1, + Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger, + ] + Clocks4: + [ + 2, + Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger, + ] + Clocks8: + [ + 3, + Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger, + ] + CKFLT: + Immediate: [0, Any external clock signal level change is considered as a valid transition] + Clocks2: + [ + 1, + External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition, + ] + Clocks4: + [ + 2, + External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition, + ] + Clocks8: + [ + 3, + External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition, + ] + CKPOL: + RisingEdge: + [ + 0, + "The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active.", + ] + FallingEdge: + [ + 1, + "The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active.", + ] + BothEdges: [2, "Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active."] + CKSEL: + Internal: [0, LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)] + External: [1, LPTIM is clocked by an external clock source through the LPTIM external Input1] +CR: + CNTSTRT: + _write: + Start: [1, Timer start in Continuous mode] + SNGSTRT: + _write: + Start: [1, LPTIM start in Single mode] + ENABLE: + Disabled: [0, LPTIM is disabled] + Enabled: [1, LPTIM is enabled] +CMP: + CMP: [0, 0xFFFF] +ARR: + ARR: [0, 0xFFFF] +CNT: + CNT: [0, 0xFFFF] diff --git a/devices/fields/lptim/v1b.yaml b/devices/fields/lptim/v1b.yaml new file mode 100644 index 000000000..97164ab60 --- /dev/null +++ b/devices/fields/lptim/v1b.yaml @@ -0,0 +1,13 @@ +_include: + - v1.yaml + +CR: + RSTARE: + Disabled: [0, CNT Register reads do not trigger reset] + Enabled: [1, CNT Register reads trigger reset of LPTIM] + COUNTRST: + _write: + Reset: [1, Trigger synchronous reset of CNT (3 LPTimer core clock cycles)] + _read: + Idle: [0, Triggering of reset is possible] + Busy: [1, "Reset in progress, do not write 1 to this field"] diff --git a/devices/fields/lptim/v2.yaml b/devices/fields/lptim/v2.yaml new file mode 100644 index 000000000..3f4de708c --- /dev/null +++ b/devices/fields/lptim/v2.yaml @@ -0,0 +1,27 @@ +_include: + - v1b.yaml + +ISR: + REPOK: + _read: + Set: [1, Repetition register update OK] + UE: + _read: + Set: [1, LPTIM update event occurred] +ICR: + REPOKCF: + _write: + Clear: [1, Clear REPOK flag] + UECF: + _write: + Clear: [1, Clear update event flag] +IER: + REPOKIE: + Disabled: [0, Repetition register update OK interrupt disabled] + Enabled: [1, Repetition register update OK interrupt enabled] + UEIE: + Disabled: [0, Update event interrupt disabled] + Enabled: [1, Update event interrupt enabled] + +RCR: + REP: [0, 0xFF] diff --git a/devices/fields/ltdc/ltdc.yaml b/devices/fields/ltdc/ltdc.yaml new file mode 100644 index 000000000..e36e197d1 --- /dev/null +++ b/devices/fields/ltdc/ltdc.yaml @@ -0,0 +1,196 @@ +SSCR: + HSW: [0, 4095] + VSH: [0, 2047] + +BPCR: + AHBP: [0, 4095] + AVBP: [0, 2047] + +AWCR: + AAW: [0, 4095] + AAH: [0, 2047] + +TWCR: + TOTALW: [0, 4095] + TOTALH: [0, 2047] + +GCR: + HSPOL: + ActiveLow: [0, Horizontal synchronization polarity is active low] + ActiveHigh: [1, Horizontal synchronization polarity is active high] + VSPOL: + ActiveLow: [0, Vertical synchronization polarity is active low] + ActiveHigh: [1, Vertical synchronization polarity is active high] + DEPOL: + ActiveLow: [0, Data enable polarity is active low] + ActiveHigh: [1, Data enable polarity is active high] + PCPOL: + RisingEdge: [0, Pixel clock on rising edge] + FallingEdge: [1, Pixel clock on falling edge] + DEN: + Disabled: [0, Dither disabled] + Enabled: [1, Dither enabled] + LTDCEN: + Disabled: [0, LCD-TFT controller disabled] + Enabled: [1, LCD-TFT controller enabled] + +SRCR: + VBR: + Reload: + [ + 1, + The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area)., + ] + NoEffect: + [ + 0, + This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set), + ] + IMR: + Reload: + [ + 1, + The shadow registers are reloaded immediately. This bit is set by software and cleared only by hardware after reload, + ] + NoEffect: + [ + 0, + This bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set), + ] + +BCCR: + BCRED: [0, 255] + BCGREEN: [0, 255] + BCBLUE: [0, 255] + +IER: + RRIE: + Disabled: [0, Register reload interrupt disabled] + Enabled: [1, Register reload interrupt enabled] + TERRIE: + Disabled: [0, Transfer error interrupt disabled] + Enabled: [1, Transfer error interrupt enabled] + FUIE: + Disabled: [0, FIFO underrun interrupt disabled] + Enabled: [1, FIFO underrun interrupt enabled] + LIE: + Disabled: [0, Line interrupt disabled] + Enabled: [1, Line interrupt enabled] + +ISR: + RRIF: + NoReload: [0, No register reload] + Reload: + [ + 1, + Register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached), + ] + TERRIF: + NoError: [0, No transfer error] + Error: [1, Transfer error interrupt generated when a bus error occurs] + FUIF: + NoUnderrun: [0, No FIFO underrun] + Underrun: + [1, "FIFO underrun interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO"] + LIF: + NotReached: [0, Programmed line not reached] + Reached: [1, Line interrupt generated when a programmed line is reached] + +ICR: + CRRIF: + _W1C: + Clear: [1, Clears the RRIF flag in the ISR register] + CTERRIF: + _W1C: + Clear: [1, Clears the TERRIF flag in the ISR register] + CFUIF: + _W1C: + Clear: [1, Clears the FUIF flag in the ISR register] + CLIF: + _W1C: + Clear: [1, Clears the LIF flag in the ISR register] + +LIPCR: + LIPOS: [0, 2047] + +CDSR: + HSYNCS: + NotActive: [0, Currently not in HSYNC phase] + Active: [1, Currently in HSYNC phase] + VSYNCS: + NotActive: [0, Currently not in VSYNC phase] + Active: [1, Currently in VSYNC phase] + HDES: + NotActive: [0, Currently not in horizontal Data Enable phase] + Active: [1, Currently in horizontal Data Enable phase] + VDES: + NotActive: [0, Currently not in vertical Data Enable phase] + Active: [1, Currently in vertical Data Enable phase] + +"L[12]CR": + CLUTEN: + Disabled: [0, Color look-up table disabled] + Enabled: [1, Color look-up table enabled] + COLKEN: + Disabled: [0, Color keying disabled] + Enabled: [1, Color keying enabled] + LEN: + Disabled: [0, Layer disabled] + Enabled: [1, Layer enabled] + +"L[12]WHPCR": + WHSPPOS: [0, 4095] + WHSTPOS: [0, 4095] + +"L[12]WVPCR": + WVSPPOS: [0, 2047] + WVSTPOS: [0, 2047] + +"L[12]CKCR": + CKRED: [0, 255] + CKGREEN: [0, 255] + CKBLUE: [0, 255] + +"L[12]PFCR": + PF: + ARGB8888: [0b000, ARGB8888] + RGB888: [0b001, RGB888] + RGB565: [0b010, RGB565] + ARGB1555: [0b011, ARGB1555] + ARGB4444: [0b100, ARGB4444] + L8: [0b101, L8 (8-bit luminance)] + AL44: [0b110, "AL44 (4-bit alpha, 4-bit luminance)"] + AL88: [0b111, "AL88 (8-bit alpha, 8-bit luminance)"] + +"L[12]CACR": + CONSTA: [0, 255] + +"L[12]DCCR": + DCALPHA: [0, 255] + DCRED: [0, 255] + DCGREEN: [0, 255] + DCBLUE: [0, 255] + +"L[12]BFCR": + BF1: + Constant: [0b100, "BF1 = constant alpha"] + Pixel: [0b110, "BF1 = pixel alpha * constant alpha"] + BF2: + Constant: [0b101, "BF2 = 1 - constant alpha"] + Pixel: [0b111, "BF2 = 1 - pixel alpha * constant alpha"] + +"L[12]CFBAR": + CFBADD: [0, 0xFFFFFFFF] + +"L[12]CFBLR": + CFBP: [0, 8191] + CFBLL: [0, 8191] + +"L[12]CFBLNR": + CFBLNBR: [0, 2047] + +"L[12]CLUTWR": + CLUTADD: [0, 255] + RED: [0, 255] + GREEN: [0, 255] + BLUE: [0, 255] diff --git a/peripherals/nvic/nvic_v1.yaml b/devices/fields/nvic/nvic_v1.yaml similarity index 97% rename from peripherals/nvic/nvic_v1.yaml rename to devices/fields/nvic/nvic_v1.yaml index 5f5f8276d..67e6ee521 100644 --- a/peripherals/nvic/nvic_v1.yaml +++ b/devices/fields/nvic/nvic_v1.yaml @@ -48,4 +48,4 @@ NVIC: PRI_31: [0, 0xFF] PRI_30: [0, 0xFF] PRI_29: [0, 0xFF] - PRI_28: [0, 0xFF] \ No newline at end of file + PRI_28: [0, 0xFF] diff --git a/devices/fields/octospi/common.yaml b/devices/fields/octospi/common.yaml new file mode 100644 index 000000000..cd46ebd5e --- /dev/null +++ b/devices/fields/octospi/common.yaml @@ -0,0 +1,329 @@ +CR: + FMODE: + IndirectWrite: [0, Indirect-write mode] + IndirectRead: [1, Indirect-read mode] + AutomaticPolling: [2, Automatic status-polling mode] + MemoryMapped: [3, Memory-mapped mode] + PMM: + ANDMatchMode: + [ + 0, + "AND-match mode, SMF is set if all the unmasked bits received from the device match the corresponding bits in the match register", + ] + ORMatchmode: + [ + 1, + "OR-match mode, SMF is set if any of the unmasked bits received from the device matches its corresponding bit in the match register", + ] + APMS: + Running: [0, Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI] + StopMatch: [1, Automatic status-polling mode stops as soon as there is a match] + TOIE,SMIE,FTIE,TCIE,TEIE: + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + FTHRES: [0, 0x1F] + TCEN: + Disabled: + [ + 0, + "Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely after an access in Memory-mapped mode", + ] + Enabled: + [ + 1, + "Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped mode after TIMEOUT[15:0] cycles of external device inactivity", + ] + DMAEN: + Disabled: [0, DMA disabled for Indirect mode] + Enabled: [1, DMA enabled for Indirect mode] + ABORT: + NotRequested: [0, No abort requested] + Requested: [1, Abort requested] + EN: + Disabled: [0, OCTOSPI disabled] + Enabled: [1, OCTOSPI enabled] + +DCR1: + MTYP: + MicronMode: + [ + 0, + "Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes", + ] + MacronixMode: + [ + 1, + "Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes", + ] + StandardMode: [2, Standard Mode] + MacronixRamMode: + [ + 3, + "Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping", + ] + HyperBusMemoryMode: + [4, "HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit DTR mode must be selected"] + HyperBusMode: + [ + 5, + "HyperBus register mode, addressing register space. The memory-mapped accesses in this mode must be non-cacheable, or Indirect read/write modes must be used", + ] + DEVSIZE: [0, 0x1F] + DLYBYP: + DelayBlockEnabled: + [ + 0, + "The internal sampling clock (called feedback clock) or the DQS data strobe external signal is delayed by the delay block (for more details on this block, refer to the dedicated section of the reference manual as it is not part of the OCTOSPI peripheral)", + ] + DelayBlockBypassed: + [ + 1, + "The delay block is bypassed, so the internal sampling clock or the DQS data strobe external signal is not affected by the delay block. The delay is shorter than when the delay block is not bypassed, even with the delay value set to minimum value in delay block", + ] + FRCK: + Disabled: [0, CLK is not free running] + Enabled: [1, CLK is free running (always provided)] + CKMODE: + Mode0: [0, CLK must stay low while NCS is high (chip-select released). This is referred to as Mode 0] + Mode3: [1, CLK must stay high while NCS is high (chip-select released). This is referred to as Mode 3] + +DCR2: + WRAPSIZE: + NoWrappingSupport: [0, Wrapped reads are not supported by the memory] + WrappingSize16: [2, External memory supports wrap size of 16 bytes] + WrappingSize32: [3, External memory supports wrap size of 32 bytes] + WrappingSize64: [4, External memory supports wrap size of 64 bytes] + WrappingSize128: [5, External memory supports wrap size of 128 bytes] + PRESCALER: [0, 0xFF] + +DCR3: + CSBOUND: [0, 0x1F] + "?~MAXTRAN": [0, 0xFF] + +DCR4: + REFRESH: [0, 0xFFFFFFFF] + +SR: + FLEVEL: [0, 0x3F] + BUSY: + Cleared: + [ + 0, + This bit is cleared automatically when the operation with the external device is finished and the FIFO is empty, + ] + Busy: [1, This bit is set when an operation is ongoing] + TOF: + Cleared: [0, This bit is cleared by writing 1 to CTOF] + Timeout: [1, This bit is set when timeout occurs] + SMF: + Cleared: [0, It is cleared by writing 1 to CSMF] + Matched: + [ + 1, + This bit is set in Automatic status-polling mode when the unmasked received data matches the corresponding bits in the match register (OCTOSPI_PSMAR), + ] + FTF: + ThresholdReached: [1, This bit is set when the FIFO threshold has been reached] + Cleared: [0, It is cleared automatically as soon as the threshold condition is no longer true] + TCF: + TransferCompleted: [1, This bit is set when the programmed number of data has been transferred] + Cleared: [0, This bit is cleared by writing 1 to CTCF] + TEF: + InvalidAddressAccessed: + [1, This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode] + Cleared: [0, This bit is cleared by writing 1 to CTEF] + +FCR: + CTOF: + Clear: [1, Writing 1 clears the TOF flag in the OCTOSPI_SR register] + CSMF: + Clear: [1, Writing 1 clears the SMF flag in the OCTOSPI_SR register] + CTCF: + Clear: [1, Writing 1 clears the TCF flag in the OCTOSPI_SR register] + CTEF: + Clear: [1, Writing 1 clears the TEF flag in the OCTOSPI_SR register] + +DLR: + DL: [0, 0xFFFFFFFF] + +AR: + ADDRESS: [0, 0xFFFFFFFF] + +DR: + DATA: [0, 0xFFFFFFFF] + +PSMKR: + MASK: [0, 0xFFFFFFFF] + +PSMAR: + MATCH: [0, 0xFFFFFFFF] + +PIR: + INTERVAL: [0, 0xFFFF] + +CCR: + "?~SIOO": + SendEveryTransaction: [0, Send instruction on every transaction] + SendOnlyFirstCmd: [1, Send instruction only for the first command] + DQSE: + Disabled: [0, DQS disabled] + Enabled: [1, DQS enabled] + DDTR: + Disabled: [0, DTR mode disabled for data phase] + Enabled: [1, DTR mode enabled for data phase] + DMODE: + NoData: [0, No data] + SingleLine: [1, Data on a single line] + TwoLines: [2, Data on two lines] + FourLines: [3, Data on four lines] + EightLines: [4, Data on eight lines] + ABSIZE: + Bits8: [0, 8-bit alternate bytes] + Bits16: [1, 16-bit alternate bytes] + Bits24: [2, 24-bit alternate bytes] + Bits32: [3, 32-bit alternate bytes] + ABDTR: + Disabled: [0, DTR mode disabled for alternate bytes phase] + Enabled: [1, DTR mode enabled for alternate bytes phase] + ABMODE: + NoAlternateBytes: [0, No alternate bytes] + SingleLine: [1, Alternate bytes on a single line] + TwoLines: [2, Alternate bytes on two lines] + FourLines: [3, Alternate bytes on four lines] + EightLines: [4, Alternate bytes on eight lines] + ADSIZE: + Bits8: [0, 8-bit address] + Bits16: [1, 16-bit address] + Bits24: [2, 24-bit address] + Bits32: [3, 32-bit address] + ADDTR: + Disabled: [0, DTR mode disabled for address phase] + Enabled: [1, DTR mode enabled for address phase] + ADMODE: + NoAddress: [0, No address] + SingleLine: [1, Address on a single line] + TwoLines: [2, Address on two lines] + FourLines: [3, Address on four lines] + EightLines: [4, Address on eight lines] + ISIZE: + Bits8: [0, 8-bit instruction] + Bits16: [1, 16-bit instruction] + Bits24: [2, 24-bit instruction] + Bits32: [3, 32-bit instruction] + IDTR: + Disabled: [0, DTR mode disabled for instruction phase] + Enabled: [1, DTR mode enabled for instruction phase] + IMODE: + NoInstruction: [0, No instruction] + SingleLine: [1, Instruction on a single line] + TwoLines: [2, Instruction on two lines] + FourLines: [3, Instruction on four lines] + EightLines: [4, Instruction on eight lines] + +TCR: + SSHIFT: + NoShift: [0, No shift] + HalfCycleShift: [1, 1/2 cycle shift] + DHQC: + NoDelay: [0, No delay hold] + QuarterCycleHold: [1, 1/4 cycle hold] + DCYC: [0, 0x1F] + +IR: + INSTRUCTION: [0, 0xFFFFFFFF] + +ABR: + ALTERNATE: [0, 0xFFFFFFFF] + +LPTR: + TIMEOUT: [0, 0xFFFF] + +W*CCR: + DQSE: + Disabled: [0, DQS disabled] + Enabled: [1, DQS enabled] + DDTR: + Disabled: [0, DTR mode disabled for data phase] + Enabled: [1, DTR mode enabled for data phase] + DMODE: + NoData: [0, No data] + SingleLine: [1, Data on a single line] + TwoLines: [2, Data on two lines] + FourLines: [3, Data on four lines] + EightLines: [4, Data on eight lines] + ABSIZE: + Bits8: [0, 8-bit alternate bytes] + Bits16: [1, 16-bit alternate bytes] + Bits24: [2, 24-bit alternate bytes] + Bits32: [3, 32-bit alternate bytes] + ABDTR: + Disabled: [0, DTR mode disabled for alternate bytes phase] + Enabled: [1, DTR mode enabled for alternate bytes phase] + ABMODE: + NoAlternateBytes: [0, No alternate bytes] + SingleLine: [1, Alternate bytes on a single line] + TwoLines: [2, Alternate bytes on two lines] + FourLines: [3, Alternate bytes on four lines] + EightLines: [4, Alternate bytes on eight lines] + ADSIZE: + Bits8: [0, 8-bit address] + Bits16: [1, 16-bit address] + Bits24: [2, 24-bit address] + Bits32: [3, 32-bit address] + ADDTR: + Disabled: [0, DTR mode disabled for address phase] + Enabled: [1, DTR mode enabled for address phase] + ADMODE: + NoAddress: [0, No address] + SingleLine: [1, Address on a single line] + TwoLines: [2, Address on two lines] + FourLines: [3, Address on four lines] + EightLines: [4, Address on eight lines] + ISIZE: + Bits8: [0, 8-bit instruction] + Bits16: [1, 16-bit instruction] + Bits24: [2, 24-bit instruction] + Bits32: [3, 32-bit instruction] + IDTR: + Disabled: [0, DTR mode disabled for instruction phase] + Enabled: [1, DTR mode enabled for instruction phase] + IMODE: + NoInstruction: [0, No instruction] + SingleLine: [1, Instruction on a single line] + TwoLines: [2, Instruction on two lines] + FourLines: [3, Instruction on four lines] + EightLines: [4, Instruction on eight lines] + +WPTCR: + SSHIFT: + NoShift: [0, No shift] + HalfCycleShift: [1, 1/2 cycle shift] + DHQC: + NoDelay: [0, No delay hold] + QuarterCycleHold: [1, 1/4 cycle hold] + DCYC: [0, 0x1F] + +WPIR: + INSTRUCTION: [0, 0xFFFFFFFF] + +WPABR: + ALTERNATE: [0, 0xFFFFFFFF] + +WTCR: + DCYC: [0, 0x1F] + +WIR: + INSTRUCTION: [0, 0xFFFFFFFF] + +WABR: + ALTERNATE: [0, 0xFFFFFFFF] + +HLCR: + TRWR: [0, 0xFF] + TACC: [0, 0xFF] + WZL: + Disabled: [0, Latency on write accesses] + Enabled: [1, No latency on write accesses] + LM: + Variable: [0, Variable initial latency] + Fixed: [1, Fixed latency] diff --git a/devices/fields/octospi/l4.yaml b/devices/fields/octospi/l4.yaml new file mode 100644 index 000000000..5277882fa --- /dev/null +++ b/devices/fields/octospi/l4.yaml @@ -0,0 +1,11 @@ +_include: + - common.yaml +CR: + FSEL: + FLASH1: [0, "FLASH 1 selected (data exchanged over IO[3:0])"] + FLASH2: [1, "FLASH 2 selected (data exchanged over IO[7:4])"] + DMM: + Disabled: [0, Dual-quad configuration disabled] + Enabled: [1, Dual-quad configuration enabled] +DCR1: + CSHT: [0, 0x3F] diff --git a/devices/fields/octospi/l5.yaml b/devices/fields/octospi/l5.yaml new file mode 100644 index 000000000..4d0e1aa1e --- /dev/null +++ b/devices/fields/octospi/l5.yaml @@ -0,0 +1,11 @@ +_include: + - common.yaml +CR: + FSEL: + FLASH1: [0, "FLASH 1 selected (data exchanged over IO[3:0])"] + FLASH2: [1, "FLASH 2 selected (data exchanged over IO[7:4])"] + DMM: + Disabled: [0, Dual-quad configuration disabled] + Enabled: [1, Dual-quad configuration enabled] +DCR1: + CSHT: [0, 7] diff --git a/devices/fields/octospi/u5.yaml b/devices/fields/octospi/u5.yaml new file mode 100644 index 000000000..ff1d47122 --- /dev/null +++ b/devices/fields/octospi/u5.yaml @@ -0,0 +1,11 @@ +_include: + - common.yaml +CR: + MSEL: + EXT1: [0, "External memory 1 selected (data exchanged over IO[3:0])"] + EXT2: [1, "External memory 2 selected (data exchanged over IO[7:4])"] + DMM: + Disabled: [0, Dual-memory configuration disabled] + Enabled: [1, Dual-memory configuration enabled] +DCR1: + CSHT: [0, 0x3F] diff --git a/devices/fields/opamp/opamp_f3.yaml b/devices/fields/opamp/opamp_f3.yaml new file mode 100644 index 000000000..3eed31ce1 --- /dev/null +++ b/devices/fields/opamp/opamp_f3.yaml @@ -0,0 +1,62 @@ +OPAMP: + OPAMP2_CSR: + OPAMP2EN: + Disabled: [0, OPAMP2 is disabled] + Enabled: [1, OPAMP2 is enabled] + FORCE_VP: + Normal: [0, Normal operating mode] + Calibration: [1, Calibration mode. Non-inverting input connected to calibration reference] + VP_SEL: + PB14: [1, PB14 used as OPAMP2 non-inverting input] + PB0: [2, PB0 used as OPAMP2 non-inverting input] + PA7: [3, PA7 used as OPAMP2 non-inverting input] + VM_SEL: + PC5: [0, PC5 (VM0) used as OPAMP2 inverting input] + PA5: [1, PA5 (VM1) used as OPAMP2 inverting input] + PGA: [2, Resistor feedback output (PGA mode)] + Follower: [3, Follower mode] + TCM_EN: + Disabled: [0, Timer controlled mux disabled] + Enabled: [1, Timer controlled mux enabled] + VMS_SEL: + PC5: [0, "PC5 (VM0) used as OPAMP2 inverting input when TCM_EN=1"] + PA5: [1, "PA5 (VM1) used as OPAMP2 inverting input when TCM_EN=1"] + VPS_SEL: + PB14: [1, "PB14 used as OPAMP2 non-inverting input when TCM_EN=1"] + PB0: [2, "PB0 used as OPAMP2 non-inverting input when TCM_EN=1"] + PA7: [3, "PA7 used as OPAMP2 non-inverting input when TCM_EN=1"] + CALON: + Disabled: [0, Calibration mode disabled] + Enabled: [1, Calibration mode enabled] + CALSEL: + Percent3_3: [0, "VREFOPAMP=3.3% VDDA"] + Percent10: [1, "VREFOPAMP=10% VDDA"] + Percent50: [2, "VREFOPAMP=50% VDDA"] + Percent90: [3, "VREFOPAMP=90% VDDA"] + PGA_GAIN: + Gain2: [0, Gain 2] + Gain4: [1, Gain 4] + Gain8: [2, Gain 8] + Gain16: [4, Gain 16] + Gain2_VM0: [8, "Gain 2, feedback connected to VM0"] + Gain4_VM0: [9, "Gain 4, feedback connected to VM0"] + Gain8_VM0: [10, "Gain 8, feedback connected to VM0"] + Gain16_VM0: [11, "Gain 16, feedback connected to VM0"] + Gain2_VM1: [12, "Gain 2, feedback connected to VM1"] + Gain4_VM1: [13, "Gain 4, feedback connected to VM1"] + Gain8_VM1: [14, "Gain 8, feedback connected to VM1"] + Gain16_VM1: [15, "Gain 16, feedback connected to VM1"] + USER_TRIM: + Disabled: [0, User trimming disabled] + Enabled: [1, User trimming enabled] + TRIMOFFSETP: [0, 31] + TRIMOFFSETN: [0, 31] + TSTREF: + Output: [0, VREFOPAMP2 is output] + NotOutput: [1, VREFOPAMP2 is not output] + OUTCAL: + Low: [0, "Non-inverting < inverting"] + High: [1, "Non-inverting > inverting"] + LOCK: + Unlocked: [0, Comparator CSR bits are read-write] + Locked: [1, Comparator CSR bits are read-only] diff --git a/devices/fields/opamp/opamp_g4_common.yaml b/devices/fields/opamp/opamp_g4_common.yaml new file mode 100644 index 000000000..787491e80 --- /dev/null +++ b/devices/fields/opamp/opamp_g4_common.yaml @@ -0,0 +1,117 @@ +OPAMP: + OPAMP?_CSR: + LOCK: + ReadWrite: [0, CSR is read-write] + ReadOnly: [1, "CSR is read-only, can only be cleared by system reset"] + CALOUT: [0, 1] + TRIMOFFSETN: [0, 31] + TRIMOFFSETP: [0, 31] + PGA_GAIN: + Gain2: [0, Gain 2] + Gain4: [1, Gain 4] + Gain8: [2, Gain 8] + Gain16: [3, Gain 16] + Gain32: [4, Gain 32] + Gain64: [5, Gain 64] + Gain2_InputVINM0: [8, "Gain 2, input/bias connected to VINM0 or inverting gain"] + Gain4_InputVINM0: [9, "Gain 4, input/bias connected to VINM0 or inverting gain"] + Gain8_InputVINM0: [10, "Gain 8, input/bias connected to VINM0 or inverting gain"] + Gain16_InputVINM0: [11, "Gain 16, input/bias connected to VINM0 or inverting gain"] + Gain32_InputVINM0: [12, "Gain 32, input/bias connected to VINM0 or inverting gain"] + Gain64_InputVINM0: [13, "Gain 64, input/bias connected to VINM0 or inverting gain"] + Gain2_FilteringVINM0: [16, "Gain 2, with filtering on VINM0"] + Gain4_FilteringVINM0: [17, "Gain 4, with filtering on VINM0"] + Gain8_FilteringVINM0: [18, "Gain 8, with filtering on VINM0"] + Gain16_FilteringVINM0: [19, "Gain 16, with filtering on VINM0"] + Gain32_FilteringVINM0: [20, "Gain 32, with filtering on VINM0"] + Gain64_FilteringVINM0: [21, "Gain 64, with filtering on VINM0"] + Gain2_InputVINM0FilteringVINM1: + [24, "Gain 2, input/bias connected to VINM0 with filtering on VINM1 or inverting gain"] + Gain4_InputVINM0FilteringVINM1: + [25, "Gain 4, input/bias connected to VINM0 with filtering on VINM1 or inverting gain"] + Gain8_InputVINM0FilteringVINM1: + [26, "Gain 8, input/bias connected to VINM0 with filtering on VINM1 or inverting gain"] + Gain16_InputVINM0FilteringVINM1: + [27, "Gain 16, input/bias connected to VINM0 with filtering on VINM1 or inverting gain"] + Gain32_InputVINM0FilteringVINM1: + [28, "Gain 32, input/bias connected to VINM0 with filtering on VINM1 or inverting gain"] + Gain64_InputVINM0FilteringVINM1: + [29, "Gain 64, input/bias connected to VINM0 with filtering on VINM1 or inverting gain"] + CALSEL: + Percent3_3: [0, 0.033*VDDA applied to OPAMP inputs during calibration] + Percent10: [1, 0.1*VDDA applied to OPAMP inputs during calibration] + Percent50: [2, 0.5*VDDA applied to OPAMP inputs during calibration] + Percent90: [3, 0.9*VDDA applied to OPAMP inputs during calibration] + CALON: + Disabled: [0, Calibration mode disabled] + Enabled: [1, Calibration mode enabled] + OPAINTOEN: + OutputPin: [0, Output is connected to the output Pin] + ADCChannel: [1, Output is connected internally to ADC channel] + OPAHSM: + Normal: [0, OpAmp in normal mode] + HighSpeed: [1, OpAmp in high speed mode] + VM_SEL: + VINM0: [0, VINM0 connected to VINM input] + VINM1: [1, VINM1 connected to VINM input] + PGA: [2, Feedback resistor connected to VINM (PGA mode)] + Output: [3, OpAmp output connected to VINM (Follower mode)] + USERTRIM: + Factory: [0, Factory trim used] + User: [1, User trim used] + FORCE_VP: + Normal: [0, Non-inverting input connected configured inputs] + CalibrationVerification: [1, Non-inverting input connected to calibration reference voltage] + OPAEN: + Disabled: [0, OpAmp disabled] + Enabled: [1, OpAmp enabled] + OPAMP?_TCMR: + LOCK: + ReadWrite: [0, TCMR is read-write] + ReadOnly: [1, "TCMR is read-only, can only be cleared by system reset"] + T20CM_EN: + Disabled: [0, Automatic input switch triggered by TIM20 disabled] + Enabled: [1, Automatic input switch triggered by TIM20 enabled] + T8CM_EN: + Disabled: [0, Automatic input switch triggered by TIM8 disabled] + Enabled: [1, Automatic input switch triggered by TIM8 enabled] + T1CM_EN: + Disabled: [0, Automatic input switch triggered by TIM1 disabled] + Enabled: [1, Automatic input switch triggered by TIM1 enabled] + + OPAMP1_CSR: + VP_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC3_CH1: [3, DAC3_CH1 connected to VINP input] + OPAMP1_TCMR: + VPS_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC3_CH1: [3, DAC3_CH1 connected to VINP input] + OPAMP2_CSR: + VP_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + VINP3: [3, VINP3 connected to VINP input] + OPAMP2_TCMR: + VPS_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + VINP3: [3, VINP3 connected to VINP input] + OPAMP3_CSR: + VP_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC3_CH2: [3, DAC3_CH2 connected to VINP input] + OPAMP3_TCMR: + VPS_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC3_CH2: [3, DAC3_CH2 connected to VINP input] diff --git a/devices/fields/opamp/opamp_g4_opamp4_5.yaml b/devices/fields/opamp/opamp_g4_opamp4_5.yaml new file mode 100644 index 000000000..f33fe2990 --- /dev/null +++ b/devices/fields/opamp/opamp_g4_opamp4_5.yaml @@ -0,0 +1,25 @@ +OPAMP: + OPAMP4_CSR: + VP_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC4_CH1: [3, DAC4_CH1 connected to VINP input] + OPAMP4_TCMR: + VPS_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC4_CH1: [3, DAC4_CH1 connected to VINP input] + OPAMP5_CSR: + VP_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC4_CH2: [3, DAC4_CH2 connected to VINP input] + OPAMP5_TCMR: + VPS_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC4_CH2: [3, DAC4_CH2 connected to VINP input] diff --git a/devices/fields/opamp/opamp_g4_opamp6.yaml b/devices/fields/opamp/opamp_g4_opamp6.yaml new file mode 100644 index 000000000..42cade876 --- /dev/null +++ b/devices/fields/opamp/opamp_g4_opamp6.yaml @@ -0,0 +1,13 @@ +OPAMP: + OPAMP6_CSR: + VP_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC3_CH1: [3, DAC3_CH1 connected to VINP input] + OPAMP6_TCMR: + VPS_SEL: + VINP0: [0, VINP0 connected to VINP input] + VINP1: [1, VINP1 connected to VINP input] + VINP2: [2, VINP2 connected to VINP input] + DAC3_CH1: [3, DAC3_CH1 connected to VINP input] diff --git a/devices/fields/opamp/opamp_l4.yaml b/devices/fields/opamp/opamp_l4.yaml new file mode 100644 index 000000000..145b62947 --- /dev/null +++ b/devices/fields/opamp/opamp_l4.yaml @@ -0,0 +1,45 @@ +OPAMP: + OPAMP?_CSR: + CALOUT: [0, 1] + PGA_GAIN: + Gain2: [0, Gain 2] + Gain4: [1, Gain 4] + Gain8: [2, Gain 8] + Gain16: [3, Gain 16] + CALSEL: + NMOS: [0, 0.2V applied to OPAMP inputs during calibration] + PMOS: [1, VDDA-0.2V applied to OPAMP inputs during calibration"] + CALON: + Disabled: [0, Normal mode] + Enabled: [1, Calibration mode] + VP_SEL: + GPIO: [0, GPIO connectet to VINP] + DAC: [1, DAC connected to VPINP] + VM_SEL: + GPIO: [0, GPIO connectet to VINM] + LOW_LEAKAGE: [1, Low leakage inputs connecte (only available in certen BGA cases] + PGA_MODE: [2, OPAMP in PGA mode] + USERTRIM: + Factory: [0, Factory trim used] + User: [1, User trim used] + OPAMODE: + PGA_DISABLED: [0, internal PGA diabled] + PGA_ENABLED: [2, "internal PGA enabled, gain programmed in PGA_GAIN"] + FOLLOWER: [3, internal follower] + OPALPM: + NORMAL: [0, OpAmp in normal mode] + LOW: [1, OpAmp in low power mode] + OPAEN: + Disabled: [0, OpAmp disabled] + Enabled: [1, OpAmp enabled] + OPAMP?_OTR: + TRIMOFFSETN: [0, 31] + TRIMOFFSETP: [0, 31] + OPAMP?_LPOTR: + TRIMLPOFFSETN: [0, 31] + TRIMLPOFFSETP: [0, 31] + + OPAMP1_CSR: + OPA_RANGE: + LOW: [0, "low range (VDDA < 2.4V"] + HIGH: [1, "low range (VDDA >2.4V"] diff --git a/devices/fields/pka/pka.yaml b/devices/fields/pka/pka.yaml new file mode 100644 index 000000000..74de00996 --- /dev/null +++ b/devices/fields/pka/pka.yaml @@ -0,0 +1,65 @@ +CR: + ADDRERRIE: + Disabled: [0, No interrupt is generated when ADDRERRF flag is set in PKA_SR] + Enabled: [1, An interrupt is generated when ADDRERRF flag is set in PKA_SR] + RAMERRIE: + Disabled: [0, No interrupt is generated when RAMERRF flag is set in PKA_SR] + Enabled: [1, An interrupt is generated when RAMERRF flag is set in PKA_SR] + PROCENDIE: + Disabled: [0, No interrupt is generated when PROCENDF flag is set in PKA_SR] + Enabled: [1, An interrupt is generated when PROCENDF flag is set in PKA_SR] + MODE: + MontgomeryCompExp: [0b000000, Montgomery parameter computation then modular exponentiation] + MontgomeryComp: [0b000001, Montgomery parameter computation only] + MontgomeryExp: [0b000010, Modular exponentiation only (Montgomery parameter must be loaded first)] + MontgomeryCompScalar: [0b100000, Montgomery parameter computation then ECC scalar multiplication] + MontgomeryScalar: [0b100010, ECC scalar multiplication only (Montgomery parameter must be loaded first)] + ECDSASign: [0b100100, ECDSA sign] + ECDSAVerif: [0b100110, ECDSA verification] + Elliptic: [0b101000, Point on elliptic curve Fp check] + RSA: [0b000111, RSA CRT exponentiation] + ModularInv: [0b001000, Modular inversion] + ArithmeticAdd: [0b001001, Arithmetic addition] + ArithmeticSub: [0b001010, Arithmetic subtraction] + ArithmeticMul: [0b001011, Arithmetic multiplication] + ArithmeticComp: [0b001100, Arithmetic comparison] + ModularRed: [0b001101, Modular reduction] + ModularAdd: [0b001110, Modular addition] + ModularSub: [0b001111, Modular subtraction] + ModularMul: [0b010000, Montgomery multiplication] + START: + _write: + Start: + [ + 1, + "Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands and data already written to the PKA RAM - This bit is always read as 0", + ] + EN: + Disabled: [0, Disable PKA] + Enabled: [1, Enable PKA] + +SR: + ADDRERRF: + NoError: [0, No error] + Error: [1, Address access is out of range (unmapped address)] + RAMERRF: + NoError: [0, No error] + Error: + [ + 1, + An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress), + ] + PROCENDF: + InProgress: [0, Operation in progress] + Completed: [1, PKA operation is completed - set when BUSY is deasserted] + BUSY: + Idle: [0, No operation in pgoress] + Busy: [1, Operation in progress] + +CLRFR: + ADDRERRFC: + Clear: [1, Clear ADDRERRF flag] + RAMERRFC: + Clear: [1, Clear RAMERRF flag] + PROCENDFC: + Clear: [1, Clear PROCENDF flag] diff --git a/devices/fields/pssi/pssi.yaml b/devices/fields/pssi/pssi.yaml new file mode 100644 index 000000000..6d4c6f432 --- /dev/null +++ b/devices/fields/pssi/pssi.yaml @@ -0,0 +1,93 @@ +CR: + OUTEN: + ReceiveMode: [0, Data is input synchronously with PSSI_PDCK] + TransmitMode: [1, Data is output synchronously with PSSI_PDCK] + + DMAEN: + Disabled: + [ + 0, + DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled., + ] + Enabled: + [ + 1, + DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR, + ] + + DERDYCFG: + Disabled: [0, PSSI_DE and PSSI_RDY both disabled] + Rdy: [1, Only PSSI_RDY enabled] + De: [2, Only PSSI_DE enabled] + RdyDeAlt: [3, Both PSSI_RDY and PSSI_DE alternate functions enabled] + RdyDe: [4, Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin] + RdyRemapped: [5, "Only PSSI_RDY function enabled, but mapped to PSSI_DE pin"] + DeRemapped: [6, "Only PSSI_DE function enabled, but mapped to PSSI_RDY pin"] + RdyDeBidi: [7, Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin] + + ENABLE: + Disabled: [0, PSSI disabled] + Enabled: [1, PSSI enabled] + + EDM: + BitWidth8: [0, Interface captures 8-bit data on every parallel data clock] + BitWidth16: [3, The interface captures 16-bit data on every parallel data clock] + + RDYPOL: + ActiveLow: [0, PSSI_RDY active low (0 indicates that the receiver is ready to receive)] + ActiveHigh: [1, PSSI_RDY active high (1 indicates that the receiver is ready to receive)] + + DEPOL: + ActiveLow: [0, PSSI_DE active low (0 indicates that data is valid)] + ActiveHigh: [1, PSSI_DE active high (1 indicates that data is valid)] + + CKPOL: + FallingEdge: [0, Falling edge active for inputs or rising edge active for outputs] + RisingEdge: [1, Rising edge active for inputs or falling edge active for outputs] + +SR: + RTT1B: + Ready: + [ + 1, + "FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO", + ] + NotReady: [0, FIFO is not ready for a 1-byte transfer] + + RTT4B: + Ready: + [ + 1, + "FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO", + ] + NotReady: [0, FIFO is not ready for a four-byte transfer] + +RIS: + OVR_RIS: + Cleared: [0, No overrun/underrun occurred] + Occurred: + [ + 1, + "An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode. This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR", + ] + +IER: + OVR_IE: + Disabled: [0, No interrupt generation] + Enabled: [1, An interrupt is generated if either an overrun or an underrun error occurred] + +MIS: + OVR_MIS: + Disabled: [0, No interrupt is generated when an overrun/underrun error occurs] + Enabled: + [ + 1, + An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER, + ] + +ICR: + OVR_ISC: + Clear: [1, Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS] + +DR: + BYTE?: [0, 0xFF] diff --git a/devices/fields/pwr/f4.yaml b/devices/fields/pwr/f4.yaml new file mode 100644 index 000000000..c8aeff83f --- /dev/null +++ b/devices/fields/pwr/f4.yaml @@ -0,0 +1,51 @@ +CR: + FPDS: + Idle: [0, Flash memory not in power-down when the device is in Stop mode] + PowerDown: [1, Flash memory in power-down when the device is in Stop mode] + DBP: + Protected: [0, Access to RTC and RTC Backup registers and backup SRAM disabled] + Writable: [1, Access to RTC and RTC Backup registers and backup SRAM enabled] + PLS: [0, 7] + PVDE: + Disabled: [0, PVD disabled] + Enabled: [1, PVD enabled] + CSBF: + _read: + Zero: [0, This bit is always read as 0] + _write: + Clear: [1, Clear the SBF Standby Flag] + CWUF: + _read: + Zero: [0, This bit is always read as 0] + _write: + Clear: [1, Clear the WUPF Wakeup Flag **after 2 System clock cycles**] + PDDS: + EnterStop: [0, Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the LPDS bit] + EnterStandby: [1, Enter Standby mode when the CPU enters deepsleep] + LPDS: + Main: [0, Main voltage regulator ON during Stop mode] + LowPower: [1, Low-power voltage regulator ON during Stop mode] + +CSR: + VOSRDY: + NotReady: [0, Not ready] + Ready: [1, Ready] + BRE: + Disabled: [0, Backup regulator disabled] + Enabled: [1, Backup regulator enabled] + BRR: + NotReady: [0, Backup Regulator not ready] + Ready: [1, Backup Regulator ready] + PVDO: + Higher: [0, "Vdd is higher than the PVD threshold selected with the PLS[2:0] bits"] + Lower: [1, "Vdd is lower than the PVD threshold selected with the PLS[2:0] bits"] + SBF: + InStandby: [0, Device has not been in Standby mode] + NotInStandby: [1, Device has been in Standby mode] + WUF: + NotOccurred: [0, No wakeup event occurred] + Occurred: + [ + 1, + "A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)", + ] diff --git a/devices/fields/pwr/pwr_f401.yaml b/devices/fields/pwr/pwr_f401.yaml new file mode 100644 index 000000000..945f12584 --- /dev/null +++ b/devices/fields/pwr/pwr_f401.yaml @@ -0,0 +1,32 @@ +# the frame was extract from stm32f469.svd.patched +_include: + - f4.yaml +CR: + VOS: + Scale3: [1, Scale 3 mode] + Scale2: [2, Scale 2 mode] + ADCDC1: [0, 1] + MRLVDS: + "On": [0, Main regulator ON when the device is in Stop mode] + UnderDrive: + [1, Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode] + LPLVDS: + "On": [0, Low-power regulator ON if LPDS bit is set when the device is in Stop mode] + UnderDrive: + [ + 1, + Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in power-down when the device is in Stop under-drive mode, + ] + +CSR: + EWUP: + GPIO: + [ + 0, + WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP pin wakes-up the system from Standby mode), + ] diff --git a/devices/fields/pwr/pwr_f405_f415_f407_f417.yaml b/devices/fields/pwr/pwr_f405_f415_f407_f417.yaml new file mode 100644 index 000000000..8b2375c27 --- /dev/null +++ b/devices/fields/pwr/pwr_f405_f415_f407_f417.yaml @@ -0,0 +1,20 @@ +# the frame was extract from stm32f469.svd.patched +_include: + - f4.yaml +CR: + VOS: + Scale2: [0, Scale 2 mode] + Scale1: [1, Scale 1 mode (default value at reset)] + +CSR: + EWUP: + GPIO: + [ + 0, + WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP pin wakes-up the system from Standby mode), + ] diff --git a/devices/fields/pwr/pwr_f410_f412_f413_f423.yaml b/devices/fields/pwr/pwr_f410_f412_f413_f423.yaml new file mode 100644 index 000000000..78486453d --- /dev/null +++ b/devices/fields/pwr/pwr_f410_f412_f413_f423.yaml @@ -0,0 +1,60 @@ +# the frame was extract from stm32f469.svd.patched +_include: + - f4.yaml +CR: + FISSR: + Run: [0, Flash Interface clock run (Default value)] + "Off": [1, Flash Interface clock off] + FMSSR: + Standard: [0, Flash standard mode (Default value)] + Forced: [1, Flash forced to be in STOP or DeepPower Down mode (depending of FPDS value bit) by hardware] + VOS: + Scale3: [1, "Scale 3 mode <= 64 MHz"] + Scale2: [2, "Scale 2 mode (reset value) <= 84 MHz"] + Scale1: [3, "Scale 1 mode <= 100 MHz"] + ADCDC1: [0, 1] + MRLVDS: + Scale3: [0, Main regulator in Voltage scale 3 when the device is in Stop mode] + LowVoltage: [1, Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is in Stop mode] + LPLVDS: + "On": [0, Low-power regulator on if LPDS bit is set when the device is in Stop mode] + UnderDrive: + [ + 1, + Low-power regulator in Low Voltage and Flash memory in Deep Sleep mode if LPDS bit is set when device is in Stop mode, + ] + +CSR: + EWUP1: + GPIO: + [ + 0, + WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP1 pin wakes-up the system from Standby mode), + ] + EWUP2: + GPIO: + [ + 0, + WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP2 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP2 pin wakes-up the system from Standby mode), + ] + EWUP3: + GPIO: + [ + 0, + WKUP3 pin is used for general purpose I/O. An event on the WKUP3 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP3 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP3 pin wakes-up the system from Standby mode), + ] diff --git a/devices/fields/pwr/pwr_f411.yaml b/devices/fields/pwr/pwr_f411.yaml new file mode 100644 index 000000000..5735b1866 --- /dev/null +++ b/devices/fields/pwr/pwr_f411.yaml @@ -0,0 +1,38 @@ +# the frame was extract from stm32f469.svd.patched +_include: + - f4.yaml +CR: + FISSR: + Run: [0, Flash Interface clock run (Default value)] + "Off": [1, Flash Interface clock off] + FMSSR: + Standard: [0, Flash standard mode (Default value)] + Forced: [1, Flash forced to be in STOP or DeepPower Down mode (depending of FPDS value bit) by hardware] + VOS: + Scale3: [1, "Scale 3 mode <= 64 MHz"] + Scale2: [2, "Scale 2 mode (reset value) <= 84 MHz"] + Scale1: [3, "Scale 1 mode <= 100 MHz"] + ADCDC1: [0, 1] + MRLVDS: + Scale3: [0, Main regulator in Voltage scale 3 when the device is in Stop mode] + LowVoltage: [1, Main regulator in Low Voltage and Flash memory in Deep Sleep mode when the device is in Stop mode] + LPLVDS: + "On": [0, Low-power regulator on if LPDS bit is set when the device is in Stop mode] + UnderDrive: + [ + 1, + Low-power regulator in Low Voltage and Flash memory in Deep Sleep mode if LPDS bit is set when device is in Stop mode, + ] + +CSR: + EWUP: + GPIO: + [ + 0, + WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP pin wakes-up the system from Standby mode), + ] diff --git a/devices/fields/pwr/pwr_f427_f437_f429_f439.yaml b/devices/fields/pwr/pwr_f427_f437_f429_f439.yaml new file mode 100644 index 000000000..4b8e81f74 --- /dev/null +++ b/devices/fields/pwr/pwr_f427_f437_f429_f439.yaml @@ -0,0 +1,51 @@ +# the frame was extract from stm32f469.svd.patched +_include: + - f4.yaml +CR: + UDEN: + Disabled: [0, Under-drive disable] + Enabled: [3, Under-drive enable] + ODSWEN: + Disabled: [0, Over-drive switching disabled] + Enabled: [1, Over-drive switching enabled] + ODEN: + Disabled: [0, Over-drive disabled] + Enabled: [1, Over-drive enabled] + VOS: + Scale3: [1, Scale 3 mode] + Scale2: [2, Scale 2 mode] + Scale1: [3, Scale 1 mode] + ADCDC1: [0, 1] + MRUDS: + "On": [0, Main regulator ON when the device is in Stop mode] + UnderDrive: + [1, Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode] + LPUDS: + "On": [0, Low-power regulator ON if LPDS bit is set when the device is in Stop mode] + UnderDrive: + [ + 1, + Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in power-down when the device is in Stop under-drive mode, + ] + +CSR: + UDRDY: + NotReady: [0, Under-drive is disabled] + Ready: [3, Under-drive mode is activated in Stop mode] + ODSWRDY: + NotReady: [0, Over-drive mode is not active] + Ready: [1, Over-drive mode is active on digital area on 1.2 V domain] + ODRDY: + NotReady: [0, Over-drive mode not ready] + Ready: [1, Over-drive mode ready] + EWUP: + GPIO: + [ + 0, + WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP pin wakes-up the system from Standby mode), + ] diff --git a/devices/fields/pwr/pwr_f446.yaml b/devices/fields/pwr/pwr_f446.yaml new file mode 100644 index 000000000..81f605bac --- /dev/null +++ b/devices/fields/pwr/pwr_f446.yaml @@ -0,0 +1,68 @@ +# the frame was extract from stm32f469.svd.patched +_include: + - f4.yaml +CR: + FISSR: + Run: [0, Flash Interface clock run (Default value)] + "Off": [1, Flash Interface clock off] + FMSSR: + Standard: [0, Flash standard mode (Default value)] + Forced: [1, Flash forced to be in STOP or DeepPower Down mode (depending of FPDS value bit) by hardware] + UDEN: + Disabled: [0, Under-drive disable] + Enabled: [3, Under-drive enable] + ODSWEN: + Disabled: [0, Over-drive switching disabled] + Enabled: [1, Over-drive switching enabled] + ODEN: + Disabled: [0, Over-drive disabled] + Enabled: [1, Over-drive enabled] + VOS: + Scale3: [1, Scale 3 mode] + Scale2: [2, Scale 2 mode] + Scale1: [3, Scale 1 mode (reset value)] + ADCDC1: [0, 1] + MRUDS: + "On": [0, Main regulator ON when the device is in Stop mode] + UnderDrive: + [1, Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode] + LPUDS: + "On": [0, Low-power regulator ON if LPDS bit is set when the device is in Stop mode] + UnderDrive: + [ + 1, + Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in power-down when the device is in Stop under-drive mode, + ] + +CSR: + UDRDY: + NotReady: [0, Under-drive is disabled] + Ready: [3, Under-drive mode is activated in Stop mode] + ODSWRDY: + NotReady: [0, Over-drive mode is not active] + Ready: [1, Over-drive mode is active on digital area on 1.2 V domain] + ODRDY: + NotReady: [0, Over-drive mode not ready] + Ready: [1, Over-drive mode ready] + EWUP1: + GPIO: + [ + 0, + WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP pin wakes-up the system from Standby mode), + ] + EWUP2: + GPIO: + [ + 0, + WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP2 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP2 pin wakes-up the system from Standby mode), + ] diff --git a/devices/fields/pwr/pwr_f469_f479.yaml b/devices/fields/pwr/pwr_f469_f479.yaml new file mode 100644 index 000000000..3c1205caa --- /dev/null +++ b/devices/fields/pwr/pwr_f469_f479.yaml @@ -0,0 +1,51 @@ +# the frame was extract from stm32f469.svd.patched +_include: + - f4.yaml +CR: + UDEN: + Disabled: [0, Under-drive disable] + Enabled: [3, Under-drive enable] + ODSWEN: + Disabled: [0, Over-drive switching disabled] + Enabled: [1, Over-drive switching enabled] + ODEN: + Disabled: [0, Over-drive disabled] + Enabled: [1, Over-drive enabled] + VOS: + Scale3: [1, Scale 3 mode] + Scale2: [2, Scale 2 mode] + Scale1: [3, Scale 1 mode] + ADCDC1: [0, 1] + MRLVDS: + "On": [0, Main regulator ON when the device is in Stop mode] + UnderDrive: + [1, Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode] + LPLVDS: + "On": [0, Low-power regulator ON if LPDS bit is set when the device is in Stop mode] + UnderDrive: + [ + 1, + Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in power-down when the device is in Stop under-drive mode, + ] + +CSR: + UDRDY: + NotReady: [0, Under-drive is disabled] + Ready: [3, Under-drive mode is activated in Stop mode] + ODSWRDY: + NotReady: [0, Over-drive mode is not active] + Ready: [1, Over-drive mode is active on digital area on 1.2 V domain] + ODRDY: + NotReady: [0, Over-drive mode not ready] + Ready: [1, Over-drive mode ready] + EWUP: + GPIO: + [ + 0, + WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode, + ] + WakeUp: + [ + 1, + WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge or falling on WKUP pin wakes-up the system from Standby mode), + ] diff --git a/devices/fields/pwr/pwr_f7.yaml b/devices/fields/pwr/pwr_f7.yaml new file mode 100644 index 000000000..ae35fe9ec --- /dev/null +++ b/devices/fields/pwr/pwr_f7.yaml @@ -0,0 +1,7 @@ +_include: pwr_v2.yaml + +CR1: + VOS: + SCALE1: [3, Scale 1 mode (reset value)] + SCALE2: [2, Scale 2 mode] + SCALE3: [1, Scale 3 mode] diff --git a/devices/fields/pwr/pwr_h5.yaml b/devices/fields/pwr/pwr_h5.yaml new file mode 100644 index 000000000..2c31310f4 --- /dev/null +++ b/devices/fields/pwr/pwr_h5.yaml @@ -0,0 +1,173 @@ +PMCR: + SRAM1SO: + Kept: [0, AHB RAM1 content is kept in Stop mode] + Lost: [1, AHB RAM1 content is lost in Stop mode] + SRAM2*: + Kept: [0, AHB RAM2 content is kept in Stop mode] + Lost: [1, AHB RAM2 content is lost in Stop mode] + AVD_READY: + NotReady: [0, Peripheral analog voltage VDDA not ready (default)] + Ready: [1, Peripheral analog voltage VDDA ready] + BOOSTE: + Disabled: [0, Booster disabled] + Enabled: [1, "Booster enabled if analog voltage ready (AVD_READY = 1)"] + FLPS: + NormalMode: [0, Flash memory remains in normal mode when the system enters Stop mode] + LowPowerMode: [1, Flash memory enters low-power mode when the system enters Stop mode] + CSSF: + Clear: [1, STOPF and SBF flags cleared] + SVOS: + Scale5: [1, SVOS5 scale 5] + Scale4: [2, SVOS4 scale 4] + Scale3: [3, SVOS3 scale 3] + LPMS: + StopMode: [0, Keeps Stop mode when entering DeepSleep] + StandbyMode: [1, Allows Standby mode when entering DeepSleep] + +PMSR: + SBF: + _read: + NoStandbyMode: [0, System has not been in standby mode] + StandbyModePreviouslyEntered: [1, System has been in Standby mode] + STOPF: + _read: + NoStopMode: [0, System has not been in stop mode] + StopModePreviouslyEntered: [1, System has been in Stop mode] + +VOSCR: + VOS: + VOS3: [0, Scale 3 (default)] + VOS2: [2, Scale 2] + VOS1: [1, Scale 1] + VOS0: [3, Scale 0] + +VOSSR: + ACTVOS: + _read: + VOS3: [0, VOS3 (lowest power)] + VOS2: [1, VOS2] + VOS1: [2, VOS1] + VOS0: [3, VOS0 (highest frequency)] + ACTVOSRDY: + _read: + NotReady: [0, "VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]"] + Ready: [1, "VCORE is equal to the current voltage scaling provided by ACTVOS[1:0]"] + VOSRDY: + _read: + NotReady: [0, "Not ready, voltage level below VOS selected level"] + Ready: [1, "Ready, voltage level at or above VOS selected level"] + +BDCR: + VBRS: + Charge5k: [0, Charge VBAT through a 5 kΩ resistor] + Charge1k5: [1, Charge VBAT through a 1.5 kΩ resistor] + VBE: + Disabled: [0, VBAT battery charging disabled] + Enabled: [1, VBAT battery charging enabled] + MONEN: + Disabled: [0, Backup domain voltage and temperature monitoring disabled] + Enabled: [1, " Backup domain voltage and temperature monitoring enabled"] + BREN: + Disabled: [0, "Backup regulator enabled; backup RAM content lost in Standby and VBAT modes"] + Enabled: [1, "Backup regulator disabled; backup RAM content preserved in Standby and VBAT modes"] + +DBPCR: + DBP: + Disabled: [0, Write access to backup domain disabled] + Enabled: [1, Write access to backup domain enabled] + +BDSR: + "*H": + _read: + BelowThreshold: [0, Below high threshold level] + AboveThreshold: [1, Equal to or Above high threshold level] + "*L": + _read: + AboveThreshold: [0, Above low threshold level] + BelowThreshold: [1, Equal to or below low threshold level] + + BRRDY: + _read: + NotReady: [0, Backup regulator not ready] + Ready: [1, Backup regulator ready] + +SCCR: + LDOEN: + _read: + Disabled: [0, Package does not use LDO regulator] + Enabled: [1, Package uses LDO regulator] + BYPASS: + InternalRegulator: [0, Power management unit normal operation. Use the internal regulator.] + Bypassed: [1, Power management unit bypassed. Use the external power.] + +VMCR: + ALS: + AvdLevel0: [0, AVD level0 (VAVD0 around 1.7 V)] + AvdLevel1: [1, AVD level1 (VAVD1 around 2.1 V)] + AvdLevel2: [2, AVD level2 (VAVD2 around 2.5 V)] + AvdLevel3: [3, AVD level3 (VAVD3 around 2.8 V)] + AVDEN: + Disabled: [0, Peripheral voltage monitor on VDDA disabled] + Enabled: [1, Peripheral voltage monitor on VDDA enabled] + PLS: + PvdLevel0: [0b000, PVD level0 (VPVD0 around 1.95 V)] + PvdLevel1: [0b001, PVD level1 (VPVD1 around 2.1 V)] + PvdLevel2: [0b010, PVD level2 (VPVD2 around 2.25 V)] + PvdLevel3: [0b011, PVD level3 (VPVD3 around 2.4 V)] + PvdLevel4: [0b100, PVD level4 (VPVD4 around 2.55 V)] + PvdLevel5: [0b101, PVD level5 (VPVD5 around 2.7 V)] + PvdLevel6: [0b110, PVD level6 (VPVD6 around 2.85 V)] + PvdIn: [0b111, PVD_IN pin] + PVDE: + Disabled: [0, PVD Disabled] + Enabled: [1, PVD Enabled] + +VMSR: + PVDO: + _read: + AboveThreshold: [0, "VDD is equal or higher than the PVD threshold selected through the PLS[2:0] bits."] + BelowThreshold: [1, "VDD is lower than the PVD threshold selected through the PLS[2:0] bits"] + VDDIO2RDY: + _read: + BelowThreshold: [0, VDDIO2 is below the threshold of the VDDIO2 voltage monitor] + AboveThreshold: [1, VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor] + AVDO: + _read: + AboveThreshold: [0, "VDDA is equal or higher than the AVD threshold selected with the ALS[2:0] bits"] + BelowThreshold: [1, "VDDA is lower than the AVD threshold selected with the ALS[2:0] bits"] + +WUSCR: + CWUF?: + _write: + Clear: [1, Writing 1 clears the WUFx wakeup pin flag (bit is cleared to 0 by hardware)] + +WUSR: + WUF?: + _read: + NoEventOccurred: [0, No wakeup event occurred] + EventOccurred: [1, A wakeup event received from WUFx pin] + +WUCR: + WUPPUPD?: + NoPull: [0, No pull-up or pull-down] + PullUp: [1, Pull-up] + PullDown: [2, Pull-down] + WUPP?: + HighLevel: [0, Detection on high level] + LowLevel: [1, Detection on low level] + WUPEN?: + Disabled: [0, An event on WUPx pin does not wakeup the system from Standby mode] + Enabled: [1, A rising or falling edge on WUPx pin wakes up the system from Standby mode] + +IORETR: + JTAGIORETEN: + Disabled: [0, IO Retention mode is disabled] + Enabled: [1, " IO Retention mode is enabled"] + IORETEN: + Disabled: [0, IO Retention mode is disabled] + Enabled: [1, " IO Retention mode is enabled"] + +PRIVCFGR: + NSPRIV: + Unprivileged: [0, Read and write to PWR functions can be done by privileged or unprivileged access] + Privileged: [1, Read and write to PWR functions can be done by privileged access only] diff --git a/devices/fields/pwr/pwr_l0.yaml b/devices/fields/pwr/pwr_l0.yaml new file mode 100644 index 000000000..5e7af631d --- /dev/null +++ b/devices/fields/pwr/pwr_l0.yaml @@ -0,0 +1,108 @@ +# Power Controller for L0 Family + +_include: + - pwr_v1.yaml + +CR: + LPRUN: + MAIN_MODE: [0, Voltage regulator in Main mode in Low-power run mode] + LOW_POWER_MODE: [1, Voltage regulator in low-power mode in Low-power run mode] + DS_EE_KOFF: + NVMWakeUp: [0, NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set] + NVMSleep: [1, NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set)] + VOS: + V1_8: [1, 1.8 V (range 1)] + V1_5: [2, 1.5 V (range 2)] + V1_2: [3, 1.2 V (range 3)] + FWU: + Disabled: [0, Low-power modes exit occurs only when VREFINT is ready] + Enabled: [1, VREFINT start up time is ignored when exiting low-power modes] + ULP: + Enabled: [0, VREFINT is on in low-power mode] + Disabled: [1, VREFINT is off in low-power mode] + DBP: + Disabled: [0, "Access to RTC, RTC Backup and RCC CSR registers disabled"] + Enabled: [1, "Access to RTC, RTC Backup and RCC CSR registers enabled"] + "?~PLS": + V1_9: [0, 1.9 V] + V2_1: [1, 2.1 V] + V2_3: [2, 2.3 V] + V2_5: [3, 2.5 V] + V2_7: [4, 2.7 V] + V2_9: [5, 2.9 V] + V3_1: [6, 3.1 V] + External: [7, External input analog voltage (Compare internally to VREFINT)] + "?~PVDE": + Disabled: [0, PVD Disabled] + Enabled: [1, PVD Enabled] + CSBF: + _write: + Clear: [1, Clear the SBF Standby flag] + CWUF: + _write: + Clear: [1, Clear the WUF Wakeup flag after 2 system clock cycles] + LPSDSR: + MAIN_MODE: [0, Voltage regulator on during Deepsleep/Sleep/Low-power run mode] + LOW_POWER_MODE: [1, Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode] +CSR: + EWUP3: + Disabled: + [ + 0, + WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode), + ] + EWUP2: + Disabled: + [ + 0, + WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode), + ] + EWUP1: + Disabled: + [ + 0, + WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode), + ] + REGLPF: + _read: + Ready: [0, Regulator is ready in Main mode] + NotReady: [1, Regulator voltage is in low-power mode] + VOSF: + _read: + Ready: [0, Regulator is ready in the selected voltage range] + NotReady: [1, Regulator voltage output is changing to the required VOS level] + VREFINTRDYF: + _read: + NotReady: [0, VREFINT is OFF] + Ready: [1, VREFINT is ready] + "?~PVDO": + _read: + AboveThreshold: [0, "VDD is higher than the PVD threshold selected with the PLS[2:0] bits"] + BelowThreshold: [1, "VDD is lower than the PVD threshold selected with the PLS[2:0] bits"] + SBF: + _read: + NoStandbyEvent: [0, Device has not been in Standby mode] + StandbyEvent: [1, Device has been in Standby mode] + WUF: + _read: + NoWakeupEvent: [0, No wakeup event occurred] + WakeupEvent: + [ + 1, + "A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)", + ] diff --git a/devices/fields/pwr/pwr_l4+.yaml b/devices/fields/pwr/pwr_l4+.yaml new file mode 100644 index 000000000..f7c4b4634 --- /dev/null +++ b/devices/fields/pwr/pwr_l4+.yaml @@ -0,0 +1,163 @@ +CR1: + LPR: + MainMode: [0, Main Mode] + LowPowerMode: [1, Low Power Mode] + VOS: + Range1: [1, Range 1] + Range2: [2, Range 1] + DBP: + Disabled: [0, Access to RTC and Backup registers disabled] + Enabled: [1, Access to RTC and Backup registers enabled] + RRSTP: + Disabled: [0, SRAM3 is powered off in Stop 2 mode (SRAM3 content is lost)] + Enabled: [1, SRAM3 is powered in Stop 2 mode (RAM3 content is kept)] + LPMS: + Stop0: [0, Stop 0 mode] + Stop1: [1, Stop 1 mode] + Stop2: [2, Stop 2 mode] + Standby: [3, Standby mode] + Shutdown: [4, Shutdown mode] + +CR2: + USV: + NotPresent: [0, VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply] + Valid: [1, VDDUSB is valid] + IOSV: + NotPresent: [0, VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply] + Valid: [1, VDDIO2 is valid] + PVME4: + Disabled: [0, PVM4 (VDDA monitoring vs. 2.2V threshold) disable] + Enabled: [1, PVM4 (VDDA monitoring vs. 2.2V threshold) enable] + PVME3: + Disabled: [0, PVM3 (VDDA monitoring vs. 1.62V threshold) disable] + Enabled: [1, PVM3 (VDDA monitoring vs. 1.62V threshold) enable] + PVME2: + Disabled: [0, PVM2 (VDDIO2 monitoring vs. 0.9V threshold) disable] + Enabled: [1, PVM2 (VDDIO2 monitoring vs. 0.9V threshold) enable] + PVME1: + Disabled: [0, PVM2 (VDDUSB monitoring vs. 1.2V threshold) disable] + Enabled: [1, PVM2 (VDDUSB monitoring vs. 1.2V threshold) enable] + PLS: + VPVD0: [0, VPVD0 around 2.0 V] + VPVD1: [1, VPVD1 around 2.2 V] + VPVD2: [2, VPVD2 around 2.4 V] + VPVD3: [3, VPVD3 around 2.5 V] + VPVD4: [4, VPVD4 around 2.6 V] + VPVD5: [5, VPVD5 around 2.8 V] + VPVD6: [6, VPVD6 around 2.9 V] + PVDIN: [7, External input analog voltage PVD_IN (compared internally to VREFINT)] + PVDE: + Disabled: [0, Power voltage detector disabled] + Enabled: [1, Power voltage detector enabled] + +CR3: + EIWUL: + Disabled: [0, Internal wakeup line disable] + Enabled: [1, Internal wakeup line enable] + DSIPDEN: + Disabled: [0, Pull-Down is disabled on DSI pins] + Enabled: [1, Pull-Down is enabled on DSI pins] + ENULP: + Disabled: [0, Sampling disabled] + Enabled: + [ + 1, + "When this bit is set, the BORL, BORH and PVD are periodically sampled instead continuous monitoring to reduce power consumption. Fast supply drop between two sample/compare phases is not detected in this mode. This bit has impact only on STOP2, Standby and shutdown low power modes", + ] + APC: + Disabled: [0, Configurations are not applied] + Enabled: + [ + 1, + "When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os, instead the I/Os will be in floating mode during Standby or configured according GPIO controller GPIOx_PUPDR register during Run mode", + ] + RRS: + PoweredOff: [0, SRAM2 is powered off in Standby mode (SRAM2 content is lost)] + PoweredOn: [1, Full SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 full content is kept)] + PartialPoweredOn: + [ + 2, + Only 4 Kbytes of SRAM2 is powered by the low-power regulator in Standby mode (4 Kbytes of SRAM2 content is kept), + ] + EWUP?: + Disabled: [0, External Wakeup pin WKUPx is disabled] + Enabled: + [ + 1, + "When this bit is set, the external wakeup pin WKUPx is enabled and triggers a wakeup from Standby or Shutdown event when a rising or a falling edge occurs. The active edge is configured via the WPx bit in the PWR_CR4 register", + ] + +CR4: + EXT_SMPS_ON: + Disabled: [0, The external SMPS switch is open] + Enabled: [1, "The external SMPS switch is closed, internal regulator output is set to 0.95 V"] + VBRS: + R5k: [0, Charge VBAT through a 5 kOhms resistor] + R1k5: [1, Charge VBAT through a 1.5 kOhms resistor] + VBE: + Disabled: [0, VBAT battery charging disable] + Enabled: [1, VBAT battery charging enable] + WP?: + RisingEdge: [0, Detection on high level (rising edge)] + FallingEdge: [1, Detection on low level (falling edge)] + +SR1: + WUFI: + Set: [0, This bit is set when a wakeup is detected on the internal wakeup line] + Cleared: [1, It is cleared when all internal wakeup sources are cleared] + EXT_SMPS_RDY: + NotReady: [0, "Internal regulator not ready in Range 2, the external SMPS cannot be connected"] + Ready: [1, "Internal regulator ready in Range 2, the external SMPS can be connected"] + SBF: + Set: [0, The device did not enter the Standby mode] + Cleared: [1, The device entered the Standby mode] + "WUF[12345]": + Set: [0, "This bit is set when a wakeup event is detected on wakeup pin, WKUPx"] + Cleared: [1, No wakeup event detected on WKUPx] + +SR2: + PVMO4: + Above: [0, VDDA voltage is above PVM4 threshold (around 2.2 V)] + Below: [1, VDDA voltage is below PVM4 threshold (around 2.2 V)] + PVMO3: + Above: [0, VDDA voltage is above PVM3 threshold (around 1.62 V)] + Below: [1, VDDA voltage is below PVM3 threshold (around 1.62 V)] + PVMO2: + Above: [0, VDDIO2 voltage is above PVM2 threshold (around 0.9 V)] + Below: [1, VDDIO2 voltage is below PVM2 threshold (around 0.9 V)] + PVMO1: + Above: [0, VDDUSB voltage is above PVM1 threshold (around 1.2 V)] + Below: [1, VDDUSB voltage is below PVM1 threshold (around 1.2 V)] + PVDO: + Above: [0, VDD is above the selected PVD threshold] + Below: [1, VDD is below the selected PVD threshold] + VOSF: + Ready: [0, The regulator is ready in the selected voltage range] + NotReady: [1, The regulator output voltage is changing to the required voltage level] + REGLPF: + MR: [0, The regulator is ready in main mode (MR)] + LPR: [1, The regulator is in low-power mode (LPR)] + REGLPS: + NotReady: [0, The low-power regulator is not ready] + Ready: [1, The low-power regulator is ready] + +SCR: + CSBF: + Clear: [1, Setting this bit clears the SBF flag in the PWR_SR1 register] + CWUF?: + Clear: [1, Setting this bit clears the WUFx flag in the PWR_SR1 register] + +PUCR?: + PU*: + Disabled: [0, Pull-Up on Pxx is disabled] + Enabled: [1, Pull-Up on Pxx is enabled] + +PDCR?: + PD*: + Disabled: [0, Pull-Down on Pxx is disabled] + Enabled: [1, Pull-Down on Pxx is enabled] + +CR5: + R1MODE: + BoostMode: [0, Main regulator in Range 1 boost mode] + NormalMode: [1, Main regulator in Range 1 normal mode] diff --git a/devices/fields/pwr/pwr_u5.yaml b/devices/fields/pwr/pwr_u5.yaml new file mode 100644 index 000000000..96da21af6 --- /dev/null +++ b/devices/fields/pwr/pwr_u5.yaml @@ -0,0 +1,296 @@ +CR1: + SRAM[123456]PD: + On: [0, SRAMx powered on] + Off: [1, SRAMx powered off] + ULPMEN: + Disabled: [0, BOR level 0 operating in continuous (normal) mode in Standby mode] + Enabled: [1, BOR level 0 operating in discontinuous (ultra-low power) mode in Standby mode] + RRSB2: + Disabled: [0, SRAM2 page2 content not retained in Stop3 and Standby modes] + Enabled: [1, SRAM2 page2 content retained in Stop 3 and Standby modes] + RRSB1: + Disabled: [0, SRAM2 page1 content not retained in Stop3 and Standby modes] + Enabled: [1, SRAM2 page1 content retained in Stop 3 and Standby modes] + LPMS: + Stop0: [0, Stop 0 mode] + Stop1: [1, Stop 1 mode] + Stop2: [2, Stop 2 mode] + Stop3: [3, Stop 3 mode] + Standby: [4, "Standby mode (Standby mode also entered if LPMS = 11X in PWR_CR1 with BREN = 1 in PWR_BDCR1)"] # same for [4, 5] + Shutdown: [6, "Shutdown mode if BREN = 0 in PWR_BDCR1"] # same for [6, 7] + "?~FORCE_USBPWR": # only on U59x, U5Ax, U5Fx, U5Gx + Disabled: [0, OTG_HS PHY power is not maintained during low-power modes] + Enabled: [1, OTG_HS PHY power is maintained during low-power modes] +CR2: + SRDRUN: + Disabled: [0, SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0/1/2 modes] + Enabled: [1, SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0/1/2 modes] + FLASHFWU: + Disabled: [0, Flash memory enters low-power mode in Stop 0/1 modes (lower-power consumption)] + Enabled: [1, Flash memory remains in normal mode in Stop 0/1 modes (faster wake-up time)] + SRAM4FWU: + Disabled: [0, SRAM4 enters low-power mode in Stop 0/1/2 modes (source biasing for lower-power consumption)] + Enabled: [1, SRAM4 remains in normal mode in Stop 0/1/2 modes (higher consumption but no SRAM4 wake-up time)] + PRAMPDS: + Disabled: [0, "FMAC, FDCAN, and USB/OTG_FS/OTG_HS SRAM content retained in Stop modes"] + Enabled: [1, "FMAC, FDCAN, and USB/OTG_FS/OTG_HS SRAM content lost in Stop modes"] + DC1RAMPDS: + Disabled: [0, DCACHE1 SRAM content retained in Stop modes] + Enabled: [1, DCACHE1 SRAM content lost in Stop modes] + ICRAMPDS: + Disabled: [0, ICACHE SRAM content retained in Stop modes] + Enabled: [1, ICACHE SRAM content lost in Stop modes] + SRAM4PDS: + Disabled: [0, SRAM4 content retained in Stop modes] + Enabled: [1, SRAM4 content lost in Stop modes] + SRAM2PDS?: + Disabled: [0, SRAM2 page x content retained in Stop modes] + Enabled: [1, SRAM2 page x content lost in Stop modes] + SRAM1PDS?: + Disabled: [0, SRAM1 page x content retained in Stop modes] + Enabled: [1, SRAM1 page x content lost in Stop modes] + "?~JPEGRAMPDS": # only on U5Fx, U5Gx + Disabled: [0, JPEG SRAM content retained in Stop 0 and Stop 1 modes] + Enabled: [1, JPEG SRAM content lost in Stop 0 and Stop 1 modes] + "?~DSIRAMPDS": # only on U599, U5A9, U5Fx, U5Gx + Disabled: [0, DSI SRAM content retained in Stop 0 and Stop 1 modes] + Enabled: [1, DSI SRAM content lost in Stop 0 and Stop 1 modes] + "?~GPRAMPDS": # only on U599, U5A9, U5Fx, U5Gx + Disabled: [0, Graphic peripherals SRAM content retained in Stop 0 and Stop 1 modes] + Enabled: [1, Graphic peripherals SRAM content lost in Stop 0 and Stop 1 modes] + "?~SRAM3PDS?": # only on U575, U585, U59x, U5Ax, U5Fx, U5Gx + Disabled: [0, SRAM3 page x content retained in Stop modes] + Enabled: [1, SRAM3 page x content lost in Stop modes] + "?~PKARAMPDS": # only on U545, U585, U5Ax, U5Gx + Disabled: [0, PKA SRAM content retained in Stop modes] + Enabled: [1, PKA SRAM content lost in Stop modes] + "?~DMA2DRAMPDS": # only on U575, U585, U59x, U5Ax, U5Fx, U5Gx + Disabled: [0, DMA2D SRAM content retained in Stop modes] + Enabled: [1, DMA2D SRAM content lost in Stop modes] + "?~DC2RAMPDS": # only on U599, U5A9, U5Fx, U5Gx + Disabled: [0, DCACHE2 SRAM content retained in Stop modes] + Enabled: [1, DCACHE2 SRAM content lost in Stop modes] +CR3: + FSTEN: + Disabled: [0, LDO/SMPS fast startup disabled (limited inrush current)] + Enabled: [1, LDO/SMPS fast startup enabled] + REGSEL: + LDO: [0, LDO selected] + SMPS: [1, SMPS selected] +CR4: + SRAM1PDS*: + Disabled: [0, SRAM1 page x content retained in Stop modes] + Enabled: [1, SRAM1 page x content lost in Stop modes] + "?~SRAM5PDS*": # only on U59x, U5Ax, U5Fx, U5Gx + Disabled: [0, SRAM5 page x content retained in Stop modes] + Enabled: [1, SRAM5 page x content lost in Stop modes] + "?~SRAM3PDS*": # only on U575, U585, U59x, U5Ax, U5Fx, U5Gx + Disabled: [0, SRAM3 page x content retained in Stop modes] + Enabled: [1, SRAM3 page x content lost in Stop modes] +CR5: + "?~SRAM6PDS*": # only on U5Fx, U5Gx + Disabled: [0, SRAM6 page x content retained in Stop modes] + Enabled: [1, SRAM6 page x content lost in Stop modes] +VOSR: + BOOSTEN: + Disabled: [0, Booster disabled] + Enabled: [1, Booster enabled] + VOS: + Range4: [0, Range 4 (lowest power)] + Range3: [1, Range 3] + Range2: [2, Range 2] + Range1: [3, Range 1 (highest frequency)] + VOSRDY: + NotReady: [0, "Not ready, voltage level < VOS selected level"] + Ready: [1, "Ready, voltage level ≥ VOS selected level"] + BOOSTRDY: + NotReady: [0, Power booster not ready] + Ready: [1, Power booster ready] + "?~VDD11USBDIS": # only on U59x, U5Ax, U5Fx, U5Gx + Enabled: [0, VDD11USB enabled] + Disabled: [1, VDD11USB disabled] + "?~USBBOOSTEN": # only on U59x, U5Ax, U5Fx, U5Gx + Disabled: [0, OTG_HS booster disabled] + Enabled: [1, OTG_HS booster enabled] + "?~USBPWREN": # only on U59x, U5Ax, U5Fx, U5Gx + Disabled: [0, OTG_HS power disabled] + Enabled: [1, OTG_HS power enabled] + "?~USBBOOSTRDY": # only on U59x, U5Ax, U5Fx, U5Gx + NotReady: [0, OTG_HS power booster not ready] + Ready: [1, OTG_HS power booster ready] +SVMCR: + ASV: + NotPresent: [0, "VDDA not present: logical and electrical isolation is applied to ignore this supply"] + Present: [1, VDDA valid] + IO2SV: + NotPresent: [0, "VDDIO2 not present: logical and electrical isolation is applied to ignore this supply"] + Present: [1, VDDIO2 valid] + USV: + NotPresent: [0, "VDDUSB not present: logical and electrical isolation is applied to ignore this supply"] + Present: [1, VDDUSB valid] + AVM2EN: + Disabled: [0, VDDA voltage monitor 2 disabled] + Enabled: [1, VDDA voltage monitor 2 enabled] + AVM1EN: + Disabled: [0, VDDA voltage monitor 1 disabled] + Enabled: [1, VDDA voltage monitor 1 enabled] + IO2VMEN: + Disabled: [0, VDDIO2 voltage monitor disabled] + Enabled: [1, VDDIO2 voltage monitor enabled] + UVMEN: + Disabled: [0, VDDUSB voltage monitor disabled] + Enabled: [1, VDDUSB voltage monitor enabled] + PVDLS: + VPVD0: [0, VPVD0 around 2.0 V] + VPVD1: [1, VPVD1 around 2.2 V] + VPVD2: [2, VPVD2 around 2.4 V] + VPVD3: [3, VPVD3 around 2.5 V] + VPVD4: [4, VPVD4 around 2.6 V] + VPVD5: [5, VPVD5 around 2.8 V] + VPVD6: [6, VPVD6 around 2.9 V] + PVDIN: [7, External input analog voltage PVD_IN (compared internally to VREFINT)] + PVDE: + Disabled: [0, PVD disabled] + Enabled: [1, PVD enabled] +WUCR1: + WUPEN?: + Disabled: [0, Wakeup pin disabled] + Enabled: [1, Wakeup pin enabled] +WUCR2: + WUPP?: + RisingEdge: [0, Detection on high level (rising edge)] + FallingEdge: [1, Detection on low level (falling edge)] +WUCR3: + WUSEL?: + WKUPx_0: [0, Wakeup pin WKUPx_0 selected] + WKUPx_1: [1, Wakeup pin WKUPx_1 selected] + WKUPx_2: [2, Wakeup pin WKUPx_2 selected] + WKUPx_3: [3, Wakeup pin WKUPx_3 selected] +BDCR1: + MONEN: + Disabled: [0, Backup domain voltage and temperature monitoring disabled] + Enabled: [1, Backup domain voltage and temperature monitoring enabled] + BREN: + Disabled: [0, Backup RAM content lost in Standby and VBAT modes] + Enabled: [1, Backup RAM content preserved in Standby and VBAT modes] +BDCR2: + VBRS: + R_5k: [0, Charge VBAT through a 5 kOhm resistor] + R_1k5: [1, Charge VBAT through a 1.5 kOhm resistor] + VBE: + Disabled: [0, VBAT battery charging disabled] + Enabled: [1, VBAT battery charging enabled] +DBPR: + DBP: + Disabled: [0, Write access to backup domain disabled] + Enabled: [1, Write access to backup domain enabled] +UCPDR: + "?~UCPD_STBY": # only on U575, U585, U59x, U5Ax, U5Fx, U5Gx + Disabled: + [ + 0, + "UCPD configuration is not memorized in Standby mode (Must be in this state after exiting Stop 3 or Standby mode, and before writing any UCPD registers)", + ] + Enabled: [1, UCPD configuration is memorized in Stop 3 and Standby modes] + "?~UCPD_DBDIS": # only on U575, U585, U59x, U5Ax, U5Fx, U5Gx + Enabled: [0, UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins] + Disabled: [1, UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins] +SECCFGR: + APCSEC: + NonSecure: [0, PWR_APCR can be read and written with secure or nonsecure access] + Secure: [1, PWR_APCR can be read and written only with secure access] + VBSEC: + NonSecure: [0, "PWR_BDCR1, PWR_BDCR2, and PWR_DBPR can be read and written with secure or nonsecure access"] + Secure: [1, "PWR_BDCR1, PWR_BDCR2, and PWR_DBPR can be read and written only with secure access"] + VDMSEC: + NonSecure: [0, PWR_SVMCR and PWR_CR3 can be read and written with secure or nonsecure access] + Secure: [1, PWR_SVMCR and PWR_CR3 can be read and written only with secure access] + LPMSEC: + NonSecure: [0, "PWR_CR1, PWR_CR2 and CSSF in the PWR_SR can be read and written with secure or nonsecure access"] + Secure: [1, "PWR_CR1, PWR_CR2, and CSSF in the PWR_SR can be read and written only with secure access"] + WUP?SEC: + NonSecure: + [ + 0, + "Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written with secure or nonsecure access", + ] + Secure: + [ + 1, + "Bits related to WKUPx pin in PWR_WUCR1, PWR_WUCR2, PWR_WUCR3, and PWR_WUSCR can be read and written only with secure access", + ] +PRIVCFGR: + NSPRIV: + NonSecure: [0, Read and write to PWR nonsecure functions can be done by privileged or unprivileged access] + Secure: [1, Read and write to PWR nonsecure functions can be done by privileged access only] + SPRIV: + NonSecure: [0, Read and write to PWR secure functions can be done by privileged or unprivileged access] + Secure: [1, Read and write to PWR secure functions can be done by privileged access only] +SR: + SBF: + _read: + NoStandby: [0, The device did not enter Standby mode] + Standby: [1, The device entered Standby mode] + STOPF: + _read: + NoStop: [0, The device did not enter any Stop mode] + Stop: [1, The device entered a Stop mode] + CSSF: + _write: + Clear: [1, Clear the STOPF and SBF flags] +SVMSR: + VDDA2RDY: + BelowThreshold: [0, VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V)] + AboveThreshold: [1, VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V)] + VDDA1RDY: + BelowThreshold: [0, VDDA is below the threshold of the VDDA voltage monitor 1 (around 1.6 V)] + EqualOrAboveThreshold: [1, VDDA is equal or above the threshold of the VDDA voltage monitor 1 (around 1.6 V)] + VDDIO2RDY: + BelowThreshold: [0, VDDIO2 is below the threshold of the VDDIO2 voltage monitor] + EqualOrAboveThreshold: [1, VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor] + VDDUSBRDY: + BelowThreshold: [0, VDDUSB is below the threshold of the VDDUSB voltage monitor] + EqualOrAboveThreshold: [1, VDDUSB is equal or above the threshold of the VDDUSB voltage monitor] + ACTVOS: + Range4: [0, Range 4 (lowest power)] + Range3: [1, Range 3] + Range2: [2, Range 2] + Range1: [3, Range 1 (highest frequency)] + ACTVOSRDY: + NotReady: [0, "VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]"] + Ready: [1, "VCORE is equal to the current voltage scaling provided by ACTVOS[1:0]"] + PVDO: + EqualOrAboveThreshold: [0, "VDD is equal or above the PVD threshold selected by PVDLS[2:0]"] + BelowThreshold: [1, "VDD is below the PVD threshold selected by PVDLS[2:0]"] + REGS: + LDO: [0, LDO selected] + SMPS: [1, SMPS selected] +BDSR: + TEMPH: + BelowHigh: [0, "Temperature < high threshold"] + AboveHigh: [1, "Temperature ≥ high threshold"] + TEMPL: + AboveLow: [0, "Temperature > low threshold"] + BelowLow: [1, "Temperature ≤ low threshold"] + VBATH: + BelowHigh: [0, "VBAT < high threshold"] + AboveHigh: [1, "VBAT ≥ high threshold"] +WUSR: + WUF?: + NoWakeup: [0, No wakeup event occurred on WKUPx pin] + Wakeup: [1, A wakeup event occurred on WKUPx pin] +WUSCR: + CWUF?: + Clear: [1, Clear the WUFx flag in PWR_WUSR] +APCR: + APC: + Disabled: [0, PWR_PUCRx and PWR_PDCRx are not applied to the I/Os] + Enabled: [1, I/O pull-up and pull-down configurations defined in PWR_PUCRx and PWR_PDCRx are applied] +PUCR?: + PU*: + Disabled: [0, Pull-up disabled] + Enabled: [1, Pull-up enabled] +PDCR?: + PD*: + Disabled: [0, Pull-down disabled] + Enabled: [1, Pull-down enabled] diff --git a/devices/fields/pwr/pwr_v1.yaml b/devices/fields/pwr/pwr_v1.yaml new file mode 100644 index 000000000..a08244bbf --- /dev/null +++ b/devices/fields/pwr/pwr_v1.yaml @@ -0,0 +1,6 @@ +# Power controller + +CR: + PDDS: + STOP_MODE: [0, Enter Stop mode when the CPU enters deepsleep] + STANDBY_MODE: [1, Enter Standby mode when the CPU enters deepsleep] diff --git a/devices/fields/pwr/pwr_v2.yaml b/devices/fields/pwr/pwr_v2.yaml new file mode 100644 index 000000000..642332f7c --- /dev/null +++ b/devices/fields/pwr/pwr_v2.yaml @@ -0,0 +1,6 @@ +# Power controller + +CR1: + PDDS: + STOP_MODE: [0, Enter Stop mode when the CPU enters deepsleep] + STANDBY_MODE: [1, Enter Standby mode when the CPU enters deepsleep] diff --git a/devices/fields/pwr/pwr_wl.yaml b/devices/fields/pwr/pwr_wl.yaml new file mode 100644 index 000000000..f573b7083 --- /dev/null +++ b/devices/fields/pwr/pwr_wl.yaml @@ -0,0 +1,300 @@ +CR1: + LPR: + MainMode: [0, Voltage regulator in Main mode in Low-power run mode] + LowPowerMode: [1, Voltage regulator in low-power mode in Low-power run mode] + VOS: + V1_2: [1, 1.2 V (range 1)] + V1_0: [2, 1.0 V (range 2)] + DBP: + Disabled: [0, Access to RTC and backup registers disabled] + Enabled: [1, Access to RTC and backup registers enabled] + FPDS: + Idle: [0, Flash memory in Idle mode when system is in LPSleep mode] + PowerDown: [1, Flash memory in Power-down mode when system is in LPSleep mode] + FPDR: + Idle: [0, Flash memory in Idle mode when system is in LPRun mode] + PowerDown: [1, Flash memory in Power-down mode when system is in LPRun mode] + SUBGHZSPINSSSEL: + SUBGHZSPICR: [0, sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled)] + LPTIM3: [1, sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled)] + LPMS: + Stop0: [0, Stop 0 mode] + Stop1: [1, Stop 1 mode] + Stop2: [2, Stop 2 mode] + Standby: [3, Standby mode] + Shutdown: [4, Shutdown mode] +CR2: + PVME3: + Disabled: [0, PVM3 (VDDA monitoring versus 1.62 V threshold) disable] + Enabled: [1, PVM3 (VDDA monitoring versus 1.62 V threshold) enable] + PLS: + V2_0: [0, 2.0V] + V2_2: [1, 2.2V] + V2_4: [2, 2.4V] + V2_5: [3, 2.5V] + V2_6: [4, 2.6V] + V2_8: [5, 2.8V] + V2_9: [6, 2.9V] + External: [7, External input analog voltage PVD_IN (compared internally to VREFINT)] + PVDE: + Disabled: [0, PVD Disabled] + Enabled: [1, PVD Enabled] +CR3: + EIWUL: + Disabled: [0, Internal wakeup line interrupt to CPU1 disabled] + Enabled: [1, Internal wakeup line interrupt to CPU1 enabled] + EWRFIRQ: + Disabled: [0, "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU1."] + Enabled: [1, "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU1."] + EWRFBUSY: + Disabled: + [ + 0, + Radio Busy is disabled and does not trigger a wakeup from Standby event to CPU1 when a rising or a falling edge occurs, + ] + Enabled: + [ + 1, + Radio Busy is enabled and triggers a wakeup from Standby event to CPU1 when a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4, + ] + APC: + Disabled: [0, I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied] + Enabled: [1, PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os] + RRS: + PowerOff: [0, SRAM2 powered off in Standby mode (SRAM2 content lost)] + OnLPR: [1, SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)] + EWPVD: + Disabled: [0, PVD not enabled by the sub-GHz radio active state] + Enabled: [1, PVD enabled while the sub-GHz radio is active] + EULPEN: + Disabled: [0, Disable (the supply voltage is monitored continuously)] + Enabled: [1, "Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only periodically"] + EWUP3: + Disabled: + [ + 0, + WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode), + ] + EWUP2: + Disabled: + [ + 0, + WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode), + ] + EWUP1: + Disabled: + [ + 0, + WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode), + ] +CR4: + WRFBUSYP: + RisingEdge: [0, Detection on high level (rising edge)] + FallingEdge: [1, Detection on low level (falling edge)] + VBRS: + R5k: [0, VBAT charging through a 5 kΩ resistor] + R1_5k: [1, VBAT charging through a 1.5 kΩ resistor] + VBE: + Disabled: [0, VBAT battery charging disabled] + Enabled: [1, VBAT battery charging enabled] + WP3: + RisingEdge: [0, Detection on high level (rising edge)] + FallingEdge: [1, Detection on low level (falling edge)] + WP2: + RisingEdge: [0, Detection on high level (rising edge)] + FallingEdge: [1, Detection on low level (falling edge)] + WP1: + RisingEdge: [0, Detection on high level (rising edge)] + FallingEdge: [1, Detection on low level (falling edge)] +SR1: + WUFI: + Clear: [0, All internal wakeup sources are cleared] + Wakeup: [1, wakeup is detected on the internal wakeup line] + WRFBUSYF: + Clear: [0, No wakeup event detected on radio busy] + Wakeup: [1, Wakeup event detected on radio busy] + WPVDF: + Clear: [0, No wakeup event detected on PVD] + Wakeup: [1, Wakeup event detected on PVD] + WUF3: + Clear: [0, No wakeup event detected on WKUP3] + Wakeup: [1, Wakeup event detected on WKUP3] + WUF2: + Clear: [0, No wakeup event detected on WKUP2] + Wakeup: [1, Wakeup event detected on WKUP2] + WUF1: + Clear: [0, No wakeup event detected on WKUP1] + Wakeup: [1, Wakeup event detected on WKUP1] +SR2: + PVMO3: + Above: [0, VDDA voltage above PVM3 threshold (around 1.62 V)] + Below: [1, VDDA voltage below PVM3 threshold (around 1.62 V)] + PVDO: + Above: [0, VDD or voltage level on PVD_IN above the selected PVD threshold] + Below: [1, VDD or voltage level on PVD_IN below the selected PVD threshold] + VOSF: + Ready: [0, Regulator ready in the selected voltage range] + Change: [1, Regulator output voltage changed to the required voltage level] + REGLPF: + Main: [0, Main regulator (MR) ready and used] + LowPower: [1, Low-power regulator (LPR) used] + REGLPS: + NotReady: [0, LPR not ready] + Ready: [1, LPR ready] + FLASHRDY: + NotReady: [0, Flash memory not ready to be accessed] + Ready: [1, Flash memory ready to be accessed] + REGMRS: + V_DD: [0, Main regulator supplied directly from VDD] + LDO_SMPS: [1, Main regulator supplied through LDO or SMPS] + RFEOLF: + Above: [0, Supply voltage above radio end-of-life operating low level] + Below: [1, Supply voltage below radio end-of-life operating low level] + LDORDY: + NotReady: [0, LDO not ready or off] + Ready: [1, LDO ready] + SMPSRDY: + NotReady: [0, SMPS step-down converter not ready or off] + Ready: [1, SMPS step-down converter ready] + RFBUSYMS: + NotBusy: [0, radio busy masked signal low (not busy)] + Busy: [1, radio busy masked signal high (busy)] + RFBUSYS: + NotBusy: [0, radio busy signal low (not busy)] + Busy: [1, radio busy signal high (busy)] +SCR: + CWRFBUSYF: + _write: + Clear: [1, Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0.] + CWPVDF: + _write: + Clear: [1, Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0.] + CWUF3: + _write: + Clear: [1, Setting this bit clears the WUF3 flag in the PWR_SR1 register. This bit is always read as 0.] + CWUF2: + _write: + Clear: [1, Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0.] + CWUF1: + _write: + Clear: [1, Setting this bit clears the WUF1 flag in the PWR_SR1 register. This bit is always read as 0.] +CR5: + SMPSEN: + Disabled: [0, SMPS step-down converter SMPS mode disabled (LDO mode enabled)] + Enabled: [1, SMPS step-down converter SMPS mode enabled] + RFEOLEN: + Disabled: [0, Radio end-of-life detector disabled] + Enabled: [1, Radio end-of-life detector enabled] +PUCRA: + "PU1[012345]": + Disabled: [0, "Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: + [ + 1, + "Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set", + ] + "PU[0123456789]": + Disabled: [0, "Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: + [ + 1, + "Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set", + ] +PDCRA: + "PD1[012345]": + Disabled: [0, "Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + "PD[0123456789]": + Disabled: [0, "Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] +PUCRB: + "PU1[012345]": + Disabled: [0, "Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: + [ + 1, + "Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set", + ] + "PU[0123456789]": + Disabled: [0, "Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: + [ + 1, + "Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set", + ] +PDCRB: + "PD1[012345]": + Disabled: [0, "Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + "PD[0123456789]": + Disabled: [0, "Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] +PUCRC: + "PU1[345]": + Disabled: [0, "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: + [ + 1, + "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set", + ] + "PU[0123456]": + Disabled: [0, "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: + [ + 1, + "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set", + ] +PDCRC: + "PD1[345]": + Disabled: [0, "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + "PD[0123456]": + Disabled: [0, "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] +PUCRH: + PU3: + Disabled: [0, "Disable pull-up on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: + [ + 1, + "Enable pull-up on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PH[y] bit is also set", + ] +PDCRH: + PD3: + Disabled: [0, "Disable the pull-down on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] +EXTSCR: + C1DS: + RunningOrSleep: [0, CPU is running or in sleep] + DeepSleep: [1, CPU is in Deep-Sleep] + C1STOPF: + NoStop: [0, System has not been in Stop 0 or 1 mode] + Stop: [1, System has been in Stop 0 or 1 mode] + C1STOP2F: + NoStop: [0, System has not been in Stop 2 mode] + Stop: [1, System has been in Stop 2 mode] + C1SBF: + NoStandby: [0, System has not been in Standby mode] + Standby: [1, System has been in Standby mode] + C1CSSF: + _write: + Clear: [1, Setting this bit clears the C1STOPF and C1SBF bits] +SUBGHZSPICR: + NSS: + Low: [0, Sub-GHz SPI NSS signal at level low] + High: [1, Sub-GHz SPI NSS signal is at level high] diff --git a/devices/fields/pwr/pwr_wl_c2.yaml b/devices/fields/pwr/pwr_wl_c2.yaml new file mode 100644 index 000000000..8ed78110b --- /dev/null +++ b/devices/fields/pwr/pwr_wl_c2.yaml @@ -0,0 +1,70 @@ +C2CR1: + FPDS: + Idle: [0, Flash memory in Idle mode when system is in LPSleep mode] + PowerDown: [1, Flash memory in Power-down mode when system is in LPSleep mode] + FPDR: + Idle: [0, Flash memory in Idle mode when system is in LPRun mode] + PowerDown: [1, Flash memory in Power-down mode when system is in LPRun mode] + LPMS: + Stop0: [0, Stop 0 mode] + Stop1: [1, Stop 1 mode] + Stop2: [2, Stop 2 mode] + Standby: [3, Standby mode] + Shutdown: [4, Shutdown mode] +C2CR3: + EIWUL: + Disabled: [0, Internal wakeup line interrupt to CPU2 disabled] + Enabled: [1, Internal wakeup line interrupt to CPU2 enabled] + EWRFIRQ: + Disabled: [0, "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU2."] + Enabled: [1, "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU2."] + EWRFBUSY: + Disabled: + [ + 0, + Radio Busy is disabled and does not trigger a wakeup from Standby event to CPU2 when a rising or a falling edge occurs, + ] + Enabled: + [ + 1, + Radio Busy is enabled and triggers a wakeup from Standby event to CPU2 when a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4, + ] + APC: + Disabled: [0, I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied] + Enabled: [1, PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os] + EWPVD: + Disabled: [0, PVD not enabled by the sub-GHz radio active state] + Enabled: [1, PVD enabled while the sub-GHz radio is active] + EWUP3: + Disabled: + [ + 0, + WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode), + ] + EWUP2: + Disabled: + [ + 0, + WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode), + ] + EWUP1: + Disabled: + [ + 0, + WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode, + ] + Enabled: + [ + 1, + WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode), + ] diff --git a/devices/fields/quadspi/quadspi_v1_dual_flash.yaml b/devices/fields/quadspi/quadspi_v1_dual_flash.yaml new file mode 100644 index 000000000..6ffbaac9b --- /dev/null +++ b/devices/fields/quadspi/quadspi_v1_dual_flash.yaml @@ -0,0 +1,4 @@ +_include: + - v1/base.yaml + - v1/dual_flash.yaml + - v1/dhhc.yaml diff --git a/devices/fields/quadspi/quadspi_v1_single_flash.yaml b/devices/fields/quadspi/quadspi_v1_single_flash.yaml new file mode 100644 index 000000000..ad5cc1a9b --- /dev/null +++ b/devices/fields/quadspi/quadspi_v1_single_flash.yaml @@ -0,0 +1,2 @@ +_include: + - v1/base.yaml diff --git a/devices/fields/quadspi/v1/base.yaml b/devices/fields/quadspi/v1/base.yaml new file mode 100644 index 000000000..05bcd0c5d --- /dev/null +++ b/devices/fields/quadspi/v1/base.yaml @@ -0,0 +1,155 @@ +CR: + PRESCALER: [0, 255] + PMM: + AndMatch: + [ + 0, + AND match mode. SMF is set if all the unmasked bits received from the Flash memory match the corresponding bits in the match register., + ] + OrMatch: + [ + 1, + OR match mode. SMF is set if any one of the unmasked bits received from the Flash memory matches its corresponding bit in the match register., + ] + APMS: + NotStopOnMatch: [0, Automatic polling mode is stopped only by abort or by disabling the QUADSPI.] + StopOnMatch: [1, Automatic polling mode stops as soon as there is a match.] + "*IE": + Disabled: [0, Interrupt disable] + Enabled: [1, Interrupt enabled] + SSHIFT: + NoShift: [0, No shift] + OneHalfCycleShift: [1, 1/2 cycle shift] + TCEN: + Disabled: + [ + 0, + "Timeout counter is disabled, and thus the chip select (nCS) remains active indefinitely after an access in memory-mapped mode.", + ] + Enabled: + [ + 1, + "Timeout counter is enabled, and thus the chip select is released in memory-mapped mode after TIMEOUT[15:0] cycles of Flash memory inactivity.", + ] + DMAEN: + Disabled: [0, DMA is disabled for indirect mode] + Enabled: [1, DMA is enabled for indirect mode] + ABORT: + NoAbortRequested: [0, No abort requested] + AbortRequested: [1, Abort requested] + EN: + Disabled: [0, QUADSPI is disabled] + Enabled: [1, QUADSPI is enabled] + +DCR: + FSIZE: [0, 31] + CSHT: [0, 7] + CKMODE: + Mode0: [0, CLK must stay low while nCS is high (chip select released). This is referred to as mode 0.] + Mode3: [1, CLK must stay high while nCS is high (chip select released). This is referred to as mode 3.] + +SR: + FLEVEL: [0, 31] + BUSY: + NotBusy: [0, ""] + Busy: [1, ""] + TOF: + NotTimeout: [0, ""] + Timeout: [1, ""] + SMF: + NotMatched: [0, ""] + Matched: [1, ""] + FTF: + NotReached: [0, ""] + Reached: [1, ""] + TCF: + NotComplete: [0, ""] + Complete: [1, ""] + TEF: + NoError: [0, ""] + Error: [1, ""] + +FCR: + CTOF: + Clear: [1, clears the TOF flag in the QUADSPI_SR register] + CSMF: + Clear: [1, clears the SMF flag in the QUADSPI_SR register] + CTCF: + Clear: [1, clears the TCF flag in the QUADSPI_SR register] + CTEF: + Clear: [1, clears the TEF flag in the QUADSPI_SR register] + +DLR: + DL: [0, 0xFFFF_FFFF] + +CCR: + DDRM: + Disabled: [0, DDR Mode disabled] + Enabled: [1, DDR Mode enabled] + SIOO: + SendEveryTransaction: [0, Send instruction on every transaction] + SendFirstCommand: [1, Send instruction only for the first command] + FMODE: + IndirectWrite: [0, Indirect write mode] + IndirectRead: [1, Indirect read mode] + AutomaticPolling: [2, Automatic polling mode] + MemoryMapped: [3, Memory-mapped mode] + DMODE: + NoData: [0, No data] + SingleLine: [1, Data on a single line] + TwoLines: [2, Data on two lines] + FourLines: [3, Data on four lines] + DCYC: [0, 31] + ABSIZE: + Bit8: [0, 8-bit alternate byte] + Bit16: [1, 16-bit alternate bytes] + Bit24: [2, 24-bit alternate bytes] + Bit32: [3, 32-bit alternate bytes] + ABMODE: + NoAlternateBytes: [0, No alternate bytes] + SingleLine: [1, Alternate bytes on a single line] + TwoLines: [2, Alternate bytes on two lines] + FourLines: [3, Alternate bytes on four lines] + ADSIZE: + Bit8: [0, 8-bit address] + Bit16: [1, 16-bit address] + Bit24: [2, 24-bit address] + Bit32: [3, 32-bit address] + ADMODE: + NoAddress: [0, No address] + SingleLine: [1, Address on a single line] + TwoLines: [2, Address on two lines] + FourLines: [3, Address on four lines] + IMODE: + NoInstruction: [0, No instruction] + SingleLine: [1, Instruction on a single line] + TwoLines: [2, Instruction on two lines] + FourLines: [3, Instruction on four lines] + INSTRUCTION: [0, 255] + +AR: + ADDRESS: [0, 0xFFFF_FFFF] + +ABR: + ALTERNATE: [0, 0xFFFF_FFFF] + +DR: + DATA: [0, 0xFFFF_FFFF] + +DR16: + DATA: [0, 0xFFFF] + +DR8: + DATA: [0, 0xFF] + +PSMKR: + MASK: [0, 0xFFFF_FFFF] + +PSMAR: + MATCH: [0, 0xFFFF_FFFF] + +PIR: + INTERVAL: [0, 0xFFFF] + +LPTR: + TIMEOUT: [0, 0xFFFF] diff --git a/devices/fields/quadspi/v1/dhhc.yaml b/devices/fields/quadspi/v1/dhhc.yaml new file mode 100644 index 000000000..95045acc4 --- /dev/null +++ b/devices/fields/quadspi/v1/dhhc.yaml @@ -0,0 +1,4 @@ +CCR: + DHHC: + NoDelay: [0, Delay the data output using analog delay] + Delayed: [1, Delay the data output by 1/4 of a QUADSPI output clock cycle.] diff --git a/devices/fields/quadspi/v1/dual_flash.yaml b/devices/fields/quadspi/v1/dual_flash.yaml new file mode 100644 index 000000000..21781d93b --- /dev/null +++ b/devices/fields/quadspi/v1/dual_flash.yaml @@ -0,0 +1,7 @@ +CR: + FSEL: + SelectFlash1: [0, FLASH 1 selected] + SelectFlash2: [1, FLASH 2 selected] + DFM: + Disabled: [0, Dual-flash mode disabled] + Enabled: [1, Dual-flash mode enabled] diff --git a/devices/fields/rcc/g4.yaml b/devices/fields/rcc/g4.yaml new file mode 100644 index 000000000..2de305976 --- /dev/null +++ b/devices/fields/rcc/g4.yaml @@ -0,0 +1,7 @@ +"A?B?RSTR,A?BRSTR,A?B?RSTR?": + "*RST": + Reset: [1, Reset the selected module] +"A?B?ENR,A?BENR,A?B?ENR?": + "*EN": + Disabled: [0, The selected clock is disabled] + Enabled: [1, The selected clock is enabled] diff --git a/devices/fields/rcc/rcc_cfgr2_f107.yaml b/devices/fields/rcc/rcc_cfgr2_f107.yaml new file mode 100644 index 000000000..c0185da9b --- /dev/null +++ b/devices/fields/rcc/rcc_cfgr2_f107.yaml @@ -0,0 +1,20 @@ +_include: + - rcc_cfgr2_prediv.yaml + +CFGR2: + PLL?MUL: + Mul8: [6, PLL clock entry x8] + Mul9: [7, PLL clock entry x9] + Mul10: [8, PLL clock entry x10] + Mul11: [9, PLL clock entry x11] + Mul12: [10, PLL clock entry x12] + Mul13: [11, PLL clock entry x13] + Mul14: [12, PLL clock entry x14] + Mul16: [14, PLL clock entry x16] + Mul20: [15, PLL clock entry x20] + PREDIV1SRC: + HSE: [0, HSE oscillator clock selected as PREDIV1 clock entry] + PLL2: [1, PLL2 selected as PREDIV1 clock entry] + I2S?SRC: + SYSCLK: [0, System clock (SYSCLK) selected as I2S clock entry] + PLL3: [1, PLL3 VCO clock selected as I2S clock entry] diff --git a/devices/fields/rcc/rcc_cfgr2_prediv.yaml b/devices/fields/rcc/rcc_cfgr2_prediv.yaml new file mode 100644 index 000000000..8cf66b7e8 --- /dev/null +++ b/devices/fields/rcc/rcc_cfgr2_prediv.yaml @@ -0,0 +1,18 @@ +CFGR2: + PREDIV,PREDIV[12]: + Div1: [0, PREDIV input clock not divided] + Div2: [1, PREDIV input clock divided by 2] + Div3: [2, PREDIV input clock divided by 3] + Div4: [3, PREDIV input clock divided by 4] + Div5: [4, PREDIV input clock divided by 5] + Div6: [5, PREDIV input clock divided by 6] + Div7: [6, PREDIV input clock divided by 7] + Div8: [7, PREDIV input clock divided by 8] + Div9: [8, PREDIV input clock divided by 9] + Div10: [9, PREDIV input clock divided by 10] + Div11: [10, PREDIV input clock divided by 11] + Div12: [11, PREDIV input clock divided by 12] + Div13: [12, PREDIV input clock divided by 13] + Div14: [13, PREDIV input clock divided by 14] + Div15: [14, PREDIV input clock divided by 15] + Div16: [15, PREDIV input clock divided by 16] diff --git a/devices/fields/rcc/rcc_cfgr3_cecsw.yaml b/devices/fields/rcc/rcc_cfgr3_cecsw.yaml new file mode 100644 index 000000000..dfb3f5422 --- /dev/null +++ b/devices/fields/rcc/rcc_cfgr3_cecsw.yaml @@ -0,0 +1,4 @@ +CFGR3: + CECSW: + HSI_Div244: [0, HSI clock divided by 244 selected as CEC clock source] + LSE: [1, LSE clock selected as CEC clock source] diff --git a/devices/fields/rcc/rcc_cfgr_mcopre.yaml b/devices/fields/rcc/rcc_cfgr_mcopre.yaml new file mode 100644 index 000000000..c8a755d91 --- /dev/null +++ b/devices/fields/rcc/rcc_cfgr_mcopre.yaml @@ -0,0 +1,10 @@ +CFGR: + MCOPRE: + Div1: [0, MCO is divided by 1] + Div2: [1, MCO is divided by 2] + Div4: [2, MCO is divided by 4] + Div8: [3, MCO is divided by 8] + Div16: [4, MCO is divided by 16] + Div32: [5, MCO is divided by 32] + Div64: [6, MCO is divided by 64] + Div128: [7, MCO is divided by 128] diff --git a/devices/fields/rcc/rcc_cfgr_pllnodiv.yaml b/devices/fields/rcc/rcc_cfgr_pllnodiv.yaml new file mode 100644 index 000000000..7a69a6a03 --- /dev/null +++ b/devices/fields/rcc/rcc_cfgr_pllnodiv.yaml @@ -0,0 +1,4 @@ +CFGR: + PLLNODIV: + Div2: [0, PLL is divided by 2 for MCO] + Div1: [1, PLL is not divided for MCO] diff --git a/devices/fields/rcc/rcc_common.yaml b/devices/fields/rcc/rcc_common.yaml new file mode 100644 index 000000000..bdd91d65d --- /dev/null +++ b/devices/fields/rcc/rcc_common.yaml @@ -0,0 +1,97 @@ +# Common bits of RCC peripheral + +CR: + CSSON: + "Off": [0, Clock security system disabled (clock detector OFF)] + "On": [1, "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] + HSEBYP: + NotBypassed: [0, HSE crystal oscillator not bypassed] + Bypassed: [1, HSE crystal oscillator bypassed with external clock] + HSICAL: [0, 255] + HSITRIM: [0, 31] + "*RDY": + _read: + NotReady: [0, Clock not ready] + Ready: [1, Clock ready] + HSION,HSEON,PLLON,PLLI2SON,PLLSAION: + "Off": [0, Clock Off] + "On": [1, Clock On] +CFGR: + PPRE*: + Div1: [-1, HCLK not divided] + Div2: [4, HCLK divided by 2] + Div4: [5, HCLK divided by 4] + Div8: [6, HCLK divided by 8] + Div16: [7, HCLK divided by 16] + HPRE: + Div1: [-1, SYSCLK not divided] + Div2: [8, SYSCLK divided by 2] + Div4: [9, SYSCLK divided by 4] + Div8: [10, SYSCLK divided by 8] + Div16: [11, SYSCLK divided by 16] + Div64: [12, SYSCLK divided by 64] + Div128: [13, SYSCLK divided by 128] + Div256: [14, SYSCLK divided by 256] + Div512: [15, SYSCLK divided by 512] +CIR: + CSSC: + _write: + Clear: [1, Clear CSSF flag] + "*RDYC": + _write: + Clear: [1, Clear interrupt flag] + "*RDYIE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + CSSF: + _read: + NotInterrupted: [0, No clock security interrupt caused by HSE clock failure] + Interrupted: [1, Clock security interrupt caused by HSE clock failure] + "*RDYF": + _read: + NotInterrupted: [0, No clock ready interrupt] + Interrupted: [1, Clock ready interrupt] +"A?B?RSTR,A?BRSTR": + "*RST": + Reset: [1, Reset the selected module] +"A?B?ENR,A?BENR": + "*EN": + Disabled: [0, The selected clock is disabled] + Enabled: [1, The selected clock is enabled] +BDCR: + BDRST: + Disabled: [0, Reset not activated] + Enabled: [1, Reset the entire RTC domain] + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock used as RTC clock] + LSI: [2, LSI oscillator clock used as RTC clock] + HSE: [3, HSE oscillator clock divided by a prescaler used as RTC clock] + LSEBYP: + NotBypassed: [0, LSE crystal oscillator not bypassed] + Bypassed: [1, LSE crystal oscillator bypassed with external clock] + LSERDY: + _read: + NotReady: [0, LSE oscillator not ready] + Ready: [1, LSE oscillator ready] + LSEON: + "Off": [0, LSE oscillator Off] + "On": [1, LSE oscillator On] +CSR: + "*RSTF": + _read: + NoReset: [0, No reset has occured] + Reset: [1, A reset has occured] + RMVF: + _write: + Clear: [1, Clears the reset flag] + LSIRDY: + _read: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSION: + "Off": [0, LSI oscillator Off] + "On": [1, LSI oscillator On] diff --git a/devices/fields/rcc/rcc_f0.yaml b/devices/fields/rcc/rcc_f0.yaml new file mode 100644 index 000000000..843d8b493 --- /dev/null +++ b/devices/fields/rcc/rcc_f0.yaml @@ -0,0 +1,68 @@ +# RCC peripheral +# Applicable to STM32F0 +# PLLSRC[0] available only on STM32F04x, STM32F07x and STM32F09x + +_include: + - rcc_f0_f1_f3_common.yaml + - rcc_f0_f3_common.yaml + - rcc_cfgr_mcopre.yaml + - rcc_cfgr_pllnodiv.yaml + - v2/bdcr_lsedrv.yaml + - rcc_cfgr2_prediv.yaml + +CFGR: + _modify: + PLLXTPRE: + description: "HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning" + ADCPRE: + description: ADCPRE is deprecated. See ADC field in CFGR2 register. + MCO: + bitWidth: 4 + + MCO: + NoMCO: [0, "MCO output disabled, no clock on MCO"] + HSI14: [1, Internal RC 14 MHz (HSI14) oscillator clock selected] + LSI: [2, Internal low speed (LSI) oscillator clock selected] + LSE: [3, External low speed (LSE) oscillator clock selected] + SYSCLK: [4, System clock selected] + HSI: [5, Internal RC 8 MHz (HSI) oscillator clock selected] + HSE: [6, External 4-32 MHz (HSE) oscillator clock selected] + PLL: [7, "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"] + HSI48: [8, Internal RC 48 MHz (HSI48) oscillator clock selected] + SWS: + _read: + HSI: [0, HSI oscillator used as system clock] + HSE: [1, HSE oscillator used as system clock] + PLL: [2, PLL used as system clock] + HSI48: [3, HSI48 used as system clock (when avaiable)] + SW: + HSI: [0, HSI selected as system clock] + HSE: [1, HSE selected as system clock] + PLL: [2, PLL selected as system clock] + HSI48: [3, HSI48 selected as system clock (when available)] +CFGR3: + _modify: + ADCSW: + description: ADCSW is deprecated. See ADC field in CFGR2 register. + +CR2: + HSI48CAL: [0, 255] + HSI48RDY: + _read: + NotReady: [0, HSI48 oscillator ready] + Ready: [1, HSI48 oscillator ready] + HSI48ON: + "Off": [0, HSI48 oscillator off] + "On": [1, HSI48 oscillator on] + HSI14CAL: [0, 255] + HSI14TRIM: [0, 31] + HSI14DIS: + Allow: [0, ADC can turn on the HSI14 oscillator] + Disallow: [1, ADC can not turn on the HSI14 oscillator] + HSI14RDY: + _read: + NotReady: [0, HSI14 oscillator not ready] + Ready: [1, HSI14 oscillator ready] + HSI14ON: + "Off": [0, HSI14 oscillator off] + "On": [1, HSI14 oscillator on] diff --git a/devices/fields/rcc/rcc_f0_f1_f3_common.yaml b/devices/fields/rcc/rcc_f0_f1_f3_common.yaml new file mode 100644 index 000000000..6452a0019 --- /dev/null +++ b/devices/fields/rcc/rcc_f0_f1_f3_common.yaml @@ -0,0 +1,24 @@ +_include: + - rcc_common.yaml + +CFGR: + PLLMUL: + Mul2: [0, PLL input clock x2] + Mul3: [1, PLL input clock x3] + Mul4: [2, PLL input clock x4] + Mul5: [3, PLL input clock x5] + Mul6: [4, PLL input clock x6] + Mul7: [5, PLL input clock x7] + Mul8: [6, PLL input clock x8] + Mul9: [7, PLL input clock x9] + Mul10: [8, PLL input clock x10] + Mul11: [9, PLL input clock x11] + Mul12: [10, PLL input clock x12] + Mul13: [11, PLL input clock x13] + Mul14: [12, PLL input clock x14] + Mul15: [13, PLL input clock x15] + Mul16: [14, PLL input clock x16] + Mul16x: [15, PLL input clock x16] + PLLXTPRE: + Div1: [0, HSE clock not divided] + Div2: [1, HSE clock divided by 2] diff --git a/devices/fields/rcc/rcc_f0_f3_common.yaml b/devices/fields/rcc/rcc_f0_f3_common.yaml new file mode 100644 index 000000000..e123ccf76 --- /dev/null +++ b/devices/fields/rcc/rcc_f0_f3_common.yaml @@ -0,0 +1,9 @@ +CFGR3: + U*ART*SW: + PCLK: [0, PCLK selected as USART clock source] + SYSCLK: [1, SYSCLK selected as USART clock source] + LSE: [2, LSE selected as USART clock source] + HSI: [3, HSI selected as USART clock source] + I2C*SW: + HSI: [0, HSI clock selected as I2C clock source] + SYSCLK: [1, SYSCLK clock selected as I2C clock source] diff --git a/devices/fields/rcc/rcc_f0x0.yaml b/devices/fields/rcc/rcc_f0x0.yaml new file mode 100644 index 000000000..de01a167a --- /dev/null +++ b/devices/fields/rcc/rcc_f0x0.yaml @@ -0,0 +1,8 @@ +_include: + - rcc_f0.yaml + - rcc_pllsrc_1bit.yaml + +CFGR3: + USBSW: + Disabled: [0, USB clock disabled] + PLLCLK: [1, PLL clock selected as USB clock source] diff --git a/devices/fields/rcc/rcc_f0x128.yaml b/devices/fields/rcc/rcc_f0x128.yaml new file mode 100644 index 000000000..e401f7b28 --- /dev/null +++ b/devices/fields/rcc/rcc_f0x128.yaml @@ -0,0 +1,14 @@ +_include: + - rcc_f0.yaml + - rcc_cfgr3_cecsw.yaml + +CFGR: + PLLSRC: + HSI_Div2: [0, HSI divided by 2 selected as PLL input clock] + HSI_Div_PREDIV: [1, HSI divided by PREDIV selected as PLL input clock] + HSE_Div_PREDIV: [2, HSE divided by PREDIV selected as PLL input clock] + HSI48_Div_PREDIV: [3, HSI48 divided by PREDIV selected as PLL input clock] +CFGR3: + USBSW: + HSI48: [0, HSI48 selected as USB clock source] + PLLCLK: [1, PLL clock selected as USB clock source] diff --git a/devices/fields/rcc/rcc_f1.yaml b/devices/fields/rcc/rcc_f1.yaml new file mode 100644 index 000000000..13377d152 --- /dev/null +++ b/devices/fields/rcc/rcc_f1.yaml @@ -0,0 +1,28 @@ +# RCC peripheral +# Applicable to STM32F1 + +_include: + - rcc_f0_f1_f3_common.yaml + - rcc_pllsrc_1bit.yaml + +CFGR: + SWS: + _read: + HSI: [0, HSI oscillator used as system clock] + HSE: [1, HSE oscillator used as system clock] + PLL: [2, PLL used as system clock] + SW: + HSI: [0, HSI selected as system clock] + HSE: [1, HSE selected as system clock] + PLL: [2, PLL selected as system clock] + MCO: + NoMCO: [0, "MCO output disabled, no clock on MCO"] + SYSCLK: [4, System clock selected] + HSI: [5, HSI oscillator clock selected] + HSE: [6, HSE oscillator clock selected] + PLL: [7, "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"] + ADCPRE: + Div2: [0, PCLK2 divided by 2] + Div4: [1, PCLK2 divided by 4] + Div6: [2, PCLK2 divided by 8] + Div8: [3, PCLK2 divided by 16] diff --git a/devices/fields/rcc/rcc_f107.yaml b/devices/fields/rcc/rcc_f107.yaml new file mode 100644 index 000000000..e3ccab956 --- /dev/null +++ b/devices/fields/rcc/rcc_f107.yaml @@ -0,0 +1,43 @@ +# RCC peripheral +# Applicable to STM32F107 + +_include: + - rcc_common.yaml + - rcc_pllsrc_1bit.yaml + +CFGR: + SWS: + _read: + HSI: [0, HSI oscillator used as system clock] + HSE: [1, HSE oscillator used as system clock] + PLL: [2, PLL used as system clock] + SW: + HSI: [0, HSI selected as system clock] + HSE: [1, HSE selected as system clock] + PLL: [2, PLL selected as system clock] + PLLMUL: + Mul4: [2, PLL input clock x4] + Mul5: [3, PLL input clock x5] + Mul6: [4, PLL input clock x6] + Mul7: [5, PLL input clock x7] + Mul8: [6, PLL input clock x8] + Mul9: [7, PLL input clock x9] + Mul6_5: [13, PLL input clock x6.5] + PLLXTPRE: + Div1: [0, HSE clock not divided] + Div2: [1, HSE clock divided by 2] + MCO: + NoMCO: [0, "MCO output disabled, no clock on MCO"] + SYSCLK: [4, System clock selected] + HSI: [5, HSI oscillator clock selected] + HSE: [6, HSE oscillator clock selected] + PLL: [7, PLL clock divided by 2 selected] + PLL2: [8, PLL2 clock selected] + PLL3: [9, PLL3 clock divided by 2 selected] + XT1: [10, XT1 external 3-25 MHz oscillator clock selected (for Ethernet)] + PLL3Ethernet: [11, PLL3 clock selected (for Ethernet)] + ADCPRE: + Div2: [0, PCLK2 divided by 2] + Div4: [1, PCLK2 divided by 4] + Div6: [2, PCLK2 divided by 8] + Div8: [3, PCLK2 divided by 16] diff --git a/devices/fields/rcc/rcc_f1_f3_usb.yaml b/devices/fields/rcc/rcc_f1_f3_usb.yaml new file mode 100644 index 000000000..8ff837866 --- /dev/null +++ b/devices/fields/rcc/rcc_f1_f3_usb.yaml @@ -0,0 +1,7 @@ +# RCC peripheral +# Applicable to STM32F103 and STMF107 + +CFGR: + USBPRE,OTGFSPRE: + DIV1_5: [0, PLL clock is divided by 1.5] + DIV1: [1, PLL clock is not divided] diff --git a/devices/fields/rcc/rcc_f3.yaml b/devices/fields/rcc/rcc_f3.yaml new file mode 100644 index 000000000..ee8a69092 --- /dev/null +++ b/devices/fields/rcc/rcc_f3.yaml @@ -0,0 +1,51 @@ +# RCC peripheral +# Applicable to STM32F3 + +_include: + - rcc_f0_f1_f3_common.yaml + - rcc_f0_f3_common.yaml + - rcc_cfgr_mcopre.yaml + - rcc_cfgr_pllnodiv.yaml + - v2/bdcr_lsedrv.yaml + - rcc_cfgr2_prediv.yaml + +CFGR: + MCO: + NoMCO: [0, "MCO output disabled, no clock on MCO"] + LSI: [2, Internal low speed (LSI) oscillator clock selected] + LSE: [3, External low speed (LSE) oscillator clock selected] + SYSCLK: [4, System clock selected] + HSI: [5, Internal RC 8 MHz (HSI) oscillator clock selected] + HSE: [6, External 4-32 MHz (HSE) oscillator clock selected] + PLL: [7, "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"] + SWS: + _read: + HSI: [0, HSI oscillator used as system clock] + HSE: [1, HSE oscillator used as system clock] + PLL: [2, PLL used as system clock] + SW: + HSI: [0, HSI selected as system clock] + HSE: [1, HSE selected as system clock] + PLL: [2, PLL selected as system clock] +CFGR2: + _modify: + ADC*PRES: + bitWidth: 5 + ADC*PRES: + NoClock: [0, No clock] # Same for [0, 15] + Div1: [16, PLL clock not divided] + Div2: [17, PLL clock divided by 2] + Div4: [18, PLL clock divided by 4] + Div6: [19, PLL clock divided by 6] + Div8: [20, PLL clock divided by 8] + Div10: [21, PLL clock divided by 10] + Div12: [22, PLL clock divided by 12] + Div16: [23, PLL clock divided by 16] + Div32: [24, PLL clock divided by 32] + Div64: [25, PLL clock divided by 64] + Div128: [26, PLL clock divided by 128] + Div256: [27, PLL clock divided by 256] # Same for [27, 31] +CFGR3: + "TIM*SW,HRTIM*SW": + PCLK2: [0, PCLK2 clock (doubled frequency when prescaled)] + PLL: [1, PLL vco output (running up to 144 MHz)] diff --git a/devices/fields/rcc/rcc_f373.yaml b/devices/fields/rcc/rcc_f373.yaml new file mode 100644 index 000000000..b6fecb4b6 --- /dev/null +++ b/devices/fields/rcc/rcc_f373.yaml @@ -0,0 +1,50 @@ +# RCC peripheral +# Applicable to STM32F373 + +_include: + - rcc_f0_f1_f3_common.yaml + - rcc_f0_f3_common.yaml + - v2/bdcr_lsedrv.yaml + - rcc_cfgr2_prediv.yaml + - rcc_cfgr3_cecsw.yaml + +CFGR: + MCO: + NoMCO: [0, "MCO output disabled, no clock on MCO"] + LSI: [2, Internal low speed (LSI) oscillator clock selected] + LSE: [3, External low speed (LSE) oscillator clock selected] + SYSCLK: [4, System clock selected] + HSI: [5, Internal RC 8 MHz (HSI) oscillator clock selected] + HSE: [6, External 4-32 MHz (HSE) oscillator clock selected] + PLL: [7, "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"] + SWS: + _read: + HSI: [0, HSI oscillator used as system clock] + HSE: [1, HSE oscillator used as system clock] + PLL: [2, PLL used as system clock] + SW: + HSI: [0, HSI selected as system clock] + HSE: [1, HSE selected as system clock] + PLL: [2, PLL selected as system clock] + ADCPRE: + Div2: [0, PCLK divided by 2] + Div4: [1, PCLK divided by 4] + Div6: [2, PCLK divided by 6] + Div8: [3, PCLK divided by 8] + SDPRE: + Div2: [-1, SYSCLK divided by 2] + Div4: [17, SYSCLK divided by 4] + Div6: [18, SYSCLK divided by 6] + Div8: [19, SYSCLK divided by 8] + Div10: [20, SYSCLK divided by 10] + Div12: [21, SYSCLK divided by 12] + Div14: [22, SYSCLK divided by 14] + Div16: [23, SYSCLK divided by 16] + Div20: [24, SYSCLK divided by 20] + Div24: [25, SYSCLK divided by 24] + Div28: [26, SYSCLK divided by 28] + Div32: [27, SYSCLK divided by 32] + Div36: [28, SYSCLK divided by 36] + Div40: [29, SYSCLK divided by 40] + Div44: [30, SYSCLK divided by 44] + Div48: [31, SYSCLK divided by 48] diff --git a/devices/fields/rcc/rcc_f3_i2s.yaml b/devices/fields/rcc/rcc_f3_i2s.yaml new file mode 100644 index 000000000..38baf87fc --- /dev/null +++ b/devices/fields/rcc/rcc_f3_i2s.yaml @@ -0,0 +1,4 @@ +CFGR: + I2SSRC: + SYSCLK: [0, System clock used as I2S clock source] + CKIN: [1, External clock mapped on the I2S_CKIN pin used as I2S clock source] diff --git a/devices/fields/rcc/rcc_g0.yaml b/devices/fields/rcc/rcc_g0.yaml new file mode 100644 index 000000000..887a1cd01 --- /dev/null +++ b/devices/fields/rcc/rcc_g0.yaml @@ -0,0 +1,29 @@ +# non-G0Bx G0 parts + +_include: + - rcc_g0_common.yaml + +CFGR: + MCOPRE: + Div1: [0b000, Divide by 1] + Div2: [0b001, Divide by 2] + Div3: [0b010, Divide by 4] + Div8: [0b011, Divide by 8] + Div16: [0b100, Divide by 16] + Div32: [0b101, Divide by 32] + Div64: [0b110, Divide by 64] + Div128: [0b111, Divide by 128] + MCOSEL: + NoClock: [0b0000, No clock] + SYSCLK: [0b0001, SYSCLK clock selected] + HSI16: [0b0011, HSI16 oscillator clock selected] + HSE: [0b0100, HSE oscillator clock selected] + PLLR: [0b0101, PLLRCLK clock selected] + LSI: [0b0110, LSI oscillator clock selected] + LSE: [0b0111, LSE oscillator clock selected] +CCIPR: + I2S1SEL: + SYSCLK: [0b00, SYSCLK clock selected] + PLLP: [0b01, PLLPCLK clock selected] + HSI16: [0b10, HSI16 clock selected] + CKIN: [0b11, I2S_CKIN clock selected] diff --git a/devices/fields/rcc/rcc_g0_common.yaml b/devices/fields/rcc/rcc_g0_common.yaml new file mode 100644 index 000000000..584da9cd8 --- /dev/null +++ b/devices/fields/rcc/rcc_g0_common.yaml @@ -0,0 +1,168 @@ +CR: + PLLRDY: + Unlocked: [0, PLL unlocked] + Locked: [1, PLL locked] + PLLON: + Disabled: [0, PLL powered off] + Enabled: [1, PLL enabled] + CSSON: + Disabled: [0, HSE clock is not monitored] + Enabled: [1, "HSE clock monitor enabled when HSE is ready, otherwise disabled"] + HSEBYP: + Crystal: [0, HSE is a crystal oscillator or ceramic resonator] + ExtClock: [1, HSE is driven by an external clock] + HSERDY: + NotReady: [0, HSE oscillator not ready] + Ready: [1, HSE oscillator ready] + HSEON: + Disabled: [0, HSE oscillator powered off] + Enabled: [1, HSE oscillator enabled] + HSIDIV: + Div1: [0b000, Divide HSI16 by 1] + Div2: [0b001, Divide HSI16 by 2] + Div4: [0b010, Divide HSI16 by 4] + Div8: [0b011, Divide HSI16 by 8] + Div16: [0b100, Divide HSI16 by 16] + Div32: [0b101, Divide HSI16 by 32] + Div64: [0b110, Divide HSI16 by 64] + Div128: [0b111, Divide HSI16 by 128] + HSIRDY: + NotReady: [0, HSI oscillator not ready] + Ready: [1, HSI oscillator ready] + HSIKERON: + NotForce: [0, No effect on HSI16 oscillator] + Forced: [1, HSI16 oscillator forced on even in Stop modes] + HSION: + Disabled: [0, HSI oscillator powered off] + Enabled: [1, HSI oscillator enabled] +ICSCR: + HSITRIM: [0, 0x7F] + HSICAL: [0, 0xFF] +CFGR: + # MCOPRE and MCOSEL handled in rcc_g0.yaml or rcc_g0b.yaml + PPRE: + Div1: [-1, Divide by 1] + Div2: [0b100, Divide by 2] + Div4: [0b101, Divide by 4] + Div8: [0b110, Divide by 8] + Div16: [0b111, Divide by 16] + HPRE: + Div1: [-1, Divide by 1] + Div2: [0b1000, Divide by 2] + Div4: [0b1001, Divide by 4] + Div8: [0b1010, Divide by 8] + Div16: [0b1011, Divide by 16] + Div64: [0b1100, Divide by 64] + Div128: [0b1101, Divide by 128] + Div256: [0b1110, Divide by 256] + Div512: [0b1111, Divide by 512] + SWS: + HSISYS: [0b000, HSISYS clock selected] + HSE: [0b001, HSE clock selected] + PLLR: [0b010, PLLRCLK clock selected] + LSI: [0b011, LSI clock selected] + LSE: [0b100, LSE clock selected] + SW: + HSISYS: [0b000, HSISYS clock selected] + HSE: [0b001, HSE clock selected] + PLLR: [0b010, PLLRCLK clock selected] + LSI: [0b011, LSI clock selected] + LSE: [0b100, LSE clock selected] +PLLCFGR: + "PLL[RQ]": [1, 7] + PLLP: [1, 31] + "PLL[PRQ]EN": + Disabled: [0, PLL output disabled (saves power)] + Enabled: [1, PLL output enabled] + PLLN: [8, 86] + PLLM: [0, 7] + PLLSRC: + NoClock: [0b00, No clock selected (saves power)] + HSI16: [0b10, HSI16 clock selected] + HSE: [0b11, HSE clock selected] +CIER: + "*": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] +CIFR: + "*": + NotInterrupted: [0, Interrupt not triggered] + Interrupted: [1, Interrup triggered] +CICR: + "*": + Clear: [1, Clear interrupt flag] +"*RSTR*": + "*": + Reset: [1, Reset peripheral] +"*ENR*": + "*": + Disabled: [0, Peripheral disabled (typically saves power)] + Enabled: [1, Peripheral enabled] +CCIPR: + ADCSEL: + SYSCLK: [0b00, System clock selected] + PLLP: [0b01, PLLPCLK clock selected] + HSI16: [0b10, HSI16 clock selected] + "TIM15SEL,TIM1SEL": + TIMP: [0, TIMPCLK clock selected] + PLLQ: [1, PLLQCLK clock selected] + # I2C2I2S1SEL handled in rcc_g0.yaml or rcc_g0b.yaml + I2C1SEL: + PCLK: [0b00, PCLK clock selected] + SYSCLK: [0b01, SYSCLK clock selected] + HSI16: [0b10, HSI16 clock selected] + "USART[123]SEL": + PCLK: [0b00, PCLK clock selected] + SYSCLK: [0b01, SYSCLK clock selected] + HSI16: [0b10, HSI16 clock selected] + LSE: [0b11, LSE clock selected] +# CCIPR2 handled in rcc_g0b.yaml +BDCR: + LSCOSEL: + LSI: [0, LSI clock selected] + LSE: [1, LSE clock selected] + LSCOEN: + Disabled: [0, Low-speed clock output disabled] + Enabled: [1, Low-speed clock output enabled] + BDRST: + Reset: [1, RTC domain software reset] + RTCEN: + Disabled: [0, RTC disabled (saves power)] + Enabled: [1, RTC enabled] + RTCSEL: + NoClock: [0b00, No clock selected] + LSE: [0b01, LSE clock selected] + LSI: [0b10, LSI clock selected] + HSE32: [0b11, HSI clock divided by 32 selected] + LSECSSD: + NoFailure: [0, No failure detected] + Failure: [1, Failure detected] + LSECSSON: + Disabled: [0, LSE clock is not monitored] + Enabled: [1, LSE clock monitor enabled] + LSEDRV: + Low: [0, Xtal mode lower driving capability] + MedLow: [1, Xtal mode medium-low driving capability] + MedHigh: [2, Xtal mode medium-high driving capability] + High: [3, Xtal mode higher driving capability] + LSEBYP: + Crystal: [0, LSE is a crystal oscillator or ceramic resonator] + ExtClock: [1, LSE is driven by an external clock] + LSERDY: + NotReady: [0, LSE oscillator not ready] + Ready: [1, LSE oscillator ready] + LSEON: + Disabled: [0, LSE oscillator powered off] + Enabled: [1, LSE oscillator enabled] +CSR: + "*RSTF": + NoReset: [0, This reset type has not occurred] + Reset: [1, This reset type has occurred] + RMVF: + Clear: [1, Clear reset flags] + LSIRDY: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSION: + Disabled: [0, LSI oscillator powered off] + Enabled: [1, LSI oscillator enabled] diff --git a/devices/fields/rcc/rcc_g0b.yaml b/devices/fields/rcc/rcc_g0b.yaml new file mode 100644 index 000000000..32098fe2d --- /dev/null +++ b/devices/fields/rcc/rcc_g0b.yaml @@ -0,0 +1,44 @@ +# G0Bx/G0Cx parts + +_include: + - rcc_g0_common.yaml + +CFGR: + "MCOPRE,MCO2PRE": + Div1: [0b0000, Divide by 1] + Div2: [0b0001, Divide by 2] + Div3: [0b0010, Divide by 4] + Div8: [0b0011, Divide by 8] + Div16: [0b0100, Divide by 16] + Div32: [0b0101, Divide by 32] + Div64: [0b0110, Divide by 64] + Div128: [0b0111, Divide by 128] + Div256: [0b1000, Divide by 256] + Div512: [0b1001, Divide by 512] + Div1024: [0b1010, Divide by 1024] + "MCOSEL,MCO2SEL": + NoClock: [0b0000, No clock] + SYSCLK: [0b0001, SYSCLK clock selected] + HSI16: [0b0011, HSI16 oscillator clock selected] + HSE: [0b0100, HSE oscillator clock selected] + PLLR: [0b0101, PLLRCLK clock selected] + LSI: [0b0110, LSI oscillator clock selected] + LSE: [0b0111, LSE oscillator clock selected] + PLLP: [0b1000, PLLPCLK clock selected] + PLLQ: [0b1001, PLLQCLK clock selected] + RTC: [0b1010, RTC clock selected] + RTCWake: [0b1011, RTC wakeup output selected] +CCIPR: + I2C2SEL: + PCLK: [0b00, PCLK clock selected] + SYSCLK: [0b01, SYSCLK clock selected] + HSI16: [0b10, HSI16 clock selected] +CCIPR2: + USBSEL: + PLLQ: [0b01, PLLQCLK clock selected] + HSE: [0b10, HSE clock selected] + "I2S[12]SEL": + SYSCLK: [0b00, SYSCLK clock selected] + PLLP: [0b01, PLLPCLK clock selected] + HSI16: [0b10, HSI16 clock selected] + CKIN: [0b11, I2S_CKIN clock selected] diff --git a/devices/fields/rcc/rcc_g0b1.yaml b/devices/fields/rcc/rcc_g0b1.yaml new file mode 100644 index 000000000..a34e8f0d8 --- /dev/null +++ b/devices/fields/rcc/rcc_g0b1.yaml @@ -0,0 +1,21 @@ +# G0B1/G0C1 + +_include: + - rcc_g0b.yaml + - rcc_g0x1.yaml + - rcc_g0x1_cec.yaml + +CR: + HSI48RDY: + NotReady: [0, HSI48 oscillator not ready] + Ready: [1, HSI48 oscillator ready] + HSI48ON: + Disabled: [0, HSI48 oscillator powered off] + Enabled: [1, HSI48 oscillator enabled] +CRRCR: + HSI48CAL: [0, 0x1FF] +CCIPR2: + FDCANSEL: + PCLK: [0b00, PCLK clock selected] + PLLQ: [0b01, PLLQCLK clock selected] + HSE: [0b10, HSE clock selected] diff --git a/devices/fields/rcc/rcc_g0x1.yaml b/devices/fields/rcc/rcc_g0x1.yaml new file mode 100644 index 000000000..a0df3cde3 --- /dev/null +++ b/devices/fields/rcc/rcc_g0x1.yaml @@ -0,0 +1,13 @@ +# all G0x1 parts + +CCIPR: + "LPTIM[12]SEL": + PCLK: [0b00, PCLK clock selected] + LSI: [0b01, LSI clock selected] + HSI16: [0b10, HSI16 clock selected] + LSE: [0b11, LSE clock selected] + "LPUART[12]SEL": + PCLK: [0b00, PCLK clock selected] + SYSCLK: [0b01, SYSCLK clock selected] + HSI16: [0b10, HSI16 clock selected] + LSE: [0b11, LSE clock selected] diff --git a/devices/fields/rcc/rcc_g0x1_aes.yaml b/devices/fields/rcc/rcc_g0x1_aes.yaml new file mode 100644 index 000000000..95b001984 --- /dev/null +++ b/devices/fields/rcc/rcc_g0x1_aes.yaml @@ -0,0 +1,13 @@ +# G0x1 parts with AES + +CCIPR: + RNGDIV: + Div1: [0b00, Divide by 1] + Div2: [0b01, Divide by 2] + Div4: [0b10, Divide by 4] + Div8: [0b11, Divide by 8] + RNGSEL: + NoClock: [0b00, No clock selected] + HSI16: [0b01, HSI16 clock selected] + SYSCLK: [0b10, SYSCLK clock selected] + PLLQ: [0b11, PLLQCLK clock selected] diff --git a/devices/fields/rcc/rcc_g0x1_cec.yaml b/devices/fields/rcc/rcc_g0x1_cec.yaml new file mode 100644 index 000000000..5e05ba2d5 --- /dev/null +++ b/devices/fields/rcc/rcc_g0x1_cec.yaml @@ -0,0 +1,6 @@ +# G0x1 parts with HDMI CEC + +CCIPR: + CECSEL: + HSI16: [0, HSI16 clock divided by 488 selected] + LSE: [1, LSE clock selected] diff --git a/devices/fields/rcc/rcc_g4.yaml b/devices/fields/rcc/rcc_g4.yaml new file mode 100644 index 000000000..998bb8649 --- /dev/null +++ b/devices/fields/rcc/rcc_g4.yaml @@ -0,0 +1,352 @@ +CR: + CSSON: + "Off": [0, Clock security system disabled (clock detector OFF)] + "On": [1, "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] + HSEBYP: + NotBypassed: [0, HSE crystal oscillator not bypassed] + Bypassed: [1, HSE crystal oscillator bypassed with external clock] + "*RDY": + _read: + NotReady: [0, Clock not ready] + Ready: [1, Clock ready] + HSION,HSEON,PLLON,PLLI2SON,PLLSAION: + "Off": [0, Clock Off] + "On": [1, Clock On] + +CFGR: + MCOPRE: + Div1: [0, MCO divided by 1] + Div2: [1, MCO divided by 2] + Div4: [2, MCO divided by 4] + Div8: [3, MCO divided by 8] + Div16: [4, MCO divided by 16] + MCOSEL: + None: [0, "MCO output disabled, no clock on MCO"] + SYSCLK: [1, SYSCLK system clock selected] + MSI: [2, MSI clock selected] + HSI: [3, HSI clock selected] + HSE: [4, HSE clock selected] + PLL: [5, Main PLL clock selected] + LSI: [6, LSI clock selected] + LSE: [7, LSE clock selected] + HSI48: [8, Internal HSI48 clock selected] + PPRE*: + Div1: [-1, HCLK not divided] + Div2: [4, HCLK divided by 2] + Div4: [5, HCLK divided by 4] + Div8: [6, HCLK divided by 8] + Div16: [7, HCLK divided by 16] + HPRE: + Div1: [-1, SYSCLK not divided] + Div2: [8, SYSCLK divided by 2] + Div4: [9, SYSCLK divided by 4] + Div8: [10, SYSCLK divided by 8] + Div16: [11, SYSCLK divided by 16] + Div64: [12, SYSCLK divided by 64] + Div128: [13, SYSCLK divided by 128] + Div256: [14, SYSCLK divided by 256] + Div512: [15, SYSCLK divided by 512] + SWS: + _read: + MSI: [0, MSI oscillator used as system clock] + HSI: [1, HSI oscillator used as system clock] + HSE: [2, HSE used as system clock] + PLL: [3, PLL used as system clock] + SW: + MSI: [0, MSI selected as system clock] + HSI: [1, HSI selected as system clock] + HSE: [2, HSE selected as system clock] + PLL: [3, PLL selected as system clock] + +PLLCFGR: + PLLPDIV: + PLLP: [0, pll_p_ck is controlled by PLLP] + Div2: [2, "pll_p_ck = vco_ck / 2"] + Div3: [3, "pll_p_ck = vco_ck / 3"] + Div4: [4, "pll_p_ck = vco_ck / 4"] + Div5: [5, "pll_p_ck = vco_ck / 5"] + Div6: [6, "pll_p_ck = vco_ck / 6"] + Div7: [7, "pll_p_ck = vco_ck / 7"] + Div8: [8, "pll_p_ck = vco_ck / 8"] + Div9: [9, "pll_p_ck = vco_ck / 9"] + Div10: [10, "pll_p_ck = vco_ck / 10"] + Div11: [11, "pll_p_ck = vco_ck / 11"] + Div12: [12, "pll_p_ck = vco_ck / 12"] + Div13: [13, "pll_p_ck = vco_ck / 13"] + Div14: [14, "pll_p_ck = vco_ck / 14"] + Div15: [15, "pll_p_ck = vco_ck / 15"] + Div16: [16, "pll_p_ck = vco_ck / 16"] + Div17: [17, "pll_p_ck = vco_ck / 17"] + Div18: [18, "pll_p_ck = vco_ck / 18"] + Div19: [19, "pll_p_ck = vco_ck / 19"] + Div20: [20, "pll_p_ck = vco_ck / 20"] + Div21: [21, "pll_p_ck = vco_ck / 21"] + Div22: [22, "pll_p_ck = vco_ck / 22"] + Div23: [23, "pll_p_ck = vco_ck / 23"] + Div24: [24, "pll_p_ck = vco_ck / 24"] + Div25: [25, "pll_p_ck = vco_ck / 25"] + Div26: [26, "pll_p_ck = vco_ck / 26"] + Div27: [27, "pll_p_ck = vco_ck / 27"] + Div28: [28, "pll_p_ck = vco_ck / 28"] + Div29: [29, "pll_p_ck = vco_ck / 29"] + Div30: [30, "pll_p_ck = vco_ck / 30"] + Div31: [31, "pll_p_ck = vco_ck / 31"] + PLLR: + Div2: [0, "pll_r_ck = vco_ck / 2"] + Div4: [1, "pll_r_ck = vco_ck / 4"] + Div6: [2, "pll_r_ck = vco_ck / 6"] + Div8: [3, "pll_r_ck = vco_ck / 8"] + PLLQ: + Div2: [0, "pll_q_ck = vco_ck / 2"] + Div4: [1, "pll_q_ck = vco_ck / 4"] + Div6: [2, "pll_q_ck = vco_ck / 6"] + Div8: [3, "pll_q_ck = vco_ck / 8"] + PLLP: + Div7: [0, "pll_p_ck = vco_ck / 7"] + Div17: [1, "pll_p_ck = vco_ck / 17"] + PLLN: + Div8: [8, "pll_n_ck = vco_ck / 8"] + Div9: [9, "pll_n_ck = vco_ck / 9"] + Div10: [10, "pll_n_ck = vco_ck / 10"] + Div11: [11, "pll_n_ck = vco_ck / 11"] + Div12: [12, "pll_n_ck = vco_ck / 12"] + Div13: [13, "pll_n_ck = vco_ck / 13"] + Div14: [14, "pll_n_ck = vco_ck / 14"] + Div15: [15, "pll_n_ck = vco_ck / 15"] + Div16: [16, "pll_n_ck = vco_ck / 16"] + Div17: [17, "pll_n_ck = vco_ck / 17"] + Div18: [18, "pll_n_ck = vco_ck / 18"] + Div19: [19, "pll_n_ck = vco_ck / 19"] + Div20: [20, "pll_n_ck = vco_ck / 20"] + Div21: [21, "pll_n_ck = vco_ck / 21"] + Div22: [22, "pll_n_ck = vco_ck / 22"] + Div23: [23, "pll_n_ck = vco_ck / 23"] + Div24: [24, "pll_n_ck = vco_ck / 24"] + Div25: [25, "pll_n_ck = vco_ck / 25"] + Div26: [26, "pll_n_ck = vco_ck / 26"] + Div27: [27, "pll_n_ck = vco_ck / 27"] + Div28: [28, "pll_n_ck = vco_ck / 28"] + Div29: [29, "pll_n_ck = vco_ck / 29"] + Div30: [30, "pll_n_ck = vco_ck / 30"] + Div31: [31, "pll_n_ck = vco_ck / 31"] + Div32: [32, "pll_n_ck = vco_ck / 32"] + Div33: [33, "pll_n_ck = vco_ck / 33"] + Div34: [34, "pll_n_ck = vco_ck / 34"] + Div35: [35, "pll_n_ck = vco_ck / 35"] + Div36: [36, "pll_n_ck = vco_ck / 36"] + Div37: [37, "pll_n_ck = vco_ck / 37"] + Div38: [38, "pll_n_ck = vco_ck / 38"] + Div39: [39, "pll_n_ck = vco_ck / 39"] + Div40: [40, "pll_n_ck = vco_ck / 40"] + Div41: [41, "pll_n_ck = vco_ck / 41"] + Div42: [42, "pll_n_ck = vco_ck / 42"] + Div43: [43, "pll_n_ck = vco_ck / 43"] + Div44: [44, "pll_n_ck = vco_ck / 44"] + Div45: [45, "pll_n_ck = vco_ck / 45"] + Div46: [46, "pll_n_ck = vco_ck / 46"] + Div47: [47, "pll_n_ck = vco_ck / 47"] + Div48: [48, "pll_n_ck = vco_ck / 48"] + Div49: [49, "pll_n_ck = vco_ck / 49"] + Div50: [50, "pll_n_ck = vco_ck / 50"] + Div51: [51, "pll_n_ck = vco_ck / 51"] + Div52: [52, "pll_n_ck = vco_ck / 52"] + Div53: [53, "pll_n_ck = vco_ck / 53"] + Div54: [54, "pll_n_ck = vco_ck / 54"] + Div55: [55, "pll_n_ck = vco_ck / 55"] + Div56: [56, "pll_n_ck = vco_ck / 56"] + Div57: [57, "pll_n_ck = vco_ck / 57"] + Div58: [58, "pll_n_ck = vco_ck / 58"] + Div59: [59, "pll_n_ck = vco_ck / 59"] + Div60: [60, "pll_n_ck = vco_ck / 60"] + Div61: [61, "pll_n_ck = vco_ck / 61"] + Div62: [62, "pll_n_ck = vco_ck / 62"] + Div63: [63, "pll_n_ck = vco_ck / 63"] + Div64: [64, "pll_n_ck = vco_ck / 64"] + Div65: [65, "pll_n_ck = vco_ck / 65"] + Div66: [66, "pll_n_ck = vco_ck / 66"] + Div67: [67, "pll_n_ck = vco_ck / 67"] + Div68: [68, "pll_n_ck = vco_ck / 68"] + Div69: [69, "pll_n_ck = vco_ck / 69"] + Div70: [70, "pll_n_ck = vco_ck / 70"] + Div71: [71, "pll_n_ck = vco_ck / 71"] + Div72: [72, "pll_n_ck = vco_ck / 72"] + Div73: [73, "pll_n_ck = vco_ck / 73"] + Div74: [74, "pll_n_ck = vco_ck / 74"] + Div75: [75, "pll_n_ck = vco_ck / 75"] + Div76: [76, "pll_n_ck = vco_ck / 76"] + Div77: [77, "pll_n_ck = vco_ck / 77"] + Div78: [78, "pll_n_ck = vco_ck / 78"] + Div79: [79, "pll_n_ck = vco_ck / 79"] + Div80: [80, "pll_n_ck = vco_ck / 80"] + Div81: [81, "pll_n_ck = vco_ck / 81"] + Div82: [82, "pll_n_ck = vco_ck / 82"] + Div83: [83, "pll_n_ck = vco_ck / 83"] + Div84: [84, "pll_n_ck = vco_ck / 84"] + Div85: [85, "pll_n_ck = vco_ck / 85"] + Div86: [86, "pll_n_ck = vco_ck / 86"] + Div87: [87, "pll_n_ck = vco_ck / 87"] + Div88: [88, "pll_n_ck = vco_ck / 88"] + Div89: [89, "pll_n_ck = vco_ck / 89"] + Div90: [90, "pll_n_ck = vco_ck / 90"] + Div91: [91, "pll_n_ck = vco_ck / 91"] + Div92: [92, "pll_n_ck = vco_ck / 92"] + Div93: [93, "pll_n_ck = vco_ck / 93"] + Div94: [94, "pll_n_ck = vco_ck / 94"] + Div95: [95, "pll_n_ck = vco_ck / 95"] + Div96: [96, "pll_n_ck = vco_ck / 96"] + Div97: [97, "pll_n_ck = vco_ck / 97"] + Div98: [98, "pll_n_ck = vco_ck / 98"] + Div99: [99, "pll_n_ck = vco_ck / 99"] + Div100: [100, "pll_n_ck = vco_ck / 100"] + Div101: [101, "pll_n_ck = vco_ck / 101"] + Div102: [102, "pll_n_ck = vco_ck / 102"] + Div103: [103, "pll_n_ck = vco_ck / 103"] + Div104: [104, "pll_n_ck = vco_ck / 104"] + Div105: [105, "pll_n_ck = vco_ck / 105"] + Div106: [106, "pll_n_ck = vco_ck / 106"] + Div107: [107, "pll_n_ck = vco_ck / 107"] + Div108: [108, "pll_n_ck = vco_ck / 108"] + Div109: [109, "pll_n_ck = vco_ck / 109"] + Div110: [110, "pll_n_ck = vco_ck / 110"] + Div111: [111, "pll_n_ck = vco_ck / 111"] + Div112: [112, "pll_n_ck = vco_ck / 112"] + Div113: [113, "pll_n_ck = vco_ck / 113"] + Div114: [114, "pll_n_ck = vco_ck / 114"] + Div115: [115, "pll_n_ck = vco_ck / 115"] + Div116: [116, "pll_n_ck = vco_ck / 116"] + Div117: [117, "pll_n_ck = vco_ck / 117"] + Div118: [118, "pll_n_ck = vco_ck / 118"] + Div119: [119, "pll_n_ck = vco_ck / 119"] + Div120: [120, "pll_n_ck = vco_ck / 120"] + Div121: [121, "pll_n_ck = vco_ck / 121"] + Div122: [122, "pll_n_ck = vco_ck / 122"] + Div123: [123, "pll_n_ck = vco_ck / 123"] + Div124: [124, "pll_n_ck = vco_ck / 124"] + Div125: [125, "pll_n_ck = vco_ck / 125"] + Div126: [126, "pll_n_ck = vco_ck / 126"] + Div127: [127, "pll_n_ck = vco_ck / 127"] + PLLM: + Div1: [0, "pll_p_ck = vco_ck / 1"] + Div2: [1, "pll_p_ck = vco_ck / 2"] + Div3: [2, "pll_p_ck = vco_ck / 3"] + Div4: [3, "pll_p_ck = vco_ck / 4"] + Div5: [4, "pll_p_ck = vco_ck / 5"] + Div6: [5, "pll_p_ck = vco_ck / 6"] + Div7: [6, "pll_p_ck = vco_ck / 7"] + Div8: [7, "pll_p_ck = vco_ck / 8"] + Div9: [8, "pll_p_ck = vco_ck / 9"] + Div10: [9, "pll_p_ck = vco_ck / 10"] + Div11: [10, "pll_p_ck = vco_ck / 11"] + Div12: [11, "pll_p_ck = vco_ck / 12"] + Div13: [12, "pll_p_ck = vco_ck / 13"] + Div14: [13, "pll_p_ck = vco_ck / 14"] + Div15: [14, "pll_p_ck = vco_ck / 15"] + Div16: [15, "pll_p_ck = vco_ck / 16"] + PLLSRC: + None: [0, No clock sent to PLL] + HSI16: [2, HSI16 sent to PLL input] + HSE: [3, HSE sent to PLL input] + +BDCR: + LSCOSEL: + LSI: [0, LSI clock selected] + LSE: [1, LSE clock selected] + LSCOEN: + Disabled: [0, LSCO disabled] + Enabled: [1, LSCO enabled] + BDRST: + Disabled: [0, Reset not activated] + Enabled: [1, Reset the entire RTC domain] + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + LSERDY: + _read: + NotReady: [0, LSE clock not ready] + Ready: [1, LSE clock ready] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock used as RTC clock] + LSI: [2, LSI oscillator clock used as RTC clock] + HSE: [3, HSE oscillator clock divided by a prescaler used as RTC clock] + LSEON: + "Off": [0, LSE only enabled when requested by a peripheral or system function] + "On": [1, LSE enabled always generated by RCC] + LSECSSD: + _read: + NoFailure: [0, No failure detected on LSE (32 kHz oscillator)] + Failure: [1, Failure detected on LSE (32 kHz oscillator)] + LSECSSON: + "Off": [0, CSS on LSE (32 kHz external oscillator) OFF] + "On": [1, CSS on LSE (32 kHz external oscillator) ON] + LSEDRV: + Lower: [0, "'Xtal mode' lower driving capability"] + MediumLow: [1, "'Xtal mode' medium low driving capability"] + MediumHigh: [2, "'Xtal mode' medium high driving capability"] + Higher: [3, "'Xtal mode' higher driving capability"] + LSEBYP: + NotBypassed: [0, LSE crystal oscillator not bypassed] + Bypassed: [1, LSE crystal oscillator bypassed with external clock] + +CSR: + "*RSTF": + _read: + NoReset: [0, No reset has occured] + Reset: [1, A reset has occured] + RMVF: + _write: + Clear: [1, Clears the reset flag] + LSIRDY: + _read: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSION: + "Off": [0, LSI oscillator Off] + "On": [1, LSI oscillator On] + +CCIPR: + ADC*SEL: + None: [0, No clock selected for ADC] + PLLP: [1, "PLL 'P' clock selected for ADC"] + System: [2, System clock selected for ADC] + CLK48SEL: + HSI48: [0, HSI48 clock selected as 48MHz clock] + PLLQ: [2, "PLL 'Q' (PLL48M1CLK) clock selected as 48MHz clock"] + FDCANSEL: + HSE: [0, HSE clock selected as FDCAN clock] + PLLQ: [1, "PLL 'Q' clock selected as FDCAN clock"] + PCLK: [2, PCLK clock selected as FDCAN clock] + I2S23SEL: + System: [0, System clock selected as I2S23 clock] + PLLQ: [1, "PLL 'Q' clock selected as I2S23 clock"] + I2S_CKIN: [2, Clock provided on I2S_CKIN pin is selected as I2S23 clock] + HSI16: [3, HSI16 clock selected as I2S23 clock] + SAI1SEL: + System: [0, System clock selected as SAI clock] + PLLQ: [1, "PLL 'Q' clock selected as SAI clock"] + I2S_CKIN: [2, Clock provided on I2S_CKIN pin is selected as SAI clock] + HSI16: [3, HSI16 clock selected as SAI clock] + LPTIM1SEL: + PCLK: [0, PCLK clock selected as LPTIM1 clock] + LSI: [1, LSI clock selected as LPTIM1 clock] + HSI16: [2, HSI16 clock selected as LPTIM1 clock] + LSE: [3, LSE clock selected as LPTIM1 clock] + I2C*SEL: + PCLK: [0, PCLK clock selected as I2C clock] + System: [1, System clock (SYSCLK) selected as I2C clock] + HSI16: [2, HSI16 clock selected as I2C clock] + "*UART*SEL": + PCLK: [0, PCLK clock selected as UART clock] + System: [1, System clock (SYSCLK) selected as UART clock] + HSI16: [2, HSI16 clock selected as UART clock] + LSE: [3, LSE clock selected as UART clock] + +CCIPR2: + QSPISEL: + System: [0, System clock selected as QUADSPI kernel clock] + HSI16: [1, HSI16 clock selected as QUADSPI kernel clock] + PLLQ: [2, "PLL 'Q' clock selected as QUADSPI kernel clock"] + I2C4SEL: + PCLK: [0, PCLK clock selected as I2C clock] + System: [1, System clock (SYSCLK) selected as I2C clock] + HSI16: [2, HSI16 clock selected as I2C clock] diff --git a/devices/fields/rcc/rcc_l0.yaml b/devices/fields/rcc/rcc_l0.yaml new file mode 100644 index 000000000..961fd6935 --- /dev/null +++ b/devices/fields/rcc/rcc_l0.yaml @@ -0,0 +1,152 @@ +# RCC peripheral +# Applicable to STM32L0xx + +CR: + HSI16OUTEN: + Disabled: [0, HSI output clock disabled] + Enabled: [1, HSI output clock enabled] + HSI16DIVF: + _read: + NotDivided: [0, 16 MHz HSI clock not divided] + Div4: [1, 16 MHz HSI clock divided by 4] + HSI16DIVEN: + NotDivided: [0, no 16 MHz HSI division requested] + Div4: [1, 16 MHz HSI division by 4 requested] + HSI16RDYF: + _read: + NotReady: [0, HSI 16 MHz oscillator not ready] + Ready: [1, HSI 16 MHz oscillator ready] +ICSCR: + MSITRIM: [0, 255] + MSICAL: [0, 255] + MSIRANGE: + Range0: [0, range 0 around 65.536 kHz] + Range1: [1, range 1 around 131.072 kHz] + Range2: [2, range 2 around 262.144 kHz] + Range3: [3, range 3 around 524.288 kHz] + Range4: [4, range 4 around 1.048 MHz] + Range5: [5, range 5 around 2.097 MHz (reset value)] + Range6: [6, range 6 around 4.194 MHz] + Range7: [7, not allowed] + HSI16TRIM: [0, 31] + HSI16CAL: [0, 255] +CFGR: + MCOSEL: + NoClock: [0, No clock] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI oscillator clock selected] + MSI: [3, MSI oscillator clock selected] + HSE: [4, HSE oscillator clock selected] + PLL: [5, PLL clock selected] + LSI: [6, LSI oscillator clock selected] + LSE: [7, LSE oscillator clock selected] + PLLSRC: + HSI16: [0, HSI selected as PLL input clock] + HSE: [1, HSE selected as PLL input clock] + STOPWUCK: + MSI: [0, Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock] + HSI16: [1, "Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1)"] + SWS: + MSI: [0, MSI oscillator used as system clock] + HSI16: [1, HSI oscillator used as system clock] + HSE: [2, HSE oscillator used as system clock] + PLL: [3, PLL used as system clock] + SW: + MSI: [0, MSI oscillator used as system clock] + HSI16: [1, HSI oscillator used as system clock] + HSE: [2, HSE oscillator used as system clock] + PLL: [3, PLL used as system clock] +CIER: + CSSLSE: + Disabled: [0, LSE CSS interrupt disabled] + Enabled: [1, LSE CSS interrupt enabled] + "*RDYIE": + Disabled: [0, Ready interrupt disabled] + Enabled: [1, Ready interrupt enabled] +CIFR: + CSSHSEF: + NoClock: [0, No clock security interrupt caused by HSE clock failure] + Clock: [1, Clock security interrupt caused by HSE clock failure] + CSSLSEF: + NoFailure: [0, No failure detected on LSE clock failure] + Failure: [1, Failure detected on LSE clock failure] + "*RDYF": + _read: + NotInterrupted: [0, No clock ready interrupt] + Interrupted: [1, Clock ready interrupt] +CICR: + "*SEC,*RDYC": + _write: + Clear: [1, Clear interrupt flag] +IOPRSTR: + IOP*RST: + Reset: [1, Reset I/O port] +IOPENR: + IOP*EN: + Disabled: [0, Port clock disabled] + Enabled: [1, Port clock enabled] +CCIPR: + LPTIM1SEL: + APB: [0, APB clock selected as Timer clock] + LSI: [1, LSI clock selected as Timer clock] + HSI16: [2, HSI16 clock selected as Timer clock] + LSE: [3, LSE clock selected as Timer clock] + I2C?SEL: + APB: [0, APB clock selected as peripheral clock] + SYSTEM: [1, System clock selected as peripheral clock] + HSI16: [2, HSI16 clock selected as peripheral clock] + "LPUART1SEL,USART?SEL": + APB: [0, APB clock selected as peripheral clock] + SYSTEM: [1, System clock selected as peripheral clock] + HSI16: [2, HSI16 clock selected as peripheral clock] + LSE: [3, LSE clock selected as peripheral clock] +CSR: + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock used as RTC clock] + LSI: [2, LSI oscillator clock used as RTC clock] + HSE: + [ + 3, + "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock", + ] + CSSLSED: + NoFailure: [0, No failure detected on LSE (32 kHz oscillator)] + Failure: [1, Failure detected on LSE (32 kHz oscillator)] + LSEDRV: + Low: [0, Lowest drive] + MediumLow: [1, Medium low drive] + MediumHigh: [2, Medium high drive] + High: [3, Highest drive] + LSEBYP: + NotBypassed: [0, LSE oscillator not bypassed] + Bypassed: [1, LSE oscillator bypassed] + "*ON": + "Off": [0, Oscillator OFF] + "On": [1, Oscillator ON] + "*RDY": + NotReady: [0, Oscillator not ready] + Ready: [1, Oscillator ready] +IOPSMEN: + IOP?SMEN: + Disabled: [0, Port x clock is disabled in Sleep mode] + Enabled: [1, Port x clock is enabled in Sleep mode (if enabled by IOPHEN)] +AHBSMENR: + CRYPSMEN: + Disabled: [0, Crypto clock disabled in Sleep mode] + Enabled: [1, Crypto clock enabled in Sleep mode] + CRCSMEN: + Disabled: [0, Test integration module clock disabled in Sleep mode] + Enabled: [1, Test integration module clock enabled in Sleep mode (if enabled by CRCEN)] + SRAMSMEN: + Disabled: [0, NVM interface clock disabled in Sleep mode] + Enabled: [1, NVM interface clock enabled in Sleep mode] + MIFSMEN: + Disabled: [0, NVM interface clock disabled in Sleep mode] + Enabled: [1, NVM interface clock enabled in Sleep mode] + DMASMEN: + Disabled: [0, DMA clock disabled in Sleep mode] + Enabled: [1, DMA clock enabled in Sleep mode] diff --git a/devices/fields/rcc/rcc_l0_l1_common.yaml b/devices/fields/rcc/rcc_l0_l1_common.yaml new file mode 100644 index 000000000..152b62e3d --- /dev/null +++ b/devices/fields/rcc/rcc_l0_l1_common.yaml @@ -0,0 +1,84 @@ +CR: + RTCPRE: + Div2: [0, HSE divided by 2] + Div4: [1, HSE divided by 4] + Div8: [2, HSE divided by 8] + Div16: [3, HSE divided by 16] + "*ON": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + PLLRDY: + _read: + Unlocked: [0, PLL unlocked] + Locked: [1, PLL locked] + HSEBYP: + NotBypassed: [0, HSE oscillator not bypassed] + Bypassed: [1, HSE oscillator bypassed] + "HSERDY,HSIRDY,MSIRDY": + _read: + NotReady: [0, Oscillator is not stable] + Ready: [1, Oscillator is stable] +CFGR: + MCOPRE: + Div1: [0, No division] + Div2: [1, Division by 2] + Div4: [2, Division by 4] + Div8: [3, Division by 8] + Div16: [4, Division by 16] + PLLDIV: + Div2: [1, PLLVCO / 2] + Div3: [2, PLLVCO / 3] + Div4: [3, PLLVCO / 4] + PLLMUL: + Mul3: [0, PLL clock entry x 3] + Mul4: [1, PLL clock entry x 4] + Mul6: [2, PLL clock entry x 6] + Mul8: [3, PLL clock entry x 8] + Mul12: [4, PLL clock entry x 12] + Mul16: [5, PLL clock entry x 16] + Mul24: [6, PLL clock entry x 24] + Mul32: [7, PLL clock entry x 32] + Mul48: [8, PLL clock entry x 48] + "PPRE[12]": + Div1: [-1, HCLK not divided] + Div2: [4, HCLK divided by 2] + Div4: [5, HCLK divided by 4] + Div8: [6, HCLK divided by 8] + Div16: [7, HCLK divided by 16] + HPRE: + Div1: [-1, system clock not divided] + Div2: [8, system clock divided by 2] + Div4: [9, system clock divided by 4] + Div8: [10, system clock divided by 8] + Div16: [11, system clock divided by 16] + Div64: [12, system clock divided by 64] + Div128: [13, system clock divided by 128] + Div256: [14, system clock divided by 256] + Div512: [15, system clock divided by 512] +AHBRSTR: + "*RST": + _write: + Reset: [1, Reset the module] +"APB[12]RSTR": + "*RST": + _write: + Reset: [1, Reset the module] +AHBENR: + "*EN": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] +APB*ENR: + "*EN": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] +CSR: + "*RSTF": + _read: + NoReset: [0, No reset has occured] + Reset: [1, A reset has occured] + RMVF: + _write: + Clear: [1, Clears the reset flag] + RTCRST: + _write: + Reset: [1, Resets the RTC peripheral] diff --git a/devices/fields/rcc/rcc_l0x0.yaml b/devices/fields/rcc/rcc_l0x0.yaml new file mode 100644 index 000000000..b94a09aac --- /dev/null +++ b/devices/fields/rcc/rcc_l0x0.yaml @@ -0,0 +1,149 @@ +# RCC peripheral +# Applicable to STM32L0xx + +CR: + HSI16OUTEN: + Disabled: [0, HSI output clock disabled] + Enabled: [1, HSI output clock enabled] + HSI16DIVF: + _read: + NotDivided: [0, 16 MHz HSI clock not divided] + Div4: [1, 16 MHz HSI clock divided by 4] + HSI16DIVEN: + NotDivided: [0, no 16 MHz HSI division requested] + Div4: [1, 16 MHz HSI division by 4 requested] + HSI16RDYF: + _read: + NotReady: [0, HSI 16 MHz oscillator not ready] + Ready: [1, HSI 16 MHz oscillator ready] +ICSCR: + MSITRIM: [0, 255] + MSICAL: [0, 255] + MSIRANGE: + Range0: [0, range 0 around 65.536 kHz] + Range1: [1, range 1 around 131.072 kHz] + Range2: [2, range 2 around 262.144 kHz] + Range3: [3, range 3 around 524.288 kHz] + Range4: [4, range 4 around 1.048 MHz] + Range5: [5, range 5 around 2.097 MHz (reset value)] + Range6: [6, range 6 around 4.194 MHz] + Range7: [7, not allowed] + HSI16TRIM: [0, 31] + HSI16CAL: [0, 255] +CFGR: + MCOSEL: + NoClock: [0, No clock] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI oscillator clock selected] + MSI: [3, MSI oscillator clock selected] + HSE: [4, HSE oscillator clock selected] + PLL: [5, PLL clock selected] + LSI: [6, LSI oscillator clock selected] + LSE: [7, LSE oscillator clock selected] + PLLSRC: + HSI16: [0, HSI selected as PLL input clock] + HSE: [1, HSE selected as PLL input clock] + STOPWUCK: + MSI: [0, Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock] + HSI16: [1, "Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1)"] + SWS: + MSI: [0, MSI oscillator used as system clock] + HSI16: [1, HSI oscillator used as system clock] + HSE: [2, HSE oscillator used as system clock] + PLL: [3, PLL used as system clock] + SW: + MSI: [0, MSI oscillator used as system clock] + HSI16: [1, HSI oscillator used as system clock] + HSE: [2, HSE oscillator used as system clock] + PLL: [3, PLL used as system clock] +CIER: + CSSLSE: + Disabled: [0, LSE CSS interrupt disabled] + Enabled: [1, LSE CSS interrupt enabled] + "*RDYIE": + Disabled: [0, Ready interrupt disabled] + Enabled: [1, Ready interrupt enabled] +CIFR: + CSSHSEF: + NoClock: [0, No clock security interrupt caused by HSE clock failure] + Clock: [1, Clock security interrupt caused by HSE clock failure] + CSSLSEF: + NoFailure: [0, No failure detected on LSE clock failure] + Failure: [1, Failure detected on LSE clock failure] + "*RDYF": + _read: + NotInterrupted: [0, No clock ready interrupt] + Interrupted: [1, Clock ready interrupt] +CICR: + "*SEC,*RDYC": + _write: + Clear: [1, Clear interrupt flag] +IOPRSTR: + IOP*RST: + Reset: [1, Reset I/O port] +IOPENR: + IOP*EN: + Disabled: [0, Port clock disabled] + Enabled: [1, Port clock enabled] +CCIPR: + LPTIM1SEL: + APB: [0, APB clock selected as Timer clock] + LSI: [1, LSI clock selected as Timer clock] + HSI16: [2, HSI16 clock selected as Timer clock] + LSE: [3, LSE clock selected as Timer clock] + I2C?SEL: + APB: [0, APB clock selected as peripheral clock] + SYSTEM: [1, System clock selected as peripheral clock] + HSI16: [2, HSI16 clock selected as peripheral clock] + "LPUART1SEL,USART?SEL": + APB: [0, APB clock selected as peripheral clock] + SYSTEM: [1, System clock selected as peripheral clock] + HSI16: [2, HSI16 clock selected as peripheral clock] + LSE: [3, LSE clock selected as peripheral clock] +CSR: + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock used as RTC clock] + LSI: [2, LSI oscillator clock used as RTC clock] + HSE: + [ + 3, + "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock", + ] + CSSLSED: + NoFailure: [0, No failure detected on LSE (32 kHz oscillator)] + Failure: [1, Failure detected on LSE (32 kHz oscillator)] + LSEDRV: + Low: [0, Lowest drive] + MediumLow: [1, Medium low drive] + MediumHigh: [2, Medium high drive] + High: [3, Highest drive] + LSEBYP: + NotBypassed: [0, LSE oscillator not bypassed] + Bypassed: [1, LSE oscillator bypassed] + "*ON": + "Off": [0, Oscillator OFF] + "On": [1, Oscillator ON] + "*RDY": + NotReady: [0, Oscillator not ready] + Ready: [1, Oscillator ready] +IOPSMEN: + IOP?SMEN: + Disabled: [0, Port x clock is disabled in Sleep mode] + Enabled: [1, Port x clock is enabled in Sleep mode (if enabled by IOPHEN)] +AHBSMENR: + CRCSMEN: + Disabled: [0, Test integration module clock disabled in Sleep mode] + Enabled: [1, Test integration module clock enabled in Sleep mode (if enabled by CRCEN)] + SRAMSMEN: + Disabled: [0, NVM interface clock disabled in Sleep mode] + Enabled: [1, NVM interface clock enabled in Sleep mode] + MIFSMEN: + Disabled: [0, NVM interface clock disabled in Sleep mode] + Enabled: [1, NVM interface clock enabled in Sleep mode] + DMASMEN: + Disabled: [0, DMA clock disabled in Sleep mode] + Enabled: [1, DMA clock enabled in Sleep mode] diff --git a/devices/fields/rcc/rcc_l1.yaml b/devices/fields/rcc/rcc_l1.yaml new file mode 100644 index 000000000..9efe436f8 --- /dev/null +++ b/devices/fields/rcc/rcc_l1.yaml @@ -0,0 +1,56 @@ +# RCC peripheral +# Applicable to STM32L1xx + +CFGR: + MCOSEL: + NoClock: [0, No clock] + SYSCLK: [1, SYSCLK clock selected] + HSI: [2, HSI oscillator clock selected] + MSI: [3, MSI oscillator clock selected] + HSE: [4, HSE oscillator clock selected] + PLL: [5, PLL clock selected] + LSI: [6, LSI oscillator clock selected] + LSE: [7, LSE oscillator clock selected] + PLLSRC: + HSI: [0, HSI selected as PLL input clock] + HSE: [1, HSE selected as PLL input clock] + SWS: + _read: + HSI: [0, MSI oscillator used as system clock] + MSI: [1, HSI oscillator used as system clock] + HSE: [2, HSE oscillator used as system clock] + PLL: [3, PLL used as system clock] + SW: + HSI: [0, MSI oscillator used as system clock] + MSI: [1, HSI oscillator used as system clock] + HSE: [2, HSE oscillator used as system clock] + PLL: [3, PLL used as system clock] +CIR: + "*CSSC": + _write: + Clear: [1, Clear interrupt] + "*RDYC": + _write: + Clear: [1, Clear interrupt] + LSECSSIE: + Disabled: [0, LSE CSS interrupt disabled] + Enabled: [1, LSE CSS interrupt enabled] + "*RDYIE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + CSSF: + _read: + NotInterupted: [0, No clock security interrupt caused by HSE clock failure] + Interupted: [1, Clock security interrupt caused by HSE clock failure] + LSECSSF: + _read: + NoFailure: [0, No failure detected on the external 32 KHz oscillator] + Failure: [1, A failure is detected on the external 32 kHz oscillator] + "*RDYF": + _read: + NotStable: [0, Clock is not stable] + Stable: [1, Clock is stable] +AHBLPENR: + "*EN": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] diff --git a/devices/fields/rcc/rcc_l4+.yaml b/devices/fields/rcc/rcc_l4+.yaml new file mode 100644 index 000000000..9afdefadc --- /dev/null +++ b/devices/fields/rcc/rcc_l4+.yaml @@ -0,0 +1,1043 @@ +# Registers for the L4+ series are again completely different from any other... + +CR: + PLLSAI2RDY: + Unlocked: [0, PLLSAI2 unlocked] + Locked: [1, PLLSAI2 locked] + PLLSAI2ON: + Disabled: [0, PLLSAI2 OFF] + Enabled: [1, PLLSAI2 ON] + PLLSAI1RDY: + Unlocked: [0, PLLSAI1 unlocked] + Locked: [1, PLLSAI1 locked] + PLLSAI1ON: + Disabled: [0, PLLSAI1 OFF] + Enabled: [1, PLLSAI1 ON] + PLLRDY: + Unlocked: [0, PLL unlocked] + Locked: [1, PLL locked] + PLLON: + Disabled: [0, PLL OFF] + Enabled: [1, PLL ON] + CSSON: + Disabled: [0, Clock security system OFF (clock detector OFF)] + Enabled: [1, "Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not)"] + HSEBYP: + NotBypassed: [0, HSE crystal oscillator not bypassed] + Bypassed: [1, HSE crystal oscillator bypassed with external clock] + HSERDY: + NotReady: [0, HSE oscillator not ready] + Ready: [1, HSE oscillator ready] + HSEON: + Disabled: [0, HSE oscillator OFF] + Enabled: [1, HSE oscillator ON] + HSIASFS: + Disabled: [0, HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wakeup clock] + Enabled: [1, HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wakeup clock] + HSIRDY: + NotReady: [0, HSI16 oscillator not ready] + Ready: [1, HSI16 oscillator ready] + HSIKERON: + Disabled: [0, No effect on HSI16 oscillator] + Enabled: [1, HSI16 oscillator is forced ON even in Stop mode] + HSION: + Disabled: [0, HSI16 oscillator OFF] + Enabled: [1, HSI16 oscillator ON] + MSIRGSEL: + CSR: [0, "MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register"] + CR: [1, "MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register"] + MSIPLLEN: + Disabled: [0, MSI PLL OFF] + Enabled: [1, MSI PLL ON] + MSIRDY: + NotReady: [0, MSI oscillator not ready] + Ready: [1, MSI oscillator ready] + MSION: + Disabled: [0, MSI oscillator OFF] + Enabled: [1, MSI oscillator ON] + MSIRANGE: + Range100K: [0b0000, range 0 around 100 kHz] + Range200K: [0b0001, range 1 around 200 kHz] + Range400K: [0b0010, range 2 around 400 kHz] + Range800K: [0b0011, range 3 around 800 kHz] + Range1M: [0b0100, range 4 around 1 MHz] + Range2M: [0b0101, range 5 around 2 MHz] + Range4M: [0b0110, range 6 around 4 MHz] + Range8M: [0b0111, range 7 around 8 MHz] + Range16M: [0b1000, range 8 around 16 MHz] + Range24M: [0b1001, range 9 around 24 MHz] + Range32M: [0b1010, range 10 around 32 MHz] + Range48M: [0b1011, range 11 around 48 MHz] + +ICSCR: + HSITRIM: [0, 0x7F] + HSICAL: [0, 0xFF] + MSITRIM: [0, 0xFF] + MSICAL: [0, 0xFF] + +CFGR: + MCOPRE: + Divider1: [0, MCO is divided by 1] + Divider2: [1, MCO is divided by 2] + Divider4: [2, MCO is divided by 4] + Divider8: [3, MCO is divided by 8] + Divider16: [4, MCO is divided by 16] + MCOSEL: + Disabled: [0, "MCO output disabled, no clock on MCO"] + SYSCLK: [0b0001, SYSCLK system clock selected] + MSI: [0b0010, MSI clock selected.] + HSI16: [0b0011, HSI16 clock selected.] + HSE: [0b0100, HSE clock selected] + MainPLL: [0b0101, Main PLL clock selected] + LSI: [0b0110, LSI clock selected] + LSE: [0b0111, LSE clock selected] + HSI48: [0b1000, Internal HSI48 clock selected] + STOPWUCK: + MSI: [0, MSI oscillator selected as wakeup from stop clock and CSS backup clock] + HSI16: [1, HSI16 oscillator selected as wakeup from stop clock and CSS backup clock] + PPRE?: + Div1: [-1, HCLK not divided] + Div2: [0b100, HCLK divided by 2] + Div4: [0b101, HCLK divided by 4] + Div8: [0b110, HCLK divided by 8] + Div16: [0b111, HCLK divided by 16] + HPRE: + Div1: [-1, SYSCLK not divided] + Div2: [0b1000, SYSCLK divided by 2] + Div4: [0b1001, SYSCLK divided by 4] + Div8: [0b1010, SYSCLK divided by 8] + Div16: [0b1011, SYSCLK divided by 16] + Div64: [0b1100, SYSCLK divided by 64] + Div128: [0b1101, SYSCLK divided by 128] + Div256: [0b1110, SYSCLK divided by 256] + Div512: [0b1111, SYSCLK divided by 512] + SWS: + MSI: [0b00, MSI oscillator used as system clock] + HSI16: [0b01, HSI16 oscillator used as system clock] + HSE: [0b10, HSE used as system clock] + PLL: [0b11, PLL used as system clock] + SW: + MSI: [0b00, MSI selected as system clock] + HSI16: [0b01, HSI16 selected as system clock] + HSE: [0b10, HSE selected as system clock] + PLL: [0b11, PLL selected as system clock] + +PLLCFGR: + PLLPDIV: + PLLP: [0, PLLSAI3CLK is controlled by the bit PLLP] + Div2: [2, "PLLSAI3CLK = VCO / 2"] + Div3: [3, "PLLSAI3CLK = VCO / 3"] + Div4: [4, "PLLSAI3CLK = VCO / 4"] + Div5: [5, "PLLSAI3CLK = VCO / 5"] + Div6: [6, "PLLSAI3CLK = VCO / 6"] + Div7: [7, "PLLSAI3CLK = VCO / 7"] + Div8: [8, "PLLSAI3CLK = VCO / 8"] + Div9: [9, "PLLSAI3CLK = VCO / 9"] + Div10: [10, "PLLSAI3CLK = VCO / 10"] + Div11: [11, "PLLSAI3CLK = VCO / 11"] + Div12: [12, "PLLSAI3CLK = VCO / 12"] + Div13: [13, "PLLSAI3CLK = VCO / 13"] + Div14: [14, "PLLSAI3CLK = VCO / 14"] + Div15: [15, "PLLSAI3CLK = VCO / 15"] + Div16: [16, "PLLSAI3CLK = VCO / 16"] + Div17: [17, "PLLSAI3CLK = VCO / 17"] + Div18: [18, "PLLSAI3CLK = VCO / 18"] + Div19: [19, "PLLSAI3CLK = VCO / 19"] + Div20: [20, "PLLSAI3CLK = VCO / 20"] + Div21: [21, "PLLSAI3CLK = VCO / 21"] + Div22: [22, "PLLSAI3CLK = VCO / 22"] + Div23: [23, "PLLSAI3CLK = VCO / 23"] + Div24: [24, "PLLSAI3CLK = VCO / 24"] + Div25: [25, "PLLSAI3CLK = VCO / 25"] + Div26: [26, "PLLSAI3CLK = VCO / 26"] + Div27: [27, "PLLSAI3CLK = VCO / 27"] + Div28: [28, "PLLSAI3CLK = VCO / 28"] + Div29: [29, "PLLSAI3CLK = VCO / 29"] + Div30: [30, "PLLSAI3CLK = VCO / 30"] + Div31: [31, "PLLSAI3CLK = VCO / 31"] + PLL[RQ]: + Div2: [0, "PLLx = 2"] + Div4: [1, "PLLx = 4"] + Div6: [2, "PLLx = 6"] + Div8: [3, "PLLx = 8"] + PLLREN: + Disabled: [0, PLLCLK output disable] + Enabled: [1, PLLCLK output enabled] + PLLQEN: + Disabled: [0, PLL48M1CLK output disable] + Enabled: [1, PLL48M1CLK output enabled] + PLLP: + Div7: [0, "PLLP = 7"] + Div17: [1, "PLLP = 17"] + PLLPEN: + Disabled: [0, PLLSAI3CLK output disable] + Enabled: [1, PLLSAI3CLK output enabled] + PLLN: [8, 127] + PLLM: + Div1: [0, "PLLM = 1"] + Div2: [1, "PLLM = 2"] + Div3: [2, "PLLM = 3"] + Div4: [3, "PLLM = 4"] + Div5: [4, "PLLM = 5"] + Div6: [5, "PLLM = 6"] + Div7: [6, "PLLM = 7"] + Div8: [7, "PLLM = 8"] + Div9: [8, "PLLM = 9"] + Div10: [9, "PLLM = 11"] + Div11: [10, "PLLM = 12"] + Div12: [11, "PLLM = 13"] + Div13: [12, "PLLM = 13"] + Div14: [13, "PLLM = 14"] + Div15: [14, "PLLM = 15"] + Div16: [15, "PLLM = 16"] + PLLSRC: + NoClock: [0, No clock sent to PLL] + MSI: [1, MSI clock selected as PLL clock entry] + HSI16: [2, HSI16 clock selected as PLL clock entry] + HSE: [3, HSE clock selected as PLL clock entry] + +PLLSAI1CFGR: + PLLSAI1PDIV: + PLLSAI1P: [0, PLLSAI1CLK is controlled by the bit PLLSAI1P] + Div2: [2, "PLLSAI1CLK = VCOSAI / 2"] + Div3: [3, "PLLSAI1CLK = VCOSAI / 3"] + Div4: [4, "PLLSAI1CLK = VCOSAI / 4"] + Div5: [5, "PLLSAI1CLK = VCOSAI / 5"] + Div6: [6, "PLLSAI1CLK = VCOSAI / 6"] + Div7: [7, "PLLSAI1CLK = VCOSAI / 7"] + Div8: [8, "PLLSAI1CLK = VCOSAI / 8"] + Div9: [9, "PLLSAI1CLK = VCOSAI / 9"] + Div10: [10, "PLLSAI1CLK = VCOSAI / 10"] + Div11: [11, "PLLSAI1CLK = VCOSAI / 11"] + Div12: [12, "PLLSAI1CLK = VCOSAI / 12"] + Div13: [13, "PLLSAI1CLK = VCOSAI / 13"] + Div14: [14, "PLLSAI1CLK = VCOSAI / 14"] + Div15: [15, "PLLSAI1CLK = VCOSAI / 15"] + Div16: [16, "PLLSAI1CLK = VCOSAI / 16"] + Div17: [17, "PLLSAI1CLK = VCOSAI / 17"] + Div18: [18, "PLLSAI1CLK = VCOSAI / 18"] + Div19: [19, "PLLSAI1CLK = VCOSAI / 19"] + Div20: [20, "PLLSAI1CLK = VCOSAI / 20"] + Div21: [21, "PLLSAI1CLK = VCOSAI / 21"] + Div22: [22, "PLLSAI1CLK = VCOSAI / 22"] + Div23: [23, "PLLSAI1CLK = VCOSAI / 23"] + Div24: [24, "PLLSAI1CLK = VCOSAI / 24"] + Div25: [25, "PLLSAI1CLK = VCOSAI / 25"] + Div26: [26, "PLLSAI1CLK = VCOSAI / 26"] + Div27: [27, "PLLSAI1CLK = VCOSAI / 27"] + Div28: [28, "PLLSAI1CLK = VCOSAI / 28"] + Div29: [29, "PLLSAI1CLK = VCOSAI / 29"] + Div30: [30, "PLLSAI1CLK = VCOSAI / 30"] + Div31: [31, "PLLSAI1CLK = VCOSAI / 31"] + PLLSAI1REN: + Disabled: [0, PLLADC1CLK output disable] + Enabled: [1, PLLADC1CLK output enabled] + PLLSAI1[RQ]: + Div2: [0, "PLLSAI1x = 2"] + Div4: [1, "PLLSAI1x = 4"] + Div6: [2, "PLLSAI1x = 6"] + Div8: [3, "PLLSAI1x = 8"] + PLLSAI1QEN: + Disabled: [0, PLL48M2CLK output disable] + Enabled: [1, PLL48M2CLK output enabled] + PLLSAI1P: + Div7: [0, "PLLSAI1P = 7"] + Div17: [1, "PLLSAI1P = 17"] + PLLSAI1PEN: + Disabled: [0, PLLSAI1CLK output disable] + Enabled: [1, PLLSAI1CLK output enabled] + PLLSAI1N: [8, 127] + PLLSAI1M: + Div1: [0, "PLLSAI1M = 1"] + Div2: [1, "PLLSAI1M = 2"] + Div3: [2, "PLLSAI1M = 3"] + Div4: [3, "PLLSAI1M = 4"] + Div5: [4, "PLLSAI1M = 5"] + Div6: [5, "PLLSAI1M = 6"] + Div7: [6, "PLLSAI1M = 7"] + Div8: [7, "PLLSAI1M = 8"] + Div9: [8, "PLLSAI1M = 9"] + Div10: [9, "PLLSAI1M = 11"] + Div11: [10, "PLLSAI1M = 12"] + Div12: [11, "PLLSAI1M = 13"] + Div13: [12, "PLLSAI1M = 13"] + Div14: [13, "PLLSAI1M = 14"] + Div15: [14, "PLLSAI1M = 15"] + Div16: [15, "PLLSAI1M = 16"] + +PLLSAI2CFGR: + PLLSAI2PDIV: + PLLSAI1P: [0, PLLSAI2CLK is controlled by the bit PLLSAI2P] + Div2: [2, "PLLSAI2CLK = VCOSAI2 / 2"] + Div3: [3, "PLLSAI2CLK = VCOSAI2 / 3"] + Div4: [4, "PLLSAI2CLK = VCOSAI2 / 4"] + Div5: [5, "PLLSAI2CLK = VCOSAI2 / 5"] + Div6: [6, "PLLSAI2CLK = VCOSAI2 / 6"] + Div7: [7, "PLLSAI2CLK = VCOSAI2 / 7"] + Div8: [8, "PLLSAI2CLK = VCOSAI2 / 8"] + Div9: [9, "PLLSAI2CLK = VCOSAI2 / 9"] + Div10: [10, "PLLSAI2CLK = VCOSAI2 / 10"] + Div11: [11, "PLLSAI2CLK = VCOSAI2 / 11"] + Div12: [12, "PLLSAI2CLK = VCOSAI2 / 12"] + Div13: [13, "PLLSAI2CLK = VCOSAI2 / 13"] + Div14: [14, "PLLSAI2CLK = VCOSAI2 / 14"] + Div15: [15, "PLLSAI2CLK = VCOSAI2 / 15"] + Div16: [16, "PLLSAI2CLK = VCOSAI2 / 16"] + Div17: [17, "PLLSAI2CLK = VCOSAI2 / 17"] + Div18: [18, "PLLSAI2CLK = VCOSAI2 / 18"] + Div19: [19, "PLLSAI2CLK = VCOSAI2 / 19"] + Div20: [20, "PLLSAI2CLK = VCOSAI2 / 20"] + Div21: [21, "PLLSAI2CLK = VCOSAI2 / 21"] + Div22: [22, "PLLSAI2CLK = VCOSAI2 / 22"] + Div23: [23, "PLLSAI2CLK = VCOSAI2 / 23"] + Div24: [24, "PLLSAI2CLK = VCOSAI2 / 24"] + Div25: [25, "PLLSAI2CLK = VCOSAI2 / 25"] + Div26: [26, "PLLSAI2CLK = VCOSAI2 / 26"] + Div27: [27, "PLLSAI2CLK = VCOSAI2 / 27"] + Div28: [28, "PLLSAI2CLK = VCOSAI2 / 28"] + Div29: [29, "PLLSAI2CLK = VCOSAI2 / 29"] + Div30: [30, "PLLSAI2CLK = VCOSAI2 / 30"] + Div31: [31, "PLLSAI2CLK = VCOSAI2 / 31"] + PLLSAI2REN: + Disabled: [0, PLLLCDCLK output disable] + Enabled: [1, PLLLCDCLK output enabled] + PLLSAI2[RQ]: + Div2: [0, "PLLSAI2x = 2"] + Div4: [1, "PLLSAI2x = 4"] + Div6: [2, "PLLSAI2x = 6"] + Div8: [3, "PLLSAI2x = 8"] + PLLSAI2QEN: + Disabled: [0, PLLDSICLK output disable] + Enabled: [1, PLLDSICLK output enabled] + PLLSAI2P: + Div7: [0, "PLLSAI2P = 7"] + Div17: [1, "PLLSAI2P = 17"] + PLLSAI2PEN: + Disabled: [0, PLLSAI2CLK output disable] + Enabled: [1, PLLSAI2CLK output enabled] + PLLSAI2N: [8, 127] + PLLSAI2M: + Div1: [0, "PLLSAI2M = 1"] + Div2: [1, "PLLSAI2M = 2"] + Div3: [2, "PLLSAI2M = 3"] + Div4: [3, "PLLSAI2M = 4"] + Div5: [4, "PLLSAI2M = 5"] + Div6: [5, "PLLSAI2M = 6"] + Div7: [6, "PLLSAI2M = 7"] + Div8: [7, "PLLSAI2M = 8"] + Div9: [8, "PLLSAI2M = 9"] + Div10: [9, "PLLSAI2M = 11"] + Div11: [10, "PLLSAI2M = 12"] + Div12: [11, "PLLSAI2M = 13"] + Div13: [12, "PLLSAI2M = 13"] + Div14: [13, "PLLSAI2M = 14"] + Div15: [14, "PLLSAI2M = 15"] + Div16: [15, "PLLSAI2M = 16"] + +CIER: + HSI48RDYIE: + Disabled: [0, HSI48 ready interrupt disabled] + Enabled: [1, HSI48 ready interrupt enabled] + LSECSSIE: + Disabled: [0, Clock security interrupt caused by LSE clock failure disabled] + Enabled: [1, Clock security interrupt caused by LSE clock failure enabled] + PLLSAI2RDYIE: + Disabled: [0, PLLSAI2 lock interrupt disabled] + Enabled: [1, PLLSAI2 lock interrupt enabled] + PLLSAI1RDYIE: + Disabled: [0, PLLSAI1 lock interrupt disabled] + Enabled: [1, PLLSAI1 lock interrupt enabled] + PLLRDYIE: + Disabled: [0, PLL lock interrupt disabled] + Enabled: [1, PLL lock interrupt enabled] + HSERDYIE: + Disabled: [0, HSE ready interrupt disabled] + Enabled: [1, HSE ready interrupt enabled] + HSIRDYIE: + Disabled: [0, HSI16 ready interrupt disabled] + Enabled: [1, HSI16 ready interrupt enabled] + MSIRDYIE: + Disabled: [0, MSI ready interrupt disabled] + Enabled: [1, MSI ready interrupt enabled] + LSERDYIE: + Disabled: [0, LSE ready interrupt disabled] + Enabled: [1, LSE ready interrupt enabled] + LSIRDYIE: + Disabled: [0, LSI ready interrupt disabled] + Enabled: [1, LSI ready interrupt enabled] + +CIFR: + HSI48RDYF: + NoInterrupt: [0, No clock ready interrupt caused by the HSI48 oscillator] + Interrupt: [1, Clock ready interrupt caused by the HSI48 oscillator] + LSECSSF: + NoInterrupt: [0, No clock security interrupt caused by LSE clock failure] + Interrupt: [1, Clock security interrupt caused by LSE clock failure] + CSSF: + NoInterrupt: [0, No clock security interrupt caused by HSE clock failure] + Interrupt: [1, Clock security interrupt caused by HSE clock failure] + PLLSAI2RDYF: + NoInterrupt: [0, No clock ready interrupt caused by PLLSAI2 lock] + Interrupt: [1, Clock ready interrupt caused by PLLSAI2 lock] + PLLSAI1RDYF: + NoInterrupt: [0, No clock ready interrupt caused by PLLSAI1 lock] + Interrupt: [1, Clock ready interrupt caused by PLLSAI1 lock] + PLLRDYF: + NoInterrupt: [0, No clock ready interrupt caused by PLL lock] + Interrupt: [1, Clock ready interrupt caused by PLL lock] + HSERDYF: + NoInterrupt: [0, No clock ready interrupt caused by the HSE oscillator] + Interrupt: [1, Clock ready interrupt caused by the HSE oscillator] + HSIRDYF: + NoInterrupt: [0, No clock ready interrupt caused by the HSI16 oscillator] + Interrupt: [1, Clock ready interrupt caused by the HSI16 oscillator] + MSIRDYF: + NoInterrupt: [0, No clock ready interrupt caused by the MSI oscillator] + Interrupt: [1, Clock ready interrupt caused by the MSI oscillator] + LSERDYF: + NoInterrupt: [0, No clock ready interrupt caused by the LSE oscillator] + Interrupt: [1, Clock ready interrupt caused by the LSE oscillator] + LSIRDYF: + NoInterrupt: [0, No clock ready interrupt caused by the LSI oscillator] + Interrupt: [1, Clock ready interrupt caused by the LSI oscillator] + +CICR: + HSI48RDYC: + Clear: [1, Clear the HSI48RDYC flag] + LSECSSC: + Clear: [1, Clear the LSECSSF flag] + CSSC: + Clear: [1, Clear the CSSF flag] + PLLSAI2RDYC: + Clear: [1, Clear PLLSAI2RDYF flag] + PLLSAI1RDYC: + Clear: [1, Clear PLLSAI1RDYF flag] + PLLRDYC: + Clear: [1, Clear PLLRDYF flag] + HSERDYC: + Clear: [1, Clear HSERDYF flag] + HSIRDYC: + Clear: [1, Clear HSIRDYF flag] + MSIRDYC: + Clear: [1, Clear the MSIRDYF flag] + LSERDYC: + Clear: [1, Clear the LSERDYF flag] + LSIRDYC: + Clear: [1, Clear the LSIRDYF flag] + +AHB1RSTR: + GFXMMURST: + NoEffect: [0, No effect] + Reset: [1, Reset GFXMMU] + DMA2DRST: + NoEffect: [0, No effect] + Reset: [1, Reset DMA2D] + TSCRST: + NoEffect: [0, No effect] + Reset: [1, Reset TSC] + CRCRST: + NoEffect: [0, No effect] + Reset: [1, Reset CRC] + FLASHRST: + NoEffect: [0, No effect] + Reset: [1, Reset Flash memory interface] + DMAMUX1RST: + NoEffect: [0, No effect] + Reset: [1, Reset DMAMUX1] + DMA2RST: + NoEffect: [0, No effect] + Reset: [1, Reset DMA2] + DMA1RST: + NoEffect: [0, No effect] + Reset: [1, Reset DMA1] + +AHB2RSTR: + SDMMC2RST: + NoEffect: [0, No effect] + Reset: [1, Reset SDMMC2] + SDMMC1RST: + NoEffect: [0, No effect] + Reset: [1, Reset SDMMC1] + OSPIMRST: + NoEffect: [0, No effect] + Reset: [1, Reset OctoSPI IO manager] + RNGRST: + NoEffect: [0, No effect] + Reset: [1, Reset RNG] + HASHRST: + NoEffect: [0, No effect] + Reset: [1, Reset HASH] + AESRST: + NoEffect: [0, No effect] + Reset: [1, Reset AES] + PKARST: + NoEffect: [0, No effect] + Reset: [1, Reset PKA] + DCMIRST: + NoEffect: [0, No effect] + Reset: [1, Reset DCMI/PSSI interface] + ADCRST: + NoEffect: [0, No effect] + Reset: [1, Reset ADC] + OTGFSRST: + NoEffect: [0, No effect] + Reset: [1, Reset USB OTG FS] + GPIO?RST: + NoEffect: [0, No effect] + Reset: [1, Reset GPIO port x] + +AHB3RSTR: + OSPI?RST: + NoEffect: [0, No effect] + Reset: [1, Reset OctoSPIx] + FMCRST: + NoEffect: [0, No effect] + Reset: [1, Reset FMC] + +APB1RSTR1: + LPTIM1RST: + NoEffect: [0, No effect] + Reset: [1, Reset LPTIM1] + OPAMPRST: + NoEffect: [0, No effect] + Reset: [1, Reset OPAMP] + DAC1RST: + NoEffect: [0, No effect] + Reset: [1, Reset DAC1] + PWRRST: + NoEffect: [0, No effect] + Reset: [1, Reset PWR] + CAN1RST: + NoEffect: [0, No effect] + Reset: [1, Reset CAN1] + CRSRST: + NoEffect: [0, No effect] + Reset: [1, Reset CRS] + I2C?RST: + NoEffect: [0, No effect] + Reset: [1, Reset I2Cx] + USART?RST: + NoEffect: [0, No effect] + Reset: [1, Reset UARTx] + SPI?RST: + NoEffect: [0, No effect] + Reset: [1, Reset SPIx] + TIM?RST: + NoEffect: [0, No effect] + Reset: [1, Reset TIMx] + +APB1RSTR2: + LPTIM2RST: + NoEffect: [0, No effect] + Reset: [1, Reset LPTIM2] + I2C4RST: + NoEffect: [0, No effect] + Reset: [1, Reset I2C4] + LPUART1RST: + NoEffect: [0, No effect] + Reset: [1, Reset LPUART1] + +APB2RSTR: + DSIRST: + NoEffect: [0, No effect] + Reset: [1, Reset DSI] + LTDCRST: + NoEffect: [0, No effect] + Reset: [1, Reset LCD-TFT] + DFSDM1RST: + NoEffect: [0, No effect] + Reset: [1, Reset DFSDM1] + SAI?RST: + NoEffect: [0, No effect] + Reset: [1, Reset SAIx] + TIM*RST: + NoEffect: [0, No effect] + Reset: [1, Reset TIMx] + USART?RST: + NoEffect: [0, No effect] + Reset: [1, Reset UARTx] + SPI1RST: + NoEffect: [0, No effect] + Reset: [1, Reset SPI1] + SYSCFGRST: + NoEffect: [0, No effect] + Reset: [1, "Reset SYSCFG + COMP + VREFBUF"] + +AHB1ENR: + GFXMMUEN: + Disabled: [0, GFXMMU clock disabled] + Enabled: [1, GFXMMU clock enabled] + DMA2DEN: + Disabled: [0, DMA2D clock disabled] + Enabled: [1, DMA2D clock enabled] + TSCEN: + Disabled: [0, TSC clock disabled] + Enabled: [1, TSC clock enabled] + CRCEN: + Disabled: [0, CRC clock disabled] + Enabled: [1, CRC clock enabled] + FLASHEN: + Disabled: [0, Flash memory interface clock disabled] + Enabled: [1, Flash memory interface clock enabled] + DMAMUX1EN: + Disabled: [0, DMAMUX1 clock disabled] + Enabled: [1, DMAMUX1 clock enabled] + DMA?EN: + Disabled: [0, DMAx clock disabled] + Enabled: [1, DMAx clock enabled] + +AHB2ENR: + SDMMC?EN: + Disabled: [0, SDMMCx clock disabled] + Enabled: [1, SDMMCx clock enabled] + OSPIMEN: + Disabled: [0, OctoSPI IO manager clock disabled] + Enabled: [1, OctoSPI IO manager clock enabled] + ADCEN: + Disabled: [0, ADC clock disabled] + Enabled: [1, ADC clock enabled] + RNGEN: + Disabled: [0, Random Number Generator clock disabled] + Enabled: [1, Random Number Generator clock enabled] + HASHEN: + Disabled: [0, HASH clock disabled] + Enabled: [1, HASH clock enabled] + AESEN: + Disabled: [0, AES clock disabled] + Enabled: [1, AES clock enabled] + PKAEN: + Disabled: [0, PKA clock disabled] + Enabled: [1, PKA clock enabled] + DCMIEN: + Disabled: [0, DCMI/PSSI clock disabled] + Enabled: [1, DCMI/PSSI clock enabled] + OTGFSEN: + Disabled: [0, USB OTG full speed clock disabled] + Enabled: [1, USB OTG full speed clock enabled] + GPIO?EN: + Disabled: [0, IO port x clock disabled] + Enabled: [1, IO port x clock enabled] + +AHB3ENR: + OSPI?EN: + Disabled: [0, OctoSPI x clock disabled] + Enabled: [1, OctoSPI x clock enabled] + FMCEN: + Disabled: [0, FMC clock disabled] + Enabled: [1, FMC clock enabled] + +APB1ENR1: + OPAMPEN: + Disabled: [0, OPAMP clock disabled] + Enabled: [1, OPAMP clock enabled] + DAC1EN: + Disabled: [0, DAC1 clock disabled] + Enabled: [1, DAC1 clock enabled] + PWREN: + Disabled: [0, Power interface clock disabled] + Enabled: [1, Power interface clock enabled] + CAN1EN: + Disabled: [0, CAN1 clock disabled] + Enabled: [1, CAN1 clock enabled] + CRSEN: + Disabled: [0, CRS clock disabled] + Enabled: [1, CRS clock enabled] + UART?EN: + Disabled: [0, UARTx clock disabled] + Enabled: [1, UARTx clock enabled] + USART?EN: + Disabled: [0, USARTx clock disabled] + Enabled: [1, USARTx clock enabled] + SPI?EN: + Disabled: [0, SPIx clock disabled] + Enabled: [1, SPIx clock enabled] + WWDGEN: + Disabled: [0, Window watchdog clock disabled] + Enabled: [1, Window watchdog clock enabled] + RTCAPBEN: + Disabled: [0, RTC APB clock disabled] + Enabled: [1, RTC APB clock enabled] + TIM?EN: + Disabled: [0, TIMx clock disabled] + Enabled: [1, TIMx clock enabled] + LPTIM1EN: + Disabled: [0, LPTIM1 clock disabled] + Enabled: [1, LPTIM1 clock enabled] + I2C3EN: + Disabled: [0, I2C3 clock disabled] + Enabled: [1, I2C3 clock enabled] + I2C2EN: + Disabled: [0, I2C2 clock disabled] + Enabled: [1, I2C2 clock enabled] + I2C1EN: + Disabled: [0, I2C1 clock disabled] + Enabled: [1, I2C1 clock enabled] + +APB1ENR2: + I2C4EN: + Disabled: [0, I2C4 clock disabled] + Enabled: [1, I2C4 clock enabled] + LPTIM2EN: + Disabled: [0, LPTIM2 clock disabled] + Enabled: [1, LPTIM2 clock enabled] + LPUART1EN: + Disabled: [0, LPUART1 clock disabled] + Enabled: [1, LPUART1 clock enabled] + +APB2ENR: + USART1EN: + Disabled: [0, USART1 clock disabled] + Enabled: [1, USART1 clock enabled] + DSIEN: + Disabled: [0, DSI clock disabled] + Enabled: [1, DSI clock enabled] + LTDCEN: + Disabled: [0, LTDC clock disabled] + Enabled: [1, LTDC clock enabled] + DFSDM1EN: + Disabled: [0, DFSDM1 clock disabled] + Enabled: [1, DFSDM1 clock enabled] + SAI?EN: + Disabled: [0, SAIx clock disabled] + Enabled: [1, SAIx clock enabled] + TIM*EN: + Disabled: [0, TIMx clock disabled] + Enabled: [1, TIMx clock enabled] + SPI1EN: + Disabled: [0, SPI1 clock disabled] + Enabled: [1, SPI1 clock enabled] + FWEN: + Disabled: [0, Firewall clock disabled] + Enabled: [1, Firewall clock enabled] + SYSCFGEN: + Disabled: [0, "SYSCFG + COMP + VREFBUF clock disabled"] + Enabled: [1, "SYSCFG + COMP + VREFBUF clock enabled"] + +AHB1SMENR: + GFXMMUSMEN: + Disabled: [0, GFXMMU clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, GFXMMU clocks enabled by the clock gating(1) during Sleep and Stop modes] + DMA2DSMEN: + Disabled: [0, DMA2D clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, DMA2D clocks enabled by the clock gating(1) during Sleep and Stop modes] + TSCSMEN: + Disabled: [0, TSC clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, TSC clocks enabled by the clock gating(1) during Sleep and Stop modes] + CRCSMEN: + Disabled: [0, CRC clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, CRC clocks enabled by the clock gating(1) during Sleep and Stop modes] + SRAM1SMEN: + Disabled: [0, SRAM1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, SRAM1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + FLASHSMEN: + Disabled: [0, Flash memory interface clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, Flash memory interface clocks enabled by the clock gating(1) during Sleep and Stop modes] + DMAMUX1SMEN: + Disabled: [0, DMAMUX1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, DMAMUX1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + DMA?SMEN: + Disabled: [0, DMAx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, DMAx clocks enabled by the clock gating(1) during Sleep and Stop modes] + +AHB2SMENR: + SDMMC?SMEN: + Disabled: [0, SDMMCx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, SDMMCx clocks enabled by the clock gating(1) during Sleep and Stop modes] + OSPIMSMEN: + Disabled: [0, OCTOSPIM clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, OCTOSPIM clocks enabled by the clock gating(1) during Sleep and Stop modes] + RNGSMEN: + Disabled: [0, Random Number Generator clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, Random Number Generator clocks enabled by the clock gating(1) during Sleep and Stop modes] + HASHSMEN: + Disabled: [0, HASH clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, HASH clocks enabled by the clock gating(1) during Sleep and Stop modes] + AESSMEN: + Disabled: [0, AES clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, AES clocks enabled by the clock gating(1) during Sleep and Stop modes] + PKASMEN: + Disabled: [0, PKA clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, PKA clocks enabled by the clock gating(1) during Sleep and Stop modes] + DCMISMEN: + Disabled: [0, DCMI/PSSI clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, DCMI/PSSI clocks enabled by the clock gating(1) during Sleep and Stop modes] + ADCSMEN: + Disabled: [0, ADC clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, ADC clocks enabled by the clock gating(1) during Sleep and Stop modes] + OTGFSSMEN: + Disabled: [0, USB OTG full speed clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, USB OTG full speed clocks enabled by the clock gating(1) during Sleep and Stop modes] + SRAM?SMEN: + Disabled: [0, SRAMx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, SRAMx clocks enabled by the clock gating(1) during Sleep and Stop modes] + GPIO?SMEN: + Disabled: [0, IO port x clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, IO port x clocks enabled by the clock gating(1) during Sleep and Stop modes] + +AHB3SMENR: + OCTOSPI2: + Disabled: [0, OctoSPI2 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, OctoSPI2 clocks enabled by the clock gating(1) during Sleep and Stop modes] + OSPI1SMEN: + Disabled: [0, OctoSPI1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, OctoSPI1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + FMCSMEN: + Disabled: [0, FMC clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, FMC clocks enabled by the clock gating(1) during Sleep and Stop modes] + +APB1SMENR1: + LPTIM1SMEN: + Disabled: [0, LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, LPTIM1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + OPAMPSMEN: + Disabled: [0, OPAMP interface clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, OPAMP interface clocks enabled by the clock gating(1) during Sleep and Stop modes] + DAC1SMEN: + Disabled: [0, DAC1 interface clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, DAC1 interface clocks enabled by the clock gating(1) during Sleep and Stop modes] + PWRSMEN: + Disabled: [0, Power interface clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, Power interface clocks enabled by the clock gating(1) during Sleep and Stop modes] + CAN1SMEN: + Disabled: [0, CAN1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, CAN1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + CRSSMEN: + Disabled: [0, CRS clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, CRS clocks enabled by the clock gating(1) during Sleep and Stop modes] + I2C?SMEN: + Disabled: [0, I2Cx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, I2Cx clocks enabled by the clock gating(1) during Sleep and Stop modes] + UART?SMEN: + Disabled: [0, UARTx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, UARTx clocks enabled by the clock gating(1) during Sleep and Stop modes] + USART?SMEN: + Disabled: [0, USARTx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, USARTx clocks enabled by the clock gating(1) during Sleep and Stop modes] + SPI?SMEN: + Disabled: [0, SPIx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, SPIx clocks enabled by the clock gating(1) during Sleep and Stop modes] + WWDGSMEN: + Disabled: [0, Window watchdog clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, Window watchdog clocks enabled by the clock gating(1) during Sleep and Stop modes] + RTCAPBSMEN: + Disabled: [0, RTC APB clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, RTC APB clocks enabled by the clock gating(1) during Sleep and Stop modes] + TIM?SMEN: + Disabled: [0, TIMx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, TIMx clocks enabled by the clock gating(1) during Sleep and Stop modes] + +APB1SMENR2: + LPTIM2SMEN: + Disabled: [0, LPTIM2 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, LPTIM2 clocks enabled by the clock gating(1) during Sleep and Stop modes] + I2C4SMEN: + Disabled: [0, I2C4 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, I2C4 clocks enabled by the clock gating(1) during Sleep and Stop modes] + LPUART1SMEN: + Disabled: [0, LPUART1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, LPUART1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + +APB2SMENR: + DSISMEN: + Disabled: [0, DSI clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, DSI clocks enabled by the clock gating(1) during Sleep and Stop modes] + LTDCSMEN: + Disabled: [0, LCD-TFT clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, LCD-TFT clocks enabled by the clock gating(1) during Sleep and Stop modes] + DFSDM1SMEN: + Disabled: [0, DFSDM1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, DFSDM1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + SAI?SMEN: + Disabled: [0, SAIx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, SAIx clocks enabled by the clock gating(1) during Sleep and Stop modes] + TIM*SMEN: + Disabled: [0, TIMx clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, TIMx clocks enabled by the clock gating(1) during Sleep and Stop modes] + USART1SMEN: + Disabled: [0, USART1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, USART1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + SPI1SMEN: + Disabled: [0, SPI1 clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, SPI1 clocks enabled by the clock gating(1) during Sleep and Stop modes] + SYSCFGSMEN: + Disabled: [0, "SYSCFG + COMP + VREFBUF clocks disabled by the clock gating during Sleep and Stop modes"] + Enabled: [1, "SYSCFG + COMP + VREFBUF clocks enabled by the clock gating(1) during Sleep and Stop modes"] + +CCIPR: + ADCSEL: + NoClock: [0, No clock selected] + PLLADC1CLK: [1, PLLADC1CLK clock selected] + SYSCLK: [3, SYSCLK clock selected] + CLK48SEL: + HSI48: + [ + 0, + "HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)", + ] + PLL48M2CLK: [1, PLL48M2CLK clock selected] + PLL48M1CLK: [2, PLL48M1CLK clock selected] + MSI: [3, MSI clock selected] + "LPTIM[12]SEL": + PCLK: [0, PCLK clock selected] + LSI: [1, LSI clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + "I2C[123]SEL": + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LPUART1SEL: + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + "UART[45]SEL": + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + "USART[123]SEL": + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + +BDCR: + LSCOSEL: + LSI: [0, LSI clock selected] + LSE: [1, LSE clock selected] + LSCOEN: + Disabled: [0, Low speed clock output (LSCO) disabled] + Enabled: [1, Low speed clock output (LSCO) enabled] + BDRST: + NoReset: [0, Reset not activated] + Reset: [1, Reset the entire Backup domain] + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock selected] + LSI: [2, LSI oscillator clock selected] + HSE: [3, HSE oscillator clock divided by 32 selected] + LSESYSDIS: + Disabled: [0, No clock LSE propagation] + Enabled: [1, Clock LSE propagation enabled] + LSECSSD: + NoFailure: [0, " No failure detected on LSE (32 kHz oscillator)"] + FailureDetected: [1, Failure detected on LSE (32 kHz oscillator)] + LSECSSON: + Disabled: [0, CSS on LSE (32 kHz external oscillator) OFF] + Enabled: [1, CSS on LSE (32 kHz external oscillator) ON] + LSEDRV: + Low: [0, "‘Xtal mode’ lower driving capability"] + MediumLow: [1, "‘Xtal mode’ medium low driving capability"] + MediumHigh: [2, "‘Xtal mode’ medium high driving capability"] + High: [3, "‘Xtal mode’ higher driving capability"] + LSEBYP: + NotBypassed: [0, LSE oscillator not bypassed] + Bypassed: [1, LSE oscillator bypassed] + LSERDY: + NotReady: [0, LSE oscillator not ready] + Ready: [1, LSE oscillator ready] + LSEON: + Disabled: [0, LSE oscillator OFF] + Enabled: [1, LSE oscillator ON] + +CSR: + LPWRRSTF: + NotOccured: [0, No illegal mode reset occurred] + Occured: [1, Illegal mode reset occurred] + WWDGRSTF: + NotOccured: [0, No window watchdog reset occurred] + Occured: [1, Window watchdog reset occurred] + IWDGRSTF: + NotOccured: [0, No independent watchdog reset occurred] + Occured: [1, Independent watchdog reset occurred] + SFTRSTF: + NotOccured: [0, No software reset occurred] + Occured: [1, Software reset occurred] + BORRSTF: + NotOccured: [0, No BOR occurred] + Occured: [1, BOR occurred] + PINRSTF: + NotOccured: [0, No reset from NRST pin occurred] + Occured: [1, Reset from NRST pin occurred] + OBLRSTF: + NotOccured: [0, No reset from Option Byte loading occurred] + Occured: [1, Reset from Option Byte loading occurred] + FWRSTF: + NotOccured: [0, No reset from the firewall occurred] + Occured: [1, Reset from the firewall occurred] + RMVF: + NoEffect: [0, No effect] + Clear: [1, Clear the reset flags] + MSISRANGE: + Range1M: [0b0100, range 4 around 1 MHz] + Range2M: [0b0101, range 5 around 2 MHz] + Range4M: [0b0110, range 6 around 4 MHz] + Range8M: [0b0111, range 7 around 8 MHz] + LSIPREDIV: + Disabled: [0, LSI PREDIV OFF] + Enabled: [1, LSI PREDIV ON] + LSIRDY: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSION: + Disabled: [0, LSI oscillator OFF] + Enabled: [1, LSI oscillator ON] + +CRRCR: + HSI48CAL: [0, 0x1FF] + HSI48RDY: + NotReady: [0, HSI48 oscillator not ready] + Ready: [1, HSI48 oscillator ready] + HSI48ON: + Disabled: [0, HSI48 oscillator OFF] + Enabled: [1, HSI48 oscillator ON] + +CCIPR2: + OSPISEL: + SYSCLK: [0, System clock selected as OctoSPI kernel clock] + MSI: [1, MSI clock selected as OctoSPI kernel clock] + PLL48M1CLK: [2, PLL48M1CLK clock selected as OctoSPI kernel clock] + PLLSAI2DIVR: + Div2: [0, "PLLSAI2DIVR = /2"] + Div4: [1, "PLLSAI2DIVR = /4"] + Div8: [2, "PLLSAI2DIVR = /8"] + Div16: [3, "PLLSAI2DIVR = /16"] + SDMMCSEL: + HSI48: [0, 48 MHz clock is selected as SDMMC kernel clock] + PLLSAI3CLK: + [ + 1, + "PLLSAI3CLK is selected as SDMMC kernel clock, used in case higher frequency than 48MHz is needed (for SDR50 mode)", + ] + DSISEL: + DSIPHY: [0, DSI-PHY is selected as DSI byte lane clock source (usual case)] + PLLDSICLK: + [ + 1, + "PLLDSICLK is selected as DSI byte lane clock source, used in case DSI PLL and DSIPHY are off (low-power mode)", + ] + SAI?SEL: + PLLSAI1CLK: [0, PLLSAI1CLK clock is selected as SAIx clock] + PLLSAI2CLK: [1, PLLSAI2CLK clock is selected as SAIx clock] + PLLSAI3CLK: [2, PLLSAI3CLK clock is selected as SAIx clock] + SAI2_EXTCLK: [3, " External clock SAIx_EXTCLK clock selected as SAIx clock"] + HSI: [4, HSI clock selected as SAIx clock] + ADFSDMSEL: + SAI1: [0, SAI1clock selected as DFSDM audio clock] + HSI: [1, HSI clock selected as DFSDM audio clock] + MSI: [2, MSI clock selected as DFSDM audio clock] + DFSDMSEL: + PCLK2: [0, APB2 clock (PCLK2) selected as DFSDM kernel clock] + SYSCLK: [1, System clock selected as DFSDM kernel clock] + I2C4SEL: + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + +DLYCFGR: + OCTOSPI2_DLY: [0, 0xF] + OCTOSPI1_DLY: [0, 0xF] diff --git a/devices/fields/rcc/rcc_l4.yaml b/devices/fields/rcc/rcc_l4.yaml new file mode 100644 index 000000000..d4e171d43 --- /dev/null +++ b/devices/fields/rcc/rcc_l4.yaml @@ -0,0 +1,91 @@ +AHB2ENR: + ADCEN: + Disabled: [0, ADC clock disabled] + Enabled: [1, ADC clock enabled] + +APB2ENR: + USART1EN: + Disabled: [0, USART1 clock disabled] + Enabled: [1, USART1 clock enabled] + +APB1ENR1: + LPTIM1EN: + Disabled: [0, LPTIM1 clock disabled] + Enabled: [1, LPTIM1 clock enabled] + I2C3EN: + Disabled: [0, I2C3 clock disabled] + Enabled: [1, I2C3 clock enabled] + I2C2EN: + Disabled: [0, I2C2 clock disabled] + Enabled: [1, I2C2 clock enabled] + I2C1EN: + Disabled: [0, I2C1 clock disabled] + Enabled: [1, I2C1 clock enabled] + +APB1ENR2: + LPTIM2EN: + Disabled: [0, LPTIM2 clock disabled] + Enabled: [1, LPTIM2 clock enabled] + LPUART1EN: + Disabled: [0, LPUART1 clock disabled] + Enabled: [1, LPUART1 clock enabled] + +CR: + MSIRANGE: + Range100K: [0b0000, range 0 around 100 kHz] + Range200K: [0b0001, range 1 around 200 kHz] + Range400K: [0b0010, range 2 around 400 kHz] + Range800K: [0b0011, range 3 around 800 kHz] + Range1M: [0b0100, range 4 around 1 MHz] + Range2M: [0b0101, range 5 around 2 MHz] + Range4M: [0b0110, range 6 around 4 MHz] + Range8M: [0b0111, range 7 around 8 MHz] + Range16M: [0b1000, range 8 around 16 MHz] + Range24M: [0b1001, range 9 around 24 MHz] + Range32M: [0b1010, range 10 around 32 MHz] + Range48M: [0b1011, range 11 around 48 MHz] + +CCIPR: + ADCSEL: + NoClock: [0, No clock selected] + PLLSAI1: [1, PLLSAI1 clock selected] + PLLSAI2: [2, PLLSAI2 clock selected (only for STM32L47x/L48x/L49x/L4Ax devices)] + SYSCLK: [3, SYSCLK clock selected] + CLK48SEL: + HSI48: + [ + 0, + "HSI48 clock selected (only for STM32L41x/L42x/L43x/L44x/L45x/L46x/L49x/L4Ax devices, otherwise no clock selected)", + ] + PLLSAI1: [1, PLLSAI1 clock selected] + PLL: [2, PLL clock selected] + MSI: [3, MSI clock selected] + "LPTIM[123]SEL": + PCLK: [0, PCLK clock selected] + LSI: [1, LSI clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + "I2C[123]SEL": + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LPUART1SEL: + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + "USART[12345]SEL": + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + +BDCR: + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock selected] + LSI: [2, LSI oscillator clock selected] + HSE: [3, HSE oscillator clock divided by 32 selected] diff --git a/devices/fields/rcc/rcc_l4_uart4.yaml b/devices/fields/rcc/rcc_l4_uart4.yaml new file mode 100644 index 000000000..9c742e206 --- /dev/null +++ b/devices/fields/rcc/rcc_l4_uart4.yaml @@ -0,0 +1,4 @@ +APB1ENR1: + UART4EN: + Disabled: [0, UART4 clock disabled] + Enabled: [1, UART4 clock enabled] diff --git a/devices/fields/rcc/rcc_l4_uart5.yaml b/devices/fields/rcc/rcc_l4_uart5.yaml new file mode 100644 index 000000000..da79b510a --- /dev/null +++ b/devices/fields/rcc/rcc_l4_uart5.yaml @@ -0,0 +1,4 @@ +APB1ENR1: + UART5EN: + Disabled: [0, UART5 clock disabled] + Enabled: [1, UART5 clock enabled] diff --git a/devices/fields/rcc/rcc_l4_usart2_3.yaml b/devices/fields/rcc/rcc_l4_usart2_3.yaml new file mode 100644 index 000000000..110a309eb --- /dev/null +++ b/devices/fields/rcc/rcc_l4_usart2_3.yaml @@ -0,0 +1,7 @@ +APB1ENR1: + USART3EN: + Disabled: [0, USART3 clock disabled] + Enabled: [1, USART3 clock enabled] + USART2EN: + Disabled: [0, USART2 clock disabled] + Enabled: [1, USART2 clock enabled] diff --git a/devices/fields/rcc/rcc_l5.yaml b/devices/fields/rcc/rcc_l5.yaml new file mode 100644 index 000000000..5cd37a1f9 --- /dev/null +++ b/devices/fields/rcc/rcc_l5.yaml @@ -0,0 +1,136 @@ +# RCC peripheral +# Applicable to STM32L5 + +# This is derived from rcc_common.yaml. rcc_common.yaml +# does not cleanly apply to STM32L5 + +CR: + CSSON: + "Off": [0, Clock security system disabled (clock detector OFF)] + "On": [1, "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] + HSEBYP: + NotBypassed: [0, HSE crystal oscillator not bypassed] + Bypassed: [1, HSE crystal oscillator bypassed with external clock] + "*RDY": + _read: + NotReady: [0, Clock not ready] + Ready: [1, Clock ready] + HSION,HSEON,PLLON,PLLI2SON,PLLSAION: + "Off": [0, Clock Off] + "On": [1, Clock On] +CFGR: + MCOPRE: + Div1: [0, MCO divided by 1] + Div2: [1, MCO divided by 2] + Div4: [2, MCO divided by 4] + Div8: [3, MCO divided by 8] + Div16: [4, MCO divided by 16] + MCOSEL: + None: [0, "MCO output disabled, no clock on MCO"] + SYSCLK: [1, SYSCLK system clock selected] + MSI: [2, MSI clock selected] + HSI: [3, HSI clock selected] + HSE: [4, HSE clock selected] + PLL: [5, Main PLL clock selected] + LSI: [6, LSI clock selected] + LSE: [7, LSE clock selected] + HSI48: [8, Internal HSI48 clock selected] + STOPWUCK: + MSI: [0, MSI oscillator selected as wakeup from stop clock and CSS backup clock] + HSI: [1, HSI oscillator selected as wakeup from stop clock and CSS backup clock] + PPRE*: + Div1: [-1, HCLK not divided] + Div2: [4, HCLK divided by 2] + Div4: [5, HCLK divided by 4] + Div8: [6, HCLK divided by 8] + Div16: [7, HCLK divided by 16] + HPRE: + Div1: [-1, SYSCLK not divided] + Div2: [8, SYSCLK divided by 2] + Div4: [9, SYSCLK divided by 4] + Div8: [10, SYSCLK divided by 8] + Div16: [11, SYSCLK divided by 16] + Div64: [12, SYSCLK divided by 64] + Div128: [13, SYSCLK divided by 128] + Div256: [14, SYSCLK divided by 256] + Div512: [15, SYSCLK divided by 512] + SWS: + _read: + MSI: [0, MSI oscillator used as system clock] + HSI: [1, HSI oscillator used as system clock] + HSE: [2, HSE used as system clock] + PLL: [3, PLL used as system clock] + SW: + MSI: [0, MSI selected as system clock] + HSI: [1, HSI selected as system clock] + HSE: [2, HSE selected as system clock] + PLL: [3, PLL selected as system clock] +"A?B?RSTR,A?BRSTR,A?B?RSTR?,A?BRSTR?": + "*RST": + Reset: [1, Reset the selected module] +"A?B?ENR,A?BENR,A?B?ENR?,A?BENR?": + "*EN": + Disabled: [0, The selected clock is disabled] + Enabled: [1, The selected clock is enabled] +BDCR: + LSCOSEL: + LSI: [0, LSI clock selected"] + LSE: [1, LSE clock selected] + LSCOEN: + Disabled: [0, LSCO disabled] + Enabled: [1, LSCO enabled] + BDRST: + Disabled: [0, Reset not activated] + Enabled: [1, Reset the entire RTC domain] + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + LSESYSRDY: + _read: + NotReady: [0, LSESYS clock not ready] + Ready: [1, LSESYS clock ready] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock used as RTC clock] + LSI: [2, LSI oscillator clock used as RTC clock] + HSE: [3, HSE oscillator clock divided by a prescaler used as RTC clock] + LSESYSEN: + Disabled: [0, LSESYS only enabled when requested by a peripheral or system function] + Enabled: [1, LSESYS enabled always generated by RCC] + LSECSSD: + _read: + NoFailure: [0, No failure detected on LSE (32 kHz oscillator)] + Failure: [1, Failure detected on LSE (32 kHz oscillator)] + LSECSSON: + "Off": [0, CSS on LSE (32 kHz external oscillator) OFF] + "On": [1, CSS on LSE (32 kHz external oscillator) ON] + LSEDRV: + Lower: [0, "'Xtal mode' lower driving capability"] + MediumLow: [1, "'Xtal mode' medium low driving capability"] + MediumHigh: [2, "'Xtal mode' medium high driving capability"] + Higher: [3, "'Xtal mode' higher driving capability"] + LSEBYP: + NotBypassed: [0, LSE crystal oscillator not bypassed] + Bypassed: [1, LSE crystal oscillator bypassed with external clock] + LSERDY: + _read: + NotReady: [0, LSE oscillator not ready] + Ready: [1, LSE oscillator ready] + LSEON: + "Off": [0, LSE oscillator Off] + "On": [1, LSE oscillator On] +CSR: + "*RSTF": + _read: + NoReset: [0, No reset has occured] + Reset: [1, A reset has occured] + RMVF: + _write: + Clear: [1, Clears the reset flag] + LSIRDY: + _read: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSION: + "Off": [0, LSI oscillator Off] + "On": [1, LSI oscillator On] diff --git a/devices/fields/rcc/rcc_pllsrc_1bit.yaml b/devices/fields/rcc/rcc_pllsrc_1bit.yaml new file mode 100644 index 000000000..391f64282 --- /dev/null +++ b/devices/fields/rcc/rcc_pllsrc_1bit.yaml @@ -0,0 +1,4 @@ +CFGR: + PLLSRC: + HSI_Div2: [0, HSI divided by 2 selected as PLL input clock] + HSE_Div_PREDIV: [1, HSE divided by PREDIV selected as PLL input clock] diff --git a/devices/fields/rcc/rcc_pllsrc_2bit.yaml b/devices/fields/rcc/rcc_pllsrc_2bit.yaml new file mode 100644 index 000000000..c1bc84451 --- /dev/null +++ b/devices/fields/rcc/rcc_pllsrc_2bit.yaml @@ -0,0 +1,5 @@ +CFGR: + PLLSRC: + HSI_Div2: [0, HSI divided by 2 selected as PLL input clock] + HSI_Div_PREDIV: [1, HSI divided by PREDIV selected as PLL input clock] + HSE_Div_PREDIV: [2, HSE divided by PREDIV selected as PLL input clock] diff --git a/devices/fields/rcc/rcc_u5.yaml b/devices/fields/rcc/rcc_u5.yaml new file mode 100644 index 000000000..2e11dbf4a --- /dev/null +++ b/devices/fields/rcc/rcc_u5.yaml @@ -0,0 +1,742 @@ +# RCC peripheral +# Applicable to STM32U5 + +CR: + PLL3RDY: + _read: + Unlocked: [0, PLL3 unlocked] + Locked: [1, PLL3 locked] + PLL3ON: + Disabled: [0, PLL3 OFF] + Enabled: [1, PLL3 ON] + PLL2RDY: + _read: + Unlocked: [0, PLL2 unlocked] + Locked: [1, PLL2 locked] + PLL2ON: + Disabled: [0, PLL2 OFF] + Enabled: [1, PLL2 ON] + PLL1RDY: + _read: + Unlocked: [0, PLL1 unlocked] + Locked: [1, PLL1 locked] + PLL1ON: + Disabled: [0, PLL1 OFF] + Enabled: [1, PLL1 ON] + HSEEXT: + Analog: [0, external HSE clock analog mode] + Digital: [1, external HSE clock digital mode (through I/O Schmitt trigger)] + CSSON: + Disabled: [0, Clock security system OFF (clock detector OFF)] + Enabled: [1, "Clock security system ON (Clock detector ON if the HSE oscillator is stable, OFF if not)"] + HSEBYP: + NotBypassed: [0, HSE crystal oscillator not bypassed] + Bypassed: [1, HSE crystal oscillator bypassed with external clock] + HSERDY: + _read: + NotReady: [0, HSE oscillator not ready] + Ready: [1, HSE oscillator ready] + HSEON: + Disabled: [0, HSE oscillator off] + Enabled: [1, HSE oscillator on] + SHSIRDY: + _read: + NotReady: [0, SHSI oscillator not ready] + Ready: [1, SHSI oscillator ready] + SHSION: + Disabled: [0, SHSI oscillator off] + Enabled: [1, SHSI oscillator on] + HSI48RDY: + _read: + NotReady: [0, HSI48 oscillator not ready] + Ready: [1, HSI48 oscillator ready] + HSI48ON: + Disabled: [0, HSI48 oscillator off] + Enabled: [1, HSI48 oscillator on] + HSIRDY: + _read: + NotReady: [0, HSI16 oscillator not ready] + Ready: [1, HSI16 oscillator ready] + HSIKERON: + NotForced: [0, No effect on HSI16 oscillator] + Forced: [1, HSI16 oscillator forced on even in Stop mode] + HSION: + Disabled: [0, HSI16 oscillator off] + Enabled: [1, HSI16 oscillator on] + MSIPLLFAST: + Normal: [0, MSI PLL normal start-up] + Fast: [1, MSI PLL fast start-up] + MSIPLLSEL: + MSIK: [0, PLL mode applied to MSIK (MSI kernel) clock output] + MSIS: [1, PLL mode applied to MSIS (MSI system) clock output] + MSIKRDY: + _read: + NotReady: [0, MSIK (MSI kernel) oscillator not ready] + Ready: [1, MSIK (MSI kernel) oscillator ready] + MSIKON: + Disabled: [0, MSIK (MSI kernel) oscillator disabled] + Enabled: [1, MSIK (MSI kernel) oscillator enabled] + MSIPLLEN: + Disabled: [0, MSI PLL-mode OFF] + Enabled: [1, MSI PLL-mode ON] + MSISRDY: + _read: + NotReady: [0, MSIS (MSI system) oscillator not ready] + Ready: [1, MSIS (MSI system) oscillator ready] + MSIKERON: + NotForced: [0, No effect on MSI oscillator] + Forced: [1, MSI oscillator forced ON even in Stop mode] + MSISON: + Disabled: [0, MSIS (MSI system) oscillator off] + Enabled: [1, MSIS (MSI system) oscillator on] +ICSCR1: + MSI?RANGE: + f_48MHz: [0, Range 0 around 48 MHz] + f_24MHz: [1, Range 1 around 24 MHz] + f_16MHz: [2, Range 2 around 16 MHz] + f_12MHz: [3, Range 3 around 12 MHz] + f_4MHz: [4, Range 4 around 4 MHz] + f_2MHz: [5, Range 5 around 2 MHz] + f_1_333MHz: [6, Range 6 around 1.33 MHz] + f_1MHz: [7, Range 7 around 1 MHz] + f_3_072MHz: [8, Range 8 around 3.072 MHz] + f_1_536MHz: [9, Range 9 around 1.536 MHz] + f_1_024MHz: [10, Range 10 around 1.024 MHz] + f_768kHz: [11, Range 11 around 768 kHz] + f_400kHz: [12, Range 12 around 400 kHz] + f_200kHz: [13, Range 13 around 200 kHz] + f_133kHz: [14, Range 14 around 133 kHz] + f_100kHz: [15, Range 15 around 100 kHz] + MSIRGSEL: + CSR: [0, "MSIS/MSIK ranges provided by MSISSRANGE[3:0] and MSIKSRANGE[3:0] in RCC_CSR"] + ICSCR1: [1, "MSIS/MSIK ranges provided by MSISRANGE[3:0] and MSIKRANGE[3:0] in RCC_ICSCR1"] + MSIBIAS: + Continuous: [0, MSI bias continuous mode (clock accuracy fast settling time)] + Sampling: + [ + 1, + "MSI bias sampling mode when the regulator is in range 4, or when the device is in Stop 1 or Stop 2 (ultra-low-power mode)", + ] + MSICAL?: [0, 0x1F] +ICSCR2: + MSITRIM?: [0, 0x1F] +ICSCR3: + HSITRIM: [0, 0x1F] + HSICAL: [0, 0xFFF] +CRRCR: + HSI48CAL: [0, 0x1FF] +CFGR1: + MCOPRE: + Div1: [0, MCO divided by 1] + Div2: [1, MCO divided by 2] + Div4: [2, MCO divided by 4] + Div8: [3, MCO divided by 8] + Div16: [4, MCO divided by 16] + MCOSEL: + None: [0, "MCO output disabled, no clock on MCO"] + SYSCLK: [1, SYSCLK system clock selected] + MSIS: [2, MSIS clock selected] + HSI16: [3, HSI16 clock selected] + HSE: [4, HSE clock selected] + PLL: [5, Main PLL clock pll1_r_ck selected] + LSI: [6, LSI clock selected] + LSE: [7, LSE clock selected] + HSI48: [8, Internal HSI48 clock selected] + MSIK: [9, MSIK clock selected] + STOPKERWUCK: + MSIK: [0, MSIK oscillator automatically enabled when exiting Stop mode or when a CSS on HSE event occurs.] + HSI16: [1, HSI16 oscillator automatically enabled when exiting Stop mode or when a CSS on HSE event occurs.] + STOPWUCK: + MSIS: [0, MSIS oscillator selected as wake-up from stop clock and CSS backup clock] + HSI16: [1, HSI16 oscillator selected as wake-up from stop clock and CSS backup clock] + SWS: + _read: + MSIS: [0, MSIS oscillator used as system clock] + HSI16: [1, HSI16 oscillator used as system clock] + HSE: [2, HSE used as system clock] + PLL: [3, PLL pll1_r_ck used as system clock] + SW: + MSIS: [0, MSIS selected as system clock] + HSI16: [1, HSI16 selected as system clock] + HSE: [2, HSE selected as system clock] + PLL: [3, PLL pll1_r_ck selected as system clock] +CFGR2: + APB2DIS: + Enabled: + [0, "APB2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"] + Disabled: [1, APB2 clock disabled] + APB1DIS: + Enabled: + [0, "APB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"] + Disabled: [1, APB1 clock disabled] + AHB2DIS2: + Enabled: + [0, "AHB2_2 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"] + Disabled: [1, AHB2_2 clock disabled] + AHB2DIS1: + Enabled: + [0, "AHB2_1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"] + Disabled: [1, AHB2_1 clock disabled] + AHB1DIS: + Enabled: + [0, "AHB1 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"] + Disabled: [1, AHB1 clock disabled] + DPRE: + Div1: [-1, DCLK not divided] + Div2: [4, DCLK divided by 2] + Div4: [5, DCLK divided by 4] + Div8: [6, DCLK divided by 8] + Div16: [7, DCLK divided by 16] + PPRE?: + Div1: [-1, PCLK not divided] + Div2: [4, PCLK divided by 2] + Div4: [5, PCLK divided by 4] + Div8: [6, PCLK divided by 8] + Div16: [7, PCLK divided by 16] + HPRE: + Div1: [-1, HCLK not divided] + Div2: [8, HCLK divided by 2] + Div4: [9, HCLK divided by 4] + Div8: [10, HCLK divided by 8] + Div16: [11, HCLK divided by 16] + Div64: [12, HCLK divided by 64] + Div128: [13, HCLK divided by 128] + Div256: [14, HCLK divided by 256] + Div512: [15, HCLK divided by 512] +CFGR3: + APB3DIS: + Enabled: + [0, "APB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"] + Disabled: [1, APB3 clock disabled] + AHB3DIS: + Enabled: + [0, "AHB3 clock enabled, distributed to peripherals according to their dedicated clock enable control bits"] + Disabled: [1, AHB3 clock disabled] + PPRE3: + Div1: [-1, PCLK not divided] + Div2: [4, PCLK divided by 2] + Div4: [5, PCLK divided by 4] + Div8: [6, PCLK divided by 8] + Div16: [7, PCLK divided by 16] +PLL?CFGR: + PLL?REN: + Disabled: [0, pllx_r_ck ready interrupt disabled] + Enabled: [1, pllx_r_ck ready interrupt enabled] + PLL?QEN: + Disabled: [0, pllx_q_ck output disabled] + Enabled: [1, pllx_q_ck output enabled] + PLL?PEN: + Disabled: [0, pllx_p_ck output disabled] + Enabled: [1, pllx_p_ck output enabled] + PLL?M: + Div1: [0, division by 1 (bypass)] + Div2: [1, division by 2] + Div3: [2, division by 3] + Div4: [3, division by 4] + Div5: [4, division by 5] + Div6: [5, division by 6] + Div7: [6, division by 7] + Div8: [7, division by 8] + Div9: [8, division by 9] + Div10: [9, division by 10] + Div11: [10, division by 11] + Div12: [11, division by 12] + Div13: [12, division by 13] + Div14: [13, division by 14] + Div15: [14, division by 15] + Div16: [15, division by 16] + PLL?FRACEN: + NoEffect: [0, No effect] + Latch: [1, Content of PLLxFRACN latched in the Σ∆ modulator on PLLxFRACEN transition from 0 to 1] + PLL?RGE: + Range1: [-1, PLLx input (refx_ck) clock range frequency between 4 and 8 MHz] + Range2: [3, PLLx input (refx_ck) clock range frequency between 8 and 16 MHz] + PLL?SRC: + NoClock: [0, No clock sent to PLLx] + MSIS: [1, MSIS clock selected as PLLx clock entry] + HSI16: [2, HSI16 clock selected as PLLx clock entry] + HSE: [3, HSE clock selected as PLLx clock entry] +PLL1CFGR: + PLL1MBOOST: + Div1: [0, division by 1 (bypass)] + Div2: [1, division by 2] + Div4: [2, division by 4] + Div6: [3, division by 6] + Div8: [4, division by 8] + Div10: [5, division by 10] + Div12: [6, division by 12] + Div14: [7, division by 14] + Div16: [8, division by 16] +PLL?DIVR: + PLL?R: + Div1: [0, "pllx_r_ck = vcox_ck"] + Div2: [1, "pllx_r_ck = vcox_ck / 2"] + Div4: [3, "pllx_r_ck = vcox_ck / 4"] + Div6: [5, "pllx_r_ck = vcox_ck / 6"] + Div8: [7, "pllx_r_ck = vcox_ck / 8"] + Div10: [9, "pllx_r_ck = vcox_ck / 10"] + Div12: [11, "pllx_r_ck = vcox_ck / 12"] + Div14: [13, "pllx_r_ck = vcox_ck / 14"] + Div16: [15, "pllx_r_ck = vcox_ck / 16"] + Div18: [17, "pllx_r_ck = vcox_ck / 18"] + Div20: [19, "pllx_r_ck = vcox_ck / 20"] + Div22: [21, "pllx_r_ck = vcox_ck / 22"] + Div24: [23, "pllx_r_ck = vcox_ck / 24"] + Div26: [25, "pllx_r_ck = vcox_ck / 26"] + Div28: [27, "pllx_r_ck = vcox_ck / 28"] + Div30: [29, "pllx_r_ck = vcox_ck / 30"] + Div32: [31, "pllx_r_ck = vcox_ck / 32"] + Div34: [33, "pllx_r_ck = vcox_ck / 34"] + Div36: [35, "pllx_r_ck = vcox_ck / 36"] + Div38: [37, "pllx_r_ck = vcox_ck / 38"] + Div40: [39, "pllx_r_ck = vcox_ck / 40"] + Div42: [41, "pllx_r_ck = vcox_ck / 42"] + Div44: [43, "pllx_r_ck = vcox_ck / 44"] + Div46: [45, "pllx_r_ck = vcox_ck / 46"] + Div48: [47, "pllx_r_ck = vcox_ck / 48"] + Div50: [49, "pllx_r_ck = vcox_ck / 50"] + Div52: [51, "pllx_r_ck = vcox_ck / 52"] + Div54: [53, "pllx_r_ck = vcox_ck / 54"] + Div56: [55, "pllx_r_ck = vcox_ck / 56"] + Div58: [57, "pllx_r_ck = vcox_ck / 58"] + Div60: [59, "pllx_r_ck = vcox_ck / 60"] + Div62: [61, "pllx_r_ck = vcox_ck / 62"] + Div64: [63, "pllx_r_ck = vcox_ck / 64"] + Div66: [65, "pllx_r_ck = vcox_ck / 66"] + Div68: [67, "pllx_r_ck = vcox_ck / 68"] + Div70: [69, "pllx_r_ck = vcox_ck / 70"] + Div72: [71, "pllx_r_ck = vcox_ck / 72"] + Div74: [73, "pllx_r_ck = vcox_ck / 74"] + Div76: [75, "pllx_r_ck = vcox_ck / 76"] + Div78: [77, "pllx_r_ck = vcox_ck / 78"] + Div80: [79, "pllx_r_ck = vcox_ck / 80"] + Div82: [81, "pllx_r_ck = vcox_ck / 82"] + Div84: [83, "pllx_r_ck = vcox_ck / 84"] + Div86: [85, "pllx_r_ck = vcox_ck / 86"] + Div88: [87, "pllx_r_ck = vcox_ck / 88"] + Div90: [89, "pllx_r_ck = vcox_ck / 90"] + Div92: [91, "pllx_r_ck = vcox_ck / 92"] + Div94: [93, "pllx_r_ck = vcox_ck / 94"] + Div96: [95, "pllx_r_ck = vcox_ck / 96"] + Div98: [97, "pllx_r_ck = vcox_ck / 98"] + Div100: [99, "pllx_r_ck = vcox_ck / 100"] + Div102: [101, "pllx_r_ck = vcox_ck / 102"] + Div104: [103, "pllx_r_ck = vcox_ck / 104"] + Div106: [105, "pllx_r_ck = vcox_ck / 106"] + Div108: [107, "pllx_r_ck = vcox_ck / 108"] + Div110: [109, "pllx_r_ck = vcox_ck / 110"] + Div112: [111, "pllx_r_ck = vcox_ck / 112"] + Div114: [113, "pllx_r_ck = vcox_ck / 114"] + Div116: [115, "pllx_r_ck = vcox_ck / 116"] + Div118: [117, "pllx_r_ck = vcox_ck / 118"] + Div120: [119, "pllx_r_ck = vcox_ck / 120"] + Div122: [121, "pllx_r_ck = vcox_ck / 122"] + Div124: [123, "pllx_r_ck = vcox_ck / 124"] + Div126: [125, "pllx_r_ck = vcox_ck / 126"] + Div128: [127, "pllx_r_ck = vcox_ck / 128"] + PLL?Q: + Div1: [0, "pllx_q_ck = vcox_ck"] + Div2: [1, "pllx_q_ck = vcox_ck / 2"] + Div4: [3, "pllx_q_ck = vcox_ck / 4"] + Div6: [5, "pllx_q_ck = vcox_ck / 6"] + Div8: [7, "pllx_q_ck = vcox_ck / 8"] + Div10: [9, "pllx_q_ck = vcox_ck / 10"] + Div12: [11, "pllx_q_ck = vcox_ck / 12"] + Div14: [13, "pllx_q_ck = vcox_ck / 14"] + Div16: [15, "pllx_q_ck = vcox_ck / 16"] + Div18: [17, "pllx_q_ck = vcox_ck / 18"] + Div20: [19, "pllx_q_ck = vcox_ck / 20"] + Div22: [21, "pllx_q_ck = vcox_ck / 22"] + Div24: [23, "pllx_q_ck = vcox_ck / 24"] + Div26: [25, "pllx_q_ck = vcox_ck / 26"] + Div28: [27, "pllx_q_ck = vcox_ck / 28"] + Div30: [29, "pllx_q_ck = vcox_ck / 30"] + Div32: [31, "pllx_q_ck = vcox_ck / 32"] + Div34: [33, "pllx_q_ck = vcox_ck / 34"] + Div36: [35, "pllx_q_ck = vcox_ck / 36"] + Div38: [37, "pllx_q_ck = vcox_ck / 38"] + Div40: [39, "pllx_q_ck = vcox_ck / 40"] + Div42: [41, "pllx_q_ck = vcox_ck / 42"] + Div44: [43, "pllx_q_ck = vcox_ck / 44"] + Div46: [45, "pllx_q_ck = vcox_ck / 46"] + Div48: [47, "pllx_q_ck = vcox_ck / 48"] + Div50: [49, "pllx_q_ck = vcox_ck / 50"] + Div52: [51, "pllx_q_ck = vcox_ck / 52"] + Div54: [53, "pllx_q_ck = vcox_ck / 54"] + Div56: [55, "pllx_q_ck = vcox_ck / 56"] + Div58: [57, "pllx_q_ck = vcox_ck / 58"] + Div60: [59, "pllx_q_ck = vcox_ck / 60"] + Div62: [61, "pllx_q_ck = vcox_ck / 62"] + Div64: [63, "pllx_q_ck = vcox_ck / 64"] + Div66: [65, "pllx_q_ck = vcox_ck / 66"] + Div68: [67, "pllx_q_ck = vcox_ck / 68"] + Div70: [69, "pllx_q_ck = vcox_ck / 70"] + Div72: [71, "pllx_q_ck = vcox_ck / 72"] + Div74: [73, "pllx_q_ck = vcox_ck / 74"] + Div76: [75, "pllx_q_ck = vcox_ck / 76"] + Div78: [77, "pllx_q_ck = vcox_ck / 78"] + Div80: [79, "pllx_q_ck = vcox_ck / 80"] + Div82: [81, "pllx_q_ck = vcox_ck / 82"] + Div84: [83, "pllx_q_ck = vcox_ck / 84"] + Div86: [85, "pllx_q_ck = vcox_ck / 86"] + Div88: [87, "pllx_q_ck = vcox_ck / 88"] + Div90: [89, "pllx_q_ck = vcox_ck / 90"] + Div92: [91, "pllx_q_ck = vcox_ck / 92"] + Div94: [93, "pllx_q_ck = vcox_ck / 94"] + Div96: [95, "pllx_q_ck = vcox_ck / 96"] + Div98: [97, "pllx_q_ck = vcox_ck / 98"] + Div100: [99, "pllx_q_ck = vcox_ck / 100"] + Div102: [101, "pllx_q_ck = vcox_ck / 102"] + Div104: [103, "pllx_q_ck = vcox_ck / 104"] + Div106: [105, "pllx_q_ck = vcox_ck / 106"] + Div108: [107, "pllx_q_ck = vcox_ck / 108"] + Div110: [109, "pllx_q_ck = vcox_ck / 110"] + Div112: [111, "pllx_q_ck = vcox_ck / 112"] + Div114: [113, "pllx_q_ck = vcox_ck / 114"] + Div116: [115, "pllx_q_ck = vcox_ck / 116"] + Div118: [117, "pllx_q_ck = vcox_ck / 118"] + Div120: [119, "pllx_q_ck = vcox_ck / 120"] + Div122: [121, "pllx_q_ck = vcox_ck / 122"] + Div124: [123, "pllx_q_ck = vcox_ck / 124"] + Div126: [125, "pllx_q_ck = vcox_ck / 126"] + Div128: [127, "pllx_q_ck = vcox_ck / 128"] + PLL?P: + Div1: [0, "pllx_p_ck = vcox_ck"] + Div2: [1, "pllx_p_ck = vcox_ck / 2"] + Div4: [3, "pllx_p_ck = vcox_ck / 4"] + Div6: [5, "pllx_p_ck = vcox_ck / 6"] + Div8: [7, "pllx_p_ck = vcox_ck / 8"] + Div10: [9, "pllx_p_ck = vcox_ck / 10"] + Div12: [11, "pllx_p_ck = vcox_ck / 12"] + Div14: [13, "pllx_p_ck = vcox_ck / 14"] + Div16: [15, "pllx_p_ck = vcox_ck / 16"] + Div18: [17, "pllx_p_ck = vcox_ck / 18"] + Div20: [19, "pllx_p_ck = vcox_ck / 20"] + Div22: [21, "pllx_p_ck = vcox_ck / 22"] + Div24: [23, "pllx_p_ck = vcox_ck / 24"] + Div26: [25, "pllx_p_ck = vcox_ck / 26"] + Div28: [27, "pllx_p_ck = vcox_ck / 28"] + Div30: [29, "pllx_p_ck = vcox_ck / 30"] + Div32: [31, "pllx_p_ck = vcox_ck / 32"] + Div34: [33, "pllx_p_ck = vcox_ck / 34"] + Div36: [35, "pllx_p_ck = vcox_ck / 36"] + Div38: [37, "pllx_p_ck = vcox_ck / 38"] + Div40: [39, "pllx_p_ck = vcox_ck / 40"] + Div42: [41, "pllx_p_ck = vcox_ck / 42"] + Div44: [43, "pllx_p_ck = vcox_ck / 44"] + Div46: [45, "pllx_p_ck = vcox_ck / 46"] + Div48: [47, "pllx_p_ck = vcox_ck / 48"] + Div50: [49, "pllx_p_ck = vcox_ck / 50"] + Div52: [51, "pllx_p_ck = vcox_ck / 52"] + Div54: [53, "pllx_p_ck = vcox_ck / 54"] + Div56: [55, "pllx_p_ck = vcox_ck / 56"] + Div58: [57, "pllx_p_ck = vcox_ck / 58"] + Div60: [59, "pllx_p_ck = vcox_ck / 60"] + Div62: [61, "pllx_p_ck = vcox_ck / 62"] + Div64: [63, "pllx_p_ck = vcox_ck / 64"] + Div66: [65, "pllx_p_ck = vcox_ck / 66"] + Div68: [67, "pllx_p_ck = vcox_ck / 68"] + Div70: [69, "pllx_p_ck = vcox_ck / 70"] + Div72: [71, "pllx_p_ck = vcox_ck / 72"] + Div74: [73, "pllx_p_ck = vcox_ck / 74"] + Div76: [75, "pllx_p_ck = vcox_ck / 76"] + Div78: [77, "pllx_p_ck = vcox_ck / 78"] + Div80: [79, "pllx_p_ck = vcox_ck / 80"] + Div82: [81, "pllx_p_ck = vcox_ck / 82"] + Div84: [83, "pllx_p_ck = vcox_ck / 84"] + Div86: [85, "pllx_p_ck = vcox_ck / 86"] + Div88: [87, "pllx_p_ck = vcox_ck / 88"] + Div90: [89, "pllx_p_ck = vcox_ck / 90"] + Div92: [91, "pllx_p_ck = vcox_ck / 92"] + Div94: [93, "pllx_p_ck = vcox_ck / 94"] + Div96: [95, "pllx_p_ck = vcox_ck / 96"] + Div98: [97, "pllx_p_ck = vcox_ck / 98"] + Div100: [99, "pllx_p_ck = vcox_ck / 100"] + Div102: [101, "pllx_p_ck = vcox_ck / 102"] + Div104: [103, "pllx_p_ck = vcox_ck / 104"] + Div106: [105, "pllx_p_ck = vcox_ck / 106"] + Div108: [107, "pllx_p_ck = vcox_ck / 108"] + Div110: [109, "pllx_p_ck = vcox_ck / 110"] + Div112: [111, "pllx_p_ck = vcox_ck / 112"] + Div114: [113, "pllx_p_ck = vcox_ck / 114"] + Div116: [115, "pllx_p_ck = vcox_ck / 116"] + Div118: [117, "pllx_p_ck = vcox_ck / 118"] + Div120: [119, "pllx_p_ck = vcox_ck / 120"] + Div122: [121, "pllx_p_ck = vcox_ck / 122"] + Div124: [123, "pllx_p_ck = vcox_ck / 124"] + Div126: [125, "pllx_p_ck = vcox_ck / 126"] + Div128: [127, "pllx_p_ck = vcox_ck / 128"] + PLL?N: [3, 0x1FF] +PLL?FRACR: + PLL?FRACN: [0, 0x1FF] +CIER: + "*RDYIE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] +CIFR: + "*RDYF": + _read: + NotInterrupted: [0, No clock ready interrupt] + Interrupted: [1, Clock ready interrupt] +CICR: + "*RDYC": + _write: + Clear: [1, Clear flag] +A[HP]B?RSTR*: + "*RST": + NoEffect: [0, No effect] + Reset: [1, Reset peripheral] +A[HP]B?ENR*: + "*EN": + Disabled: [0, Peripheral clock disabled] + Enabled: [1, Peripheral clock enabled] +A[HP]B?SMENR*: + "*SMEN": + Disabled: [0, Peripheral clocks disabled by the clock gating during Sleep and Stop modes] + Enabled: [1, Peripheral clocks enabled by the clock gating during Sleep and Stop modes] +SRDAMR: + "*AMEN": + Disabled: [0, Peripheral autonomous mode disabled during Stop 0/1/2 mode] + Enabled: [1, Peripheral autonomous mode enabled during Stop 0/1/2 mode] +CCIPR1: + TIMICSEL: + Disabled: [-1, "HSI, MSIK and MSIS dividers disabled"] + HsiMsisMsis: + [ + 4, + "HSI/256, MSIS/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture", + ] + HsiMsisMsik: + [ + 5, + "HSI/256, MSIS/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture", + ] + HsiMsikMsis: + [ + 6, + "HSI/256, MSIK/1024 and MSIS/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture", + ] + HsiMsikMsik: + [ + 7, + "HSI/256, MSIK/1024 and MSIK/4 generated and can be selected by TIM16, TIM17, and LPTIM2 as internal input capture", + ] + ICLKSEL: + HSI: [0, HSI48 clock selected] + PLL2Q: [1, 'PLL2 "Q" (pll2_q_ck) selected'] + PLL1Q: [2, 'PLL1 "Q" (pll1_q_ck) selected'] + MSIK: [3, MSIK clock selected] + FDCAN1SEL: + HSE: [0, HSE clock selected] + PLL1Q: [1, 'PLL1 "Q" (pll2_q_ck) selected'] + PLL2P: [2, 'PLL2 "P" (pll1_p_ck) selected'] + SYSTICKSEL: + HCLK_Div8: [0, HCLK/8 selected] + LSI: [1, LSI selected] + LSE: [2, LSE selected] + LPTIM2SEL: + PCLK1: [0, PCLK1 selected] + LSI: [1, LSI selected] + HSI16: [2, HSI16 selected] + MSIK: [3, MSIK selected] + SPI?SEL,I2C[124]SEL,UART[45]SEL,USART?SEL: + PCLK: [0, PCLKx selected] + SYSCLK: [1, SYSCLK selected] + HSI16: [2, HSI16 selected] + MSIK: [3, MSIK selected] +CCIPR2: + OTGHSSEL: + HSE: [0, HSE selected] + PLL1P: [1, 'PLL1 "Q" (pll1_q_ck) selected'] + HSE2: [2, HSE/2 selected] + PLL1P_Div2: [3, 'PLL1 "P" divided by 2 (pll1_p_ck/2) selected'] + I2C[56]SEL,USART6SEL: + PCLK1: [0, PCLK1 selected] + SYSCLK: [1, SYSCLK selected] + HSI16: [2, HSI16 selected] + MSIK: [3, MSIK selected] + HSPI1SEL: + SYSCLK: [0, SYSCLK selected] + PLL1Q: [1, 'PLL1 "Q" (pll1_q_ck) selected, can be up to 200 MHz'] + PLL2Q: [2, 'PLL2 "Q" (pll2_q_ck) selected, can be up to 200 MHz'] + PLL3R: [3, 'PLL3 "R" (pll3_r_ck) selected, can be up to 200 MHz'] + OCTOSPISEL: + SYSCLK: [0, SYSCLK selected] + MSIK: [1, MSIK selected] + PLL1Q: [2, 'PLL1 "Q" (pll1_q_ck) selected, can be up to 200 MHz'] + PLL2Q: [3, 'PLL2 "Q" (pll2_q_ck) selected, can be up to 200 MHz'] + LTDCSEL: + PLL3R: [0, 'PLL3 "R" (pll3_r_ck) selected'] + PLL2R: [1, 'PLL2 "R" (pll2_r_ck) selected'] + DSISEL: + PLL3P: [0, 'PLL3 "P" (pll3_p_ck) selected'] + DSI_PHY_PLL: [1, DSI PHY PLL output selected] + SDMMCSEL: + ICLK: [0, ICLK clock selected] + PLL1P: [1, 'PLL1 "P" (pll1_p_ck) selected, in case higher than 48 MHz is needed (for SDR50 mode)'] + RNGSEL: + HSI48: [0, HSI48 clock selected] + HSI48_Div2: [1, "HSI48 / 2 selected, can be used in range 4"] + HSI16: [2, HSI16 selected] + SAESSEL: + SHSI: [0, SHSI selected] + SHSI_Div2: [1, "SHSI / 2 selected, can be used in range 4"] + SAI?SEL: + PLL2P: [0, 'PLL2 "P" (pll2_p_ck) selected'] + PLL3P: [1, 'PLL3 "P" (pll3_p_ck) selected'] + PLL1P: [2, 'PLL1 "P" (pll1_p_ck) selected'] + AUDIOCLK: [3, input pin AUDIOCLK selected] + HSI16: [4, HSI16 clock selected] + MDF1SEL: + HCLK: [0, HCLK selected] + PLL1P: [1, 'PLL1 "P" (pll1_p_ck) selected'] + PLL3Q: [2, 'PLL3 "Q" (pll3_q_ck) selected'] + AUDIOCLK: [3, input pin AUDIOCLK selected] + MSIK: [4, MSIK clock selected] +CCIPR3: + ADF1SEL: + HCLK: [0, HCLK selected] + PLL1P: [1, 'PLL1 "P" (pll1_p_ck) selected'] + PLL3Q: [2, 'PLL3 "Q" (pll3_q_ck) selected'] + AUDIOCLK: [3, input pin AUDIOCLK selected] + MSIK: [4, MSIK clock selected] + DAC1SEL: + LSE: [0, LSE selected] + LSI: [1, LSI selected] + ADCDACSEL: + HCLK: [0, HCLK clock selected] + SYSCLK: [1, SYSCLK selected] + PLL2R: [2, 'PLL2 "R" (pll2_r_ck) selected'] + HSE: [3, HSE clock selected] + HSI16: [4, HSI16 clock selected] + MSIK: [5, MSIK clock selected] + LPTIM1SEL: + MSIK: [0, MSIK clock selected] + LSI: [1, LSI selected] + HSI16: [2, HSI16 selected] + LSE: [3, LSE selected] + LPTIM34SEL: + MSIK: [0, MSIK clock selected] + LSI: [1, LSI selected] + HSI: [2, HSI selected] + LSE: [3, LSE selected] + I2C3SEL,SPI3SEL: + PCLK3: [0, PCLK3 selected] + SYSCLK: [1, SYSCLK selected] + HSI16: [2, HSI16 selected] + MSIK: [3, MSIK selected] + LPUART1SEL: + PCLK3: [0, PCLK3 selected] + SYSCLK: [1, SYSCLK selected] + HSI16: [2, HSI16 selected] + LSE: [3, LSE selected] + MSIK: [4, MSIK selected] +BDCR: + LSIPREDIV: + Div1: [0, LSI not divided] + Div128: [1, LSI divided by 128] + LSIRDY: + _read: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSION: + Disabled: [0, LSI oscillator OFF] + Enabled: [1, LSI oscillator ON] + LSCOSEL: + LSI: [0, LSI clock selected] + LSE: [1, LSE clock selected] + LSCOEN: + Disabled: [0, LSCO disabled] + Enabled: [1, LSCO enabled] + BDRST: + NoReset: [0, Reset not activated] + Reset: [1, Reset the entire backup domain] + RTCEN: + Disabled: [0, RTC and TAMP clock disabled] + Enabled: [1, RTC and TAMP clock enabled] + LSEGFON: + Disabled: [0, LSE glitch filter disabled] + Enabled: [1, LSE glitch filter enabled] + LSESYSRDY: + _read: + NotReady: [0, LSESYS clock not ready] + Ready: [1, LSESYS clock ready] + RTCSEL: + NoClock: [0, No clock selected] + LSE: [1, LSE oscillator clock selected] + LSI: [2, LSI oscillator clock selected] + HSE_Div32: [3, HSE oscillator clock divided by 32 selected] + LSESYSEN: + Disabled: [0, "LSE can be used only for RTC, TAMP, and CSS on LSE"] + Enabled: [1, LSE can be used by any other peripheral or function] + LSECSSD: + _read: + NoFailure: [0, No failure detected on LSE] + Failure: [1, Failure detected on LSE] + LSECSSON: + Disabled: [0, CSS on LSE OFF] + Enabled: [1, CSS on LSE ON] + LSEDRV: + Lower: [0, "'Xtal mode' lower driving capability"] + MediumLow: [1, "'Xtal mode' medium-low driving capability"] + MediumHigh: [2, "'Xtal mode' medium-high driving capability"] + Higher: [3, "'Xtal mode' higher driving capability"] + LSEBYP: + NotBypassed: [0, LSE oscillator not bypassed] + Bypassed: [1, LSE oscillator bypassed] + LSERDY: + _read: + NotReady: [0, LSE oscillator not ready] + Ready: [1, LSE oscillator ready] + LSEON: + Disabled: [0, LSE oscillator off] + Enabled: [1, LSE oscillator on] +CSR: + LPWRRSTF: + _read: + NotOccured: [0, No illegal low-power mode reset occurred] + Occured: [1, Illegal low-power mode reset occurred] + WWDGRSTF: + _read: + NotOccured: [0, No window watchdog reset occurred] + Occured: [1, Window watchdog reset occurred] + IWDGRSTF: + _read: + NotOccured: [0, No independent watchdog reset occurred] + Occured: [1, Independent watchdog reset occurred] + SFTRSTF: + _read: + NotOccured: [0, No software reset occurred] + Occured: [1, Software reset occurred] + BORRSTF: + _read: + NotOccured: [0, No BOR/exit from Shutdown mode reset occurred] + Occured: [1, BOR/exit from Shutdown mode reset occurred] + PINRSTF: + _read: + NotOccured: [0, No reset from NRST pin occurred] + Occured: [1, Reset from NRST pin occurred] + OBLRSTF: + _read: + NotOccured: [0, No reset from option-byte loading occurred] + Occured: [1, Reset from option-byte loading occurred] + RMVF: + _write: + Clear: [1, Clear the reset flags] + MSI?SRANGE: + f_4MHz: [4, Range 4 around 4 MHz] + f_2MHz: [5, Range 5 around 2 MHz] + f_1_33MHz: [6, Range 6 around 1.33 MHz] + f_1MHz: [7, Range 7 around 1 MHz] + f_3_072MHz: [8, Range 8 around 3.072 MHz] +SECCFGR: + "*SEC": + NonSecure: [0, Nonsecure] + Secure: [1, Secure] +PRIVCFGR: + NSPRIV: + Unprivileged: [0, Read and write to RCC nonsecure functions can be done by privileged or unprivileged access] + Privileged: [1, Read and write to RCC nonsecure functions can be done by privileged access only] + SPRIV: + Unprivileged: [0, Read and write to RCC secure functions can be done by privileged or unprivileged access] + Privileged: [1, Read and write to RCC secure functions can be done by privileged access only] diff --git a/devices/fields/rcc/rcc_wb.yaml b/devices/fields/rcc/rcc_wb.yaml new file mode 100644 index 000000000..94e0f8157 --- /dev/null +++ b/devices/fields/rcc/rcc_wb.yaml @@ -0,0 +1,465 @@ +_add: + HSECR_KEY: + alternateRegister: HSECR + addressOffset: 0x9C + access: write-only + fields: + KEY: + bitOffset: 0 + bitWidth: 32 +HSECR_KEY: + KEY: + Unlock: [0xcafecafe, Write enable key] + +CR: + PLLSAI1RDY: + Unlocked: [0, PLLSAI1 unlocked] + Locked: [1, PLLSAI1 unlocked] + PLLSAI1ON: + "Off": [0, PLLSAI1 Off] + "On": [1, PLLSAI1 On] + PLLRDY: + Unlocked: [0, PLL unlocked] + Locked: [1, PLL Locked] + PLLON: + "Off": [0, Main PLL Off] + "On": [1, Main PLL On] + HSEPRE: + Div1: [0, SYSCLK not divided (HSE32)] + Div2: [1, SYSCLK divided by two (HSE32/2)] + CSSON: + Disabled: [0, HSE32 CSS off] + Enabled: [1, HSE32 CSS on if the HSE32 oscillator is stable and off if not] + HSERDY: + NotReady: [0, HSE32 oscillator not ready] + Ready: [1, HSE32 oscillator ready] + HSEON: + Disabled: [0, HSE32 oscillator for CPU disabled] + Enabled: [1, HSE32 oscillator for CPU enabled] + HSIKERDY: + NotReady: [0, HSI16 oscillator not ready] + Ready: [1, HSI16 oscillator ready] + HSIASFS: + Disabled: [0, HSI16 not enabled by hardware when exiting Stop modes with MSI as wakeup clock] + Enabled: [1, HSI16 enabled by hardware when exiting Stop mode with MSI as wakeup clock] + HSIRDY: + NotReady: [0, HSI16 oscillator not ready] + Ready: [1, HSI16 oscillator ready] + HSIKERON: + NotForced: [0, No effect on HSI16 oscillator] + Forced: [1, HSI16 oscillator forced on even in Stop modes] + HSION: + Disabled: [0, HSI16 oscillator off] + Enabled: [1, HSI16 oscillator on] + MSIRANGE: + Range100K: [0b0000, range 0 around 100 kHz] + Range200K: [0b0001, range 1 around 200 kHz] + Range400K: [0b0010, range 2 around 400 kHz] + Range800K: [0b0011, range 3 around 800 kHz] + Range1M: [0b0100, range 4 around 1 MHz] + Range2M: [0b0101, range 5 around 2 MHz] + Range4M: [0b0110, range 6 around 4 MHz (reset value)] + Range8M: [0b0111, range 7 around 8 MHz] + Range16M: [0b1000, range 8 around 16 MHz] + Range24M: [0b1001, range 9 around 24 MHz] + Range32M: [0b1010, range 10 around 32 MHz] + Range48M: [0b1011, range 11 around 48 MHz] + MSIPLLEN: + "Off": [0, MSI PLL Off] + "On": [1, MSI PLL On] + MSIRDY: + NotReady: [0, MSI oscillator not ready] + Ready: [1, MSI oscillator ready] + MSION: + Disabled: [0, MSI oscillator off] + Enabled: [1, MSI oscillator on] + +ICSCR: + HSITRIM: [0, 0x3F] + HSICAL: [0, 0xFF] + MSITRIM: [0, 0xFF] + MSICAL: [0, 0xFF] + +CFGR: + MCOPRE: + Div1: [0, No division] + Div2: [1, Division by 2] + Div4: [2, Division by 4] + Div8: [3, Division by 8] + Div16: [4, Division by 16] + MCOSEL: + NoClock: [0, No clock] + SYSCLK: [1, SYSCLK clock selected] + MSI: [2, MSI oscillator clock selected] + HSI16: [3, HSI16 oscillator clock selected] + HSE32: [4, HSE32 oscillator clock selected] + PLLR: [5, Main PLLRCLK clock selected] + LSI: [6, LSI oscillator clock selected] + LSE: [8, LSE oscillator clock selected] + PLLP: [13, Main PLLPCLK clock selected] + PLLQ: [14, Main PLLQCLK clock selected] + PPRE2F: + NotApplied: [0, PCLK2 prescaler value not yet applied] + Applied: [1, PCLK2 prescaler value applied] + PPRE1F: + NotApplied: [0, PCLK1 prescaler value not yet applied] + Applied: [1, PCLK1 prescaler value applied] + HPREF: + NotApplied: [0, HCLK1 prescaler value not yet applied] + Applied: [1, HCLK1 prescaler value applied] + STOPWUCK: + MSI: [0, MSI oscillator selected as wakeup from stop clock and CSS backup clock] + HSI16: [1, HSI16 oscillator selected as wakeup from stop clock and CSS backup clock] + PPRE2: + Div1: [-1, HCLK not divided] + Div2: [4, HCLK divided by 2] + Div4: [5, HCLK divided by 4] + Div8: [6, HCLK divided by 8] + Div16: [7, HCLK divided by 16] + PPRE1: + Div1: [-1, HCLK not divided] + Div2: [4, HCLK divided by 2] + Div4: [5, HCLK divided by 4] + Div8: [6, HCLK divided by 8] + Div16: [7, HCLK divided by 16] + HPRE: + Div1: [-1, SYSCLK not divided] + Div3: [0b0001, SYSCLK divided by 3] + Div5: [0b0010, SYSCLK divided by 5] + Div6: [0b0101, SYSCLK divided by 6] + Div10: [0b0110, SYSCLK divided by 10] + Div32: [0b0111, SYSCLK divided by 32] + Div2: [0b1000, SYSCLK divided by 2] + Div4: [0b1001, SYSCLK divided by 4] + Div8: [0b1010, SYSCLK divided by 8] + Div16: [0b1011, SYSCLK divided by 16] + Div64: [0b1100, SYSCLK divided by 64] + Div128: [0b1101, SYSCLK divided by 128] + Div256: [0b1110, SYSCLK divided by 256] + Div512: [0b1111, SYSCLK divided by 512] + SWS: + MSI: [0, MSI oscillator used as system clock] + HSI16: [1, HSI16 oscillator used as system clock] + HSE32: [2, HSE32 oscillator used as system clock] + PLLR: [3, PLLRCLK used as system clock] + SW: + MSI: [0, MSI oscillator used as system clock] + HSI16: [1, HSI16 oscillator used as system clock] + HSE32: [2, HSE32 oscillator used as system clock] + PLLR: [3, PLLRCLK used as system clock] + +PLLCFGR: + "PLL[RQ]": + Div2: [1, "PLL = VCO/(N+1)"] + Div3: [2, "PLL = VCO/(N+1)"] + Div4: [3, "PLL = VCO/(N+1)"] + Div5: [4, "PLL = VCO/(N+1)"] + Div6: [5, "PLL = VCO/(N+1)"] + Div7: [6, "PLL = VCO/(N+1)"] + Div8: [7, "PLL = VCO/(N+1)"] + "PLL[PRQ]EN": + Disabled: [0, PLLCLK output disabled] + Enabled: [1, PLLCLK output enabled] + PLLP: + Div2: [1, "PLL = VCO/(N+1)"] + Div3: [2, "PLL = VCO/(N+1)"] + Div4: [3, "PLL = VCO/(N+1)"] + Div5: [4, "PLL = VCO/(N+1)"] + Div6: [5, "PLL = VCO/(N+1)"] + Div7: [6, "PLL = VCO/(N+1)"] + Div8: [7, "PLL = VCO/(N+1)"] + Div9: [8, "PLL = VCO/(N+1)"] + Div10: [9, "PLL = VCO/(N+1)"] + Div11: [10, "PLL = VCO/(N+1)"] + Div12: [11, "PLL = VCO/(N+1)"] + Div13: [12, "PLL = VCO/(N+1)"] + Div14: [13, "PLL = VCO/(N+1)"] + Div15: [14, "PLL = VCO/(N+1)"] + Div16: [15, "PLL = VCO/(N+1)"] + Div17: [16, "PLL = VCO/(N+1)"] + Div18: [17, "PLL = VCO/(N+1)"] + Div19: [18, "PLL = VCO/(N+1)"] + Div20: [19, "PLL = VCO/(N+1)"] + Div21: [20, "PLL = VCO/(N+1)"] + Div22: [21, "PLL = VCO/(N+1)"] + Div23: [22, "PLL = VCO/(N+1)"] + Div24: [23, "PLL = VCO/(N+1)"] + Div25: [24, "PLL = VCO/(N+1)"] + Div26: [25, "PLL = VCO/(N+1)"] + Div27: [26, "PLL = VCO/(N+1)"] + Div28: [27, "PLL = VCO/(N+1)"] + Div29: [28, "PLL = VCO/(N+1)"] + Div30: [29, "PLL = VCO/(N+1)"] + Div31: [30, "PLL = VCO/(N+1)"] + Div32: [31, "PLL = VCO/(N+1)"] + PLLN: [4, 127] + PLLM: + Div1: [0, "VCO input = PLL input / PLLM"] + Div2: [1, "VCO input = PLL input / PLLM"] + Div3: [2, "VCO input = PLL input / PLLM"] + Div4: [3, "VCO input = PLL input / PLLM"] + Div5: [4, "VCO input = PLL input / PLLM"] + Div6: [5, "VCO input = PLL input / PLLM"] + Div7: [6, "VCO input = PLL input / PLLM"] + Div8: [7, "VCO input = PLL input / PLLM"] + PLLSRC: + NoClock: [0, No clock sent to PLL] + MSI: [1, MSI clock selected as PLL and PLLSAI1 clock entry] + HSI16: [2, HSI16 clock selected as PLL and PLLSAI1 clock entry] + HSE32: [3, HSE32 clock selected as PLL and PLLSAI1 clock entry] + +PLLSAI1CFGR: + "PLL[RQ]": + Div2: [1, "PLL = VCO/(N+1)"] + Div3: [2, "PLL = VCO/(N+1)"] + Div4: [3, "PLL = VCO/(N+1)"] + Div5: [4, "PLL = VCO/(N+1)"] + Div6: [5, "PLL = VCO/(N+1)"] + Div7: [6, "PLL = VCO/(N+1)"] + Div8: [7, "PLL = VCO/(N+1)"] + "PLL[PRQ]EN": + Disabled: [0, PLLCLK output disabled] + Enabled: [1, PLLCLK output enabled] + PLLP: + Div2: [1, "PLL = VCO/(N+1)"] + Div3: [2, "PLL = VCO/(N+1)"] + Div4: [3, "PLL = VCO/(N+1)"] + Div5: [4, "PLL = VCO/(N+1)"] + Div6: [5, "PLL = VCO/(N+1)"] + Div7: [6, "PLL = VCO/(N+1)"] + Div8: [7, "PLL = VCO/(N+1)"] + Div9: [8, "PLL = VCO/(N+1)"] + Div10: [9, "PLL = VCO/(N+1)"] + Div11: [10, "PLL = VCO/(N+1)"] + Div12: [11, "PLL = VCO/(N+1)"] + Div13: [12, "PLL = VCO/(N+1)"] + Div14: [13, "PLL = VCO/(N+1)"] + Div15: [14, "PLL = VCO/(N+1)"] + Div16: [15, "PLL = VCO/(N+1)"] + Div17: [16, "PLL = VCO/(N+1)"] + Div18: [17, "PLL = VCO/(N+1)"] + Div19: [18, "PLL = VCO/(N+1)"] + Div20: [19, "PLL = VCO/(N+1)"] + Div21: [20, "PLL = VCO/(N+1)"] + Div22: [21, "PLL = VCO/(N+1)"] + Div23: [22, "PLL = VCO/(N+1)"] + Div24: [23, "PLL = VCO/(N+1)"] + Div25: [24, "PLL = VCO/(N+1)"] + Div26: [25, "PLL = VCO/(N+1)"] + Div27: [26, "PLL = VCO/(N+1)"] + Div28: [27, "PLL = VCO/(N+1)"] + Div29: [28, "PLL = VCO/(N+1)"] + Div30: [29, "PLL = VCO/(N+1)"] + Div31: [30, "PLL = VCO/(N+1)"] + Div32: [31, "PLL = VCO/(N+1)"] + PLLN: [4, 127] + +CIER: + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + +CIFR: + _modify: + HSECSSF: + name: CSSF + "*F": + NotInterrupted: [0, Not interrupted] + Interrupted: [1, Interrupted] + +CICR: + _modify: + HSECSSC: + name: CSSC + "*C": + Clear: [1, Clear interrupt flag] + +SMPSCR: + SMPSSWS: + HSI16: [0, HSI16 oscillator used as SMPS step-down converter clock] + MSI: [1, MSI oscillator used as SMPS step-down converter clock] + HSE: [2, HSE oscillator used as SMPS step-down converter clock] + NoClock: [3, No clock is used] + SMPSSEL: + HSI16: [0, HSI16 selected as SMPS step-down converter clock] + MSI: [1, MSI selected as SMPS step-down converter clock] + HSE: [2, HSE selected as SMPS step-down converter clock] + +"AHB[123]RSTR": + "*": + NoReset: [0, No effect] + Reset: [1, Reset peripheral] + +"APB[123]RSTR?": + "*": + NoReset: [0, No effect] + Reset: [1, Reset peripheral] + +"A[PH]B[123]ENR": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +"APB[123]ENR?": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +"A[PH]B[123]SMENR?": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +CCIPR: + RNGSEL: + CLK48: [0, Use clock as selected by CLK48SEL] + LSI: [1, LSI clock selected] + LSE: [2, LSE clock selected] + ADCSEL: + NoClock: [0, No clock selected] + PLLSAI1: [1, PLLSAI1R clock selected] + PLL: [2, PLLP clock selected] + SYSCLK: [3, SYSCLK clock selected] + CLK48SEL: + HSI48: [0, HSI48 clock selected] + PLLSAI1: [1, PLLSAI1Q clock selected] + PLL: [2, PLLQ clock selected] + MSI: [3, MSI clock selected] + SAI1SEL: + PLLSAI1: [0, PLLSAI1P clock selected] + PLL: [1, PLLP clock selected] + HSI16: [2, HSI16 clock selected] + Ext: [3, External clock input selected] + "LPTIM[12]SEL": + PCLK: [0, PCLK clock selected] + LSI: [1, LSI clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + "I2C[13]SEL": + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LPUART1SEL: + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + USART1SEL: + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + +BDCR: + LSCOSEL: + LSI: [0, LSI clock selected] + LSE: [1, LSE clock selected] + LSCOEN: + Disabled: [0, LSCO disabled] + Enabled: [1, LSCO enabled] + BDRST: + NotActive: [0, Reset not activated] + Reset: [1, Entire Backup domain reset] + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock selected] + LSI: [2, LSI oscillator clock selected] + HSE32: [3, HSE32 oscillator clock divided by 32 selected] + _modify: + LSECSSD_: + name: LSECSSD + LSECSSD: + NoFailure: [0, No failure detected on LSE] + Failure: [1, Failure detected on LSE] + LSECSSON: + Disabled: [0, CSS on LSE disabled] + Enabled: [1, CSS on LSE enabled] + LSEDRV: + Low: [0, Xtal mode lower driving capability] + MedLow: [1, Xtal mode medium-low driving capability] + MedHigh: [2, Xtal mode medium-high driving capability] + High: [3, Xtal mode higher driving capability] + LSEBYP: + Disabled: [0, LSE oscillator not bypassed] + Enabled: [1, LSE oscillator bypassed] + LSERDY: + NotReady: [0, LSE oscillator not ready] + Ready: [1, LSE oscillator ready] + LSEON: + "Off": [0, LSE oscillator off] + "On": [1, LSE oscillator on] + +CSR: + LPWRRSTF,WWDGRSTF,IWDGRSTF,SFTRSTF,BORRSTF,PINRSTF,OBLRSTF: + NoReset: [0, No reset occurred] + Reset: [1, Reset occurred] + RMVF: + NoEffect: [0, No effect] + Clear: [1, Reset flags reset] + RFRSTS: + NoReset: [0, Radio system BLE and 802.15.4 not in reset] + Reset: [1, Radio system BLE and 802.15.4 under reset] + RFWKPSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock selected] + HSE: [3, HSE oscillator clock selected] + LSI[21]RDY: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSI[21]ON: + "Off": [0, LSI oscillator off] + "On": [1, LSI oscillator on] + +CRRCR: + HSI48RDY: + NotReady: [0, HSI48 oscillator not ready] + Ready: [1, HSI48 oscillator ready] + HSI48ON: + "Off": [0, HSI48 oscillator off] + "On": [1, HSI48 oscillator on] + +HSECR: + _modify: + HSETUNE: + access: read-write + HSEGMC: + Max0_18: [0, Current max limit 0.18 mA/V] + Max0_57: [1, Current max limit 0.57 mA/V] + Max0_78: [2, Current max limit 0.78 mA/V] + Max1_13: [3, Current max limit 1.13 mA/V] + Max0_61: [4, Current max limit 0.61 mA/V] + Max1_65: [5, Current max limit 1.65 mA/V] + Max2_12: [6, Current max limit 2.12 mA/V] + Max2_84: [7, Current max limit 2.84 mA/V] + HSES: + OneHalf: [0, HSE bias current factor 1/2] + ThreeQuarter: [1, HSE bias current factor 3/4] + +EXTCFGR: + RFCSS: + HSI16: [0, HSI16 used for radio system HCLK5 and APB3 clock] + HSE_Div2: [1, HSE divided by 2 used for radio system HCLK5 and APB3 clock] + C2HPREF: + NotApplied: [0, HCLK2 prescaler value not yet applied] + Applied: [1, HCLK2 prescaler value applied] + SHDHPREF: + NotApplied: [0, HCLK4 prescaler value not yet applied] + Applied: [1, HCLK4 prescaler value applied] + C2HPRE,SHDHPRE: + Div1: [0b0000, SYSCLK not divided] + Div3: [0b0001, SYSCLK divided by 3] + Div5: [0b0010, SYSCLK divided by 5] + Div6: [0b0101, SYSCLK divided by 6] + Div10: [0b0110, SYSCLK divided by 10] + Div32: [0b0111, SYSCLK divided by 32] + Div2: [0b1000, SYSCLK divided by 2] + Div4: [0b1001, SYSCLK divided by 4] + Div8: [0b1010, SYSCLK divided by 8] + Div16: [0b1011, SYSCLK divided by 16] + Div64: [0b1100, SYSCLK divided by 64] + Div128: [0b1101, SYSCLK divided by 128] + Div256: [0b1110, SYSCLK divided by 256] + Div512: [0b1111, SYSCLK divided by 512] diff --git a/devices/fields/rcc/rcc_wl.yaml b/devices/fields/rcc/rcc_wl.yaml new file mode 100644 index 000000000..6907c70c3 --- /dev/null +++ b/devices/fields/rcc/rcc_wl.yaml @@ -0,0 +1,360 @@ +CR: + PLLRDY: + Unlocked: [0, PLL unlocked] + Locked: [1, PLL Locked] + PLLON: + "Off": [0, Main PLL Off] + "On": [1, Main PLL On] + HSEBYPPWR: + PB0: [0, PB0 selected] + VDDTCXO: [1, VDDTCXO selected] + HSEPRE: + Div1: [0, SYSCLK not divided (HSE32)] + Div2: [1, SYSCLK divided by two (HSE32/2)] + CSSON: + Disabled: [0, HSE32 CSS off] + Enabled: [1, HSE32 CSS on if the HSE32 oscillator is stable and off if not] + HSERDY: + NotReady: [0, HSE32 oscillator not ready] + Ready: [1, HSE32 oscillator ready] + HSEON: + Disabled: [0, HSE32 oscillator for CPU disabled] + Enabled: [1, HSE32 oscillator for CPU enabled] + HSIKERDY: + NotReady: [0, HSI16 oscillator not ready] + Ready: [1, HSI16 oscillator ready] + HSIASFS: + Disabled: [0, HSI16 not enabled by hardware when exiting Stop modes with MSI as wakeup clock] + Enabled: [1, HSI16 enabled by hardware when exiting Stop mode with MSI as wakeup clock] + HSIRDY: + NotReady: [0, HSI16 oscillator not ready] + Ready: [1, HSI16 oscillator ready] + HSIKERON: + NotForced: [0, No effect on HSI16 oscillator] + Forced: [1, HSI16 oscillator forced on even in Stop modes] + HSION: + Disabled: [0, HSI16 oscillator off] + Enabled: [1, HSI16 oscillator on] + MSIRANGE: + Range100K: [0b0000, range 0 around 100 kHz] + Range200K: [0b0001, range 1 around 200 kHz] + Range400K: [0b0010, range 2 around 400 kHz] + Range800K: [0b0011, range 3 around 800 kHz] + Range1M: [0b0100, range 4 around 1 MHz] + Range2M: [0b0101, range 5 around 2 MHz] + Range4M: [0b0110, range 6 around 4 MHz (reset value)] + Range8M: [0b0111, range 7 around 8 MHz] + Range16M: [0b1000, range 8 around 16 MHz] + Range24M: [0b1001, range 9 around 24 MHz] + Range32M: [0b1010, range 10 around 32 MHz] + Range48M: [0b1011, range 11 around 48 MHz] + MSIRGSEL: + CSR: [0, "MSI frequency range defined by MSISRANGE[3:0] in the RCC_CSR register"] + CR: [1, "MSI frequency range defined by MSIRANGE[3:0] in the RCC_CR register"] + MSIPLLEN: + "Off": [0, MSI PLL Off] + "On": [1, MSI PLL On] + MSIRDY: + NotReady: [0, MSI oscillator not ready] + Ready: [1, MSI oscillator ready] + MSION: + Disabled: [0, MSI oscillator off] + Enabled: [1, MSI oscillator on] + +ICSCR: + HSITRIM: [0, 0x3F] + HSICAL: [0, 0xFF] + MSITRIM: [0, 0xFF] + MSICAL: [0, 0xFF] + +CFGR: + MCOPRE: + Div1: [0, No division] + Div2: [1, Division by 2] + Div4: [2, Division by 4] + Div8: [3, Division by 8] + Div16: [4, Division by 16] + MCOSEL: + NoClock: [0, No clock] + SYSCLK: [1, SYSCLK clock selected] + MSI: [2, MSI oscillator clock selected] + HSI16: [3, HSI16 oscillator clock selected] + HSE32: [4, HSE32 oscillator clock selected] + PLLR: [5, Main PLLRCLK clock selected] + LSI: [6, LSI oscillator clock selected] + LSE: [8, LSE oscillator clock selected] + PLLP: [13, Main PLLPCLK clock selected] + PLLQ: [14, Main PLLQCLK clock selected] + PPRE2F: + NotApplied: [0, PCLK2 prescaler value not yet applied] + Applied: [1, PCLK2 prescaler value applied] + PPRE1F: + NotApplied: [0, PCLK1 prescaler value not yet applied] + Applied: [1, PCLK1 prescaler value applied] + HPREF: + NotApplied: [0, HCLK1 prescaler value not yet applied] + Applied: [1, HCLK1 prescaler value applied] + STOPWUCK: + MSI: [0, MSI oscillator selected as wakeup from stop clock and CSS backup clock] + HSI16: [1, HSI16 oscillator selected as wakeup from stop clock and CSS backup clock] + PPRE[12]: + Div1: [-1, HCLK not divided] + Div2: [4, HCLK divided by 2] + Div4: [5, HCLK divided by 4] + Div8: [6, HCLK divided by 8] + Div16: [7, HCLK divided by 16] + HPRE: + Div1: [-1, SYSCLK not divided] + Div3: [0b0001, SYSCLK divided by 3] + Div5: [0b0010, SYSCLK divided by 5] + Div6: [0b0101, SYSCLK divided by 6] + Div10: [0b0110, SYSCLK divided by 10] + Div32: [0b0111, SYSCLK divided by 32] + Div2: [0b1000, SYSCLK divided by 2] + Div4: [0b1001, SYSCLK divided by 4] + Div8: [0b1010, SYSCLK divided by 8] + Div16: [0b1011, SYSCLK divided by 16] + Div64: [0b1100, SYSCLK divided by 64] + Div128: [0b1101, SYSCLK divided by 128] + Div256: [0b1110, SYSCLK divided by 256] + Div512: [0b1111, SYSCLK divided by 512] + SWS: + MSI: [0, MSI oscillator used as system clock] + HSI16: [1, HSI16 oscillator used as system clock] + HSE32: [2, HSE32 oscillator used as system clock] + PLLR: [3, PLLRCLK used as system clock] + SW: + MSI: [0, MSI oscillator used as system clock] + HSI16: [1, HSI16 oscillator used as system clock] + HSE32: [2, HSE32 oscillator used as system clock] + PLLR: [3, PLLRCLK used as system clock] + +PLLCFGR: + "PLL[RQ]": + Div2: [1, "PLL = VCO/(N+1)"] + Div3: [2, "PLL = VCO/(N+1)"] + Div4: [3, "PLL = VCO/(N+1)"] + Div5: [4, "PLL = VCO/(N+1)"] + Div6: [5, "PLL = VCO/(N+1)"] + Div7: [6, "PLL = VCO/(N+1)"] + Div8: [7, "PLL = VCO/(N+1)"] + "PLL[PRQ]EN": + Disabled: [0, PLLCLK output disabled] + Enabled: [1, PLLCLK output enabled] + PLLP: + Div2: [1, "PLL = VCO/(N+1)"] + Div3: [2, "PLL = VCO/(N+1)"] + Div4: [3, "PLL = VCO/(N+1)"] + Div5: [4, "PLL = VCO/(N+1)"] + Div6: [5, "PLL = VCO/(N+1)"] + Div7: [6, "PLL = VCO/(N+1)"] + Div8: [7, "PLL = VCO/(N+1)"] + Div9: [8, "PLL = VCO/(N+1)"] + Div10: [9, "PLL = VCO/(N+1)"] + Div11: [10, "PLL = VCO/(N+1)"] + Div12: [11, "PLL = VCO/(N+1)"] + Div13: [12, "PLL = VCO/(N+1)"] + Div14: [13, "PLL = VCO/(N+1)"] + Div15: [14, "PLL = VCO/(N+1)"] + Div16: [15, "PLL = VCO/(N+1)"] + Div17: [16, "PLL = VCO/(N+1)"] + Div18: [17, "PLL = VCO/(N+1)"] + Div19: [18, "PLL = VCO/(N+1)"] + Div20: [19, "PLL = VCO/(N+1)"] + Div21: [20, "PLL = VCO/(N+1)"] + Div22: [21, "PLL = VCO/(N+1)"] + Div23: [22, "PLL = VCO/(N+1)"] + Div24: [23, "PLL = VCO/(N+1)"] + Div25: [24, "PLL = VCO/(N+1)"] + Div26: [25, "PLL = VCO/(N+1)"] + Div27: [26, "PLL = VCO/(N+1)"] + Div28: [27, "PLL = VCO/(N+1)"] + Div29: [28, "PLL = VCO/(N+1)"] + Div30: [29, "PLL = VCO/(N+1)"] + Div31: [30, "PLL = VCO/(N+1)"] + Div32: [31, "PLL = VCO/(N+1)"] + PLLN: [6, 127] + PLLM: + Div1: [0, "VCO input = PLL input / PLLM"] + Div2: [1, "VCO input = PLL input / PLLM"] + Div3: [2, "VCO input = PLL input / PLLM"] + Div4: [3, "VCO input = PLL input / PLLM"] + Div5: [4, "VCO input = PLL input / PLLM"] + Div6: [5, "VCO input = PLL input / PLLM"] + Div7: [6, "VCO input = PLL input / PLLM"] + Div8: [7, "VCO input = PLL input / PLLM"] + PLLSRC: + NoClock: [0, No clock sent to PLL] + MSI: [1, MSI clock selected as PLL clock entry] + HSI16: [2, HSI16 clock selected as PLL clock entry] + HSE32: [3, HSE32 clock selected as PLL clock entry] + +CIER: + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + +CIFR: + "*F": + NotInterrupted: [0, Not interrupted] + Interrupted: [1, Interrupted] + +CICR: + "*C": + Clear: [1, Clear interrupt flag] + +"AHB[123]RSTR": + "*": + NoReset: [0, No effect] + Reset: [1, Reset peripheral] + +"APB[123]RSTR?": + "*": + NoReset: [0, No effect] + Reset: [1, Reset peripheral] + +"A[PH]B[123]ENR": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +"APB[123]ENR?": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +"A[PH]B[123]SMENR?": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +CCIPR: + RNGSEL: + PLLQ: [0, PLLQ clock selected] + LSI: [1, LSI clock selected] + LSE: [2, LSE clock selected] + MSI: [3, MSI clock selected] + ADCSEL: + NoClock: [0, No clock selected] + HSI16: [1, HSI16 clock selected] + PLLP: [2, PLLP clock selected] + SYSCLK: [3, SYSCLK clock selected] + "LPTIM[123]SEL": + PCLK: [0, PCLK clock selected] + LSI: [1, LSI clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + "I2C[123]SEL": + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LPUART1SEL: + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + SPI2S2SEL: + PLLQ: [1, PLLQ clock selected] + HSI16: [2, HSI16 clock selected] + I2S: [3, External input I2S_CKIN selected] + "USART[12]SEL": + PCLK: [0, PCLK clock selected] + SYSCLK: [1, SYSCLK clock selected] + HSI16: [2, HSI16 clock selected] + LSE: [3, LSE clock selected] + +BDCR: + LSCOSEL: + LSI: [0, LSI clock selected] + LSE: [1, LSE clock selected] + LSCOEN: + Disabled: [0, LSCO disabled] + Enabled: [1, LSCO enabled] + BDRST: + NotActive: [0, Reset not activated] + Reset: [1, Entire Backup domain reset] + RTCEN: + Disabled: [0, RTC kernel clock disabled] + Enabled: [1, RTC kernel clock enabled] + LSESYSRDY: + NotReady: [0, LSE system clock not ready] + Ready: [1, LSE system clock ready] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock selected] + LSI: [2, LSI oscillator clock selected] + HSE32: [3, HSE32 oscillator clock divided by 32 selected] + LSESYSEN: + Disabled: [0, "LSE system clock disabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode"] + Enabled: [1, "LSE system clock enabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode"] + LSECSSD: + NoFailure: [0, No failure detected on LSE] + Failure: [1, Failure detected on LSE] + LSECSSON: + Disabled: [0, CSS on LSE disabled] + Enabled: [1, CSS on LSE enabled] + LSEDRV: + Low: [0, Xtal mode lower driving capability] + MedLow: [1, Xtal mode medium-low driving capability] + MedHigh: [2, Xtal mode medium-high driving capability] + High: [3, Xtal mode higher driving capability] + LSEBYP: + Disabled: [0, LSE oscillator not bypassed] + Enabled: [1, LSE oscillator bypassed] + LSERDY: + NotReady: [0, LSE oscillator not ready] + Ready: [1, LSE oscillator ready] + LSEON: + "Off": [0, LSE oscillator off] + "On": [1, LSE oscillator on] + +CSR: + LPWRRSTF,WWDGRSTF,IWDGRSTF,SFTRSTF,BORRSTF,PINRSTF,OBLRSTF: + NoReset: [0, No reset occurred] + Reset: [1, Reset occurred] + RFILARSTF: + NoIllegalCommand: [0, No SUBGHZ radio illegal command occurred] + IllegalCommand: [1, SUBGHZ radio illegal command occurred] + RMVF: + NoEffect: [0, No effect] + Clear: [1, Reset flags reset] + RFRST: + Removed: [0, Sub-GHz radio software reset removed] + Reset: [1, Sub-GHz radio software reset active] + RFRSTF: + NoReset: [0, Sub-GHz radio out of reset] + Reset: [1, Sub-GHz radio in reset] + MSISRANGE: + f_1MHz: [0b0100, Range 4 around 1 MHz] + f_2MHz: [0b0101, Range 5 around 2 MHz] + f_4MHz: [0b0110, Range 6 around 4 MHz (reset value)] + f_8MHz: [0b0111, Range 7 around 8 MHz] + LSIPRE: + Div1: [0, LSI clock not divided] + Div128: [1, LSI clock divided by 128] + LSIRDY: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSION: + "Off": [0, LSI oscillator off] + "On": [1, LSI oscillator on] + +EXTCFGR: + SHDHPREF: + NotApplied: [0, HCLK3 prescaler value not yet applied] + Applied: [1, HCLK3 prescaler value applied] + SHDHPRE: + Div1: [-1, SYSCLK not divided] + Div3: [0b0001, SYSCLK divided by 3] + Div5: [0b0010, SYSCLK divided by 5] + Div6: [0b0101, SYSCLK divided by 6] + Div10: [0b0110, SYSCLK divided by 10] + Div32: [0b0111, SYSCLK divided by 32] + Div2: [0b1000, SYSCLK divided by 2] + Div4: [0b1001, SYSCLK divided by 4] + Div8: [0b1010, SYSCLK divided by 8] + Div16: [0b1011, SYSCLK divided by 16] + Div64: [0b1100, SYSCLK divided by 64] + Div128: [0b1101, SYSCLK divided by 128] + Div256: [0b1110, SYSCLK divided by 256] + Div512: [0b1111, SYSCLK divided by 512] diff --git a/devices/fields/rcc/rcc_wx_c2.yaml b/devices/fields/rcc/rcc_wx_c2.yaml new file mode 100644 index 000000000..20e605eb7 --- /dev/null +++ b/devices/fields/rcc/rcc_wx_c2.yaml @@ -0,0 +1,19 @@ +"C2A[PH]B[123]ENR": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +"C2APB[123]ENR?": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +"C2A[PH]B[123]SMENR": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] + +"C2A[PH]B[123]SMENR?": + "*": + Disabled: [0, Clock disabled] + Enabled: [1, Clock enabled] diff --git a/devices/fields/rcc/v2/bdcr_lsedrv.yaml b/devices/fields/rcc/v2/bdcr_lsedrv.yaml new file mode 100644 index 000000000..bffb1145d --- /dev/null +++ b/devices/fields/rcc/v2/bdcr_lsedrv.yaml @@ -0,0 +1,6 @@ +BDCR: + LSEDRV: + Low: [0, Low drive capacity] + MediumHigh: [1, Medium-high drive capacity] + MediumLow: [2, Medium-low drive capacity] + High: [3, High drive capacity] diff --git a/devices/fields/rcc/v2/bdcr_lsemod.yaml b/devices/fields/rcc/v2/bdcr_lsemod.yaml new file mode 100644 index 000000000..d5fa141e5 --- /dev/null +++ b/devices/fields/rcc/v2/bdcr_lsemod.yaml @@ -0,0 +1,4 @@ +BDCR: + LSEMOD: + Low: [0, LSE oscillator low power mode selection] + High: [1, LSE oscillator high drive mode selection] diff --git a/devices/fields/rcc/v2/cfgr_mcoen.yaml b/devices/fields/rcc/v2/cfgr_mcoen.yaml new file mode 100644 index 000000000..8f6a982b7 --- /dev/null +++ b/devices/fields/rcc/v2/cfgr_mcoen.yaml @@ -0,0 +1,4 @@ +CFGR: + MCO?EN: + Disabled: [0, MCO output disabled] + Enabled: [1, MCO output enabled] diff --git a/devices/fields/rcc/v2/ckgatenr.yaml b/devices/fields/rcc/v2/ckgatenr.yaml new file mode 100644 index 000000000..8722fc07b --- /dev/null +++ b/devices/fields/rcc/v2/ckgatenr.yaml @@ -0,0 +1,4 @@ +CKGATENR: + "*_CKEN": + Enabled: [0, The clock gating is enabled] + Disabled: [1, "The clock gating is disabled, the clock is always enabled"] diff --git a/devices/fields/rcc/v2/common.yaml b/devices/fields/rcc/v2/common.yaml new file mode 100644 index 000000000..b28f7b923 --- /dev/null +++ b/devices/fields/rcc/v2/common.yaml @@ -0,0 +1,58 @@ +# Applicable at least to STM32F4 and STM32F7. + +_include: + - ../rcc_common.yaml + +PLLCFGR: + _merge: [PLLM*, PLLN*, PLLP*, PLLQ*] + PLLSRC: + HSI: [0, HSI clock selected as PLL and PLLI2S clock entry] + HSE: [1, HSE oscillator clock selected as PLL and PLLI2S clock entry] + PLLQ: [2, 15] + PLLP: + Div2: [0, "PLLP=2"] + Div4: [1, "PLLP=4"] + Div6: [2, "PLLP=6"] + Div8: [3, "PLLP=8"] + PLLN: [50, 432] + PLLM: [2, 63] +CFGR: + SWS: + _read: + HSI: [0, HSI oscillator used as system clock] + HSE: [1, HSE oscillator used as system clock] + PLL: [2, PLL used as system clock] + SW: + HSI: [0, HSI selected as system clock] + HSE: [1, HSE selected as system clock] + PLL: [2, PLL selected as system clock] + MCO2: + SYSCLK: [0, System clock (SYSCLK) selected] + PLLI2S: [1, PLLI2S clock selected] + HSE: [2, HSE oscillator clock selected] + PLL: [3, PLL clock selected] + MCO?PRE: + Div1: [-1, No division] + Div2: [4, Division by 2] + Div3: [5, Division by 3] + Div4: [6, Division by 4] + Div5: [7, Division by 5] + MCO1: + HSI: [0, HSI clock selected] + LSE: [1, LSE oscillator selected] + HSE: [2, HSE oscillator clock selected] + PLL: [3, PLL clock selected] + RTCPRE: [0, 31] +A?B?LPENR: + "*LPEN": + DisabledInSleep: [0, Selected module is disabled during Sleep mode] + EnabledInSleep: [1, Selected module is enabled during Sleep mode] +SSCGR: + SSCGEN: + Disabled: [0, Spread spectrum modulation disabled] + Enabled: [1, Spread spectrum modulation enabled] + SPREADSEL: + Center: [0, Center spread] + Down: [1, Down spread] + INCSTEP: [0, 32767] + MODPER: [0, 8191] diff --git a/devices/fields/rcc/v2/dckcfgr2_48m_sd.yaml b/devices/fields/rcc/v2/dckcfgr2_48m_sd.yaml new file mode 100644 index 000000000..72de93db9 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr2_48m_sd.yaml @@ -0,0 +1,7 @@ +DCKCFGR2: + CK48MSEL: + PLL: [0, 48MHz clock from PLL is selected] + PLLSAI: [1, 48MHz clock from PLLSAI is selected] + SDMMC?SEL,SDIOSEL: + CK48M: [0, 48 MHz clock is selected as SD clock] + SYSCLK: [1, System clock is selected as SD clock] diff --git a/devices/fields/rcc/v2/dckcfgr2_cecsel.yaml b/devices/fields/rcc/v2/dckcfgr2_cecsel.yaml new file mode 100644 index 000000000..48e74efc8 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr2_cecsel.yaml @@ -0,0 +1,4 @@ +DCKCFGR2: + CECSEL: + LSE: [0, LSE clock is selected as HDMI-CEC clock] + HSI_Div488: [1, HSI divided by 488 clock is selected as HDMI-CEC clock] diff --git a/devices/fields/rcc/v2/dckcfgr2_i2csel.yaml b/devices/fields/rcc/v2/dckcfgr2_i2csel.yaml new file mode 100644 index 000000000..6b4f5f090 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr2_i2csel.yaml @@ -0,0 +1,5 @@ +DCKCFGR2: + "*I2C?SEL": + APB: [0, APB clock selected as I2C clock] + SYSCLK: [1, System clock selected as I2C clock] + HSI: [2, HSI clock selected as I2C clock] diff --git a/devices/fields/rcc/v2/dckcfgr2_lptimsel.yaml b/devices/fields/rcc/v2/dckcfgr2_lptimsel.yaml new file mode 100644 index 000000000..694295171 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr2_lptimsel.yaml @@ -0,0 +1,6 @@ +DCKCFGR2: + LPTIM1SEL: + APB1: [0, APB1 clock (PCLK1) selected as LPTILM1 clock] + LSI: [1, LSI clock is selected as LPTILM1 clock] + HSI: [2, HSI clock is selected as LPTILM1 clock] + LSE: [3, LSE clock is selected as LPTILM1 clock] diff --git a/devices/fields/rcc/v2/dckcfgr2_spdifrxsel.yaml b/devices/fields/rcc/v2/dckcfgr2_spdifrxsel.yaml new file mode 100644 index 000000000..6b757438d --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr2_spdifrxsel.yaml @@ -0,0 +1,4 @@ +DCKCFGR2: + SPDIFRXSEL: + PLL: [0, SPDIF-Rx clock from PLL is selected] + PLLI2S: [1, SPDIF-Rx clock from PLLI2S is selected] diff --git a/devices/fields/rcc/v2/dckcfgr2_usartsel.yaml b/devices/fields/rcc/v2/dckcfgr2_usartsel.yaml new file mode 100644 index 000000000..c15d08c24 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr2_usartsel.yaml @@ -0,0 +1,11 @@ +DCKCFGR2: + USART2SEL,USART3SEL,UART4SEL,UART5SEL,UART7SEL,UART8SEL: + APB1: [0, APB1 clock (PCLK1) is selected as USART clock] + SYSCLK: [1, System clock is selected as USART clock] + HSI: [2, HSI clock is selected as USART clock] + LSE: [3, LSE clock is selected as USART clock] + USART1SEL,USART6SEL: + APB2: [0, APB2 clock (PCLK2) is selected as USART clock] + SYSCLK: [1, System clock is selected as USART clock] + HSI: [2, HSI clock is selected as USART clock] + LSE: [3, LSE clock is selected as USART clock] diff --git a/devices/fields/rcc/v2/dckcfgr_48m_sd.yaml b/devices/fields/rcc/v2/dckcfgr_48m_sd.yaml new file mode 100644 index 000000000..d040d4971 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_48m_sd.yaml @@ -0,0 +1,7 @@ +DCKCFGR: + CK48MSEL: + PLL: [0, 48MHz clock from PLL is selected] + PLLSAI: [1, 48MHz clock from PLLSAI is selected] + SDIOSEL: + CK48M: [0, 48 MHz clock is selected as SD clock] + SYSCLK: [1, System clock is selected as SD clock] diff --git a/devices/fields/rcc/v2/dckcfgr_dfsdm_f4.yaml b/devices/fields/rcc/v2/dckcfgr_dfsdm_f4.yaml new file mode 100644 index 000000000..4f0d3f61e --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_dfsdm_f4.yaml @@ -0,0 +1,7 @@ +DCKCFGR: + CKDFSDM?ASEL: + I2S1: [0, CK_I2S_APB1 selected as audio clock] + I2S2: [1, CK_I2S_APB2 selected as audio clock] + CKDFSDM1SEL: + APB2: [0, APB2 clock used as Kernel clock] + SYSCLK: [1, System clock used as Kernel clock] diff --git a/devices/fields/rcc/v2/dckcfgr_dfsdm_f7.yaml b/devices/fields/rcc/v2/dckcfgr_dfsdm_f7.yaml new file mode 100644 index 000000000..ab18841b4 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_dfsdm_f7.yaml @@ -0,0 +1,7 @@ +DCKCFGR1: + DFSDM1SEL: + APB2: [0, APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source] + SYSCLK: [1, System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source] + ADFSDM1SEL: + SAI1: [0, SAI1 clock selected as DFSDM1 Audio clock source] + SAI2: [1, SAI2 clock selected as DFSDM1 Audio clock source] diff --git a/devices/fields/rcc/v2/dckcfgr_dsisel.yaml b/devices/fields/rcc/v2/dckcfgr_dsisel.yaml new file mode 100644 index 000000000..fd7167745 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_dsisel.yaml @@ -0,0 +1,4 @@ +DCKCFGR,DCKCFGR2: + DSISEL: + DSI_PHY: [0, DSI-PHY used as DSI byte lane clock source (usual case)] + PLLR: [1, "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)"] diff --git a/devices/fields/rcc/v2/dckcfgr_i2s12src.yaml b/devices/fields/rcc/v2/dckcfgr_i2s12src.yaml new file mode 100644 index 000000000..930b22de2 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_i2s12src.yaml @@ -0,0 +1,6 @@ +DCKCFGR: + I2S?SRC: + PLLI2SR: [0, "I2Sx clock frequency = f(PLLI2S_R)"] + I2S_CKIN: [1, "I2Sx clock frequency = I2S_CKIN Alternate function input frequency"] + PLLR: [2, "I2Sx clock frequency = f(PLL_R)"] + HSI_HSE: [3, "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])"] diff --git a/devices/fields/rcc/v2/dckcfgr_i2s_sai_common.yaml b/devices/fields/rcc/v2/dckcfgr_i2s_sai_common.yaml new file mode 100644 index 000000000..9764a4a36 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_i2s_sai_common.yaml @@ -0,0 +1,67 @@ +DCKCFGR,DCKCFGR1: + PLLI2SDIVQ,PLLI2SDIVR: + Div1: [0, "PLLI2SDIVQ = /1"] + Div2: [1, "PLLI2SDIVQ = /2"] + Div3: [2, "PLLI2SDIVQ = /3"] + Div4: [3, "PLLI2SDIVQ = /4"] + Div5: [4, "PLLI2SDIVQ = /5"] + Div6: [5, "PLLI2SDIVQ = /6"] + Div7: [6, "PLLI2SDIVQ = /7"] + Div8: [7, "PLLI2SDIVQ = /8"] + Div9: [8, "PLLI2SDIVQ = /9"] + Div10: [9, "PLLI2SDIVQ = /10"] + Div11: [10, "PLLI2SDIVQ = /11"] + Div12: [11, "PLLI2SDIVQ = /12"] + Div13: [12, "PLLI2SDIVQ = /13"] + Div14: [13, "PLLI2SDIVQ = /14"] + Div15: [14, "PLLI2SDIVQ = /15"] + Div16: [15, "PLLI2SDIVQ = /16"] + Div17: [16, "PLLI2SDIVQ = /17"] + Div18: [17, "PLLI2SDIVQ = /18"] + Div19: [18, "PLLI2SDIVQ = /19"] + Div20: [19, "PLLI2SDIVQ = /20"] + Div21: [20, "PLLI2SDIVQ = /21"] + Div22: [21, "PLLI2SDIVQ = /22"] + Div23: [22, "PLLI2SDIVQ = /23"] + Div24: [23, "PLLI2SDIVQ = /24"] + Div25: [24, "PLLI2SDIVQ = /25"] + Div26: [25, "PLLI2SDIVQ = /26"] + Div27: [26, "PLLI2SDIVQ = /27"] + Div28: [27, "PLLI2SDIVQ = /28"] + Div29: [28, "PLLI2SDIVQ = /29"] + Div30: [29, "PLLI2SDIVQ = /30"] + Div31: [30, "PLLI2SDIVQ = /31"] + Div32: [31, "PLLI2SDIVQ = /32"] + PLLSAIDIVQ,PLLDIVR: + Div1: [0, "PLLSAIDIVQ = /1"] + Div2: [1, "PLLSAIDIVQ = /2"] + Div3: [2, "PLLSAIDIVQ = /3"] + Div4: [3, "PLLSAIDIVQ = /4"] + Div5: [4, "PLLSAIDIVQ = /5"] + Div6: [5, "PLLSAIDIVQ = /6"] + Div7: [6, "PLLSAIDIVQ = /7"] + Div8: [7, "PLLSAIDIVQ = /8"] + Div9: [8, "PLLSAIDIVQ = /9"] + Div10: [9, "PLLSAIDIVQ = /10"] + Div11: [10, "PLLSAIDIVQ = /11"] + Div12: [11, "PLLSAIDIVQ = /12"] + Div13: [12, "PLLSAIDIVQ = /13"] + Div14: [13, "PLLSAIDIVQ = /14"] + Div15: [14, "PLLSAIDIVQ = /15"] + Div16: [15, "PLLSAIDIVQ = /16"] + Div17: [16, "PLLSAIDIVQ = /17"] + Div18: [17, "PLLSAIDIVQ = /18"] + Div19: [18, "PLLSAIDIVQ = /19"] + Div20: [19, "PLLSAIDIVQ = /20"] + Div21: [20, "PLLSAIDIVQ = /21"] + Div22: [21, "PLLSAIDIVQ = /22"] + Div23: [22, "PLLSAIDIVQ = /23"] + Div24: [23, "PLLSAIDIVQ = /24"] + Div25: [24, "PLLSAIDIVQ = /25"] + Div26: [25, "PLLSAIDIVQ = /26"] + Div27: [26, "PLLSAIDIVQ = /27"] + Div28: [27, "PLLSAIDIVQ = /28"] + Div29: [28, "PLLSAIDIVQ = /29"] + Div30: [29, "PLLSAIDIVQ = /30"] + Div31: [30, "PLLSAIDIVQ = /31"] + Div32: [31, "PLLSAIDIVQ = /32"] diff --git a/devices/fields/rcc/v2/dckcfgr_i2s_sai_f4.yaml b/devices/fields/rcc/v2/dckcfgr_i2s_sai_f4.yaml new file mode 100644 index 000000000..8aea0c271 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_i2s_sai_f4.yaml @@ -0,0 +1,12 @@ +_include: + - dckcfgr_i2s_sai_common.yaml + +DCKCFGR: + SAI1ASRC: + PLLSAI: [0, "SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] + PLLI2S: [1, "SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] + I2S_CKIN: [2, "SAI1-A clock frequency = Alternate function input frequency"] + SAI1BSRC: + PLLSAI: [0, "SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] + PLLI2S: [1, "SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] + I2S_CKIN: [2, "SAI1-B clock frequency = Alternate function input frequency"] diff --git a/devices/fields/rcc/v2/dckcfgr_i2s_sai_f446.yaml b/devices/fields/rcc/v2/dckcfgr_i2s_sai_f446.yaml new file mode 100644 index 000000000..986a72fd8 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_i2s_sai_f446.yaml @@ -0,0 +1,14 @@ +_include: + - dckcfgr_i2s_sai_common.yaml + +DCKCFGR: + SAI1SRC: + PLLSAI: [0, "SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] + PLLI2S: [1, "SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] + PLLR: [2, "SAI1 clock frequency = f(PLL_R)"] + I2S_CKIN: [3, I2S_CKIN Alternate function input frequency] + SAI2SRC: + PLLSAI: [0, "SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] + PLLI2S: [1, "SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] + PLLR: [2, "SAI2 clock frequency = f(PLL_R)"] + HSI_HSE: [3, "SAI2 clock frequency = Alternate function input frequency"] diff --git a/devices/fields/rcc/v2/dckcfgr_i2s_sai_f7.yaml b/devices/fields/rcc/v2/dckcfgr_i2s_sai_f7.yaml new file mode 100644 index 000000000..db9238192 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_i2s_sai_f7.yaml @@ -0,0 +1,14 @@ +_include: + - dckcfgr_i2s_sai_common.yaml + +DCKCFGR1: + SAI1SEL: + PLLSAI: [0, "SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] + PLLI2S: [1, "SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] + AFIF: [2, "SAI1 clock frequency = Alternate function input frequency"] + HSI_HSE: [3, "SAI1 clock frequency = HSI or HSE"] + SAI2SEL: + PLLSAI: [0, "SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] + PLLI2S: [1, "SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] + AFIF: [2, "SAI2 clock frequency = Alternate function input frequency"] + HSI_HSE: [3, "SAI2 clock frequency = HSI or HSE"] diff --git a/devices/fields/rcc/v2/dckcfgr_i2ssrc.yaml b/devices/fields/rcc/v2/dckcfgr_i2ssrc.yaml new file mode 100644 index 000000000..9d72e44f5 --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_i2ssrc.yaml @@ -0,0 +1,5 @@ +DCKCFGR: + I2SSRC: + PLLCLKR: [0, "I2Sx clock frequency = f(PLLCLK_R)"] + I2S_CKIN: [1, "I2Sx clock frequency = I2S_CKIN Alternate function input frequency"] + HSI_HSE: [3, "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])"] diff --git a/devices/fields/rcc/v2/dckcfgr_saidivr.yaml b/devices/fields/rcc/v2/dckcfgr_saidivr.yaml new file mode 100644 index 000000000..68b3a652f --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_saidivr.yaml @@ -0,0 +1,6 @@ +DCKCFGR,DCKCFGR1: + PLLSAIDIVR: + Div2: [0, "PLLSAIDIVR = /2"] + Div4: [1, "PLLSAIDIVR = /4"] + Div8: [2, "PLLSAIDIVR = /8"] + Div16: [3, "PLLSAIDIVR = /16"] diff --git a/devices/fields/rcc/v2/dckcfgr_timpre.yaml b/devices/fields/rcc/v2/dckcfgr_timpre.yaml new file mode 100644 index 000000000..d1f643cea --- /dev/null +++ b/devices/fields/rcc/v2/dckcfgr_timpre.yaml @@ -0,0 +1,4 @@ +DCKCFGR,DCKCFGR1: + TIMPRE: + Mul1Or2: [0, "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx"] + Mul1Or4: [1, "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx"] diff --git a/devices/fields/rcc/v2/f7.yaml b/devices/fields/rcc/v2/f7.yaml new file mode 100644 index 000000000..9a9f6f506 --- /dev/null +++ b/devices/fields/rcc/v2/f7.yaml @@ -0,0 +1,20 @@ +_include: + - common.yaml + - i2s.yaml + - i2s_pll.yaml + - i2s_pllq.yaml + - sai_pllp.yaml + - bdcr_lsedrv.yaml + - dckcfgr_timpre.yaml + - dckcfgr_i2s_sai_f7.yaml + - dckcfgr2_48m_sd.yaml + - dckcfgr2_lptimsel.yaml + - dckcfgr2_i2csel.yaml + - dckcfgr2_usartsel.yaml + +APB1RSTR: + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST diff --git a/devices/fields/rcc/v2/i2s.yaml b/devices/fields/rcc/v2/i2s.yaml new file mode 100644 index 000000000..d4b57d1ca --- /dev/null +++ b/devices/fields/rcc/v2/i2s.yaml @@ -0,0 +1,6 @@ +# Applicable at least to some STM32F4 and STM32F7. + +CFGR: + I2SSRC: + PLLI2S: [0, PLLI2S clock used as I2S clock source] + CKIN: [1, External clock mapped on the I2S_CKIN pin used as I2S clock source] diff --git a/devices/fields/rcc/v2/i2s_pll.yaml b/devices/fields/rcc/v2/i2s_pll.yaml new file mode 100644 index 000000000..5ece1cf7f --- /dev/null +++ b/devices/fields/rcc/v2/i2s_pll.yaml @@ -0,0 +1,6 @@ +# Applicable at least to some STM32F4 and STM32F7. + +PLLI2SCFGR: + PLL*R: [2, 7] +PLLI2SCFGR,PLLSAICFGR: + PLL*N: [50, 432] diff --git a/devices/fields/rcc/v2/i2s_pllm.yaml b/devices/fields/rcc/v2/i2s_pllm.yaml new file mode 100644 index 000000000..b98f33a9e --- /dev/null +++ b/devices/fields/rcc/v2/i2s_pllm.yaml @@ -0,0 +1,4 @@ +# Applicable at least to some STM32F4 and STM32F7. + +PLLI2SCFGR,PLLSAICFGR: + PLL*M: [2, 63] diff --git a/devices/fields/rcc/v2/i2s_pllp.yaml b/devices/fields/rcc/v2/i2s_pllp.yaml new file mode 100644 index 000000000..1156067f8 --- /dev/null +++ b/devices/fields/rcc/v2/i2s_pllp.yaml @@ -0,0 +1,6 @@ +PLLI2SCFGR: + PLL*P: + Div2: [0, "PLL*P=2"] + Div4: [1, "PLL*P=4"] + Div6: [2, "PLL*P=6"] + Div8: [3, "PLL*P=8"] diff --git a/devices/fields/rcc/v2/i2s_pllq.yaml b/devices/fields/rcc/v2/i2s_pllq.yaml new file mode 100644 index 000000000..c29918ae6 --- /dev/null +++ b/devices/fields/rcc/v2/i2s_pllq.yaml @@ -0,0 +1,4 @@ +# Applicable at least to some STM32F4 and STM32F7. + +PLLI2SCFGR,PLLSAICFGR: + PLL*Q: [2, 15] diff --git a/devices/fields/rcc/v2/i2s_pllsrc.yaml b/devices/fields/rcc/v2/i2s_pllsrc.yaml new file mode 100644 index 000000000..4064c5496 --- /dev/null +++ b/devices/fields/rcc/v2/i2s_pllsrc.yaml @@ -0,0 +1,6 @@ +# Applicable at least to some STM32F4 + +PLLI2SCFGR: + PLLI2SSRC: + HSE_HSI: [0, HSE or HSI depending on PLLSRC of PLLCFGR] + External: [1, External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry] diff --git a/devices/fields/rcc/v2/pllcfgr_pllr.yaml b/devices/fields/rcc/v2/pllcfgr_pllr.yaml new file mode 100644 index 000000000..a1e3163b0 --- /dev/null +++ b/devices/fields/rcc/v2/pllcfgr_pllr.yaml @@ -0,0 +1,2 @@ +PLLCFGR: + PLLR: [2, 7] diff --git a/devices/fields/rcc/v2/sai_pllp.yaml b/devices/fields/rcc/v2/sai_pllp.yaml new file mode 100644 index 000000000..d964e12a0 --- /dev/null +++ b/devices/fields/rcc/v2/sai_pllp.yaml @@ -0,0 +1,6 @@ +PLLSAICFGR: + PLL*P: + Div2: [0, "PLL*P=2"] + Div4: [1, "PLL*P=4"] + Div6: [2, "PLL*P=6"] + Div8: [3, "PLL*P=8"] diff --git a/devices/fields/rcc/v2/sai_pllr.yaml b/devices/fields/rcc/v2/sai_pllr.yaml new file mode 100644 index 000000000..8fa07396f --- /dev/null +++ b/devices/fields/rcc/v2/sai_pllr.yaml @@ -0,0 +1,4 @@ +# Applicable at least to some STM32F4 and STM32F7. + +PLLSAICFGR: + PLL*R: [2, 7] diff --git a/devices/fields/rcc/v3/bdcr_ext.yaml b/devices/fields/rcc/v3/bdcr_ext.yaml new file mode 100644 index 000000000..0c1c13b8f --- /dev/null +++ b/devices/fields/rcc/v3/bdcr_ext.yaml @@ -0,0 +1,16 @@ +# Should be applied on top of v3/common.yaml + +BDCR: + LSIRDY: + _read: + NotReady: [0, Clock not ready] + Ready: [1, Clock ready] + LSION: + Disabled: [0, Oscillator disabled] + Enabled: [1, Oscillator enabled] + LSCOSEL: + LSI: [0, LSI clock selected] + LSE: [1, LSE clock selected] + LSEEXT: + Analog: [0, HSE in analog mode] + Digital: [1, HSE in digital mode] diff --git a/devices/fields/rcc/v3/cfgr.yaml b/devices/fields/rcc/v3/cfgr.yaml new file mode 100644 index 000000000..4a84faaa6 --- /dev/null +++ b/devices/fields/rcc/v3/cfgr.yaml @@ -0,0 +1,33 @@ +CFGR: + MCO2: + SYSCLK: [0, System clock selected for micro-controller clock output] + PLL2_P: [1, pll2_p selected for micro-controller clock output] + HSE: [2, HSE selected for micro-controller clock output] + PLL1_P: [3, pll1_p selected for micro-controller clock output] + CSI: [4, CSI selected for micro-controller clock output] + LSI: [5, LSI selected for micro-controller clock output] + MCO1: + HSI: [0, HSI selected for micro-controller clock output] + LSE: [1, LSE selected for micro-controller clock output] + HSE: [2, HSE selected for micro-controller clock output] + PLL1_Q: [3, pll1_q selected for micro-controller clock output] + HSI48: [4, HSI48 selected for micro-controller clock output] + MCO?PRE: [0, 15] + TIMPRE: + DefaultX2: [0, Timer kernel clock equal to 2x pclk by default] + DefaultX4: [1, Timer kernel clock equal to 4x pclk by default] + RTCPRE: [0, 63] + STOPWUCK,STOPKERWUCK: + HSI: [0, HSI selected as wake up clock from system Stop] + CSI: [1, CSI selected as wake up clock from system Stop] + SWS: + _read: + HSI: [0, HSI oscillator used as system clock] + CSI: [1, CSI oscillator used as system clock] + HSE: [2, HSE oscillator used as system clock] + PLL1: [3, PLL1 used as system clock] + SW: + HSI: [0, HSI selected as system clock] + CSI: [1, CSI selected as system clock] + HSE: [2, HSE selected as system clock] + PLL1: [3, PLL1 selected as system clock] diff --git a/devices/fields/rcc/v3/cfgr1_cfgr2.yaml b/devices/fields/rcc/v3/cfgr1_cfgr2.yaml new file mode 100644 index 000000000..24bf8a6f1 --- /dev/null +++ b/devices/fields/rcc/v3/cfgr1_cfgr2.yaml @@ -0,0 +1,53 @@ +CFGR1: + MCO2SEL: + SYSCLK: [0, System clock selected (sys_ck)] + PLL2_P: [1, PLL2 oscillator clock selected (pll2_p_ck)] + HSE: [2, HSE clock selected (hse_ck)] + PLL1_P: [3, PLL1 clock selected (pll1_p_ck)] + CSI: [4, CSI clock selected (csi_ck)] + LSI: [5, LSI clock selected (lsi_ck)] + MCO1SEL: + HSI: [0, HSI clock selected (hsi_ck)] + LSE: [1, LSE clock selected (lse_ck)] + HSE: [2, HSE clock selected (hse_ck)] + PLL1_Q: [3, PLL1 clock selected (pll1_q_ck)] + HSI48: [4, HSI48 clock selected (hsi48_ck)] + MCO?PRE: [0, 15] + TIMPRE: + DefaultX2: [0, Timer kernel clock equal to 2x pclk by default] + DefaultX4: [1, Timer kernel clock equal to 4x pclk by default] + RTCPRE: [0, 63] + STOPWUCK,STOPKERWUCK: + HSI: [0, HSI selected as wake up clock from system Stop] + CSI: [1, CSI selected as wake up clock from system Stop] + SWS: + _read: + HSI: [0, HSI oscillator used as system clock] + CSI: [1, CSI oscillator used as system clock] + HSE: [2, HSE oscillator used as system clock] + PLL1: [3, PLL1 used as system clock] + SW: + HSI: [0, HSI selected as system clock] + CSI: [1, CSI selected as system clock] + HSE: [2, HSE selected as system clock] + PLL1: [3, PLL1 selected as system clock] +CFGR2: + A?B?DIS: + Enabled: [0, The selected clock is enabled] + Disabled: [1, The selected clock is disabled] + PPRE*: + Div1: [-1, HCLK not divided] + Div2: [4, HCLK divided by 2] + Div4: [5, HCLK divided by 4] + Div8: [6, HCLK divided by 8] + Div16: [7, HCLK divided by 16] + HPRE: + Div1: [-1, SYSCLK not divided] + Div2: [8, SYSCLK divided by 2] + Div4: [9, SYSCLK divided by 4] + Div8: [10, SYSCLK divided by 8] + Div16: [11, SYSCLK divided by 16] + Div64: [12, SYSCLK divided by 64] + Div128: [13, SYSCLK divided by 128] + Div256: [14, SYSCLK divided by 256] + Div512: [15, SYSCLK divided by 512] diff --git a/devices/fields/rcc/v3/common.yaml b/devices/fields/rcc/v3/common.yaml new file mode 100644 index 000000000..c23101273 --- /dev/null +++ b/devices/fields/rcc/v3/common.yaml @@ -0,0 +1,89 @@ +# Applicable at least to H7 + +# Fresh start - even fields from rcc_common are quite different + +CR: + HSIDIVF: + _read: + NotPropagated: [0, New HSIDIV ratio has not yet propagated to hsi_ck] + Propagated: [1, HSIDIV ratio has propagated to hsi_ck] + HSEBYP: + NotBypassed: [0, HSE crystal oscillator not bypassed] + Bypassed: [1, HSE crystal oscillator bypassed with external clock] + HSIDIV: + Div1: [0, No division] + Div2: [1, Division by 2] + Div4: [2, Division by 4] + Div8: [3, Division by 8] + "*RDY": + _read: + NotReady: [0, Clock not ready] + Ready: [1, Clock ready] + "*ON": + "Off": [0, Clock Off] + "On": [1, Clock On] +CIER: + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] +CIFR: + "*RDYF": + _read: + NotInterrupted: [0, No clock ready interrupt] + Interrupted: [1, Clock ready interrupt] +CICR: + "*C": + Clear: [1, Clear interrupt flag] +BDCR: + BDRST,VSWRST: + NotActivated: [0, Reset not activated] + Reset: [1, Resets the entire VSW domain] + RTCEN: + Disabled: [0, RTC clock disabled] + Enabled: [1, RTC clock enabled] + RTCSEL: + NoClock: [0, No clock] + LSE: [1, LSE oscillator clock used as RTC clock] + LSI: [2, LSI oscillator clock used as RTC clock] + HSE: [3, HSE oscillator clock divided by a prescaler used as RTC clock] + LSECSSD: + _read: + NoFailure: [0, No failure detected on 32 kHz oscillator] + Failure: [1, Failure detected on 32 kHz oscillator] + LSECSSON: + SecurityOff: [0, Clock security system on 32 kHz oscillator off] + SecurityOn: [1, Clock security system on 32 kHz oscillator on] + LSEDRV: + Lowest: [0, Lowest LSE oscillator driving capability] + MediumLow: [1, Medium low LSE oscillator driving capability] + MediumHigh: [2, Medium high LSE oscillator driving capability] + Highest: [3, Highest LSE oscillator driving capability] + LSEBYP: + NotBypassed: [0, LSE crystal oscillator not bypassed] + Bypassed: [1, LSE crystal oscillator bypassed with external clock] + LSERDY: + _read: + NotReady: [0, LSE oscillator not ready] + Ready: [1, LSE oscillator ready] + LSEON: + "Off": [0, LSE oscillator Off] + "On": [1, LSE oscillator On] +"A?B?RSTR,A?B??RSTR": + "*RST": + Reset: [1, Reset the selected module] +RSR,C1_RSR: + "*RSTF": + _read: + NoResetOccurred: [0, No reset occurred for block] + ResetOccurred: [1, Reset occurred for block] + RMVF: + NotActivated: [0, Reset not activated] + Reset: [1, Reset the reset status flags] +"A?B?ENR,A?B??ENR,C1_A?B?ENR,C1_A?B??ENR": + "*EN": + Disabled: [0, The selected clock is disabled] + Enabled: [1, The selected clock is enabled] +"A?B?LPENR,A?B??LPENR,C1_A?B?LPENR,C1_A?B??LPENR": + "*LPEN": + Disabled: [0, The selected clock is disabled during csleep mode] + Enabled: [1, The selected clock is enabled during csleep mode] diff --git a/devices/fields/rcc/v3/cr_hseext.yaml b/devices/fields/rcc/v3/cr_hseext.yaml new file mode 100644 index 000000000..1b7ffdb1a --- /dev/null +++ b/devices/fields/rcc/v3/cr_hseext.yaml @@ -0,0 +1,6 @@ +# Should be applied on top of v3/common.yaml + +CR: + HSEEXT: + Analog: [0, HSE in analog mode] + Digital: [1, HSE in digital mode] diff --git a/devices/fields/rcc/v3/csr.yaml b/devices/fields/rcc/v3/csr.yaml new file mode 100644 index 000000000..ff963d847 --- /dev/null +++ b/devices/fields/rcc/v3/csr.yaml @@ -0,0 +1,10 @@ +# CSR definition for V3. Not available on all devices + +CSR: + LSIRDY: + _read: + NotReady: [0, LSI oscillator not ready] + Ready: [1, LSI oscillator ready] + LSION: + "Off": [0, LSI oscillator Off] + "On": [1, LSI oscillator On] diff --git a/devices/fields/rcc/v3/d3amr_srdamr.yaml b/devices/fields/rcc/v3/d3amr_srdamr.yaml new file mode 100644 index 000000000..e4d15e98b --- /dev/null +++ b/devices/fields/rcc/v3/d3amr_srdamr.yaml @@ -0,0 +1,6 @@ +# Applicable at least to H7 + +D3AMR,SRDAMR: + "*AMEN": + Disabled: [0, Clock disabled in autonomous mode] + Enabled: [1, Clock enabled in autonomous mode] diff --git a/devices/fields/rcc/v3/gsr.yaml b/devices/fields/rcc/v3/gsr.yaml new file mode 100644 index 000000000..75b8ebb8a --- /dev/null +++ b/devices/fields/rcc/v3/gsr.yaml @@ -0,0 +1,6 @@ +# Applicable at least to H7 + +GCR: + WW1RSC: + Clear: [0, Clear WWDG1 scope control] + Set: [1, Set WWDG1 scope control] diff --git a/devices/fields/rcc/v3/h5.yaml b/devices/fields/rcc/v3/h5.yaml new file mode 100644 index 000000000..ee3dcc30b --- /dev/null +++ b/devices/fields/rcc/v3/h5.yaml @@ -0,0 +1,75 @@ +# Common RCC patches for H5 chips +# The H562/3 and H573 chips are typically a superset of H503, so additional fields +# need to be specified for those chips. Some registers (notably CCIPRx) because of +# difference in available clocks between H503 and (H562/3 and H573 family) + +_include: + - common.yaml + - cr_hseext.yaml + - hsicfgr.yaml + - cfgr1_cfgr2.yaml + - bdcr_ext.yaml + +CSICFGR: + CSITRIM: [0, 0x3F] +PLL?CFGR: + PLL??EN: + Disabled: [0, Clock output is disabled] + Enabled: [1, Clock output is enabled] + PLL?M: [0, 0, 0x3F] + PLL?VCOSEL: + WideVCO: [0, VCO frequency range 192 to 836 MHz] + MediumVCO: [1, VCO frequency range 150 to 420 MHz] + PLL?FRACEN: + Reset: [0, Reset latch to transfer FRACN to the Sigma-Delta modulator] + Set: [1, Set latch to transfer FRACN to the Sigma-Delta modulator] + PLL?RGE: + Range1: [0, Frequency is between 1 and 2 MHz] + Range2: [1, Frequency is between 2 and 4 MHz] + Range4: [2, Frequency is between 4 and 8 MHz] + Range8: [3, Frequency is between 8 and 16 MHz] + PLL?SRC: + None: [0, No clock sent to DIVMx dividers and PLLs] + HSI: [1, HSI selected as PLL clock] + CSI: [2, CSI selected as PLL clock] + HSE: [3, HSE selected as PLL clock] +PLL?DIVR: + PLL?[PQR]: [0, 0x7F] + PLL?N: [3, 0x1FF] +PLL?FRACR: + PLL?FRACN: [0, 0x1FFF] +CIFR: + HSECSSF: + _read: + NoInterrupt: [0, No clock security interrupt caused by HSE clock failure] + Interrupt: [1, Clock security interrupt caused by HSE clock failure] +CCIPR1: + TIMICSEL: + Disabled: [0, No internal clock available for timers input capture] + Enabled: [1, "hsi_ker_ck/1024, hsi_ker_ck/8 and csi_ker_ck/128 selected for timers input capture"] +CCIPR4: + SYSTICKSEL: + HCLK_DIV8: [0, RCC HLCK divided by 8 selected as clock source (rcc_hclk / 8)] + LSI_KER: [1, LSI kernel selected as clock source (lsi_ker_ck)] + LSE: [2, LSE selected as clock source (lse_ck)] +CCIPR5: + CKPERSEL: + HSI_KER: [0, HSI kernel clock selected as clock source (hsi_ker_ck)] + CSI_KER: [1, CSI kernel clock selected as clock source (csi_ker_ck)] + HSE: [2, HSE clock selected as clock source (hse_ck)] + FDCANSEL: + HSE: [0, HSE clock selected as clock source (hse_ck)] + PLL1_Q: [1, PLL1 Q clock selected as clock source (pll1_q_ck)] + PLL2_Q: [2, PLL2 Q clock selected as clock source (pll2_q_ck)] + RNGSEL: + HSI48_KER: [0, HSI48 kernel clock selected as clock source (hsi48_ker_ck)] + PLL1_Q: [1, PLL1 Q clock selected as clock source (pll1_q_ck)] + LSE: [2, LSE clock selected as clock source (lse_ck)] + LSI: [3, LSI kernel clock selected as clock source (lsi_ker_ck)] + ADCDACSEL: + HCLK: [0, HLCK clock selected as clock source (rcc_hclk)] + SYS: [1, System clock selected as pclock source (sys_ck)] + PLL2_R: [2, PLL2 R clock selected as clock source (pll2_r_ck)] + HSE: [3, HSE clock selected as clock source (hse_ck)] + HSI_KER: [4, HSI kernel clock selected as clock source (hsi_ker_ck)] + CSI_KER: [5, CSI kernel clock selected as clock source (csi_ker_ck)] diff --git a/devices/fields/rcc/v3/h503.yaml b/devices/fields/rcc/v3/h503.yaml new file mode 100644 index 000000000..f2ea2f416 --- /dev/null +++ b/devices/fields/rcc/v3/h503.yaml @@ -0,0 +1,55 @@ +# RCC patches specifically for H503 + +_include: + - h5.yaml + +CCIPR1: + USART*SEL: + _name: USARTSEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL2_Q: [1, PLL2 Q clock selected as clock source (pll2_q_ck)] + HSI_KER: [3, HSI kernel clock selected as clock source (hsi_ker_ck)] + CSI_KER: [4, CSI kernel clock selected as clock source (csi_ker_ck)] + LSE: [5, LSE clock selected as clock source (lse_ck)] +CCIPR2: + LPTIM*SEL: + _name: LPTIMSEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL2_P: [1, PLL2 P clock selected as clock source (pll2_p_ck)] + LSE_KER: [3, LSE kernel selected as clock source (lse_ck)] + LSI_KER: [4, LSI kernel selected as clock source (lsi_ker_ck)] + PER_CK: [5, per_ck clock selected as clock source] +CCIPR3: + _derive: + LPUART1SEL: CCIPR1.USART1SEL + SPI*SEL: + _name: SPI123SEL + PLL1_Q: [0, PLL1 Q clock selected as clock source (pll1_q_ck)] + PLL2_P: [1, PLL2 P clock selected as clock source (pll2_p_ck)] + AUDIOCLK: [3, AUDIOCLK clock selected as clock source] + PER_CK: [4, per_ck clock selected as clock source] +CCIPR4: + I3C*SEL: + _name: I3CSEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL2_R: [1, PLL2 R clock selected as clock source (pll2_r_ck)] + HSI_KER: [2, HSI kernel clock selected as clock source (hsi_ker_ck)] + I2C*SEL: + _name: I2CSEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL2_R: [1, PLL2 R Clock selected as clock source (pll2_r_ck)] + HSI_KER: [2, HSI kernel clock selected as clock source (hsi_ker_ck)] + CSI_KER: [3, CSI kernel clock selected as clock source (csi_ker_ck)] + USBSEL: + DISABLE: [0, Disable the clock] + PLL1_Q: [1, PLL1 Q clock selected as clock source (pll1_q_ck)] + PLL2_Q: [2, PLL2 Q clock selected as clock source (pll2_q_ck)] + HSI48: [3, HSI48 clock selected as clock source (hsi48_ker_ck)] +CCIPR5: + DAC1SEL: + LSE: [0, LSE selected as clock source (lse_ck)] + LSI_KER: [1, LSI kernel selected as clock source (lsi_ker_ck)] +PRIVCFGR: + PRIV: + Any: [0, RCC functions can be modified by privileged or unprivileged access] + PrivilegedOnly: [1, RCC functions can only be modified by privileged access] diff --git a/devices/fields/rcc/v3/h56x_h57x.yaml b/devices/fields/rcc/v3/h56x_h57x.yaml new file mode 100644 index 000000000..abfa27a28 --- /dev/null +++ b/devices/fields/rcc/v3/h56x_h57x.yaml @@ -0,0 +1,90 @@ +_include: + - h5.yaml + +CCIPR1: + USART*SEL,UART*SEL: + _name: USARTSEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL2_Q: [1, PLL2 Q clock selected as clock source (pll2_q_ck)] + PLL3_Q: [2, PLL3 Q clock selected as clock source (pll3_q_ck)] + HSI_KER: [3, HSI kernel clock selected as clock source (hsi_ker_ck)] + CSI_KER: [4, CSI kernel clock selected as clock source (csi_ker_ck)] + LSE: [5, LSE clock selected as clock source (lse_ck)] +CCIPR2: + LPTIM*SEL: + _name: LPTIMSEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL2_P: [1, PLL2 P clock selected as clock source (pll2_p_ck)] + PLL3_R: [2, PLL3 R clock selected as clock source (pll3_r_ck)] + LSE_KER: [3, LSE kernel selected as clock source (lse_ck)] + LSI_KER: [4, LSI kernel selected as clock source (lsi_ker_ck)] + PER_CK: [5, per_ck clock selected as clock source] + _derive: + USART*SEL,UART*SEL: CCIPR1.USART1SEL +CCIPR3: + _derive: + LPUART*SEL: CCIPR1.USART1SEL + SPI[456]SEL: + _name: SPI456SEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL2_Q: [1, PLL2 Q clock selected as clock source (pll2_p_ck)] + PLL3_Q: [2, PLL3 Q clock selected as clock source (pll3_p_ck)] + HSI_KER: [3, HSI kernel clock selected as clock source (hsi_ker_ck)] + CSI_KER: [4, CSI kernel clock selected as clock source (csi_ker_ck)] + HSE: [5, HSE clock selected as clock source (hse_ck)] + SPI[123]SEL: + _name: SPI123SEL + PLL1_Q: [0, PLL1 Q clock selected as clock source (pll1_q_ck)] + PLL2_P: [1, PLL2 P clock selected as clock source (pll2_p_ck)] + PLL3_P: [2, PLL3 P clock selected as clock source (pll3_p_ck)] + AUDIOCLK: [3, AUDIOCLK clock selected as clock source] + PER_CK: [4, per_ck clock selected as clock source] +CCIPR4: + USBSEL: + DISABLE: [0, Disable the clock] + PLL1_Q: [1, PLL1 Q clock selected as clock source (pll1_q_ck)] + PLL3_Q: [2, PLL3 Q clock selected as clock source (pll3_q_ck)] + HSI48: [3, HSI48 clock selected as clock source (hsi48_ker_ck)] + I3C*SEL: + _name: I3CSEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL3_R: [1, PLL3 R clock selected as clock source (pll3_r_ck)] + HSI_KER: [2, HSI kernel clock selected as clock source (hsi_ker_ck)] + I2C*SEL: + _name: I2CSEL + PCLK: [0, Peripheral bus clock used as selected as clock source (rcc_pclk_x)] + PLL3_R: [1, PLL3 R Clock selected as clock source (pll3_r_ck)] + HSI_KER: [2, HSI kernel clock selected as clock source (hsi_ker_ck)] + CSI_KER: [3, CSI kernel clock selected as clock source (csi_ker_ck)] + SDMMC*SEL: + _name: SDMMCSEL + PLL1_Q: [0, PLL1 Q clock selected as clock source (pll1_q_ck)] + PLL2_R: [1, PLL2 R clock selected as clock source (pll2_r_ck)] + OCTOSPI1SEL: + RCC_HCLK4: [0, HCLK4 selected as clock source (rcc_hclk4)] + PLL1_Q: [1, PLL1 Q clock selected as clock source (pll1_q_ck)] + PLL2_R: [2, PLL2 R clock selected as clock source (pll2_r_ck)] + PER_CK: [3, per_ck clock selected as clock source] +CCIPR5: + SAI*SEL: + _name: SAISEL + PLL1_Q: [0, PLL1 Q clock selected as clock source (pll1_q_ck)] + PLL2_P: [1, PLL2 P clock selected as clock source (pll2_p_ck)] + PLL3_P: [2, PLL3 P clock selected as clock source (pll3_p_ck)] + AUDIOCLK: [3, AUDIOCLK clock selected as clock source] + PER_CK: [4, per_ck clock selected as clock source] + CECSEL: + LSE: [0, LSE selected as clock source (lse_ck)] + LSI_KER: [1, LSI kernel selected as clock source (lsi_ker_ck)] + CSI_KER: [2, CSI kernel clock divided by 122 selected as clock source (csi_ker_ck/122)] + DACSEL: + LSE: [0, LSE selected as clock source (lse_ck)] + LSI_KER: [1, LSI kernel selected as clock source (lsi_ker_ck)] +SECCFGR: + "*SEC": + NonSecure: [0, Non secure] + Secure: [1, Secure] +PRIVCFGR: + "*PRIV": + Any: [0, RCC functions can be modified by privileged or unprivileged access] + PrivilegedOnly: [1, RCC functions can only be modified by privileged access] diff --git a/devices/fields/rcc/v3/h7.yaml b/devices/fields/rcc/v3/h7.yaml new file mode 100644 index 000000000..2159f161e --- /dev/null +++ b/devices/fields/rcc/v3/h7.yaml @@ -0,0 +1,8 @@ +_include: + - common.yaml + - cfgr.yaml + - csr.yaml + - gsr.yaml + - d3amr_srdamr.yaml + - pll.yaml + - h7_ccip.yaml diff --git a/devices/fields/rcc/v3/h7_ccip.yaml b/devices/fields/rcc/v3/h7_ccip.yaml new file mode 100644 index 000000000..54016796d --- /dev/null +++ b/devices/fields/rcc/v3/h7_ccip.yaml @@ -0,0 +1,148 @@ +# Applicable at least to H7 + +# Domain kernel clock configuration registers (DxCCIPR) and Domain +# clock configuration registers (DxCFGR) + +D1CFGR,CDCFGR1: + "D?CPRE,HPRE,CDCPRE": + Div1: [-1, sys_ck not divided] + Div2: [8, sys_ck divided by 2] + Div4: [9, sys_ck divided by 4] + Div8: [10, sys_ck divided by 8] + Div16: [11, sys_ck divided by 16] + Div64: [12, sys_ck divided by 64] + Div128: [13, sys_ck divided by 128] + Div256: [14, sys_ck divided by 256] + Div512: [15, sys_ck divided by 512] +D?CFGR,CDCFGR?: + D?PPR*,CDPPRE*: + Div1: [-1, rcc_hclk not divided] + Div2: [4, rcc_hclk divided by 2] + Div4: [5, rcc_hclk divided by 4] + Div8: [6, rcc_hclk divided by 8] + Div16: [7, rcc_hclk divided by 16] +D1CCIPR,CDCCIPR: + CKPERSEL: + HSI: [0, HSI selected as peripheral clock] + CSI: [1, CSI selected as peripheral clock] + HSE: [2, HSE selected as peripheral clock] + SDMMCSEL: + PLL1_Q: [0, pll1_q selected as peripheral clock] + PLL2_R: [1, pll2_r selected as peripheral clock] + QSPISEL,FMCSEL,OCTOSPISEL: + RCC_HCLK3: [0, rcc_hclk3 selected as peripheral clock] + PLL1_Q: [1, pll1_q selected as peripheral clock] + PLL2_R: [2, pll2_r selected as peripheral clock] + PER: [3, PER selected as peripheral clock] +D2CCIP1R,CDCCIP1R: + SWPSEL,SWPMISEL: + PCLK: [0, pclk selected as peripheral clock] + HSI_KER: [1, hsi_ker selected as peripheral clock] + FDCANSEL: + HSE: [0, HSE selected as peripheral clock] + PLL1_Q: [1, pll1_q selected as peripheral clock] + PLL2_Q: [2, pll2_q selected as peripheral clock] + DFSDM1SEL: + RCC_PCLK2: [0, rcc_pclk2 selected as peripheral clock] + SYS: [1, System clock selected as peripheral clock] + SPDIFSEL,SPDIFRXSEL: + PLL1_Q: [0, pll1_q selected as peripheral clock] + PLL2_R: [1, pll2_r selected as peripheral clock] + PLL3_R: [2, pll3_r selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] + SPI45SEL: + APB: [0, APB clock selected as peripheral clock] + PLL2_Q: [1, pll2_q selected as peripheral clock] + PLL3_Q: [2, pll3_q selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] + CSI_KER: [4, csi_ker selected as peripheral clock] + HSE: [5, HSE selected as peripheral clock] + SPI123SEL,SAI23SEL,SAI1SEL: + PLL1_Q: [0, pll1_q selected as peripheral clock] + PLL2_P: [1, pll2_p selected as peripheral clock] + PLL3_P: [2, pll3_p selected as peripheral clock] + I2S_CKIN: [3, I2S_CKIN selected as peripheral clock] + PER: [4, PER selected as peripheral clock] +D2CCIP2R,CDCCIP2R: + LPTIM1SEL: + RCC_PCLK1: [0, rcc_pclk1 selected as peripheral clock] + PLL2_P: [1, pll2_p selected as peripheral clock] + PLL3_R: [2, pll3_r selected as peripheral clock] + LSE: [3, LSE selected as peripheral clock] + LSI: [4, LSI selected as peripheral clock] + PER: [5, PER selected as peripheral clock] + CECSEL: + LSE: [0, LSE selected as peripheral clock] + LSI: [1, LSI selected as peripheral clock] + CSI_KER: [2, csi_ker selected as peripheral clock] + USBSEL: + DISABLE: [0, Disable the kernel clock] + PLL1_Q: [1, pll1_q selected as peripheral clock] + PLL3_Q: [2, pll3_q selected as peripheral clock] + HSI48: [3, HSI48 selected as peripheral clock] + I2C123SEL,I2C1235SEL: + RCC_PCLK1: [0, rcc_pclk1 selected as peripheral clock] + PLL3_R: [1, pll3_r selected as peripheral clock] + HSI_KER: [2, hsi_ker selected as peripheral clock] + CSI_KER: [3, csi_ker selected as peripheral clock] + RNGSEL: + HSI48: [0, HSI48 selected as peripheral clock] + PLL1_Q: [1, pll1_q selected as peripheral clock] + LSE: [2, LSE selected as peripheral clock] + LSI: [3, LSI selected as peripheral clock] + USART16SEL,USART16910SEL: + RCC_PCLK2: [0, rcc_pclk2 selected as peripheral clock] + PLL2_Q: [1, pll2_q selected as peripheral clock] + PLL3_Q: [2, pll3_q selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] + CSI_KER: [4, csi_ker selected as peripheral clock] + LSE: [5, LSE selected as peripheral clock] + USART234578SEL: + RCC_PCLK1: [0, rcc_pclk1 selected as peripheral clock] + PLL2_Q: [1, pll2_q selected as peripheral clock] + PLL3_Q: [2, pll3_q selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] + CSI_KER: [4, csi_ker selected as peripheral clock] + LSE: [5, LSE selected as peripheral clock] + +# D3 / SRD +D3CCIPR,SRDCCIPR: + SPI6SEL: + RCC_PCLK4: [0, rcc_pclk4 selected as peripheral clock] + PLL2_Q: [1, pll2_q selected as peripheral clock] + PLL3_Q: [2, pll3_q selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] + CSI_KER: [4, csi_ker selected as peripheral clock] + HSE: [5, HSE selected as peripheral clock] + ADCSEL: + PLL2_P: [0, pll2_p selected as peripheral clock] + PLL3_R: [1, pll3_r selected as peripheral clock] + PER: [2, PER selected as peripheral clock] + LPTIM345SEL,LPTIM2SEL: + RCC_PCLK4: [0, rcc_pclk4 selected as peripheral clock] + PLL2_P: [1, pll2_p selected as peripheral clock] + PLL3_R: [2, pll3_r selected as peripheral clock] + LSE: [3, LSE selected as peripheral clock] + LSI: [4, LSI selected as peripheral clock] + PER: [5, PER selected as peripheral clock] + I2C4SEL: + RCC_PCLK4: [0, rcc_pclk4 selected as peripheral clock] + PLL3_R: [1, pll3_r selected as peripheral clock] + HSI_KER: [2, hsi_ker selected as peripheral clock] + CSI_KER: [3, csi_ker selected as peripheral clock] + LPUART1SEL: + RCC_PCLK_D3: [0, rcc_pclk_d3 selected as peripheral clock] + PLL2_Q: [1, pll2_q selected as peripheral clock] + PLL3_Q: [2, pll3_q selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] + CSI_KER: [4, csi_ker selected as peripheral clock] + LSE: [5, LSE selected as peripheral clock] + +# Applies to SAI2 or SAI4 when split +D3CCIPR,CDCCIP1R: + SAI*[AB]SEL: + PLL1_Q: [0, pll1_q selected as peripheral clock] + PLL2_P: [1, pll2_p selected as peripheral clock] + PLL3_P: [2, pll3_p selected as peripheral clock] + I2S_CKIN: [3, i2s_ckin selected as peripheral clock] + PER: [4, PER selected as peripheral clock] diff --git a/devices/fields/rcc/v3/h7_revision_v.yaml b/devices/fields/rcc/v3/h7_revision_v.yaml new file mode 100644 index 000000000..cda684dcc --- /dev/null +++ b/devices/fields/rcc/v3/h7_revision_v.yaml @@ -0,0 +1,9 @@ +# Revision V of H7 has HSICFGR / CSICFGR instead of ICSCR. + +# Does not apply to Revsion Y of H7 + +_include: + - hsicfgr.yaml + +CSICFGR: + CSITRIM: [0, 0x3F] diff --git a/devices/fields/rcc/v3/h7_revision_y.yaml b/devices/fields/rcc/v3/h7_revision_y.yaml new file mode 100644 index 000000000..8989229a9 --- /dev/null +++ b/devices/fields/rcc/v3/h7_revision_y.yaml @@ -0,0 +1,7 @@ +# Revision Y of H7 has ICSCR. + +# Does not apply to Revsion V of H7 + +ICSCR: + CSITRIM: [0, 0x1F] + HSITRIM: [0, 0x3F] diff --git a/devices/fields/rcc/v3/h7rs.yaml b/devices/fields/rcc/v3/h7rs.yaml new file mode 100644 index 000000000..4c4bd7efb --- /dev/null +++ b/devices/fields/rcc/v3/h7rs.yaml @@ -0,0 +1,203 @@ +_include: + - common.yaml + - cfgr.yaml + - csr.yaml + +PLLCKSELR: + DIVM?: [0, 63] + PLLSRC: + HSI: [0, HSI selected as PLL clock] + CSI: [1, CSI selected as PLL clock] + HSE: [2, HSE selected as PLL clock] + None: [3, No clock sent to DIVMx dividers and PLLs] +PLLCFGR: + DIV??EN: + Disabled: [0, Clock ouput is disabled] + Enabled: [1, Clock output is enabled] + PLL?RGE: + Range1: [0, Frequency is between 1 and 2 MHz] + Range2: [1, Frequency is between 2 and 4 MHz] + Range4: [2, Frequency is between 4 and 8 MHz] + Range8: [3, Frequency is between 8 and 16 MHz] + PLL?VCOSEL: + WideVCO: [0, VCO frequency range 192 to 836 MHz] + MediumVCO: [1, VCO frequency range 150 to 420 MHz] + PLL?FRACEN: + Reset: [0, Reset latch to tranfer FRACN to the Sigma-Delta modulator] + Set: [1, Set latch to tranfer FRACN to the Sigma-Delta modulator] +BMCFGR: + HPRE: + Div1: [-1, sys_ck not divided] + Div2: [8, sys_ck divided by 2] + Div4: [9, sys_ck divided by 4] + Div8: [10, sys_ck divided by 8] + Div16: [11, sys_ck divided by 16] + Div64: [12, sys_ck divided by 64] + Div128: [13, sys_ck divided by 128] + Div256: [14, sys_ck divided by 256] + Div512: [15, sys_ck divided by 512] +CCIPR1: + CKPERSEL: + HSI: [0, HSI selected as peripheral clock] + CSI: [1, CSI selected as peripheral clock] + HSE: [2, HSE selected as peripheral clock] + PSSISEL: + PLL3_R: [0, pll3_r selected as peripheral clock] + PER: [1, per selected as kernel peripheral clock] + ADCSEL: + PLL2_P: [0, pll2_p selected as peripheral clock] + PLL3_R: [1, pll3_r selected as peripheral clock] + PER: [2, per selected as peripheral clock] + ADFSEL: + HCLK1: [0, hclk1 selected as ADF clock] + PLL2_p: [1, pll2_p_ck selected as ADF clock] + PLL3_P: [2, pll3_p_ck selected as ADF clock] + I2S_CLKIN: [3, I2S_CKIN selected as ADF clock] + CSI_KER: [4, csi_ker_ck selected as ADF clock] + HSI_KER: [5, hsi_ker_ck selected as ADF clock] + ETHPHY_CLK_SEL: + HSE_KER: [0, hse_ker selected as clock source] + PLL3_S: [1, pll3_s selected clock source] + ETH1_REF_CLK_SEL: + ETH_RMII_REF: [0, ETH_RMII_REF selected as peripheral clock] + HSE_KER: [1, hse_ker selected as peripheral clock] + ETH_CLK_FB: [2, eth_clk_fb selected as peripheral clock] + OTGFSSEL: + HSI48_KER: [0, hsi48_ker_ck] + PLL3_Q: [1, pll3_q_ck] + HSE_KER: [2, hse_ker_ck] + CLK48: [3, clk48mohci] + USBPHYCSEL: + HSE_KER: [0, hse_ker_ck] + HSE_KER_DIV2: [1, hse_ker_ck / 2] + PLL3_Q: [2, pll3_q_ck] + USBREFCKSEL: + MHz16: [3, The clock frequency provided to the USBPHYC is 16 MHz] + MHz19: [8, The clock frequency provided to the USBPHYC is 19.2 MHz] + MHz20: [9, The clock frequency provided to the USBPHYC is 20MHz] + MHz24: [10, The clock frequency provided to the USBPHYC is 24 MHz] + MHz26: [14, The clock frequency provided to the USBPHYC is 26 MHz] + MHz32: [11, The clock frequency provided to the USBPHYC is 32 MHz] + OCTOSPI1SEL: + RCC_HCLK5: [0, hclk5 selected as peripheral clock] + PLL2_S: [1, pll2_s_ck selected as peripheral clock] + PLL2_T: [2, pll2_t_ck selected as peripheral clock] + OCTOSPI2SEL: + RCC_HCLK5: [0, hclk5 selected as peripheral clock] + PLL2_S: [1, pll2_s_ck selected as peripheral clock] + PLL2_T: [2, pll2_t_ck selected as peripheral clock] + SDMMCSEL: + PLL2_S: [0, pll1_s selected as peripheral clock] + PLL2_T: [1, pll2_t selected as peripheral clock] + FMCSEL: + RCC_HCLK5: [0, hclk5 selected as peripheral clock] + PLL1_Q: [1, pll1_q selected as peripheral clock] + PLL2_R: [2, pll2_r selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] +CCIPR2: + CECSEL: + LSE: [0, lse selected as clock] + LSI: [1, lsi selected as clock] + CSI_KER: [2, csi_ker divided by 122 selected as clock] + SPDIFRXSEL: + PLL1_Q: [0, pll1_q selected as clock] + PLL2_R: [1, pll2_r selected as clock] + PLL3_R: [2, pll3_r selected as clock] + HSI_KER: [3, hsi_ker selected as clock] + FDCANSEL: + HSE_KER: [0, hse_ker selected as clock] + PLL1_Q: [1, pll1_q selected as clock] + PLL2_P: [2, pll2_p selected as clock] + LPTIM1SEL: + PCLK1: [0, pclk1 selected as peripheral clock] + PLL2_P: [1, pll2_p selected as peripheral clock] + PLL3_R: [2, pll3_r selected as peripheral clock] + LSE: [3, lse selected as peripheral clock] + LSI: [4, lsi selected as peripheral clock] + PER: [5, per selected as peripheral clock] + I2C1I3C1SEL: + PCLK1: [0, pclk1 selected as peripheral clock] + PLL3_R: [1, pll3_r selected as peripheral clock] + HSI_KER: [2, hsi_ker selected as peripheral clock] + CSI_KER: [3, csi_ker selected as peripheral clock] + I2C23SEL: + PCLK1: [0, pclk1 selected as clock] + PLL3_R: [1, pll3_r selected as clock] + HSI_KER: [2, hsi_ker selected as clock] + CSI_KER: [3, csi_ker selected as clock] + SPI23SEL: + PLL1_Q: [0, pll1_q selected as clock] + PLL2_P: [1, pll2_p selected as clock] + PLL3_P: [2, pll3_p selected as clock] + I2S_CKIN: [3, I2S_CKIN selected as clock] + PER: [4, per selected as clock] + UART234578SEL: + PCLK1: [0, pclk1 selected as clock] + PLL2_Q: [1, pll2_q selected as clock] + PLL3_Q: [2, pll3_q selected as clock] + HSI_KER: [3, hsi_ker selected as clock] + CSI_KER: [4, csi_ker selected as clock] + LSE: [5, lse selected as clock] +CCIPR3: + SAI2SEL: + PLL1_Q: [0, pll1_q selected as clock] + PLL2_P: [1, pll2_p selected as clock] + PLL3_P: [2, pll3_p selected as clock] + I2S_CKIN: [3, I2S_CKIN selected as clock] + PER: [4, per selected as clock] + SPDIFRX_SYMB: [5, spdifrx_symb selected as clock] + SAI1SEL: + PLL1_Q: [0, pll1_q selected as clock] + PLL2_P: [1, pll2_p selected as clock] + PLL3_P: [2, pll3_p selected as clock] + I2S_CKIN: [3, I2S_CKIN selected as clock] + PER: [4, per selected as clock] + SPI1SEL: + PLL1_Q: [0, pll1_q selected as SPI/I2S1 and 7 clock] + PLL2_P: [1, pll2_p selected as SPI/I2S1 and 7 clock] + PLL3_P: [2, pll3_p selected as SPI/I2S1 and 7 clock] + I2S_CKIN: [3, I2S_CKIN selected as SPI/I2S1 and 7 clock] + PER: [4, "per selected as SPI/I2S1,and 7 clock"] + SPI45SEL: + PCLK2: [0, pclk2 selected as clock] + PLL2_Q: [1, pll2_q is selected as clock] + PLL3_Q: [2, pll3_q is selected as clock] + HSI_KER: [3, hsi_ker is selected as clock] + CSI_KER: [4, csi_ker is selected as clock] + HSE_KER: [5, hse_ker is selected as clock] + USART1SEL: + PCLK2: [0, pclk2 selected as clock] + PLL2_Q: [1, pll2_q selected as clock] + PLL3_Q: [2, pll3_q selected as clock] + HSI_KER: [3, hsi_ker selected as clock] + CSI_KER: [4, csi_ker selected as clock] + LSE: [5, lse selected as clock] +CCIPR4: + LPTIM23SEL: + PCLK4: [0, pclk4 selected as peripheral clock] + PLL2_P: [1, pll2_p selected as peripheral clock] + PLL3_R: [2, pll3_r selected as peripheral clock] + LSE: [3, lse selected as peripheral clock] + LSI: [4, lsi selected as peripheral clock] + PER: [5, per selected as peripheral clock] + LPTIM45SEL: + PCLK4: [0, pclk4 selected as peripheral clock] + PLL2_P: [1, pll2_p selected as peripheral clock] + PLL3_R: [2, pll3_r selected as peripheral clock] + LSE: [3, lse selected as peripheral clock] + LSI: [4, lsi selected as peripheral clock] + PER: [5, per selected as peripheral clock] + SPI6SEL: + PCLK4: [0, pclk4 selected as peripheral clock] + PLL2_Q: [1, pll2_q selected as peripheral clock] + PLL3_Q: [2, pll3_q selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] + CSI_KER: [4, csi_ker selected as peripheral clock] + HSE_KER: [5, hse_ker selected as peripheral clock] + LPUART1SEL: + PCLK4: [0, pclk4 selected as peripheral clock] + PLL2_Q: [1, pll2_q selected as peripheral clock] + PLL3_Q: [2, pll3_q selected as peripheral clock] + HSI_KER: [3, hsi_ker selected as peripheral clock] + CSI_KER: [4, csi_ker selected as peripheral clock] + LSE: [5, lse selected as peripheral clock] diff --git a/devices/fields/rcc/v3/hrtim.yaml b/devices/fields/rcc/v3/hrtim.yaml new file mode 100644 index 000000000..22c7cdd7e --- /dev/null +++ b/devices/fields/rcc/v3/hrtim.yaml @@ -0,0 +1,6 @@ +# Applicable at least to H7, except RM0455 parts with no HRTIM + +CFGR: + HRTIMSEL: + TIMY_KER: [0, The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)] + C_CK: [1, The HRTIM prescaler clock source is the CPU clock (c_ck)] diff --git a/devices/fields/rcc/v3/hsicfgr.yaml b/devices/fields/rcc/v3/hsicfgr.yaml new file mode 100644 index 000000000..04f3a5749 --- /dev/null +++ b/devices/fields/rcc/v3/hsicfgr.yaml @@ -0,0 +1,2 @@ +HSICFGR: + HSITRIM: [0, 0x7F] diff --git a/devices/fields/rcc/v3/pll.yaml b/devices/fields/rcc/v3/pll.yaml new file mode 100644 index 000000000..50034813f --- /dev/null +++ b/devices/fields/rcc/v3/pll.yaml @@ -0,0 +1,100 @@ +# Applicable at least to H7 + +# PLL registers + +PLLCKSELR: + DIVM?: [0, 63] + PLLSRC: + HSI: [0, HSI selected as PLL clock] + CSI: [1, CSI selected as PLL clock] + HSE: [2, HSE selected as PLL clock] + None: [3, No clock sent to DIVMx dividers and PLLs] +PLLCFGR: + DIV??EN: + Disabled: [0, Clock ouput is disabled] + Enabled: [1, Clock output is enabled] + PLL?RGE: + Range1: [0, Frequency is between 1 and 2 MHz] + Range2: [1, Frequency is between 2 and 4 MHz] + Range4: [2, Frequency is between 4 and 8 MHz] + Range8: [3, Frequency is between 8 and 16 MHz] + PLL?VCOSEL: + WideVCO: [0, VCO frequency range 192 to 836 MHz] + MediumVCO: [1, VCO frequency range 150 to 420 MHz] + PLL?FRACEN: + Reset: [0, Reset latch to tranfer FRACN to the Sigma-Delta modulator] + Set: [1, Set latch to tranfer FRACN to the Sigma-Delta modulator] +PLL1DIVR: + DIVP1: + Div1: [0, "pll_p_ck = vco_ck"] + Div2: [1, "pll_p_ck = vco_ck / 2"] + Div4: [3, "pll_p_ck = vco_ck / 4"] + Div6: [5, "pll_p_ck = vco_ck / 6"] + Div8: [7, "pll_p_ck = vco_ck / 8"] + Div10: [9, "pll_p_ck = vco_ck / 10"] + Div12: [11, "pll_p_ck = vco_ck / 12"] + Div14: [13, "pll_p_ck = vco_ck / 14"] + Div16: [15, "pll_p_ck = vco_ck / 16"] + Div18: [17, "pll_p_ck = vco_ck / 18"] + Div20: [19, "pll_p_ck = vco_ck / 20"] + Div22: [21, "pll_p_ck = vco_ck / 22"] + Div24: [23, "pll_p_ck = vco_ck / 24"] + Div26: [25, "pll_p_ck = vco_ck / 26"] + Div28: [27, "pll_p_ck = vco_ck / 28"] + Div30: [29, "pll_p_ck = vco_ck / 30"] + Div32: [31, "pll_p_ck = vco_ck / 32"] + Div34: [33, "pll_p_ck = vco_ck / 34"] + Div36: [35, "pll_p_ck = vco_ck / 36"] + Div38: [37, "pll_p_ck = vco_ck / 38"] + Div40: [39, "pll_p_ck = vco_ck / 40"] + Div42: [41, "pll_p_ck = vco_ck / 42"] + Div44: [43, "pll_p_ck = vco_ck / 44"] + Div46: [45, "pll_p_ck = vco_ck / 46"] + Div48: [47, "pll_p_ck = vco_ck / 48"] + Div50: [49, "pll_p_ck = vco_ck / 50"] + Div52: [51, "pll_p_ck = vco_ck / 52"] + Div54: [53, "pll_p_ck = vco_ck / 54"] + Div56: [55, "pll_p_ck = vco_ck / 56"] + Div58: [57, "pll_p_ck = vco_ck / 58"] + Div60: [59, "pll_p_ck = vco_ck / 60"] + Div62: [61, "pll_p_ck = vco_ck / 62"] + Div64: [63, "pll_p_ck = vco_ck / 64"] + Div66: [65, "pll_p_ck = vco_ck / 66"] + Div68: [67, "pll_p_ck = vco_ck / 68"] + Div70: [69, "pll_p_ck = vco_ck / 70"] + Div72: [71, "pll_p_ck = vco_ck / 72"] + Div74: [73, "pll_p_ck = vco_ck / 74"] + Div76: [75, "pll_p_ck = vco_ck / 76"] + Div78: [77, "pll_p_ck = vco_ck / 78"] + Div80: [79, "pll_p_ck = vco_ck / 80"] + Div82: [81, "pll_p_ck = vco_ck / 82"] + Div84: [83, "pll_p_ck = vco_ck / 84"] + Div86: [85, "pll_p_ck = vco_ck / 86"] + Div88: [87, "pll_p_ck = vco_ck / 88"] + Div90: [89, "pll_p_ck = vco_ck / 90"] + Div92: [91, "pll_p_ck = vco_ck / 92"] + Div94: [93, "pll_p_ck = vco_ck / 94"] + Div96: [95, "pll_p_ck = vco_ck / 96"] + Div98: [97, "pll_p_ck = vco_ck / 98"] + Div100: [99, "pll_p_ck = vco_ck / 100"] + Div102: [101, "pll_p_ck = vco_ck / 102"] + Div104: [103, "pll_p_ck = vco_ck / 104"] + Div106: [105, "pll_p_ck = vco_ck / 106"] + Div108: [107, "pll_p_ck = vco_ck / 108"] + Div110: [109, "pll_p_ck = vco_ck / 110"] + Div112: [111, "pll_p_ck = vco_ck / 112"] + Div114: [113, "pll_p_ck = vco_ck / 114"] + Div116: [115, "pll_p_ck = vco_ck / 116"] + Div118: [117, "pll_p_ck = vco_ck / 118"] + Div120: [119, "pll_p_ck = vco_ck / 120"] + Div122: [121, "pll_p_ck = vco_ck / 122"] + Div124: [123, "pll_p_ck = vco_ck / 124"] + Div126: [125, "pll_p_ck = vco_ck / 126"] + Div128: [127, "pll_p_ck = vco_ck / 128"] +#PLL2DIVR,PLL3DIVR: +# DIVP?: [0, 127] +PLL?DIVR: + DIVR?,DIVQ?: [0, 127] + DIVN?: [3, 511] +PLL?FRACR: + FRACN?: [0, 0x1FFF] diff --git a/devices/fields/rng/v1.yaml b/devices/fields/rng/v1.yaml new file mode 100644 index 000000000..3be222333 --- /dev/null +++ b/devices/fields/rng/v1.yaml @@ -0,0 +1,51 @@ +CR: + RNGEN: + Disabled: [0, Random number generator is disabled] + Enabled: [1, Random number generator is enabled] + IE: + Disabled: [0, RNG interrupt is disabled] + Enabled: [1, RNG interrupt is enabled] + "?~CED": + Enabled: [0, Clock error detection is enabled] + Disabled: [1, Clock error detection is disabled] + +SR: + "[CS]EIS": + _W0C: + Clear: [0, Clear flag] + SEIS: + _read: + NoFault: [0, No faulty sequence detected] + Fault: + [ + 1, + "At least one faulty sequence has been detected. See **SECS** bit description for details.\nAn interrupt is pending if IE = 1 in the RNG_CR register.", + ] + CEIS: + _read: + Correct: [0, The RNG clock is correct] + Slow: [1, "The RNG has been detected too slow\nAn interrupt is pending if IE = 1 in the RNG_CR register"] + SECS: + NoFault: + [ + 0, + "No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered.", + ] + Fault: [1, At least one faulty sequence has been detected - see ref manual for details] + CECS: + Correct: + [ + 0, + "The RNG clock is correct. If the CEIS bit is set, this means that a slow clock was detected and the situation has been recovered.", + ] + Slow: [1, The RNG clock is too slow] + DRDY: + Invalid: [0, "The RNG_DR register is not yet valid, no random data is available"] + Valid: + [ + 1, + "The RNG_DR register contains valid random data.\nOnce the RNG_DR register has been read, this bit returns to 0 until a new random value is generated.", + ] + +DR: + RNDATA: [0, 0xFFFFFFFF] diff --git a/devices/fields/rng/v2.yaml b/devices/fields/rng/v2.yaml new file mode 100644 index 000000000..7b9950415 --- /dev/null +++ b/devices/fields/rng/v2.yaml @@ -0,0 +1,45 @@ +_include: + - ./v1.yaml + +CR: + CONFIGLOCK: + Enabled: [0, "Writes to the RNG_CR configuration bits [29:4] are allowed"] + Disabled: [1, "Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset"] + CONDRST: + RNG_CONFIG1: + ConfigA: [0x0F, Recommended value for config A (NIST certifiable)] + ConfigB: [0x18, Recommended value for config B (not NIST certifiable)] + RNG_CONFIG2: + ConfigA_B: [0x00, Recommended value for config A and B] + RNG_CONFIG3: + ConfigA: [0x0D, Recommended value for config A (NIST certifiable)] + ConfigB: [0x00, Recommended value for config B (not NIST certifiable)] + CLKDIV: + Div1: [0, Internal RNG clock after divider is similar to incoming RNG clock] + Div2: [1, "Divide RNG clock by 2^1"] + Div4: [2, "Divide RNG clock by 2^2"] + Div8: [3, "Divide RNG clock by 2^3"] + Div16: [4, "Divide RNG clock by 2^4"] + Div32: [5, "Divide RNG clock by 2^5"] + Div64: [6, "Divide RNG clock by 2^6"] + Div128: [7, "Divide RNG clock by 2^7"] + Div256: [8, "Divide RNG clock by 2^8"] + Div512: [9, "Divide RNG clock by 2^9"] + Div1024: [10, "Divide RNG clock by 2^10"] + Div2048: [11, "Divide RNG clock by 2^11"] + Div4096: [12, "Divide RNG clock by 2^12"] + Div8192: [13, "Divide RNG clock by 2^13"] + Div16384: [14, "Divide RNG clock by 2^14"] + Div32768: [15, "Divide RNG clock by 2^15"] + NISTC: + Default: + [ + 0, + Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used, + ] + Custom: [1, Custom values for NIST compliant RNG] + +HTCR: + HTCFG: + Magic: [0x1759_0ABC, Magic number to be written before any write (0x1759_0ABC)] + Recommended: [0x0000_AA74, Recommended value for RNG certification (0x0000_AA74)] diff --git a/devices/fields/rtc/v1/f1.yaml b/devices/fields/rtc/v1/f1.yaml new file mode 100644 index 000000000..5d6c724f4 --- /dev/null +++ b/devices/fields/rtc/v1/f1.yaml @@ -0,0 +1,49 @@ +CRH: + OWIE: + Disabled: [0, Overflow interrupt is masked] + Enabled: [1, Overflow interrupt is enabled] + ALRIE: + Disabled: [0, Alarm interrupt is masked] + Enabled: [1, Alarm interrupt is enabled] + SECIE: + Disabled: [0, Second interrupt is masked] + Enabled: [1, Second interrupt is enabled] +CRL: + RTOFF: + Enabled: [0, Last write operation on RTC registers is still ongoing] + Disabled: [1, Last write operation on RTC registers terminated] + CNF: + Exit: [0, Exit configuration mode (start update of RTC registers)] + Enter: [1, Enter configuration mode] + RSF: + _read: + NotSynchronized: [0, Registers not yet synchronized] + Synchronized: [1, Registers synchronized] + OWF: + _read: + NoOverflow: [0, Overflow not detected] + Overflow: [1, 32-bit programmable counter overflow occurred] + ALRF: + _read: + NoAlarm: [0, Alarm not detected] + Alarm: [1, Alarm detected] + SECF: + _read: + NoPrescalerOverflow: [0, Second flag condition not met] + PrescalerOverflow: [1, Second flag condition met] + "RSF,OWF,ALRF,SECF": + _W0C: + _name: Clear + Clear: [0, Clear flag] +PRLH: + PRLH: [0, 0xF] +PRLL: + PRLL: [0, 0xFFFF] +DIVH: + DIVH: [0, 0xF] +DIVL: + DIVL: [0, 0xFFFF] +CNT[HL]: + CNT[HL]: [0, 0xFFFF] +ALR[HL]: + ALR[HL]: [0, 0xFFFF] diff --git a/devices/fields/rtc/v2/basic.yaml b/devices/fields/rtc/v2/basic.yaml new file mode 100644 index 000000000..48ed84b35 --- /dev/null +++ b/devices/fields/rtc/v2/basic.yaml @@ -0,0 +1,157 @@ +# Real Time Clock + +TR: + PM: + AM: [0, AM or 24-hour format] + PM: [1, PM] + HT: [0, 3] + HU: [0, 15] + MNT: [0, 7] + MNU: [0, 15] + ST: [0, 7] + SU: [0, 15] +DR: + YT: [0, 15] + YU: [0, 15] + WDU: [1, 7] + MT: + Zero: [0, Month tens is 0] + One: [1, Month tens is 1] + MU: [0, 15] + DT: [0, 3] + DU: [0, 15] +CR: + COE: + Disabled: [0, Calibration output disabled] + Enabled: [1, Calibration output enabled] + OSEL: + Disabled: [0, Output disabled] + AlarmA: [1, Alarm A output enabled] + AlarmB: [2, Alarm B output enabled] + Wakeup: [3, Wakeup output enabled] + POL: + High: [0, "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"] + Low: [1, "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"] + BKP: + DST_Not_Changed: [0, Daylight Saving Time change has not been performed] + DST_Changed: [1, Daylight Saving Time change has been performed] + SUB1H: + _write: + Sub1: + [1, Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode] + ADD1H: + _write: + Add1: [1, Adds 1 hour to the current time. This can be used for summer time change outside initialization mode] + TSIE: + Disabled: [0, Time-stamp Interrupt disabled] + Enabled: [1, Time-stamp Interrupt enabled] + ALR[AB]IE: + Disabled: [0, Alarm Interrupt disabled] + Enabled: [1, Alarm Interrupt enabled] + TSE: + Disabled: [0, Timestamp disabled] + Enabled: [1, Timestamp enabled] + ALR[AB]E: + Disabled: [0, Alarm disabled] + Enabled: [1, Alarm enabled] + FMT: + Twenty_Four_Hour: [0, 24 hour/day format] + AM_PM: [1, AM/PM hour format] + REFCKON: + Disabled: [0, RTC_REFIN detection disabled] + Enabled: [1, RTC_REFIN detection enabled] + TSEDGE: + RisingEdge: [0, RTC_TS input rising edge generates a time-stamp event] + FallingEdge: [1, RTC_TS input falling edge generates a time-stamp event] +ISR: + TAMP*F: + _read: + Tampered: [1, This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input] + _W0C: + Clear: [0, Flag cleared by software writing 0] + TSOVF: + _read: + Overflow: [1, This flag is set by hardware when a time-stamp event occurs while TSF is already set] + _W0C: + Clear: [0, This flag is cleared by software by writing 0] + TSF: + _read: + TimestampEvent: [1, This flag is set by hardware when a time-stamp event occurs] + _W0C: + Clear: [0, This flag is cleared by software by writing 0] + ALR[AB]F: + _read: + Match: + [ + 1, + This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR), + ] + _W0C: + Clear: [0, This flag is cleared by software by writing 0] + INIT: + FreeRunningMode: [0, Free running mode] + InitMode: + [ + 1, + "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.", + ] + INITF: + _read: + NotAllowed: [0, Calendar registers update is not allowed] + Allowed: [1, Calendar registers update is allowed] + RSF: + _read: + NotSynced: [0, Calendar shadow registers not yet synchronized] + Synced: [1, Calendar shadow registers synchronized] + _W0C: + Clear: [0, This flag is cleared by software by writing 0] + INITS: + _read: + NotInitalized: [0, Calendar has not been initialized] + Initalized: [1, Calendar has been initialized] + ALR?WF: + _read: + UpdateNotAllowed: [0, Alarm update not allowed] + UpdateAllowed: [1, Alarm update allowed] +PRER: + PREDIV_A: [0, 0x7F] +ALRM?R: + MSK*: + Mask: [0, Alarm set if the date/day match] + NotMask: [1, "Date/day don’t care in Alarm comparison"] + WDSEL: + DateUnits: [0, "DU[3:0] represents the date units"] + WeekDay: [1, "DU[3:0] represents the week day. DT[1:0] is don’t care."] + DT: [0, 3] + DU: [0, 15] + PM: + AM: [0, AM or 24-hour format] + PM: [1, PM] + HT: [0, 3] + HU: [0, 15] + MNT: [0, 7] + MNU: [0, 15] + ST: [0, 7] + SU: [0, 15] +WPR: + KEY: [0, 255] +TSTR: + PM: + AM: [0, AM or 24-hour format] + PM: [1, PM] + HT: [0, 3] + HU: [0, 15] + MNT: [0, 7] + MNU: [0, 15] + ST: [0, 7] + SU: [0, 15] +TSDR: + WDU: [0, 3] + MT: + Zero: [0, Month tens is 0] + One: [1, Month tens is 1] + MU: [0, 7] + DT: [0, 3] + DU: [0, 15] +BKP?R: + BKP: [0, 0xFFFFFFFF] diff --git a/devices/fields/rtc/v2/common.yaml b/devices/fields/rtc/v2/common.yaml new file mode 100644 index 000000000..692d85444 --- /dev/null +++ b/devices/fields/rtc/v2/common.yaml @@ -0,0 +1,61 @@ +# Real Time Clock + +_include: + - basic.yaml + - wakeup.yaml + +CR: + COSEL: + CalFreq_512Hz: [0, Calibration output is 512 Hz (with default prescaler setting)] + CalFreq_1Hz: [1, Calibration output is 1 Hz (with default prescaler setting)] + BYPSHAD: + ShadowReg: + [ + 0, + "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles", + ] + BypassShadowReg: + [ + 1, + "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters", + ] + +ISR: + RECALPF: + _read: + Pending: + [ + 1, + "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0", + ] + SHPF: + _read: + NoShiftPending: [0, No shift operation is pending] + ShiftPending: [1, A shift operation is pending] +SSR: + SS: [0, 65535] +SHIFTR: + ADD1S: + _write: + Add1: [1, Add one second to the clock/calendar] + SUBFS: [0, 32767] +PRER: + PREDIV_S: [0, 0x7FFF] +TSSSR: + SS: [0, 65535] +CALR: + CALP: + NoChange: [0, No RTCCLK pulses are added] + IncreaseFreq: [1, "One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)"] + CALW8: + Eight_Second: [1, "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"] + CALW16: + Sixteen_Second: + [ + 1, + "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1", + ] + CALM: [0, 511] +ALRM?SSR: + MASKSS: [0, 15] + SS: [0, 32767] diff --git a/devices/fields/rtc/v2/f3.yaml b/devices/fields/rtc/v2/f3.yaml new file mode 100644 index 000000000..3f57a83ca --- /dev/null +++ b/devices/fields/rtc/v2/f3.yaml @@ -0,0 +1,55 @@ +# Real Time Clock for F3 Family + +TAFCR: + PC*MODE: + Floating: [0, PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode] + PushPull: [1, PCx is forced to push-pull output if LSE is disabled] + PC*VALUE: + High: [1, "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high"] + Low: [0, "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low"] + TAMPPUDIS: + Enabled: [0, Precharge RTC_TAMPx pins before sampling (enable internal pull-up)] + Disabled: [1, Disable precharge of RTC_TAMPx pins] + TAMPPRCH: + Cycles1: [0, 1 RTCCLK cycle] + Cycles2: [1, 2 RTCCLK cycles] + Cycles4: [2, 4 RTCCLK cycles] + Cycles8: [3, 8 RTCCLK cycles] + TAMPFLT: + Immediate: + [ + 0, + Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input), + ] + Samples2: [1, Tamper event is activated after 2 consecutive samples at the active level] + Samples4: [2, Tamper event is activated after 4 consecutive samples at the active level] + Samples8: [3, Tamper event is activated after 8 consecutive samples at the active level] + TAMPFREQ: + Div32768: [0, "RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)"] + Div16384: [1, "RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)"] + Div8192: [2, "RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)"] + Div4096: [3, "RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)"] + Div2048: [4, "RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)"] + Div1024: [5, "RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)"] + Div512: [6, "RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)"] + Div256: [7, "RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"] + TAMPTS: + NoSave: [0, Tamper detection event does not cause a timestamp to be saved] + Save: [1, Save timestamp on tamper detection event] + TAMP*TRG: + RisingEdge: + [ + 0, + "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.", + ] + FallingEdge: + [ + 1, + "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event", + ] + "TAMP[123]E": + Disabled: [0, RTC_TAMPx input detection disabled] + Enabled: [1, RTC_TAMPx input detection enabled] + TAMPIE: + Disabled: [0, Tamper interrupt disabled] + Enabled: [1, Tamper interrupt enabled] diff --git a/devices/fields/rtc/v2/h7.yaml b/devices/fields/rtc/v2/h7.yaml new file mode 100644 index 000000000..6e464d571 --- /dev/null +++ b/devices/fields/rtc/v2/h7.yaml @@ -0,0 +1,14 @@ +CR: + ITSE: + Disabled: [0, Internal event timestamp is disabled] + Enabled: [1, Internal event timestamp is enabled] +ISR: + ITSF: + _read: + Match: [1, This flag is set by hardware when a time-stamp on the internal event occurs] + _W0C: + Clear: + [ + 0, + "This flag is cleared by software by writing 0, and must be cleared together with TSF bit by writing 0 in both bits", + ] diff --git a/devices/fields/rtc/v2/l0.yaml b/devices/fields/rtc/v2/l0.yaml new file mode 100644 index 000000000..0aa585e00 --- /dev/null +++ b/devices/fields/rtc/v2/l0.yaml @@ -0,0 +1,69 @@ +# Real Time Clock for L0 Family + +TAMPCR: + TAMP*MF: + NotMasked: + [ + 0, + Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection, + ] + Masked: + [ + 1, + Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased., + ] + TAMP*NOERASE: + Erase: [0, Tamper x event erases the backup registers] + NoErase: [1, Tamper x event does not erase the backup registers] + "TAMP[123]IE": + Disabled: [0, "Tamper x interrupt is disabled if TAMPIE = 0"] + Enabled: [1, Tamper x interrupt enabled] + TAMPPUDIS: + Enabled: [0, Precharge RTC_TAMPx pins before sampling (enable internal pull-up)] + Disabled: [1, Disable precharge of RTC_TAMPx pins] + TAMPPRCH: + Cycles1: [0, 1 RTCCLK cycle] + Cycles2: [1, 2 RTCCLK cycles] + Cycles4: [2, 4 RTCCLK cycles] + Cycles8: [3, 8 RTCCLK cycles] + TAMPFLT: + Immediate: + [ + 0, + Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input), + ] + Samples2: [1, Tamper event is activated after 2 consecutive samples at the active level] + Samples4: [2, Tamper event is activated after 4 consecutive samples at the active level] + Samples8: [3, Tamper event is activated after 8 consecutive samples at the active level] + TAMPFREQ: + Div32768: [0, "RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)"] + Div16384: [1, "RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)"] + Div8192: [2, "RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)"] + Div4096: [3, "RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)"] + Div2048: [4, "RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)"] + Div1024: [5, "RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)"] + Div512: [6, "RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)"] + Div256: [7, "RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"] + TAMPTS: + NoSave: [0, Tamper detection event does not cause a timestamp to be saved] + Save: [1, Save timestamp on tamper detection event] + TAMP*TRG: + RisingEdge: + [ + 0, + "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event.", + ] + FallingEdge: + [ + 1, + "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event", + ] + "TAMP[123]E": + Disabled: [0, RTC_TAMPx input detection disabled] + Enabled: [1, RTC_TAMPx input detection enabled] + TAMPIE: + Disabled: [0, Tamper interrupt disabled] + Enabled: [1, Tamper interrupt enabled] +OR: + RTC_OUT_RMP: [0, 1] + RTC_ALARM_TYPE: [0, 1] diff --git a/devices/fields/rtc/v2/wakeup.yaml b/devices/fields/rtc/v2/wakeup.yaml new file mode 100644 index 000000000..49ba85fd9 --- /dev/null +++ b/devices/fields/rtc/v2/wakeup.yaml @@ -0,0 +1,28 @@ +# Real Time Clock + +CR: + WUTIE: + Disabled: [0, Wakeup timer interrupt disabled] + Enabled: [1, Wakeup timer interrupt enabled] + WUTE: + Disabled: [0, Wakeup timer disabled] + Enabled: [1, Wakeup timer enabled] + WUCKSEL: + Div16: [0, RTC/16 clock is selected] + Div8: [1, RTC/8 clock is selected] + Div4: [2, RTC/4 clock is selected] + Div2: [3, RTC/2 clock is selected] + ClockSpare: [4, ck_spre (usually 1 Hz) clock is selected] + ClockSpareWithOffset: [6, ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value] +ISR: + WUTF: + _read: + Zero: [1, This flag is set by hardware when the wakeup auto-reload counter reaches 0] + _W0C: + Clear: [0, This flag is cleared by software by writing 0] + WUTWF: + _read: + UpdateNotAllowed: [0, Wakeup timer configuration update not allowed] + UpdateAllowed: [1, Wakeup timer configuration update allowed] +WUTR: + WUT: [0, 0xFFFF] diff --git a/devices/fields/rtc/v3/basic.yaml b/devices/fields/rtc/v3/basic.yaml new file mode 100644 index 000000000..96c74e9d2 --- /dev/null +++ b/devices/fields/rtc/v3/basic.yaml @@ -0,0 +1,208 @@ +TR: + PM: + AM: [0, AM or 24-hour format] + PM: [1, PM] + HT: [0, 3] + HU: [0, 15] + MNT: [0, 7] + MNU: [0, 15] + ST: [0, 7] + SU: [0, 15] +DR: + YT: [0, 15] + YU: [0, 15] + WDU: [1, 7] + MT: [0, 1] + MU: [0, 15] + DT: [0, 3] + DU: [0, 15] + +SSR: + SS: [0, 65535] + +ICSR: + RECALPF: + _read: + Pending: + [ + 1, + "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0", + ] + INIT: + FreeRunningMode: [0, Free running mode] + InitMode: + [ + 1, + "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset.", + ] + INITF: + _read: + NotAllowed: [0, Calendar registers update is not allowed] + Allowed: [1, Calendar registers update is allowed] + RSF: + _read: + NotSynced: [0, Calendar shadow registers not yet synchronized] + Synced: [1, Calendar shadow registers synchronized] + _W0C: + Clear: [0, This flag is cleared by software by writing 0] + INITS: + _read: + NotInitalized: [0, Calendar has not been initialized] + Initalized: [1, Calendar has been initialized] + SHPF: + _read: + NoShiftPending: [0, No shift operation is pending] + ShiftPending: [1, A shift operation is pending] + +PRER: + PREDIV_A: [0, 0x7F] + PREDIV_S: [0, 0x7FFF] + +CR: + OUT2EN: + Disabled: [0, RTC output 2 disable] + Enabled: [1, RTC output 2 enable] + TAMPALRM_TYPE: + PushPull: [0, TAMPALRM is push-pull output] + OpenDrain: [1, TAMPALRM is open-drain output] + TAMPALRM_PU: + NoPullUp: [0, No pull-up is applied on TAMPALRM output] + PullUp: [1, A pull-up is applied on TAMPALRM output] + COE: + Disabled: [0, Calibration output disabled] + Enabled: [1, Calibration output enabled] + OSEL: + Disabled: [0, Output disabled] + AlarmA: [1, Alarm A output enabled] + AlarmB: [2, Alarm B output enabled] + Wakeup: [3, Wakeup output enabled] + POL: + High: [0, "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"] + Low: [1, "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"] + COSEL: + CalFreq_512Hz: [0, Calibration output is 512 Hz (with default prescaler setting)] + CalFreq_1Hz: [1, Calibration output is 1 Hz (with default prescaler setting)] + BKP: + DSTNotChanged: [0, Daylight Saving Time change has not been performed] + DSTChanged: [1, Daylight Saving Time change has been performed] + SUB1H: + _write: + Sub1: + [1, Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode] + ADD1H: + _write: + Add1: [1, Adds 1 hour to the current time. This can be used for summer time change outside initialization mode] + TSIE: + Disabled: [0, Time-stamp Interrupt disabled] + Enabled: [1, Time-stamp Interrupt enabled] + ALR[AB]IE: + Disabled: [0, Alarm Interrupt disabled] + Enabled: [1, Alarm Interrupt enabled] + TSE: + Disabled: [0, Timestamp disabled] + Enabled: [1, Timestamp enabled] + ALR[AB]E: + Disabled: [0, Alarm disabled] + Enabled: [1, Alarm enabled] + FMT: + TwentyFourHour: [0, 24 hour/day format] + AmPm: [1, AM/PM hour format] + BYPSHAD: + ShadowReg: + [ + 0, + "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles", + ] + BypassShadowReg: + [ + 1, + "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters", + ] + REFCKON: + Disabled: [0, RTC_REFIN detection disabled] + Enabled: [1, RTC_REFIN detection enabled] + TSEDGE: + RisingEdge: [0, RTC_TS input rising edge generates a time-stamp event] + FallingEdge: [1, RTC_TS input falling edge generates a time-stamp event] + +WPR: + KEY: + Deactivate1: [0xCA, Key 1] + Deactivate2: [0x53, Key 2] + Activate: [0x0, Activate write protection (any value that is not the keys)] + +CALR: + CALP: + NoChange: [0, No RTCCLK pulses are added] + IncreaseFreq: [1, "One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)"] + CALW8: + EightSeconds: [1, "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"] + CALW16: + SixteenSeconds: + [ + 1, + "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1", + ] + + CALM: [0, 511] + +SHIFTR: + ADD1S: + _write: + Add1: [1, Add one second to the clock/calendar] + SUBFS: [0, 32767] + +TSTR: + PM: + AM: [0, AM or 24-hour format] + PM: [1, PM] + +ALRM[AB]R: + MSK*: + Mask: [0, Alarm set if the date/day match] + NotMask: [1, "Date/day don’t care in Alarm comparison"] + WDSEL: + DateUnits: [0, "DU[3:0] represents the date units"] + WeekDay: [1, "DU[3:0] represents the week day. DT[1:0] is don’t care."] + DT: [0, 3] + DU: [0, 15] + PM: + AM: [0, AM or 24-hour format] + PM: [1, PM] + HT: [0, 3] + HU: [0, 15] + MNT: [0, 7] + MNU: [0, 15] + ST: [0, 7] + SU: [0, 15] + +ALRM?SSR: + SS: [0, 0x7FFF] + +SR: + TSOVF: + Overflow: [1, This flag is set by hardware when a time-stamp event occurs while TSF is already set] + TSF: + TimestampEvent: [1, This flag is set by hardware when a time-stamp event occurs] + ALR[AB]F: + Match: + [ + 1, + This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRxBR), + ] + +MISR: + TSOVMF: + Overflow: [1, This flag is set by hardware when a time-stamp event occurs while TSF is already set] + TSMF: + TimestampEvent: [1, This flag is set by hardware when a time-stamp event occurs] + ALR[AB]MF: + Match: + [ + 1, + This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm register (RTC_ALRMxR), + ] + +SCR: + "*": + Clear: [1, Clear interrupt flag] diff --git a/devices/fields/rtc/v3/common.yaml b/devices/fields/rtc/v3/common.yaml new file mode 100644 index 000000000..a7029e05b --- /dev/null +++ b/devices/fields/rtc/v3/common.yaml @@ -0,0 +1,4 @@ +_include: + - basic.yaml + - tamper.yaml + - wakeup.yaml diff --git a/devices/fields/rtc/v3/tamper.yaml b/devices/fields/rtc/v3/tamper.yaml new file mode 100644 index 000000000..3bf6d4444 --- /dev/null +++ b/devices/fields/rtc/v3/tamper.yaml @@ -0,0 +1,22 @@ +CR: + TAMPOE: + Disabled: [0, The tamper flag is not routed on TAMPALRM] + Enabled: + [ + 1, + "The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL", + ] + TAMPTS: + Disabled: [0, Tamper detection event does not cause a RTC timestamp to be saved] + Enabled: [1, Save RTC timestamp on tamper detection event] + ITSE: + Disabled: [0, Internal event timestamp disabled] + Enabled: [1, Internal event timestamp enabled] + +SR: + ITSF: + TimestampEvent: [1, This flag is set by hardware when a timestamp on the internal event occurs] + +MISR: + ITSMF: + TimestampEvent: [1, This flag is set by hardware when a timestamp on the internal event occurs] diff --git a/devices/fields/rtc/v3/wakeup.yaml b/devices/fields/rtc/v3/wakeup.yaml new file mode 100644 index 000000000..16294bbf4 --- /dev/null +++ b/devices/fields/rtc/v3/wakeup.yaml @@ -0,0 +1,31 @@ +CR: + WUTIE: + Disabled: [0, Wakeup timer interrupt disabled] + Enabled: [1, Wakeup timer interrupt enabled] + WUTE: + Disabled: [0, Wakeup timer disabled] + Enabled: [1, Wakeup timer enabled] + WUCKSEL: + Div16: [0, RTC/16 clock is selected] + Div8: [1, RTC/8 clock is selected] + Div4: [2, RTC/4 clock is selected] + Div2: [3, RTC/2 clock is selected] + ClockSpare: [4, ck_spre (usually 1 Hz) clock is selected] + ClockSpareWithOffset: [6, "ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value"] + +SR: + WUTF: + Zero: [1, This flag is set by hardware when the wakeup auto-reload counter reaches 0] + +MISR: + WUTMF: + Zero: [1, This flag is set by hardware when the wakeup auto-reload counter reaches 0] + +ICSR: + WUTWF: + _read: + UpdateNotAllowed: [0, Wakeup timer configuration update not allowed] + UpdateAllowed: [1, Wakeup timer configuration update allowed] + +WUTR: + WUT: [0, 0xFFFF] diff --git a/devices/fields/rtc/v3/wl.yaml b/devices/fields/rtc/v3/wl.yaml new file mode 100644 index 000000000..0009e8cf5 --- /dev/null +++ b/devices/fields/rtc/v3/wl.yaml @@ -0,0 +1,53 @@ +_include: common.yaml + +CR: + SSRUIE: + Disabled: [0, SSR underflow interrupt disabled] + Enabled: [1, SSR underflow interrupt enabled] + +ICSR: + BCDU: + Bit7: [0, "1s increment each time SS[7:0]=0"] + Bit8: [1, "1s increment each time SS[8:0]=0"] + Bit9: [2, "1s increment each time SS[9:0]=0"] + Bit10: [3, "1s increment each time SS[10:0]=0"] + Bit11: [4, "1s increment each time SS[11:0]=0"] + Bit12: [5, "1s increment each time SS[12:0]=0"] + Bit13: [6, "1s increment each time SS[13:0]=0"] + Bit14: [7, "1s increment each time SS[14:0]=0"] + BIN: + BCD: [0, Free running BCD calendar mode (Binary mode disabled)] + Binary: [1, Free running Binary mode (BCD mode disabled)] + BinBCD: [2, Free running BCD calendar and Binary modes] + BinBCD2: [3, Free running BCD calendar and Binary modes] + +WUTR: + WUTOCLR: [0, 0xFFFF] +CALR: + LPCAL: + RTCCLK: + [ + 0, + "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required", + ] + CkApre: [1, "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode"] +ALRM?SSR: + SSCLR: + FreeRunning: [0, "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running"] + ALRMBINR: + [ + 1, + "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]", + ] + MASKSS: [0, 0x3F] + +SR: + SSRUF: + Underflow: [1, "This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1"] + +MISR: + SSRUMF: + Underflow: [1, "This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1"] + +ALR?BINR: + SS: [0, 0xFFFFFFFF] diff --git a/devices/fields/sai/sai.yaml b/devices/fields/sai/sai.yaml new file mode 100644 index 000000000..473a3061f --- /dev/null +++ b/devices/fields/sai/sai.yaml @@ -0,0 +1,190 @@ +"*CR1": + #MCKDIV: + "NODIV,NOMCK": + MasterClock: + [0, MCLK output is enabled. Forces the ratio between FS and MCLK to 256 or 512 according to the OSR value] + NoDiv: + [1, "MCLK output enable set by the MCKEN bit (where present, else 0). Ratio between FS and MCLK depends on FRL."] + DMAEN: + Disabled: [0, DMA disabled] + Enabled: [1, DMA enabled] + SAIEN,SAI?EN: + Disabled: [0, SAI audio block disabled] + Enabled: [1, SAI audio block enabled] + OUTDRIV: + OnStart: [0, Audio block output driven when SAIEN is set] + Immediately: [1, Audio block output driven immediately after the setting of this bit] + MONO: + Stereo: [0, Stereo mode] + Mono: [1, Mono mode] + SYNCEN: + Asynchronous: [0, audio sub-block in asynchronous mode] + Internal: + [ + 1, + "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode", + ] + External: + [ + 2, + audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode, + ] + CKSTR: + FallingEdge: [0, Data strobing edge is falling edge of SCK] + RisingEdge: [1, Data strobing edge is rising edge of SCK] + LSBFIRST: + MsbFirst: [0, Data are transferred with MSB first] + LsbFirst: [1, Data are transferred with LSB first] + DS: + Bit8: [2, 8 bits] + Bit10: [3, 10 bits] + Bit16: [4, 16 bits] + Bit20: [5, 20 bits] + Bit24: [6, 24 bits] + Bit32: [7, 32 bits] + PRTCFG: + Free: + [ + 0, + Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol, + ] + Spdif: [1, SPDIF protocol] + Ac97: [2, "AC’97 protocol"] + MODE: + MasterTx: [0, Master transmitter] + MasterRx: [1, Master receiver] + SlaveTx: [2, Slave transmitter] + SlaveRx: [3, Slave receiver] + +"*CR2": + COMP: + NoCompanding: [0, No companding algorithm] + MuLaw: [2, μ-Law algorithm] + ALaw: [3, A-Law algorithm] + CPL: + OnesComplement: [0, "1’s complement representation"] + TwosComplement: [1, "2’s complement representation"] + #MUTECN,MUTECNT: + MUTEVAL: + SendZero: [0, Bit value 0 is sent during the mute mode] + SendLast: [1, Last values are sent during the mute mode] + MUTE: + Disabled: [0, No mute mode] + Enabled: [1, Mute mode enabled] + #TRIS: + FFLUSH: + NoFlush: [0, No FIFO flush] + Flush: + [ + 1, + FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared, + ] + FTH: + Empty: [0, FIFO empty] + Quarter1: [1, "1⁄4 FIFO"] + Quarter2: [2, "1⁄2 FIFO"] + Quarter3: [3, "3⁄4 FIFO"] + Full: [4, FIFO full] + +"*FRCR": + FSOFF: + OnFirst: [0, FS is asserted on the first bit of the slot 0] + BeforeFirst: [1, FS is asserted one bit before the first bit of the slot 0] + FSPOL: + FallingEdge: [0, FS is active low (falling edge)] + RisingEdge: [1, FS is active high (rising edge)] + #FSDEF: + #FSALL: + #FRL: + +"*SLOTR": + SLOTEN: + Inactive: [0, Inactive slot] + Active: [1, Active slot] + #NBSLOT: + SLOTSZ: + DataSize: [0, "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)"] + Bit16: [1, 16-bit] + Bit32: [2, 32-bit] + #FBOFF: + +"*IM": + LFSDETIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is enabled] + AFSDETIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is enabled] + CNRDYIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is enabled] + FREQIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is enabled] + WCKCFGIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is enabled] + MUTEDETIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is enabled] + OVRUDRIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is enabled] + +"*SR": + FLTH,FLVL: + _read: + Empty: [0, FIFO empty] + Quarter1: [1, "FIFO <= 1⁄4 but not empty"] + Quarter2: [2, "1⁄4 < FIFO <= 1⁄2"] + Quarter3: [3, "1⁄2 < FIFO <= 3⁄4"] + Quarter4: [4, "3⁄4 < FIFO but not full"] + Full: [5, FIFO full] + LFSDET: + _read: + NoError: [0, No error] + NoSync: [1, Frame synchronization signal is not present at the right time] + AFSDET: + _read: + NoError: [0, No error] + EarlySync: [1, Frame synchronization signal is detected earlier than expected] + CNRDY: + _read: + Ready: [0, "External AC’97 Codec is ready"] + NotReady: [1, "External AC’97 Codec is not ready"] + FREQ: + _read: + NoRequest: [0, No FIFO request] + Request: [1, FIFO request to read or to write the SAI_xDR] + WCKCFG: + _read: + Correct: [0, Clock configuration is correct] + Wrong: [1, Clock configuration does not respect the rule concerning the frame length specification] + MUTEDET: + _read: + NoMute: [0, No MUTE detection on the SD input line] + Mute: [1, MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame] + OVRUDR: + _read: + NoError: [0, No overrun/underrun error] + Overrun: [1, Overrun/underrun error detection] + +"*CLRFR": + CLFSDET: + _write: + Clear: [1, Clears the LFSDET flag] + CAFSDET: + _write: + Clear: [1, Clears the AFSDET flag] + CCNRDY: + _write: + Clear: [1, Clears the CNRDY flag] + CWCKCFG: + _write: + Clear: [1, Clears the WCKCFG flag] + CMUTEDET: + _write: + Clear: [1, Clears the MUTEDET flag] + COVRUDR: + _write: + Clear: [1, Clears the OVRUDR flag] diff --git a/devices/fields/sbs/sbs.yaml b/devices/fields/sbs/sbs.yaml new file mode 100644 index 000000000..b25dd867f --- /dev/null +++ b/devices/fields/sbs/sbs.yaml @@ -0,0 +1,96 @@ +# System configuration, boot, and security (SBS). Applicable to H5 family, at least. + +HDPLCR: + INCR_HDPL: + Increment: [0x6A, Increment HDPL value] + +HDPLSR: + HDPL: + _read: + HDPL0: [0xB4, Protection level reserved for ST code and data] + HDPL1: [0x51, Protection level to be used to execute and protect immutable Root of Trust (IROT) stage] + HDPL2: [0x8A, Protection level to be used to execute and protect an updatable Root of Trust (UROT) stage] + HDPL3: [0x6F, Protection level to be used to execute the application] + +DBGCR: + DBG_AUTH_HDPL: + HDPL1: [0x51, Protection level to be used to execute and protect immutable Root of Trust (IROT) stage] + HDPL2: [0x8A, Protection level to be used to execute and protect an updatable Root of Trust (UROT) stage] + HDPL3: [0x6F, Protection level to be used to execute the application] + DBG_UNLOCK: + Unlocked: [0xB4, "Debug unlocked when HDPLSR:HDPL is equal to DBG_AUTH_HDPL"] + AP_UNLOCK: + Unlocked: [0xB4, Device access port unlocked] + +DBGLOCKR: + DBGCFG_LOCK: + _write: + Locked: [0xC3, Debug configuration register (DBGCR) locked] + Unlocked: [0xB4, Debug configuration register (DBGCR) unlocked] + _read: + Locked: [0x6A, Debug configuration register (DBGCR) locked] + Unlocked: [0xB4, Debug configuration register (DBGCR) unlocked] + +PMCR: + PB8_FMP: + Disabled: [0, Fast-mode Plus mode on PB8 disabled] + Enabled: [1, Fast-mode Plus mode on PB8 enabled] + PB7_FMP: + Disabled: [0, Fast-mode Plus mode on PB7 disabled] + Enabled: [1, Fast-mode Plus mode on PB7 enabled] + PB6_FMP: + Disabled: [0, Fast-mode Plus mode on PB6 disabled] + Enabled: [1, Fast-mode Plus mode on PB6 enabled] + +FPUIMR: + FPU_IE?: + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + +MESR: + IPMEE: + _read: + EraseInProgress: [0, ICACHE erase ongoing] + EraseCompleted: [1, ICACHE erase completed] + _W1C: + Clear: [1, Clear ICACHE erase status flag] + MCLR: + _read: + EraseInProgress: [0, Memory erase in progress] + EraseComplete: [1, Memory erase complete] + _W1C: + Clear: [1, Clear memory erase status flag] + +CCCSR: + RDY?: + _read: + NotReady: [0, VDDIO compensation cell not ready] + Ready: [1, VDDIO compensation cell ready] + CS?: + Cell: [0, Code from cell selected] + CCSWCR: [1, Code from CCSWCR selected] + EN?: + Disabled: [0, I/O compensation cell disabled] + Enabled: [1, I/O compensation cell enabled] + +CCSWCR: + SW_APSRC?: [0, 0xF] + SW_ANSRC?: [0, 0xF] + +CFGR2: + "*L": + Disconnected: [0, Flag/Interrupt disconnected from timer break inputs] + Connected: [1, Flag/Interrupt connected to timer break inputs] + +CNSLCKR: + LOCKNSMPU: + Unlocked: [0, MPU registers write enabled] + Locked: [1, MPU registers write disabled] + LOCKNSVTOR: + Unlocked: [0, VTOR_NS register write enabled] + Locked: [1, VTOR_NS register write disabled] + +ECCNMIR: + ECCNMI_MASK_EN: + Enabled: [0, NMI enabled] + Disabled: [1, NMI disabled] diff --git a/devices/fields/sdio/v1-ata.yaml b/devices/fields/sdio/v1-ata.yaml new file mode 100644 index 000000000..92bde2769 --- /dev/null +++ b/devices/fields/sdio/v1-ata.yaml @@ -0,0 +1,24 @@ +_include: + - v1.yaml + +CMD: + CE_ATACMD: + Disabled: [0, CE-ATA command disabled] + Enabled: [1, CE-ATA command enabled] + nIEN: + Disabled: [0, Interrupts to the CE-ATA not disabled] + Enabled: [1, Interrupt to the CE-ATA are disabled] + ENCMDcompl: + Disabled: [0, Command complete signal disabled] + Enabled: [1, Command complete signal enabled] + +STA: + CEATAEND: + NotReceived: [0, Completion signal not received] + Received: [1, CE-ATA command completion signal received for CMD61] + STBITERR: + Detected: [0, No start bit detected error] + NotDetected: [1, Start bit not detected error] + +DCTRL: + DBLOCKSIZE: [0, 0xF] diff --git a/devices/fields/sdio/v1.yaml b/devices/fields/sdio/v1.yaml new file mode 100644 index 000000000..7ae18d234 --- /dev/null +++ b/devices/fields/sdio/v1.yaml @@ -0,0 +1,182 @@ +POWER: + PWRCTRL: + PowerOff: [0, Power off] + PowerOn: [3, Power on] + +CLKCR: + HWFC_EN: + Disabled: [0, HW Flow Control is disabled] + Enabled: [1, HW Flow Control is enabled] + NEGEDGE: + Rising: [0, SDIO_CK generated on the rising edge] + Falling: [1, SDIO_CK generated on the falling edge] + WIDBUS: + BusWidth1: [0, 1 lane wide bus] + BusWidth4: [1, 4 lane wide bus] + BusWidth8: [2, 8 lane wide bus] + BYPASS: + Disabled: [0, SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal.] + Enabled: [1, SDIOCLK directly drives the SDIO_CK output signal] + PWRSAV: + Disabled: [1, SDIO_CK is only enabled when the bus is active] + Enabled: [0, SDIO_CK clock is always enabled] + CLKEN: + Disabled: [0, Disable clock] + Enabled: [1, Enable clock] + CLKDIV: [0, 0xFF] + +ARG: + CMDARG: [0, 0xFFFFFFFF] + +CMD: + SDIOSuspend: + Disabled: [0, Next command is not a SDIO suspend command] + Enabled: [1, Next command send is a SDIO suspend command] + CPSMEN: + Disabled: [0, Command path state machine disabled] + Enabled: [1, Command path state machine enabled] + WAITPEND: + Disabled: [0, Don't wait for data end] + Enabled: [1, Wait for end of data transfer signal before sending command] + WAITINT: + Disabled: [0, Don't wait for interrupt request] + Enabled: [1, Wait for interrupt request] + WAITRESP: + NoResponse: [0, No response] + ShortResponse: [1, Short response] + NoResponse2: [2, No reponse] + LongResponse: [3, Long reponse] + CMDINDEX: [0, 0x3F] + +RESPCMD: + RESPCMD: [0, 0x3F] + +RESP?: + CARDSTATUS: [0, 0xFFFFFFFF] + +DTIMER: + DATATIME: [0, 0xFFFFFFFF] + +DLEN: + DATALENGTH: [0, 0x01FFFFFF] + +DCTRL: + SDIOEN: + Disabled: [0, SDIO operations disabled] + Enabled: [1, SDIO operations enabled] + RWMOD: + D2: [0, Read wait control stopping using SDIO_D2] + Ck: [1, Read wait control using SDIO_CK] + RWSTOP: + Disabled: [0, Read wait in progress if RWSTART is enabled] + Enabled: [1, Enable for read wait stop if RWSTART is enabled] + RWSTART: + Disabled: [0, Don't start read wait operation] + Enabled: [1, Read wait operation starts] + DMAEN: + Disabled: [0, Dma disabled] + Enabled: [1, Dma enabled] + DTMODE: + BlockMode: [0, Bloack data transfer] + StreamMode: [1, Stream or SDIO multibyte data transfer] + DTDIR: + ControllerToCard: [0, From controller to card] + CardToController: [1, From card to controller] + DTEN: + Disabled: [0, Disabled] + Enabled: [1, Start transfer] + +DCOUNT: + DATACOUNT: [0, 0x01FFFFFF] + +STA: + SDIOIT: + NotReceived: [0, SDIO interrupt not receieved] + Received: [1, SDIO interrupt received] + RXDAVL: + NotAvailable: [0, Data not available in receive FIFO] + Available: [1, Data available in receive FIFO] + TXDAVL: + NotAvailable: [0, Data not available in transmit FIFO] + Available: [1, Data available in transmit FIFO] + RXFIFOE: + NotEmpty: [0, Receive FIFO not empty] + Empty: [1, Receive FIFO empty] + TXFIFOE: + NotEmpty: [0, Transmit FIFO not empty] + Empty: + [ + 1, + "Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words.", + ] + RXFIFOF: + NotFull: [0, Transmit FIFO not full] + Full: + [ + 1, + "Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full.", + ] + TXFIFOF: + NotFull: [0, Transmit FIFO not full] + Full: [1, Transmit FIFO full] + RXFIFOHF: + NotHalfFull: [0, Receive FIFO not half full] + HalfFull: [1, Receive FIFO half full. At least 8 words in the FIFO] + TXFIFOHE: + NotHalfEmpty: [0, Transmit FIFO not half empty] + HalfEmpty: [1, Transmit FIFO half empty. At least 8 words can be written into the FIFO] + RXACT: + NotInProgress: [0, Data receive not in progress] + InProgress: [1, Data receive in progress] + TXACT: + NotInProgress: [0, Data transmit is not in progress] + InProgress: [1, Data transmit in progress] + CMDACT: + NotInProgress: [0, Command transfer not in progress] + InProgress: [1, Command tranfer in progress] + DBCKEND: + NotTransferred: [0, Data block not sent/received (CRC check failed)] + Transferred: [1, Data block sent/received (CRC check passed)] + DATAEND: + Done: [1, "Data end (DCOUNT, is zero)"] + NotDone: [0, Not done] + CMDSENT: + NotSent: [0, Command not sent] + Sent: [1, Command sent (no response required)] + CMDREND: + NotDone: [0, Command not done] + Done: [1, Command response received (CRC check passed)] + RXOVERR: + NoOverrun: [0, No FIFO overrun error] + Overrun: [1, Receive FIFO overrun error] + TXUNDERR: + NoUnderrun: [0, No transmit FIFO underrun error] + Underrun: [1, Transmit FIFO underrun error] + DTIMEOUT: + NoTimeout: [0, No data timeout] + Timeout: [1, Data timeout] + CTIMEOUT: + NoTimeout: [0, No Command timeout] + Timeout: [1, Command timeout] + DCRCFAIL: + NotFailed: [0, No Data block sent/received crc check fail] + Failed: [1, Data block sent/received crc failed] + CCRCFAIL: + NotFailed: [0, "Command response received, crc check passed"] + Failed: [1, "Command response received, crc check failed"] + +ICR: + "*C": + _write: + Clear: [1, Clear flag] + +MASK: + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + +FIFOCNT: + FIFOCOUNT: [0, 0x00FFFFFF] + +FIFO: + FIFOData: [0, 0xFFFFFFFF] diff --git a/devices/fields/spi/dff.yaml b/devices/fields/spi/dff.yaml new file mode 100644 index 000000000..c9685c7cd --- /dev/null +++ b/devices/fields/spi/dff.yaml @@ -0,0 +1,4 @@ +CR1: + DFF: + EightBit: [0, 8-bit data frame format is selected for transmission/reception] + SixteenBit: [1, 16-bit data frame format is selected for transmission/reception] diff --git a/devices/fields/spi/spi_FRF_FRE.yaml b/devices/fields/spi/spi_FRF_FRE.yaml new file mode 100644 index 000000000..a71335662 --- /dev/null +++ b/devices/fields/spi/spi_FRF_FRE.yaml @@ -0,0 +1,9 @@ +CR2: + FRF: + Motorola: [0, SPI Motorola mode] + TI: [1, SPI TI mode] +SR: + FRE,TIFRFE: + _read: + NoError: [0, No frame format error] + Error: [1, A frame format error occurred] diff --git a/devices/fields/spi/spi_I2S.yaml b/devices/fields/spi/spi_I2S.yaml new file mode 100644 index 000000000..58e41af89 --- /dev/null +++ b/devices/fields/spi/spi_I2S.yaml @@ -0,0 +1,42 @@ +I2SCFGR: + I2SMOD: + SPIMode: [0, SPI mode is selected] + I2SMode: [1, I2S mode is selected] + I2SE: + Disabled: [0, I2S peripheral is disabled] + Enabled: [1, I2S peripheral is enabled] + I2SCFG: + SlaveTx: [0, Slave - transmit] + SlaveRx: [1, Slave - receive] + MasterTx: [2, Master - transmit] + MasterRx: [3, Master - receive] + PCMSYNC: + Short: [0, Short frame synchronisation] + Long: [1, Long frame synchronisation] + I2SSTD: + Philips: [0, I2S Philips standard] + MSB: [1, MSB justified standard] + LSB: [2, LSB justified standard] + PCM: [3, PCM standard] + CKPOL: + IdleLow: [0, I2S clock inactive state is low level] + IdleHigh: [1, I2S clock inactive state is high level] + DATLEN: + SixteenBit: [0, 16-bit data length] + TwentyFourBit: [1, 24-bit data length] + ThirtyTwoBit: [2, 32-bit data length] + CHLEN: + SixteenBit: [0, 16-bit wide] + ThirtyTwoBit: [1, 32-bit wide] + "?~ASTRTEN": + AsyncStartDisabled: [0, Asynchronous start disabled] + AsyncStartEnabled: [1, Asynchronous start enabled] + +I2SPR: + MCKOE: + Disabled: [0, Master clock output is disabled] + Enabled: [1, Master clock output is enabled] + ODD: + Even: [0, Real divider value is I2SDIV * 2] + Odd: [1, Real divider value is (I2SDIV * 2) + 1] + I2SDIV: [2, 255] diff --git a/devices/fields/spi/spi_SR_UDR_CHSIDE.yaml b/devices/fields/spi/spi_SR_UDR_CHSIDE.yaml new file mode 100644 index 000000000..d6fd4bd73 --- /dev/null +++ b/devices/fields/spi/spi_SR_UDR_CHSIDE.yaml @@ -0,0 +1,8 @@ +SR: + UDR: + _read: + NoUnderrun: [0, No underrun occurred] + Underrun: [1, Underrun occurred] + CHSIDE: + Left: [0, Channel left has to be transmitted or has been received] + Right: [1, Channel right has to be transmitted or has been received] diff --git a/devices/fields/spi/spi_common.yaml b/devices/fields/spi/spi_common.yaml new file mode 100644 index 000000000..a2f222fe0 --- /dev/null +++ b/devices/fields/spi/spi_common.yaml @@ -0,0 +1,102 @@ +# Common fields between SPIv1 and SPIv2 (most of them) +# Note that frustratingly the peripheral everything else derives from +# is occasionally I2S2ext instead of SPI1 in the SVD. + +CR1: + BIDIMODE: + Unidirectional: [0, 2-line unidirectional data mode selected] + Bidirectional: [1, 1-line bidirectional data mode selected] + BIDIOE: + OutputDisabled: [0, Output disabled (receive-only mode)] + OutputEnabled: [1, Output enabled (transmit-only mode)] + CRCEN: + Disabled: [0, CRC calculation disabled] + Enabled: [1, CRC calculation enabled] + CRCNEXT: + TxBuffer: [0, Next transmit value is from Tx buffer] + CRC: [1, Next transmit value is from Tx CRC register] + RXONLY: + FullDuplex: [0, Full duplex (Transmit and receive)] + OutputDisabled: [1, Output disabled (Receive-only mode)] + SSM: + Disabled: [0, Software slave management disabled] + Enabled: [1, Software slave management enabled] + SSI: + SlaveSelected: [0, 0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored] + SlaveNotSelected: [1, 1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored] + LSBFIRST: + MSBFirst: [0, Data is transmitted/received with the MSB first] + LSBFirst: [1, Data is transmitted/received with the LSB first] + SPE: + Disabled: [0, Peripheral disabled] + Enabled: [1, Peripheral enabled] + BR: + Div2: [0, f_PCLK / 2] + Div4: [1, f_PCLK / 4] + Div8: [2, f_PCLK / 8] + Div16: [3, f_PCLK / 16] + Div32: [4, f_PCLK / 32] + Div64: [5, f_PCLK / 64] + Div128: [6, f_PCLK / 128] + Div256: [7, f_PCLK / 256] + MSTR: + Slave: [0, Slave configuration] + Master: [1, Master configuration] + CPOL: + IdleLow: [0, CK to 0 when idle] + IdleHigh: [1, CK to 1 when idle] + CPHA: + FirstEdge: [0, The first clock transition is the first data capture edge] + SecondEdge: [1, The second clock transition is the first data capture edge] +CR2: + TXEIE: + Masked: [0, TXE interrupt masked] + NotMasked: [1, TXE interrupt not masked] + RXNEIE: + Masked: [0, RXE interrupt masked] + NotMasked: [1, RXE interrupt not masked] + ERRIE: + Masked: [0, Error interrupt masked] + NotMasked: [1, Error interrupt not masked] + SSOE: + Disabled: [0, SS output is disabled in master mode] + Enabled: [1, SS output is enabled in master mode] + TXDMAEN: + Disabled: [0, Tx buffer DMA disabled] + Enabled: [1, Tx buffer DMA enabled] + RXDMAEN: + Disabled: [0, Rx buffer DMA disabled] + Enabled: [1, Rx buffer DMA enabled] +SR: + BSY: + _read: + NotBusy: [0, SPI not busy] + Busy: [1, SPI busy] + OVR: + _read: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + MODF: + _read: + NoFault: [0, No mode fault occurred] + Fault: [1, Mode fault occurred] + CRCERR: + _read: + Match: [0, CRC value received matches the SPIx_RXCRCR value] + NoMatch: [1, CRC value received does not match the SPIx_RXCRCR value] + _W0C: + Clear: [0, Clear flag] + TXE: + NotEmpty: [0, Tx buffer not empty] + Empty: [1, Tx buffer empty] + RXNE: + Empty: [0, Rx buffer empty] + NotEmpty: [1, Rx buffer not empty] +DR: + DR: [0, 65535] +CRCPR: + CRCPOLY: [0, 65535] +RXCRCR: + "R[xX]CRC": [0, 65535] +TXCRCR: + T[xX]CRC: [0, 65535] diff --git a/devices/fields/spi/spi_v1.yaml b/devices/fields/spi/spi_v1.yaml new file mode 100644 index 000000000..86bec1452 --- /dev/null +++ b/devices/fields/spi/spi_v1.yaml @@ -0,0 +1,5 @@ +# SPIv1 is used on F1 and F4 + +_include: + - spi_v1_without_FRF_FRE.yaml + - spi_FRF_FRE.yaml diff --git a/devices/fields/spi/spi_v1_without_FRF_FRE.yaml b/devices/fields/spi/spi_v1_without_FRF_FRE.yaml new file mode 100644 index 000000000..26fed2b2e --- /dev/null +++ b/devices/fields/spi/spi_v1_without_FRF_FRE.yaml @@ -0,0 +1,7 @@ +# SPIv1 is used on F1 and F4 + +_include: + - spi_common.yaml + - dff.yaml + - spi_SR_UDR_CHSIDE.yaml + - spi_I2S.yaml diff --git a/devices/fields/spi/spi_v2.yaml b/devices/fields/spi/spi_v2.yaml new file mode 100644 index 000000000..bd405b50c --- /dev/null +++ b/devices/fields/spi/spi_v2.yaml @@ -0,0 +1,6 @@ +# SPI for F0x1, F0x2, F0x8, F3, F7 +# it includes all that the F0x0 has plus SR has UDR and CHSIDE + +_include: + - spi_v2_without_UDR_CHSIDE.yaml + - spi_SR_UDR_CHSIDE.yaml diff --git a/devices/fields/spi/spi_v2_i2s.yaml b/devices/fields/spi/spi_v2_i2s.yaml new file mode 100644 index 000000000..4ed979e31 --- /dev/null +++ b/devices/fields/spi/spi_v2_i2s.yaml @@ -0,0 +1,6 @@ +# SPI for F0x0 + +_include: + - spi_common.yaml + - spi_FRF_FRE.yaml + - spi_I2S.yaml diff --git a/devices/fields/spi/spi_v2_spi.yaml b/devices/fields/spi/spi_v2_spi.yaml new file mode 100644 index 000000000..2ae8ae7a8 --- /dev/null +++ b/devices/fields/spi/spi_v2_spi.yaml @@ -0,0 +1,44 @@ +CR1: + CRCL: + EightBit: [0, 8-bit CRC length] + SixteenBit: [1, 16-bit CRC length] +CR2: + LDMA_TX: + Even: [0, Number of data to transfer for transmit is even] + Odd: [1, Number of data to transfer for transmit is odd] + LDMA_RX: + Even: [0, Number of data to transfer for receive is even] + Odd: [1, Number of data to transfer for receive is odd] + FRXTH: + Half: [0, RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)] + Quarter: [1, RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)] + DS: + FourBit: [3, 4-bit] + FiveBit: [4, 5-bit] + SixBit: [5, 6-bit] + SevenBit: [6, 7-bit] + EightBit: [7, 8-bit] + NineBit: [8, 9-bit] + TenBit: [9, 10-bit] + ElevenBit: [10, 11-bit] + TwelveBit: [11, 12-bit] + ThirteenBit: [12, 13-bit] + FourteenBit: [13, 14-bit] + FifteenBit: [14, 15-bit] + SixteenBit: [15, 16-bit] + NSSP: + NoPulse: [0, No NSS pulse] + PulseGenerated: [1, NSS pulse generated] +SR: + FTLVL: + _read: + Empty: [0, Tx FIFO Empty] + Quarter: [1, Tx 1/4 FIFO] + Half: [2, Tx 1/2 FIFO] + Full: [3, Tx FIFO full] + FRLVL: + _read: + Empty: [0, Rx FIFO Empty] + Quarter: [1, Rx 1/4 FIFO] + Half: [2, Rx 1/2 FIFO] + Full: [3, Rx FIFO full] diff --git a/devices/fields/spi/spi_v2_without_UDR_CHSIDE.yaml b/devices/fields/spi/spi_v2_without_UDR_CHSIDE.yaml new file mode 100644 index 000000000..87bee4aad --- /dev/null +++ b/devices/fields/spi/spi_v2_without_UDR_CHSIDE.yaml @@ -0,0 +1,7 @@ +# SPI for F0x0 + +_include: + - spi_common.yaml + - spi_FRF_FRE.yaml + - spi_I2S.yaml + - spi_v2_spi.yaml diff --git a/devices/fields/spi/spi_v3.yaml b/devices/fields/spi/spi_v3.yaml new file mode 100644 index 000000000..e1d72dfef --- /dev/null +++ b/devices/fields/spi/spi_v3.yaml @@ -0,0 +1,17 @@ +_include: + - spi_v3_base.yaml + - spi_v3_i2s.yaml + +CFG1: + UDRDET: + StartOfFrame: [0, Underrun is detected at begin of data frame] + EndOfFrame: [1, Underrun is detected at end of last data frame] + StartOfSlaveSelect: [2, Underrun is detected at begin of active SS signal] + UDRCFG: + RepeatTransmitted: [2, Slave repeats last transmitted data frame] +CR2: + TSER: [0, 65535] +SR: + TSERF: + NotLoaded: [0, Additional number of SPI data to be transacted not yet loaded] + Loaded: [1, Additional number of SPI data to be transacted was reloaded] diff --git a/devices/fields/spi/spi_v3_base.yaml b/devices/fields/spi/spi_v3_base.yaml new file mode 100644 index 000000000..cfc573978 --- /dev/null +++ b/devices/fields/spi/spi_v3_base.yaml @@ -0,0 +1,191 @@ +CR1: + IOLOCK: + Unlocked: [0, IO configuration unlocked] + Locked: [1, IO configuration locked] + TCRCINI: + AllZeros: [0, All zeros TX CRC initialization pattern] + AllOnes: [1, All ones TX CRC initialization pattern] + RCRCINI: + AllZeros: [0, All zeros RX CRC initialization pattern] + AllOnes: [1, All ones RX CRC initialization pattern] + CRC33_17: + Disabled: [0, Full size (33/17 bit) CRC polynomial is not used] + Enabled: [1, Full size (33/17 bit) CRC polynomial is used] + SSI: + SlaveSelected: [0, 0 is forced onto the SS signal and the I/O value of the SS pin is ignored] + SlaveNotSelected: [1, 1 is forced onto the SS signal and the I/O value of the SS pin is ignored] + HDDIR: + Receiver: [0, Receiver in half duplex mode] + Transmitter: [1, Transmitter in half duplex mode] + CSUSP: + _write: + NotRequested: [0, Do not request master suspend] + Requested: [1, Request master suspend] + CSTART: + NotStarted: [0, Do not start master transfer] + Started: [1, Start master transfer] + MASRX: + Disabled: [0, Automatic suspend in master receive-only mode disabled] + Enabled: [1, Automatic suspend in master receive-only mode enabled] + SPE: + Disabled: [0, Peripheral disabled] + Enabled: [1, Peripheral enabled] + +CR2: + TSIZE: [0, 65535] + +CFG1: + MBR: + Div2: [0, f_spi_ker_ck / 2] + Div4: [1, f_spi_ker_ck / 4] + Div8: [2, f_spi_ker_ck / 8] + Div16: [3, f_spi_ker_ck / 16] + Div32: [4, f_spi_ker_ck / 32] + Div64: [5, f_spi_ker_ck / 64] + Div128: [6, f_spi_ker_ck / 128] + Div256: [7, f_spi_ker_ck / 256] + CRCEN: + Disabled: [0, CRC calculation disabled] + Enabled: [1, CRC calculation enabled] + CRCSIZE: [0, 31] + TXDMAEN: + Disabled: [0, Tx buffer DMA disabled] + Enabled: [1, Tx buffer DMA enabled] + RXDMAEN: + Disabled: [0, Rx buffer DMA disabled] + Enabled: [1, Rx buffer DMA enabled] + UDRCFG: + Constant: [0, Slave sends a constant underrun pattern] + RepeatReceived: [1, Slave repeats last received data frame from master] + FTHLV: + OneFrame: [0, 1 frame] + TwoFrames: [1, 2 frames] + ThreeFrames: [2, 3 frames] + FourFrames: [3, 4 frames] + FiveFrames: [4, 5 frames] + SixFrames: [5, 6 frames] + SevenFrames: [6, 7 frames] + EightFrames: [7, 8 frames] + NineFrames: [8, 9 frames] + TenFrames: [9, 10 frames] + ElevenFrames: [10, 11 frames] + TwelveFrames: [11, 12 frames] + ThirteenFrames: [12, 13 frames] + FourteenFrames: [13, 14 frames] + FifteenFrames: [14, 15 frames] + SixteenFrames: [15, 16 frames] + DSIZE: [0, 31] + +CFG2: + AFCNTR: + NotControlled: [0, Peripheral takes no control of GPIOs while disabled] + Controlled: [1, Peripheral controls GPIOs while disabled] + SSOM: + Asserted: [0, SS is asserted until data transfer complete] + NotAsserted: [1, Data frames interleaved with SS not asserted during MIDI] + SSOE: + Disabled: [0, SS output is disabled in master mode] + Enabled: [1, SS output is enabled in master mode] + SSIOP: + ActiveLow: [0, Low level is active for SS signal] + ActiveHigh: [1, High level is active for SS signal] + SSM: + Disabled: [0, Software slave management disabled] + Enabled: [1, Software slave management enabled] + CPOL: + IdleLow: [0, CK to 0 when idle] + IdleHigh: [1, CK to 1 when idle] + CPHA: + FirstEdge: [0, The first clock transition is the first data capture edge] + SecondEdge: [1, The second clock transition is the first data capture edge] + LSBFRST: + MSBFirst: [0, Data is transmitted/received with the MSB first] + LSBFirst: [1, Data is transmitted/received with the LSB first] + MASTER: + Slave: [0, Slave configuration] + Master: [1, Master configuration] + SP: + Motorola: [0, Motorola SPI protocol] + TI: [1, TI SPI protocol] + COMM: + FullDuplex: [0, Full duplex] + Transmitter: [1, Simplex transmitter only] + Receiver: [2, Simplex receiver only] + HalfDuplex: [3, Half duplex] + IOSWP: + Disabled: [0, MISO and MOSI not swapped] + Enabled: [1, MISO and MOSI swapped] + MIDI: [0, 15] + MSSI: [0, 15] + +IER: + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + +SR: + CTSIZE: [0, 65535] + RXWNE: + LessThan32: [0, Less than 32-bit data frame received] + AtLeast32: [1, At least 32-bit data frame received] + RXPLVL: + ZeroFrames: [0, Zero frames beyond packing ratio available] + OneFrame: [1, One frame beyond packing ratio available] + TwoFrames: [2, Two frame beyond packing ratio available] + ThreeFrames: [3, Three frame beyond packing ratio available] + TXC: + Ongoing: [0, Transmission ongoing] + Completed: [1, Transmission completed] + SUSP: + NotSuspended: [0, Master not suspended] + Suspended: [1, Master suspended] + MODF: + NoFault: [0, No mode fault detected] + Fault: [1, Mode fault detected] + TIFRE: + NoError: [0, TI frame format error detected] + Error: [1, TI frame format error detected] + CRCE: + NoError: [0, No CRC error detected] + Error: [1, CRC error detected] + OVR: + NoOverrun: [0, No overrun occurred] + Overrun: [1, Overrun occurred] + UDR: + NoUnderrun: [0, No underrun occurred] + Underrun: [1, Underrun occurred] + TXTF: + NotCompleted: [0, Transmission buffer incomplete] + Completed: [1, Transmission buffer filled with at least one transfer] + EOT: + NotCompleted: [0, Transfer ongoing or not started] + Completed: [1, Transfer complete] + DXP: + Unavailable: [0, "Duplex packet unavailable: no space for transmission and/or no data received"] + Available: [1, "Duplex packet available: space for transmission and data received"] + TXP: + Full: [0, Tx buffer full] + NotFull: [1, Tx buffer not full] + RXP: + Empty: [0, Rx buffer empty] + NotEmpty: [1, Rx buffer not empty] + +IFCR: + "*C": + _W1C: + Clear: [1, Clear interrupt flag] + +TXDR: + TXDR: [0, 0xFFFFFFFF] + +RXCRC: + RXCRC: [0, 0xFFFFFFFF] + +TXCRC: + TXCRC: [0, 0xFFFFFFFF] + +CRCPOLY: + CRCPOLY: [0, 0xFFFFFFFF] + +UDRDR: + UDRDR: [0, 0xFFFFFFFF] diff --git a/devices/fields/spi/spi_v3_i2s.yaml b/devices/fields/spi/spi_v3_i2s.yaml new file mode 100644 index 000000000..a926cc5db --- /dev/null +++ b/devices/fields/spi/spi_v3_i2s.yaml @@ -0,0 +1,44 @@ +I2SCFGR: + MCKOE: + Disabled: [0, Master clock output disabled] + Enabled: [1, Master clock output enabled] + ODD: + Even: [0, Real divider value is I2SDIV*2] + Odd: [1, Real divider value is I2SDIV*2 + 1] + DATFMT: + RightAligned: [0, The data inside RXDR and TXDR are right aligned] + LeftAligned: [1, The data inside RXDR and TXDR are left aligned] + WSINV: + Disabled: [0, Word select inversion disabled] + Enabled: [1, Word select inversion enabled] + FIXCH: + NotFixed: [0, The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)] + Fixed: [1, The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)] + CKPOL: + SampleOnRising: [0, Signals are sampled on rising and changed on falling clock edges] + SampleOnFalling: [1, Signals are sampled on falling and changed on rising clock edges] + CHLEN: + Bits16: [0, 16 bit per channel] + Bits32: [1, 32 bit per channel] + DATLEN: + Bits16: [0, 16 bit data length] + Bits24: [1, 24 bit data length] + Bits32: [2, 32 bit data length] + PCMSYNC: + Short: [0, Short PCM frame synchronization] + Long: [1, Long PCM frame synchronization] + I2SSTD: + Philips: [0, I2S Philips standard] + LeftAligned: [1, MSB/left justified standard] + RightAligned: [2, LSB/right justified standard] + PCM: [3, PCM standard] + I2SCFG: + SlaveTransmit: [0, "Slave, transmit"] + SlaveReceive: [1, "Slave, recteive"] + MasterTransmit: [2, "Master, transmit"] + MasterReceive: [3, "Master, receive"] + SlaveFullDuplex: [4, "Slave, full duplex"] + MasterFullDuplex: [5, "Master, full duplex"] + I2SMOD: + SPI: [0, SPI mode selected] + I2S: [1, I2S/PCM mode selected] diff --git a/devices/fields/spi/spi_v4.yaml b/devices/fields/spi/spi_v4.yaml new file mode 100644 index 000000000..9e42e3e25 --- /dev/null +++ b/devices/fields/spi/spi_v4.yaml @@ -0,0 +1,23 @@ +_include: + - spi_v3_base.yaml + +CFG1: + BPASS: + Disabled: [0, Bypass is disabled] + Enabled: [1, Bypass is enabled] +CFG2: + RDIOP: + High: [0, high level of the signal means the slave is ready for communication] + Low: [1, low level of the signal means the slave is ready for communication] + RDIOM: + Active: [0, RDY signal is defined internally fixed as permanently active (RDIOP setting has no effect)] + Pin: + - 1 + - RDY signal is overtaken from alternate function input (at master case) or output (at slave case) of the dedicated pin (RDIOP setting takes effect) +"?~AUTOCR": + TRIGEN: + Disabled: [0, Hardware control disabled] + Enabled: [1, Hardware control enabled] + TRIGPOL: + RaisingEdge: [0, trigger is active on raising edge] + FallingEdge: [1, trigger is active on falling edge] diff --git a/devices/fields/syscfg/f4/cmpcr.yaml b/devices/fields/syscfg/f4/cmpcr.yaml new file mode 100644 index 000000000..a0daa6dc1 --- /dev/null +++ b/devices/fields/syscfg/f4/cmpcr.yaml @@ -0,0 +1,7 @@ +CMPCR: + READY: + NotReady: [0, I/O compensation cell not ready] + Ready: [1, I/O compensation cell ready] + CMP_PD: + PowerDown: [0, I/O compensation cell power-down mode] + Enabled: [1, I/O compensation cell enabled] diff --git a/devices/fields/syscfg/f4/syscfg_f401_f411.yaml b/devices/fields/syscfg/f4/syscfg_f401_f411.yaml new file mode 100644 index 000000000..996950ef5 --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f401_f411.yaml @@ -0,0 +1,21 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + +PMC: + ADC1DC2: [0, 1] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] diff --git a/devices/fields/syscfg/f4/syscfg_f405.yaml b/devices/fields/syscfg/f4/syscfg_f405.yaml new file mode 100644 index 000000000..bcb1d3d11 --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f405.yaml @@ -0,0 +1,22 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + FSMCBank1: [2, FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + PI: [8, Select PIx as the source input for the EXTIx external interrupt] diff --git a/devices/fields/syscfg/f4/syscfg_f410.yaml b/devices/fields/syscfg/f4/syscfg_f410.yaml new file mode 100644 index 000000000..b360a54a1 --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f410.yaml @@ -0,0 +1,35 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + +PMC: + ADC1DC2: [0, 1] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + +CFGR2: + PVDL: + NotConnected: [0, "PVD interrupt not connected to TIM1 Break input. PVDE and PVDS[2:0] can be read and modified"] + Connected: [1, "PVD interrupt connected to TIM1 Break input. PVDE and PVDS[2:0] are read-only"] + CLL: + NotConnected: [0, Cortex-M4 LOCKUP output not connected to TIM1 Break input] + Connected: [1, Cortex-M4 LOCKUP output connected to TIM1 Break input] + +CFGR: + FMPI2C4_SDA: + Clear: [0, ""] + Forced: [1, "forces FM+ drive capability on FMPI2C4_SDA pin"] + FMPI2C4_SCL: + Clear: [0, ""] + Forced: [1, "forces FM+ drive capability on FMPI2C4_SCL pin"] diff --git a/devices/fields/syscfg/f4/syscfg_f412.yaml b/devices/fields/syscfg/f4/syscfg_f412.yaml new file mode 100644 index 000000000..24c110359 --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f412.yaml @@ -0,0 +1,39 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + FSMCBank1: [2, FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + +PMC: + ADC1DC2: [0, 1] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + +CFGR2: + PVDL: + NotConnected: [0, "PVD interrupt not connected to TIM1 Break input. PVDE and PVDS[2:0] can be read and modified"] + Connected: [1, "PVD interrupt connected to TIM1 Break input. PVDE and PVDS[2:0] are read-only"] + CLL: + NotConnected: [0, Cortex-M4 LOCKUP output not connected to TIM1 Break input] + Connected: [1, Cortex-M4 LOCKUP output connected to TIM1 Break input] + +CFGR: + I2CFMP1_SDA: + Clear: [0, ""] + Forced: [1, "forces FM+ drive capability on I2CFMP1_SDA pin"] + I2CFMP1_SCL: + Clear: [0, ""] + Forced: [1, "forces FM+ drive capability on I2CFMP1_SCL pin"] diff --git a/devices/fields/syscfg/f4/syscfg_f413_f423.yaml b/devices/fields/syscfg/f4/syscfg_f413_f423.yaml new file mode 100644 index 000000000..5c0958e1b --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f413_f423.yaml @@ -0,0 +1,75 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + +PMC: + ADC1DC2: [0, 1] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + +CFGR2: + PVDL: + NotConnected: [0, "PVD interrupt not connected to TIM1/8 Break input. PVDE and PVDS[2:0] can be read and modified"] + Connected: [1, "PVD interrupt connected to TIM1/8 Break input. PVDE and PVDS[2:0] are read-only"] + CLL: + NotConnected: [0, Cortex-M4 LOCKUP output not connected to TIM1/8 Break input] + Connected: [1, Cortex-M4 LOCKUP output connected to TIM1/8 Break input] + +CFGR: + I2CFMP1_SDA: + Clear: [0, ""] + Forced: [1, "forces FM+ drive capability on I2CFMP1_SDA pin"] + I2CFMP1_SCL: + Clear: [0, ""] + Forced: [1, "forces FM+ drive capability on I2CFMP1_SCL pin"] + +MCHDLYCR: + DFSDM2_CKOSEL: [0, 1] + DFSDM2_CFG: [0, 1] + DFSDM2_CK37SEL: + CkIn3: [0, "The gated clock is distributed to CkIn3 (DM3 = 0)"] + CkIn7: [1, "The gated clock is distributed to CkIn7 (DM3 = 1)"] + DFSDM2_CK26SEL: + CkIn2: [0, "The gated clock is distributed to CkIn2 (DM4 = 0)"] + CkIn6: [1, "The gated clock is distributed to CkIn6 (DM4 = 1)"] + DFSDM2_CK15SEL: + CkIn1: [0, "The gated clock is distributed to CkIn1 (DM5 = 0)"] + CkIn5: [1, "The gated clock is distributed to CkIn5 (DM5 = 1)"] + DFSDM2_CK04SEL: + CkIn0: [0, "The gated clock is distributed to CkIn0 (DM6 = 0)"] + CkIn4: [1, "The gated clock is distributed to CkIn4 (DM6 = 1)"] + DFSDM2_D6SEL: [0, 1] + DFSDM2_D4SEL: [0, 1] + DFSDM2_D2SEL: [0, 1] + DFSDM2_D0SEL: [0, 1] + MCHDLYEN2: + Disabled: [0, "Delay clock for DFSDM2 is disabled (G[6:3] = 0)"] + Enabled: [1, "Delay clock for DFSDM2 is enabled (G[6:3] = 1)"] + DFSDM1_CKOSEL: [0, 1] + DFSDM1_CFG: [0, 1] + DFSDM1_CK13SEL: + CkIn1: [0, "The gated clock is distributed to CkIn1 (DM1 = 0)"] + CkIn3: [1, "The gated clock is distributed to CkIn3 (DM1 = 1)"] + DFSDM1_CK02SEL: + CkIn0: [0, "The gated clock is distributed to CkIn0 (DM2 = 0)"] + CkIn2: [1, "The gated clock is distributed to CkIn2 (DM2 = 1)"] + DFSDM1_D2SEL: [0, 1] + DFSDM1_D0SEL: [0, 1] + MCHDLYEN1: + Disabled: [0, "Delay clock for DFSDM1 is disabled (G[2:1] = 0)"] + Enabled: [1, "Delay clock for DFSDM1 is enabled (G[2:1] = 1)"] + BSCKSEL: [0, 1] diff --git a/devices/fields/syscfg/f4/syscfg_f415_f407_f417.yaml b/devices/fields/syscfg/f4/syscfg_f415_f407_f417.yaml new file mode 100644 index 000000000..21a1d789a --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f415_f407_f417.yaml @@ -0,0 +1,27 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + FSMCBank1: [2, FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + +PMC: + MII_RMII_SEL: + MII: [0, MII interface is selected] + RMII_PHY: [1, RMII PHY interface is selected] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + PI: [8, Select PIx as the source input for the EXTIx external interrupt] diff --git a/devices/fields/syscfg/f4/syscfg_f427_f437_f429_f439.yaml b/devices/fields/syscfg/f4/syscfg_f427_f437_f429_f439.yaml new file mode 100644 index 000000000..c94e904ef --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f427_f437_f429_f439.yaml @@ -0,0 +1,37 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + SWP_FMC: + NoSwap: [0, No FMC memory mapping swap] + Swapped: [1, SDRAM banks and NAND Bank 2/PCCARD mapping are swapped"] + FB_MODE: [0, 1] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + FSMCBank1: [2, FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + FMCSDRAMBank1: [4, FMC/SDRAM Bank 1 mapped at 0x0000 0000] + +PMC: + MII_RMII_SEL: + MII: [0, MII interface is selected] + RMII_PHY: [1, RMII PHY interface is selected] + ADC3DC2: [0, 1] + ADC2DC2: [0, 1] + ADC1DC2: [0, 1] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + PI: [8, Select PIx as the source input for the EXTIx external interrupt] + PJ: [9, Select PJx as the source input for the EXTIx external interrupt] + PK: [10, Select PKx as the source input for the EXTIx external interrupt] diff --git a/devices/fields/syscfg/f4/syscfg_f446.yaml b/devices/fields/syscfg/f4/syscfg_f446.yaml new file mode 100644 index 000000000..c17cdd85f --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f446.yaml @@ -0,0 +1,38 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + SWP_FMC: + NoSwap: [0, No FMC memory mapping swap] + Swapped: [1, SDRAM banks and NAND Bank 2/PCCARD mapping are swapped"] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + FSMCBank1: [2, FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + FMCSDRAMBank1: [4, FMC/SDRAM Bank 1 mapped at 0x0000 0000] + +PMC: + ADC3DC2: [0, 1] + ADC2DC2: [0, 1] + ADC1DC2: [0, 1] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + +CFGR: + FMPI2C1_SDA: + Clear: [0, ""] + Forced: [1, "forces FM+ drive capability on FMPI2C1_SDA pin"] + FMPI2C1_SCL: + Clear: [0, ""] + Forced: [1, "forces FM+ drive capability on FMPI2C1_SCL pin"] diff --git a/devices/fields/syscfg/f4/syscfg_f469_f479.yaml b/devices/fields/syscfg/f4/syscfg_f469_f479.yaml new file mode 100644 index 000000000..69d342e1b --- /dev/null +++ b/devices/fields/syscfg/f4/syscfg_f469_f479.yaml @@ -0,0 +1,30 @@ +_include: + - ../../exti/derive.yaml + - cmpcr.yaml + +MEMRMP: + SWP_FMC: + NoSwap: [0, No FMC memory mapping swap] + Swapped: [1, SDRAM banks and NAND Bank 2/PCCARD mapping are swapped"] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000 0000] + SystemFlash: [1, System Flash memory mapped at 0x0000 0000] + FSMCBank1: [2, FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x0000 0000] + EmbeddedSRAM: [3, Embedded SRAM mapped at 0x0000 0000] + FMCSDRAMBank1: [4, FMC/SDRAM Bank 1 mapped at 0x0000 0000] + +PMC: + ADC3DC2: [0, 1] + ADC2DC2: [0, 1] + ADC1DC2: [0, 1] + +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] diff --git a/devices/fields/syscfg/syscfg_f0.yaml b/devices/fields/syscfg/syscfg_f0.yaml new file mode 100644 index 000000000..afea79f62 --- /dev/null +++ b/devices/fields/syscfg/syscfg_f0.yaml @@ -0,0 +1,65 @@ +CFGR1: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + MainFlash2: [2, Main Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] + PA11_PA12_RMP: + NotRemapped: [0, Pin pair PA9/PA10 mapped on the pins] + Remapped: [1, Pin pair PA11/PA12 mapped instead of PA9/PA10] + ADC_DMA_RMP: + NotRemapped: [0, ADC DMA request mapped on DMA channel 1] + Remapped: [1, ADC DMA request mapped on DMA channel 2] + USART1_TX_DMA_RMP: + NotRemapped: [0, USART1_TX DMA request mapped on DMA channel 2] + Remapped: [1, USART1_TX DMA request mapped on DMA channel 4] + USART1_RX_DMA_RMP: + NotRemapped: [0, USART1_RX DMA request mapped on DMA channel 3] + Remapped: [1, USART1_RX DMA request mapped on DMA channel 5] + TIM16_DMA_RMP: + NotRemapped: [0, TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3] + Remapped: [1, TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4] + TIM17_DMA_RMP: + NotRemapped: [0, TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1] + Remapped: [1, TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2] + I2C_PB6_FMP: + Standard: [0, PB6 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] + I2C_PB7_FMP: + Standard: [0, PB7 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] + I2C_PB8_FMP: + Standard: [0, PB8 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] + I2C_PB9_FMP: + Standard: [0, PB9 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] + I2C1_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers"] + I2C_PA9_FMP: + Standard: [0, PA9 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PA9 and the Speed control is bypassed"] + I2C_PA10_FMP: + Standard: [0, PA10 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PA10 and the Speed control is bypassed"] + USART3_DMA_RMP: + NotRemapped: + [ + 0, + USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0), + ] + Remapped: [1, USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively] +CFGR2: + LOCKUP_LOCK: + Disconnected: [0, Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input] + Connected: [1, Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input] + SRAM_PARITY_LOCK: + Disconnected: [0, SRAM parity error disconnected from TIM1/15/16/17 Break input] + Connected: [1, SRAM parity error connected to TIM1/15/16/17 Break input] + SRAM_PEF: + _read: + NoParityError: [0, No SRAM parity error detected] + ParityErrorDetected: [1, SRAM parity error detected] + _write: + Clear: [1, Clear SRAM parity error flag] diff --git a/devices/fields/syscfg/syscfg_f0x128.yaml b/devices/fields/syscfg/syscfg_f0x128.yaml new file mode 100644 index 000000000..b391e709c --- /dev/null +++ b/devices/fields/syscfg/syscfg_f0x128.yaml @@ -0,0 +1,48 @@ +_include: + - syscfg_f0.yaml + - ../exti/derive.yaml + +CFGR1: + IR_MOD: + TIM16: [0, TIM16 selected] + USART1: [1, USART1 selected] + USART4: [2, USART4 selected] + TIM16_DMA_RMP2: + NotAlternateRemapped: [0, TIM16 DMA request mapped according to TIM16_DMA_RMP bit] + AlternateRemapped: [1, TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6] + TIM17_DMA_RMP2: + NotAlternateRemapped: [0, TIM17 DMA request mapped according to TIM16_DMA_RMP bit] + AlternateRemapped: [1, TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7] + I2C2_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers"] + SPI2_DMA_RMP: + NotRemapped: [0, SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively] + Remapped: [1, SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively] + USART2_DMA_RMP: + NotRemapped: [0, USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively] + Remapped: [1, USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively] + I2C1_DMA_RMP: + NotRemapped: [0, I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively] + Remapped: [1, I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively] + TIM1_DMA_RMP: + NotRemapped: [0, "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively"] + Remapped: [1, "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6"] + TIM2_DMA_RMP: + NotRemapped: [0, TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively] + Remapped: [1, TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7] + TIM3_DMA_RMP: + NotRemapped: [0, TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4] + Remapped: [1, TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6] +CFGR2: + PVD_LOCK: + Disconnected: [0, PVD interrupt disconnected from TIM1/15/16/17 Break input] + Connected: [1, PVD interrupt connected to TIM1/15/16/17 Break input] +EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIX external interrupt] diff --git a/devices/fields/syscfg/syscfg_f3.yaml b/devices/fields/syscfg/syscfg_f3.yaml new file mode 100644 index 000000000..9bc9adaba --- /dev/null +++ b/devices/fields/syscfg/syscfg_f3.yaml @@ -0,0 +1,51 @@ +CFGR1: + FPU_IE5: + Disabled: [0, Inexact interrupt disable] + Enabled: [1, Inexact interrupt enable] + FPU_IE4: + Disabled: [0, Input denormal interrupt disable] + Enabled: [1, Input denormal interrupt enable] + FPU_IE3: + Disabled: [0, Overflow interrupt disable] + Enabled: [1, Overflow interrupt enable] + FPU_IE2: + Disabled: [0, Underflow interrupt disable] + Enabled: [1, Underflow interrupt enable] + FPU_IE1: + Disabled: [0, Devide-by-zero interrupt disable] + Enabled: [1, Devide-by-zero interrupt enable] + FPU_IE0: + Disabled: [0, Invalid operation interrupt disable] + Enabled: [1, Invalid operation interrupt enable] + I2C2_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: + [ + 1, + "FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits", + ] + I2C1_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: + [ + 1, + "FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits", + ] + I2C_PB9_FMP: + Standard: [0, PB9 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] + I2C_PB8_FMP: + Standard: [0, PB8 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] + I2C_PB7_FMP: + Standard: [0, PB7 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] + I2C_PB6_FMP: + Standard: [0, PB6 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] + TIM17_DMA_RMP: + NotRemapped: [0, TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1] + Remapped: [1, TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2] + TIM16_DMA_RMP: + NotRemapped: [0, TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3] + Remapped: [1, TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4] diff --git a/devices/fields/syscfg/syscfg_f301.yaml b/devices/fields/syscfg/syscfg_f301.yaml new file mode 100644 index 000000000..723854966 --- /dev/null +++ b/devices/fields/syscfg/syscfg_f301.yaml @@ -0,0 +1,55 @@ +CFGR1: + I2C3_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: + [ + 1, + "FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits", + ] + ENCODER_MODE: + NoRedirection: [0, No redirection] + MapTim2Tim15: [1, TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively] + TIM6_DAC1_DMA_RMP: + NotRemapped: [0, TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3] + Remapped: [1, TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3] + TIM1_ITR3_RMP: + NotRemapped: [0, Not remapped] + Remapped: [1, "TIM1_ITR3 = TIM17_OC"] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + MainFlash2: [2, Main Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] +EXTICR1: + _derive: + EXTI1: EXTI0 + EXTI2: EXTI0 + EXTI0: + _name: ExtiAbcf + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIX external interrupt] + EXTI3: + _name: ExtiAbc + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] +EXTICR2: + _derive: + EXTI4: EXTICR1.EXTI3 + EXTI5: EXTICR1.EXTI3 + EXTI6: EXTICR1.EXTI3 + EXTI7: EXTICR1.EXTI3 +EXTICR3: + _derive: + EXTI8: EXTICR1.EXTI3 + EXTI9: EXTICR1.EXTI3 + EXTI10: EXTICR1.EXTI3 + EXTI11: EXTICR1.EXTI3 +EXTICR4: + _derive: + EXTI12: EXTICR1.EXTI3 + EXTI13: EXTICR1.EXTI3 + EXTI14: EXTICR1.EXTI3 + EXTI15: EXTICR1.EXTI3 diff --git a/devices/fields/syscfg/syscfg_f302.yaml b/devices/fields/syscfg/syscfg_f302.yaml new file mode 100644 index 000000000..9988f518a --- /dev/null +++ b/devices/fields/syscfg/syscfg_f302.yaml @@ -0,0 +1,97 @@ +CFGR1: + I2C3_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: + [ + 1, + "FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits", + ] + ENCODER_MODE: + NoRedirection: [0, No redirection] + MapTim2Tim15: [1, TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively] + MapTim3Tim15: [2, TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively] + MapTim4Tim15: + [3, TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively (STM32F302xB/C devices only)] + TIM6_DAC1_DMA_RMP: + NotRemapped: [0, TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3] + Remapped: [1, TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3] + ADC2_DMA_RMP: + NotRemapped: [0, ADC24 DMA requests mapped on DMA2 channels 1 and 2] + Remapped: [1, ADC24 DMA requests mapped on DMA2 channels 3 and 4] + DAC1_TRIG_RMP: + NotRemapped: [0, DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices] + Remapped: [1, DAC trigger is TIM3_TRGO] + TIM1_ITR3_RMP: + NotRemapped: [0, "TIM1_ITR3 = TIM4_TRGO in STM32F303xB/C and STM32F358xC devices"] + Remapped: [1, "TIM1_ITR3 = TIM17_OC"] + # Is documented as reserverd but appears in register table (RM0365 p.172) and register map + USB_IT_RMP: + NotRemapped: + [0, "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively"] + Remapped: [1, "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively"] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] + FMC: [4, FMC Bank (Only the first two banks) (Available on STM32F302xD/E only)] +EXTICR1: + _derive: + EXTI1: EXTI0 + EXTI2: EXTI0 + EXTI0: + _name: ExtiAbcdef + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + EXTI3: + _name: ExtiAbcde + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] +EXTICR2: + _derive: + EXTI4: EXTICR1.EXTI0 + EXTI5: EXTICR1.EXTI0 + EXTI6: EXTICR1.EXTI0 + EXTI7: EXTICR1.EXTI3 +EXTICR3: + _derive: + EXTI8: EXTICR1.EXTI3 + EXTI9: EXTICR1.EXTI0 + EXTI10: EXTICR1.EXTI0 + EXTI11: EXTICR1.EXTI3 +EXTICR4: + _derive: + EXTI12: EXTICR1.EXTI3 + EXTI13: EXTICR1.EXTI3 + EXTI14: EXTICR1.EXTI3 + EXTI15: EXTICR1.EXTI3 +CFGR2: + SRAM_PEF: + _read: + NoParityError: [0, No SRAM parity error detected] + ParityErrorDetected: [1, SRAM parity error detected] + _write: + Clear: [1, Clear SRAM parity error flag] + BYP_ADDR_PAR: + NoBypass: + [ + 0, + The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated, + ] + Bypass: + [ + 1, + The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated, + ] + SRAM_PARITY_LOCK: + Disconnected: [0, SRAM parity error disconnected from TIM1/15/16/17 Break input] + Connected: [1, SRAM parity error connected to TIM1/15/16/17 Break input] + LOCKUP_LOCK: + Disconnected: [0, Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break input] + Connected: [1, Cortex-M4 LOCKUP output connected to TIM1/15/16/17 Break input] diff --git a/devices/fields/syscfg/syscfg_f303_3x8.yaml b/devices/fields/syscfg/syscfg_f303_3x8.yaml new file mode 100644 index 000000000..08bbcbef1 --- /dev/null +++ b/devices/fields/syscfg/syscfg_f303_3x8.yaml @@ -0,0 +1,180 @@ +CFGR1: + I2C3_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: + [ + 1, + "FM+ mode is enabled on all I2C3 pins selected through selection through IOPORT control registers AF selection bits", + ] + ENCODER_MODE: + NoRedirection: [0, No redirection] + MapTim2Tim15: [1, TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively] + MapTim3Tim15: [2, TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively] + MapTim4Tim15: + [ + 3, + TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively (STM32F303xB/C and STM32F358xC devices only), + ] + DAC2_CH1_DMA_RMP: + NotRemapped: [0, Not remapped] + Remapped: [1, DAC2_CH1 DMA requests mapped on DMA1 channel 5] + TIM7_DAC1_CH2_DMA_RMP: + NotRemapped: [0, TIM7_UP and DAC_CH2 DMA requests mapped on DMA2 channel 4 in STM32F303xB/C and STM32F358xC devices] + Remapped: [1, TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4] + TIM6_DAC1_CH1_DMA_RMP: + NotRemapped: [0, TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 in STM32F303xB/C and STM32F358xC] + Remapped: [1, TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3] + # TODO: Is named ADC2_... in register description (RM0316 p.247) but ADC24_... in register map (RM0316 p.261) + ADC2_DMA_RMP: + NotRemapped: [0, ADC24 DMA requests mapped on DMA2 channels 1 and 2] + Remapped: [1, ADC24 DMA requests mapped on DMA2 channels 3 and 4] + # TODO: Is named DAC1_... in register description (RM0316 p.247) but DAC_... in register map (RM0316 p.261) + DAC1_TRIG_RMP: + NotRemapped: [0, DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices] + Remapped: [1, DAC trigger is TIM3_TRGO] + TIM1_ITR3_RMP: + NotRemapped: [0, "TIM1_ITR3 = TIM4_TRGO in STM32F303xB/C and STM32F358xC devices"] + Remapped: [1, "TIM1_ITR3 = TIM17_OC"] + USB_IT_RMP: + NotRemapped: + [0, "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively"] + Remapped: [1, "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively"] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] + FMC: [4, FMC Bank (Only the first two banks) (Available on STM32F303xD/E only)] +RCR: + PAGE*_WP: + Disabled: [0, Write protection of pagex is disabled] + Enabled: [1, Write protection of pagex is enabled] +EXTICR1: + _derive: + EXTI1: EXTI0 + EXTI2: EXTI0 + EXTI0: + _name: ExtiAbcdefgh + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + EXTI3: + _name: ExtiAbcdefg + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] +EXTICR2: + _derive: + EXTI4: EXTICR1.EXTI3 + EXTI5: EXTICR1.EXTI3 + EXTI6: EXTICR1.EXTI3 + EXTI7: EXTICR1.EXTI3 +EXTICR3: + _derive: + EXTI8: EXTICR1.EXTI3 + EXTI9: EXTICR1.EXTI3 + EXTI10: EXTICR1.EXTI3 + EXTI11: EXTICR1.EXTI3 +EXTICR4: + _derive: + EXTI12: EXTICR1.EXTI3 + EXTI13: EXTICR1.EXTI3 + EXTI14: EXTICR1.EXTI3 + EXTI15: EXTICR1.EXTI3 + +CFGR2: + SRAM_PEF: + _read: + NoParityError: [0, No SRAM parity error detected] + ParityErrorDetected: [1, SRAM parity error detected] + _write: + Clear: [1, Clear SRAM parity error flag] + BYP_ADDR_PAR: + NoBypass: + [ + 0, + The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated, + ] + Bypass: + [ + 1, + The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated, + ] + SRAM_PARITY_LOCK: + Disconnected: [0, SRAM parity error disconnected from TIM1/15/16/17 Break input] + Connected: [1, SRAM parity error connected to TIM1/15/16/17 Break input] + LOCKUP_LOCK: + Disconnected: [0, Cortex-M4F LOCKUP output disconnected from TIM1/15/16/17 Break input] + Connected: [1, Cortex-M4F LOCKUP output connected to TIM1/15/16/17 Break input] +CFGR3: + ADC2_DMA_RMP: + MapDma2: [0, ADC2 mapped on DMA2] + MapDma1Ch2: [2, ADC2 mapped on DMA1 channel 2] + MapDma1Ch4: [3, ADC2 mapped on DMA1 channel 4] + I2C1_TX_DMA_RMP: + MapDma1Ch6: [0, I2C1_TX mapped on DMA1 CH6] + MapDma1Ch2: [1, I2C1_TX mapped on DMA1 CH2] + MapDma1Ch4: [2, I2C1_TX mapped on DMA1 CH4] + I2C1_RX_DMA_RMP: + MapDma1Ch7: [0, I2C1_RX mapped on DMA1 CH7] + MapDma1Ch3: [1, I2C1_RX mapped on DMA1 CH3] + MapDma1Ch5: [2, I2C1_RX mapped on DMA1 CH5] + SPI1_TX_DMA_RMP: + MapDma1Ch3: [0, SPI1_TX mapped on DMA1 CH3] + MapDma1Ch5: [1, SPI1_TX mapped on DMA1 CH5] + MapDma1Ch7: [2, SPI1_TX mapped on DMA1 CH7] + SPI1_RX_DMA_RMP: + MapDma1Ch3: [0, SPI1_RX mapped on DMA1 CH2] + MapDma1Ch5: [1, SPI1_RX mapped on DMA1 CH4] + MapDma1Ch7: [2, SPI1_RX mapped on DMA1 CH6] +CFGR4: + ADC34_JEXT14_RMP: + Tim7: [0, Trigger source is TIM7_TRGO] + Tim20: [1, Trigger source is TIM20_CC2] + ADC34_JEXT11_RMP: + Tim1: [0, Trigger source is TIM1_CC3] + Tim20: [1, Trigger source is TIM20_TRGO2] + ADC34_JEXT5_RMP: + Tim4: [0, Trigger source is TIM4_CC3] + Tim20: [1, Trigger source is TIM20_TRGO] + ADC34_EXT15_RMP: + Tim2: [0, Trigger source is TIM2_CC1] + Tim20: [1, Trigger source is TIM20_CC1] + ADC34_EXT6_RMP: + Tim4: [0, Trigger source is TIM4_CC1] + Tim20: [1, Trigger source is TIM20_TRGO2] + ADC34_EXT5_RMP: + Exti2: [0, Trigger source is EXTI line 2 when reset at 0] + Tim20: [1, Trigger source is TIM20_TRGO] + ADC12_JEXT13_RMP: + Tim3: [0, Trigger source is TIM3_CC1] + Tim20: [1, Trigger source is TIM20_CC4] + ADC12_JEXT6_RMP: + Exti15: [0, Trigger source is EXTI line 15] + Tim20: [1, Trigger source is TIM20_TRGO2] + ADC12_JEXT3_RMP: + Tim2: [0, Trigger source is TIM2_CC1] + Tim20: [1, Trigger source is TIM20_TRGO] + ADC12_EXT15_RMP: + Tim3: [0, Trigger source is TIM3_CC4] + Tim20: [1, Trigger source is TIM20_CC3] + ADC12_EXT13_RMP: + Tim6: [0, Trigger source is TIM6_TRGO] + Tim20: [1, Trigger source is TIM20_CC2] + ADC12_EXT5_RMP: + Tim4: [0, Trigger source is TIM4_CC4] + Tim20: [1, Trigger source is TIM20_CC1] + ADC12_EXT3_RMP: + Tim2: [0, Trigger source is TIM2_CC2] + Tim20: [1, rigger source is TIM20_TRGO2] + ADC12_EXT2_RMP: + Tim1: [0, Trigger source is TIM3_CC3] + Tim20: [1, rigger source is TIM20_TRGO] diff --git a/devices/fields/syscfg/syscfg_f37x.yaml b/devices/fields/syscfg/syscfg_f37x.yaml new file mode 100644 index 000000000..dd307ae03 --- /dev/null +++ b/devices/fields/syscfg/syscfg_f37x.yaml @@ -0,0 +1,73 @@ +CFGR1: + VBAT_MON: + Disable: [0, Disable the power switch to not deliver VBAT voltage on ADC channel 18 input] + Enable: [1, Enable the power switch to deliver VBAT voltage on ADC channel 18 input] + TIM18_DAC2_OUT1_DMA_RMP: + NotRemapped: [0, TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5] + Remapped: [1, TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5] + TIM7_DAC1_OUT2_DMA_RMP: + NotRemapped: [0, TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4] + Remapped: [1, TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4] + TIM6_DAC1_OUT1_DMA_RMP: + NotRemapped: [0, TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3] + Remapped: [1, TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + MainFlash2: [2, Main Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] +EXTICR1: + _derive: + EXTI1: EXTI0 + EXTI2: EXTI0 + EXTI0: + _name: ExtiAbcdef + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + EXTI3: + _name: ExtiAbcde + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] +EXTICR2: + _derive: + EXTI4: EXTICR1.EXTI0 + EXTI5: EXTICR1.EXTI3 + EXTI6: EXTICR1.EXTI0 + EXTI7: EXTICR1.EXTI0 +EXTICR3: + _derive: + EXTI8: EXTICR1.EXTI3 + EXTI9: EXTICR1.EXTI0 + EXTI10: EXTICR1.EXTI0 + EXTI11: + _name: ExtiAcde + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] +EXTICR4: + _derive: + EXTI12: EXTICR3.EXTI11 + EXTI13: EXTICR3.EXTI11 + EXTI14: EXTICR1.EXTI3 + EXTI15: EXTICR1.EXTI3 +CFGR2: + SRAM_PEF: + _read: + NoParityError: [0, No SRAM parity error detected] + ParityErrorDetected: [1, SRAM parity error detected] + _write: + Clear: [1, Clear SRAM parity error flag] + SRAM_PARITY_LOCK: + Disconnected: [0, SRAM parity error disconnected from TIM1/15/16/17 Break input] + Connected: [1, SRAM parity error connected to TIM1/15/16/17 Break input] + LOCKUP_LOCK: + Disconnected: [0, Cortex-M4F LOCKUP output disconnected from TIM1/15/16/17 Break input] + Connected: [1, Cortex-M4F LOCKUP output connected to TIM1/15/16/17 Break input] diff --git a/devices/fields/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml b/devices/fields/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml new file mode 100644 index 000000000..3cd3d8902 --- /dev/null +++ b/devices/fields/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml @@ -0,0 +1,4 @@ +CFGR2: + PVD_LOCK: + Disconnected: [0, PVD interrupt disconnected from TIM15/16/17 Break input] + Connected: [1, PVD interrupt connected to TIM15/16/17 Break input] diff --git a/devices/fields/syscfg/syscfg_f3x4.yaml b/devices/fields/syscfg/syscfg_f3x4.yaml new file mode 100644 index 000000000..3277e028b --- /dev/null +++ b/devices/fields/syscfg/syscfg_f3x4.yaml @@ -0,0 +1,117 @@ +CFGR1: + ENCODER_MODE: + NoRedirection: [0, No redirection] + MapTim2Tim15: [1, TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively] + MapTim3Tim15: [2, TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively] + DAC2_CH1_DMA_RMP: + NotRemapped: [0, Not remapped] + Remapped: [1, DAC2_CH1 DMA requests mapped on DMA1 channel 5] + TIM7_DAC1_CH2_DMA_RMP: + NotRemapped: [0, Not remapped] + Remapped: [1, TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4] + TIM6_DAC1_CH1_DMA_RMP: + NotRemapped: [0, TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3] + Remapped: [1, TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3] + DAC_TRIG_RMP: + NotRemapped: [0, Not remapped] + Remapped: [1, DAC trigger is TIM3_TRGO] + TIM1_ITR3_RMP: + NotRemapped: [0, Not remapped] + Remapped: [1, "TIM1_ITR3 = TIM17_OC"] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + MainFlash2: [2, Main Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] +RCR: + PAGE*_WP: + Disabled: [0, Write protection of pagex is disabled] + Enabled: [1, Write protection of pagex is enabled] +EXTICR1: + _derive: + EXTI1: EXTI0 + EXTI2: EXTI0 + EXTI0: + _name: ExtiAbcdef + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + EXTI3: + _name: ExtiAbcde + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] +EXTICR2: + _derive: + EXTI4: EXTICR1.EXTI0 + EXTI5: EXTICR1.EXTI0 + EXTI6: EXTICR1.EXTI0 + EXTI7: EXTICR1.EXTI3 +EXTICR3: + _derive: + EXTI8: EXTICR1.EXTI3 + EXTI9: EXTICR1.EXTI0 + EXTI10: EXTICR1.EXTI0 + EXTI11: EXTICR1.EXTI3 +EXTICR4: + _derive: + EXTI12: EXTICR1.EXTI3 + EXTI13: EXTICR1.EXTI0 + EXTI14: EXTICR1.EXTI0 + EXTI15: EXTICR1.EXTI0 +CFGR2: + SRAM_PEF: + _read: + NoParityError: [0, No SRAM parity error detected] + ParityErrorDetected: [1, SRAM parity error detected] + _write: + Clear: [1, Clear SRAM parity error flag] + BYP_ADDR_PAR: + NoBypass: + [ + 0, + The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated, + ] + Bypass: + [ + 1, + The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated, + ] + SRAM_PARITY_LOCK: + Disconnected: [0, SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs] + Connected: [1, SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs] + LOCKUP_LOCK: + Disconnected: [0, Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT.] + Connected: [1, Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs] +CFGR3: + DAC1_TRIG5_RMP: + NotRemapped: [0, Not remapped] + Remapped: [1, DAC trigger is HRTIM1_DAC1_TRIG2] + DAC1_TRIG3_RMP: + Tim15: [0, DAC trigger is TIM15_TRGO] + HrTim1: [1, DAC trigger is HRTIM1_DAC1_TRIG1] + ADC2_DMA_RMP: + MapDma2: [0, ADC2 mapped on DMA2] + MapDma1Ch2: [2, ADC2 mapped on DMA1 channel 2] + MapDma1Ch4: [3, ADC2 mapped on DMA1 channel 4] + I2C1_TX_DMA_RMP: + MapDma1Ch6: [0, I2C1_TX mapped on DMA1 CH6] + MapDma1Ch2: [1, I2C1_TX mapped on DMA1 CH2] + MapDma1Ch4: [2, I2C1_TX mapped on DMA1 CH4] + I2C1_RX_DMA_RMP: + MapDma1Ch7: [0, I2C1_RX mapped on DMA1 CH7] + MapDma1Ch3: [1, I2C1_RX mapped on DMA1 CH3] + MapDma1Ch5: [2, I2C1_RX mapped on DMA1 CH5] + SPI1_TX_DMA_RMP: + MapDma1Ch3: [0, SPI1_TX mapped on DMA1 CH3] + MapDma1Ch5: [1, SPI1_TX mapped on DMA1 CH5] + MapDma1Ch7: [2, SPI1_TX mapped on DMA1 CH7] + SPI1_RX_DMA_RMP: + MapDma1Ch3: [0, SPI1_RX mapped on DMA1 CH2] + MapDma1Ch5: [1, SPI1_RX mapped on DMA1 CH4] + MapDma1Ch7: [2, SPI1_RX mapped on DMA1 CH6] diff --git a/devices/fields/syscfg/syscfg_g0_common.yaml b/devices/fields/syscfg/syscfg_g0_common.yaml new file mode 100644 index 000000000..57a6bf031 --- /dev/null +++ b/devices/fields/syscfg/syscfg_g0_common.yaml @@ -0,0 +1,34 @@ +CFGR1: + I2C*_FMP: + Disabled: [0, Uses normal GPIO drive] + Enabled: [1, "Uses I2C FastMode+ drive"] + UCPD*_STROBE: + Disconnect: [1, Disconnect the UCPD pull-down resistors] + BOOSTEN: + VDD: [0, supply analog switches from VDD] + BOOST: [1, supply analog switches from dedicated voltage booster] + # TODO: IR_MOD + IR_POL: + Normal: [0, Output of IRTIM is not inverted] + Inverted: [1, Output of IRTIM is inverted] + PA12_RMP: + Normal: [0, PA12 pin connected to PA12 GPIO] + Remap: [1, PA12 pin connected to PA10 GPIO] + PA11_RMP: + Normal: [0, PA11 pin connected to PA11 GPIO] + Remap: [1, PA11 pin connected to PA9 GPIO] + MEM_MODE: + MainFlash: [0b00, Main flash memory mapped at zero address] # accepts 0x10 + SystemFlash: [0b10, System flash memory mapped at zero address] + SRAM: [0b11, Embedded SRAM mapped at zero address] +CFGR2: + SRAM_PEF: + Normal: [0, No SRAM parity error detected] + Error: [1, SRAM parity error detected] + "*_LOCK": + Disabled: [0, error not connected to timers] + Enabled: [1, error triggers TIM1/15/16/17 break input] +ITLINE*: + "*": + NotInterrupted: [0, Interrupt not triggered] + Interrupted: [1, Interrup triggered] diff --git a/devices/fields/syscfg/syscfg_g0_usart2.yaml b/devices/fields/syscfg/syscfg_g0_usart2.yaml new file mode 100644 index 000000000..1c724c0a5 --- /dev/null +++ b/devices/fields/syscfg/syscfg_g0_usart2.yaml @@ -0,0 +1,8 @@ +_include: + - syscfg_g0_common.yaml + +CFGR1: + IR_MOD: + TIM16: [0b00, IR modulation envelope from TIM16] + USART1: [0b01, IR modulation envelope from USART1] + USART2: [0b10, IR modulation envelope from USART2] diff --git a/devices/fields/syscfg/syscfg_g0_usart4.yaml b/devices/fields/syscfg/syscfg_g0_usart4.yaml new file mode 100644 index 000000000..a0a27ecf3 --- /dev/null +++ b/devices/fields/syscfg/syscfg_g0_usart4.yaml @@ -0,0 +1,8 @@ +_include: + - syscfg_g0_common.yaml + +CFGR1: + IR_MOD: + TIM16: [0b00, IR modulation envelope from TIM16] + USART1: [0b01, IR modulation envelope from USART1] + USART4: [0b10, IR modulation envelope from USART4] diff --git a/devices/fields/syscfg/syscfg_h747.yaml b/devices/fields/syscfg/syscfg_h747.yaml new file mode 100644 index 000000000..8f5b5fa95 --- /dev/null +++ b/devices/fields/syscfg/syscfg_h747.yaml @@ -0,0 +1,4 @@ +PWRCR: + ODEN: + Disabled: [0, Overdrive mode disabled] + Enabled: [1, Overdrive mode enabled (the LDO generates VOS0 for VCORE)] diff --git a/devices/fields/syscfg/syscfg_l0.yaml b/devices/fields/syscfg/syscfg_l0.yaml new file mode 100644 index 000000000..5e1a5fcf6 --- /dev/null +++ b/devices/fields/syscfg/syscfg_l0.yaml @@ -0,0 +1,161 @@ +# System configuration controller and COMP registers for L0 family +CFGR1: + BOOT_MODE: + MainFlash: [0, Main Flash memory boot mode] + SystemFlash: [1, System Flash memory boot mode] + SRAM: [3, Embedded SRAM boot mode] + UFB: + Bank1: + [ + 0, + "Flash Program memory Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if MEM_MODE=00) and Data EEPROM Bank 1 at 0x0808 0000 (aliased at 0x0008 0000 if MEM_MODE=00)", + ] + Bank2: + [ + 1, + "Flash Program memory Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if MEM_MODE=00) and Data EEPROM Bank 2 at 0x0808 0000 (and aliased at 0x0008 0000 if MEM_MODE=00)", + ] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] +CFGR2: + I2C3_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers"] + I2C2_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers"] + I2C1_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers"] + I2C_PB9_FMP: + Standard: [0, PB9 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] + I2C_PB8_FMP: + Standard: [0, PB8 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] + I2C_PB7_FMP: + Standard: [0, PB7 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] + I2C_PB6_FMP: + Standard: [0, PB6 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] + FWDIS: + Enabled: [0, Firewall access enabled] + Disabled: [1, Firewall access disabled] +CFGR3: + REF_LOCK: + ReadWrite: [0, "SYSCFG_CFGR3[31:0] bits are read/write"] + ReadOnly: [1, "SYSCFG_CFGR3[31:0] bits are read-only"] + VREFINT_RDYF: + NotReady: [0, VREFINT OFF] + Ready: [1, VREFINT ready] + ENBUF_VREFINT_COMP2: + Disabled: [0, Disables the buffer used to generate VREFINT references for COMP2] + Enabled: [1, Enables the buffer used to generate VREFINT references for COMP2] + ENBUF_SENSOR_ADC: + Disabled: [0, Disables the buffer used to generate VREFINT reference for the temperature sensor] + Enabled: [1, Enables the buffer used to generate VREFINT reference for the temperature sensor] + ENBUF_VREFINT_ADC: + Disabled: [0, Disables the buffer used to generate VREFINT reference for the ADC] + Enabled: [1, Enables the buffer used to generate VREFINT reference for the ADC] + SEL_VREF_OUT: + NoConnection: [0, no pad connected] + PB0: [1, PB0 connected] + PB1: [2, PB1 connected] + Both: [3, PB0 and PB1 connected] + EN_VREFINT: + Disabled: [0, "VREFINT voltage disabled in low-power mode (if ULP=1) and scaler for COMP2 disabled"] + Enabled: [1, VREFINT voltage enabled in low-power mode and scaler for COMP2 enabled] +EXTICR1: + _derive: + EXTI[123]: EXTI0 + EXTI0: + _name: ExtiAbcdeh + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PH: [5, Select PHx as the source input for the EXTIx external interrupt] +EXTICR2: + _derive: + EXTI[567]: EXTI4 + EXTI4: + _name: ExtiAbcde + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] +EXTICR3: + _derive: + EXTI*: EXTICR1.EXTI0 +EXTICR4: + _derive: + EXTI*: EXTICR2.EXTI4 +COMP1_CSR: + COMP1LOCK: + ReadWrite: [0, "COMP1_CSR[31:0] for comparator 1 are read/write"] + ReadOnly: [1, "COMP1_CSR[31:0] for comparator 1 are read-only"] + COMP1VALUE: + _read: + NotEqual: [0, Comparator values are not equal] + Equal: [1, Comparator values are equal] + COMP1POLARITY: + NotInverted: [0, Comparator 1 output value not inverted] + Inverted: [1, Comparator 1 output value inverted] + COMP1LPTIMIN1: + Gated: [0, Comparator 1 output gated] + NotGated: [1, Comparator 1 output sent to LPTIM input 1] + COMP1WM: + PA1: [0, Plus input of comparator 1 connected to PA1] + Comp2Plus: [1, Plus input of comparator 1 shorted with Plus input of comparator 2 (see COMP1_CSR)] + COMP1INNSEL: + VREFINT: [0, VREFINT] + PA0: [1, PA0] + PA4: [2, PA4] + PA5: [3, PA5] + COMP1EN: + Disabled: [0, Comparator 1 switched OFF] + Enabled: [1, Comparator 1 switched ON] +COMP2_CSR: + COMP2LOCK: + ReadWrite: [0, "COMP2_CSR[31:0] for comparator 2 are read/write"] + ReadOnly: [1, "COMP2_CSR[31:0] for comparator 2 are read-only"] + COMP2VALUE: + _read: + NotEqual: [0, Comparator values are not equal] + Equal: [1, Comparator values are equal] + COMP2POLARITY: + NotInverted: [0, Comparator 2 output value not inverted] + Inverted: [1, Comparator 2 output value inverted] + COMP2LPTIMIN1: + Gated: [0, Comparator 2 output gated] + NotGated: [1, Comparator 2 output sent to LPTIM input 1] + COMP2LPTIMIN2: + Gated: [0, Comparator 2 output gated] + NotGated: [1, Comparator 2 output sent to LPTIM input 2] + COMP2INPSEL: + PA3: [0, PA3] + PB4: [1, PB4] + PB5: [2, PB5] + PB6: [3, PB6] + PB7: [4, PB7] + PA7: [5, PA7] + COMP2INNSEL: + VREFINT: [0, VREFINT] + PA2: [1, PA2] + PA4: [2, PA4] + PA5: [3, PA5] + VREFINT_Div4: [4, 1/4 VREFINT] + VREFINT_Div2: [5, 1/2 VREFINT] + VREFINT_Div3_4: [6, 3/4 VREFINT] + PB3: [7, PB3] + COMP2SPEED: + Slow: [0, Slow speed] + Fast: [1, Fast speed] + COMP2EN: + Disabled: [0, Comparator 2 switched OFF] + Enabled: [1, Comparator 2 switched ON] diff --git a/devices/fields/syscfg/syscfg_l0x0.yaml b/devices/fields/syscfg/syscfg_l0x0.yaml new file mode 100644 index 000000000..ff53096da --- /dev/null +++ b/devices/fields/syscfg/syscfg_l0x0.yaml @@ -0,0 +1,60 @@ +# System configuration controller and COMP registers for L0 family +CFGR1: + BOOT_MODE: + MainFlash: [0, Main Flash memory boot mode] + SystemFlash: [1, System Flash memory boot mode] + SRAM: [3, Embedded SRAM boot mode] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] +CFGR2: + _delete: CAPA + _modify: + FWDISEN: + name: FWDIS +CFGR3: + REF_LOCK: + ReadWrite: [0, "SYSCFG_CFGR3[31:0] bits are read/write"] + ReadOnly: [1, "SYSCFG_CFGR3[31:0] bits are read-only"] + VREFINT_RDYF: + NotReady: [0, VREFINT OFF] + Ready: [1, VREFINT ready] + ENBUF_SENSOR_ADC: + Disabled: [0, Disables the buffer used to generate VREFINT reference for the temperature sensor] + Enabled: [1, Enables the buffer used to generate VREFINT reference for the temperature sensor] + SEL_VREF_OUT: + NoConnection: [0, no pad connected] + PB0: [1, PB0 connected] + PB1: [2, PB1 connected] + Both: [3, PB0 and PB1 connected] +EXTICR1: + _derive: + EXTI1: EXTI0 + EXTI3: EXTI2 + EXTI0: + _name: ExtiAbcdeh + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PH: [5, Select PHx as the source input for the EXTIx external interrupt] + EXTI2: + _name: ExtiAbcde + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] +EXTICR2: + _derive: + EXTI*: EXTICR1.EXTI2 +EXTICR3: + _derive: + EXTI8: EXTICR1.EXTI2 + EXTI9: EXTICR1.EXTI0 + EXTI1[01]: EXTICR1.EXTI0 +EXTICR4: + _derive: + EXTI*: EXTICR1.EXTI2 diff --git a/devices/fields/syscfg/syscfg_l4+.yaml b/devices/fields/syscfg/syscfg_l4+.yaml new file mode 100644 index 000000000..65029a063 --- /dev/null +++ b/devices/fields/syscfg/syscfg_l4+.yaml @@ -0,0 +1,115 @@ +MEMRMP: + FB_MODE: + Normal: [0, "Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000(1)) and Flash Bank 2 mapped at offset"] + Inverted: [1, "Flash Bank 2 mapped at 0x0800 0000 (and aliased @0x0000 0000(1)) and Flash Bank 1 mapped at offset"] + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x00000000] + SystemFlash: [1, System Flash memory mapped at 0x00000000] + FMC: [2, FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000] + SRAM1: [3, SRAM1 mapped at 0x00000000] + OCTOSPI1: [4, OCTOSPI1 memory mapped at 0x00000000] + OCTOSPI2: [5, OCTOSPI2 memory mapped at 0x00000000] + +CFGR1: + FPU_IE?: + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] + I2C?_FMP: + Disabled: [0, "Fm+ mode is not enabled on I2Cx pins selected through AF selection bits"] + Enabled: [1, "Fm+ mode is enabled on I2Cx pins selected through AF selection bits"] + I2C_PB?_FMP: + Disabled: [0, PBx pin operates in standard mode] + Enabled: [1, "Fm+ mode enabled on PB7 pin, and the Speed control is bypassed"] + ANASWVDD: + VDDA: [0, I/O analog switches supplied by VDDA or booster when booster is ON] + VDD: [1, I/O analog switches supplied by VDD] + BOOSTEN: + Disabled: + [ + 0, + I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation, + ] + Enabled: + [ + 1, + I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation, + ] + FWDIS: + Disabled: [1, Firewall protection disabled] + Enabled: [0, Firewall protection enabled] + +EXTICR1: + _derive: + EXTI[123]: EXTI0 + EXTI0: + _name: ExtiAbcdefgh + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + PI: [8, Select PIx as the source input for the EXTIx external interrupt] + +EXTICR[23]: + _derive: + EXTI*: EXTICR1.EXTI0 + +EXTICR4: + _derive: + EXTI1[345]: EXTI12 + EXTI12: + _name: ExtiAbcdefgh + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + PG: [6, Select PGx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + +SCSR: + SRAM2BS: + NotBusy: [0, No SRAM2 erase operation is on going] + Busy: [1, SRAM2 erase operation is on going] + SRAM2ER: + Erase: [1, Setting this bit starts a hardware SRAM2 erase operation] + +CFGR2: + SPF: + Cleared: [0, No SRAM2 parity error detected] + Set: [1, SRAM2 parity error detected] + ECCL: + Disconnected: [0, ECC error disconnected from TIM1/8/15/16/17 Break input] + Connected: [1, ECC error connected to TIM1/8/15/16/17 Break input] + PVDL: + Disconnected: + [ + 0, + "PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application", + ] + Connected: [1, "PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0] bits are read only"] + SPL: + Disconnected: [0, SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs] + Connected: [1, SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs] + CLL: + Disconnected: [0, "Cortex®-M4 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs"] + Connected: [1, "Cortex®-M4 LOCKUP output connected to TIM1/8/15/16/17 Break inputs"] + +SWPR: + P*WP: + Disabled: [0, Write protection of SRAM2 page x is disabled] + Enabled: [1, Write protection of SRAM2 page x is enabled] + +SKR: + KEY: + Key1: [0xCA, "1. Write 0xCA into Key[7:0]"] + Key2: [0x53, "2. Write 0x53 into Key[7:0]"] + +SWPR2: + P*WP: + Disabled: [0, Write protection of SRAM2 page x is disabled] + Enabled: [1, Write protection of SRAM2 page x is enabled] diff --git a/devices/fields/syscfg/syscfg_wb.yaml b/devices/fields/syscfg/syscfg_wb.yaml new file mode 100644 index 000000000..7e1866eec --- /dev/null +++ b/devices/fields/syscfg/syscfg_wb.yaml @@ -0,0 +1,155 @@ +MEMRMP: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] + QUADSPI: [6, QUADSPI memory mapped at 0x0000_0000] + +CFGR1: + _split: [FPU_IE] + FPU_IE5: + Disabled: [0, Inexact interrupt disable] + Enabled: [1, Inexact interrupt enable] + FPU_IE4: + Disabled: [0, Input denormal interrupt disable] + Enabled: [1, Input denormal interrupt enable] + FPU_IE3: + Disabled: [0, Overflow interrupt disable] + Enabled: [1, Overflow interrupt enable] + FPU_IE2: + Disabled: [0, Underflow interrupt disable] + Enabled: [1, Underflow interrupt enable] + FPU_IE1: + Disabled: [0, Devide-by-zero interrupt disable] + Enabled: [1, Devide-by-zero interrupt enable] + FPU_IE0: + Disabled: [0, Invalid operation interrupt disable] + Enabled: [1, Invalid operation interrupt enable] + I2C3_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers"] + I2C1_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers"] + I2C_PB9_FMP: + Standard: [0, PB9 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] + I2C_PB8_FMP: + Standard: [0, PB8 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] + I2C_PB7_FMP: + Standard: [0, PB7 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] + I2C_PB6_FMP: + Standard: [0, PB6 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] + BOOSTEN: + Disabled: + [ + 0, + I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation, + ] + Enabled: + [ + 1, + I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation, + ] + +SCSR: + C2RFD: + Disabled: [0, "CPU2 fetch from SRAM1, SRAM2a and SRAM2b enabled"] + Enabled: [1, "CPU2 fetch from SRAM1, SRAM2a and SRAM2b disabled"] + SRAM2BSY: + Idle: [0, No SRAM2 or PKA RAM erase operation is ongoing] + Busy: [1, SRAM2 and/or PKA RAM erase operation is ongoing] + SRAM2ER: + _write: + Erase: [1, Start SRAM2 erase operation] + +CFGR2: + _modify: + ECCL: + access: read-write + PVDL: + access: read-write + SPL: + access: read-write + CLL: + access: read-write + SPF: + _read: + Nominal: [0, No SRAM2 parity error detected] + Error: [1, SRAM2 parity error detected] + _write: + Clear: [1, Clear SRAM2 parity error flag] + ECCL: + _read: + Disconnected: [0, ECC error disconnected from TIM1/16/17 break input] + Connected: [1, ECC error connected to TIM1/16/17 break input] + _write: + Connect: [1, Connect ECC error to TIM1/16/17 break input] + PVDL: + _read: + Disconnected: + [ + 0, + "PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be programmed by the application", + ] + Connected: [1, "PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only"] + _write: + Connect: [1, Connect PVD interretup to TIM1/16/17 break input] + SPL: + _read: + Disconnected: [0, SRAM2 parity error signal disconnected from TIM1/16/17 break input] + Connected: [1, SRAM2 parity error signal connected to TIM1/16/17 break input] + _write: + Connect: [1, Connect SRAM2 parity error signal to TIM1/16/17 break input] + CLL: + _read: + Disconnected: [0, CPU LOCKUP output disconnected from TIM1/16/17 break input] + Connected: [1, CPU LOCKUP output connected to TIM1/16/17 break input] + _write: + Connect: [1, Connect CPU LOCKUP output to TIM1/16/17 break input] + +SWPR: + P??WP: + Disabled: [0, SRAM2 1 KB page protection disabled] + Enabled: [1, SRAM2 1 KB page protection enabled] + P?WP: + Disabled: [0, SRAM2 1 KB page protection disabled] + Enabled: [1, SRAM2 1 KB page protection enabled] + +SKR: + KEY: + Step1: [0xCA, Step 1 to remove SRAM2ER bits write protection] + Step2: [0x53, Step 2 to remove SRAM2ER bits write protection] + WriteProtect: [0x11, Activate SRAM2ER bits write protection] + +SWPR2: + P??WP: + Disabled: [0, SRAM2 1 KB page protection disabled] + Enabled: [1, SRAM2 1 KB page protection enabled] + +IMR?: + "*IM": + Unmasked: [0, Peripheral interrupt forwarded to CPU1] + Masked: [1, Peripheral interrupt to CPU1 masked] + +C2IMR?: + "*": + Unmasked: [0, Peripheral interrupt forwarded to CPU2] + Masked: [1, Peripheral interrupt to CPU2 masked] + +SIPCR: + SRNG: + Disabled: [0, True RNG security disabled] + Enabled: [1, True RNG security enabled] + SPKA: + Disabled: [0, PKA security disabled] + Enabled: [1, PKA security enabled] + SAES2: + Disabled: [0, AES2 security disabled] + Enabled: [1, AES2 security enabled] + SAES1: + Disabled: [0, "AES1 KEY[7:0] security disabled"] + Enabled: [1, "AES1 KEY[7:0] security enabled"] diff --git a/devices/fields/syscfg/syscfg_wb55.yaml b/devices/fields/syscfg/syscfg_wb55.yaml new file mode 100644 index 000000000..eaf448622 --- /dev/null +++ b/devices/fields/syscfg/syscfg_wb55.yaml @@ -0,0 +1,36 @@ +_include: + - syscfg_wb.yaml + +EXTICR1: + _derive: + EXTI[13]: EXTI0 + EXTI0: + _name: ExtiAbcdeh + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + EXTI2: + _name: ExtiAbcde + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PE: [4, Select PEx as the source input for the EXTIx external interrupt] + +EXTICR2: + _derive: + EXTI4: EXTICR1.EXTI2 + EXTI[67]: EXTI5 + EXTI5: + _name: ExtiAbcd + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + +EXTICR[34]: + _derive: + EXTI*: EXTICR2.EXTI5 diff --git a/devices/fields/syscfg/syscfg_wl.yaml b/devices/fields/syscfg/syscfg_wl.yaml new file mode 100644 index 000000000..ea1994e2e --- /dev/null +++ b/devices/fields/syscfg/syscfg_wl.yaml @@ -0,0 +1,137 @@ +MEMRMP: + MEM_MODE: + MainFlash: [0, Main Flash memory mapped at 0x0000_0000] + SystemFlash: [1, System Flash memory mapped at 0x0000_0000] + SRAM: [3, Embedded SRAM mapped at 0x0000_0000] + +CFGR1: + I2C3_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers"] + I2C2_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers"] + I2C1_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers"] + I2C_PB9_FMP: + Standard: [0, PB9 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] + I2C_PB8_FMP: + Standard: [0, PB8 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] + I2C_PB7_FMP: + Standard: [0, PB7 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] + I2C_PB6_FMP: + Standard: [0, PB6 pin operate in standard mode] + FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] + BOOSTEN: + Disabled: + [ + 0, + I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation, + ] + Enabled: + [ + 1, + I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation, + ] + +EXTICR1: + _derive: + EXTI[12]: EXTI0 + EXTI0: + _name: ExtiAbc + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + EXTI3: + _name: ExtiAbch + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PH: [7, Select PHx as the source input for the EXTIx external interrupt] + +EXTICR2: + _derive: + EXTI[456]: EXTICR1.EXTI0 + EXTI7: + _name: ExtiAb + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + +EXTICR3: + _derive: + EXTI*: EXTICR2.EXTI7 + +EXTICR4: + _derive: + EXTI12: EXTICR2.EXTI7 + EXTI1[345]: EXTICR1.EXTI0 + +SCSR: + PKASRAMBSY: + Idle: [0, No PKA SRAM erase operation is ongoing] + Busy: [1, PKA SRAM erase operation is ongoing] + SRAMBSY: + Idle: [0, No SRAM1 or SRAM2 erase operation is ongoing] + Busy: [1, SRAM1 or SRAM2 erase operation is ongoing] + SRAM2ER: + _write: + Erase: [1, Start SRAM2 erase operation] + +CFGR2: + SPF: + _read: + Nominal: [0, No SRAM2 parity error detected] + Error: [1, SRAM2 parity error detected] + _write: + Clear: [1, Clear SRAM2 parity error flag] + ECCL: + _read: + Disconnected: [0, ECC error disconnected from TIM1/16/17 break input] + Connected: [1, ECC error connected to TIM1/16/17 break input] + _write: + Connect: [1, Connect ECC error to TIM1/16/17 break input] + PVDL: + _read: + Disconnected: + [ + 0, + "PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be programmed by the application", + ] + Connected: [1, "PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only"] + _write: + Connect: [1, Connect PVD interretup to TIM1/16/17 break input] + SPL: + _read: + Disconnected: [0, SRAM2 parity error signal disconnected from TIM1/16/17 break input] + Connected: [1, SRAM2 parity error signal connected to TIM1/16/17 break input] + _write: + Connect: [1, Connect SRAM2 parity error signal to TIM1/16/17 break input] + CLL: + _read: + Disconnected: [0, CPU LOCKUP output disconnected from TIM1/16/17 break input] + Connected: [1, CPU LOCKUP output connected to TIM1/16/17 break input] + _write: + Connect: [1, Connect CPU LOCKUP output to TIM1/16/17 break input] + +SWPR: + P??WP: + Disabled: [0, SRAM2 1 KB page protection disabled] + Enabled: [1, SRAM2 1 KB page protection enabled] + P?WP: + Disabled: [0, SRAM2 1 KB page protection disabled] + Enabled: [1, SRAM2 1 KB page protection enabled] + +SKR: + KEY: + Step1: [0xCA, Step 1 to remove SRAM2ER bits write protection] + Step2: [0x53, Step 2 to remove SRAM2ER bits write protection] + WriteProtect: [0x11, Activate SRAM2ER bits write protection] + +RFDCR: + RFTBSEL: + Digital: [0, "Digital test bus selected on RF_ADTB[3:0]"] + Analog: [1, "Analog test bus selected on RF_ADTB[3:0]"] diff --git a/devices/fields/tamp/tamp_wl.yaml b/devices/fields/tamp/tamp_wl.yaml new file mode 100644 index 000000000..58f7c8964 --- /dev/null +++ b/devices/fields/tamp/tamp_wl.yaml @@ -0,0 +1,108 @@ +CR1: + ITAMP?E: + Disabled: [0, Internal tamper x disabled] + Enabled: [1, Internal tamper x enabled] + TAMP?E: + Disabled: [0, Tamper detection on TAMP_INx is disabled] + Enabled: [1, Tamper detection on TAMP_IN3 is enabled] + +CR2: + TAMP?TRG: + FilteredLowOrUnfilteredHigh: + [ + 0, + "If TAMPFLT != 00 Tamper x input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper x input rising edge and high level triggers a tamper detection event", + ] + FilteredHighOrUnfilteredLow: + [ + 1, + "If TAMPFLT != 00 Tamper x input staying high triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge and low level triggers a tamper detection event", + ] + BKERASE: + _write: + Reset: [1, Reset backup registers] + TAMP?MSK: + ResetBySoftware: + [ + 0, + Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection, + ] + ResetByHardware: + [ + 1, + Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. The tamper x interrupt must not be enabled when TAMP3MSK is set, + ] + TAMP?NOER: + Erase: [0, Tamper x event erases the backup registers] + NotErase: [1, Tamper x event does not erase the backup registers] + +CR3: + ITAMP?NOER: + Erase: [0, Internal tamper x event erases the backup registers] + NotErase: [1, Internal tamper x event does not erase the backup registers] + +FLTCR: + TAMPPUDIS: + Enabled: [0, Precharge TAMP_INx pins before sampling (enable internal pull-up)] + Disabled: [1, Disable precharge of TAMP_INx pins] + TAMPPRCH: + Cycles1: [0, 1 RTCCLK cycle] + Cycles2: [1, 2 RTCCLK cycles] + Cycles4: [2, 4 RTCCLK cycles] + Cycles8: [3, 8 RTCCLK cycles] + TAMPFLT: + NoFilter: + [ + 0, + Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input)", + ] + Filter2: [1, Tamper event is activated after 2 consecutive samples at the active level"] + Filter4: [2, Tamper event is activated after 4 consecutive samples at the active level"] + Filter8: [3, Tamper event is activated after 8 consecutive samples at the active level"] + TAMPFREQ: + Hz_1: [0, "RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)"] + Hz_2: [1, "RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)"] + Hz_4: [2, "RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)"] + Hz_8: [3, "RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)"] + Hz_16: [4, "RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)"] + Hz_32: [5, "RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)"] + Hz_64: [6, "RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)"] + Hz_128: [7, "RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"] + +IER: + ITAMP?IE: + Disabled: [0, Internal tamper x interrupt disabled] + Enabled: [1, Internal tamper x interrupt enabled] + TAMP?IE: + Disabled: [0, Tamper x interrupt disabled] + Enabled: [1, Tampoer x interrupt enabled] + +SR: + ITAMP?F: + Idle: [0, No tamper detected] + Tamper: [1, Internal tamper detected] + TAMP?F: + Idle: [0, No tamper detected] + Tamper: [1, Tamper detected] + +MISR: + ITAMP?MF: + Idle: [0, No tamper detected - Masked] + Tamper: [1, Internal tamper detected - Masked] + TAMP?MF: + Idle: [0, No tamper detected - Masked] + Tamper: [1, Tamper detected - Masked] + +SCR: + CITAMP?F: + _write: + Clear: [1, Clear tamper flag] + CTAMP?F: + _write: + Clear: [1, Clear tamper flag] + +COUNTR: + COUNT: [0, 0xFFFFFFFF] + +BKP?*R: + BKP: [0, 0xFFFFFFFF] diff --git a/devices/fields/tim/basic.yaml b/devices/fields/tim/basic.yaml new file mode 100644 index 000000000..a7bd8ca91 --- /dev/null +++ b/devices/fields/tim/basic.yaml @@ -0,0 +1,36 @@ +CR1: + ARPE: + Disabled: [0, TIMx_APRR register is not buffered] + Enabled: [1, TIMx_APRR register is buffered] + "?~OPM": + Disabled: [0, Counter is not stopped at update event] + Enabled: [1, Counter stops counting at the next update event (clearing the CEN bit)] + URS: + AnyEvent: + [ + 0, + "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request", + ] + CounterOnly: [1, Only counter overflow/underflow generates an update interrupt or DMA request] + UDIS: + Enabled: [0, Update event enabled] + Disabled: [1, Update event disabled] + CEN: + Disabled: [0, Counter disabled] + Enabled: [1, Counter enabled] +DIER: + UIE: + Disabled: [0, Update interrupt disabled] + Enabled: [1, Update interrupt enabled] +SR: + UIF: + _read: + NoUpdateOccurred: [0, No update occurred] + UpdatePending: [1, Update interrupt pending] + _W0C: + Clear: [0, Clear flag] +EGR: + UG: + Update: [1, Re-initializes the timer counter and generates an update of the registers.] +PSC: + PSC: [0, 0xFFFF] diff --git a/devices/fields/tim/bdtr_common.yaml b/devices/fields/tim/bdtr_common.yaml new file mode 100644 index 000000000..97709a237 --- /dev/null +++ b/devices/fields/tim/bdtr_common.yaml @@ -0,0 +1,41 @@ +BDTR: + MOE: + DisabledIdle: [0, OC/OCN are disabled or forced idle depending on OSSI] + Enabled: [1, OC/OCN are enabled if CCxE/CCxNE are set] + AOE: + Manual: [0, MOE can be set only by software] + Automatic: + [ + 1, + MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active), + ] + "BKP,BK2P": + ActiveLow: [0, Break input BRKx is active low] + ActiveHigh: [1, Break input BRKx is active high] + "BKE,BK2E": + Disabled: [0, Break function x disabled] + Enabled: [1, Break function x enabled] + OSSR: + HiZ: [0, "When inactive, OC/OCN outputs are disabled"] + IdleLevel: [1, "When inactive, OC/OCN outputs are enabled with their inactive level"] + OSSI: + HiZ: [0, "When inactive, OC/OCN outputs are disabled"] + IdleLevel: [1, "When inactive, OC/OCN outputs are forced to idle level"] + LOCK: + "Off": [0, No bit is write protected] + Level1: + [ + 1, + "Any bits except MOE, OSSR, OSSI and LOCK in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register can no longer be written", + ] + Level2: + [ + 2, + "LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written", + ] + Level3: + [ + 3, + "LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written", + ] + DTG: [0, 0xFF] diff --git a/devices/fields/tim/ccds.yaml b/devices/fields/tim/ccds.yaml new file mode 100644 index 000000000..abb89f905 --- /dev/null +++ b/devices/fields/tim/ccds.yaml @@ -0,0 +1,4 @@ +CR2: + CCDS: + OnCompare: [0, CCx DMA request sent when CCx event occurs] + OnUpdate: [1, CCx DMA request sent when update event occurs] diff --git a/devices/fields/tim/ccpc.yaml b/devices/fields/tim/ccpc.yaml new file mode 100644 index 000000000..56ac8dffb --- /dev/null +++ b/devices/fields/tim/ccpc.yaml @@ -0,0 +1,11 @@ +CR2: + CCPC: + NotPreloaded: [0, "CCxE, CCxNE and OCxM bits are not preloaded"] + Preloaded: [1, "CCxE, CCxNE and OCxM bits are preloaded"] + CCUS: + Sw: [0, "When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only"] + SwOrEdge: + [ + 1, + "When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI", + ] diff --git a/devices/fields/tim/ccr.yaml b/devices/fields/tim/ccr.yaml new file mode 100644 index 000000000..032c8660b --- /dev/null +++ b/devices/fields/tim/ccr.yaml @@ -0,0 +1,20 @@ +_include: ccr_common.yaml + +CCMR1_Input: + "?~CC2S": + TI2: [1, "CC2 channel is configured as input, IC2 is mapped on TI2"] + TI1: [2, "CC2 channel is configured as input, IC2 is mapped on TI1"] + TRC: [3, "CC2 channel is configured as input, IC2 is mapped on TRC"] + CC1S: + TI1: [1, "CC1 channel is configured as input, IC1 is mapped on TI1"] + TI2: [2, "CC1 channel is configured as input, IC1 is mapped on TI2"] + TRC: [3, "CC1 channel is configured as input, IC1 is mapped on TRC"] +"?~CCMR2_Input": + CC4S: + TI4: [1, "CC4 channel is configured as input, IC4 is mapped on TI4"] + TI3: [2, "CC4 channel is configured as input, IC4 is mapped on TI3"] + TRC: [3, "CC4 channel is configured as input, IC4 is mapped on TRC"] + CC3S: + TI3: [1, "CC3 channel is configured as input, IC3 is mapped on TI3"] + TI4: [2, "CC3 channel is configured as input, IC3 is mapped on TI4"] + TRC: [3, "CC3 channel is configured as input, IC3 is mapped on TRC"] diff --git a/devices/fields/tim/ccr1.yaml b/devices/fields/tim/ccr1.yaml new file mode 100644 index 000000000..358698f6c --- /dev/null +++ b/devices/fields/tim/ccr1.yaml @@ -0,0 +1,5 @@ +_include: ccr_common.yaml + +CCMR1_Input: + CC1S: + TI1: [1, "CC1 channel is configured as input, IC1 is mapped on TI1"] diff --git a/devices/fields/tim/ccr_common.yaml b/devices/fields/tim/ccr_common.yaml new file mode 100644 index 000000000..7a3d2480a --- /dev/null +++ b/devices/fields/tim/ccr_common.yaml @@ -0,0 +1,88 @@ +"?~CR2": + "?~OIS?N": + Reset: [0, "OCxN=0 after a dead-time when MOE=0"] + Set: [1, "OCxN=1 after a dead-time when MOE=0"] + "?~OIS?": + Reset: [0, "OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0"] + Set: [1, "OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0"] + +DIER: + "?~CC?DE": + Disabled: [0, CCx DMA request disabled] + Enabled: [1, CCx DMA request enabled] + CC?IE: + Disabled: [0, CCx interrupt disabled] + Enabled: [1, CCx interrupt enabled] +SR: + CC?OF: + _read: + NoOvercapture: [0, No overcapture has been detected] + Overcapture: [1, The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set] + _W0C: + Clear: [0, Clear flag] + CC?IF: + _read: + NoMatch: [0, No campture/compare has been detected] + Match: + [ + 1, + "If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register.", + ] + _W0C: + Clear: [0, Clear flag] +EGR: + CC?G: + _write: + Trigger: + [ + 1, + "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register.", + ] + +CCMR?_Input: + IC?F: + _name: ICFilter + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + IC?PSC: + _name: ICPrescaler + NoPrescaler: [0, "No prescaler, capture is done each time an edge is detected on the capture input"] + TwoEvents: [1, Capture is done once every 2 events] + FourEvents: [2, Capture is done once every 4 events] + EightEvents: [3, Capture is done once every 8 events] + +CCMR?_Output: + OC?FE: + Disabled: [0, Fast output disabled] + Enabled: [1, Fast output enabled] + OC?PE: + Disabled: [0, Preload register on CCRx disabled. New values written to CCRx are taken into account immediately] + Enabled: [1, Preload register on CCRx enabled. Preload value is loaded into active register on each update event] +CCMR[12]_Output: + CC?S: + Output: [0, CCx channel is configured as output] + +CCER: + "?~CC?NE": + Disabled: [0, Complementary output disabled] + Enabled: [1, Complementary output enabled] + CC?E: + Disabled: [0, Capture disabled] + Enabled: [1, Capture enabled] + CC?P: + RisingEdge: [0, Noninverted/rising edge] + FallingEdge: [1, Inverted/falling edge] diff --git a/devices/fields/tim/ccxnp.yaml b/devices/fields/tim/ccxnp.yaml new file mode 100644 index 000000000..613bc5395 --- /dev/null +++ b/devices/fields/tim/ccxnp.yaml @@ -0,0 +1,4 @@ +CCER: + CC?NP: + ActiveHigh: [0, OCxN active high] + ActiveLow: [1, OCxN active low] diff --git a/devices/fields/tim/com_break.yaml b/devices/fields/tim/com_break.yaml new file mode 100644 index 000000000..2c45d5367 --- /dev/null +++ b/devices/fields/tim/com_break.yaml @@ -0,0 +1,37 @@ +DIER: + COMIE: + Disabled: [0, COM interrupt disabled] + Enabled: [1, COM interrupt enabled] + BIE: + Disabled: [0, Break interrupt disabled] + Enabled: [1, Break interrupt enabled] + +SR: + BIF: + _read: + NoTrigger: [0, No break event occurred] + Trigger: + [ + 1, + "An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register", + ] + _W0C: + Clear: [0, Clear flag] + COMIF: + _read: + NoCOM: [0, No COM event occurred] + COM: [1, COM interrupt pending] + _W0C: + Clear: [0, Clear flag] + +EGR: + BG: + _write: + Trigger: + [ + 1, + A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled, + ] + COMG: + _write: + Trigger: [1, "When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated"] diff --git a/devices/fields/tim/dithen.yaml b/devices/fields/tim/dithen.yaml new file mode 100644 index 000000000..4e62e7cfb --- /dev/null +++ b/devices/fields/tim/dithen.yaml @@ -0,0 +1,4 @@ +CR1: + DITHEN: + Disabled: [0, Dithering disabled] + Enabled: [1, Dithering enabled] diff --git a/devices/fields/tim/external.yaml b/devices/fields/tim/external.yaml new file mode 100644 index 000000000..5462dfacb --- /dev/null +++ b/devices/fields/tim/external.yaml @@ -0,0 +1,29 @@ +SMCR: + ETP: + NotInverted: [0, "ETR is noninverted, active at high level or rising edge"] + Inverted: [1, "ETR is inverted, active at low level or falling edge"] + ECE: + Disabled: [0, External clock mode 2 disabled] + Enabled: [1, External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.] + ETPS: + Div1: [0, Prescaler OFF] + Div2: [1, ETRP frequency divided by 2] + Div4: [2, ETRP frequency divided by 4] + Div8: [3, ETRP frequency divided by 8] + ETF: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] diff --git a/devices/fields/tim/generic.yaml b/devices/fields/tim/generic.yaml new file mode 100644 index 000000000..630bc39b7 --- /dev/null +++ b/devices/fields/tim/generic.yaml @@ -0,0 +1,29 @@ +# Common base for 16bit and 32bit TIM2 peripheral + +_include: + - ccds.yaml + - external.yaml + - trigger.yaml + +CR2: + TI1S: + Normal: [0, The TIMx_CH1 pin is connected to TI1 input] + XOR: [1, "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] +SMCR: + MSM: + NoSync: [0, No action] + Sync: + [ + 1, + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event., + ] +DIER: + TDE: + Disabled: [0, Trigger DMA request disabled] + Enabled: [1, Trigger DMA request enabled] + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] +DCR: + DBL: [0, 18] + DBA: [0, 31] diff --git a/devices/fields/tim/tim12_common_wl.yaml b/devices/fields/tim/tim12_common_wl.yaml new file mode 100644 index 000000000..09c029f50 --- /dev/null +++ b/devices/fields/tim/tim12_common_wl.yaml @@ -0,0 +1,101 @@ +# Common base for 16bit and 32bit TIM2 peripheral + +_include: + - ccds.yaml + - trigger.yaml + - external.yaml + - ccxnp.yaml + +CR1: + UIFREMAP: + Disabled: [0, No remapping. UIF status bit is not copied to TIMx_CNT register bit 31] + Enabled: [1, Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31] +CR2: + TI1S: + Normal: [0, The TIMx_CH1 pin is connected to TI1 input] + XOR: [1, "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + MMS: + Reset: [0, The UG bit from the TIMx_EGR register is used as trigger output] + Enable: [1, "The counter enable signal, CNT_EN, is used as trigger output"] + Update: [2, The update event is selected as trigger output] + ComparePulse: + [ + 3, + "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred", + ] + CompareOC1: [4, OC1REF signal is used as trigger output] + CompareOC2: [5, OC2REF signal is used as trigger output] + CompareOC3: [6, OC3REF signal is used as trigger output] + CompareOC4: [7, OC4REF signal is used as trigger output] +SMCR: + MSM: + NoSync: [0, No action] + Sync: + [ + 1, + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event, + ] + TS: + ITR0: [0, Internal Trigger 0 (ITR0)] + ITR1: [1, Internal Trigger 1 (ITR1)] + ITR2: [2, Internal Trigger 2 (ITR2)] + TI1F_ED: [4, TI1 Edge Detector (TI1F_ED)] + TI1FP1: [5, Filtered Timer Input 1 (TI1FP1)] + TI2FP2: [6, Filtered Timer Input 2 (TI2FP2)] + ETRF: [7, External Trigger input (ETRF)] + SMS_3: + Disabled: [0, "Slave mode disabled (see SMS[0:2])"] + CombinedResetTrigger: + [ + 1, + "SMS[0:2] must be 0b000 (DisabledOrCombined). Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter", + ] + SMS: + DisabledOrCombined: + [ + 0, + "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. If SMS[3]=1 then Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter", + ] + EncoderMode1: [1, Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level] + EncoderMode2: [2, Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level] + EncoderMode3: + [ + 3, + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input, + ] + ResetMode: + [ + 4, + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers, + ] + GatedMode: + [ + 5, + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled, + ] + TriggerMode: + [ + 6, + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled, + ] + ExtClockMode: [7, External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter] +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] + +DCR: + DBL: [0, 0b10001] + DBA: [0, 31] + +AF1: + _modify: + "ResETRSEL,ETRSEL": + name: ETRSEL + ETRSEL: + Legacy: [0, ETR legacy mode] + COMP1: [1, COMP1 output] + COMP2: [2, COMP2 output] +TISEL: + TI?SEL: + Selected: [0, TIM1_CHx input selected] diff --git a/devices/fields/tim/tim16.yaml b/devices/fields/tim/tim16.yaml new file mode 100644 index 000000000..e5ac887a9 --- /dev/null +++ b/devices/fields/tim/tim16.yaml @@ -0,0 +1,4 @@ +_include: + - ccds.yaml + - ccpc.yaml + - com_break.yaml diff --git a/devices/fields/tim/tim16_wl.yaml b/devices/fields/tim/tim16_wl.yaml new file mode 100644 index 000000000..99deff508 --- /dev/null +++ b/devices/fields/tim/tim16_wl.yaml @@ -0,0 +1,76 @@ +_include: + - tim16.yaml + - tim_16bit.yaml + - ccxnp.yaml + - bdtr_common.yaml + +DMAR: + DMAB: [0, 0xFFFF] + +CR1: + UIFREMAP: + Disabled: [0, No remapping. UIF status bit is not copied to TIMx_CNT register bit 31] + Enabled: [1, Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31] + +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] + +EGR: + CC?G: + _write: + Trigger: + [ + 1, + "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register", + ] + +RCR: + REP: [0, 0xFF] + +BDTR: + _modify: + DT: + name: DTG + BKBID: + Input: [0, Break input BRK in input mode] + Bidirectional: [1, Break input BRK in bidirectional mode] + BKDSRM: + Armed: [0, Break input BRK is armed] + Disarmed: [1, Break input BRK is disarmed] + +DCR: + DBL: [0, 0b10001] + DBA: [0, 31] + +OR1: + TI1_RMP: + GPIO: [0, TI1 is connected to GPIO] + LSI: [1, TI1 is connected to LSI] + LSE: [2, TI1 is connected to LSE] + RTC: [3, TI1 is connected to RTC wake-up interrupt] + +AF1: + BKCMP2P: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BKCMP1P: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BKINP: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BKCMP2E: + Disabled: [0, COMP2 input disabled] + Enabled: [1, COMP2 input enabled] + BKCMP1E: + Disabled: [0, COMP1 input disabled] + Enabled: [1, COMP1 input enabled] + BKINE: + Disabled: [0, BKIN input disabled] + Enabled: [1, BKIN input enabled] + +TISEL: + TISEL: + Selected: [0, TIM1_CH1 input selected] diff --git a/devices/fields/tim/tim1_advanced.yaml b/devices/fields/tim/tim1_advanced.yaml new file mode 100644 index 000000000..0da02c507 --- /dev/null +++ b/devices/fields/tim/tim1_advanced.yaml @@ -0,0 +1,67 @@ +AF1: + BKCMP?P: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BKINP: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BKCMP?E: + Disabled: [0, Input disabled] + Enabled: [1, Input enabled] + BKINE: + Disabled: [0, BKIN input disabled] + Enabled: [1, BKIN input enabled] + +AF2: + BK2CMP?P: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BK2INP: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BK2CMP?E: + Disabled: [0, Input disabled] + Enabled: [1, Input enabled] + BK2INE: + Disabled: [0, BKIN input disabled] + Enabled: [1, BKIN input enabled] + +BDTR: + BK2BID: + Input: [0, Break input BRK2 in input mode] + Bidirectional: [1, Break input BRK2 in bidirectional mode] + BKBID: + Input: [0, Break input BRK in input mode] + Bidirectional: [1, Break input BRK in bidirectional mode] + BK2DSRM: + Armed: [0, Break input BRK2 is armed] + Disarmed: [1, Break input BRK2 is disarmed] + BKDSRM: + Armed: [0, Break input BRK is armed] + Disarmed: [1, Break input BRK is disarmed] + BK2P: + Low: [0, Break input BRK2 is active low] + High: [1, Break input BRK2 is active high] + BK2E: + Disabled: [0, Break function disabled] + Enabled: [1, Break function enabled] + "BKF,BK2F": + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + +DMAR: + DMAB: [0, 0xFFFF] diff --git a/devices/fields/tim/tim1_wl.yaml b/devices/fields/tim/tim1_wl.yaml new file mode 100644 index 000000000..080560481 --- /dev/null +++ b/devices/fields/tim/tim1_wl.yaml @@ -0,0 +1,147 @@ +_include: + - com_break.yaml + - tim_advanced.yaml + - tim_16bit.yaml + +CR2: + MMS2: + Reset: + [ + 0b0000, + "Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset", + ] + Enable: + [ + 0b0001, + "Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)", + ] + Update: + [ + 0b0010, + "Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer", + ] + ComparePulse: + [ + 0b0011, + "Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2)", + ] + CompareOC1: [0b0100, Compare - OC1REFC signal is used as trigger output (TRGO2)] + CompareOC2: [0b0101, Compare - OC2REFC signal is used as trigger output (TRGO2)] + CompareOC3: [0b0110, Compare - OC3REFC signal is used as trigger output (TRGO2)] + CompareOC4: [0b0111, Compare - OC4REFC signal is used as trigger output (TRGO2)] + CompareOC5: [0b1000, Compare - OC5REFC signal is used as trigger output (TRGO2)] + CompareOC6: [0b1001, Compare - OC6REFC signal is used as trigger output (TRGO2)] + PulseOC4: [0b1010, Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2] + PulseOC6: [0b1011, Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2] + RisingOC4_6: [0b1100, Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2] + RisingOC4_FallingOC6: [0b1101, Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2] + RisingOC5_6: [0b1110, Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2] + RisingOC5_FallingOC6: [0b1111, Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2] + +DIER: + TDE: + Disabled: [0, Trigger DMA request disabled] + Enabled: [1, Trigger DMA request enabled] + +EGR: + _modify: + COM: + name: COMG + +AF1: + BKCMP2P: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BKCMP1P: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BKINP: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BKCMP2E: + Disabled: [0, COMP2 input disabled] + Enabled: [1, COMP2 input enabled] + BKCMP1E: + Disabled: [0, COMP1 input disabled] + Enabled: [1, COMP1 input enabled] + BKINE: + Disabled: [0, BKIN input disabled] + Enabled: [1, BKIN input enabled] + +AF2: + BK2CMP2P: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BK2CMP1P: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BK2INP: + NotInverted: [0, Input polarity not inverted] + Inverted: [1, Input polarity inverted] + BK2CMP2E: + Disabled: [0, COMP2 input disabled] + Enabled: [1, COMP2 input enabled] + BK2CMP1E: + Disabled: [0, COMP1 input disabled] + Enabled: [1, COMP1 input enabled] + BK2INE: + Disabled: [0, BKIN input disabled] + Enabled: [1, BKIN input enabled] + +BDTR: + _modify: + DT: + name: DTG + BK2BID: + Input: [0, Break input BRK2 in input mode] + Bidirectional: [1, Break input BRK2 in bidirectional mode] + BKBID: + Input: [0, Break input BRK in input mode] + Bidirectional: [1, Break input BRK in bidirectional mode] + BK2DSRM: + Armed: [0, Break input BRK2 is armed] + Disarmed: [1, Break input BRK2 is disarmed] + BKDSRM: + Armed: [0, Break input BRK is armed] + Disarmed: [1, Break input BRK is disarmed] + "BKF,BK2F": + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + +RCR: + REP: [0, 0xFFFF] +CCR5: + GC5C3: + Disabled: [0, No effect of OC5REF on OC3REFC] + Enabled: [1, OC3REFC is the logical AND of OC3REFC and OC5REF] + GC5C2: + Disabled: [0, No effect of OC5REF on OC2REFC] + Enabled: [1, OC2REFC is the logical AND of OC2REFC and OC5REF] + GC5C1: + Disabled: [0, No effect of OC5REF on OC1REFC] + Enabled: [1, OC1REFC is the logical AND of OC1REFC and OC5REF] +DMAR: + DMAB: [0, 0xFFFFFFFF] +OR1: + TI1_RMP: + IO: [0, TIM1 input capture 1 is connected to I/O] + COMP1: [1, TIM1 input capture 1 is connected to COMP1 output] + TIM1_ETR_ADC1_RMP: + Select: [0, TIM1_ETR is not connected to ADC AWDx (must be selected when the ETR comes from the ETR input pin)] + ADC_AWD1: [1, TIM1_ETR is connected to ADC AWD1] + ADC_AWD2: [2, TIM1_ETR is connected to ADC AWD2] + ADC_AWD3: [3, TIM1_ETR is connected to ADC AWD3] diff --git a/devices/fields/tim/tim21.yaml b/devices/fields/tim/tim21.yaml new file mode 100644 index 000000000..2c89e802d --- /dev/null +++ b/devices/fields/tim/tim21.yaml @@ -0,0 +1,5 @@ +# TI2_RMP is only available on TIM21 +OR: + TI2_RMP: + GPIO: [0, TIM2x TI2 input connected to GPIO] + COMP2_OUT: [1, TIM2x TI2 input connected to COMP2_OUT] diff --git a/devices/fields/tim/tim2_l0.yaml b/devices/fields/tim/tim2_l0.yaml new file mode 100644 index 000000000..eefde7d20 --- /dev/null +++ b/devices/fields/tim/tim2_l0.yaml @@ -0,0 +1,15 @@ +CCER: + CC?NP: + Negative: [0, Negative polarity] + Positive: [1, Positive polarity] +DMAR: + DMAB: [0, 0xFFFF] +OR: + TI4_RMP: + COMP2_OUT: [1, TIM2 TI4 input connected to COMP2_OUT] + COMP1_OUT: [2, TIM2 TI4 input connected to COMP1_OUT] + ETR_RMP: + COMP1_OUT: [7, TIM2 ETR input is connected to COMP1_OUT] + COMP2_OUT: [6, TIM2 ETR input is connected to COMP2_OUT] + LSE: [5, TIM2 ETR input is connected to LSE] + HSI: [3, TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set] diff --git a/devices/fields/tim/tim2_wl.yaml b/devices/fields/tim/tim2_wl.yaml new file mode 100644 index 000000000..10aef4a20 --- /dev/null +++ b/devices/fields/tim/tim2_wl.yaml @@ -0,0 +1,13 @@ +_include: + - ./tim_32bit.yaml +OR1: + TI4_RMP: + GPIO: [0, "TIM2 TI4 is connected to GPIO: Refer to Alternate Function mapping"] + COMP_1: [1, TIM2 TI4 is connected to COMP1_OUT] + COMP_2: [2, TIM2 TI4 is connected to COMP2_OUT] + COMP_12: [3, TIM2 TI4 is connected to a logical OR between COMP1_OUT and COMP2_OUT] + ETR_RMP: + GPIO: [0, "TIM2 ETR is connected to GPIO: Refer to Alternate Function mapping"] + TIM2_ETR: [1, LSE internal clock is connected to TIM2_ETR input] +DMAR: + DMAB: [0, 0xFFFF] diff --git a/devices/fields/tim/tim2x.yaml b/devices/fields/tim/tim2x.yaml new file mode 100644 index 000000000..dca06599d --- /dev/null +++ b/devices/fields/tim/tim2x.yaml @@ -0,0 +1,139 @@ +# TIM21 and TIM22 peripherals + +CR1: + CMS: + EdgeAligned: [0, The counter counts up or down depending on the direction bit] + CenterAligned1: + [ + 1, + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down., + ] + CenterAligned2: + [ + 2, + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up., + ] + CenterAligned3: + [ + 3, + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down., + ] + DIR: + Up: [0, Counter used as upcounter] + Down: [1, Counter used as downcounter] +CR2: + MMS: + Reset: [0, Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO)] + Enable: [1, "Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO)"] + Update: [2, Update - The update event is selected as trigger output (TRGO)] + ComparePulse: + [ + 3, + "Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred", + ] + OC1REF: [4, OC1REF signal is used as trigger output (TRGO)] + OC2REF: [5, OC2REF signal is used as trigger output (TRGO)] +SMCR: + ETP: + RisingEdge: [0, "ETR is non-inverted, active at high level or rising edge"] + FallingEdge: [1, "ETR is inverted, active at low level or falling edge"] + ECE: + Disabled: [0, External clock mode 2 disabled] + Enabled: [1, External clock mode 2 enabled] + ETPS: + Div1: [0, Prescaler OFF] + Div2: [1, ETRP frequency divided by 2] + Div4: [2, ETRP frequency divided by 4] + Div8: [3, ETRP frequency divided by 8] + ETF: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + MSM: + NoSync: [0, No action] + Sync: + [ + 1, + The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event., + ] + TS: + ITR0: [0, Internal Trigger 0 (ITR0)] + ITR1: [1, Internal Trigger 1 (ITR1)] + ITR2: [2, Internal Trigger 2 (ITR2)] + TI1F_ED: [4, TI1 Edge Detector (TI1F_ED)] + TI1FP1: [5, Filtered Timer Input 1 (TI1FP1)] + TI2FP2: [6, Filtered Timer Input 2 (TI2FP2)] + ETRF: [7, External Trigger input (ETRF)] + SMS: + Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + Encoder_Mode_1: [1, Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.] + Encoder_Mode_2: [2, Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.] + Encoder_Mode_3: + [ + 3, + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input., + ] + Reset_Mode: + [ + 4, + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers., + ] + Gated_Mode: + [ + 5, + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled., + ] + Trigger_Mode: + [ + 6, + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled., + ] + Ext_Clock_Mode: [7, External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.] +DIER: + TIE: + Disabled: [0, Trigger interrupt disabled] + Enabled: [1, Trigger interrupt enabled] +SR: + TIF: + _read: + NoTrigger: [0, No trigger event occurred] + Trigger: [1, Trigger interrupt pending] + _W0C: + Clear: [0, Clear flag] +EGR: + TG: + _write: + Trigger: [1, The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.] +CCER: + CC?NP: + Negative: [0, Negative polarity] + Positive: [1, Positive polarity] +CNT: + CNT: [0, 0xFFFF] +ARR: + ARR: [0, 0xFFFF] +CCR?: + CCR: [0, 0xFFFF] +OR: + TI1_RMP: + GPIO: [0, TIM2x TI1 input connected to GPIO] + COMP2_OUT: [1, TIM2x TI1 input connected to COMP2_OUT] + COMP1_OUT: [2, TIM2x TI1 input connected to COMP1_OUT] + ETR_RMP: + GPIO: [0, TIM2x ETR input connected to GPIO] + COMP2_OUT: [1, TIM2x ETR input connected to COMP2_OUT] + COMP1_OUT: [2, TIM2x ETR input connected to COMP1_OUT] + LSE: [3, TIM2x ETR input connected to LSE clock] diff --git a/devices/fields/tim/tim6_base.yaml b/devices/fields/tim/tim6_base.yaml new file mode 100644 index 000000000..b7bd43cac --- /dev/null +++ b/devices/fields/tim/tim6_base.yaml @@ -0,0 +1,15 @@ +# TIM6 and TIM7 base registers +# Present accross all STM32 except STM32F401 and STM32F411 devices. +# STM32F410 has only TIM6 + +CR2: + MMS: + Reset: [0, Use UG bit from TIMx_EGR register] + Enable: [1, Use CNT bit from TIMx_CEN register] + Update: [2, Use the update event] +CNT: + CNT: [0, 0xFFFF] +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] diff --git a/devices/fields/tim/tim_16bit.yaml b/devices/fields/tim/tim_16bit.yaml new file mode 100644 index 000000000..bf9d4e45c --- /dev/null +++ b/devices/fields/tim/tim_16bit.yaml @@ -0,0 +1,6 @@ +CNT: + CNT: [0, 0xFFFF] +ARR: + ARR: [0, 0xFFFF] +CCR?: + CCR: [0, 0xFFFF] diff --git a/devices/fields/tim/tim_16bit_dither.yaml b/devices/fields/tim/tim_16bit_dither.yaml new file mode 100644 index 000000000..bb0c61d1a --- /dev/null +++ b/devices/fields/tim/tim_16bit_dither.yaml @@ -0,0 +1,6 @@ +CNT: + CNT: [0, 0xFFFF] +ARR: + ARR: [0, 0xFFFFF] +CCR?: + CCR: [0, 0xFFFFF] diff --git a/devices/fields/tim/tim_32bit.yaml b/devices/fields/tim/tim_32bit.yaml new file mode 100644 index 000000000..bdd51e7d8 --- /dev/null +++ b/devices/fields/tim/tim_32bit.yaml @@ -0,0 +1,9 @@ +# 32bit timer peripheral with 4 channel +# Applies to General-purpose (gp) timers + +CNT: + CNT: [0, 0xFFFFFFFF] +ARR: + ARR: [0, 0xFFFFFFFF] +CCR?: + CCR: [0, 0xFFFFFFFF] diff --git a/devices/fields/tim/tim_advanced.yaml b/devices/fields/tim/tim_advanced.yaml new file mode 100644 index 000000000..dea6be7c4 --- /dev/null +++ b/devices/fields/tim/tim_advanced.yaml @@ -0,0 +1,42 @@ +# Advanced-control timers TIM1,TIM8. + +_include: + - ccpc.yaml + - bdtr_common.yaml + +# Various features not present in other timers +DIER: + COMDE: + Disabled: [0, COM DMA request disabled] + Enabled: [1, COM DMA request enabled] + +SR: + "?~SBIF": + _read: + NoTrigger: [0, No break event occurred] + Trigger: + [ + 1, + "An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register", + ] + _W0C: + Clear: [0, Clear flag] + "?~B2IF": + _read: + NoTrigger: [0, No break event occurred] + Trigger: + [ + 1, + "An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register", + ] + _W0C: + Clear: [0, Clear flag] + +EGR: + "?~B2G": + _write: + Trigger: + [ + 1, + A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled, + ] diff --git a/devices/fields/tim/tim_ckd.yaml b/devices/fields/tim/tim_ckd.yaml new file mode 100644 index 000000000..0006dc414 --- /dev/null +++ b/devices/fields/tim/tim_ckd.yaml @@ -0,0 +1,5 @@ +CR1: + CKD: + Div1: [0, "t_DTS = t_CK_INT"] + Div2: [1, "t_DTS = 2 × t_CK_INT"] + Div4: [2, "t_DTS = 4 × t_CK_INT"] diff --git a/devices/fields/tim/tim_common_ext.yaml b/devices/fields/tim/tim_common_ext.yaml new file mode 100644 index 000000000..f17d77852 --- /dev/null +++ b/devices/fields/tim/tim_common_ext.yaml @@ -0,0 +1,73 @@ +# Extended functionality for GP and Advanced timers. Applicable to H5. + +CR2: + MMS: [0, 7] + MMS_3: [0, 1] + +SMCR: + TS: [0, 7] + TS2: [0, 3] + SMS: [0, 7] + SMS_3: [0, 1] + SMSPS: + Update: [0, "SMSM[3:0] is preloaded from Update event"] + Index: [1, "SMSM[3:0] is preloaded from Index event"] + SMSPE: + NotPreloaded: [0, "SMSM[3:0] is not preloaded"] + PreloadEnabled: [1, "SMSM[3:0] is preload is enabled"] + +DIER: + TERRIE: + Disabled: [0, Transition error interrupt disabled] + Enabled: [1, Transition error interrupt enabled] + IERRIE: + Disabled: [0, Index error interrupt disabled] + Enabled: [1, Index error interrupt enabled] + DIRIE: + Disabled: [0, Direction change interrupt disabled] + Enabled: [1, Direction change interrupt enabled] + IDXIE: + Disabled: [0, Index change interrupt disabled] + Enabled: [1, Index change interrupt enabled] + +SR: + TERRF: + _read: + NoTrigger: [0, No encoder transition error has been detected] + Trigger: [1, An encoder transition error has been detected] + _W0C: + Clear: [0, Clear flag] + IERRF: + _read: + NoTrigger: [0, No index error has been detected] + Trigger: [1, An index erorr has been detected] + _W0C: + Clear: [0, Clear flag] + DIRF: + _read: + NoTrigger: [0, No direction change has been detected] + Trigger: [1, A direction change has been detected] + _W0C: + Clear: [0, Clear flag] + IDXF: + _read: + NoTrigger: [0, No index event occurred] + Trigger: [1, An index event has occurred] + _W0C: + Clear: [0, Clear flag] + +AF1: + ETRSEL: + Legacy: [0, ETR legacy mode] + COMP1: [1, COMP1 output] + COMP2: [2, COMP2 output] + +AF2: + OCRSEL: [0, 7] + +TISEL: + TI?SEL: + Selected: [0, TIM1_CHx input selected] + +DCR: + DBSS: [0, 7] diff --git a/devices/fields/tim/tim_gp1.yaml b/devices/fields/tim/tim_gp1.yaml new file mode 100644 index 000000000..d2a10298b --- /dev/null +++ b/devices/fields/tim/tim_gp1.yaml @@ -0,0 +1,21 @@ +CR1: + CMS: + EdgeAligned: [0, The counter counts up or down depending on the direction bit] + CenterAligned1: + [ + 1, + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down., + ] + CenterAligned2: + [ + 2, + The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up., + ] + CenterAligned3: + [ + 3, + The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down., + ] + DIR: + Up: [0, Counter used as upcounter] + Down: [1, Counter used as downcounter] diff --git a/devices/fields/tim/tim_mms_ts_sms.yaml b/devices/fields/tim/tim_mms_ts_sms.yaml new file mode 100644 index 000000000..f4b0028dc --- /dev/null +++ b/devices/fields/tim/tim_mms_ts_sms.yaml @@ -0,0 +1,48 @@ +CR2: + MMS: + Reset: [0, The UG bit from the TIMx_EGR register is used as trigger output] + Enable: [1, "The counter enable signal, CNT_EN, is used as trigger output"] + Update: [2, The update event is selected as trigger output] + ComparePulse: + [ + 3, + "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred", + ] + CompareOC1: [4, OC1REF signal is used as trigger output] + CompareOC2: [5, OC2REF signal is used as trigger output] + CompareOC3: [6, OC3REF signal is used as trigger output] + CompareOC4: [7, OC4REF signal is used as trigger output] +SMCR: + TS: + ITR0: [0, Internal Trigger 0 (ITR0)] + ITR1: [1, Internal Trigger 1 (ITR1)] + ITR2: [2, Internal Trigger 2 (ITR2)] + TI1F_ED: [4, TI1 Edge Detector (TI1F_ED)] + TI1FP1: [5, Filtered Timer Input 1 (TI1FP1)] + TI2FP2: [6, Filtered Timer Input 2 (TI2FP2)] + ETRF: [7, External Trigger input (ETRF)] + SMS: + Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + Encoder_Mode_1: [1, Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.] + Encoder_Mode_2: [2, Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.] + Encoder_Mode_3: + [ + 3, + Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input., + ] + Reset_Mode: + [ + 4, + Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers., + ] + Gated_Mode: + [ + 5, + Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled., + ] + Trigger_Mode: + [ + 6, + Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled., + ] + Ext_Clock_Mode: [7, External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.] diff --git a/devices/fields/tim/tim_uifremap.yaml b/devices/fields/tim/tim_uifremap.yaml new file mode 100644 index 000000000..5723ffdb6 --- /dev/null +++ b/devices/fields/tim/tim_uifremap.yaml @@ -0,0 +1,9 @@ +CR1: + UIFREMAP: + Disabled: [0, No remapping. UIF status bit is not copied to TIMx_CNT register bit 31] + Enabled: [1, Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31] +CNT: + UIFCPY: + _read: + NoUpdateOccurred: [0, No update occurred] + UpdatePending: [1, Update interrupt pending] diff --git a/devices/fields/tim/trigger.yaml b/devices/fields/tim/trigger.yaml new file mode 100644 index 000000000..e5c8cc7df --- /dev/null +++ b/devices/fields/tim/trigger.yaml @@ -0,0 +1,15 @@ +DIER: + TIE: + Disabled: [0, Trigger interrupt disabled] + Enabled: [1, Trigger interrupt enabled] +SR: + TIF: + _read: + NoTrigger: [0, No trigger event occurred] + Trigger: [1, Trigger interrupt pending] + _W0C: + Clear: [0, Clear flag] +EGR: + TG: + _write: + Trigger: [1, The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled.] diff --git a/devices/fields/tim/v1/ccm.yaml b/devices/fields/tim/v1/ccm.yaml new file mode 100644 index 000000000..0a54a3967 --- /dev/null +++ b/devices/fields/tim/v1/ccm.yaml @@ -0,0 +1,26 @@ +CCMR?_Output: + OC?M: + Frozen: + [ + 0, + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs, + ] + ActiveOnMatch: + [ + 1, + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register, + ] + InactiveOnMatch: + [ + 2, + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register, + ] + Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + ForceInactive: [4, OCyREF is forced low] + ForceActive: [5, OCyREF is forced high] + PwmMode1: + [ + 6, + "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active", + ] + PwmMode2: [7, Inversely to PwmMode1] diff --git a/devices/fields/tim/v1/occe.yaml b/devices/fields/tim/v1/occe.yaml new file mode 100644 index 000000000..1a9a43424 --- /dev/null +++ b/devices/fields/tim/v1/occe.yaml @@ -0,0 +1,4 @@ +CCMR?_Output: + OC?CE: + Disabled: [0, OCxRef is not affected by the ETRF signal] + Enabled: [1, OCxRef is cleared as soon as a High level is detected on ETRF signal] diff --git a/devices/fields/tim/v1/tim1.yaml b/devices/fields/tim/v1/tim1.yaml new file mode 100644 index 000000000..936251085 --- /dev/null +++ b/devices/fields/tim/v1/tim1.yaml @@ -0,0 +1,15 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../com_break.yaml + - ../tim_gp1.yaml + - ../generic.yaml + - ../tim_ckd.yaml + - ../tim_advanced.yaml + - ../ccr.yaml + - ../ccxnp.yaml + - occe.yaml + - ccm.yaml + +RCR: + REP: [0, 0xFF] diff --git a/devices/fields/tim/v1/tim10.yaml b/devices/fields/tim/v1/tim10.yaml new file mode 100644 index 000000000..7107d682c --- /dev/null +++ b/devices/fields/tim/v1/tim10.yaml @@ -0,0 +1,6 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../ccr1.yaml + - ccm.yaml diff --git a/devices/fields/tim/v1/tim13.yaml b/devices/fields/tim/v1/tim13.yaml new file mode 100644 index 000000000..9530e0533 --- /dev/null +++ b/devices/fields/tim/v1/tim13.yaml @@ -0,0 +1,2 @@ +_include: + - tim10.yaml diff --git a/devices/fields/tim/v1/tim15.yaml b/devices/fields/tim/v1/tim15.yaml new file mode 100644 index 000000000..6c33c02d9 --- /dev/null +++ b/devices/fields/tim/v1/tim15.yaml @@ -0,0 +1,22 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../ccds.yaml + - ../ccpc.yaml + - ../trigger.yaml + - ../com_break.yaml + - ../ccr.yaml + - ../ccxnp.yaml + - ccm.yaml + +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] + TDE: + Disabled: [0, Trigger DMA request disabled] + Enabled: [1, Trigger DMA request enabled] + +RCR: + REP: [0, 0xFF] diff --git a/devices/fields/tim/v1/tim16.yaml b/devices/fields/tim/v1/tim16.yaml new file mode 100644 index 000000000..101fea8f5 --- /dev/null +++ b/devices/fields/tim/v1/tim16.yaml @@ -0,0 +1,16 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../tim16.yaml + - ../ccr1.yaml + - ../ccxnp.yaml + - ccm.yaml + +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] + +RCR: + REP: [0, 0xFF] diff --git a/devices/fields/tim/v1/tim2.yaml b/devices/fields/tim/v1/tim2.yaml new file mode 100644 index 000000000..5b45971be --- /dev/null +++ b/devices/fields/tim/v1/tim2.yaml @@ -0,0 +1,9 @@ +_include: + - ../basic.yaml + - ../tim_32bit.yaml + - ../tim_gp1.yaml + - ../generic.yaml + - ../tim_ckd.yaml + - ../ccr.yaml + - occe.yaml + - ccm.yaml diff --git a/devices/fields/tim/v1/tim3.yaml b/devices/fields/tim/v1/tim3.yaml new file mode 100644 index 000000000..e4b4a74ef --- /dev/null +++ b/devices/fields/tim/v1/tim3.yaml @@ -0,0 +1,9 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_gp1.yaml + - ../generic.yaml + - ../tim_ckd.yaml + - ../ccr.yaml + - occe.yaml + - ccm.yaml diff --git a/devices/fields/tim/v1/tim6.yaml b/devices/fields/tim/v1/tim6.yaml new file mode 100644 index 000000000..998919ee0 --- /dev/null +++ b/devices/fields/tim/v1/tim6.yaml @@ -0,0 +1,5 @@ +_include: + - ../basic.yaml + - ../tim6_base.yaml +ARR: + ARR: [0, 0xFFFF] diff --git a/devices/fields/tim/v1/tim9.yaml b/devices/fields/tim/v1/tim9.yaml new file mode 100644 index 000000000..80b7d32a1 --- /dev/null +++ b/devices/fields/tim/v1/tim9.yaml @@ -0,0 +1,26 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../trigger.yaml + - ../ccr.yaml + - ccm.yaml + +SMCR: + MSM: + NoSync: [0, No action] + Sync: + - 1 + - The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. + SMS: + Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + Reset_Mode: + - 4 + - Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. + Gated_Mode: + - 5 + - Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. + Trigger_Mode: + - 6 + - Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. + Ext_Clock_Mode: [7, External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.] diff --git a/devices/fields/tim/v2/ccm9_15.yaml b/devices/fields/tim/v2/ccm9_15.yaml new file mode 100644 index 000000000..916d3039c --- /dev/null +++ b/devices/fields/tim/v2/ccm9_15.yaml @@ -0,0 +1,37 @@ +CCMR?_Output: + OC?M: + Frozen: + [ + 0, + "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive", + ] + ActiveOnMatch: + [ + 1, + "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1", + ] + InactiveOnMatch: + [ + 2, + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved, + ] + Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"] + ForceInactive: + [ + 4, + "OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF", + ] + ForceActive: + [ + 5, + "OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF", + ] + PwmMode1: + [ + 6, + "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / Reserved", + ] + PwmMode2: [7, Inversely to PwmMode1 / Reserved] + OC?M_3: + Normal: [0, Normal output compare mode (modes 0-7)] + Extended: [1, Extended output compare mode (modes 7-15)] diff --git a/devices/fields/tim/v2/ccm_common.yaml b/devices/fields/tim/v2/ccm_common.yaml new file mode 100644 index 000000000..0a54a3967 --- /dev/null +++ b/devices/fields/tim/v2/ccm_common.yaml @@ -0,0 +1,26 @@ +CCMR?_Output: + OC?M: + Frozen: + [ + 0, + The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs, + ] + ActiveOnMatch: + [ + 1, + Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register, + ] + InactiveOnMatch: + [ + 2, + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register, + ] + Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + ForceInactive: [4, OCyREF is forced low] + ForceActive: [5, OCyREF is forced high] + PwmMode1: + [ + 6, + "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active", + ] + PwmMode2: [7, Inversely to PwmMode1] diff --git a/devices/fields/tim/v2/ccm_extended.yaml b/devices/fields/tim/v2/ccm_extended.yaml new file mode 100644 index 000000000..0e7813650 --- /dev/null +++ b/devices/fields/tim/v2/ccm_extended.yaml @@ -0,0 +1,37 @@ +CCMR?_Output: + OC?M: + Frozen: + [ + 0, + "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive", + ] + ActiveOnMatch: + [ + 1, + "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1", + ] + InactiveOnMatch: + [ + 2, + Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved, + ] + Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"] + ForceInactive: + [ + 4, + "OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF", + ] + ForceActive: + [ + 5, + "OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF", + ] + PwmMode1: + [ + 6, + "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down", + ] + PwmMode2: [7, "Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1"] + OC?M_3: + Normal: [0, Normal output compare mode (modes 0-7)] + Extended: [1, Extended output compare mode (modes 7-15)] diff --git a/devices/fields/tim/v2/tim1.yaml b/devices/fields/tim/v2/tim1.yaml new file mode 100644 index 000000000..932b27f4e --- /dev/null +++ b/devices/fields/tim/v2/tim1.yaml @@ -0,0 +1,15 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../com_break.yaml + - ../tim_gp1.yaml + - ../generic.yaml + - ../tim_ckd.yaml + - ../tim_advanced.yaml + - ../ccr.yaml + - ../ccxnp.yaml + - ../v1/occe.yaml + - ccm_extended.yaml + +RCR: + REP: [0, 0xFFFF] diff --git a/devices/fields/tim/v2/tim10.yaml b/devices/fields/tim/v2/tim10.yaml new file mode 100644 index 000000000..d36a4b439 --- /dev/null +++ b/devices/fields/tim/v2/tim10.yaml @@ -0,0 +1,6 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../ccr1.yaml + - ccm_common.yaml diff --git a/devices/fields/tim/v2/tim13.yaml b/devices/fields/tim/v2/tim13.yaml new file mode 100644 index 000000000..d36a4b439 --- /dev/null +++ b/devices/fields/tim/v2/tim13.yaml @@ -0,0 +1,6 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../ccr1.yaml + - ccm_common.yaml diff --git a/devices/fields/tim/v2/tim15.yaml b/devices/fields/tim/v2/tim15.yaml new file mode 100644 index 000000000..ab1395571 --- /dev/null +++ b/devices/fields/tim/v2/tim15.yaml @@ -0,0 +1,26 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../ccds.yaml + - ../ccpc.yaml + - ../trigger.yaml + - ../com_break.yaml + - ../bdtr_common.yaml + - ../ccr.yaml + - ../ccxnp.yaml + - ccm9_15.yaml + +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] + COMDE: + Disabled: [0, COM DMA request disabled] + Enabled: [1, COM DMA request enabled] + TDE: + Disabled: [0, Trigger DMA request disabled] + Enabled: [1, Trigger DMA request enabled] + +RCR: + REP: [0, 0xFF] diff --git a/devices/fields/tim/v2/tim16.yaml b/devices/fields/tim/v2/tim16.yaml new file mode 100644 index 000000000..ad817c901 --- /dev/null +++ b/devices/fields/tim/v2/tim16.yaml @@ -0,0 +1,17 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../tim16.yaml + - ../bdtr_common.yaml + - ../ccr1.yaml + - ../ccxnp.yaml + - ccm_common.yaml + +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] + +RCR: + REP: [0, 0xFF] diff --git a/devices/fields/tim/v2/tim2.yaml b/devices/fields/tim/v2/tim2.yaml new file mode 100644 index 000000000..2b40f3d41 --- /dev/null +++ b/devices/fields/tim/v2/tim2.yaml @@ -0,0 +1,9 @@ +_include: + - ../basic.yaml + - ../tim_32bit.yaml + - ../tim_gp1.yaml + - ../generic.yaml + - ../tim_ckd.yaml + - ../ccr.yaml + - ../v1/occe.yaml + - ccm_extended.yaml diff --git a/devices/fields/tim/v2/tim3.yaml b/devices/fields/tim/v2/tim3.yaml new file mode 100644 index 000000000..bce0e553f --- /dev/null +++ b/devices/fields/tim/v2/tim3.yaml @@ -0,0 +1,9 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_gp1.yaml + - ../generic.yaml + - ../tim_ckd.yaml + - ../ccr.yaml + - ../v1/occe.yaml + - ccm_extended.yaml diff --git a/devices/fields/tim/v2/tim6.yaml b/devices/fields/tim/v2/tim6.yaml new file mode 100644 index 000000000..998919ee0 --- /dev/null +++ b/devices/fields/tim/v2/tim6.yaml @@ -0,0 +1,5 @@ +_include: + - ../basic.yaml + - ../tim6_base.yaml +ARR: + ARR: [0, 0xFFFF] diff --git a/devices/fields/tim/v2/tim9.yaml b/devices/fields/tim/v2/tim9.yaml new file mode 100644 index 000000000..8d33dc867 --- /dev/null +++ b/devices/fields/tim/v2/tim9.yaml @@ -0,0 +1,7 @@ +_include: + - ../basic.yaml + - ../tim_16bit.yaml + - ../tim_ckd.yaml + - ../trigger.yaml + - ../ccr.yaml + - ccm9_15.yaml diff --git a/devices/fields/tim/v3/occe.yaml b/devices/fields/tim/v3/occe.yaml new file mode 100644 index 000000000..0a3fa040d --- /dev/null +++ b/devices/fields/tim/v3/occe.yaml @@ -0,0 +1,4 @@ +CCMR?_Output: + OC?CE: + Disabled: [0, OCxRef is not affected by the ocref_clr_int signal] + Enabled: [1, OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal] diff --git a/devices/fields/tim/v3/tim1.yaml b/devices/fields/tim/v3/tim1.yaml new file mode 100644 index 000000000..22a359752 --- /dev/null +++ b/devices/fields/tim/v3/tim1.yaml @@ -0,0 +1,17 @@ +_include: + - ../tim_gp1.yaml + - ../generic.yaml + - ../com_break.yaml + - ../basic.yaml + - ../tim_uifremap.yaml + - ../dithen.yaml + - ../tim_ckd.yaml + - ../tim_advanced.yaml + - ../tim_16bit_dither.yaml + - ../ccr.yaml + - ../ccxnp.yaml + - occe.yaml + - ../v2/ccm_extended.yaml + +RCR: + REP: [0, 0xFFFF] diff --git a/devices/fields/tim/v3/tim13.yaml b/devices/fields/tim/v3/tim13.yaml new file mode 100644 index 000000000..965f58068 --- /dev/null +++ b/devices/fields/tim/v3/tim13.yaml @@ -0,0 +1,8 @@ +_include: + - ../basic.yaml + - ../tim_16bit_dither.yaml + - ../tim_uifremap.yaml + - ../dithen.yaml + - ../tim_ckd.yaml + - ../ccr1.yaml + - ../v2/ccm_common.yaml diff --git a/devices/fields/tim/v3/tim15.yaml b/devices/fields/tim/v3/tim15.yaml new file mode 100644 index 000000000..234dc47ff --- /dev/null +++ b/devices/fields/tim/v3/tim15.yaml @@ -0,0 +1,29 @@ +_include: + - ../basic.yaml + - ../tim_16bit_dither.yaml + - ../tim_uifremap.yaml + - ../dithen.yaml + - ../tim_ckd.yaml + - ../ccds.yaml + - ../ccpc.yaml + - ../trigger.yaml + - ../com_break.yaml + - ../bdtr_common.yaml + - ../ccr.yaml + - ../ccxnp.yaml + - occe.yaml + - ../v2/ccm9_15.yaml + +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] + COMDE: + Disabled: [0, COM DMA request disabled] + Enabled: [1, COM DMA request enabled] + TDE: + Disabled: [0, Trigger DMA request disabled] + Enabled: [1, Trigger DMA request enabled] + +RCR: + REP: [0, 0xFF] diff --git a/devices/fields/tim/v3/tim16.yaml b/devices/fields/tim/v3/tim16.yaml new file mode 100644 index 000000000..0ee62f184 --- /dev/null +++ b/devices/fields/tim/v3/tim16.yaml @@ -0,0 +1,19 @@ +_include: + - ../basic.yaml + - ../tim_16bit_dither.yaml + - ../tim_uifremap.yaml + - ../dithen.yaml + - ../tim_ckd.yaml + - ../bdtr_common.yaml + - ../tim16.yaml + - ../ccr1.yaml + - ../ccxnp.yaml + - ../v2/ccm_common.yaml + +DIER: + UDE: + Disabled: [0, Update DMA request disabled] + Enabled: [1, Update DMA request enabled] + +RCR: + REP: [0, 0xFF] diff --git a/devices/fields/tim/v3/tim2.yaml b/devices/fields/tim/v3/tim2.yaml new file mode 100644 index 000000000..df170c00c --- /dev/null +++ b/devices/fields/tim/v3/tim2.yaml @@ -0,0 +1,11 @@ +_include: + - ../tim_32bit.yaml + - ../tim_gp1.yaml + - ../generic.yaml + - ../basic.yaml + - ../tim_uifremap.yaml + - ../dithen.yaml + - ../tim_ckd.yaml + - ../ccr.yaml + - occe.yaml + - ../v2/ccm_extended.yaml diff --git a/devices/fields/tim/v3/tim3.yaml b/devices/fields/tim/v3/tim3.yaml new file mode 100644 index 000000000..eaeb8d127 --- /dev/null +++ b/devices/fields/tim/v3/tim3.yaml @@ -0,0 +1,11 @@ +_include: + - ../basic.yaml + - ../tim_16bit_dither.yaml + - ../tim_uifremap.yaml + - ../dithen.yaml + - ../tim_gp1.yaml + - ../generic.yaml + - ../tim_ckd.yaml + - ../ccr.yaml + - occe.yaml + - ../v2/ccm_extended.yaml diff --git a/devices/fields/tim/v3/tim6.yaml b/devices/fields/tim/v3/tim6.yaml new file mode 100644 index 000000000..72b29d684 --- /dev/null +++ b/devices/fields/tim/v3/tim6.yaml @@ -0,0 +1,9 @@ +# TIM6 and TIM7 with dithering support + +_include: + - ../basic.yaml + - ../tim_uifremap.yaml + - ../dithen.yaml + - ../tim6_base.yaml +ARR: + ARR: [0, 0xFFFFF] diff --git a/devices/fields/tim/v3/tim9.yaml b/devices/fields/tim/v3/tim9.yaml new file mode 100644 index 000000000..5fe959ddc --- /dev/null +++ b/devices/fields/tim/v3/tim9.yaml @@ -0,0 +1,9 @@ +_include: + - ../basic.yaml + - ../tim_16bit_dither.yaml + - ../tim_uifremap.yaml + - ../dithen.yaml + - ../tim_ckd.yaml + - ../trigger.yaml + - ../ccr.yaml + - ../v2/ccm9_15.yaml diff --git a/devices/fields/tsc/tsc.yaml b/devices/fields/tsc/tsc.yaml new file mode 100644 index 000000000..bf7e4f60f --- /dev/null +++ b/devices/fields/tsc/tsc.yaml @@ -0,0 +1,59 @@ +CR: + SSE: + Disabled: [0, Spread spectrum disabled] + Enabled: [1, Spread spectrum enabled] + IODEF: + PushPull: [0, I/Os are forced to output push-pull low] + Floating: [1, I/Os are in input floating] + SYNCPOL: + FallingEdge: [0, Falling edge only] + RisingEdge: [1, Rising edge and high level] + AM: + Normal: [0, Normal acquisition mode (acquisition starts as soon as START bit is set)] + Synchronized: + [ + 1, + Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin), + ] + START: + NoStarted: [0, Acquisition not started] + Started: [1, Start a new acquisition] + TSCE: + Disabled: [0, Touch sensing controller disabled] + Enabled: [1, Touch sensing controller enabled] + +IER: + MCEIE: + Disabled: [0, Max count error interrupt disabled] + Enabled: [1, Max count error interrupt enabled] + EOAIE: + Disabled: [0, End of acquisition interrupt disabled] + Enabled: [1, End of acquisition interrupt enabled] + +IOHCR: + G?_IO?: + Disabled: [0, Gx_IOy Schmitt trigger hysteresis disabled] + Enabled: [1, Gx_IOy Schmitt trigger hysteresis enabled] + +IOASCR: + G?_IO?: + Disabled: [0, Gx_IOy analog switch disabled (opened)] + Enabled: [1, Gx_IOy analog switch enabled (closed)] + +IOSCR: + G?_IO?: + Disabled: [0, Gx_IOy unused] + Enabled: [1, Gx_IOy used as sampling capacitor] + +IOCCR: + G?_IO?: + Disabled: [0, Gx_IOy unused] + Enabled: [1, Gx_IOy used as channel] + +IOGCSR: + G?S: + Ongoing: [0, Acquisition on analog I/O group x is ongoing or not started] + Complete: [1, Acquisition on analog I/O group x is complete] + G?E: + Disabled: [0, Acquisition on analog I/O group x disabled] + Enabled: [1, Acquisition on analog I/O group x enabled] diff --git a/devices/fields/ucpd/ucpd_v1.yaml b/devices/fields/ucpd/ucpd_v1.yaml new file mode 100644 index 000000000..f07b71aa2 --- /dev/null +++ b/devices/fields/ucpd/ucpd_v1.yaml @@ -0,0 +1,176 @@ +# UCPD peripheral + +CFGR1: + UCPDEN: + Disabled: [0, UCPD peripheral disabled] + Enabled: [1, UCPD peripheral enabled] + RXDMAEN: + Disabled: [0, DMA mode for reception disabled] + Enabled: [1, DMA mode for reception enabled] + TXDMAEN: + Disabled: [0, DMA mode for transmission disabled] + Enabled: [1, DMA mode for transmission enabled] + RXORDSETEN?: + Disabled: [0, Flag disabled] + Enabled: [1, Flag enabled] + PSC_USBPDCLK: + Div1: [0, Divide by 1] + Div2: [1, Divide by 2] + Div4: [2, Divide by 4] + Div8: [3, Divide by 8] + Div16: [4, Divide by 16] + TRANSWIN: [1, 0x1F] + IFRGAP: [1, 0x1F] + HBITCLKDIV: [0, 0x3F] +CFGR2: + "*EN": + Disabled: [0, Disabled] + Enabled: [1, Enabled] + FORCECLK: + NoForce: [0, Do not force clock request] + Force: [1, Force clock request] + RXFILT2N3: + Samp3: [0, 3 samples] + Samp2: [1, 2 samples] + RXFILTDIS: + Enabled: [0, Rx pre-filter enabled] + Disabled: [1, Rx pre-filter disabled] +?~CFGR3: + # Note: on some device datasheets, this is called TRIMx_CC_xxx but "incorrectly" named in the svd. + # For consistency across devices, we'll stick with the NG_CCx naming. + TRIM[12]_NG_CC*: [0, 0xF] +CR: + CC?TCDIS: + Enabled: [0, Type-C detector on the CCx line enabled] + Disabled: [1, Type-C detector on the CCx line disabled] + RDCH: + NoEffect: [0, No effect] + ConditionDrive: [1, Rdch condition drive] + FRSTX: + NoEffect: [0, No effect] + Enabled: [1, FRS Tx signaling enabled] + FRSRXEN: + Disabled: [0, FRS Rx event detection disabled] + Enabled: [1, FRS Rx event detection enabled] + CCENABLE: + Disabled: [0, Both PHYs disabled] + CC1Enabled: [1, CC1 PHY enabled] + CC2Enabled: [2, CC2 PHY enabled] + BothEnabled: [3, CC1 and CC2 PHYs enabled] + ANAMODE: + Source: [0, Source] + Sink: [1, Sink] + ANASUBMODE: + Disabled: [0, Disabled] + Rp_DefaultUSB: [1, Default USB Rp] + Rp_1_5A: [2, 1.5A Rp] + Rp_3A: [3, 3A Rp] + PHYCCSEL: + CC1: [0, Use CC1 IO for Power Delivery communication] + CC2: [1, Use CC2 IO for Power Delivery communication] + PHYRXEN: + Disabled: [0, USB Power Delivery receiver disabled] + Enabled: [1, USB Power Delivery receiver enabled] + RXMODE: + Normal: [0, Normal receive mode] + BIST: [1, BIST receive mode (BIST test data mode)] + TXHRST: + NoEffect: [0, No effect] + Start: [1, Start Tx Hard Reset message] + TXSEND: + NoEffect: [0, No effect] + Start: [1, Start Tx packet transmission] + TXMODE: + RegisterSet: [0, Transmission of Tx packet previously defined in other registers] + CableReset: [1, Cable Reset sequence] + BISTTest: [2, BIST test sequence (BIST Carrier Mode 2)] +IMR: + "*IE": + Disabled: [0, Interrupt disabled] + Enabled: [1, Interrupt enabled] +SR: + FRSEVT: + NoNewEvent: [0, No new event] + NewEvent: [1, New FRS receive event occurred] + TYPEC_VSTATE_CC?: + Lowest: [0, Lowest] + Low: [1, Low] + High: [2, High] + Highest: [3, Highest] + TYPECEVT?: + NoNewEvent: [0, No new event] + NewEvent: [1, A new Type-C event occurred] + RXERR: + NoError: [0, No error detected] + Error: [1, Error(s) detected] + RXMSGEND: + NoNewMessage: [0, No new Rx message received] + NewMessage: [1, A new Rx message received] + RXOVR: + NoOverflow: [0, No overflow] + Overflow: [1, Overflow] + RXHRSTDET: + NoHardReset: [0, Hard Reset not received] + HardReset: [1, Hard Reset received] + RXORDDET: + NoOrderedSet: [0, No ordered set detected] + OrderedSet: [1, Ordered set detected] + RXNE: + Empty: [0, Rx data register empty] + NotEmpty: [1, Rx data register not empty] + TXUND: + NoUnderrun: [0, No Tx data underrun detected] + Underrun: [1, Tx data underrun detected] + HRSTSENT: + NotSent: [0, No Hard Reset message sent] + Sent: [1, Hard Reset message sent] + HRSTDISC: + NotDiscarded: [0, No Hard Reset discarded] + Discarded: [1, Hard Reset discarded] + TXMSGABT: + NoAbort: [0, No transmit message abort] + Abort: [1, Transmit message abort] + TXMSGSENT: + NotCompleted: [0, No Tx message completed] + Completed: [1, Tx message completed] + TXMSGDISC: + NotDiscarded: [0, No Tx message discarded] + Discarded: [1, Tx message discarded] + TXIS: + NotRequired: [0, New Tx data write not required] + Required: [1, New Tx data write required] +ICR: + "*CF": + _write: + Clear: [1, Clear flag in UCPD_SR] +TX_ORDSETR: + TXORDSET: [0, 0xFFFFF] +TX_PAYSZR: + TXPAYSZ: [0, 0x3FF] +TXDR: + TXDATA: [0, 0xFF] +RX_ORDSETR: + RXSOPKINVALID: + Valid: [0, No K-code corrupted] + FirstCorrupted: [1, First K-code corrupted] + SecondCorrupted: [2, Second K-code corrupted] + ThirdCorrupted: [3, Third K-code corrupted] + FourthCorrupted: [4, Fourth K-code corrupted] + RXSOP3OF4: + AllCorrect: [0, 4 correct K-codes out of 4] + OneIncorrect: [1, 3 correct K-codes out of 4] + RXORDSET: + SOP: [0, SOP code detected in receiver] + SOPPrime: [1, "SOP' code detected in receiver"] + SOPDoublePrime: [2, "SOP'' code detected in receiver"] + SOPPrimeDebug: [3, "SOP'_Debug detected in receiver"] + SOPDoublePrimeDebug: [4, "SOP''_Debug detected in receiver"] + CableReset: [5, Cable Reset detected in receiver] + SOPExtension1: [6, "SOP extension #1 detected in receiver"] + SOPExtension2: [7, "SOP extension #2 detected in receiver"] +RX_PAYSZR: + RXPAYSZ: [0, 0x3FF] +RXDR: + RXDATA: [0, 0xFF] +RX_ORDEXTR?: + RXSOPX?: [0, 0xFFFFF] diff --git a/devices/fields/ucpd/ucpd_v2.yaml b/devices/fields/ucpd/ucpd_v2.yaml new file mode 100644 index 000000000..45754ff16 --- /dev/null +++ b/devices/fields/ucpd/ucpd_v2.yaml @@ -0,0 +1,16 @@ +# Slightly different version found in G0x1 families + +_include: + - ucpd_v1.yaml + +CR: + DBATTEN: + Disabled: [0, Dead battery function disabled] + Enabled: [1, Dead battery function enabled] + # Not in G071 and G081, unsure why + ?~CC2VCONNEN: + Disabled: [0, VCONN switch for CC2 disabled] + Enabled: [1, VCONN switch for CC2 enabled] + ?~CC1VCONNEN: + Disabled: [0, VCONN switch for CC1 disabled] + Enabled: [1, VCONN switch for CC1 enabled] diff --git a/devices/fields/usart/v1/common.yaml b/devices/fields/usart/v1/common.yaml new file mode 100644 index 000000000..f8ef9f989 --- /dev/null +++ b/devices/fields/usart/v1/common.yaml @@ -0,0 +1,120 @@ +DR: + DR: [0, 0x1FF] + +BRR: + DIV_Mantissa: [0, 0xFFF] + DIV_Fraction: [0, 0xF] + +CR1: + UE: + Disabled: [0, USART prescaler and outputs disabled] + Enabled: [1, USART enabled] + M: + M8: [0, 8 data bits] + M9: [1, 9 data bits] + WAKE: + IdleLine: [0, USART wakeup on idle line] + AddressMark: [1, USART wakeup on address mark] + PCE: + Disabled: [0, Parity control disabled] + Enabled: [1, Parity control enabled] + PS: + Even: [0, Even parity] + Odd: [1, Odd parity] + PEIE: + Disabled: [0, PE interrupt disabled] + Enabled: [1, PE interrupt enabled] + TXEIE: + Disabled: [0, TXE interrupt disabled] + Enabled: [1, TXE interrupt enabled] + TCIE: + Disabled: [0, TC interrupt disabled] + Enabled: [1, TC interrupt enabled] + RXNEIE: + Disabled: [0, RXNE interrupt disabled] + Enabled: [1, RXNE interrupt enabled] + IDLEIE: + Disabled: [0, IDLE interrupt disabled] + Enabled: [1, IDLE interrupt enabled] + TE: + Disabled: [0, Transmitter disabled] + Enabled: [1, Transmitter enabled] + RE: + Disabled: [0, Receiver disabled] + Enabled: [1, Receiver enabled] + RWU: + Active: [0, Receiver in active mode] + Mute: [1, Receiver in mute mode] + SBK: + NoBreak: [0, No break character is transmitted] + Break: [1, Break character transmitted] + +CR2: + LINEN: + Disabled: [0, LIN mode disabled] + Enabled: [1, LIN mode enabled] + LBDIE: + Disabled: [0, LIN break detection interrupt disabled] + Enabled: [1, LIN break detection interrupt enabled] + LBDL: + LBDL10: [0, 10-bit break detection] + LBDL11: [1, 11-bit break detection] + ADD: [0, 0xF] + +CR3: + DMAT: + Disabled: [0, DMA mode is disabled for transmission] + Enabled: [1, DMA mode is enabled for transmission] + DMAR: + Disabled: [0, DMA mode is disabled for reception] + Enabled: [1, DMA mode is enabled for reception] + HDSEL: + FullDuplex: [0, Half duplex mode is not selected] + HalfDuplex: [1, Half duplex mode is selected] + IRLP: + Normal: [0, Normal mode] + LowPower: [1, Low-power mode] + IREN: + Disabled: [0, IrDA disabled] + Enabled: [1, IrDA enabled] + EIE: + Disabled: [0, Error interrupt disabled] + Enabled: [1, Error interrupt enabled] + +SR: + PE: + NoError: [0, No parity error] + Error: [1, Parity error] + FE: + NoError: [0, No Framing error is detected] + Error: [1, Framing error or break character is detected] + "NE,NF": + NoNoise: [0, No noise is detected] + Noise: [1, Noise is detected] + ORE: + NoOverrun: [0, No Overrun error] + Overrun: [1, Overrun error is detected] + IDLE: + NoIdle: [0, No Idle Line is detected] + Idle: [1, Idle Line is detected] + RXNE: + _read: + NoData: [0, Data is not received] + DataReady: [1, Received data is ready to be read] + _W0C: + Clear: [0, Clear received data ready flag] + TC: + _read: + TxNotComplete: [0, Transmission is not complete] + TxComplete: [1, Transmission is complete] + _W0C: + Clear: [0, Clear transmission complete flag] + TXE: + TxNotEmpty: [0, Data is not transferred to the shift register] + TxEmpty: [1, Data is transferred to the shift register] + LBD: + _read: + NotDetected: [0, LIN break not detected] + Detected: [1, LIN break detected] + _W0C: + Clear: [0, Clear LIN break detection flag] diff --git a/devices/fields/usart/v1/uart.yaml b/devices/fields/usart/v1/uart.yaml new file mode 100644 index 000000000..1fa47a57d --- /dev/null +++ b/devices/fields/usart/v1/uart.yaml @@ -0,0 +1,6 @@ +_include: common.yaml + +CR2: + STOP: + Stop1: [0, 1 stop bit] + Stop2: [2, 2 stop bits] diff --git a/devices/fields/usart/v1/usart.yaml b/devices/fields/usart/v1/usart.yaml new file mode 100644 index 000000000..144777e79 --- /dev/null +++ b/devices/fields/usart/v1/usart.yaml @@ -0,0 +1,49 @@ +_include: common.yaml + +CR2: + LBCL: + Disabled: [0, The clock pulse of the last data bit is not output to the CK pin] + Enabled: [1, The clock pulse of the last data bit is output to the CK pin] + STOP: + Stop1: [0, 1 stop bit] + Stop0p5: [1, 0.5 stop bits] + Stop2: [2, 2 stop bits] + Stop1p5: [3, 1.5 stop bits] + CLKEN: + Disabled: [0, CK pin disabled] + Enabled: [1, CK pin enabled] + CPOL: + Low: [0, Steady low value on CK pin outside transmission window] + High: [1, Steady high value on CK pin outside transmission window] + CPHA: + First: [0, The first clock transition is the first data capture edge] + Second: [1, The second clock transition is the first data capture edge] + +CR3: + CTSIE: + Disabled: [0, CTS interrupt disabled] + Enabled: [1, CTS interrupt enabled] + CTSE: + Disabled: [0, CTS hardware flow control disabled] + Enabled: [1, CTS hardware flow control enabled] + RTSE: + Disabled: [0, RTS hardware flow control disabled] + Enabled: [1, RTS hardware flow control enabled] + SCEN: + Disabled: [0, Smartcard mode disabled] + Enabled: [1, Smartcard mode enabled] + NACK: + Disabled: [0, NACK transmission in case of parity error is disabled] + Enabled: [1, NACK transmission during parity error is enabled] + +SR: + CTS: + _read: + NotChanged: [0, No change occurred on the CTS status line] + Changed: [1, A change occurred on the CTS status line] + _W0C: + Clear: [0, Clear CTS toggle detection flag] + +GTPR: + PSC: [1, 0xFF] + GT: [0, 0xFF] diff --git a/devices/fields/usart/v2/sample.yaml b/devices/fields/usart/v2/sample.yaml new file mode 100644 index 000000000..88f6f7a8c --- /dev/null +++ b/devices/fields/usart/v2/sample.yaml @@ -0,0 +1,8 @@ +CR1: + OVER8: + Oversample16: [0, Oversampling by 16] + Oversample8: [1, Oversampling by 8] +CR3: + ONEBIT: + Sample3: [0, Three sample bit method] + Sample1: [1, One sample bit method] diff --git a/devices/fields/usart/v2/uart.yaml b/devices/fields/usart/v2/uart.yaml new file mode 100644 index 000000000..8038106b9 --- /dev/null +++ b/devices/fields/usart/v2/uart.yaml @@ -0,0 +1,6 @@ +_include: + - ../v1/uart.yaml + - sample.yaml + +"?~GTPR": + PSC: [1, 0xFF] diff --git a/devices/fields/usart/v2/usart.yaml b/devices/fields/usart/v2/usart.yaml new file mode 100644 index 000000000..674924975 --- /dev/null +++ b/devices/fields/usart/v2/usart.yaml @@ -0,0 +1,3 @@ +_include: + - ../v1/usart.yaml + - sample.yaml diff --git a/devices/fields/usart/v3/ABC_common.yaml b/devices/fields/usart/v3/ABC_common.yaml new file mode 100644 index 000000000..f4c3d29fe --- /dev/null +++ b/devices/fields/usart/v3/ABC_common.yaml @@ -0,0 +1,186 @@ +# Common fields between v2 A, B and C peripherals + +CR1: + DEAT: [0, 0b11111] + DEDT: [0, 0b11111] + CMIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is generated when the CMF bit is set in the ISR register] + MME: + Disabled: [0, Receiver in active mode permanently] + Enabled: [1, Receiver can switch between mute mode and active mode] + WAKE: + Idle: [0, Idle line] + Address: [1, Address mask] + PCE: + Disabled: [0, Parity control disabled] + Enabled: [1, Parity control enabled] + PS: + Even: [0, Even parity] + Odd: [1, Odd parity] + PEIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever PE=1 in the ISR register"] + TXEIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever TXE=1 in the ISR register"] + TCIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever TC=1 in the ISR register"] + RXNEIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register"] + IDLEIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever IDLE=1 in the ISR register"] + TE: + Disabled: [0, Transmitter is disabled] + Enabled: [1, Transmitter is enabled] + RE: + Disabled: [0, Receiver is disabled] + Enabled: [1, Receiver is enabled] + UE: + Disabled: [0, UART is disabled] + Enabled: [1, UART is enabled] +CR2: + ADD: [0, 0xFF] + MSBFIRST: + LSB: [0, "data is transmitted/received with data bit 0 first, following the start bit"] + MSB: [1, "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"] + TXINV: + Standard: [0, TX pin signal works using the standard logic levels] + Inverted: [1, TX pin signal values are inverted] + RXINV: + Standard: [0, RX pin signal works using the standard logic levels] + Inverted: [1, RX pin signal values are inverted] + DATAINV: + Positive: [0, Logical data from the data register are send/received in positive/direct logic] + Negative: [1, Logical data from the data register are send/received in negative/inverse logic] + SWAP: + Standard: [0, TX/RX pins are used as defined in standard pinout] + Swapped: [1, The TX and RX pins functions are swapped] + STOP: + Stop1: [0, 1 stop bit] + Stop0p5: [1, 0.5 stop bit] + Stop2: [2, 2 stop bit] + Stop1p5: [3, 1.5 stop bit] + "?~CLKEN": + Disabled: [0, CK pin disabled] + Enabled: [1, CK pin enabled] + ADDM7: + Bit4: [0, 4-bit address detection] + Bit7: [1, 7-bit address detection] +CR3: + DEP: + High: [0, DE signal is active high] + Low: [1, DE signal is active low] + DEM: + Disabled: [0, DE function is disabled] + Enabled: [1, The DE signal is output on the RTS pin] + DDRE: + NotDisabled: [0, DMA is not disabled in case of reception error] + Disabled: [1, DMA is disabled following a reception error] + OVRDIS: + Enabled: [0, "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"] + Disabled: + [ + 1, + Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register, + ] + CTSIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, "An interrupt is generated whenever CTSIF=1 in the ISR register"] + CTSE: + Disabled: [0, CTS hardware flow control disabled] + Enabled: [1, "CTS mode enabled, data is only transmitted when the CTS input is asserted"] + RTSE: + Disabled: [0, RTS hardware flow control disabled] + Enabled: [1, "RTS output enabled, data is only requested when there is space in the receive buffer"] + DMAT: + Disabled: [0, DMA mode is disabled for transmission] + Enabled: [1, DMA mode is enabled for transmission] + DMAR: + Disabled: [0, DMA mode is disabled for reception] + Enabled: [1, DMA mode is enabled for reception] + HDSEL: + NotSelected: [0, Half duplex mode is not selected] + Selected: [1, Half duplex mode is selected] + EIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"] +RQR: + RXFRQ: + Discard: + [ + 1, + "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition", + ] + MMRQ: + Mute: [1, Puts the USART in mute mode and sets the RWU flag] + SBKRQ: + Break: + [1, "sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"] +ISR: + PE: + NoError: [0, No parity error] + Error: [1, Parity error] + FE: + NoError: [0, No Framing error is detected] + Error: [1, Framing error or break character is detected] + "NE,NF": + NoNoise: [0, No noise is detected] + Noise: [1, Noise is detected] + ORE: + NoOverrun: [0, No Overrun error] + Overrun: [1, Overrun error is detected] + IDLE: + NoIdle: [0, No Idle Line is detected] + Idle: [1, Idle Line is detected] + "RXNE,RXFNE": + NoData: [0, Data is not received] + DataReady: [1, Received data is ready to be read] + TC: + TxNotComplete: [0, Transmission is not complete] + TxComplete: [1, Transmission is complete] + "TXE,TXFNF": + Full: [0, Transmit FIFO is full] + NotFull: [1, Transmit FIFO is not full] + CTSIF: + NotChanged: [0, No change occurred on the CTS status line] + Changed: [1, A change occurred on the CTS status line] + CTS: + Set: [0, CTS line set] + Reset: [1, CTS line reset] + BUSY: + Idle: [0, USART is idle (no reception)] + Busy: [1, Reception on going] + CMF: + NoMatch: [0, No Character match detected] + Match: [1, Character match detected] + SBKF: + NoBreak: [0, No break character transmitted] + Break: [1, Break character transmitted] + TEACK: +ICR: + "*": + _W1C: {} + CMCF: + Clear: [1, Clears the CMF flag in the ISR register] + CTSCF: + Clear: [1, Clears the CTSIF flag in the ISR register] + TCCF: + Clear: [1, Clears the TC flag in the ISR register] + IDLECF: + Clear: [1, Clears the IDLE flag in the ISR register] + ORECF: + Clear: [1, Clears the ORE flag in the ISR register] + "NCF,NCEF,NECF": + Clear: [1, Clears the NF flag in the ISR register] + FECF: + Clear: [1, Clears the FE flag in the ISR register] + PECF: + Clear: [1, Clears the PE flag in the ISR register] +RDR: + RDR: [0, 0x1FF] +TDR: + TDR: [0, 0x1FF] diff --git a/devices/fields/usart/v3/AB_common.yaml b/devices/fields/usart/v3/AB_common.yaml new file mode 100644 index 000000000..d9301b29b --- /dev/null +++ b/devices/fields/usart/v3/AB_common.yaml @@ -0,0 +1,23 @@ +# Common fields between v2 A and B peripherals + +CR1: + UESM: + Disabled: [0, USART not able to wake up the MCU from Stop mode] + Enabled: [1, USART able to wake up the MCU from Stop mode] +CR3: + WUFIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, "An USART interrupt is generated whenever WUF=1 in the ISR register"] + WUS: + Address: [0, WUF active on address match] + Start: [2, WuF active on Start bit detection] + RXNE: [3, WUF active on RXNE] +ISR: + RWU: + Active: [0, Receiver in Active mode] + Mute: [1, Receiver in Mute mode] + "REAK,REACK": + WUF: +ICR: + WUCF: + Clear: [1, Clears the WUF flag in the ISR register] diff --git a/devices/fields/usart/v3/B.yaml b/devices/fields/usart/v3/B.yaml new file mode 100644 index 000000000..524a52d54 --- /dev/null +++ b/devices/fields/usart/v3/B.yaml @@ -0,0 +1,7 @@ +# USART v2B found on F3, F0, F7, L0 and L4 family + +_include: + - ABC_common.yaml + - AB_common.yaml + - BC_common.yaml + - m.yaml diff --git a/devices/fields/usart/v3/BC_common.yaml b/devices/fields/usart/v3/BC_common.yaml new file mode 100644 index 000000000..0fd967925 --- /dev/null +++ b/devices/fields/usart/v3/BC_common.yaml @@ -0,0 +1,95 @@ +# Common fields between v2 B and C peripherals + +CR1: + OVER8: + Oversampling16: [0, Oversampling by 16] + Oversampling8: [1, Oversampling by 8] + EOBIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, A USART interrupt is generated when the EOBF flag is set in the ISR register] + RTOIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, An USART interrupt is generated when the RTOF bit is set in the ISR register] +CR2: + RTOEN: + Disabled: [0, Receiver timeout feature disabled] + Enabled: [1, Receiver timeout feature enabled] + ABRMOD: + Start: [0, Measurement of the start bit is used to detect the baud rate] + Edge: [1, Falling edge to falling edge measurement] + Frame7F: [2, 0x7F frame detection] + Frame55: [3, 0x55 frame detection] + ABREN: + Disabled: [0, Auto baud rate detection is disabled] + Enabled: [1, Auto baud rate detection is enabled] + LINEN: + Disabled: [0, LIN mode disabled] + Enabled: [1, LIN mode enabled] + CPOL: + Low: [0, Steady low value on CK pin outside transmission window] + High: [1, Steady high value on CK pin outside transmission window] + CPHA: + First: [0, The first clock transition is the first data capture edge] + Second: [1, The second clock transition is the first data capture edge] + LBCL: + NotOutput: [0, The clock pulse of the last data bit is not output to the CK pin] + Output: [1, The clock pulse of the last data bit is output to the CK pin] + LBDIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, "An interrupt is generated whenever LBDF=1 in the ISR register"] + LBDL: + Bit10: [0, 10-bit break detection] + Bit11: [1, 11-bit break detection] +CR3: + SCARCNT: [0, 7] + ONEBIT: + Sample3: [0, Three sample bit method] + Sample1: [1, One sample bit method] + SCEN: + Disabled: [0, Smartcard Mode disabled] + Enabled: [1, Smartcard Mode enabled] + NACK: + Disabled: [0, NACK transmission in case of parity error is disabled] + Enabled: [1, NACK transmission during parity error is enabled] + IRLP: + Normal: [0, Normal mode] + LowPower: [1, Low-power mode] + IREN: + Disabled: [0, IrDA disabled] + Enabled: [1, IrDA enabled] +BRR: + BRR: [0, 0xFFFF] +GTPR: + GT: [0, 0xFF] + PSC: [0, 0xFF] +RTOR: + BLEN: [0, 0xFF] + RTO: [0, 0xFFFFFF] +RQR: + TXFRQ: + Discard: [1, Set the TXE flags. This allows to discard the transmit data] + ABRRQ: + Request: + [ + 1, + resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame, + ] +ISR: + LBDF: + NotDetected: [0, LIN break not detected] + Detected: [1, LIN break detected] + RTOF: + NotReached: [0, Timeout value not reached] + Reached: [1, Timeout value reached without any data reception] + EOBF: + NotReached: [0, End of Block not reached] + Reached: [1, End of Block (number of characters) reached] + ABRF: + ABRE: +ICR: + EOBCF: + Clear: [1, Clears the EOBF flag in the ISR register] + LBDCF: + Clear: [1, Clears the LBDF flag in the ISR register] + RTOCF: + Clear: [1, Clears the RTOF flag in the ISR register] diff --git a/devices/fields/usart/v3/C.yaml b/devices/fields/usart/v3/C.yaml new file mode 100644 index 000000000..742a91a36 --- /dev/null +++ b/devices/fields/usart/v3/C.yaml @@ -0,0 +1,6 @@ +# USART v2C found on some F7 devices + +_include: + - ABC_common.yaml + - BC_common.yaml + - m.yaml diff --git a/devices/fields/usart/v3/lp_A.yaml b/devices/fields/usart/v3/lp_A.yaml new file mode 100644 index 000000000..02e017b4c --- /dev/null +++ b/devices/fields/usart/v3/lp_A.yaml @@ -0,0 +1,11 @@ +# LPUART1 found on L0 and L4 families + +_include: + - ABC_common.yaml + - AB_common.yaml + - m.yaml + +ISR: + CMCF: +BRR: + BRR: [0, 0xFFFFF] diff --git a/devices/fields/usart/v3/m.yaml b/devices/fields/usart/v3/m.yaml new file mode 100644 index 000000000..ed4c5b139 --- /dev/null +++ b/devices/fields/usart/v3/m.yaml @@ -0,0 +1,10 @@ +# USART v2 with 7bit data + +# FIXME workaround separated M0 and M1 fields +CR1: + "M,M0": + Bit8: [0, "1 start bit, 8 data bits, n stop bits"] + Bit9: [1, "1 start bit, 9 data bits, n stop bits"] + "?~M1": + M0: [0, Use M0 to set the data bits] + Bit7: [1, "1 start bit, 7 data bits, n stop bits"] diff --git a/devices/fields/usart/v3/usart3_B2.yaml b/devices/fields/usart/v3/usart3_B2.yaml new file mode 100644 index 000000000..6f938827a --- /dev/null +++ b/devices/fields/usart/v3/usart3_B2.yaml @@ -0,0 +1,11 @@ +CR3: + TCBGTIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, "An USART interrupt is generated whenever TCBGT=1 in the ISR register"] + UCESM: + Disabled: [0, USART clock is disabled in STOP mode] + Enabled: [1, USART clock is enabled in STOP mode] +ISR: + TCBGT: + NotCompleted: [0, Transmission not completed] + Completed: [1, Transmission has completed] diff --git a/devices/fields/usart/v4/B.yaml b/devices/fields/usart/v4/B.yaml new file mode 100644 index 000000000..a13c2f891 --- /dev/null +++ b/devices/fields/usart/v4/B.yaml @@ -0,0 +1,7 @@ +_include: + - ../v3/B.yaml + - fifoen_common.yaml + - fifoen_usart.yaml + - sync_slave.yaml + - smartcard.yaml + - prescalar.yaml diff --git a/devices/fields/usart/v4/C.yaml b/devices/fields/usart/v4/C.yaml new file mode 100644 index 000000000..b228d3623 --- /dev/null +++ b/devices/fields/usart/v4/C.yaml @@ -0,0 +1,7 @@ +_include: + - ../v3/C.yaml + - fifoen_common.yaml + - fifoen_usart.yaml + - sync_slave.yaml + - smartcard.yaml + - prescalar.yaml diff --git a/devices/fields/usart/v4/fifoen_common.yaml b/devices/fields/usart/v4/fifoen_common.yaml new file mode 100644 index 000000000..f1f884f0f --- /dev/null +++ b/devices/fields/usart/v4/fifoen_common.yaml @@ -0,0 +1,44 @@ +CR1: + RXFFIE: + Disabled: [0, Interrupt inhibited] + Enabled: [1, "USART interrupt generated when RXFF = 1 in the USART_ISR register"] + TXFEIE: + Disabled: [0, Interrupt inhibited] + Enabled: [1, "USART interrupt generated when TXFE = 1 in the USART_ISR register"] + FIFOEN: + Disabled: [0, FIFO mode is disabled] + Enabled: [1, FIFO mode is enabled] +CR3: + TXFTCFG: + Depth_1_8: [0, TXFIFO reaches 1/8 of its depth] + Depth_1_4: [1, TXFIFO reaches 1/4 of its depth] + Depth_1_2: [2, TXFIFO reaches 1/2 of its depth] + Depth_3_4: [3, TXFIFO reaches 3/4 of its depth] + Depth_7_8: [4, TXFIFO reaches 7/8 of its depth] + Empty: [5, TXFIFO becomes empty] + RXFTIE: + Disabled: [0, Interrupt inhibited] + Enabled: [1, USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG] + RXFTCFG: + Depth_1_8: [0, RXFIFO reaches 1/8 of its depth] + Depth_1_4: [1, RXFIFO reaches 1/4 of its depth] + Depth_1_2: [2, RXFIFO reaches 1/2 of its depth] + Depth_3_4: [3, RXFIFO reaches 3/4 of its depth] + Depth_7_8: [4, RXFIFO reaches 7/8 of its depth] + Full: [5, RXFIFO becomes full] + TXFTIE: + Disabled: [0, Interrupt inhibited] + Enabled: [1, USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG] +ISR: + TXFE: + NotEmpty: [0, TXFIFO not empty.] + Empty: [1, TXFIFO empty.] + RXFF: + NotFull: [0, RXFIFO not full.] + Full: [1, RXFIFO Full.] + RXFT: + NotReached: [0, Receive FIFO does not reach the programmed threshold.] + Reached: [1, Receive FIFO reached the programmed threshold.] + TXFT: + NotReached: [0, TXFIFO does not reach the programmed threshold.] + Reached: [1, TXFIFO reached the programmed threshold.] diff --git a/devices/fields/usart/v4/fifoen_usart.yaml b/devices/fields/usart/v4/fifoen_usart.yaml new file mode 100644 index 000000000..630b3d945 --- /dev/null +++ b/devices/fields/usart/v4/fifoen_usart.yaml @@ -0,0 +1,3 @@ +ICR: + TXFECF: + Clear: [1, Clear the TXFE flag in the ISR register] diff --git a/devices/fields/usart/v4/lp_wl.yaml b/devices/fields/usart/v4/lp_wl.yaml new file mode 100644 index 000000000..a1b9b0001 --- /dev/null +++ b/devices/fields/usart/v4/lp_wl.yaml @@ -0,0 +1,161 @@ +# LPUART in WL family +_include: + - ../v3/AB_common.yaml + - ../v3/m.yaml + - fifoen_common.yaml +CR1: + DEAT: [0, 0b11111] + DEDT: [0, 0b11111] + CMIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, Interrupt is generated when the CMF bit is set in the ISR register] + MME: + Disabled: [0, Receiver in active mode permanently] + Enabled: [1, Receiver can switch between mute mode and active mode] + WAKE: + Idle: [0, Idle line] + Address: [1, Address mask] + PCE: + Disabled: [0, Parity control disabled] + Enabled: [1, Parity control enabled] + PS: + Even: [0, Even parity] + Odd: [1, Odd parity] + PEIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever PE=1 in the ISR register"] + TXEIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever TXE=1 in the ISR register"] + TCIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever TC=1 in the ISR register"] + RXNEIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register"] + IDLEIE: + Disabled: [0, Interrupt is disabled] + Enabled: [1, "Interrupt is generated whenever IDLE=1 in the ISR register"] + TE: + Disabled: [0, Transmitter is disabled] + Enabled: [1, Transmitter is enabled] + RE: + Disabled: [0, Receiver is disabled] + Enabled: [1, Receiver is enabled] + UE: + Disabled: [0, UART is disabled] + Enabled: [1, UART is enabled] +CR2: + ADD: [0, 0xFF] + MSBFIRST: + LSB: [0, "data is transmitted/received with data bit 0 first, following the start bit"] + MSB: [1, "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"] + DATAINV: + Positive: [0, Logical data from the data register are send/received in positive/direct logic] + Negative: [1, Logical data from the data register are send/received in negative/inverse logic] + TXINV: + Standard: [0, TX pin signal works using the standard logic levels] + Inverted: [1, TX pin signal values are inverted] + RXINV: + Standard: [0, RX pin signal works using the standard logic levels] + Inverted: [1, RX pin signal values are inverted] + SWAP: + Standard: [0, TX/RX pins are used as defined in standard pinout] + Swapped: [1, The TX and RX pins functions are swapped] + STOP: + Stop1: [0, 1 stop bit] + Stop2: [2, 2 stop bit] + ADDM7: + Bit4: [0, 4-bit address detection] + Bit7: [1, 7-bit address detection] +CR3: + DEP: + High: [0, DE signal is active high] + Low: [1, DE signal is active low] + DEM: + Disabled: [0, DE function is disabled] + Enabled: [1, The DE signal is output on the RTS pin] + DDRE: + NotDisabled: [0, DMA is not disabled in case of reception error] + Disabled: [1, DMA is disabled following a reception error] + OVRDIS: + Enabled: [0, "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"] + Disabled: + [ + 1, + Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register, + ] + CTSIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, "An interrupt is generated whenever CTSIF=1 in the ISR register"] + CTSE: + Disabled: [0, CTS hardware flow control disabled] + Enabled: [1, "CTS mode enabled, data is only transmitted when the CTS input is asserted"] + RTSE: + Disabled: [0, RTS hardware flow control disabled] + Enabled: [1, "RTS output enabled, data is only requested when there is space in the receive buffer"] + DMAT: + Disabled: [0, DMA mode is disabled for transmission] + Enabled: [1, DMA mode is enabled for transmission] + DMAR: + Disabled: [0, DMA mode is disabled for reception] + Enabled: [1, DMA mode is enabled for reception] + HDSEL: + NotSelected: [0, Half duplex mode is not selected] + Selected: [1, Half duplex mode is selected] + EIE: + Disabled: [0, Interrupt is inhibited] + Enabled: [1, "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"] +RQR: + TXFRQ: + Discard: [1, Set the TXE flags. This allows to discard the transmit data] + RXFRQ: + Discard: + [ + 1, + "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition", + ] + MMRQ: + Mute: [1, Puts the USART in mute mode and sets the RWU flag] + SBKRQ: + Break: + [1, "sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"] +ICR: + "*": + _W1C: {} + CMCF: + Clear: [1, Clears the CMF flag in the ISR register] + CTSCF: + Clear: [1, Clears the CTSIF flag in the ISR register] + TCCF: + Clear: [1, Clears the TC flag in the ISR register] + IDLECF: + Clear: [1, Clears the IDLE flag in the ISR register] + ORECF: + Clear: [1, Clears the ORE flag in the ISR register] + "NECF,NCF": + Clear: [1, Clears the NF flag in the ISR register] + FECF: + Clear: [1, Clears the FE flag in the ISR register] + PECF: + Clear: [1, Clears the PE flag in the ISR register] +RDR: + RDR: [0, 0x1FF] +TDR: + TDR: [0, 0x1FF] +BRR: + BRR: [0, 0xFFFFF] +PRESC: + PRESCALER: + Div1: [0b0000, "/1"] + Div2: [0b0001, "/2"] + Div4: [0b0010, "/4"] + Div6: [0b0011, "/6"] + Div8: [0b0100, "/8"] + Div10: [0b0101, "/10"] + Div12: [0b0110, "/12"] + Div16: [0b0111, "/16"] + Div32: [0b1000, "/32"] + Div64: [0b1001, "/64"] + Div128: [0b1010, "/128"] + Div256: [0b1011, "/256"] diff --git a/devices/fields/usart/v4/prescalar.yaml b/devices/fields/usart/v4/prescalar.yaml new file mode 100644 index 000000000..97ce1be36 --- /dev/null +++ b/devices/fields/usart/v4/prescalar.yaml @@ -0,0 +1,14 @@ +PRESC: + PRESCALER: + Div1: [0b0000, Input clock divided by 1] + Div2: [0b0001, Input clock divided by 2] + Div4: [0b0010, Input clock divided by 4] + Div6: [0b0011, Input clock divided by 6] + Div8: [0b0100, Input clock divided by 8] + Div10: [0b0101, Input clock divided by 10] + Div12: [0b0110, Input clock divided by 12] + Div16: [0b0111, Input clock divided by 16] + Div32: [0b1000, Input clock divided by 32] + Div64: [0b1001, Input clock divided by 64] + Div128: [0b1010, Input clock divided by 128] + Div256: [0b1011, Input clock divided by 256] diff --git a/devices/fields/usart/v4/smartcard.yaml b/devices/fields/usart/v4/smartcard.yaml new file mode 100644 index 000000000..970a49520 --- /dev/null +++ b/devices/fields/usart/v4/smartcard.yaml @@ -0,0 +1,18 @@ +CR3: + TCBGTIE: + Disabled: [0, Interrupt inhibited] + Enabled: [1, "USART interrupt generated whenever TCBGT=1 in the USART_ISR register"] + +ISR: + TCBGT: + NotCompleted: + [ + 0, + Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is received from the card), + ] + Completed: + [1, Transmission is complete successfully (before Guard time completion and there is no NACK from the smart card)] + +ICR: + TCBGTCF: + Clear: [1, Clear the TCBGT flag in the ISR register] diff --git a/devices/fields/usart/v4/sync_slave.yaml b/devices/fields/usart/v4/sync_slave.yaml new file mode 100644 index 000000000..589c41c07 --- /dev/null +++ b/devices/fields/usart/v4/sync_slave.yaml @@ -0,0 +1,14 @@ +CR2: + DIS_NSS: + Disabled: [0, SPI slave selection depends on NSS input pin] + Enabled: [1, SPI slave is always selected and NSS input pin is ignored] + SLVEN: + Disabled: [0, Slave mode disabled] + Enabled: [1, Slave mode enabled] +ISR: + UDR: + NoUnderrun: [0, No underrun error] + Underrun: [1, underrun error] +ICR: + UDRCF: + Clear: [1, Clear the UDR flag in the ISR register] diff --git a/devices/fields/usb/v1.yaml b/devices/fields/usb/v1.yaml new file mode 100644 index 000000000..f86021f2d --- /dev/null +++ b/devices/fields/usb/v1.yaml @@ -0,0 +1,174 @@ +# USB peripheral and associated SRAM + +CNTR: + CTRM: + Disabled: [0, Correct Transfer (CTR) Interrupt disabled] + Enabled: + [ + 1, + "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + PMAOVRM: + Disabled: [0, PMAOVR Interrupt disabled] + Enabled: + [ + 1, + "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + ERRM: + Disabled: [0, ERR Interrupt disabled] + Enabled: + [ + 1, + "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + WKUPM: + Disabled: [0, WKUP Interrupt disabled] + Enabled: + [ + 1, + "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + SUSPM: + Disabled: [0, Suspend Mode Request SUSP Interrupt disabled] + Enabled: + [ + 1, + "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + RESETM: + Disabled: [0, RESET Interrupt disabled] + Enabled: + [ + 1, + "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + SOFM: + Disabled: [0, SOF Interrupt disabled] + Enabled: + [ + 1, + "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + ESOFM: + Disabled: [0, ESOF Interrupt disabled] + Enabled: + [ + 1, + "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + RESUME: + Requested: [1, Resume requested] + FSUSP: + NoEffect: [0, No effect] + Suspend: [1, Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected] + "LPMODE,LP_MODE": + Disabled: [0, No low-power mode] + Enabled: [1, Enter low-power mode] + PDWN: + Disabled: [0, No power down] + Enabled: [1, Enter power down mode] + FRES: + NoReset: [0, Clear USB reset] + Reset: [1, "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB"] +ISTR: + CTR: + Completed: [1, Endpoint has successfully completed a transaction] + PMAOVR: + _read: + NotOverrun: [0, Overrun is not occurred] + Overrun: [1, Microcontroller has not been able to respond in time to an USB memory request] + _W0C: + Clear: [0, Clear flag] + ERR: + _read: + NotOverrun: [0, Errors are not occurred] + Error: [1, "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred"] + _W0C: + Clear: [0, Clear flag] + WKUP: + _read: + NotWakeup: [0, NotWakeup] + Wakeup: [1, Activity is detected that wakes up the USB peripheral] + _W0C: + Clear: [0, Clear flag] + SUSP: + _read: + NotSuspend: [0, NotSuspend] + Suspend: [1, "No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus"] + _W0C: + Clear: [0, Clear flag] + RESET: + _read: + NotReset: [0, NotReset] + Reset: [1, Peripheral detects an active USB RESET signal at its inputs] + _W0C: + Clear: [0, Clear flag] + SOF: + _read: + NotStartOfFrame: [0, NotStartOfFrame] + StartOfFrame: [1, Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus] + _W0C: + Clear: [0, Clear flag] + ESOF: + _read: + NotExpectedStartOfFrame: [0, NotExpectedStartOfFrame] + ExpectedStartOfFrame: [1, An SOF packet is expected but not received] + _W0C: + Clear: [0, Clear flag] + DIR: + To: [0, Data transmitted by the USB peripheral to the host PC] + From: [1, Data received by the USB peripheral from the host PC] + EP_ID: [0, 0b1111] +FNR: + RXDP: + Received: [1, received data plus upstream port data line] + RXDM: + Received: [1, received data minus upstream port data line] + LCK: + Locked: [1, the frame timer remains in this state until an USB reset or USB suspend event occurs] + LSOF: [0, 0b11] + FN: [0, 0b11111111111] +DADDR: + EF: + Disabled: [0, USB device disabled] + Enabled: [1, USB device enabled] + ADD: [0, 0b1111111] +BTABLE: + BTABLE: [0, 0b1111111111111] +EP*R: + _modify: + STAT_[RT]X: + access: read-write + CTR_RX: + _W0C: {} + DTOG_RX: + _W1T: {} + STAT_RX: + _read: + Disabled: [0, all reception requests addressed to this endpoint are ignored] + Stall: [1, the endpoint is stalled and all reception requests result in a STALL handshake] + Nak: [2, the endpoint is naked and all reception requests result in a NAK handshake] + Valid: [3, this endpoint is enabled for reception] + _W1T: {} + SETUP: + #"the last completed transaction is a SETUP"] + EP_TYPE: + Bulk: [0, Bulk endpoint] + Control: [1, Control endpoint] + Iso: [2, Iso endpoint] + Interrupt: [3, Interrupt endpoint] + EP_KIND: + #"DBL_BUF if EP_TYPE=Bulk or STATUS_OUT if EP_TYPE=Control"] + CTR_TX: + _W0C: {} + DTOG_TX: + _W1T: {} + STAT_TX: + _read: + Disabled: [0, all transmission requests addressed to this endpoint are ignored] + Stall: [1, the endpoint is stalled and all transmission requests result in a STALL handshake] + Nak: [2, the endpoint is naked and all transmission requests result in a NAK handshake] + Valid: [3, this endpoint is enabled for transmission] + _W1T: {} + EA: [0, 0b1111] diff --git a/devices/fields/usb/v2.yaml b/devices/fields/usb/v2.yaml new file mode 100644 index 000000000..e6057f48c --- /dev/null +++ b/devices/fields/usb/v2.yaml @@ -0,0 +1,50 @@ +# Extends USB peripheral with Low-Power Mode + +_include: + - v1.yaml + +CNTR: + L1REQM: + Disabled: [0, L1REQ Interrupt disabled] + Enabled: + [ + 1, + "L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set", + ] + L1RESUME: + Requested: [1, LPM L1 request requested] +ISTR: + L1REQ: + _read: + NotReceived: [0, LPM command to enter the L1 state is not received] + Received: [1, LPM command to enter the L1 state is successfully received and acknowledged] + _W0C: + Clear: [0, Clear flag] +BCDR: + DPPU: + Disabled: [0, signalize disconnect to the host when needed by the user software] + Enabled: [1, enable the embedded pull-up on the DP line] + PS2DET: + Normal: [0, Normal port detected] + PS2: [1, PS2 port or proprietary charger detected] + SDET: + CDP: [0, CDP detected] + DCP: [1, DCP detected] + PDET: + NoBCD: [0, no BCD support detected] + BCD: [1, BCD support detected] + DCDET: + NotDetected: [0, data lines contact not detected] + Detected: [1, data lines contact detected] + SDEN: + Disabled: [0, Secondary detection (SD) mode disabled] + Enabled: [1, Secondary detection (SD) mode enabled] + PDEN: + Disabled: [0, Primary detection (PD) mode disabled] + Enabled: [1, Primary detection (PD) mode enabled] + DCDEN: + Disabled: [0, Data contact detection (DCD) mode disabled] + Enabled: [1, Data contact detection (DCD) mode enabled] + BCDEN: + Disabled: [0, disable the BCD support] + Enabled: [1, enable the BCD support within the USB device] diff --git a/devices/fields/usb/v2_with_LPM.yaml b/devices/fields/usb/v2_with_LPM.yaml new file mode 100644 index 000000000..bb531551e --- /dev/null +++ b/devices/fields/usb/v2_with_LPM.yaml @@ -0,0 +1,14 @@ +# Extends USB peripheral with Low-Power Mode + +_include: + - v2.yaml + +LPMCSR: + BESL: [0, 0xf] + REMWAKE: + LPMACK: + Nyet: [0, The valid LPM Token will be NYET] + Ack: [1, The valid LPM Token will be ACK] + LPMEN: + Disabled: [0, No LPM transactions are handled] + Enabled: [1, Enable the LPM support within the USB device] diff --git a/devices/fields/usb/v3.yaml b/devices/fields/usb/v3.yaml new file mode 100644 index 000000000..2ef235f9b --- /dev/null +++ b/devices/fields/usb/v3.yaml @@ -0,0 +1,137 @@ +# Fixes duplicate enum values +CNTR: + USBRST: + NoEffect: [0, No effect] + Reset: [1, USB core is under reset / USB reset driven] + SUSPEN: + NoEffect: [0, No effect] + Suspend: [1, Enter L1/L2 suspend] + "L1RESUME,L1RES": + NoEffect: [0, No effect] + WakeupResume: [1, Send 50us remote-wakeup signaling to host / Send L1 resume signaling to device] +LPMCSR: + LPMACK: + Nyet: [0, The valid LPM Token will be NYET / NYET answer] + Ack: [1, The valid LPM Token will be ACK / ACK answer] +CHEP?R: + _modify: + STAT[RT]X: + access: read-write + STATTX: + _read: + Disabled: [0, All transmission requests addressed to this endpoint/channel are ignored.] + Stall: + [ + 1, + "Device mode: the endpoint is stalled and all transmission requests result in a STALL handshake.\nHost mode: this indicates that the device has STALLed the channel.", + ] + Nak: + [ + 2, + "Device mode: the endpoint is NAKed and all transmission requests result in a NAK handshake.\nHost mode: this indicates that the device has NAKed the transmission request.", + ] + Valid: [3, This endpoint/channel is enabled for transmission.] + _W1T: + Keep: [0, Do not change bits] + DTOGTX: + _W1T: + Toggle: [1, Flip bit] + VTTX: + _W0C: + Clear: [0, Clear flag] + UTYPE: + Bulk: [0, Bulk endpoint] + Control: [1, Control endpoint] + Iso: [2, Isochronous endpoint] + Interrupt: [3, Interrupt endpoint] + STATRX: + _read: + Disabled: [0, All reception requests addressed to this endpoint/channel are ignored.] + Stall: + [ + 1, + "Device mode: the endpoint is stalled and all reception requests result in a STALL handshake.\nHost mode: this indicates that the device has STALLed the channel.", + ] + Nak: + [ + 2, + "Device mode: the endpoint is NAKed and all reception requests result in a NAK handshake.\nHost mode: this indicates that the device has NAKed the reception request.", + ] + Valid: [3, This endpoint/channel is enabled for reception.] + _W1T: + Keep: [0, Do not change bits] + DTOGRX: + _W1T: + Toggle: [1, Flip bit] + VTRX: + _W0C: + Clear: [0, Clear flag] + NAK: + _W0C: + Clear: [0, Clear flag] + ERR_TX: + _W0C: + Clear: [0, Clear flag] + ERR_RX: + _W0C: + Clear: [0, Clear flag] +ISTR: + THR512: + _read: + NotReached: [0, 512 bytes threshold not reached] + Reached: [1, 512 bytes have been transmitted or received during isochronous transfers] + _W0C: + Clear: [0, Clear flag] + CTR: + Completed: [1, Endpoint has successfully completed a transaction] + PMAOVR: + _read: + NotOverrun: [0, Overrun is not occurred] + Overrun: [1, Microcontroller has not been able to respond in time to an USB memory request] + _W0C: + Clear: [0, Clear flag] + ERR: + _read: + NotError: [0, Errors are not occurred] + Error: [1, "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred"] + _W0C: + Clear: [0, Clear flag] + WKUP: + _read: + NotWakeup: [0, NotWakeup] + Wakeup: [1, Activity is detected that wakes up the USB peripheral] + _W0C: + Clear: [0, Clear flag] + SUSP: + _read: + NotSuspend: [0, NotSuspend] + Suspend: [1, "No traffic has been received for 3 ms, indicating a suspend mode request from the USB bus"] + _W0C: + Clear: [0, Clear flag] + RST_DCON: + _read: + NotReset: [0, NotReset] + Reset: [1, Peripheral detects an active USB RESET signal at its inputs] + _W0C: + Clear: [0, Clear flag] + SOF: + _read: + NotStartOfFrame: [0, NotStartOfFrame] + StartOfFrame: [1, Beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus] + _W0C: + Clear: [0, Clear flag] + ESOF: + _read: + NotExpectedStartOfFrame: [0, NotExpectedStartOfFrame] + ExpectedStartOfFrame: [1, An SOF packet is expected but not received] + _W0C: + Clear: [0, Clear flag] + L1REQ: + _read: + NotL1State: [0, NotL1State] + L1State: [1, LPM command to enter the L1 state is successfully received and acknowledged] + _W0C: + Clear: [0, Clear flag] + DIR: + To: [0, Data transmitted by the USB peripheral to the host PC] + From: [1, Data received by the USB peripheral from the host PC] diff --git a/devices/fields/vrefbuf/vrefbuf_wl.yaml b/devices/fields/vrefbuf/vrefbuf_wl.yaml new file mode 100644 index 000000000..5af9c8268 --- /dev/null +++ b/devices/fields/vrefbuf/vrefbuf_wl.yaml @@ -0,0 +1,17 @@ +# Vrefbuf peripheral for WL family + +CSR: + VRR: + NotReady: [0, The voltage reference buffer output is not ready] + Ready: [1, The voltage reference buffer output reached the requested level] + VRS: + V2_048: [0, Voltage reference set to VREF_OUT1 (around 2.048 V)] + V2_5: [1, Voltage reference set to VREF_OUT2 (around 2.5 V)] + HIZ: + Connected: [0, "VREF+ pin is internally connected to the voltage reference buffer output"] + HighZ: [1, "VREF+ pin is high impedance"] + ENVR: + Disabled: [0, Internal voltage reference mode disable (external voltage reference mode)] + Enabled: [1, Internal voltage reference mode (reference buffer enable or hold mode) enable] +CCR: + TRIM: [0, 0b111111] diff --git a/devices/fields/wwdg/wwdg.yaml b/devices/fields/wwdg/wwdg.yaml new file mode 100644 index 000000000..63092eba5 --- /dev/null +++ b/devices/fields/wwdg/wwdg.yaml @@ -0,0 +1,25 @@ +# Window watchdog + +CR: + WDGA: + Disabled: [0, Watchdog disabled] + Enabled: [1, Watchdog enabled] + T: [0, 127] +CFR: + _merge: WDGTB* + WDGTB: + Div1: [0, Counter clock (PCLK1 div 4096) div 1] + Div2: [1, Counter clock (PCLK1 div 4096) div 2] + Div4: [2, Counter clock (PCLK1 div 4096) div 4] + Div8: [3, Counter clock (PCLK1 div 4096) div 8] + W: [0, 127] + EWI: + _write: + Enable: [1, interrupt occurs whenever the counter reaches the value 0x40] +SR: + EWIF: + _read: + Pending: [1, The EWI Interrupt Service Routine has been triggered] + Finished: [0, The EWI Interrupt Service Routine has been serviced] + _W0C: + Finished: [0, The EWI Interrupt Service Routine has been serviced] diff --git a/devices/fields/wwdg/wwdg_v2.yaml b/devices/fields/wwdg/wwdg_v2.yaml new file mode 100644 index 000000000..5f0623e09 --- /dev/null +++ b/devices/fields/wwdg/wwdg_v2.yaml @@ -0,0 +1,12 @@ +# WWDG peripheral for the g4 and h7 families. +# Extend `wwdg.yaml`. + +_include: + - wwdg.yaml + +CFR: + WDGTB: + Div16: [4, Counter clock (PCLK1 div 4096) div 16] + Div32: [5, Counter clock (PCLK1 div 4096) div 32] + Div64: [6, Counter clock (PCLK1 div 4096) div 64] + Div128: [7, Counter clock (PCLK1 div 4096) div 128] diff --git a/devices/patches/16bit.yaml b/devices/patches/16bit.yaml new file mode 100644 index 000000000..90c628a26 --- /dev/null +++ b/devices/patches/16bit.yaml @@ -0,0 +1,3 @@ +_modify: + "?*": + size: 16 diff --git a/devices/patches/16bit_with_mask.yaml b/devices/patches/16bit_with_mask.yaml new file mode 100644 index 000000000..c1ed54511 --- /dev/null +++ b/devices/patches/16bit_with_mask.yaml @@ -0,0 +1,4 @@ +_modify: + "?*": + size: 16 + resetMask: 0xffff diff --git a/devices/patches/adc/adc_common_group_name.yaml b/devices/patches/adc/adc_common_group_name.yaml new file mode 100644 index 000000000..b32e5a206 --- /dev/null +++ b/devices/patches/adc/adc_common_group_name.yaml @@ -0,0 +1,5 @@ +# Rename group name of ADC_Common from ADC to ADC_Common + +_modify: + ADC_Common: + groupName: ADC_Common diff --git a/devices/patches/adc/c0.yaml b/devices/patches/adc/c0.yaml new file mode 100644 index 000000000..707bf91ae --- /dev/null +++ b/devices/patches/adc/c0.yaml @@ -0,0 +1,7 @@ +_strip: ADC_ +_modify: + CHSELR_MOD0: + name: CHSELR0 + CHSELR_MOD1: + name: CHSELR1 + alternateRegister: CHSELR0 diff --git a/devices/patches/adc/dr_rdata.yaml b/devices/patches/adc/dr_rdata.yaml new file mode 100644 index 000000000..7c87a4ebb --- /dev/null +++ b/devices/patches/adc/dr_rdata.yaml @@ -0,0 +1,5 @@ +DR: + _modify: + regularDATA: + name: RDATA + description: Regular data diff --git a/devices/patches/adc/f0_cfgr2_ckmode.yaml b/devices/patches/adc/f0_cfgr2_ckmode.yaml new file mode 100644 index 000000000..2e68d9347 --- /dev/null +++ b/devices/patches/adc/f0_cfgr2_ckmode.yaml @@ -0,0 +1,11 @@ +# Merge together ADC CFGR2 separated JITOFF_Dx fields +# and properly rename to CKMODE + +CFGR2: + _modify: + JITOFF_D2: + name: CKMODE0 + JITOFF_D4: + name: CKMODE1 + description: ADC clock mode + _merge: CKMODE* diff --git a/devices/patches/adc/f0_fixes.yaml b/devices/patches/adc/f0_fixes.yaml new file mode 100644 index 000000000..a722a9185 --- /dev/null +++ b/devices/patches/adc/f0_fixes.yaml @@ -0,0 +1,19 @@ +# Renames a few fields in the F0 ADC and replaces AUTDLY with WAIT + +ISR: + _modify: + EOS: + name: EOSEQ +IER: + _modify: + EOSIE: + name: EOSEQIE +CFGR1: + _modify: + AUTDLY: + name: WAIT + description: Wait conversion mode +SMPR: + _modify: + SMPR: + name: SMP diff --git a/devices/patches/adc/f3.yaml b/devices/patches/adc/f3.yaml new file mode 100644 index 000000000..f97f88ff9 --- /dev/null +++ b/devices/patches/adc/f3.yaml @@ -0,0 +1,22 @@ +_include: + - dr_rdata.yaml + +SQR1: + _modify: + L3: + name: L +DIFSEL: + _merge: + DIFSEL: DIFSEL* +CFGR: + _delete: + - AUTOFF + _modify: + AWDCH1CH: + name: AWD1CH +CR: + _delete: + - DEEPPWD + _modify: + ADVREGEN: + bitWidth: 2 diff --git a/devices/patches/adc/f3_multi_dual.yaml b/devices/patches/adc/f3_multi_dual.yaml new file mode 100644 index 000000000..c296adeaa --- /dev/null +++ b/devices/patches/adc/f3_multi_dual.yaml @@ -0,0 +1,5 @@ +CCR: + _modify: + MULT: + name: DUAL + description: Dual ADC mode selection diff --git a/devices/patches/adc/g0.yaml b/devices/patches/adc/g0.yaml new file mode 100644 index 000000000..dbd604907 --- /dev/null +++ b/devices/patches/adc/g0.yaml @@ -0,0 +1,14 @@ +_modify: + CHSELR: + name: CHSELR0 + CHSELR_1: + name: CHSELR1 + alternateRegister: CHSELR0 +CFGR1: + _modify: + AWDCH1CH: + name: AWD1CH +DR: + _modify: + regularDATA: + name: DATA diff --git a/devices/patches/adc/g4.yaml b/devices/patches/adc/g4.yaml new file mode 100644 index 000000000..351f9d9fb --- /dev/null +++ b/devices/patches/adc/g4.yaml @@ -0,0 +1,302 @@ +_include: + - jdata.yaml + - offset_en.yaml + +ISR: + _modify: + JQOVF: + description: Injected context queue overflow + AWD3: + description: Analog watchdog 3 flag + AWD2: + description: Analog watchdog 2 flag + AWD1: + description: Analog watchdog 1 flag + JEOS: + description: Injected channel end of sequence flag + JEOC: + description: Injected channel end of conversion flag + OVR: + description: ADC overrun + EOS: + description: End of regular sequence flag + EOC: + description: End of conversion flag + EOSMP: + description: End of sampling flag + ADRDY: + description: ADC ready + +IER: + _modify: + JQOVFIE: + description: Injected context queue overflow interrupt enable + AWD3IE: + description: Analog watchdog 3 interrupt enable + AWD2IE: + description: Analog watchdog 2 interrupt enable + AWD1IE: + description: Analog watchdog 1 interrupt enable + JEOSIE: + description: End of injected sequence of conversions interrupt enable + JEOCIE: + description: End of injected conversion interrupt enable + OVRIE: + description: Overrun interrupt enable + EOSIE: + description: End of regular sequence of conversions interrupt enable + EOCIE: + description: End of regular conversion interrupt enable + EOSMPIE: + description: End of sampling flag interrupt enable for regular conversions + ADRDYIE: + description: ADC ready interrupt enable + +CR: + _modify: + ADCAL: + description: ADC calibration + ADCALDIF: + description: Differential mode for calibration + DEEPPWD: + description: Deep-power-down enable + ADVREGEN: + description: ADC voltage regulator enable + JADSTP: + description: ADC stop of injected conversion command + ADSTP: + description: ADC stop of regular conversion command + JADSTART: + description: ADC start of injected conversion + ADSTART: + description: ADC start of regular conversion + ADDIS: + description: ADC disable command + ADEN: + description: ADC enable control + +CFGR: + _modify: + "AWDCH1CH,AWD1CH": + name: AWD1CH + description: Analog watchdog 1 channel selection + JAUTO: + description: Automatic injected group conversion + JAWD1EN: + description: Analog watchdog 1 enable on injected channels + AWD1EN: + description: Analog watchdog 1 enable on regular channels + AWD1SGL: + description: Enable the watchdog 1 on a single channel or on all channels + JQM: + description: JSQR queue mode + JDISCEN: + description: Discontinuous mode on injected channels + DISCNUM: + description: Discontinuous mode channel count + DISCEN: + description: Discontinuous mode for regular channels + ALIGN: + description: Data alignment + AUTDLY: + description: Delayed conversion mode + CONT: + description: Single / continuous conversion mode for regular conversions + OVRMOD: + description: Overrun mode + EXTEN: + description: External trigger enable and polarity selection for regular channels + EXTSEL: + description: External trigger selection for regular group + bitOffset: 5 + bitWidth: 5 + RES: + description: Data resolution + DMACFG: + description: Direct memory access configuration + DMAEN: + description: Direct memory access enable + +CFGR2: + _modify: + SMPTRIG: + description: Sampling time control trigger mode + BULB: + description: Bulb sampling mode + SWTRIG: + description: Software trigger bit for sampling time control trigger mode + GCOMP: + description: Gain compensation mode + ROVSM: + description: Regular Oversampling mode + TROVS: + description: Triggered Regular Oversampling + OVSS: + description: Oversampling shift + OVSR: + description: Oversampling ratio + JOVSE: + description: Injected Oversampling Enable + ROVSE: + description: Regular Oversampling Enable + +SMPR1: + _modify: + SMPPLUS: + description: Addition of one clock cycle to the sampling time + SMP9: + description: Channel 9 sampling time selection + SMP8: + description: Channel 8 sampling time selection + SMP7: + description: Channel 7 sampling time selection + SMP6: + description: Channel 6 sampling time selection + SMP5: + description: Channel 5 sampling time selection + SMP4: + description: Channel 4 sampling time selection + SMP3: + description: Channel 3 sampling time selection + SMP2: + description: Channel 2 sampling time selection + SMP1: + description: Channel 1 sampling time selection + SMP0: + description: Channel 0 sampling time selection + +SMPR2: + _modify: + SMP18: + description: Channel 18 sampling time selection + SMP17: + description: Channel 17 sampling time selection + SMP16: + description: Channel 16 sampling time selection + SMP15: + description: Channel 15 sampling time selection + SMP14: + description: Channel 14 sampling time selection + SMP13: + description: Channel 13 sampling time selection + SMP11: + description: Channel 12 sampling time selection + SMP12: + description: Channel 11 sampling time selection + SMP10: + description: Channel 10 sampling time selection + +TR1: + _modify: + HT1: + description: Analog watchdog 1 higher threshold + AWDFILT: + description: Analog watchdog filtering parameter + LT1: + description: Analog watchdog 1 lower threshold + +TR2: + _modify: + HT2: + description: Analog watchdog 2 higher threshold + LT2: + description: Analog watchdog 2 lower threshold + +TR3: + _modify: + HT3: + description: Analog watchdog 3 higher threshold + LT3: + description: Analog watchdog 3 lower threshold + +SQR1: + _modify: + SQ4: + description: 4th conversion in regular sequence + SQ3: + description: 3rd conversion in regular sequence + SQ2: + description: 2nd conversion in regular sequence + SQ1: + description: 1st conversion in regular sequence + L: + description: Regular channel sequence length + +SQR2: + _modify: + SQ9: + description: 9th conversion in regular sequence + SQ8: + description: 8th conversion in regular sequence + SQ7: + description: 7th conversion in regular sequence + SQ6: + description: 6th conversion in regular sequence + SQ5: + description: 5th conversion in regular sequence + +SQR3: + _modify: + SQ14: + description: 14th conversion in regular sequence + SQ13: + description: 13th conversion in regular sequence + SQ12: + description: 12th conversion in regular sequence + SQ11: + description: 11th conversion in regular sequence + SQ10: + description: 10th conversion in regular sequence + +SQR4: + _modify: + SQ16: + description: 16th conversion in regular sequence + SQ15: + description: 15th conversion in regular sequence + +JSQR: + _modify: + JSQ4: + description: 4th conversion in the injected sequence + JSQ3: + description: 3rd conversion in the injected sequence + JSQ2: + description: 2nd conversion in the injected sequence + JSQ1: + description: 1st conversion in the injected sequence + JEXTEN: + description: External Trigger Enable and Polarity Selection for injected channels + JEXTSEL: + description: External Trigger Selection for injected group + JL: + description: Injected channel sequence length + +OFR?: + _modify: + SATEN: + description: Saturation enable + OFFSETPOS: + description: Positive offset + +AWD2CR: + _modify: + AWD2CH: + description: Analog watchdog 2 channel selection + +AWD3CR: + _modify: + AWD3CH: + description: Analog watchdog 3 channel selection + +CALFACT: + _modify: + CALFACT_D: + description: Calibration Factors in differential mode + CALFACT_S: + description: Calibration Factors In single-ended mode + +GCOMP: + _modify: + GCOMPCOEFF: + description: Gain compensation coefficient diff --git a/devices/patches/adc/h7.yaml b/devices/patches/adc/h7.yaml new file mode 100644 index 000000000..c3dd72506 --- /dev/null +++ b/devices/patches/adc/h7.yaml @@ -0,0 +1,13 @@ +# ADC fields that require modifications on H7 + +_modify: + LHTR1: + name: HTR1 +HTR1: + _modify: + LHTR1: + name: HTR1 +OFR?: + _modify: + SSATE: + description: Signed saturation enable diff --git a/devices/patches/adc/h7_1.yaml b/devices/patches/adc/h7_1.yaml new file mode 100644 index 000000000..6bdebdf67 --- /dev/null +++ b/devices/patches/adc/h7_1.yaml @@ -0,0 +1,24 @@ +CFGR2: + _modify: + OSR: + name: OSVR +SQR1: + _modify: + L3: + name: L +SMPR1: + _add: + SMP0: + description: ADC channel 0 sampling time selection + bitOffset: 0 + bitWidth: 3 + access: read-write +SMPR2: + _modify: + SMP19: + description: ADC channel 19 sampling time selection + +CFGR: + _modify: + AWDCH1CH: + name: AWD1CH diff --git a/devices/patches/adc/h7_2.yaml b/devices/patches/adc/h7_2.yaml new file mode 100644 index 000000000..82a16ecc9 --- /dev/null +++ b/devices/patches/adc/h7_2.yaml @@ -0,0 +1,30 @@ +DIFSEL: + _merge: + DIFSEL: DIFSEL* +CFGR2: + _modify: + OSR: + name: OSVR +DR: + _modify: + RDATA: + bitWidth: 32 +SQR1: + _modify: + L3: + name: L +SMPR1: + _add: + SMP0: + description: ADC channel 0 sampling time selection + bitWidth: 3 + bitOffset: 0 +SMPR2: + _modify: + SMP19: + description: ADC channel 19 sampling time selection + +CFGR: + _modify: + AWDCH1CH: + name: AWD1CH diff --git a/devices/patches/adc/h7_boost_rev_v.yaml b/devices/patches/adc/h7_boost_rev_v.yaml new file mode 100644 index 000000000..121051c43 --- /dev/null +++ b/devices/patches/adc/h7_boost_rev_v.yaml @@ -0,0 +1,8 @@ +# ADC fields different on H7 Rev V + +CR: + _modify: + # See RM0433 Section 24.6.3 + BOOST: + bitOffset: 8 + bitWidth: 2 diff --git a/devices/patches/adc/jdata.yaml b/devices/patches/adc/jdata.yaml new file mode 100644 index 000000000..c38d39270 --- /dev/null +++ b/devices/patches/adc/jdata.yaml @@ -0,0 +1,5 @@ +JDR?: + _modify: + JDATA?: + name: JDATA + description: Injected data diff --git a/devices/patches/adc/l1_smpr.yaml b/devices/patches/adc/l1_smpr.yaml new file mode 100644 index 000000000..456f35036 --- /dev/null +++ b/devices/patches/adc/l1_smpr.yaml @@ -0,0 +1,142 @@ +# Fix the poorly defined SMPR fields in L1xx + +SMPR0: + _delete: SMP + _add: + SMP31: + description: Channel 31 sampling time selection + bitWidth: 3 + bitOffset: 3 + SMP30: + description: Channel 30 sampling time selection + bitWidth: 3 + bitOffset: 0 +SMPR1: + _delete: SMP + _add: + SMP29: + description: Channel 29 sampling time selection + bitWidth: 3 + bitOffset: 27 + SMP28: + description: Channel 28 sampling time selection + bitWidth: 3 + bitOffset: 24 + SMP27: + description: Channel 27 sampling time selection + bitWidth: 3 + bitOffset: 21 + SMP26: + description: Channel 26 sampling time selection + bitWidth: 3 + bitOffset: 18 + SMP25: + description: Channel 25 sampling time selection + bitWidth: 3 + bitOffset: 15 + SMP24: + description: Channel 24 sampling time selection + bitWidth: 3 + bitOffset: 12 + SMP23: + description: Channel 23 sampling time selection + bitWidth: 3 + bitOffset: 9 + SMP22: + description: Channel 22 sampling time selection + bitWidth: 3 + bitOffset: 6 + SMP21: + description: Channel 21 sampling time selection + bitWidth: 3 + bitOffset: 3 + SMP20: + description: Channel 20 sampling time selection + bitWidth: 3 + bitOffset: 0 +SMPR2: + _delete: SMP + _add: + SMP19: + description: Channel 19 sampling time selection + bitWidth: 3 + bitOffset: 27 + SMP18: + description: Channel 18 sampling time selection + bitWidth: 3 + bitOffset: 24 + SMP17: + description: Channel 17 sampling time selection + bitWidth: 3 + bitOffset: 21 + SMP16: + description: Channel 16 sampling time selection + bitWidth: 3 + bitOffset: 18 + SMP15: + description: Channel 15 sampling time selection + bitWidth: 3 + bitOffset: 15 + SMP14: + description: Channel 14 sampling time selection + bitWidth: 3 + bitOffset: 12 + SMP13: + description: Channel 13 sampling time selection + bitWidth: 3 + bitOffset: 9 + SMP12: + description: Channel 12 sampling time selection + bitWidth: 3 + bitOffset: 6 + SMP11: + description: Channel 11 sampling time selection + bitWidth: 3 + bitOffset: 3 + SMP10: + description: Channel 10 sampling time selection + bitWidth: 3 + bitOffset: 0 +SMPR3: + _delete: SMP + _add: + SMP9: + description: Channel 9 sampling time selection + bitWidth: 3 + bitOffset: 27 + SMP8: + description: Channel 8 sampling time selection + bitWidth: 3 + bitOffset: 24 + SMP7: + description: Channel 7 sampling time selection + bitWidth: 3 + bitOffset: 21 + SMP6: + description: Channel 6 sampling time selection + bitWidth: 3 + bitOffset: 18 + SMP5: + description: Channel 5 sampling time selection + bitWidth: 3 + bitOffset: 15 + SMP4: + description: Channel 4 sampling time selection + bitWidth: 3 + bitOffset: 12 + SMP3: + description: Channel 3 sampling time selection + bitWidth: 3 + bitOffset: 9 + SMP2: + description: Channel 2 sampling time selection + bitWidth: 3 + bitOffset: 6 + SMP1: + description: Channel 1 sampling time selection + bitWidth: 3 + bitOffset: 3 + SMP0: + description: Channel 0 sampling time selection + bitWidth: 3 + bitOffset: 0 diff --git a/devices/patches/adc/l4+.yaml b/devices/patches/adc/l4+.yaml new file mode 100644 index 000000000..0abe24bc1 --- /dev/null +++ b/devices/patches/adc/l4+.yaml @@ -0,0 +1,12 @@ +_include: jdata.yaml + +CFGR: + _merge: EXTSEL* + + _modify: + AWDCH1CH: + name: AWD1CH + +DIFSEL: + _merge: + DIFSEL: DIFSEL* diff --git a/devices/patches/adc/l4+common.yaml b/devices/patches/adc/l4+common.yaml new file mode 100644 index 000000000..d62811395 --- /dev/null +++ b/devices/patches/adc/l4+common.yaml @@ -0,0 +1,13 @@ +CSR: + _modify: + "ADDRDY_MST,ADRDY_MST": + name: ADRDY_MST + +CCR: + _modify: + CH18SEL: + name: VBATEN + description: VBAT selection + CH17SEL: + name: VSENSEEN + description: Temperature sensor selection diff --git a/devices/patches/adc/l4_adc_common.yaml b/devices/patches/adc/l4_adc_common.yaml new file mode 100644 index 000000000..9c81e6c24 --- /dev/null +++ b/devices/patches/adc/l4_adc_common.yaml @@ -0,0 +1,166 @@ +_add: + # This SVD is missing the ADC_Common peripheral that most other parts with + # this ADC contain; consequently it's missing the CSR and CCR and CDR regs + # from RM0394. + ADC_Common: + description: ADC common registers + groupName: ADC_Common + baseAddress: 0x50040300 + addressBlock: + offset: 0 + size: 0x10 + usage: registers + registers: + CSR: + description: ADC common status register + addressOffset: 0x0 + access: read-only + resetValue: 0x00000000 + fields: + JQOVF_SLV: + description: Injected Context Queue Overflow flag of the slave ADC + bitOffset: 26 + bitWidth: 1 + AWD3_SLV: + description: Analog watchdog 3 flag of the slave ADC + bitOffset: 25 + bitWidth: 1 + AWD2_SLV: + description: Analog watchdog 2 flag of the slave ADC + bitOffset: 24 + bitWidth: 1 + AWD1_SLV: + description: Analog watchdog 1 flag of the slave ADC + bitOffset: 23 + bitWidth: 1 + JEOS_SLV: + description: End of injected sequence flag of the slave ADC + bitOffset: 22 + bitWidth: 1 + JEOC_SLV: + description: End of injected conversion flag of the slave ADC + bitOffset: 21 + bitWidth: 1 + OVR_SLV: + description: Overrun flag of the slave ADC + bitOffset: 20 + bitWidth: 1 + EOS_SLV: + description: End of regular sequence flag of the slave ADC + bitOffset: 19 + bitWidth: 1 + EOC_SLV: + description: End of regular conversion flag of the slave ADC + bitOffset: 18 + bitWidth: 1 + EOSMP_SLV: + description: End of Sampling phase flag of the slave ADC + bitOffset: 17 + bitWidth: 1 + ADRDY_SLV: + description: Slave ADC ready + bitOffset: 16 + bitWidth: 1 + + JQOVF_MST: + description: Injected Context Queue Overflow flag of the master ADC + bitOffset: 10 + bitWidth: 1 + AWD3_MST: + description: Analog watchdog 3 flag of the master ADC + bitOffset: 9 + bitWidth: 1 + AWD2_MST: + description: Analog watchdog 2 flag of the master ADC + bitOffset: 8 + bitWidth: 1 + AWD1_MST: + description: Analog watchdog 1 flag of the master ADC + bitOffset: 7 + bitWidth: 1 + JEOS_MST: + description: End of injected sequence flag of the master ADC + bitOffset: 6 + bitWidth: 1 + JEOC_MST: + description: End of injected conversion flag of the master ADC + bitOffset: 5 + bitWidth: 1 + OVR_MST: + description: Overrun flag of the master ADC + bitOffset: 4 + bitWidth: 1 + EOS_MST: + description: End of regular sequence flag of the master ADC + bitOffset: 3 + bitWidth: 1 + EOC_MST: + description: End of regular conversion flag of the master ADC + bitOffset: 2 + bitWidth: 1 + EOSMP_MST: + description: End of Sampling phase flag of the master ADC + bitOffset: 1 + bitWidth: 1 + ADRDY_MST: + description: master ADC ready + bitOffset: 0 + bitWidth: 1 + + CCR: + description: ADC common control register + addressOffset: 0x08 + access: read-write + resetValue: 0x00000000 + fields: + CH18SEL: + description: CH18 selection (Vbat) + bitOffset: 24 + bitWidth: 1 + CH17SEL: + description: CH17 selection (temperature) + bitOffset: 23 + bitWidth: 1 + VREFEN: + description: Vrefint enable + bitOffset: 22 + bitWidth: 1 + PRESC: + description: ADC prescaler + bitOffset: 18 + bitWidth: 4 + CKMODE: + description: ADC clock mode + bitOffset: 16 + bitWidth: 2 + MDMA: + description: Direct memory access mode for dual ADC mode + bitOffset: 14 + bitWidth: 2 + DMACFG: + description: DMA configuration (for dual ADC mode) + bitOffset: 13 + bitWidth: 1 + DELAY: + description: Delay between 2 sampling phases + bitOffset: 8 + bitWidth: 4 + DUAL: + description: Dual ADC mode selection + bitOffset: 0 + bitWidth: 5 + + CDR: + description: ADC common regular data register for dual mode + addressOffset: 0x0C + access: read-only + resetValue: 0x00000000 + fields: + RDATA_SLV: + description: Regular data of the slave ADC + bitOffset: 16 + bitWidth: 16 + RDATA_MST: + description: Regular data of the master ADC + bitOffset: 0 + bitWidth: 16 diff --git a/devices/patches/adc/l4_smpr.yaml b/devices/patches/adc/l4_smpr.yaml new file mode 100644 index 000000000..ef71b59b0 --- /dev/null +++ b/devices/patches/adc/l4_smpr.yaml @@ -0,0 +1,47 @@ +# Fix the poorly defined SMPR fields in STM32L4 + +SMPR1: + _add: + SMP0: + description: Channel 0 sampling time selection + bitWidth: 3 + bitOffset: 0 + _modify: + SMP1: + description: Channel 1 sampling time selection + SMP2: + description: Channel 2 sampling time selection + SMP3: + description: Channel 3 sampling time selection + SMP4: + description: Channel 4 sampling time selection + SMP5: + description: Channel 5 sampling time selection + SMP6: + description: Channel 6 sampling time selection + SMP7: + description: Channel 7 sampling time selection + SMP8: + description: Channel 8 sampling time selection + SMP9: + description: Channel 9 sampling time selection +SMPR2: + _modify: + SMP10: + description: Channel 10 sampling time selection + SMP11: + description: Channel 11 sampling time selection + SMP12: + description: Channel 12 sampling time selection + SMP13: + description: Channel 13 sampling time selection + SMP14: + description: Channel 14 sampling time selection + SMP15: + description: Channel 15 sampling time selection + SMP16: + description: Channel 16 sampling time selection + SMP17: + description: Channel 17 sampling time selection + SMP18: + description: Channel 18 sampling time selection diff --git a/devices/patches/adc/l4_sqr1.yaml b/devices/patches/adc/l4_sqr1.yaml new file mode 100644 index 000000000..3e5f77973 --- /dev/null +++ b/devices/patches/adc/l4_sqr1.yaml @@ -0,0 +1,7 @@ +# Rename the L3 field to L to match RM0394 + +SQR1: + _modify: + L3: + name: L + description: Regular channel sequence length diff --git a/devices/patches/adc/multi.yaml b/devices/patches/adc/multi.yaml new file mode 100644 index 000000000..0065cd0e4 --- /dev/null +++ b/devices/patches/adc/multi.yaml @@ -0,0 +1,5 @@ +CCR: + _modify: + # This appears to have the wrong name in every single SVD. + MULT: + name: MULTI diff --git a/devices/patches/adc/offset.yaml b/devices/patches/adc/offset.yaml new file mode 100644 index 000000000..af9c9fad4 --- /dev/null +++ b/devices/patches/adc/offset.yaml @@ -0,0 +1,8 @@ +OFR?: + _modify: + OFFSET?_CH: + name: OFFSET_CH + description: Channel selection for the data offset X + OFFSET?: + name: OFFSET + description: Data offset X for the channel programmed into bits OFFSET_CH diff --git a/devices/patches/adc/offset_en.yaml b/devices/patches/adc/offset_en.yaml new file mode 100644 index 000000000..e477ce8d4 --- /dev/null +++ b/devices/patches/adc/offset_en.yaml @@ -0,0 +1,7 @@ +_include: offset.yaml + +OFR?: + _modify: + OFFSET?_EN: + name: OFFSET_EN + description: Offset X Enable diff --git a/devices/patches/adc/smpx_17.yaml b/devices/patches/adc/smpx_17.yaml new file mode 100644 index 000000000..dc2517425 --- /dev/null +++ b/devices/patches/adc/smpx_17.yaml @@ -0,0 +1,78 @@ +SMPR1: + _delete: SMPx_x + _add: + SMP17: + description: Channel 17 sampling time selection + bitWidth: 3 + bitOffset: 21 + SMP16: + description: Channel 16 sampling time selection + bitWidth: 3 + bitOffset: 18 + SMP15: + description: Channel 15 sampling time selection + bitWidth: 3 + bitOffset: 15 + SMP14: + description: Channel 14 sampling time selection + bitWidth: 3 + bitOffset: 12 + SMP13: + description: Channel 13 sampling time selection + bitWidth: 3 + bitOffset: 9 + SMP12: + description: Channel 12 sampling time selection + bitWidth: 3 + bitOffset: 6 + SMP11: + description: Channel 11 sampling time selection + bitWidth: 3 + bitOffset: 3 + SMP10: + description: Channel 10 sampling time selection + bitWidth: 3 + bitOffset: 0 +SMPR2: + _delete: SMPx_x + _add: + SMP9: + description: Channel 9 sampling time selection + bitWidth: 3 + bitOffset: 27 + SMP8: + description: Channel 8 sampling time selection + bitWidth: 3 + bitOffset: 24 + SMP7: + description: Channel 7 sampling time selection + bitWidth: 3 + bitOffset: 21 + SMP6: + description: Channel 6 sampling time selection + bitWidth: 3 + bitOffset: 18 + SMP5: + description: Channel 5 sampling time selection + bitWidth: 3 + bitOffset: 15 + SMP4: + description: Channel 4 sampling time selection + bitWidth: 3 + bitOffset: 12 + SMP3: + description: Channel 3 sampling time selection + bitWidth: 3 + bitOffset: 9 + SMP2: + description: Channel 2 sampling time selection + bitWidth: 3 + bitOffset: 6 + SMP1: + description: Channel 1 sampling time selection + bitWidth: 3 + bitOffset: 3 + SMP0: + description: Channel 0 sampling time selection + bitWidth: 3 + bitOffset: 0 diff --git a/devices/patches/adc/smpx_18.yaml b/devices/patches/adc/smpx_18.yaml new file mode 100644 index 000000000..e80f1b982 --- /dev/null +++ b/devices/patches/adc/smpx_18.yaml @@ -0,0 +1,8 @@ +_include: smpx_17.yaml + +SMPR1: + _add: + SMP18: + description: Channel 18 sampling time selection + bitWidth: 3 + bitOffset: 24 diff --git a/devices/patches/adc/split.yaml b/devices/patches/adc/split.yaml new file mode 100644 index 000000000..c75271c80 --- /dev/null +++ b/devices/patches/adc/split.yaml @@ -0,0 +1,6 @@ +AWD2CR: + _split: AWD2CH +AWD3CR: + _split: AWD3CH +DIFSEL: + _split: DIFSEL* diff --git a/devices/patches/adc/u5_access.yaml b/devices/patches/adc/u5_access.yaml new file mode 100644 index 000000000..0a3f761e4 --- /dev/null +++ b/devices/patches/adc/u5_access.yaml @@ -0,0 +1,4 @@ +CR: + _modify: + ADCAL,ADSTP,JADSTP,ADSTART,JADSTART,ADDIS,ADEN: + access: read-write diff --git a/devices/patches/adc/u5_vsensesel.yaml b/devices/patches/adc/u5_vsensesel.yaml new file mode 100644 index 000000000..cc3d47679 --- /dev/null +++ b/devices/patches/adc/u5_vsensesel.yaml @@ -0,0 +1,6 @@ +# Some U5 devices have the VSENSESEL field incorrectly named as TSEN + +CCR: + _modify: + TSEN: + name: VSENSESEL diff --git a/devices/patches/adc/wb_adc_common.yaml b/devices/patches/adc/wb_adc_common.yaml new file mode 100644 index 000000000..f39acbd23 --- /dev/null +++ b/devices/patches/adc/wb_adc_common.yaml @@ -0,0 +1,91 @@ +# Not quite the same as L4 ADC_Common, as there's no slave ADC on WB. +_add: + # This SVD is missing the ADC_Common peripheral that most other parts with + # this ADC contain; consequently it's missing the CSR and CCR regs + # from RM0434. + ADC_Common: + description: ADC common registers + groupName: ADC_Common + baseAddress: 0x50040300 + addressBlock: + offset: 0 + size: 0xc + usage: registers + registers: + CSR: + description: ADC common status register + addressOffset: 0x0 + access: read-only + resetValue: 0x00000000 + fields: + JQOVF_MST: + description: Injected Context Queue Overflow flag of the master ADC + bitOffset: 10 + bitWidth: 1 + AWD3_MST: + description: Analog watchdog 3 flag of the master ADC + bitOffset: 9 + bitWidth: 1 + AWD2_MST: + description: Analog watchdog 2 flag of the master ADC + bitOffset: 8 + bitWidth: 1 + AWD1_MST: + description: Analog watchdog 1 flag of the master ADC + bitOffset: 7 + bitWidth: 1 + JEOS_MST: + description: End of injected sequence flag of the master ADC + bitOffset: 6 + bitWidth: 1 + JEOC_MST: + description: End of injected conversion flag of the master ADC + bitOffset: 5 + bitWidth: 1 + OVR_MST: + description: Overrun flag of the master ADC + bitOffset: 4 + bitWidth: 1 + EOS_MST: + description: End of regular sequence flag of the master ADC + bitOffset: 3 + bitWidth: 1 + EOC_MST: + description: End of regular conversion flag of the master ADC + bitOffset: 2 + bitWidth: 1 + EOSMP_MST: + description: End of Sampling phase flag of the master ADC + bitOffset: 1 + bitWidth: 1 + ADRDY_MST: + description: master ADC ready + bitOffset: 0 + bitWidth: 1 + + CCR: + description: ADC common control register + addressOffset: 0x08 + access: read-write + resetValue: 0x00000000 + fields: + CH18SEL: + description: CH18 selection (Vbat) + bitOffset: 24 + bitWidth: 1 + CH17SEL: + description: CH17 selection (temperature) + bitOffset: 23 + bitWidth: 1 + VREFEN: + description: Vrefint enable + bitOffset: 22 + bitWidth: 1 + PRESC: + description: ADC prescaler + bitOffset: 18 + bitWidth: 4 + CKMODE: + description: ADC clock mode + bitOffset: 16 + bitWidth: 2 diff --git a/devices/patches/adc/wl.yaml b/devices/patches/adc/wl.yaml new file mode 100644 index 000000000..16c5074b6 --- /dev/null +++ b/devices/patches/adc/wl.yaml @@ -0,0 +1,14 @@ +CCR: + _merge: PRESC* +CFGR2: + _merge: + - OVSS* + - OVSR* +SMPR: + _split: SMPSEL +AWD2CR: + _split: AWD2CH +AWD3CR: + _split: AWD3CH +CHSELR0: + _split: CHSEL diff --git a/devices/patches/aes/fields.yaml b/devices/patches/aes/fields.yaml new file mode 100644 index 000000000..d4b53e856 --- /dev/null +++ b/devices/patches/aes/fields.yaml @@ -0,0 +1,20 @@ +DINR: + _modify: + "DINR,AES_DINR": + name: DIN +DOUTR: + _modify: + "DOUTR,AES_DOUTR": + name: DOUT +KEYR?: + _modify: + "KEYR?,AES_KEYR?,KEY": + name: KEY +IVR?: + _modify: + "IVR?,AES_IVR?": + name: IVI +"?~SUSP?R": + _modify: + "SUSP?R,AES_SUSP?R,SUSP": + name: SUSP diff --git a/devices/patches/aes/l4+.yaml b/devices/patches/aes/l4+.yaml new file mode 100644 index 000000000..114e0b53d --- /dev/null +++ b/devices/patches/aes/l4+.yaml @@ -0,0 +1,9 @@ +_include: + - l4.yaml + +CR: + _add: + NPBLB: + description: Number of padding bytes in last block + bitOffset: 20 + bitWidth: 4 diff --git a/devices/patches/aes/l4.yaml b/devices/patches/aes/l4.yaml new file mode 100644 index 000000000..f0ad3d4ed --- /dev/null +++ b/devices/patches/aes/l4.yaml @@ -0,0 +1,155 @@ +_add: + KEYR4: + description: key register 4 + addressOffset: 0x30 + size: 32 + access: read-write + resetValue: 0x0 + fields: + KEY: + description: Cryptographic key, bits [159:128] + bitOffset: 0 + bitWidth: 32 + KEYR5: + description: key register 5 + addressOffset: 0x34 + size: 32 + access: read-write + resetValue: 0x0 + fields: + KEY: + description: Cryptographic key, bits [191:160] + bitOffset: 0 + bitWidth: 32 + KEYR6: + description: key register 6 + addressOffset: 0x38 + size: 32 + access: read-write + resetValue: 0x0 + fields: + KEY: + description: Cryptographic key, bits [223:192] + bitOffset: 0 + bitWidth: 32 + KEYR7: + description: key register 7 + addressOffset: 0x3C + size: 32 + access: read-write + resetValue: 0x0 + fields: + KEY: + description: Cryptographic key, bits [255:224] + bitOffset: 0 + bitWidth: 32 + SUSP0R: + description: suspend registers + addressOffset: 0x40 + size: 32 + access: read-write + resetValue: 0x0 + fields: + SUSP: + description: AES suspend + bitOffset: 0 + bitWidth: 32 + SUSP1R: + description: suspend registers + addressOffset: 0x44 + size: 32 + access: read-write + resetValue: 0x0 + fields: + SUSP: + description: AES suspend + bitOffset: 0 + bitWidth: 32 + SUSP2R: + description: suspend registers + addressOffset: 0x48 + size: 32 + access: read-write + resetValue: 0x0 + fields: + SUSP: + description: AES suspend + bitOffset: 0 + bitWidth: 32 + SUSP3R: + description: suspend registers + addressOffset: 0x4C + size: 32 + access: read-write + resetValue: 0x0 + fields: + SUSP: + description: AES suspend + bitOffset: 0 + bitWidth: 32 + SUSP4R: + description: suspend registers + addressOffset: 0x50 + size: 32 + access: read-write + resetValue: 0x0 + fields: + SUSP: + description: AES suspend + bitOffset: 0 + bitWidth: 32 + SUSP5R: + description: suspend registers + addressOffset: 0x54 + size: 32 + access: read-write + resetValue: 0x0 + fields: + SUSP: + description: AES suspend + bitOffset: 0 + bitWidth: 32 + SUSP6R: + description: suspend registers + addressOffset: 0x58 + size: 32 + access: read-write + resetValue: 0x0 + fields: + SUSP: + description: AES suspend + bitOffset: 0 + bitWidth: 32 + SUSP7R: + description: suspend registers + addressOffset: 0x5C + size: 32 + access: read-write + resetValue: 0x0 + fields: + SUSP: + description: AES suspend + bitOffset: 0 + bitWidth: 32 + +CR: + _add: + KEYSIZE: + description: Key size selection + bitOffset: 18 + bitWidth: 1 + CHMOD2: + description: Chaining mode selection, bit [2] + bitOffset: 16 + bitWidth: 1 + GCMPH: + description: GCM or CCM phase selection + bitOffset: 13 + bitWidth: 2 + +SR: + _add: + BUSY: + description: Busy + bitOffset: 3 + bitWidth: 1 diff --git a/devices/patches/bkp/bkp.yaml b/devices/patches/bkp/bkp.yaml new file mode 100644 index 000000000..43d4c8c75 --- /dev/null +++ b/devices/patches/bkp/bkp.yaml @@ -0,0 +1,3 @@ +_modify: + BKP: + baseAddress: "0x40006C04" diff --git a/devices/patches/can/l4x3_missing_regs.yaml b/devices/patches/can/l4x3_missing_regs.yaml new file mode 100644 index 000000000..d802d5108 --- /dev/null +++ b/devices/patches/can/l4x3_missing_regs.yaml @@ -0,0 +1,269 @@ +_add: + FMR: + displayName: FMR + description: filter master register + addressOffset: 512 + size: 32 + access: read-write + resetValue: 706481665 + fields: + FINIT: + description: Filter initialization mode + bitOffset: 0 + bitWidth: 1 + FM1R: + displayName: FM1R + description: filter mode register + addressOffset: 516 + size: 32 + access: read-write + resetValue: 0 + fields: + FBM0: + description: Filter mode + bitOffset: 0 + bitWidth: 1 + FBM1: + description: Filter mode + bitOffset: 1 + bitWidth: 1 + FBM2: + description: Filter mode + bitOffset: 2 + bitWidth: 1 + FBM3: + description: Filter mode + bitOffset: 3 + bitWidth: 1 + FBM4: + description: Filter mode + bitOffset: 4 + bitWidth: 1 + FBM5: + description: Filter mode + bitOffset: 5 + bitWidth: 1 + FBM6: + description: Filter mode + bitOffset: 6 + bitWidth: 1 + FBM7: + description: Filter mode + bitOffset: 7 + bitWidth: 1 + FBM8: + description: Filter mode + bitOffset: 8 + bitWidth: 1 + FBM9: + description: Filter mode + bitOffset: 9 + bitWidth: 1 + FBM10: + description: Filter mode + bitOffset: 10 + bitWidth: 1 + FBM11: + description: Filter mode + bitOffset: 11 + bitWidth: 1 + FBM12: + description: Filter mode + bitOffset: 12 + bitWidth: 1 + FBM13: + description: Filter mode + bitOffset: 13 + bitWidth: 1 + FS1R: + displayName: FS1R + description: filter scale register + addressOffset: 524 + size: 32 + access: read-write + resetValue: 0 + fields: + FSC0: + description: Filter scale configuration + bitOffset: 0 + bitWidth: 1 + FSC1: + description: Filter scale configuration + bitOffset: 1 + bitWidth: 1 + FSC2: + description: Filter scale configuration + bitOffset: 2 + bitWidth: 1 + FSC3: + description: Filter scale configuration + bitOffset: 3 + bitWidth: 1 + FSC4: + description: Filter scale configuration + bitOffset: 4 + bitWidth: 1 + FSC5: + description: Filter scale configuration + bitOffset: 5 + bitWidth: 1 + FSC6: + description: Filter scale configuration + bitOffset: 6 + bitWidth: 1 + FSC7: + description: Filter scale configuration + bitOffset: 7 + bitWidth: 1 + FSC8: + description: Filter scale configuration + bitOffset: 8 + bitWidth: 1 + FSC9: + description: Filter scale configuration + bitOffset: 9 + bitWidth: 1 + FSC10: + description: Filter scale configuration + bitOffset: 10 + bitWidth: 1 + FSC11: + description: Filter scale configuration + bitOffset: 11 + bitWidth: 1 + FSC12: + description: Filter scale configuration + bitOffset: 12 + bitWidth: 1 + FSC13: + description: Filter scale configuration + bitOffset: 13 + bitWidth: 1 + FFA1R: + displayName: FFA1R + description: "filter FIFO assignment\n register" + addressOffset: 532 + size: 32 + access: read-write + resetValue: 0 + fields: + FFA0: + description: Filter FIFO assignment for filter 0 + bitOffset: 0 + bitWidth: 1 + FFA1: + description: Filter FIFO assignment for filter 1 + bitOffset: 1 + bitWidth: 1 + FFA2: + description: Filter FIFO assignment for filter 2 + bitOffset: 2 + bitWidth: 1 + FFA3: + description: Filter FIFO assignment for filter 3 + bitOffset: 3 + bitWidth: 1 + FFA4: + description: Filter FIFO assignment for filter 4 + bitOffset: 4 + bitWidth: 1 + FFA5: + description: Filter FIFO assignment for filter 5 + bitOffset: 5 + bitWidth: 1 + FFA6: + description: Filter FIFO assignment for filter 6 + bitOffset: 6 + bitWidth: 1 + FFA7: + description: Filter FIFO assignment for filter 7 + bitOffset: 7 + bitWidth: 1 + FFA8: + description: Filter FIFO assignment for filter 8 + bitOffset: 8 + bitWidth: 1 + FFA9: + description: Filter FIFO assignment for filter 9 + bitOffset: 9 + bitWidth: 1 + FFA10: + description: Filter FIFO assignment for filter 10 + bitOffset: 10 + bitWidth: 1 + FFA11: + description: Filter FIFO assignment for filter 11 + bitOffset: 11 + bitWidth: 1 + FFA12: + description: Filter FIFO assignment for filter 12 + bitOffset: 12 + bitWidth: 1 + FFA13: + description: Filter FIFO assignment for filter 13 + bitOffset: 13 + bitWidth: 1 + FA1R: + displayName: FA1R + description: filter activation register + addressOffset: 540 + size: 32 + access: read-write + resetValue: 0 + fields: + FACT0: + description: Filter active + bitOffset: 0 + bitWidth: 1 + FACT1: + description: Filter active + bitOffset: 1 + bitWidth: 1 + FACT2: + description: Filter active + bitOffset: 2 + bitWidth: 1 + FACT3: + description: Filter active + bitOffset: 3 + bitWidth: 1 + FACT4: + description: Filter active + bitOffset: 4 + bitWidth: 1 + FACT5: + description: Filter active + bitOffset: 5 + bitWidth: 1 + FACT6: + description: Filter active + bitOffset: 6 + bitWidth: 1 + FACT7: + description: Filter active + bitOffset: 7 + bitWidth: 1 + FACT8: + description: Filter active + bitOffset: 8 + bitWidth: 1 + FACT9: + description: Filter active + bitOffset: 9 + bitWidth: 1 + FACT10: + description: Filter active + bitOffset: 10 + bitWidth: 1 + FACT11: + description: Filter active + bitOffset: 11 + bitWidth: 1 + FACT12: + description: Filter active + bitOffset: 12 + bitWidth: 1 + FACT13: + description: Filter active + bitOffset: 13 + bitWidth: 1 diff --git a/devices/patches/cec/cfgr.yaml b/devices/patches/cec/cfgr.yaml new file mode 100644 index 000000000..1701194bd --- /dev/null +++ b/devices/patches/cec/cfgr.yaml @@ -0,0 +1,45 @@ +_delete: CFGR +_add: + CFGR: + description: configuration register + addressOffset: 0x4 + size: 0x20 + access: read-write + resetValue: 0x0 + fields: + SFT: + bitOffset: 0 + bitWidth: 3 + description: Signal Free Time + RXTOL: + bitOffset: 3 + bitWidth: 1 + description: Rx-Tolerance + BRESTP: + bitOffset: 4 + bitWidth: 1 + description: Rx-stop on bit rising error + BREGEN: + bitOffset: 5 + bitWidth: 1 + description: Generate error-bit on bit rising error + LBPEGEN: + bitOffset: 6 + bitWidth: 1 + description: Generate Error-Bit on Long Bit Period Error + BRDNOGEN: + bitOffset: 7 + bitWidth: 1 + description: Avoid Error-Bit Generation in Broadcast + SFTOP: + bitOffset: 8 + bitWidth: 1 + description: SFT Option Bit + OAR: + bitOffset: 16 + bitWidth: 15 + description: Own Address + LSTN: + bitOffset: 31 + bitWidth: 1 + description: Listen mode diff --git a/devices/patches/comp/f0_common.yaml b/devices/patches/comp/f0_common.yaml new file mode 100644 index 000000000..d14ff8bd0 --- /dev/null +++ b/devices/patches/comp/f0_common.yaml @@ -0,0 +1,100 @@ +_add: + COMP: + description: General purpose comparators + baseAddress: 0x40010000 + addressBlock: + offset: 0 + size: 0x400 + usage: registers + registers: + CSR: + description: control and status register + addressOffset: 0x1C + size: 0x20 + resetValue: 0x00000000 + fields: + COMP1EN: + description: Comparator 1 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + COMP1MODE: + description: Comparator 1 mode + bitOffset: 2 + bitWidth: 2 + access: read-write + COMP1INSEL: + description: Comparator 1 inverting input selection + bitOffset: 4 + bitWidth: 3 + access: read-write + COMP1OUTSEL: + description: Comparator 1 output selection + bitOffset: 8 + bitWidth: 3 + access: read-write + COMP1POL: + description: Comparator 1 output polarity + bitOffset: 11 + bitWidth: 1 + access: read-write + COMP1HYST: + description: Comparator 1 hysteresis + bitOffset: 12 + bitWidth: 2 + access: read-write + COMP1OUT: + description: Comparator 1 output + bitOffset: 14 + bitWidth: 1 + access: read-only + COMP1LOCK: + description: Comparator 1 lock + bitOffset: 15 + bitWidth: 1 + access: read-write + COMP2EN: + description: Comparator 2 enable + bitOffset: 16 + bitWidth: 1 + access: read-write + COMP2MODE: + description: Comparator 2 mode + bitOffset: 18 + bitWidth: 2 + access: read-write + COMP2INSEL: + description: Comparator 2 inverting input selection + bitOffset: 20 + bitWidth: 3 + access: read-write + WNDWEN: + description: Window mode enable + bitOffset: 23 + bitWidth: 1 + access: read-write + COMP2OUTSEL: + description: Comparator 2 output selection + bitOffset: 24 + bitWidth: 3 + access: read-write + COMP2POL: + description: Comparator 2 output polarity + bitOffset: 27 + bitWidth: 1 + access: read-write + COMP2HYST: + description: Comparator 2 hysteresis + bitOffset: 28 + bitWidth: 2 + access: read-write + COMP2OUT: + description: Comparator 2 output + bitOffset: 30 + bitWidth: 1 + access: read-only + COMP2LOCK: + description: Comparator 2 lock + bitOffset: 31 + bitWidth: 1 + access: read-write diff --git a/devices/common_patches/f3_comp1234567.yaml b/devices/patches/comp/f3_comp1234567.yaml similarity index 100% rename from devices/common_patches/f3_comp1234567.yaml rename to devices/patches/comp/f3_comp1234567.yaml diff --git a/devices/common_patches/f3_comp1246.yaml b/devices/patches/comp/f3_comp1246.yaml similarity index 100% rename from devices/common_patches/f3_comp1246.yaml rename to devices/patches/comp/f3_comp1246.yaml diff --git a/devices/common_patches/f3_comp246.yaml b/devices/patches/comp/f3_comp246.yaml similarity index 100% rename from devices/common_patches/f3_comp246.yaml rename to devices/patches/comp/f3_comp246.yaml diff --git a/devices/common_patches/f3_comp246_inmsel3.yaml b/devices/patches/comp/f3_comp246_inmsel3.yaml similarity index 100% rename from devices/common_patches/f3_comp246_inmsel3.yaml rename to devices/patches/comp/f3_comp246_inmsel3.yaml diff --git a/devices/common_patches/f3_comp2_inp_dac.yaml b/devices/patches/comp/f3_comp2_inp_dac.yaml similarity index 100% rename from devices/common_patches/f3_comp2_inp_dac.yaml rename to devices/patches/comp/f3_comp2_inp_dac.yaml diff --git a/devices/patches/comp/g4.yaml b/devices/patches/comp/g4.yaml new file mode 100644 index 000000000..603f23d1f --- /dev/null +++ b/devices/patches/comp/g4.yaml @@ -0,0 +1,11 @@ +COMP: + _copy: + C5CSR: + _from: COMP_C1CSR + addressOffset: 0x10 + C6CSR: + _from: COMP_C1CSR + addressOffset: 0x14 + C7CSR: + _from: COMP_C1CSR + addressOffset: 0x18 diff --git a/devices/patches/comp/l4xx_comp_reg_rename.yaml b/devices/patches/comp/l4xx_comp_reg_rename.yaml new file mode 100644 index 000000000..2a2aea16d --- /dev/null +++ b/devices/patches/comp/l4xx_comp_reg_rename.yaml @@ -0,0 +1,5 @@ +COMP: + COMP1_CSR: + _strip: COMP1_ + COMP2_CSR: + _strip: COMP2_ diff --git a/devices/patches/cordic/g4.yaml b/devices/patches/cordic/g4.yaml new file mode 100644 index 000000000..3ac8c9e9a --- /dev/null +++ b/devices/patches/cordic/g4.yaml @@ -0,0 +1,11 @@ +CSR: + _modify: + PRECISION: + description: Precision (number of iterations/cycles) required + SCALE: + description: Scaling factor (2^-n for arguments, 2^n for results) +_modify: + WDATA: + description: CORDIC argument register + RDATA: + description: CORDIC result register diff --git a/devices/patches/crc/add_dr8.yaml b/devices/patches/crc/add_dr8.yaml new file mode 100644 index 000000000..989a5a682 --- /dev/null +++ b/devices/patches/crc/add_dr8.yaml @@ -0,0 +1,25 @@ +_add: + DR8: + description: Data register - byte sized + addressOffset: 0x0 + size: 0x8 + access: read-write + resetValue: 0xFF + alternateRegister: DR + fields: + DR8: + description: Data register bits + bitOffset: 0 + bitWidth: 8 + DR16: + description: Data register - half-word sized + addressOffset: 0x0 + size: 0x10 + access: read-write + resetValue: 0xFFFF + alternateRegister: DR + fields: + DR16: + description: Data register bits + bitOffset: 0 + bitWidth: 16 diff --git a/devices/patches/crc/crc_add_pol.yaml b/devices/patches/crc/crc_add_pol.yaml new file mode 100644 index 000000000..e66c494ba --- /dev/null +++ b/devices/patches/crc/crc_add_pol.yaml @@ -0,0 +1,14 @@ +# The SVD is missing the programmable polynomial register "POL" +_add: + POL: + displayName: POL + description: CRC polynomial + addressOffset: 0x14 + size: 0x20 + access: read-write + resetValue: 0x04C11DB7 + fields: + POL: + description: Programmable polynomial + bitOffset: 0 + bitWidth: 32 diff --git a/devices/patches/crc/crc_rename_init.yaml b/devices/patches/crc/crc_rename_init.yaml new file mode 100644 index 000000000..4581145a9 --- /dev/null +++ b/devices/patches/crc/crc_rename_init.yaml @@ -0,0 +1,4 @@ +INIT: + _modify: + CRC_INIT: + name: INIT diff --git a/devices/patches/crc/crc_rename_pol.yaml b/devices/patches/crc/crc_rename_pol.yaml new file mode 100644 index 000000000..50a67e1f0 --- /dev/null +++ b/devices/patches/crc/crc_rename_pol.yaml @@ -0,0 +1,4 @@ +POL: + _modify: + Polynomialcoefficients: + name: POL diff --git a/devices/patches/crc/f0_init_addr_fix.yaml b/devices/patches/crc/f0_init_addr_fix.yaml new file mode 100644 index 000000000..161a55d91 --- /dev/null +++ b/devices/patches/crc/f0_init_addr_fix.yaml @@ -0,0 +1,5 @@ +# Corrects the address of the INIT register of the CRC peripheral + +_modify: + INIT: + addressOffset: 0x10 diff --git a/devices/patches/crc/f7_polysize_rev_in_rev_out.yaml b/devices/patches/crc/f7_polysize_rev_in_rev_out.yaml new file mode 100644 index 000000000..f3189e51e --- /dev/null +++ b/devices/patches/crc/f7_polysize_rev_in_rev_out.yaml @@ -0,0 +1,22 @@ +# The SVD calls the RESET field "CR", and misses some fields, fix per RM0410 +CR: + _modify: + CR: + name: RESET + description: RESET bit + _add: + REV_OUT: + description: Reverse output data + bitOffset: 7 + bitWidth: 1 + access: read-write + REV_IN: + description: Reverse input data + bitOffset: 5 + bitWidth: 2 + access: read-write + POLYSIZE: + description: Polynomial size + bitOffset: 3 + bitWidth: 2 + access: read-write diff --git a/devices/patches/crc/h7_addr_fix.yaml b/devices/patches/crc/h7_addr_fix.yaml new file mode 100644 index 000000000..2e224d09e --- /dev/null +++ b/devices/patches/crc/h7_addr_fix.yaml @@ -0,0 +1,7 @@ +# Corrects the addresses of the INIT and POL registers of the CRC peripheral + +_modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 diff --git a/devices/patches/crc/idr.yaml b/devices/patches/crc/idr.yaml new file mode 100644 index 000000000..e2b23e1e5 --- /dev/null +++ b/devices/patches/crc/idr.yaml @@ -0,0 +1,5 @@ +IDR: + _modify: + GPDR: + name: IDR + description: General-purpose 32-bit data register bits diff --git a/devices/patches/cryp/merge_fields.yaml b/devices/patches/cryp/merge_fields.yaml new file mode 100644 index 000000000..10a5ae38f --- /dev/null +++ b/devices/patches/cryp/merge_fields.yaml @@ -0,0 +1,9 @@ +# Merge the hundreds of individual bit fields into single fields for the +# crypt key/iv registers. + +"K[0123][LR]R": + _merge: + - b* +"IV[01][LR]R": + _merge: + - IV* diff --git a/devices/patches/dac/dac_l4+.yaml b/devices/patches/dac/dac_l4+.yaml new file mode 100644 index 000000000..6177508ac --- /dev/null +++ b/devices/patches/dac/dac_l4+.yaml @@ -0,0 +1,21 @@ +_modify: + CR: + description: DAC control register + +CR: + _modify: + TSEL2: + bitOffset: 18 + bitWidth: 4 + TEN2: + bitOffset: 17 + TSEL1: + bitOffset: 2 + bitWidth: 4 + TEN1: + bitOffset: 1 + _add: + HFSEL: + description: High frequency interface mode enable + bitOffset: 15 + bitWidth: 1 diff --git a/devices/patches/dac/tsel_4bit.yaml b/devices/patches/dac/tsel_4bit.yaml new file mode 100644 index 000000000..36e768a57 --- /dev/null +++ b/devices/patches/dac/tsel_4bit.yaml @@ -0,0 +1,4 @@ +CR: + _modify: + TSEL?: + bitWidth: 4 diff --git a/devices/patches/dbgmcu/dbgmcu.yaml b/devices/patches/dbgmcu/dbgmcu.yaml new file mode 100644 index 000000000..a9176f6ff --- /dev/null +++ b/devices/patches/dbgmcu/dbgmcu.yaml @@ -0,0 +1,9 @@ +_include: + - rename.yaml + +DBGMCU: + _strip: DBGMCU_ + APB1_FZ: + _modify: + DBG_IWDEG_STOP: + name: DBG_IWDG_STOP diff --git a/devices/patches/dbgmcu/f3.yaml b/devices/patches/dbgmcu/f3.yaml new file mode 100644 index 000000000..a9fb6d618 --- /dev/null +++ b/devices/patches/dbgmcu/f3.yaml @@ -0,0 +1,6 @@ +DBGMCU: + _modify: + APB1FZ: + name: APB1_FZ + APB2FZ: + name: APB2_FZ diff --git a/devices/common_patches/f7_dbgmcu.yaml b/devices/patches/dbgmcu/f7.yaml similarity index 100% rename from devices/common_patches/f7_dbgmcu.yaml rename to devices/patches/dbgmcu/f7.yaml diff --git a/devices/patches/dbgmcu/h7.yaml b/devices/patches/dbgmcu/h7.yaml new file mode 100644 index 000000000..cc443ed41 --- /dev/null +++ b/devices/patches/dbgmcu/h7.yaml @@ -0,0 +1,11 @@ +# Patches for H7 DBGMCU periperal + +# Remove registers not present in RM0433 Rev 7 +DBGMCU: + CR: + _delete: + - DBGSTBY_D2 + - DBGSTOP_D2 + - DBGSLEEP_D2 + - DBGSTOP_D3 + - DBGSTBY_D3 diff --git a/devices/patches/dbgmcu/l4+.yaml b/devices/patches/dbgmcu/l4+.yaml new file mode 100644 index 000000000..bf130b190 --- /dev/null +++ b/devices/patches/dbgmcu/l4+.yaml @@ -0,0 +1,15 @@ +DBGMCU: + APB1FZR1: + _modify: + DBG_LPTIMER_STOP: + name: DBG_LPTIM1_STOP + + DBG_CAN_STOP: + name: DBG_CAN1_STOP + + APB1FZR2: + _add: + DBG_I2C4_STOP: + description: I2C4 SMBUS timeout counter stopped when core is halted + bitOffset: 1 + bitWidth: 1 diff --git a/devices/patches/dbgmcu/l4_apb_fzr_rename.yaml b/devices/patches/dbgmcu/l4_apb_fzr_rename.yaml new file mode 100644 index 000000000..4493a2428 --- /dev/null +++ b/devices/patches/dbgmcu/l4_apb_fzr_rename.yaml @@ -0,0 +1,8 @@ +DBGMCU: + _modify: + APB1_FZR1: + name: APB1FZR1 + APB1_FZR2: + name: APB1FZR2 + APB2_FZR: + name: APB2FZR diff --git a/devices/common_patches/dbgmcu_rename.yaml b/devices/patches/dbgmcu/rename.yaml similarity index 100% rename from devices/common_patches/dbgmcu_rename.yaml rename to devices/patches/dbgmcu/rename.yaml diff --git a/devices/patches/dcmi/byte.yaml b/devices/patches/dcmi/byte.yaml new file mode 100644 index 000000000..62f68e04c --- /dev/null +++ b/devices/patches/dcmi/byte.yaml @@ -0,0 +1,10 @@ +DR: + _modify: + Byte0: + name: BYTE0 + Byte1: + name: BYTE1 + Byte2: + name: BYTE2 + Byte3: + name: BYTE3 diff --git a/devices/patches/dcmi/dcmi.yaml b/devices/patches/dcmi/dcmi.yaml new file mode 100644 index 000000000..436feee75 --- /dev/null +++ b/devices/patches/dcmi/dcmi.yaml @@ -0,0 +1,5 @@ +_modify: + _interrupts: + DCMI: + name: DCMI_PSSI + description: DCMI/PSSI global interrupt diff --git a/devices/patches/dfsdm/dfsdm_v1.yaml b/devices/patches/dfsdm/dfsdm_v1.yaml new file mode 100644 index 000000000..d94b8aede --- /dev/null +++ b/devices/patches/dfsdm/dfsdm_v1.yaml @@ -0,0 +1,19 @@ +_include: + - split.yaml + +# Add fake DFSDMEN and CKOUTSRC fields to channel registers beyond 0 +# to permit them to be clustered. +CH[1-7]CFGR1: + _add: + DFSDMEN: + description: DFSDMEN (CH0CFGR1 only) + bitOffset: 31 + bitWidth: 1 + CKOUTSRC: + description: CKOUTSRC (CH0CFGR1 only) + bitOffset: 30 + bitWidth: 1 + CKOUTDIV: + description: CKOUTDIV (CH0CFGR1 only) + bitOffset: 16 + bitWidth: 8 diff --git a/devices/patches/dfsdm/f7.yaml b/devices/patches/dfsdm/f7.yaml new file mode 100644 index 000000000..6a0b9ee40 --- /dev/null +++ b/devices/patches/dfsdm/f7.yaml @@ -0,0 +1,15 @@ +DFSDM[0123]_AWHTR: + _split: BKAWH + +DFSDM[0123]_AWLTR: + _split: BKAWL + +DFSDM[0123]_AWSR: + _split: + - AWHTF + - AWLTF + +DFSDM[0123]_AWCFR: + _split: + - CLRAWHTF + - CLRAWLTF diff --git a/devices/patches/dfsdm/h735_747_753.yaml b/devices/patches/dfsdm/h735_747_753.yaml new file mode 100644 index 000000000..8bbb3d5db --- /dev/null +++ b/devices/patches/dfsdm/h735_747_753.yaml @@ -0,0 +1,10 @@ +_include: + - dfsdm_v1.yaml + - jextsel.yaml + - jchgr.yaml + +# Remove non-existant DLYR fields. +_delete: + - "CH*DLYR" + +_strip: DFSDM_ diff --git a/devices/patches/dfsdm/jchgr.yaml b/devices/patches/dfsdm/jchgr.yaml new file mode 100644 index 000000000..0273f8cd9 --- /dev/null +++ b/devices/patches/dfsdm/jchgr.yaml @@ -0,0 +1,3 @@ +_modify: + FLT1CHGR: + name: FLT1JCHGR diff --git a/devices/patches/dfsdm/jextsel.yaml b/devices/patches/dfsdm/jextsel.yaml new file mode 100644 index 000000000..4b2171c55 --- /dev/null +++ b/devices/patches/dfsdm/jextsel.yaml @@ -0,0 +1,4 @@ +FLT?CR1: + _modify: + JEXTSEL: + bitWidth: 5 diff --git a/devices/patches/dfsdm/split.yaml b/devices/patches/dfsdm/split.yaml new file mode 100644 index 000000000..379636a7f --- /dev/null +++ b/devices/patches/dfsdm/split.yaml @@ -0,0 +1,15 @@ +FLT?AWHTR: + _split: BKAWH + +FLT?AWLTR: + _split: BKAWL + +FLT?AWSR: + _split: + - AWHTF + - AWLTF + +FLT?AWCFR: + _split: + - CLRAWHTF + - CLRAWLTF diff --git a/devices/patches/dma/bdma.yaml b/devices/patches/dma/bdma.yaml new file mode 100644 index 000000000..d1a319aac --- /dev/null +++ b/devices/patches/dma/bdma.yaml @@ -0,0 +1,156 @@ +_add: + CM1AR0: + description: Channel x memory 1 address register + addressOffset: 0x18 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR1: + description: Channel x memory 1 address register + addressOffset: 0x2C + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR2: + description: Channel x memory 1 address register + addressOffset: 0x40 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR3: + description: Channel x memory 1 address register + addressOffset: 0x54 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR4: + description: Channel x memory 1 address register + addressOffset: 0x68 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR5: + description: Channel x memory 1 address register + addressOffset: 0x7C + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR6: + description: Channel x memory 1 address register + addressOffset: 0x90 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR7: + description: Channel x memory 1 address register + addressOffset: 0xA4 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 +_modify: + CMAR1: + name: CM0AR0 + CMAR2: + name: CM0AR1 + CMAR3: + name: CM0AR2 + CMAR4: + name: CM0AR3 + CMAR5: + name: CM0AR4 + CMAR6: + name: CM0AR5 + CMAR7: + name: CM0AR6 + CMAR8: + name: CM0AR7 + CCR1: + name: CCR0 + CCR2: + name: CCR1 + CCR3: + name: CCR2 + CCR4: + name: CCR3 + CCR5: + name: CCR4 + CCR6: + name: CCR5 + CCR7: + name: CCR6 + CCR8: + name: CCR7 + CNDTR1: + name: CNDTR0 + CNDTR2: + name: CNDTR1 + CNDTR3: + name: CNDTR2 + CNDTR4: + name: CNDTR3 + CNDTR5: + name: CNDTR4 + CNDTR6: + name: CNDTR5 + CNDTR7: + name: CNDTR6 + CNDTR8: + name: CNDTR7 + CPAR1: + name: CPAR0 + CPAR2: + name: CPAR1 + CPAR3: + name: CPAR2 + CPAR4: + name: CPAR3 + CPAR5: + name: CPAR4 + CPAR6: + name: CPAR5 + CPAR7: + name: CPAR6 + CPAR8: + name: CPAR7 +CCR?: + _add: + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + CT: + description: Current target memory in double-buffer mode + bitOffset: 16 + bitWidth: 1 diff --git a/devices/patches/dma/bdma_v2.yaml b/devices/patches/dma/bdma_v2.yaml new file mode 100644 index 000000000..8f55b885d --- /dev/null +++ b/devices/patches/dma/bdma_v2.yaml @@ -0,0 +1,16 @@ +CCR?: + _add: + CT: + description: Current target memory in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 +CM1AR?: + _add: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 diff --git a/devices/patches/dma/dma2d_l4+.yaml b/devices/patches/dma/dma2d_l4+.yaml new file mode 100644 index 000000000..65acb0fb2 --- /dev/null +++ b/devices/patches/dma/dma2d_l4+.yaml @@ -0,0 +1,22 @@ +CR: + _modify: + MODE: + bitWidth: 3 + + _add: + LOM: + description: Line Offset Mode + bitOffset: 6 + bitWidth: 1 + +?GOR: + _modify: + LO: + bitWidth: 16 + +OPFCCR: + _add: + SB: + description: Swap Bytes + bitOffset: 9 + bitWidth: 1 diff --git a/devices/patches/dma/dma2d_v2.yaml b/devices/patches/dma/dma2d_v2.yaml new file mode 100644 index 000000000..336ef7fca --- /dev/null +++ b/devices/patches/dma/dma2d_v2.yaml @@ -0,0 +1,14 @@ +# "Chrom-Art Accelerator" 2D DMA engine +# Version 2 + +"[FB]GOR,OOR": + _modify: + LO: + bitWidth: 16 + +OPFCCR: + _add: + SB: + description: Swap Bytes + bitOffset: 8 + bitWidth: 1 diff --git a/devices/patches/dma/dma_v2.yaml b/devices/patches/dma/dma_v2.yaml new file mode 100644 index 000000000..39ae139b4 --- /dev/null +++ b/devices/patches/dma/dma_v2.yaml @@ -0,0 +1,4 @@ +S?CR: + _modify: + CHSEL: + bitWidth: 3 diff --git a/devices/patches/dma/dma_v21.yaml b/devices/patches/dma/dma_v21.yaml new file mode 100644 index 000000000..e575788a9 --- /dev/null +++ b/devices/patches/dma/dma_v21.yaml @@ -0,0 +1,4 @@ +S?CR: + _modify: + CHSEL: + bitWidth: 4 diff --git a/devices/patches/dma/dmamux_add_csr06.yaml b/devices/patches/dma/dmamux_add_csr06.yaml new file mode 100644 index 000000000..dde518409 --- /dev/null +++ b/devices/patches/dma/dmamux_add_csr06.yaml @@ -0,0 +1,29 @@ +_add: + CSR: + displayName: CSR + description: DMAMUX request line multiplexer interrupt channel status register + addressOffset: 128 + size: 32 + access: read-only + resetValue: 0 + resetMask: 4294967295 + fields: + SOF: + description: Synchronization Overrun Flag + bitOffset: 0 + bitWidth: 7 + access: read-only + CFR: + displayName: CFR + description: DMAMUX request line multiplexer interrupt clear flag register + addressOffset: 132 + size: 32 + access: write-only + resetValue: 0 + resetMask: 4294967295 + fields: + CSOF: + description: Synchronization Clear Overrun Flag + bitOffset: 0 + bitWidth: 7 + access: write-only diff --git a/devices/patches/dma/dmamux_split.yaml b/devices/patches/dma/dmamux_split.yaml new file mode 100644 index 000000000..b9d66b533 --- /dev/null +++ b/devices/patches/dma/dmamux_split.yaml @@ -0,0 +1,8 @@ +CFR: + _split: CSOF +RGSR: + _split: OF +RGCFR: + _split: COF +CSR: + _split: SOF diff --git a/devices/patches/dma/fcr_wo.yaml b/devices/patches/dma/fcr_wo.yaml new file mode 100644 index 000000000..4fb172606 --- /dev/null +++ b/devices/patches/dma/fcr_wo.yaml @@ -0,0 +1,5 @@ +# Many devices have these flag clear registers incorrectly set to read-write + +_modify: + "[LH]IFCR": + access: write-only diff --git a/devices/patches/dma/g0_5ch.yaml b/devices/patches/dma/g0_5ch.yaml new file mode 100644 index 000000000..1bbfa95ab --- /dev/null +++ b/devices/patches/dma/g0_5ch.yaml @@ -0,0 +1,13 @@ +# convert a G0 DMA peripheral from 7 channels to 5 +# include _inside_ the DMA peripheral + +ISR: + _delete: + - "*[67]" +IFCR: + _delete: + - "*[67]" + +_delete: + _registers: + - "*[67]" diff --git a/devices/patches/dma/g0_dma1_5ch_only.yaml b/devices/patches/dma/g0_dma1_5ch_only.yaml new file mode 100644 index 000000000..9df61bb64 --- /dev/null +++ b/devices/patches/dma/g0_dma1_5ch_only.yaml @@ -0,0 +1,18 @@ +# the vendor SVD has 7ch DMA1 and DMA2 +# but the device only has a 5ch DMA1 and no DMA2 + +_delete: + - DMA2 + +DMA1: + _modify: + _interrupts: + DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5: + name: DMA1_Channel4_5_DMAMUX + description: interrupts for DMA1 channels 4-5 and DMAMUX + +SYSCFG: + ITLINE11: + _delete: + - "DMA1_CH[67]" + - "DMA2_CH*" diff --git a/devices/patches/dma/g0_dma1_7ch_only.yaml b/devices/patches/dma/g0_dma1_7ch_only.yaml new file mode 100644 index 000000000..fc8cd9337 --- /dev/null +++ b/devices/patches/dma/g0_dma1_7ch_only.yaml @@ -0,0 +1,17 @@ +# the vendor SVD has 7ch DMA1 and DMA2 +# but the device only has a 7ch DMA1 and no DMA2 + +_delete: + - DMA2 + +DMA1: + _modify: + _interrupts: + DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5: + name: DMA1_Channel4_5_6_7_DMAMUX + description: interrupts for DMA1 channels 4-7 and DMAMUX + +SYSCFG: + ITLINE11: + _delete: + - "DMA2_CH*" diff --git a/devices/patches/dma/g0_dma2_5ch.yaml b/devices/patches/dma/g0_dma2_5ch.yaml new file mode 100644 index 000000000..2e0cd93a5 --- /dev/null +++ b/devices/patches/dma/g0_dma2_5ch.yaml @@ -0,0 +1,13 @@ +# the vendor SVD has DMA2 derivedFrom DMA1 +# but it only has 5 channels, not 7 like DMA1 +# so copy it and remove the extra registers/fields + +_copy: + DMA2: + from: DMA1 + +DMA1: + _interrupts: + DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5: + description: > + interrupts for DMA1 channels 4-7, DMAMUX, and DMA2 channels 1-5 diff --git a/devices/patches/dma/gpdma_u5_tr1.yaml b/devices/patches/dma/gpdma_u5_tr1.yaml new file mode 100644 index 000000000..b6244ea13 --- /dev/null +++ b/devices/patches/dma/gpdma_u5_tr1.yaml @@ -0,0 +1,37 @@ +_copy: + C4TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x290 + C5TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x310 + C6TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x390 + C7TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x410 + C8TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x490 + C9TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x510 + C10TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x590 + C11TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x610 + C12TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x690 + C13TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x710 + C14TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x790 + C15TR1: + _from: GPDMA_C3TR1 + addressOffset: 0x810 diff --git a/devices/patches/dma/h7_dmacr.yaml b/devices/patches/dma/h7_dmacr.yaml new file mode 100644 index 000000000..70941d7cb --- /dev/null +++ b/devices/patches/dma/h7_dmacr.yaml @@ -0,0 +1,10 @@ +S?CR: + _add: + TRBUFF: + description: Enable the DMA to handle bufferable transfers + bitOffset: 20 + bitWidth: 1 + access: read-write + TRBUFF: + Disabled: [0, Bufferable transfers not enabled] + Enabled: [1, Bufferable transfers enabled] diff --git a/devices/common_patches/dma_interrupt_names.yaml b/devices/patches/dma/interrupt_names.yaml similarity index 100% rename from devices/common_patches/dma_interrupt_names.yaml rename to devices/patches/dma/interrupt_names.yaml diff --git a/devices/patches/dsi/f7_wpcr.yaml b/devices/patches/dsi/f7_wpcr.yaml new file mode 100644 index 000000000..a22b86601 --- /dev/null +++ b/devices/patches/dsi/f7_wpcr.yaml @@ -0,0 +1,16 @@ +_modify: + WPCR1: + name: WPCR0 + displayName: WPCR0 + WPCR2: + name: WPCR1 + displayName: WPCR1 + WPCR3: + name: WPCR2 + displayName: WPCR2 + WPCR4: + name: WPCR3 + displayName: WPCR3 + WPCR5: + name: WPCR4 + displayName: WPCR4 diff --git a/devices/patches/dsi/h7-desc.yaml b/devices/patches/dsi/h7-desc.yaml new file mode 100644 index 000000000..1780c00e4 --- /dev/null +++ b/devices/patches/dsi/h7-desc.yaml @@ -0,0 +1,606 @@ +# H7 MIPI DSI Host Peripheral + +_add: + _interrupts: + DSI: + description: DSI Host global interrupt + value: 123 + +VR: + _modify: + VERSION: + description: Version of the DSI Host +CR: + _modify: + EN: + description: Enable +CCR: + _modify: + TOCKDIV: + description: Timeout clock division + TXECKDIV: + description: TX escape clock division +LVCIDR: + _modify: + VCID: + description: Virtual channel ID +LCOLCR: + _modify: + LPE: + description: Loosely packet enable + COLC: + description: Color coding +LPCR: + _modify: + HSP: + description: HSYNC polarity + VSP: + description: VSYNC polarity + DEP: + description: Data enable polarity +LPMCR: + _modify: + LPSIZE: + description: Largest packet size + VLPSIZE: + description: VACT largest packet size +PCR: + _modify: + CRCRXE: + description: CRC reception enable + ECCRXE: + description: ECC reception enable + BTAE: + description: Bus + ETRXE: + description: EoTp reception enable + ETTXE: + description: EoTp transmission enable +GVCIDR: + _modify: + VCID: + description: Virtual channel ID +MCR: + _modify: + CMDM: + description: Command mode +VMCR: + _modify: + PGO: + description: Pattern generator orientation + PGM: + description: Pattern generator mode + PGE: + description: Pattern generator enable + LPCE: + description: Low-power command enable + FBTAAE: + description: Frame bus-turn-around acknowledge enable + LPHFPE: + description: Low-power horizontal front-porch enable + LPHBPE: + description: Low-power horizontal back-porch enable + LPVAE: + description: Low-power vertical active enable + LPVFPE: + description: Low-power vertical front-porch enable + LPVBPE: + description: Low-power vertical back-porch enable + LPVSAE: + description: Low-power vertical sync active enable + VMT: + description: Video mode type +VPCR: + _modify: + VPSIZE: + description: Video packet size +VCCR: + _modify: + NUMC: + description: Number of chunks +VNPCR: + _modify: + NPSIZE: + description: Null packet size +VHSACR: + _modify: + HSA: + description: Horizontal synchronism active duration +VHBPCR: + _modify: + HBP: + description: Horizontal back-porch duration +VLCR: + _modify: + HLINE: + description: Horizontal line duration +VVSACR: + _modify: + VSA: + description: Vertical synchronism active duration +VVBPCR: + _modify: + VBP: + description: Vertical back-porch duration +VVFPCR: + _modify: + VFP: + description: Vertical front-porch duration +VVACR: + _modify: + VA: + description: Vertical active duration +LCCR: + _modify: + CMDSIZE: + description: Command size +CMCR: + _modify: + MRDPS: + description: Maximum read packet size + DLWTX: + description: DCS long write transmission + DSR0TX: + description: DCS short read zero parameter transmission + DSW1TX: + description: DCS short read one parameter transmission + DSW0TX: + description: DCS short write zero parameter transmission + GLWTX: + description: Generic long write transmission + GSR2TX: + description: Generic short read two parameters transmission + GSR1TX: + description: Generic short read one parameters transmission + GSR0TX: + description: Generic short read zero parameters transmission + GSW2TX: + description: Generic short write two parameters transmission + GSW1TX: + description: Generic short write one parameters transmission + GSW0TX: + description: Generic short write zero parameters transmission + ARE: + description: Acknowledge request enable + TEARE: + description: Tearing effect acknowledge request enable +GHCR: + _modify: + WCMSB: + description: WordCount MSB + WCLSB: + description: WordCount LSB + VCID: + description: Channel + DT: + description: Type +GPDR: + _modify: + DATA4: + description: Payload byte 4 + DATA3: + description: Payload byte 3 + DATA2: + description: Payload byte 2 + DATA1: + description: Payload byte 1 +GPSR: + _modify: + RCB: + description: Read command busy + PRDFF: + description: Payload read FIFO full + PRDFE: + description: Payload read FIFO empty + PWRFF: + description: Payload write FIFO full + PWRFE: + description: Payload write FIFO empty + CMDFF: + description: Command FIFO full + CMDFE: + description: Command FIFO empty +TCCR0: + _modify: + HSTX_TOCNT: + description: High-speed transmission timeout counter + LPRX_TOCNT: + description: Low-power reception timeout counter +TCCR1: + _modify: + HSRD_TOCNT: + description: High-speed read timeout counter +TCCR2: + _modify: + LPRD_TOCNT: + description: Low-power read timeout counter +TCCR3: + _modify: + PM: + description: Presp mode + HSWR_TOCNT: + description: High-speed write timeout counter +TCCR4: + _modify: + LPWR_TOCNT: + description: Low-power write timeout counter +TCCR5: + _modify: + BTA_TOCNT: + description: Bus-turn-around timeout counter +CLCR: + _modify: + ACR: + description: Automatic clock lane control + DPCC: + description: D-PHY clock control +CLTCR: + _modify: + HS2LP_TIME: + description: High-speed to low-power time + LP2HS_TIME: + description: Low-power to high-speed time +DLTCR: + _modify: + HS2LP_TIME: + description: High-speed to low-power time + LP2HS_TIME: + description: Low-power to high-speed time + MRD_TIME: + description: Maximum read time +PCTLR: + _modify: + CKE: + description: Clock enable + DEN: + description: Digital enable +PCONFR: + _modify: + SW_TIME: + description: Stop wait time + NL: + description: Number of lanes +PUCR: + _modify: + UEDL: + description: ULPS exit on data lane + URDL: + description: ULPS request on data lane + UECL: + description: ULPS exit on clock lane + URCL: + description: ULPS request on clock lane +PTTCR: + _modify: + TX_TRIG: + description: Transmission trigger +PSR: + _modify: + UAN1: + description: ULPS active not lane 1 + PSS1: + description: PHY stop state lane 1 + RUE0: + description: RX ULPS escape lane 0 + UAN0: + description: ULPS active not lane 1 + PSS0: + description: PHY stop state lane 0 + UANC: + description: ULPS active not clock lane + PSSC: + description: PHY stop state clock lane + PD: + description: PHY direction +ISR1: + _modify: + GPRXE: + description: Generic payload receive error + GPRDE: + description: Generic payload read error + GPTXE: + description: Generic payload transmit error + GPWRE: + description: Generic payload write error + GCWRE: + description: Generic command write error + LPWRE: + description: LTDC payload write error + EOTPE: + description: EoTp error + PSE: + description: Packet size error + CRCE: + description: CRC error + ECCME: + description: ECC multi + ECCSE: + description: ECC single + TOLPRX: + description: Timeout low + TOHSTX: + description: Timeout high +IER1: + _modify: + GPRXEIE: + description: Generic payload receive error interrupt enable + GPRDEIE: + description: Generic payload read error interrupt enable + GPTXEIE: + description: Generic payload transmit error interrupt enable + GPWREIE: + description: Generic payload write error interrupt enable + GCWREIE: + description: Generic command write error interrupt enable + LPWREIE: + description: LTDC payload write error interrupt enable + EOTPEIE: + description: EoTp error interrupt enable + PSEIE: + description: Packet size error interrupt enable + CRCEIE: + description: CRC error interrupt enable + ECCMEIE: + description: ECC multi + ECCSEIE: + description: ECC single + TOLPRXIE: + description: Timeout low + TOHSTXIE: + description: Timeout high +FIR1: + _modify: + FGPRXE: + description: Force generic payload receive error + FGPRDE: + description: Force generic payload read error + FGPTXE: + description: Force generic payload transmit error + FGPWRE: + description: Force generic payload write error + FGCWRE: + description: Force generic command write error + FLPWRE: + description: Force LTDC payload write error + FEOTPE: + description: Force EoTp error + FPSE: + description: Force packet size error + FCRCE: + description: Force CRC error + FECCME: + description: Force ECC multi + FECCSE: + description: Force ECC single + FTOLPRX: + description: Force timeout low + FTOHSTX: + description: Force timeout high +VSCR: + _modify: + UR: + description: Update register + EN: + description: Enable +LCVCIDR: + _modify: + VCID: + description: Virtual channel ID +LCCCR: + _modify: + LPE: + description: Loosely packed enable + COLC: + description: Color coding +LPMCCR: + _modify: + LPSIZE: + description: Largest packet size + VLPSIZE: + description: VACT largest packet size +VMCCR: + _modify: + LPCE: + description: Low-power command enable + FBTAAE: + description: Frame BTA acknowledge enable + LPHFE: + description: Low-power horizontal front-porch enable + LPHBPE: + description: Low-power horizontal back-porch enable + LPVAE: + description: Low-power vertical active enable + LPVFPE: + description: Low-power vertical front-porch enable + LPVBPE: + description: Low-power vertical back-porch enable + LPVSAE: + description: Low-power vertical sync time enable + VMT: + description: Video mode type +VPCCR: + _modify: + VPSIZE: + description: Video packet size +VCCCR: + _modify: + NUMC: + description: Number of chunks +VNPCCR: + _modify: + NPSIZE: + description: Null packet size +VHSACCR: + _modify: + HSA: + description: Horizontal synchronism active duration +VHBPCCR: + _modify: + HBP: + description: Horizontal back +VLCCR: + _modify: + HLINE: + description: Horizontal line duration +VVSACCR: + _modify: + VSA: + description: Vertical synchronism active duration +VVBPCCR: + _modify: + VBP: + description: Vertical back +VVFPCCR: + _modify: + VFP: + description: Vertical front +VVACCR: + _modify: + VA: + description: Vertical active duration +WCFGR: + _modify: + VSPOL: + description: VSync polarity + AR: + description: Automatic refresh + TEPOL: + description: TE polarity + TESRC: + description: TE source + COLMUX: + description: Color multiplexing + DSIM: + description: DSI mode +WCR: + _modify: + DSIEN: + description: DSI enable + LTDCEN: + description: LTDC enable + SHTDN: + description: Shutdown + COLM: + description: Color mode +WIER: + _modify: + RRIE: + description: Regulator ready interrupt enable + PLLUIE: + description: PLL unlock interrupt enable + PLLLIE: + description: PLL lock interrupt enable + ERIE: + description: End of refresh interrupt enable + TEIE: + description: Tearing effect interrupt enable +WISR: + _modify: + RRIF: + description: Regulator ready interrupt flag + RRS: + description: Regulator ready status + PLLUIF: + description: PLL unlock interrupt flag + PLLLIF: + description: PLL lock interrupt flag + PLLLS: + description: PLL lock status + BUSY: + description: Busy flag + ERIF: + description: End of refresh interrupt flag + TEIF: + description: Tearing effect interrupt flag +WIFCR: + _modify: + CRRIF: + description: Clear regulator ready interrupt flag + CPLLUIF: + description: Clear PLL unlock interrupt flag + CPLLLIF: + description: Clear PLL lock interrupt flag + CERIF: + description: Clear end of refresh interrupt flag + CTEIF: + description: Clear tearing effect interrupt flag +WPCR0: + _modify: + TCLKPOSTEN: + description: Custom time for tCLK + TLPXCEN: + description: Custom time for tLPX for clock lane enable + THSEXITEN: + description: Custom time for tHS + TLPXDEN: + description: Custom time for tLPX for data lanes enable + THSZEROEN: + description: Custom time for tHS + THSTRAILEN: + description: Custom time for tHS + THSPREPEN: + description: Custom time for tHS + TCLKZEROEN: + description: Custom time for tCLK + TCLKPREPEN: + description: Custom time for tCLK + PDEN: + description: Pull-down enable + TDDL: + description: Turn disable data lanes + CDOFFDL: + description: Contention detection OFF on data lanes + FTXSMDL: + description: Force in TX Stop mode the data lanes + FTXSMCL: + description: Force in TX Stop mode the clock lane + HSIDL1: + description: Invert the high-speed data signal on data lane 1 + HSIDL0: + description: Invert the high-speed data signal on data lane 0 + HSICL: + description: Invert high + SWDL1: + description: Swap data lane 1 pins + SWDL0: + description: Swap data lane 0 pins + SWCL: + description: Swap clock lane pins + UIX4: + description: Unit interval multiplied by 4 +WPCR2: + _modify: + THSTRAIL: + description: tHSTRAIL + THSPREP: + description: tHS-PREPARE + TCLKZERO: + description: tCLK-ZERO + TCLKPREP: + description: tCLK-PREPARE +WPCR3: + _modify: + TLPXC: + description: tLPXC for clock lane + THSEXIT: + description: tHSEXIT + TLPXD: + description: tLPX for data lanes + THSZERO: + description: tHS-ZERO +WPCR4: + _modify: + TCLKPOST: + description: tCLK-POST +WRPCR: + _modify: + REGEN: + description: Regulator enable + ODF: + description: PLL output division factor + IDF: + description: PLL input division factor + NDIV: + description: PLL loop division factor + PLLEN: + description: PLL enable diff --git a/devices/patches/ethernet/f1.yaml b/devices/patches/ethernet/f1.yaml new file mode 100644 index 000000000..749097912 --- /dev/null +++ b/devices/patches/ethernet/f1.yaml @@ -0,0 +1,18 @@ +Ethernet_MAC: + MACFCR: + _modify: + FCB_BPA: + name: FCB + MACA3LR: + _modify: + MBCA3L: + name: MACA3L + MACA2HR: + _modify: + ETH_MACA2HR: + name: MACA2H +Ethernet_DMA: + DMABMR: + _modify: + RTPR: + name: PM diff --git a/devices/common_patches/f2_f4_ethernet.yaml b/devices/patches/ethernet/f2_f4.yaml similarity index 100% rename from devices/common_patches/f2_f4_ethernet.yaml rename to devices/patches/ethernet/f2_f4.yaml diff --git a/devices/patches/ethernet/f4_f7.yaml b/devices/patches/ethernet/f4_f7.yaml new file mode 100644 index 000000000..ad2d85752 --- /dev/null +++ b/devices/patches/ethernet/f4_f7.yaml @@ -0,0 +1,9 @@ +Ethernet_PTP: + PTPPPSCR: + _add: + PPSFREQ: + bitWidth: 4 + bitOffset: 0 + access: read-write + description: PPS frequency selection + _delete: [TSSO, TSTTR] diff --git a/devices/patches/ethernet/h7_combined_desc.yaml b/devices/patches/ethernet/h7_combined_desc.yaml new file mode 100644 index 000000000..b9220dab3 --- /dev/null +++ b/devices/patches/ethernet/h7_combined_desc.yaml @@ -0,0 +1,18 @@ +# Applies to H7 where MAC and MTL registers are combined under +# the Ethernet_MAC peripheral + +# Create separate DMA and MTL periperhals +_include: + - h7_dma.yaml + - h7_mtl.yaml + +Ethernet_MAC: + # Delete DMA and MTL parts from MAC + _delete: + _registers: + - DMA* + - MTL* + + # Descriptions for MAC + _include: + - h7_desc_mac.yaml diff --git a/devices/patches/ethernet/h7_desc.yaml b/devices/patches/ethernet/h7_desc.yaml new file mode 100644 index 000000000..74c5b2924 --- /dev/null +++ b/devices/patches/ethernet/h7_desc.yaml @@ -0,0 +1,17 @@ +# Applies to H7 + +Ethernet_MTL: + _include: + - h7_desc_mtl.yaml + +Ethernet_MAC: + _include: + - h7_desc_mac.yaml + MACRWKPFR: + _modify: + MACRWKPFR: + description: Remote wakeup packet filter + MACHWF1R: + _modify: + ADDR64: + description: Address width diff --git a/devices/patches/ethernet/h7_desc_mac.yaml b/devices/patches/ethernet/h7_desc_mac.yaml new file mode 100644 index 000000000..ecfcc0593 --- /dev/null +++ b/devices/patches/ethernet/h7_desc_mac.yaml @@ -0,0 +1,822 @@ +# Descriptions of H7 Media Access Control module (MAC) registers + +MACCR: + _modify: + RE: + description: Receiver Enable + TE: + description: Transmitter Enable + PRELEN: + description: Preamble Length for Transmit Packets + DC: + description: Deferral Check + BL: + description: Back-Off Limit + DR: + description: Disable Retry + DCRS: + description: Disable Carrier Sense During Transmission + DO: + description: Disable Receive Own + ECRSFD: + description: Enable Carrier Sense Before Transmission in Full-Duplex Mode + LM: + description: Loopback Mode + DM: + description: Duplex Mode + FES: + description: MAC Speed + JE: + description: Jumbo Packet Enable + JD: + description: Jabber Disable + WD: + description: Watchdog Disable + ACS: + description: Automatic Pad or CRC Stripping + CST: + description: CRC stripping for Type packets + S2KP: + description: IEEE 802.3as Support for 2K Packets + GPSLCE: + description: Giant Packet Size Limit Control Enable + IPG: + description: Inter-Packet Gap + IPC: + description: Checksum Offload + SARC: + description: Source Address Insertion or Replacement Control + ARPEN: + description: ARP Offload Enable +MACECR: + _modify: + GPSL: + description: Giant Packet Size Limit + DCRCC: + description: Disable CRC Checking for Received Packets + SPEN: + description: Slow Protocol Detection Enable + USP: + description: Unicast Slow Protocol Packet Detect + EIPGEN: + description: Extended Inter-Packet Gap Enable + EIPG: + description: Extended Inter-Packet Gap +MACPFR: + _modify: + RA: + description: Receive All + DNTU: + description: Drop Non-TCP/UDP over IP Packets + IPFE: + description: Layer 3 and Layer 4 Filter Enable + VTFE: + description: VLAN Tag Filter Enable + HPF: + description: Hash or Perfect Filter + SAF: + description: Source Address Filter Enable + SAIF: + description: SA Inverse Filtering + PCF: + description: Pass Control Packets + DBF: + description: Disable Broadcast Packets + PM: + description: Pass All Multicast + DAIF: + description: DA Inverse Filtering + HMC: + description: Hash Multicast + HUC: + description: Hash Unicast + PR: + description: Promiscuous Mode +MACWTR: + _modify: + WTO: + description: Watchdog Timeout + PWE: + description: Programmable Watchdog Enable +MACHT0R: + _modify: + HT31T0: + description: MAC Hash Table First 32 Bits +MACHT1R: + _modify: + HT63T32: + description: MAC Hash Table Second 32 Bits +MACVTR: + _modify: + EIVLRXS: + description: Enable Inner VLAN Tag in Rx Status + EIVLS: + description: Enable Inner VLAN Tag Stripping on Receive + ERIVLT: + description: Enable Inner VLAN Tag + EDVLP: + description: Enable Double VLAN Processing + VTHM: + description: VLAN Tag Hash Table Match Enable + EVLRXS: + description: Enable VLAN Tag in Rx status + EVLS: + description: Enable VLAN Tag Stripping on Receive + DOVLTC: + description: Disable VLAN Type Check + ERSVLM: + description: Enable Receive S-VLAN Match + ESVL: + description: Enable S-VLAN + VTIM: + description: VLAN Tag Inverse Match Enable + ETV: + description: Enable 12-Bit VLAN Tag Comparison + VL: + description: VLAN Tag Identifier for Receive Packets +MACVHTR: + _modify: + VLHT: + description: VLAN Hash Table +MACVIR: + _modify: + VLTI: + description: VLAN Tag Input + CSVL: + description: C-VLAN or S-VLAN + VLP: + description: VLAN Priority Control + VLC: + description: VLAN Tag Control in Transmit Packets + VLT: + description: VLAN Tag for Transmit Packets +MACIVIR: + _modify: + VLTI: + description: VLAN Tag Input + CSVL: + description: C-VLAN or S-VLAN + VLP: + description: VLAN Priority Control + VLC: + description: VLAN Tag Control in Transmit Packets + VLT: + description: VLAN Tag for Transmit Packets +MACQTxFCR: + _modify: + PT: + description: Pause Time + DZPQ: + description: Disable Zero-Quanta Pause + PLT: + description: Pause Low Threshold + TFE: + description: Transmit Flow Control Enable + FCB_BPA: + description: Flow Control Busy or Backpressure Activate +MACRxFCR: + _modify: + UP: + description: Unicast Pause Packet Detect + RFE: + description: Receive Flow Control Enable +MACISR: + _modify: + RXSTSIS: + description: Receive Status Interrupt + TXSTSIS: + description: Transmit Status Interrupt + TSIS: + description: Timestamp Interrupt Status + MMCTXIS: + description: MMC Transmit Interrupt Status + MMCRXIS: + description: MMC Receive Interrupt Status + MMCIS: + description: MMC Interrupt Status + LPIIS: + description: LPI Interrupt Status + PMTIS: + description: PMT Interrupt Status + PHYIS: + description: PHY Interrupt +MACIER: + _modify: + RXSTSIE: + description: Receive Status Interrupt Enable + TXSTSIE: + description: Transmit Status Interrupt Enable + TSIE: + description: Timestamp Interrupt Enable + LPIIE: + description: LPI Interrupt Enable + PMTIE: + description: PMT Interrupt Enable + PHYIE: + description: PHY Interrupt Enable +MACRxTxSR: + _modify: + RWT: + description: Receive Watchdog Timeout + EXCOL: + description: Excessive Collisions + LCOL: + description: Late Collision + EXDEF: + description: Excessive Deferral + LCARR: + description: Loss of Carrier + NCARR: + description: No Carrier + TJT: + description: Transmit Jabber Timeout +MACPCSR: + _modify: + RWKFILTRST: + description: Remote wakeup Packet Filter Register Pointer Reset + RWKPTR: + description: Remote wakeup FIFO Pointer + RWKPFE: + description: Remote wakeup Packet Forwarding Enable + GLBLUCAST: + description: Global Unicast + RWKPRCVD: + description: Remote wakeup Packet Received + MGKPRCVD: + description: Magic Packet Received + RWKPKTEN: + description: Remote wakeup Packet Enable + MGKPKTEN: + description: Magic Packet Enable + PWRDWN: + description: Power Down +MACLCSR: + _modify: + LPITE: + description: LPI Timer Enable + LPITXA: + description: LPI Tx Automate + PLSEN: + description: PHY Link Status Enable + PLS: + description: PHY Link Status + LPIEN: + description: LPI Enable + RLPIST: + description: Receive LPI State + TLPIST: + description: Transmit LPI State + RLPIEX: + description: Receive LPI Exit + RLPIEN: + description: Receive LPI Entry + TLPIEX: + description: Transmit LPI Exit + TLPIEN: + description: Transmit LPI Entry +MACLTCR: + _modify: + LST: + description: LPI LS Timer + TWT: + description: LPI TW Timer +MACLETR: + _modify: + LPIET: + description: LPI Entry Timer +MAC1USTCR: + _modify: + TIC_1US_CNTR: + description: 1 µs tick Counter +MACVR: + _modify: + USERVER: + description: ST-defined version + SNPSVER: + description: IP version +MACDR: + _modify: + TFCSTS: + description: MAC Transmit Packet Controller Status + TPESTS: + description: MAC MII Transmit Protocol Engine Status + RFCFCSTS: + description: MAC Receive Packet Controller FIFO Status + RPESTS: + description: MAC MII Receive Protocol Engine Status +MACHWF1R: + _modify: + L3L4FNUM: + description: Total number of L3 or L4 Filters + HASHTBLSZ: + description: Hash Table Size + AVSEL: + description: AV Feature Enable + DBGMEMA: + description: DMA Debug Registers Enable + TSOEN: + description: TCP Segmentation Offload Enable + SPHEN: + description: Split Header Feature Enable + DCBEN: + description: DCB Feature Enable + ADVTHWORD: + description: IEEE 1588 High Word Register Enable + PTOEN: + description: PTP Offload Enable + OSTEN: + description: One-Step Timestamping Enable + TXFIFOSIZE: + description: MTL Transmit FIFO Size + RXFIFOSIZE: + description: MTL Receive FIFO Size +MACHWF2R: + _modify: + AUXSNAPNUM: + description: Number of Auxiliary Snapshot Inputs + PPSOUTNUM: + description: Number of PPS Outputs + TXCHCNT: + description: Number of DMA Transmit Channels + RXCHCNT: + description: Number of DMA Receive Channels + TXQCNT: + description: Number of MTL Transmit Queues + RXQCNT: + description: Number of MTL Receive Queues +MACMDIOAR: + _modify: + PSE: + description: Preamble Suppression Enable + BTB: + description: Back to Back transactions + PA: + description: Physical Layer Address + RDA: + description: Register/Device Address + NTC: + description: Number of Training Clocks + CR: + description: CSR Clock Range + SKAP: + description: Skip Address Packet + GOC: + description: MII Operation Command + C45E: + description: Clause 45 PHY Enable + MB: + description: MII Busy +MACMDIODR: + _modify: + RA: + description: Register Address + MD: + description: MII Data +MACARPAR: + _modify: + # TODO - this might actually be at 0xAE0 - the reference manual says it + # is, but ST's own HAL and where they locate it in the map disagree. + ARPPA: + description: ARP Protocol Address +MACA0HR: + _modify: + AE: + description: Address Enable + ADDRHI: + description: MAC Address0[47:32] +MACA0LR: + _modify: + ADDRLO: + description: MAC Address 0 [31:0] +MACA1LR: + _modify: + ADDRLO: + description: MAC Address 1 [31:0] +MACA2LR: + _modify: + ADDRLO: + description: MAC Address 2 [31:0] +MACA3LR: + _modify: + ADDRLO: + description: MAC Address 3 [31:0] +MACA1HR: + _modify: + AE: + description: Address Enable + SA: + description: Source Address + MBC: + description: Mask Byte Control + ADDRHI: + description: MAC Address1 [47:32] +MACA2HR: + _modify: + AE: + description: Address Enable + SA: + description: Source Address + MBC: + description: Mask Byte Control + ADDRHI: + description: MAC Address2 [47:32] +MACA3HR: + _modify: + AE: + description: Address Enable + SA: + description: Source Address + MBC: + description: Mask Byte Control + ADDRHI: + description: MAC Address3 [47:32] +TX_SINGLE_COLLISION_GOOD_PACKETS: + _modify: + TXSNGLCOLG: + description: Tx Single Collision Good Packets +TX_MULTIPLE_COLLISION_GOOD_PACKETS: + _modify: + TXMULTCOLG: + description: Tx Multiple Collision Good Packets +TX_PACKET_COUNT_GOOD: + _modify: + TXPKTG: + description: Tx Packet Count Good +RX_CRC_ERROR_PACKETS: + _modify: + RXCRCERR: + description: Rx CRC Error Packets +RX_ALIGNMENT_ERROR_PACKETS: + _modify: + RXALGNERR: + description: Rx Alignment Error Packets +RX_UNICAST_PACKETS_GOOD: + _modify: + RXUCASTG: + description: Rx Unicast Packets Good +TX_LPI_USEC_CNTR: + _modify: + TXLPIUSC: + description: Tx LPI Microseconds Counter +TX_LPI_TRAN_CNTR: + _modify: + TXLPITRC: + description: Tx LPI Transition counter +RX_LPI_USEC_CNTR: + _modify: + RXLPIUSC: + description: Rx LPI Microseconds Counter +RX_LPI_TRAN_CNTR: + _modify: + RXLPITRC: + description: Rx LPI Transition counter +MACL3L4C0R: + _modify: + L4DPIM0: + description: Layer 4 Destination Port Inverse Match Enable + L4DPM0: + description: Layer 4 Destination Port Match Enable + L4SPIM0: + description: Layer 4 Source Port Inverse Match Enable + L4SPM0: + description: Layer 4 Source Port Match Enable + L4PEN0: + description: Layer 4 Protocol Enable + L3HDBM0: + description: Layer 3 IP DA Higher Bits Match + L3HSBM0: + description: Layer 3 IP SA Higher Bits Match + L3DAIM0: + description: Layer 3 IP DA Inverse Match Enable + L3DAM0: + description: Layer 3 IP DA Match Enable + L3SAIM0: + description: Layer 3 IP SA Inverse Match Enable + L3SAM0: + description: Layer 3 IP SA Match Enable + L3PEN0: + description: Layer 3 Protocol Enable +MACL4A0R: + _modify: + L4DP0: + description: Layer 4 Destination Port Number Field + L4SP0: + description: Layer 4 Source Port Number Field +MACL3A00R: + _modify: + L3A00: + description: Layer 3 Address 0 Field +MACL3A10R: + _modify: + L3A10: + description: Layer 3 Address 1 Field +MACL3A20: + _modify: + L3A20: + description: Layer 3 Address 2 Field +MACL3A30: + _modify: + L3A30: + description: Layer 3 Address 3 Field +MACL3L4C1R: + _modify: + L4DPIM1: + description: Layer 4 Destination Port Inverse Match Enable + L4DPM1: + description: Layer 4 Destination Port Match Enable + L4SPIM1: + description: Layer 4 Source Port Inverse Match Enable + L4SPM1: + description: Layer 4 Source Port Match Enable + L4PEN1: + description: Layer 4 Protocol Enable + L3HDBM1: + description: Layer 3 IP DA Higher Bits Match + L3HSBM1: + description: Layer 3 IP SA Higher Bits Match + L3DAIM1: + description: Layer 3 IP DA Inverse Match Enable + L3DAM1: + description: Layer 3 IP DA Match Enable + L3SAIM1: + description: Layer 3 IP SA Inverse Match Enable + L3SAM1: + description: Layer 3 IP SA Match Enable + L3PEN1: + description: Layer 3 Protocol Enable +MACL4A1R: + _modify: + L4DP1: + description: Layer 4 Destination Port Number Field + L4SP1: + description: Layer 4 Source Port Number Field +MACL3A01R: + _modify: + L3A01: + description: Layer 3 Address 0 Field +MACL3A11R: + _modify: + L3A11: + description: Layer 3 Address 1 Field +MACL3A21R: + _modify: + L3A21: + description: Layer 3 Address 2 Field +MACL3A31R: + _modify: + L3A31: + description: Layer 3 Address 3 Field +MACTSCR: + _modify: + TXTSSTSM: + description: Transmit Timestamp Status Mode + CSC: + description: Enable checksum correction during OST for PTP over UDP/IPv4 packets + TSENMACADDR: + description: Enable MAC Address for PTP Packet Filtering + SNAPTYPSEL: + description: Select PTP packets for Taking Snapshots + TSMSTRENA: + description: Enable Snapshot for Messages Relevant to Master + TSEVNTENA: + description: Enable Timestamp Snapshot for Event Messages + TSIPV4ENA: + description: Enable Processing of PTP Packets Sent over IPv4-UDP + TSIPV6ENA: + description: Enable Processing of PTP Packets Sent over IPv6-UDP + TSIPENA: + description: Enable Processing of PTP over Ethernet Packets + TSVER2ENA: + description: Enable PTP Packet Processing for Version 2 Format + TSCTRLSSR: + description: Timestamp Digital or Binary Rollover Control + TSENALL: + description: Enable Timestamp for All Packets + TSADDREG: + description: Update Addend Register + TSUPDT: + description: Update Timestamp + TSINIT: + description: Initialize Timestamp + TSCFUPDT: + description: Fine or Coarse Timestamp Update + TSENA: + description: Enable Timestamp +MACSSIR: + _modify: + SSINC: + description: Sub-second Increment Value + SNSINC: + description: Sub-nanosecond Increment Value +MACSTSR: + _modify: + TSS: + description: Timestamp Second +MACSTNR: + _modify: + TSSS: + description: Timestamp Sub-seconds +MACSTSUR: + _modify: + TSS: + description: Timestamp Seconds +MACSTNUR: + _modify: + ADDSUB: + description: Add or Subtract Time + TSSS: + description: Timestamp Sub-seconds +MACTSAR: + _modify: + TSAR: + description: Timestamp Addend Register +MACTSSR: + _modify: + ATSNS: + description: Number of Auxiliary Timestamp Snapshots + ATSSTM: + description: Auxiliary Timestamp Snapshot Trigger Missed + ATSSTN: + description: Auxiliary Timestamp Snapshot Trigger Identifier + TXTSSIS: + description: Tx Timestamp Status Interrupt Status + TSTRGTERR0: + description: Timestamp Target Time Error + AUXTSTRIG: + description: Auxiliary Timestamp Trigger Snapshot + TSTARGT0: + description: Timestamp Target Time Reached + TSSOVF: + description: Timestamp Seconds Overflow +MACTxTSSNR: + _modify: + TXTSSMIS: + description: Transmit Timestamp Status Missed + TXTSSLO: + description: Transmit Timestamp Status Low +MACTxTSSSR: + _modify: + TXTSSHI: + description: Transmit Timestamp Status High +MACACR: + _modify: + ATSEN3: + description: Auxiliary Snapshot 3 Enable + ATSEN2: + description: Auxiliary Snapshot 2 Enable + ATSEN1: + description: Auxiliary Snapshot 1 Enable + ATSEN0: + description: Auxiliary Snapshot 0 Enable + ATSFC: + description: Auxiliary Snapshot FIFO Clear +MACATSNR: + _modify: + AUXTSLO: + description: Auxiliary Timestamp +MACATSSR: + _modify: + AUXTSHI: + description: Auxiliary Timestamp +MACTSIACR: + _modify: + OSTIAC: + description: One-Step Timestamp Ingress Asymmetry Correction +MACTSEACR: + _modify: + OSTEAC: + description: One-Step Timestamp Egress Asymmetry Correction +MACTSICNR: + _modify: + TSIC: + description: Timestamp Ingress Correction +MACTSECNR: + _modify: + TSEC: + description: Timestamp Egress Correction +MACPPSCR: + _modify: + TRGTMODSEL0: + description: Target Time Register Mode for PPS Output + PPSEN0: + description: Flexible PPS Output Mode Enable + PPSCTRL: + description: Flexible PPS Output (ptp_pps_o[0]) Control or PPSCTRL PPS Output Frequency Control if PPSEN0 is cleared +MACPPSTTSR: + _modify: + TSTRH0: + description: PPS Target Time Seconds Register +MACPPSTTNR: + _modify: + TRGTBUSY0: + description: PPS Target Time Register Busy + TTSL0: + description: Target Time Low for PPS Register +MACPPSIR: + _modify: + PPSINT0: + description: PPS Output Signal Interval +MACPPSWR: + _modify: + PPSWIDTH0: + description: PPS Output Signal Width +MACPOCR: + _modify: + DN: + description: Domain Number + DRRDIS: + description: Disable PTO Delay Request/Response response generation + APDREQTRIG: + description: Automatic PTP Pdelay_Req message Trigger + ASYNCTRIG: + description: Automatic PTP SYNC message Trigger + APDREQEN: + description: Automatic PTP Pdelay_Req message Enable + ASYNCEN: + description: Automatic PTP SYNC message Enable + PTOEN: + description: PTP Offload Enable +MACSPI0R: + _modify: + SPI0: + description: Source Port Identity 0 +MACSPI1R: + _modify: + SPI1: + description: Source Port Identity 1 +MACSPI2R: + _modify: + SPI2: + description: Source Port Identity 2 +MACLMIR: + _modify: + LMPDRI: + description: Log Min Pdelay_Req Interval + DRSYNCR: + description: Delay_Req to SYNC Ratio + LSI: + description: Log Sync Interval +MMC_CONTROL: + _modify: + UCDBC: + description: Update MMC Counters for Dropped Broadcast Packets + CNTPRSTLVL: + description: Full-Half Preset + CNTPRST: + description: Counters Preset + CNTFREEZ: + description: MMC Counter Freeze + RSTONRD: + description: Reset on Read + CNTSTOPRO: + description: Counter Stop Rollover + CNTRST: + description: Counters Reset +MMC_RX_INTERRUPT: + _modify: + RXLPITRCIS: + description: MMC Receive LPI transition counter interrupt status + RXLPIUSCIS: + description: MMC Receive LPI microsecond counter interrupt status + RXUCGPIS: + description: MMC Receive Unicast Good Packet Counter Interrupt Status + RXALGNERPIS: + description: MMC Receive Alignment Error Packet Counter Interrupt Status + RXCRCERPIS: + description: MMC Receive CRC Error Packet Counter Interrupt Status +MMC_TX_INTERRUPT: + _modify: + TXLPITRCIS: + description: MMC Transmit LPI transition counter interrupt status + TXLPIUSCIS: + description: MMC Transmit LPI microsecond counter interrupt status + TXGPKTIS: + description: MMC Transmit Good Packet Counter Interrupt Status + TXMCOLGPIS: + description: MMC Transmit Multiple Collision Good Packet Counter Interrupt Status + TXSCOLGPIS: + description: MMC Transmit Single Collision Good Packet Counter Interrupt Status +MMC_RX_INTERRUPT_MASK: + _modify: + RXLPITRCIM: + description: MMC Receive LPI transition counter interrupt Mask + RXLPIUSCIM: + description: MMC Receive LPI microsecond counter interrupt Mask + RXUCGPIM: + description: MMC Receive Unicast Good Packet Counter Interrupt Mask + RXALGNERPIM: + description: MMC Receive Alignment Error Packet Counter Interrupt Mask + RXCRCERPIM: + description: MMC Receive CRC Error Packet Counter Interrupt Mask +MMC_TX_INTERRUPT_MASK: + _modify: + TXLPITRCIM: + description: MMC Transmit LPI transition counter interrupt Mask + TXLPIUSCIM: + description: MMC Transmit LPI microsecond counter interrupt Mask + TXGPKTIM: + description: MMC Transmit Good Packet Counter Interrupt Mask + TXMCOLGPIM: + description: MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask + TXSCOLGPIM: + description: MMC Transmit Single Collision Good Packet Counter Interrupt Mask diff --git a/devices/common_patches/h7_ethernet_desc_mtl.yaml b/devices/patches/ethernet/h7_desc_mtl.yaml similarity index 100% rename from devices/common_patches/h7_ethernet_desc_mtl.yaml rename to devices/patches/ethernet/h7_desc_mtl.yaml diff --git a/devices/patches/ethernet/h7_dma.yaml b/devices/patches/ethernet/h7_dma.yaml new file mode 100644 index 000000000..6f8cc8871 --- /dev/null +++ b/devices/patches/ethernet/h7_dma.yaml @@ -0,0 +1,380 @@ +# Add H7 Ethernet DMA peripheral + +_add: + Ethernet_DMA: + description: Ethernet DMA + baseAddress: 0x40029000 + registers: + DMAMR: + description: DMA mode register + addressOffset: 0x0000 + resetValue: 0x00000000 + fields: + INTM: + description: Interrupt Mode + bitOffset: 16 + bitWidth: 2 + PR: + description: Priority ratio + bitOffset: 12 + bitWidth: 3 + TXPR: + description: Transmit priority + bitOffset: 11 + bitWidth: 1 + DA: + description: DMA Tx or Rx Arbitration Scheme + bitOffset: 1 + bitWidth: 1 + SWR: + description: Software Reset + bitOffset: 0 + bitWidth: 1 + DMASBMR: + description: System bus mode register + addressOffset: 0x0004 + resetValue: 0x01010000 + fields: + RB: + description: Rebuild INCRx Burst + bitOffset: 15 + bitWidth: 1 + MB: + description: Mixed Burst + bitOffset: 14 + bitWidth: 1 + AAL: + description: Address-Aligned Beats + bitOffset: 12 + bitWidth: 1 + FB: + description: Fixed Burst Length + bitOffset: 0 + bitWidth: 1 + DMAISR: + description: Interrupt status register + addressOffset: 0x0008 + resetValue: 0x00000000 + fields: + MACIS: + description: MAC Interrupt Status + bitOffset: 17 + bitWidth: 1 + MTLIS: + description: MTL Interrupt Status + bitOffset: 16 + bitWidth: 1 + DC0IS: + description: DMA Channel Interrupt Status + bitOffset: 0 + bitWidth: 1 + DMADSR: + description: Debug status register + addressOffset: 0x000C + resetValue: 0x00000000 + fields: + TPS0: + description: DMA Channel Transmit Process State + bitOffset: 12 + bitWidth: 4 + RPS0: + description: DMA Channel Receive Process State + bitOffset: 8 + bitWidth: 4 + AXWHSTS: + description: AHB Master Write Channel + bitOffset: 0 + bitWidth: 1 + DMACCR: + description: Channel control register + addressOffset: 0x0100 + resetValue: 0x00000000 + fields: + DSL: + description: Descriptor Skip Length + bitOffset: 18 + bitWidth: 3 + PBLX8: + description: 8xPBL mode + bitOffset: 16 + bitWidth: 1 + MSS: + description: Maximum Segment Size + bitOffset: 0 + bitWidth: 14 + DMACTxCR: + description: Channel transmit control register + addressOffset: 0x0104 + resetValue: 0x00000000 + fields: + TXPBL: + description: Transmit Programmable Burst Length + bitOffset: 16 + bitWidth: 6 + TSE: + description: TCP Segmentation Enabled + bitOffset: 12 + bitWidth: 1 + OSF: + description: Operate on Second Packet + bitOffset: 4 + bitWidth: 1 + ST: + description: Start or Stop Transmission Command + bitOffset: 0 + bitWidth: 1 + DMACRxCR: + description: Channel receive control register + addressOffset: 0x0108 + resetValue: 0x00000000 + fields: + RPF: + description: DMA Rx Channel Packet Flush + bitOffset: 31 + bitWidth: 1 + RXPBL: + description: Receive Programmable Burst Length + bitOffset: 16 + bitWidth: 6 + RBSZ: + description: Receive Buffer size + bitOffset: 1 + bitWidth: 14 + SR: + description: Start or Stop Receive + bitOffset: 0 + bitWidth: 1 + DMACTxDLAR: + description: Channel Tx descriptor list address register + addressOffset: 0x0114 + resetValue: 0x00000000 + fields: + TDESLA: + description: Start of Transmit List + bitOffset: 2 + bitWidth: 30 + DMACRxDLAR: + description: Channel Rx descriptor list address register + addressOffset: 0x011C + resetValue: 0x00000000 + fields: + RDESLA: + description: Start of Receive List + bitOffset: 2 + bitWidth: 30 + DMACTxDTPR: + description: Channel Tx descriptor tail pointer register + addressOffset: 0x0120 + resetValue: 0x00000000 + fields: + TDT: + description: Transmit Descriptor Tail Pointer + bitOffset: 2 + bitWidth: 30 + DMACRxDTPR: + description: Channel Rx descriptor tail pointer register + addressOffset: 0x0128 + resetValue: 0x00000000 + fields: + RDT: + description: Receive Descriptor Tail Pointer + bitOffset: 2 + bitWidth: 30 + DMACTxRLR: + description: Channel Tx descriptor ring length register + addressOffset: 0x012C + resetValue: 0x00000000 + fields: + TDRL: + description: Transmit Descriptor Ring Length + bitOffset: 0 + bitWidth: 10 + DMACRxRLR: + description: Channel Rx descriptor ring length register + addressOffset: 0x0130 + resetValue: 0x00000000 + fields: + RDRL: + description: Receive Descriptor Ring Length + bitOffset: 0 + bitWidth: 10 + DMACIER: + description: Channel interrupt enable register + addressOffset: 0x0134 + resetValue: 0x00000000 + fields: + NIE: + description: Normal Interrupt Summary Enable + bitOffset: 15 + bitWidth: 1 + AIE: + description: Abnormal Interrupt Summary Enable + bitOffset: 14 + bitWidth: 1 + CDEE: + description: Context Descriptor Error Enable + bitOffset: 13 + bitWidth: 1 + FBEE: + description: Fatal Bus Error Enable + bitOffset: 12 + bitWidth: 1 + ERIE: + description: Early Receive Interrupt Enable + bitOffset: 11 + bitWidth: 1 + ETIE: + description: Early Transmit Interrupt Enable + bitOffset: 10 + bitWidth: 1 + RWTE: + description: Receive Watchdog Timeout Enable + bitOffset: 9 + bitWidth: 1 + RSE: + description: Receive Stopped Enable + bitOffset: 8 + bitWidth: 1 + RBUE: + description: Receive Buffer Unavailable Enable + bitOffset: 7 + bitWidth: 1 + RIE: + description: Receive Interrupt Enable + bitOffset: 6 + bitWidth: 1 + TBUE: + description: Transmit Buffer Unavailable Enable + bitOffset: 2 + bitWidth: 1 + TXSE: + description: Transmit Stopped Enable + bitOffset: 1 + bitWidth: 1 + TIE: + description: Transmit Interrupt Enable + bitOffset: 0 + bitWidth: 1 + DMACRxIWTR: + description: Channel Rx interrupt watchdog timer register + addressOffset: 0x0138 + resetValue: 0x00000000 + fields: + RWT: + description: Receive Interrupt Watchdog Timer Count + bitOffset: 0 + bitWidth: 8 + DMACCATxDR: + description: Channel current application transmit descriptor register + addressOffset: 0x0144 + resetValue: 0x00000000 + fields: + CURTDESAPTR: + description: Application Transmit Descriptor Address Pointer + bitOffset: 0 + bitWidth: 32 + DMACCARxDR: + description: Channel current application receive descriptor register + addressOffset: 0x014C + resetValue: 0x00000000 + fields: + CURRDESAPTR: + description: Application Receive Descriptor Address Pointer + bitOffset: 0 + bitWidth: 32 + DMACCATxBR: + description: Channel current application transmit buffer register + addressOffset: 0x0154 + resetValue: 0x00000000 + fields: + CURTBUFAPTR: + description: Application Transmit Buffer Address Pointer + bitOffset: 0 + bitWidth: 32 + DMACCARxBR: + description: Channel current application receive buffer register + addressOffset: 0x015C + resetValue: 0x00000000 + fields: + CURRBUFAPTR: + description: Application Receive Buffer Address Pointer + bitOffset: 0 + bitWidth: 32 + DMACSR: + description: Channel status register + addressOffset: 0x0160 + resetValue: 0x00000000 + fields: + REB: + description: Rx DMA Error Bits + bitOffset: 19 + bitWidth: 3 + TEB: + description: Tx DMA Error Bits + bitOffset: 16 + bitWidth: 3 + NIS: + description: Normal Interrupt Summary + bitOffset: 15 + bitWidth: 1 + AIS: + description: Abnormal Interrupt Summary + bitOffset: 14 + bitWidth: 1 + CDE: + description: Context Descriptor Error + bitOffset: 13 + bitWidth: 1 + FBE: + description: Fatal Bus Error + bitOffset: 12 + bitWidth: 1 + ERI: + description: Early Receive Interrupt + bitOffset: 11 + bitWidth: 1 + ETI: + description: Early Transmit Interrupt + bitOffset: 10 + bitWidth: 1 + RWT: + description: Receive Watchdog Timeout + bitOffset: 9 + bitWidth: 1 + RPS: + description: Receive Process Stopped + bitOffset: 8 + bitWidth: 1 + RBU: + description: Receive Buffer Unavailable + bitOffset: 7 + bitWidth: 1 + RI: + description: Receive Interrupt + bitOffset: 6 + bitWidth: 1 + TBU: + description: Transmit Buffer Unavailable + bitOffset: 2 + bitWidth: 1 + TPS: + description: Transmit Process Stopped + bitOffset: 1 + bitWidth: 1 + TI: + description: Transmit Interrupt + bitOffset: 0 + bitWidth: 1 + DMACMFCR: + description: Channel missed frame count register + addressOffset: 0x016C + resetValue: 0x00000000 + fields: + MFCO: + description: Overflow status of the MFC Counter + bitOffset: 15 + bitWidth: 1 + MFC: + description: Dropped Packet Counters + bitOffset: 0 + bitWidth: 11 diff --git a/devices/patches/ethernet/h7_dma_mr.yaml b/devices/patches/ethernet/h7_dma_mr.yaml new file mode 100644 index 000000000..434348dbd --- /dev/null +++ b/devices/patches/ethernet/h7_dma_mr.yaml @@ -0,0 +1,17 @@ +Ethernet_DMA: + DMAMR: + _modify: + INTM: + bitWidth: 2 + PR: + access: read-write + TXPR: + access: read-write + DA: + access: read-write + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write diff --git a/devices/patches/ethernet/h7_mac.yaml b/devices/patches/ethernet/h7_mac.yaml new file mode 100644 index 000000000..28ef263ea --- /dev/null +++ b/devices/patches/ethernet/h7_mac.yaml @@ -0,0 +1,10 @@ +Ethernet_MAC: + MMC_TX_INTERRUPT_MASK: + _modify: + TXLPITRCIM: + access: read-write + + MMC_RX_INTERRUPT_MASK: + _modify: + RXLPITRCIM: + access: read-write diff --git a/devices/common_patches/h7_ethernet_mtl.yaml b/devices/patches/ethernet/h7_mtl.yaml similarity index 100% rename from devices/common_patches/h7_ethernet_mtl.yaml rename to devices/patches/ethernet/h7_mtl.yaml diff --git a/devices/patches/ethernet/mac_lpiet_3.yaml b/devices/patches/ethernet/mac_lpiet_3.yaml new file mode 100644 index 000000000..bc464067c --- /dev/null +++ b/devices/patches/ethernet/mac_lpiet_3.yaml @@ -0,0 +1,4 @@ +MACLETR: + _modify: + LPIET: + bitOffset: 3 diff --git a/devices/patches/ethernet/mac_regs.yaml b/devices/patches/ethernet/mac_regs.yaml new file mode 100644 index 000000000..0fad20d30 --- /dev/null +++ b/devices/patches/ethernet/mac_regs.yaml @@ -0,0 +1,65 @@ +Ethernet_MAC: + MACFFR: + _modify: + SAIF: + bitOffset: 8 + SAF: + bitOffset: 9 + HPF: + bitOffset: 10 + MACMIIDR: + _modify: + "TD,MD": + name: MD + MACDBGR: + _delete: + - "*" + _add: + TFF: + description: Tx FIFO full + bitOffset: 25 + bitWidth: 1 + TFNE: + description: Tx FIFO not empty + bitOffset: 24 + bitWidth: 1 + TFWA: + description: Tx FIFO write active + bitOffset: 22 + bitWidth: 1 + TFRS: + description: Tx FIFO read status + bitOffset: 20 + bitWidth: 2 + MTP: + description: MAC transmitter in pause + bitOffset: 19 + bitWidth: 1 + MTFCS: + description: MAC transmit frame controller status + bitOffset: 17 + bitWidth: 2 + MMTEA: + description: MAC MII transmit engine active + bitOffset: 16 + bitWidth: 1 + RFFL: + description: Rx FIFO fill level + bitOffset: 8 + bitWidth: 2 + RFRCS: + description: Rx FIFO read controller status + bitOffset: 5 + bitWidth: 2 + RFWRA: + description: Rx FIFO write controller active + bitOffset: 4 + bitWidth: 1 + MSFRWCS: + description: MAC small FIFO read/write controllers status + bitOffset: 1 + bitWidth: 2 + MMRPEA: + description: MAC MII receive protocol engine active + bitOffset: 0 + bitWidth: 1 diff --git a/devices/patches/ethernet/mmc.yaml b/devices/patches/ethernet/mmc.yaml new file mode 100644 index 000000000..22347cadd --- /dev/null +++ b/devices/patches/ethernet/mmc.yaml @@ -0,0 +1,6 @@ +Ethernet_MMC: + MMCTIMR: + _modify: + TGFM: + # SVDs for F2, F4, and F7 have TGFM in position 16 instead of 21. + bitOffset: 21 diff --git a/devices/patches/exti/add_fpu_interrupt.yaml b/devices/patches/exti/add_fpu_interrupt.yaml new file mode 100644 index 000000000..1c40a4761 --- /dev/null +++ b/devices/patches/exti/add_fpu_interrupt.yaml @@ -0,0 +1,5 @@ +_add: + _interrupts: + FPU: + description: Floating point unit interrupt + value: 81 diff --git a/devices/patches/exti/exti4_5.yaml b/devices/patches/exti/exti4_5.yaml new file mode 100644 index 000000000..300307f08 --- /dev/null +++ b/devices/patches/exti/exti4_5.yaml @@ -0,0 +1,5 @@ +_modify: + _interrupts: + EXTI4_5: + name: EXTI4_15 + description: EXTI line 4 to 15 interrupt diff --git a/devices/patches/exti/exti_rename.yaml b/devices/patches/exti/exti_rename.yaml new file mode 100644 index 000000000..53770b6d2 --- /dev/null +++ b/devices/patches/exti/exti_rename.yaml @@ -0,0 +1,40 @@ +EXTICR1: + _modify: + EXTI0_7: + name: EXTI0 + EXTI8_15: + name: EXTI1 + EXTI16_23: + name: EXTI2 + EXTI24_31: + name: EXTI3 +EXTICR2: + _modify: + EXTI0_7: + name: EXTI4 + EXTI8_15: + name: EXTI5 + EXTI16_23: + name: EXTI6 + EXTI24_31: + name: EXTI7 +EXTICR3: + _modify: + EXTI0_7: + name: EXTI8 + EXTI8_15: + name: EXTI9 + EXTI16_23: + name: EXTI10 + EXTI24_31: + name: EXTI11 +EXTICR4: + _modify: + EXTI0_7: + name: EXTI12 + EXTI8_15: + name: EXTI13 + EXTI16_23: + name: EXTI14 + EXTI24_31: + name: EXTI15 diff --git a/devices/patches/exti/f3_offset.yaml b/devices/patches/exti/f3_offset.yaml new file mode 100644 index 000000000..58e831b99 --- /dev/null +++ b/devices/patches/exti/f3_offset.yaml @@ -0,0 +1,13 @@ +_modify: + IMR2: + addressOffset: 0x20 + EMR2: + addressOffset: 0x24 + RTSR2: + addressOffset: 0x28 + FTSR2: + addressOffset: 0x2C + SWIER2: + addressOffset: 0x30 + PR2: + addressOffset: 0x34 diff --git a/devices/patches/exti/g4.yaml b/devices/patches/exti/g4.yaml new file mode 100644 index 000000000..d16f0d9d0 --- /dev/null +++ b/devices/patches/exti/g4.yaml @@ -0,0 +1,152 @@ +RTSR1: + _delete: + - RT18 + _modify: + RT: + name: RT29 + description: Rising trigger event configuration of line 29 + bitOffset: 29 + bitWidth: 1 + _add: + RT17: + description: Rising trigger event configuration of line 17 + bitOffset: 17 + bitWidth: 1 + RT30: + description: Rising trigger event configuration of line 30 + bitOffset: 30 + bitWidth: 1 + RT31: + description: Rising trigger event configuration of line 31 + bitOffset: 31 + bitWidth: 1 +FTSR1: + _delete: + - FT18 + _add: + FT17: + description: Falling trigger event configuration of line 17 + bitOffset: 17 + bitWidth: 1 + FT29: + description: Falling trigger event configuration of line 29 + bitOffset: 29 + bitWidth: 1 + FT30: + description: Falling trigger event configuration of line 30 + bitOffset: 30 + bitWidth: 1 + FT31: + description: Falling trigger event configuration of line 31 + bitOffset: 31 + bitWidth: 1 +SWIER1: + _delete: + - SWI18 + _add: + SWI17: + description: Software Interrupt on line 17 + bitOffset: 17 + bitWidth: 1 +PR1: + _delete: + - PIF18 + _add: + PIF17: + description: Pending bit 17 + bitOffset: 17 + bitWidth: 1 +IMR2: + _delete: + - IM38 + - IM39 +EMR2: + _delete: + - EM38 + - EM39 + _add: + EM41: + description: Event mask on external/internal line 41 + bitOffset: 9 + bitWidth: 1 + EM42: + description: Event mask on external/internal line 42 + bitOffset: 10 + bitWidth: 1 + EM43: + description: Event mask on external/internal line 43 + bitOffset: 11 + bitWidth: 1 +RTSR2: + _delete: + - RT38 + - RT39 +FTSR2: + _delete: + - FT35 + - FT36 + - FT37 + - FT38 + _add: + FT32: + description: Falling trigger event configuration of line 32 + bitOffset: 0 + bitWidth: 1 + FT33: + description: Falling trigger event configuration of line 33 + bitOffset: 1 + bitWidth: 1 + FT40: + description: Falling trigger event configuration of line 40 + bitOffset: 8 + bitWidth: 1 + FT41: + description: Falling trigger event configuration of line 41 + bitOffset: 9 + bitWidth: 1 +SWIER2: + _delete: + - SWI35 + - SWI36 + - SWI37 + - SWI38 + _add: + SWI32: + description: Software interrupt on line 32 + bitOffset: 0 + bitWidth: 1 + SWI33: + description: Software interrupt on line 33 + bitOffset: 1 + bitWidth: 1 + SWI40: + description: Software interrupt on line 40 + bitOffset: 8 + bitWidth: 1 + SWI41: + description: Software interrupt on line 41 + bitOffset: 9 + bitWidth: 1 +PR2: + _delete: + - PIF35 + - PIF36 + - PIF37 + - PIF38 + _add: + PIF32: + description: Pending bit 32 + bitOffset: 0 + bitWidth: 1 + PIF33: + description: Pending bit 33 + bitOffset: 1 + bitWidth: 1 + PIF40: + description: Pending bit 40 + bitOffset: 8 + bitWidth: 1 + PIF41: + description: Pending bit 41 + bitOffset: 9 + bitWidth: 1 diff --git a/devices/patches/exti/h7_dualcore.yaml b/devices/patches/exti/h7_dualcore.yaml new file mode 100644 index 000000000..7d96a5b10 --- /dev/null +++ b/devices/patches/exti/h7_dualcore.yaml @@ -0,0 +1,870 @@ +# H7 EXTI module, for dual core parts + +_modify: + CPUIMR1: + name: C1IMR1 + CPUEMR1: + name: C1EMR1 + CPUPR1: + name: C1PR1 + CPUIMR2: + name: C1IMR2 + CPUEMR2: + name: C1EMR2 + CPUPR2: + name: C1PR2 + CPUIMR3: + name: C1IMR3 + CPUEMR3: + name: C1EMR3 + CPUPR3: + name: C1PR3 + C1PR2,C1IMR3,C1EMR3,C1PR3: + access: read-write + +_add: + C2IMR1: + description: CPU2 EXTI interrupt mask register + addressOffset: 0x00C0 + resetValue: 0xFFC00000 + fields: + MR0: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 0 + bitWidth: 1 + MR1: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 1 + bitWidth: 1 + MR2: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 2 + bitWidth: 1 + MR3: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 3 + bitWidth: 1 + MR4: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 4 + bitWidth: 1 + MR5: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 5 + bitWidth: 1 + MR6: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 6 + bitWidth: 1 + MR7: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 7 + bitWidth: 1 + MR8: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 8 + bitWidth: 1 + MR9: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 9 + bitWidth: 1 + MR10: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 10 + bitWidth: 1 + MR11: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 11 + bitWidth: 1 + MR12: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 12 + bitWidth: 1 + MR13: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 13 + bitWidth: 1 + MR14: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 14 + bitWidth: 1 + MR15: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 15 + bitWidth: 1 + MR16: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 16 + bitWidth: 1 + MR17: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 17 + bitWidth: 1 + MR18: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 18 + bitWidth: 1 + MR19: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 19 + bitWidth: 1 + MR20: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 20 + bitWidth: 1 + MR21: + description: CPU2 interrupt mask on Configurable Event input + bitOffset: 21 + bitWidth: 1 + MR22: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 22 + bitWidth: 1 + MR23: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 23 + bitWidth: 1 + MR24: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 24 + bitWidth: 1 + MR25: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 25 + bitWidth: 1 + MR26: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 26 + bitWidth: 1 + MR27: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 27 + bitWidth: 1 + MR28: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 28 + bitWidth: 1 + MR29: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 29 + bitWidth: 1 + MR30: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 30 + bitWidth: 1 + MR31: + description: CPU2 interrupt mask on Direct Event input + bitOffset: 31 + bitWidth: 1 + C2EMR1: + description: CPU2 EXTI event mask register + addressOffset: 0x00C4 + resetValue: 0x00000000 + fields: + MR0: + description: CPU2 event mask on Event input x + bitOffset: 0 + bitWidth: 1 + MR1: + description: CPU2 event mask on Event input x + bitOffset: 1 + bitWidth: 1 + MR2: + description: CPU2 event mask on Event input x + bitOffset: 2 + bitWidth: 1 + MR3: + description: CPU2 event mask on Event input x + bitOffset: 3 + bitWidth: 1 + MR4: + description: CPU2 event mask on Event input x + bitOffset: 4 + bitWidth: 1 + MR5: + description: CPU2 event mask on Event input x + bitOffset: 5 + bitWidth: 1 + MR6: + description: CPU2 event mask on Event input x + bitOffset: 6 + bitWidth: 1 + MR7: + description: CPU2 event mask on Event input x + bitOffset: 7 + bitWidth: 1 + MR8: + description: CPU2 event mask on Event input x + bitOffset: 8 + bitWidth: 1 + MR9: + description: CPU2 event mask on Event input x + bitOffset: 9 + bitWidth: 1 + MR10: + description: CPU2 event mask on Event input x + bitOffset: 10 + bitWidth: 1 + MR11: + description: CPU2 event mask on Event input x + bitOffset: 11 + bitWidth: 1 + MR12: + description: CPU2 event mask on Event input x + bitOffset: 12 + bitWidth: 1 + MR13: + description: CPU2 event mask on Event input x + bitOffset: 13 + bitWidth: 1 + MR14: + description: CPU2 event mask on Event input x + bitOffset: 14 + bitWidth: 1 + MR15: + description: CPU2 event mask on Event input x + bitOffset: 15 + bitWidth: 1 + MR16: + description: CPU2 event mask on Event input x + bitOffset: 16 + bitWidth: 1 + MR17: + description: CPU2 event mask on Event input x + bitOffset: 17 + bitWidth: 1 + MR18: + description: CPU2 event mask on Event input x + bitOffset: 18 + bitWidth: 1 + MR19: + description: CPU2 event mask on Event input x + bitOffset: 19 + bitWidth: 1 + MR20: + description: CPU2 event mask on Event input x + bitOffset: 20 + bitWidth: 1 + MR21: + description: CPU2 event mask on Event input x + bitOffset: 21 + bitWidth: 1 + MR22: + description: CPU2 event mask on Event input x + bitOffset: 22 + bitWidth: 1 + MR23: + description: CPU2 event mask on Event input x + bitOffset: 23 + bitWidth: 1 + MR24: + description: CPU2 event mask on Event input x + bitOffset: 24 + bitWidth: 1 + MR25: + description: CPU2 event mask on Event input x + bitOffset: 25 + bitWidth: 1 + MR26: + description: CPU2 event mask on Event input x + bitOffset: 26 + bitWidth: 1 + MR27: + description: CPU2 event mask on Event input x + bitOffset: 27 + bitWidth: 1 + MR28: + description: CPU2 event mask on Event input x + bitOffset: 28 + bitWidth: 1 + MR29: + description: CPU2 event mask on Event input x + bitOffset: 29 + bitWidth: 1 + MR30: + description: CPU2 event mask on Event input x + bitOffset: 30 + bitWidth: 1 + MR31: + description: CPU2 event mask on Event input x + bitOffset: 31 + bitWidth: 1 + C2PR1: + description: CPU2 EXTI pending register + addressOffset: 0x00C8 + resetValue: 0x00000000 + fields: + PR0: + description: Configurable event input pending + bitOffset: 0 + bitWidth: 1 + PR1: + description: Configurable event input pending + bitOffset: 1 + bitWidth: 1 + PR2: + description: Configurable event input pending + bitOffset: 2 + bitWidth: 1 + PR3: + description: Configurable event input pending + bitOffset: 3 + bitWidth: 1 + PR4: + description: Configurable event input pending + bitOffset: 4 + bitWidth: 1 + PR5: + description: Configurable event input pending + bitOffset: 5 + bitWidth: 1 + PR6: + description: Configurable event input pending + bitOffset: 6 + bitWidth: 1 + PR7: + description: Configurable event input pending + bitOffset: 7 + bitWidth: 1 + PR8: + description: Configurable event input pending + bitOffset: 8 + bitWidth: 1 + PR9: + description: Configurable event input pending + bitOffset: 9 + bitWidth: 1 + PR10: + description: Configurable event input pending + bitOffset: 10 + bitWidth: 1 + PR11: + description: Configurable event input pending + bitOffset: 11 + bitWidth: 1 + PR12: + description: Configurable event input pending + bitOffset: 12 + bitWidth: 1 + PR13: + description: Configurable event input pending + bitOffset: 13 + bitWidth: 1 + PR14: + description: Configurable event input pending + bitOffset: 14 + bitWidth: 1 + PR15: + description: Configurable event input pending + bitOffset: 15 + bitWidth: 1 + PR16: + description: Configurable event input pending + bitOffset: 16 + bitWidth: 1 + PR17: + description: Configurable event input pending + bitOffset: 17 + bitWidth: 1 + PR18: + description: Configurable event input pending + bitOffset: 18 + bitWidth: 1 + PR19: + description: Configurable event input pending + bitOffset: 19 + bitWidth: 1 + PR20: + description: Configurable event input pending + bitOffset: 20 + bitWidth: 1 + PR21: + description: Configurable event input pending + bitOffset: 21 + bitWidth: 1 + C2IMR2: + description: CPU2 EXTI interrupt mask register + addressOffset: 0x00D0 + resetValue: 0xFFF5FFFF + fields: + MR32: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 0 + bitWidth: 1 + MR33: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 1 + bitWidth: 1 + MR34: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 2 + bitWidth: 1 + MR35: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 3 + bitWidth: 1 + MR36: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 4 + bitWidth: 1 + MR37: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 5 + bitWidth: 1 + MR38: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 6 + bitWidth: 1 + MR39: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 7 + bitWidth: 1 + MR40: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 8 + bitWidth: 1 + MR41: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 9 + bitWidth: 1 + MR42: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 10 + bitWidth: 1 + MR43: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 11 + bitWidth: 1 + MR44: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 12 + bitWidth: 1 + MR46: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 14 + bitWidth: 1 + MR47: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 15 + bitWidth: 1 + MR48: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 16 + bitWidth: 1 + MR49: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 17 + bitWidth: 1 + MR50: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 18 + bitWidth: 1 + MR51: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 19 + bitWidth: 1 + MR52: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 20 + bitWidth: 1 + MR53: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 21 + bitWidth: 1 + MR54: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 22 + bitWidth: 1 + MR55: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 23 + bitWidth: 1 + MR56: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 24 + bitWidth: 1 + MR57: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 25 + bitWidth: 1 + MR58: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 26 + bitWidth: 1 + MR59: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 27 + bitWidth: 1 + MR60: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 28 + bitWidth: 1 + MR61: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 29 + bitWidth: 1 + MR62: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 30 + bitWidth: 1 + MR63: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 31 + bitWidth: 1 + C2EMR2: + description: CPU2 EXTI event mask register + addressOffset: 0x00D4 + resetValue: 0x00000000 + fields: + MR32: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 0 + bitWidth: 1 + MR33: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 1 + bitWidth: 1 + MR34: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 2 + bitWidth: 1 + MR35: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 3 + bitWidth: 1 + MR36: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 4 + bitWidth: 1 + MR37: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 5 + bitWidth: 1 + MR38: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 6 + bitWidth: 1 + MR39: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 7 + bitWidth: 1 + MR40: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 8 + bitWidth: 1 + MR41: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 9 + bitWidth: 1 + MR42: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 10 + bitWidth: 1 + MR43: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 11 + bitWidth: 1 + MR44: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 12 + bitWidth: 1 + MR46: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 14 + bitWidth: 1 + MR47: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 15 + bitWidth: 1 + MR48: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 16 + bitWidth: 1 + MR49: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 17 + bitWidth: 1 + MR50: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 18 + bitWidth: 1 + MR51: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 19 + bitWidth: 1 + MR52: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 20 + bitWidth: 1 + MR53: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 21 + bitWidth: 1 + MR54: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 22 + bitWidth: 1 + MR55: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 23 + bitWidth: 1 + MR56: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 24 + bitWidth: 1 + MR57: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 25 + bitWidth: 1 + MR58: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 26 + bitWidth: 1 + MR59: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 27 + bitWidth: 1 + MR60: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 28 + bitWidth: 1 + MR61: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 29 + bitWidth: 1 + MR62: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 30 + bitWidth: 1 + MR63: + description: CPU2 interrupt Mask on Direct Event input x+32 + bitOffset: 31 + bitWidth: 1 + C2PR2: + description: CPU2 EXTI pending register + addressOffset: 0x00D8 + resetValue: 0x00000000 + fields: + PR49: + description: CPU2 configurable event inputs x+32 Pending bit + bitOffset: 17 + bitWidth: 1 + PR51: + description: CPU2 configurable event inputs x+32 Pending bit + bitOffset: 19 + bitWidth: 1 + C2IMR3: + description: CPU2 EXTI interrupt mask register + addressOffset: 0x00E0 + resetValue: 0x018BFFFF + fields: + MR64: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 0 + bitWidth: 1 + MR65: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 1 + bitWidth: 1 + MR66: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 2 + bitWidth: 1 + MR67: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 3 + bitWidth: 1 + MR68: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 4 + bitWidth: 1 + MR69: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 5 + bitWidth: 1 + MR70: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 6 + bitWidth: 1 + MR71: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 7 + bitWidth: 1 + MR72: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 8 + bitWidth: 1 + MR73: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 9 + bitWidth: 1 + MR74: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 10 + bitWidth: 1 + MR75: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 11 + bitWidth: 1 + MR76: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 12 + bitWidth: 1 + MR77: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 13 + bitWidth: 1 + MR78: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 14 + bitWidth: 1 + MR79: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 15 + bitWidth: 1 + MR80: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 16 + bitWidth: 1 + MR82: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 18 + bitWidth: 1 + MR84: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 20 + bitWidth: 1 + MR85: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 21 + bitWidth: 1 + MR86: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 22 + bitWidth: 1 + MR87: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 23 + bitWidth: 1 + MR88: + description: CPU2 interrupt Mask on Direct Event input x+64 + bitOffset: 24 + bitWidth: 1 + C2EMR3: + description: CPU2 EXTI event mask register + addressOffset: 0x00E4 + resetValue: 0x00000000 + fields: + MR64: + description: CPU2 event mask on Event input x+64 + bitOffset: 0 + bitWidth: 1 + MR65: + description: CPU2 event mask on Event input x+64 + bitOffset: 1 + bitWidth: 1 + MR66: + description: CPU2 event mask on Event input x+64 + bitOffset: 2 + bitWidth: 1 + MR67: + description: CPU2 event mask on Event input x+64 + bitOffset: 3 + bitWidth: 1 + MR68: + description: CPU2 event mask on Event input x+64 + bitOffset: 4 + bitWidth: 1 + MR69: + description: CPU2 event mask on Event input x+64 + bitOffset: 5 + bitWidth: 1 + MR70: + description: CPU2 event mask on Event input x+64 + bitOffset: 6 + bitWidth: 1 + MR71: + description: CPU2 event mask on Event input x+64 + bitOffset: 7 + bitWidth: 1 + MR72: + description: CPU2 event mask on Event input x+64 + bitOffset: 8 + bitWidth: 1 + MR73: + description: CPU2 event mask on Event input x+64 + bitOffset: 9 + bitWidth: 1 + MR74: + description: CPU2 event mask on Event input x+64 + bitOffset: 10 + bitWidth: 1 + MR75: + description: CPU2 event mask on Event input x+64 + bitOffset: 11 + bitWidth: 1 + MR76: + description: CPU2 event mask on Event input x+64 + bitOffset: 12 + bitWidth: 1 + MR77: + description: CPU2 event mask on Event input x+64 + bitOffset: 13 + bitWidth: 1 + MR78: + description: CPU2 event mask on Event input x+64 + bitOffset: 14 + bitWidth: 1 + MR79: + description: CPU2 event mask on Event input x+64 + bitOffset: 15 + bitWidth: 1 + MR80: + description: CPU2 event mask on Event input x+64 + bitOffset: 16 + bitWidth: 1 + MR82: + description: CPU2 event mask on Event input x+64 + bitOffset: 18 + bitWidth: 1 + MR84: + description: CPU2 event mask on Event input x+64 + bitOffset: 20 + bitWidth: 1 + MR85: + description: CPU2 event mask on Event input x+64 + bitOffset: 21 + bitWidth: 1 + MR86: + description: CPU2 event mask on Event input x+64 + bitOffset: 22 + bitWidth: 1 + MR87: + description: CPU2 event mask on Event input x+64 + bitOffset: 23 + bitWidth: 1 + MR88: + description: CPU2 event mask on Event input x+64 + bitOffset: 24 + bitWidth: 1 + C2PR3: + description: CPU2 EXTI pending register + addressOffset: 0x00E8 + resetValue: 0x00000000 + fields: + PR82: + description: CPU2 configurable event inputs x+64 Pending bit + bitOffset: 18 + bitWidth: 1 + PR84: + description: CPU2 configurable event inputs x+64 Pending bit + bitOffset: 20 + bitWidth: 1 + PR85: + description: CPU2 configurable event inputs x+64 Pending bit + bitOffset: 21 + bitWidth: 1 + PR86: + description: CPU2 configurable event inputs x+64 Pending bit + bitOffset: 22 + bitWidth: 1 diff --git a/devices/patches/exti/h7_singlecore.yaml b/devices/patches/exti/h7_singlecore.yaml new file mode 100644 index 000000000..5a7e9c09c --- /dev/null +++ b/devices/patches/exti/h7_singlecore.yaml @@ -0,0 +1,5 @@ +# H7 EXTI module, for single core parts + +_modify: + CPUPR2,CPUIMR3,CPUEMR3,CPUPR3: + access: read-write diff --git a/devices/patches/exti/l4+.yaml b/devices/patches/exti/l4+.yaml new file mode 100644 index 000000000..5555051a6 --- /dev/null +++ b/devices/patches/exti/l4+.yaml @@ -0,0 +1,12 @@ +IMR2: + _add: + MR40: + description: Interrupt Mask on external/internal line 40 + bitOffset: 8 + bitWidth: 1 +EMR2: + _add: + MR40: + description: Event mask on external/internal line 40 + bitOffset: 8 + bitWidth: 1 diff --git a/devices/patches/exti/split.yaml b/devices/patches/exti/split.yaml new file mode 100644 index 000000000..53f2b960e --- /dev/null +++ b/devices/patches/exti/split.yaml @@ -0,0 +1,12 @@ +IMR: + _split: [MR] +EMR: + _split: [MR] +RTSR: + _split: [TR] +FTSR: + _split: [TR] +SWIER: + _split: [SWIER] +PR: + _split: [PR] diff --git a/devices/patches/exti/wl.yaml b/devices/patches/exti/wl.yaml new file mode 100644 index 000000000..cc7919eaa --- /dev/null +++ b/devices/patches/exti/wl.yaml @@ -0,0 +1,46 @@ +RTSR1: + _add: + RT22: + description: Rising trigger event configuration bit of Configurable Event input + bitOffset: 22 + bitWidth: 1 + access: read-write + _modify: + RT21: + bitWidth: 1 + _split: [RT] +FTSR1: + _add: + FT22: + description: Falling trigger event configuration bit of Configurable Event input + bitOffset: 22 + bitWidth: 1 + access: read-write + _modify: + FT21: + bitWidth: 1 + _split: [FT] +SWIER1: + _add: + SWI22: + description: Software interrupt on event + bitOffset: 22 + bitWidth: 1 + access: read-write + _modify: + SWI21: + bitWidth: 1 + _split: [SWI] +PR1: + _add: + PIF22: + description: Configurable event inputs Pending bit + bitOffset: 22 + bitWidth: 1 + access: read-write + _modify: + PIF21: + bitWidth: 1 + _split: [PIF] +C1IMR1,IMR1: + _split: [IM] diff --git a/devices/patches/f0_syscfg_comp.yaml b/devices/patches/f0_syscfg_comp.yaml new file mode 100644 index 000000000..ae314158b --- /dev/null +++ b/devices/patches/f0_syscfg_comp.yaml @@ -0,0 +1,38 @@ +_modify: + SYSCFG_COMP: + name: SYSCFG + +SYSCFG: + _include: syscfg/f0_common.yaml + _strip: SYSCFG_ + _delete: + - COMP_CSR + CFGR1: + _add: + IR_MOD: + description: IR Modulation Envelope signal selection + bitOffset: 6 + bitWidth: 2 + TIM16_DMA_RMP2: + description: TIM16 alternate DMA request remapping bit + bitOffset: 13 + bitWidth: 1 + TIM17_DMA_RMP2: + description: TIM17 alternate DMA request remapping bit + bitOffset: 14 + bitWidth: 1 + _modify: + I2C2_FM_plus: + name: I2C2_FMP + +_include: + - ./comp/f0_common.yaml + +COMP: + CSR: + _add: + COMP1SW1: + description: Comparator 1 non inverting input DAC switch + bitOffset: 1 + bitWidth: 1 + access: read-write diff --git a/devices/patches/f7_interrupts.yaml b/devices/patches/f7_interrupts.yaml new file mode 100644 index 000000000..c1f1aa748 --- /dev/null +++ b/devices/patches/f7_interrupts.yaml @@ -0,0 +1,42 @@ +# Add the many missing interrupts for the STM32F7x5 devices. + +I2C2: + _add: + _interrupts: + I2C2_EV: + description: I2C2 event interrupt + value: 33 + I2C2_ER: + description: I2C2 error interrupt + value: 34 + +I2C3: + _add: + _interrupts: + I2C3_EV: + description: I2C3 event interrupt + value: 72 + I2C3_ER: + description: I2C3 error interrupt + value: 73 + +UART4: + _add: + _interrupts: + UART4: + description: UART4 global interrupt + value: 52 + +UART7: + _add: + _interrupts: + UART7: + description: UART7 global interrupt + value: 82 + +USART6: + _add: + _interrupts: + USART6: + description: USART6 global interrupt + value: 71 diff --git a/devices/patches/f7_lptim_interrupt.yaml b/devices/patches/f7_lptim_interrupt.yaml new file mode 100644 index 000000000..6676757a1 --- /dev/null +++ b/devices/patches/f7_lptim_interrupt.yaml @@ -0,0 +1,7 @@ +# Add missing LP_Timer1 interrupt for some STM32F7 devices. + +LPTIM1: + _modify: + _interrupts: + LPTimer1: + name: LP_Timer1 diff --git a/devices/patches/fdcan/fdcan_common.yaml b/devices/patches/fdcan/fdcan_common.yaml new file mode 100644 index 000000000..517bfe3b1 --- /dev/null +++ b/devices/patches/fdcan/fdcan_common.yaml @@ -0,0 +1,21 @@ +# Patches for the Flexible Data Rate CAN (FDCAN) on at least H7, G4 + +_modify: + "DBTP,TDCR,TSCV,TOCV,IR,IE,ILS,NDAT1,NDAT2": + access: read-write +TEST: + _modify: + "TX,LBCK": + access: read-write +RWD: + _modify: + WDC: + access: read-write +NBTP: + _modify: + TSEG2: + name: NTSEG2 +ECR: + _modify: + TREC: + name: REC diff --git a/devices/patches/fdcan/fdcan_h7.yaml b/devices/patches/fdcan/fdcan_h7.yaml new file mode 100644 index 000000000..d1b4e7320 --- /dev/null +++ b/devices/patches/fdcan/fdcan_h7.yaml @@ -0,0 +1,44 @@ +# Patches for the Flexible Data Rate CAN (FDCAN) on H7 + +_include: + - ./fdcan_common.yaml + +RXF0C: + _modify: + "F0S,F0WM": + bitWidth: 7 + _add: + F0OM: + description: FIFO 0 operation mode + bitOffset: 31 + bitWidth: 1 +RXF0S: + _modify: + F0G: + name: F0GI + F0P: + name: F0PI +RXF0A: + _modify: + FA01: + name: F0AI +RXF1C: + _add: + F1OM: + description: FIFO 1 operation mode + bitOffset: 31 + bitWidth: 1 +TTOST: + _modify: + GTP: + name: QGTP +TTCPT: + _modify: + CT: + name: CCV + +_modify: + TEST: + access: read-write + CAN_TTGTP: + name: TTGTP diff --git a/devices/patches/firewall/l4+.yaml b/devices/patches/firewall/l4+.yaml new file mode 100644 index 000000000..f4e4882e1 --- /dev/null +++ b/devices/patches/firewall/l4+.yaml @@ -0,0 +1,32 @@ +FIREWALL: + VDSSA: + # Can't even figure it out from the reference manual if this is really correct + _modify: + ADD: + bitWidth: 12 + + VDSL: + # Can't even figure it out from the reference manual if this is really correct + _modify: + LENG: + bitWidth: 12 + + CR: + VDE: + NotExecutable: [0, "Volatile data segment cannot be executed if VDS = 0"] + Executable: [1, Volatile data segment is declared executable whatever VDS bit value] + VDS: + NotShared: + [ + 0, + "Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed. If it is accessed in such a condition, a system reset will be generated by the Firewall", + ] + Shared: + [ + 1, + Volatile data segment is shared with non protected application code. It can be accessed whatever the Firewall state (opened or closed), + ] + FPA: + Reset: + [0, Any code executed outside the protected segment when the Firewall is opened will generate a system reset] + Close: [1, Any code executed outside the protected segment will close the Firewall] diff --git a/devices/patches/flash/acr/latency_16_states.yaml b/devices/patches/flash/acr/latency_16_states.yaml new file mode 100644 index 000000000..0647dfff1 --- /dev/null +++ b/devices/patches/flash/acr/latency_16_states.yaml @@ -0,0 +1,5 @@ +ACR: + _modify: + LATENCY: + bitOffset: 0 + bitWidth: 4 diff --git a/devices/patches/flash/cr/mer1_mer2.yaml b/devices/patches/flash/cr/mer1_mer2.yaml new file mode 100644 index 000000000..45476e4cf --- /dev/null +++ b/devices/patches/flash/cr/mer1_mer2.yaml @@ -0,0 +1,6 @@ +CR: + _modify: + MER1: + name: MER2 + MER: + name: MER1 diff --git a/devices/patches/flash/f3.yaml b/devices/patches/flash/f3.yaml new file mode 100644 index 000000000..2b7b8aa4a --- /dev/null +++ b/devices/patches/flash/f3.yaml @@ -0,0 +1,22 @@ +_modify: + OBR: + resetValue: 0xFFFFFF0F +ACR: + _add: + HLFCYA: + description: Flash half cycle access enable + bitOffset: 3 + bitWidth: 1 + access: read-write +SR: + _modify: + WRPRT: + name: WRPRTERR +CR: + _modify: + FORCE_OPTLOAD: + name: OBL_LAUNCH +OBR: + _modify: + BOOT1: + name: nBOOT1 diff --git a/devices/patches/flash/f3_obr_rdptr.yaml b/devices/patches/flash/f3_obr_rdptr.yaml new file mode 100644 index 000000000..3d3bb7126 --- /dev/null +++ b/devices/patches/flash/f3_obr_rdptr.yaml @@ -0,0 +1,9 @@ +OBR: + _delete: + - LEVEL1_PROT + - LEVEL2_PROT + _add: + RDPRT: + description: Read protection Level status + bitOffset: 1 + bitWidth: 2 diff --git a/devices/patches/flash/flash_boot0s.yaml b/devices/patches/flash/flash_boot0s.yaml new file mode 100644 index 000000000..87d4a54ab --- /dev/null +++ b/devices/patches/flash/flash_boot0s.yaml @@ -0,0 +1,10 @@ +OPTR: + _add: + nSWBOOT0: + description: Software BOOT0 + bitOffset: 26 + bitWidth: 1 + nBOOT0: + description: nBOOT0 option bit + bitOffset: 27 + bitWidth: 1 diff --git a/devices/patches/flash/flash_dual_bank.yaml b/devices/patches/flash/flash_dual_bank.yaml new file mode 100644 index 000000000..88150a3b7 --- /dev/null +++ b/devices/patches/flash/flash_dual_bank.yaml @@ -0,0 +1,24 @@ +# Cluster bank-specific registers + +KEYR1: + _strip_end: "1" +CR1: + _strip_end: "1" +SR1: + _strip_end: "1" +CCR1: + _strip_end: "1" +PRAR_CUR1: + _strip_end: "1" +PRAR_PRG1: + _strip_end: "1" +SCAR_CUR1: + _strip_end: "1" +SCAR_PRG1: + _strip_end: "1" +WPSN_CUR1R: + _strip_end: "1" +WPSN_PRG1R: + _strip_end: "1" +ECC_FA?R: + _strip_end: "1" diff --git a/devices/patches/flash/g0.yaml b/devices/patches/flash/g0.yaml new file mode 100644 index 000000000..54fcd8375 --- /dev/null +++ b/devices/patches/flash/g0.yaml @@ -0,0 +1,21 @@ +_modify: + # Fix access and reset values. + WRP??R: + access: read-write + resetValue: 0x000000ff +KEYR: + _modify: + KEYR: + name: KEY +OPTKEYR: + _modify: + OPTKEYR: + name: OPTKEY +SR: + _modify: + MISERR: + name: MISSERR +OPTR: + _modify: + IDWG_SW: + name: IWDG_SW diff --git a/devices/patches/flash/g4_dual_bank.yaml b/devices/patches/flash/g4_dual_bank.yaml new file mode 100644 index 000000000..019741f2c --- /dev/null +++ b/devices/patches/flash/g4_dual_bank.yaml @@ -0,0 +1,14 @@ +CR: + _add: + BKER: + description: Bank erase + bitOffset: 11 + bitWidth: 1 + MER2: + description: Bank 2 Mass erase + bitOffset: 15 + bitWidth: 1 + SEC_PROT2: + description: Securable memory area protection bit for bank 2. + bitOffset: 29 + bitWidth: 1 diff --git a/devices/patches/flash/g4_dual_bank_optr.yaml b/devices/patches/flash/g4_dual_bank_optr.yaml new file mode 100644 index 000000000..76396285f --- /dev/null +++ b/devices/patches/flash/g4_dual_bank_optr.yaml @@ -0,0 +1,13 @@ +_modify: + OPTR: + resetValue: 0xFFEFF8AA +OPTR: + _add: + DBANK: + description: Single or dual bank mode + bitOffset: 22 + bitWidth: 1 + BFB2: + description: Bank to boot from + bitOffset: 20 + bitWidth: 1 diff --git a/devices/patches/flash/h7_dualcore.yaml b/devices/patches/flash/h7_dualcore.yaml new file mode 100644 index 000000000..92c6ee8f1 --- /dev/null +++ b/devices/patches/flash/h7_dualcore.yaml @@ -0,0 +1,1277 @@ +# Dual Core H7 Flash Peripheral + +_delete: + - Flash + +_add: + FLASH: + description: Embedded Flash Memory + groupName: FLASH + baseAddress: 0x52002000 + addressBlock: + offset: 0x000 + size: 0x200 + usage: registers + registers: + ACR: + description: FLASH access control register + addressOffset: 0x000 + resetValue: 0x00000037 + fields: + WRHIGHFREQ: + description: Flash signal delay + bitOffset: 4 + bitWidth: 2 + LATENCY: + description: Read latency + bitOffset: 0 + bitWidth: 4 + KEYR1: + description: FLASH key register for bank 1 + addressOffset: 0x004 + resetValue: 0x00000000 + access: write-only + fields: + KEY1R: + description: Bank access configuration unlock key + bitOffset: 0 + bitWidth: 32 + OPTKEYR: + description: FLASH option key register + addressOffset: 0x008 + resetValue: 0x00000000 + access: write-only + fields: + OPTKEYR: + description: FLASH option bytes control access unlock key + bitOffset: 0 + bitWidth: 32 + CR1: + description: FLASH control register for bank 1 + addressOffset: 0x00C + resetValue: 0x00000031 + fields: + CRCRDERRIE: + description: Bank 1 CRC read error interrupt enable bit + bitOffset: 28 + bitWidth: 1 + CRCENDIE: + description: Bank 1 CRC end of calculation interrupt enable bit + bitOffset: 27 + bitWidth: 1 + DBECCERRIE: + description: Bank 1 ECC double detection error interrupt enable bit + bitOffset: 26 + bitWidth: 1 + SNECCERRIE: + description: Bank 1 ECC single correction error interrupt enable bit + bitOffset: 25 + bitWidth: 1 + RDSERRIE: + description: Bank 1 secure error interrupt enable bit + bitOffset: 24 + bitWidth: 1 + RDPERRIE: + description: Bank 1 read protection error interrupt enable bit + bitOffset: 23 + bitWidth: 1 + OPERRIE: + description: Bank 1 write + bitOffset: 22 + bitWidth: 1 + INCERRIE: + description: Bank 1 inconsistency error interrupt enable bit + bitOffset: 21 + bitWidth: 1 + STRBERRIE: + description: Bank 1 strobe error interrupt enable bit + bitOffset: 19 + bitWidth: 1 + PGSERRIE: + description: Bank 1 programming sequence error interrupt enable bit + bitOffset: 18 + bitWidth: 1 + WRPERRIE: + description: Bank 1 write protection error interrupt enable bit + bitOffset: 17 + bitWidth: 1 + EOPIE: + description: Bank 1 end-of-program interrupt control bit + bitOffset: 16 + bitWidth: 1 + CRC_EN: + description: Bank 1 CRC control bit + bitOffset: 15 + bitWidth: 1 + SNB: + description: Bank 1 sector erase selection number + bitOffset: 8 + bitWidth: 3 + START: + description: Bank 1 erase start control bit + bitOffset: 7 + bitWidth: 1 + FW: + description: Bank 1 write forcing control bit + bitOffset: 6 + bitWidth: 1 + PSIZE: + description: Bank 1 program size + bitOffset: 4 + bitWidth: 2 + BER: + description: Bank 1 erase request + bitOffset: 3 + bitWidth: 1 + SER: + description: Bank 1 sector erase request + bitOffset: 2 + bitWidth: 1 + PG: + description: Bank 1 internal buffer control bit + bitOffset: 1 + bitWidth: 1 + LOCK: + description: Bank 1 configuration lock bit + bitOffset: 0 + bitWidth: 1 + SR1: + description: FLASH status register for bank 1 + addressOffset: 0x010 + resetValue: 0x00000000 + fields: + CRCRDERR1: + description: Bank 1 CRC read error flag + bitOffset: 28 + bitWidth: 1 + CRCEND1: + description: Bank 1 CRC end of calculation flag + bitOffset: 27 + bitWidth: 1 + DBECCERR1: + description: Bank 1 ECC double detection error flag + bitOffset: 26 + bitWidth: 1 + SNECCERR1: + description: Bank 1 single correction error flag + bitOffset: 25 + bitWidth: 1 + RDSERR1: + description: Bank 1 secure error flag + bitOffset: 24 + bitWidth: 1 + RDPERR1: + description: Bank 1 read protection error flag + bitOffset: 23 + bitWidth: 1 + OPERR1: + description: Bank 1 write + bitOffset: 22 + bitWidth: 1 + INCERR1: + description: Bank 1 inconsistency error flag + bitOffset: 21 + bitWidth: 1 + STRBERR1: + description: Bank 1 strobe error flag + bitOffset: 19 + bitWidth: 1 + PGSERR1: + description: Bank 1 programming sequence error flag + bitOffset: 18 + bitWidth: 1 + WRPERR1: + description: Bank 1 write protection error flag + bitOffset: 17 + bitWidth: 1 + EOP1: + description: Bank 1 end-of-program flag + bitOffset: 16 + bitWidth: 1 + CRC_BUSY1: + description: Bank 1 CRC busy flag + bitOffset: 3 + bitWidth: 1 + QW1: + description: Bank 1 wait queue flag + bitOffset: 2 + bitWidth: 1 + WBNE1: + description: Bank 1 write buffer not empty flag + bitOffset: 1 + bitWidth: 1 + BSY1: + description: Bank 1 busy flag + bitOffset: 0 + bitWidth: 1 + CCR1: + description: FLASH clear control register for bank 1 + addressOffset: 0x014 + resetValue: 0x00000000 + fields: + CLR_CRCRDERR1: + description: Bank 1 CRCRDERR1 flag clear bit + bitOffset: 28 + bitWidth: 1 + CLR_CRCEND1: + description: Bank 1 CRCEND1 flag clear bit + bitOffset: 27 + bitWidth: 1 + CLR_DBECCERR1: + description: Bank 1 DBECCERR1 flag clear bit + bitOffset: 26 + bitWidth: 1 + CLR_SNECCERR1: + description: Bank 1 SNECCERR1 flag clear bit + bitOffset: 25 + bitWidth: 1 + CLR_RDSERR1: + description: Bank 1 RDSERR1 flag clear bit + bitOffset: 24 + bitWidth: 1 + CLR_RDPERR1: + description: Bank 1 RDPERR1 flag clear bit + bitOffset: 23 + bitWidth: 1 + CLR_OPERR1: + description: Bank 1 OPERR1 flag clear bit + bitOffset: 22 + bitWidth: 1 + CLR_INCERR1: + description: Bank 1 INCERR1 flag clear bit + bitOffset: 21 + bitWidth: 1 + CLR_STRBERR1: + description: Bank 1 STRBERR1 flag clear bit + bitOffset: 19 + bitWidth: 1 + CLR_PGSERR1: + description: Bank 1 PGSERR1 flag clear bit + bitOffset: 18 + bitWidth: 1 + CLR_WRPERR1: + description: Bank 1 WRPERR1 flag clear bit + bitOffset: 17 + bitWidth: 1 + CLR_EOP1: + description: Bank 1 EOP1 flag clear bit + bitOffset: 16 + bitWidth: 1 + OPTCR: + description: FLASH option control register + addressOffset: 0x018 + resetValue: 0x00000001 + fields: + SWAP_BANK: + description: Bank swapping option configuration bit + bitOffset: 31 + bitWidth: 1 + OPTCHANGEERRIE: + description: Option byte change error interrupt enable bit + bitOffset: 30 + bitWidth: 1 + MER: + description: mass erase request + bitOffset: 4 + bitWidth: 1 + OPTSTART: + description: Option byte start change option configuration bit + bitOffset: 1 + bitWidth: 1 + OPTLOCK: + description: FLASH + bitOffset: 0 + bitWidth: 1 + OPTSR_CUR: + description: FLASH option status register + addressOffset: 0x01C + resetValue: 0x00000000 + fields: + SWAP_BANK_OPT: + description: Bank swapping option status bit + bitOffset: 31 + bitWidth: 1 + OPTCHANGEERR: + description: Option byte change error flag + bitOffset: 30 + bitWidth: 1 + IO_HSLV: + description: I + bitOffset: 29 + bitWidth: 1 + NRST_STBY_D2: + description: D2 domain DStandby entry reset option status bit + bitOffset: 25 + bitWidth: 1 + NRST_STOP_D2: + description: D2 domain DStop entry reset option status bit + bitOffset: 24 + bitWidth: 1 + BOOT_CM7: + description: Arm Cortex + bitOffset: 23 + bitWidth: 1 + BOOT_CM4: + description: Arm Cortex + bitOffset: 22 + bitWidth: 1 + SECURITY: + description: Security enable option status bit + bitOffset: 21 + bitWidth: 1 + ST_RAM_SIZE: + description: ST RAM size option status + bitOffset: 19 + bitWidth: 2 + IWDG_FZ_SDBY: + description: IWDG Standby mode freeze option status bit + bitOffset: 18 + bitWidth: 1 + IWDG_FZ_STOP: + description: IWDG Stop mode freeze option status bit + bitOffset: 17 + bitWidth: 1 + RDP: + description: Readout protection level option status byte + bitOffset: 8 + bitWidth: 8 + RST_STDY_D1: + description: D1 domain DStandby entry reset option status bit + bitOffset: 7 + bitWidth: 1 + NRST_STOP_D1: + description: D1 domain DStop entry reset option status bit + bitOffset: 6 + bitWidth: 1 + IWDG2_SW: + description: IWDG2 control mode option status bit + bitOffset: 5 + bitWidth: 1 + IWDG_SW: + description: IWDG control mode option status bit + bitOffset: 4 + bitWidth: 1 + BOR_LEV: + description: Brownout level option status bit + bitOffset: 2 + bitWidth: 2 + OPT_BUSY: + description: Option byte change ongoing flag + bitOffset: 0 + bitWidth: 1 + OPTSR_PRG: + description: FLASH option status register + addressOffset: 0x020 + resetValue: 0x00000000 + fields: + SWAP_BANK_OPT: + description: Bank swapping option configuration bit + bitOffset: 31 + bitWidth: 1 + IO_HSLV: + description: I + bitOffset: 29 + bitWidth: 1 + NRST_STBY_D2: + description: D2 domain DStandby entry reset option configuration bit + bitOffset: 25 + bitWidth: 1 + NRST_STOP_D2: + description: D2 domain DStop entry reset option configuration bit + bitOffset: 24 + bitWidth: 1 + BOOT_CM7: + description: Arm Cortex + bitOffset: 23 + bitWidth: 1 + BOOT_CM4: + description: Arm Cortex + bitOffset: 22 + bitWidth: 1 + SECURITY: + description: Security enable option configuration bit + bitOffset: 21 + bitWidth: 1 + ST_RAM_SIZE: + description: ST RAM size option configuration bits + bitOffset: 19 + bitWidth: 2 + IWDG_FZ_SDBY: + description: IWDG Standby mode freeze option configuration bit + bitOffset: 18 + bitWidth: 1 + IWDG_FZ_STOP: + description: IWDG Stop mode freeze option configuration bit + bitOffset: 17 + bitWidth: 1 + RDP: + description: Readout protection level option configuration bits + bitOffset: 8 + bitWidth: 8 + NRST_STDY_D1: + description: D1 domain DStandby entry reset option configuration bit + bitOffset: 7 + bitWidth: 1 + NRST_STOP_D1: + description: D1 domain DStop entry reset option configuration bit + bitOffset: 6 + bitWidth: 1 + IWDG2_SW: + description: IWDG2 control mode option configuration bit + bitOffset: 5 + bitWidth: 1 + IWDG_SW: + description: IWDG control mode option configuration bit + bitOffset: 4 + bitWidth: 1 + BOR_LEV: + description: Brownout level option configuration bit + bitOffset: 2 + bitWidth: 2 + OPTCCR: + description: FLASH option clear control register + addressOffset: 0x024 + resetValue: 0x00000000 + fields: + CLR_OPTCHANGEERR: + description: OPTCHANGEERR reset bit + bitOffset: 30 + bitWidth: 1 + PRAR_CUR1: + description: FLASH protection address for bank 1 + addressOffset: 0x028 + resetValue: 0x00000000 + fields: + DMEP1: + description: Bank 1 PCROP protected erase enable option status bit + bitOffset: 31 + bitWidth: 1 + PROT_AREA_END1: + description: Bank 1 PCROP area end status bits + bitOffset: 16 + bitWidth: 12 + PROT_AREA_START1: + description: Bank 1 PCROP area start status bits + bitOffset: 0 + bitWidth: 12 + PRAR_PRG1: + description: FLASH protection address for bank 1 + addressOffset: 0x02C + resetValue: 0x00000000 + fields: + DMEP1: + description: Bank 1 PCROP protected erase enable option configuration bit + bitOffset: 31 + bitWidth: 1 + PROT_AREA_END1: + description: Bank 1 PCROP area end configuration bits + bitOffset: 16 + bitWidth: 12 + PROT_AREA_START1: + description: Bank 1 PCROP area start configuration bits + bitOffset: 0 + bitWidth: 12 + SCAR_CUR1: + description: FLASH secure address for bank 1 + addressOffset: 0x030 + resetValue: 0x00000000 + fields: + DMES1: + description: Bank 1 secure access protected erase enable option status bit + bitOffset: 31 + bitWidth: 1 + SEC_AREA_END1: + description: Bank 1 secure-only area end status bits + bitOffset: 16 + bitWidth: 12 + SEC_AREA_START1: + description: Bank 1 secure-only area start status bits + bitOffset: 0 + bitWidth: 12 + SCAR_PRG1: + description: FLASH secure address for bank 1 + addressOffset: 0x034 + resetValue: 0x00000000 + fields: + DMES1: + description: Bank 1 secure access protected erase enable option configuration bit + bitOffset: 31 + bitWidth: 1 + SEC_AREA_END1: + description: Bank 1 secure-only area end configuration bits + bitOffset: 16 + bitWidth: 12 + SEC_AREA_START1: + description: Bank 1 secure-only area start configuration bits + bitOffset: 0 + bitWidth: 12 + WPSN_CUR1R: + description: FLASH write sector protection for bank 1 + addressOffset: 0x038 + resetValue: 0x00000000 + fields: + WRPSn1: + description: Bank 1 sector write protection option status byte + bitOffset: 0 + bitWidth: 8 + WPSN_PRG1R: + description: FLASH write sector protection for bank 1 + addressOffset: 0x03C + resetValue: 0x00000000 + fields: + WRPSn1: + description: Bank 1 sector write protection option status byte + bitOffset: 0 + bitWidth: 8 + BOOT7_CURR: + description: FLASH register boot address for Arm Cortex-M7 core + addressOffset: 0x040 + resetValue: 0x00000000 + fields: + BOOT_CM7_ADD1: + description: Arm Cortex-M7 boot address 1 + bitOffset: 16 + bitWidth: 16 + BOOT_CM7_ADD0: + description: Arm Cortex-M7 boot address 0 + bitOffset: 0 + bitWidth: 16 + BOOT7_PRGR: + description: FLASH register boot address for Arm Cortex-M7 core + addressOffset: 0x044 + resetValue: 0x00000000 + fields: + BOOT_CM7_ADD1: + description: Arm Cortex-M7 boot address 1 configuration + bitOffset: 16 + bitWidth: 16 + BOOT_CM7_ADD0: + description: Arm Cortex-M7 boot address 0 configuration + bitOffset: 0 + bitWidth: 16 + BOOT4_CURR: + description: FLASH register boot address for Arm Cortex-M4 core + addressOffset: 0x048 + resetValue: 0x00000000 + fields: + BOOT_CM4_ADD1: + description: Arm Cortex-M4 boot address 1 + bitOffset: 16 + bitWidth: 16 + BOOT_CM4_ADD0: + description: Arm Cortex-M4 boot address 0 + bitOffset: 0 + bitWidth: 16 + BOOT4_PRGR: + description: FLASH register boot address for Arm Cortex-M4 core + addressOffset: 0x04C + resetValue: 0x00000000 + fields: + BOOT_CM4_ADD1: + description: Arm Cortex-M4 boot address 1 configuration + bitOffset: 16 + bitWidth: 16 + BOOT_CM4_ADD0: + description: Arm Cortex-M4 boot address 0 configuration + bitOffset: 0 + bitWidth: 16 + CRCCR1: + description: FLASH CRC control register for bank 1 + addressOffset: 0x050 + resetValue: 0x001C0000 + fields: + ALL_BANK: + description: Bank 1 CRC select bit + bitOffset: 22 + bitWidth: 1 + CRC_BURST: + description: Bank 1 CRC burst size + bitOffset: 20 + bitWidth: 2 + CLEAN_CRC: + description: Bank 1 CRC clear bit + bitOffset: 17 + bitWidth: 1 + START_CRC: + description: Bank 1 CRC start bit + bitOffset: 16 + bitWidth: 1 + CLEAN_SECT: + description: Bank 1 CRC sector list clear bit + bitOffset: 10 + bitWidth: 1 + ADD_SECT: + description: Bank 1 CRC sector select bit + bitOffset: 9 + bitWidth: 1 + CRC_BY_SECT: + description: Bank 1 CRC sector mode select bit + bitOffset: 8 + bitWidth: 1 + CRC_SECT: + description: Bank 1 CRC sector number + bitOffset: 0 + bitWidth: 3 + CRCSADD1R: + description: FLASH CRC start address register for bank 1 + addressOffset: 0x054 + resetValue: 0x00000000 + fields: + CRC_START_ADDR: + description: CRC start address on bank 1 + bitOffset: 2 + bitWidth: 18 + CRCEADD1R: + description: FLASH CRC end address register for bank 1 + addressOffset: 0x058 + resetValue: 0x00000000 + fields: + CRC_END_ADDR: + description: CRC end address on bank 1 + bitOffset: 2 + bitWidth: 18 + CRCDATAR: + description: FLASH CRC data register + addressOffset: 0x05C + resetValue: 0x00000000 + fields: + CRC_DATA: + description: CRC result + bitOffset: 0 + bitWidth: 32 + ECC_FA1R: + description: FLASH ECC fail address for bank 1 + addressOffset: 0x060 + resetValue: 0x00000000 + fields: + FAIL_ECC_ADDR1: + description: Bank 1 ECC error address + bitOffset: 0 + bitWidth: 15 + ACR_: + description: FLASH access control register + addressOffset: 0x100 + resetValue: 0x00000037 + fields: + WRHIGHFREQ: + description: Flash signal delay + bitOffset: 4 + bitWidth: 2 + LATENCY: + description: Read latency + bitOffset: 0 + bitWidth: 4 + KEYR2: + description: FLASH key register for bank 2 + addressOffset: 0x104 + resetValue: 0x00000000 + access: write-only + fields: + KEYR: + description: Bank access configuration unlock key + bitOffset: 0 + bitWidth: 32 + OPTKEYR_: + description: FLASH option key register + addressOffset: 0x108 + resetValue: 0x00000000 + access: write-only + fields: + OPTKEYR: + description: FLASH option bytes control access unlock key + bitOffset: 0 + bitWidth: 32 + + CR2: + description: FLASH control register for bank 2 + addressOffset: 0x10C + resetValue: 0x00000031 + fields: + CRCRDERRIE: + description: Bank 2 CRC read error interrupt enable bit + bitOffset: 28 + bitWidth: 1 + CRCENDIE: + description: Bank 2 CRC end of calculation interrupt enable bit + bitOffset: 27 + bitWidth: 1 + DBECCERRIE: + description: Bank 2 ECC double detection error interrupt enable bit + bitOffset: 26 + bitWidth: 1 + SNECCERRIE: + description: Bank 2 ECC single correction error interrupt enable bit + bitOffset: 25 + bitWidth: 1 + RDSERRIE: + description: Bank 2 secure error interrupt enable bit + bitOffset: 24 + bitWidth: 1 + RDPERRIE: + description: Bank 2 read protection error interrupt enable bit + bitOffset: 23 + bitWidth: 1 + OPERRIE: + description: Bank 2 write + bitOffset: 22 + bitWidth: 1 + INCERRIE: + description: Bank 2 inconsistency error interrupt enable bit + bitOffset: 21 + bitWidth: 1 + STRBERRIE: + description: Bank 2 strobe error interrupt enable bit + bitOffset: 19 + bitWidth: 1 + PGSERRIE: + description: Bank 2 programming sequence error interrupt enable bit + bitOffset: 18 + bitWidth: 1 + WRPERRIE: + description: Bank 2 write protection error interrupt enable bit + bitOffset: 17 + bitWidth: 1 + EOPIE: + description: Bank 2 end-of-program interrupt control bit + bitOffset: 16 + bitWidth: 1 + CRC_EN: + description: Bank 2 CRC control bit + bitOffset: 15 + bitWidth: 1 + SNB: + description: Bank 2 sector erase selection number + bitOffset: 8 + bitWidth: 3 + START: + description: Bank 2 erase start control bit + bitOffset: 7 + bitWidth: 1 + FW: + description: Bank 2 write forcing control bit + bitOffset: 6 + bitWidth: 1 + PSIZE: + description: Bank 2 program size + bitOffset: 4 + bitWidth: 2 + BER: + description: Bank 2 erase request + bitOffset: 3 + bitWidth: 1 + SER: + description: Bank 2 sector erase request + bitOffset: 2 + bitWidth: 1 + PG: + description: Bank 2 internal buffer control bit + bitOffset: 1 + bitWidth: 1 + LOCK: + description: Bank 2 configuration lock bit + bitOffset: 0 + bitWidth: 1 + SR2: + description: FLASH status register for bank 2 + addressOffset: 0x110 + resetValue: 0x00000000 + fields: + CRCRDERR2: + description: Bank 2 CRC read error flag + bitOffset: 28 + bitWidth: 1 + CRCEND2: + description: Bank 2 CRC end of calculation flag + bitOffset: 27 + bitWidth: 1 + DBECCERR2: + description: Bank 2 ECC double detection error flag + bitOffset: 26 + bitWidth: 1 + SNECCERR2: + description: Bank 2 single correction error flag + bitOffset: 25 + bitWidth: 1 + RDSERR2: + description: Bank 2 secure error flag + bitOffset: 24 + bitWidth: 1 + RDPERR2: + description: Bank 2 read protection error flag + bitOffset: 23 + bitWidth: 1 + OPERR2: + description: Bank 2 write + bitOffset: 22 + bitWidth: 1 + INCERR2: + description: Bank 2 inconsistency error flag + bitOffset: 21 + bitWidth: 1 + STRBERR2: + description: Bank 2 strobe error flag + bitOffset: 19 + bitWidth: 1 + PGSERR2: + description: Bank 2 programming sequence error flag + bitOffset: 18 + bitWidth: 1 + WRPERR2: + description: Bank 2 write protection error flag + bitOffset: 17 + bitWidth: 1 + EOP2: + description: Bank 2 end-of-program flag + bitOffset: 16 + bitWidth: 1 + CRC_BUSY2: + description: Bank 2 CRC busy flag + bitOffset: 3 + bitWidth: 1 + QW2: + description: Bank 2 wait queue flag + bitOffset: 2 + bitWidth: 1 + WBNE2: + description: Bank 2 write buffer not empty flag + bitOffset: 1 + bitWidth: 1 + BSY2: + description: Bank 2 busy flag + bitOffset: 0 + bitWidth: 1 + CCR2: + description: FLASH clear control register for bank 2 + addressOffset: 0x114 + resetValue: 0x00000000 + fields: + CLR_CRCRDERR2: + description: Bank 2 CRCRDERR2 flag clear bit + bitOffset: 28 + bitWidth: 1 + CLR_CRCEND2: + description: Bank 2 CRCEND2 flag clear bit + bitOffset: 27 + bitWidth: 1 + CLR_DBECCERR2: + description: Bank 2 DBECCERR2 flag clear bit + bitOffset: 26 + bitWidth: 1 + CLR_SNECCERR2: + description: Bank 2 SNECCERR2 flag clear bit + bitOffset: 25 + bitWidth: 1 + CLR_RDSERR2: + description: Bank 2 RDSERR2 flag clear bit + bitOffset: 24 + bitWidth: 1 + CLR_RDPERR2: + description: Bank 2 RDPERR2 flag clear bit + bitOffset: 23 + bitWidth: 1 + CLR_OPERR2: + description: Bank 2 OPERR2 flag clear bit + bitOffset: 22 + bitWidth: 1 + CLR_INCERR2: + description: Bank 2 INCERR2 flag clear bit + bitOffset: 21 + bitWidth: 1 + CLR_STRBERR2: + description: Bank 2 STRBERR2 flag clear bit + bitOffset: 19 + bitWidth: 1 + CLR_PGSERR2: + description: Bank 2 PGSERR2 flag clear bit + bitOffset: 18 + bitWidth: 1 + CLR_WRPERR2: + description: Bank 2 WRPERR2 flag clear bit + bitOffset: 17 + bitWidth: 1 + CLR_EOP2: + description: Bank 2 EOP2 flag clear bit + bitOffset: 16 + bitWidth: 1 + OPTCR_: + description: FLASH option control register + addressOffset: 0x118 + resetValue: 0x00000001 + fields: + SWAP_BANK: + description: Bank swapping option configuration bit + bitOffset: 31 + bitWidth: 1 + OPTCHANGEERRIE: + description: Option byte change error interrupt enable bit + bitOffset: 30 + bitWidth: 1 + MER: + description: mass erase request + bitOffset: 4 + bitWidth: 1 + OPTSTART: + description: Option byte start change option configuration bit + bitOffset: 1 + bitWidth: 1 + OPTLOCK: + description: FLASH + bitOffset: 0 + bitWidth: 1 + OPTSR_CUR_: + description: FLASH option status register + addressOffset: 0x11C + resetValue: 0x00000000 + fields: + SWAP_BANK_OPT: + description: Bank swapping option status bit + bitOffset: 31 + bitWidth: 1 + OPTCHANGEERR: + description: Option byte change error flag + bitOffset: 30 + bitWidth: 1 + IO_HSLV: + description: I + bitOffset: 29 + bitWidth: 1 + NRST_STBY_D2: + description: D2 domain DStandby entry reset option status bit + bitOffset: 25 + bitWidth: 1 + NRST_STOP_D2: + description: D2 domain DStop entry reset option status bit + bitOffset: 24 + bitWidth: 1 + BOOT_CM7: + description: Arm Cortex + bitOffset: 23 + bitWidth: 1 + BOOT_CM4: + description: Arm Cortex + bitOffset: 22 + bitWidth: 1 + SECURITY: + description: Security enable option status bit + bitOffset: 21 + bitWidth: 1 + ST_RAM_SIZE: + description: ST RAM size option status + bitOffset: 19 + bitWidth: 2 + IWDG_FZ_SDBY: + description: IWDG Standby mode freeze option status bit + bitOffset: 18 + bitWidth: 1 + IWDG_FZ_STOP: + description: IWDG Stop mode freeze option status bit + bitOffset: 17 + bitWidth: 1 + RDP: + description: Readout protection level option status byte + bitOffset: 8 + bitWidth: 8 + RST_STDY_D1: + description: D1 domain DStandby entry reset option status bit + bitOffset: 7 + bitWidth: 1 + NRST_STOP_D1: + description: D1 domain DStop entry reset option status bit + bitOffset: 6 + bitWidth: 1 + IWDG2_SW: + description: IWDG2 control mode option status bit + bitOffset: 5 + bitWidth: 1 + IWDG_SW: + description: IWDG control mode option status bit + bitOffset: 4 + bitWidth: 1 + BOR_LEV: + description: Brownout level option status bit + bitOffset: 2 + bitWidth: 2 + OPT_BUSY: + description: Option byte change ongoing flag + bitOffset: 0 + bitWidth: 1 + OPTSR_PRG_: + description: FLASH option status register + addressOffset: 0x120 + resetValue: 0x00000000 + fields: + SWAP_BANK_OPT: + description: Bank swapping option configuration bit + bitOffset: 31 + bitWidth: 1 + IO_HSLV: + description: I + bitOffset: 29 + bitWidth: 1 + NRST_STBY_D2: + description: D2 domain DStandby entry reset option configuration bit + bitOffset: 25 + bitWidth: 1 + NRST_STOP_D2: + description: D2 domain DStop entry reset option configuration bit + bitOffset: 24 + bitWidth: 1 + BOOT_CM7: + description: Arm Cortex + bitOffset: 23 + bitWidth: 1 + BOOT_CM4: + description: Arm Cortex + bitOffset: 22 + bitWidth: 1 + SECURITY: + description: Security enable option configuration bit + bitOffset: 21 + bitWidth: 1 + ST_RAM_SIZE: + description: ST RAM size option configuration bits + bitOffset: 19 + bitWidth: 2 + IWDG_FZ_SDBY: + description: IWDG Standby mode freeze option configuration bit + bitOffset: 18 + bitWidth: 1 + IWDG_FZ_STOP: + description: IWDG Stop mode freeze option configuration bit + bitOffset: 17 + bitWidth: 1 + RDP: + description: Readout protection level option configuration bits + bitOffset: 8 + bitWidth: 8 + NRST_STDY_D1: + description: D1 domain DStandby entry reset option configuration bit + bitOffset: 7 + bitWidth: 1 + NRST_STOP_D1: + description: D1 domain DStop entry reset option configuration bit + bitOffset: 6 + bitWidth: 1 + IWDG2_SW: + description: IWDG2 control mode option configuration bit + bitOffset: 5 + bitWidth: 1 + IWDG_SW: + description: IWDG control mode option configuration bit + bitOffset: 4 + bitWidth: 1 + BOR_LEV: + description: Brownout level option configuration bit + bitOffset: 2 + bitWidth: 2 + OPTCCR_: + description: FLASH option clear control register + addressOffset: 0x124 + resetValue: 0x00000000 + fields: + CLR_OPTCHANGEERR: + description: OPTCHANGEERR reset bit + bitOffset: 30 + bitWidth: 1 + PRAR_CUR2: + description: FLASH protection address for bank 2 + addressOffset: 0x128 + resetValue: 0x00000000 + fields: + DMEP2: + description: Bank 2 PCROP protected erase enable option status bit + bitOffset: 31 + bitWidth: 1 + PROT_AREA_END2: + description: Bank 2 PCROP area end status bits + bitOffset: 16 + bitWidth: 12 + PROT_AREA_START2: + description: Bank 2 PCROP area start status bits + bitOffset: 0 + bitWidth: 12 + PRAR_PRG2: + description: FLASH protection address for bank 2 + addressOffset: 0x12C + resetValue: 0x00000000 + fields: + DMEP2: + description: Bank 2 PCROP protected erase enable option configuration bit + bitOffset: 31 + bitWidth: 1 + PROT_AREA_END2: + description: Bank 2 PCROP area end configuration bits + bitOffset: 16 + bitWidth: 12 + PROT_AREA_START2: + description: Bank 2 PCROP area start configuration bits + bitOffset: 0 + bitWidth: 12 + SCAR_CUR2: + description: FLASH secure address for bank 2 + addressOffset: 0x130 + resetValue: 0x00000000 + fields: + DMES2: + description: Bank 2 secure protected erase enable option status bit + bitOffset: 31 + bitWidth: 1 + SEC_AREA_END2: + description: Bank 2 secure-only area end status bits + bitOffset: 16 + bitWidth: 12 + SEC_AREA_START2: + description: Bank 2 secure-only area start status bits + bitOffset: 0 + bitWidth: 12 + SCAR_PRG2: + description: FLASH secure address for bank 2 + addressOffset: 0x134 + resetValue: 0x00000000 + fields: + DMES2: + description: Bank 2 secure access protected erase enable option configuration bit + bitOffset: 31 + bitWidth: 1 + SEC_AREA_END2: + description: Bank 2 secure-only area end configuration bits + bitOffset: 16 + bitWidth: 12 + SEC_AREA_START2: + description: Bank 2 secure-only area start configuration bits + bitOffset: 0 + bitWidth: 12 + WPSN_CUR2R: + description: FLASH write sector protection for bank 2 + addressOffset: 0x138 + resetValue: 0x00000000 + fields: + WRPSN2: + description: Bank 2 sector write protection option status byte + bitOffset: 0 + bitWidth: 8 + WPSN_PRG2R: + description: FLASH write sector protection for bank 2 + addressOffset: 0x13C + resetValue: 0x00000000 + fields: + WRPSN2: + description: Bank 2 sector write protection option status byte + bitOffset: 0 + bitWidth: 8 + BOOT7_CURR_: + description: FLASH register boot address for Arm Cortex-M7 core + addressOffset: 0x140 + resetValue: 0x00000000 + fields: + BOOT_CM7_ADD1: + description: Arm Cortex-M7 boot address 1 + bitOffset: 16 + bitWidth: 16 + BOOT_CM7_ADD0: + description: Arm Cortex-M7 boot address 0 + bitOffset: 0 + bitWidth: 16 + BOOT7_PRGR_: + description: FLASH register boot address for Arm Cortex-M7 core + addressOffset: 0x144 + resetValue: 0x00000000 + fields: + BOOT_CM7_ADD1: + description: Arm Cortex-M7 boot address 1 configuration + bitOffset: 16 + bitWidth: 16 + BOOT_CM7_ADD0: + description: Arm Cortex-M7 boot address 0 configuration + bitOffset: 0 + bitWidth: 16 + BOOT4_CURR_: + description: FLASH register boot address for Arm Cortex-M4 core + addressOffset: 0x148 + resetValue: 0x00000000 + fields: + BOOT_CM4_ADD1: + description: Arm Cortex-M4 boot address 1 + bitOffset: 16 + bitWidth: 16 + BOOT_CM4_ADD0: + description: Arm Cortex-M4 boot address 0 + bitOffset: 0 + bitWidth: 16 + BOOT4_PRGR_: + description: FLASH register boot address for Arm Cortex-M4 core + addressOffset: 0x14C + resetValue: 0x00000000 + fields: + BOOT_CM4_ADD1: + description: Arm Cortex-M4 boot address 1 configuration + bitOffset: 16 + bitWidth: 16 + BOOT_CM4_ADD0: + description: Arm Cortex-M4 boot address 0 configuration + bitOffset: 0 + bitWidth: 16 + CRCCR2: + description: FLASH CRC control register for bank 2 + addressOffset: 0x150 + resetValue: 0x001C0000 + fields: + ALL_BANK: + description: Bank 2 CRC select bit + bitOffset: 22 + bitWidth: 1 + CRC_BURST: + description: Bank 2 CRC burst size + bitOffset: 20 + bitWidth: 2 + CLEAN_CRC: + description: Bank 2 CRC clear bit + bitOffset: 17 + bitWidth: 1 + START_CRC: + description: Bank 2 CRC start bit + bitOffset: 16 + bitWidth: 1 + CLEAN_SECT: + description: Bank 2 CRC sector list clear bit + bitOffset: 10 + bitWidth: 1 + ADD_SECT: + description: Bank 2 CRC sector select bit + bitOffset: 9 + bitWidth: 1 + CRC_BY_SECT: + description: Bank 2 CRC sector mode select bit + bitOffset: 8 + bitWidth: 1 + CRC_SECT: + description: Bank 2 CRC sector number + bitOffset: 0 + bitWidth: 3 + CRCSADD2R: + description: FLASH CRC start address register for bank 2 + addressOffset: 0x154 + resetValue: 0x00000000 + fields: + CRC_START_ADDR: + description: CRC start address on bank 2 + bitOffset: 2 + bitWidth: 18 + CRCEADD2R: + description: FLASH CRC end address register for bank 2 + addressOffset: 0x158 + resetValue: 0x00000000 + fields: + CRC_END_ADDR: + description: CRC end address on bank 2 + bitOffset: 2 + bitWidth: 18 + ECC_FA2R: + description: FLASH ECC fail address for bank 2 + addressOffset: 0x160 + resetValue: 0x00000000 + fields: + FAIL_ECC_ADDR: + description: Bank 2 ECC error address + bitOffset: 0 + bitWidth: 15 diff --git a/devices/patches/flash/h7_hi_mem.yaml b/devices/patches/flash/h7_hi_mem.yaml new file mode 100644 index 000000000..cd588a3d5 --- /dev/null +++ b/devices/patches/flash/h7_hi_mem.yaml @@ -0,0 +1,4 @@ +CR[12]: + _modify: + SSN[12]: + name: SNB diff --git a/devices/patches/flash/l0.yaml b/devices/patches/flash/l0.yaml new file mode 100644 index 000000000..a840c8923 --- /dev/null +++ b/devices/patches/flash/l0.yaml @@ -0,0 +1,5 @@ +# Fix write permissions of EOP field +SR: + _modify: + EOP: + access: read-write diff --git a/devices/patches/flash/l4+.yaml b/devices/patches/flash/l4+.yaml new file mode 100644 index 000000000..f55209c0a --- /dev/null +++ b/devices/patches/flash/l4+.yaml @@ -0,0 +1,76 @@ +_include: + - flash_boot0s.yaml + +_add: + CFGR: + description: flash configuration register + addressOffset: 0x130 + resetValue: 0x0 + fields: + LVEN: + description: Low voltage enable + bitOffset: 0 + bitWidth: 1 + +_modify: + OPTR: + resetValue: 0xFFEFF8AA + WRP2AR: + addressOffset: 0x30 + WRP1BR: + addressOffset: 0x4C + +SR: + _add: + PEMPTY: + bitOffset: 17 + bitWidth: 1 + +ECCR: + _add: + ECCD2: + description: ECC2 detection + bitOffset: 29 + bitWidth: 1 + ECCC2: + description: ECC2 correction + bitOffset: 28 + bitWidth: 1 + _modify: + ADDR_ECC: + bitWidth: 21 + +OPTR: + _add: + DBANK: + bitOffset: 22 + bitWidth: 1 + DB1M: + bitOffset: 21 + bitWidth: 1 + _modify: + IDWG_SW: + name: IWDG_SW + + _delete: + - DUALBANK + +PCROP1SR: + _modify: + PCROP1_STRT: + bitWidth: 17 + +PCROP1ER: + _modify: + PCROP1_END: + bitWidth: 17 + +PCROP2SR: + _modify: + PCROP2_STRT: + bitWidth: 17 + +PCROP2ER: + _modify: + PCROP2_END: + bitWidth: 17 diff --git a/devices/patches/flash/optcr/nwrp.yaml b/devices/patches/flash/optcr/nwrp.yaml new file mode 100644 index 000000000..d8dd57548 --- /dev/null +++ b/devices/patches/flash/optcr/nwrp.yaml @@ -0,0 +1,4 @@ +OPTCR: + _split: + nWRP: + name: nWRP%s diff --git a/devices/patches/flash/optcr/sprmod.yaml b/devices/patches/flash/optcr/sprmod.yaml new file mode 100644 index 000000000..b2c65c6cf --- /dev/null +++ b/devices/patches/flash/optcr/sprmod.yaml @@ -0,0 +1,6 @@ +OPTCR: + _add: + SPRMOD: + description: Selection of Protection Mode of nWPR bits + bitOffset: 31 + bitWidth: 1 diff --git a/devices/patches/flash/optcr1/nwrp.yaml b/devices/patches/flash/optcr1/nwrp.yaml new file mode 100644 index 000000000..ef7d45019 --- /dev/null +++ b/devices/patches/flash/optcr1/nwrp.yaml @@ -0,0 +1,4 @@ +OPTCR1: + _split: + nWRP: + name: nWRP%s diff --git a/devices/patches/flash/optcr2/pcrop.yaml b/devices/patches/flash/optcr2/pcrop.yaml new file mode 100644 index 000000000..52bf994e0 --- /dev/null +++ b/devices/patches/flash/optcr2/pcrop.yaml @@ -0,0 +1,4 @@ +OPTCR2: + _split: + PCROP: + name: PCROP%s diff --git a/devices/patches/flash/optkeyr/optkeyr.yaml b/devices/patches/flash/optkeyr/optkeyr.yaml new file mode 100644 index 000000000..91ca00572 --- /dev/null +++ b/devices/patches/flash/optkeyr/optkeyr.yaml @@ -0,0 +1,4 @@ +OPTKEYR: + _modify: + OPTKEY: + name: OPTKEYR diff --git a/devices/patches/flash/sr/erserr.yaml b/devices/patches/flash/sr/erserr.yaml new file mode 100644 index 000000000..adb5d1e17 --- /dev/null +++ b/devices/patches/flash/sr/erserr.yaml @@ -0,0 +1,5 @@ +SR: + _modify: + PGSERR: + name: ERSERR + description: Erase Sequence Error diff --git a/devices/patches/flash/sr/rderr.yaml b/devices/patches/flash/sr/rderr.yaml new file mode 100644 index 000000000..7280ee296 --- /dev/null +++ b/devices/patches/flash/sr/rderr.yaml @@ -0,0 +1,6 @@ +SR: + _add: + RDERR: + description: Read Protection Error (PCROP) + bitOffset: 8 + bitWidth: 1 diff --git a/devices/patches/fsmc/bcr_clean.yaml b/devices/patches/fsmc/bcr_clean.yaml new file mode 100644 index 000000000..5d9594239 --- /dev/null +++ b/devices/patches/fsmc/bcr_clean.yaml @@ -0,0 +1,6 @@ +BCR[2-4]: + _delete: + - FMCEN + - BMAP + - WFDIS + - CCLKEN diff --git a/devices/patches/fsmc/bwtr_clean.yaml b/devices/patches/fsmc/bwtr_clean.yaml new file mode 100644 index 000000000..36413e936 --- /dev/null +++ b/devices/patches/fsmc/bwtr_clean.yaml @@ -0,0 +1,4 @@ +BWTR?: + _delete: + - CLKDIV + - DATLAT diff --git a/devices/patches/fsmc/l4+.yaml b/devices/patches/fsmc/l4+.yaml new file mode 100644 index 000000000..00980f6f1 --- /dev/null +++ b/devices/patches/fsmc/l4+.yaml @@ -0,0 +1,58 @@ +_add: + PCSCNTR: + description: PSRAM chip select counter register + addressOffset: 0x20 + resetValue: 0x0 + fields: + CSCOUNT: + description: Chip select counter + bitOffset: 0 + bitWidth: 16 + CNTB1EN: + description: Counter Bank 1 enable + bitOffset: 16 + bitWidth: 1 + CNTB2EN: + description: Counter Bank 2 enable + bitOffset: 17 + bitWidth: 1 + CNTB3EN: + description: Counter Bank 3 enable + bitOffset: 18 + bitWidth: 1 + CNTB4EN: + description: Counter Bank 4 enable + bitOffset: 19 + bitWidth: 1 + +BCR?: + _delete: + - WRAPMOD + + _add: + CPSIZE: + description: CRAM page size + bitOffset: 16 + bitWidth: 3 + NBLSET: + description: Byte lane (NBL) setup + bitOffset: 22 + bitWidth: 2 + +BTR?: + _add: + DATAHLD: + description: Data hold phase duration + bitOffset: 30 + bitWidth: 2 + +BWTR?: + _add: + BUSTURN: + description: Bus turnaround phase duration + bitOffset: 16 + bitWidth: 4 + DATAHLD: + description: Data hold phase duration + bitOffset: 30 + bitWidth: 2 diff --git a/devices/patches/fsmc/nand.yaml b/devices/patches/fsmc/nand.yaml new file mode 100644 index 000000000..039f30ed4 --- /dev/null +++ b/devices/patches/fsmc/nand.yaml @@ -0,0 +1,8 @@ +PMEM*: + _strip_end: x +PATT*: + _strip_end: x +ECCR*: + _strip_end: x +"?~PIO*": + _strip_end: x diff --git a/devices/patches/fsmc/sdfix.yaml b/devices/patches/fsmc/sdfix.yaml new file mode 100644 index 000000000..a4048be8d --- /dev/null +++ b/devices/patches/fsmc/sdfix.yaml @@ -0,0 +1,6 @@ +SDSR: + _add: + RE: + description: Refresh error flag + bitOffset: 0 + bitWidth: 1 diff --git a/devices/patches/fsmc/sramfix.yaml b/devices/patches/fsmc/sramfix.yaml new file mode 100644 index 000000000..22948bc28 --- /dev/null +++ b/devices/patches/fsmc/sramfix.yaml @@ -0,0 +1,13 @@ +_include: + - sramfix_common.yaml +BCR1: + _add: + WRAPMOD: + description: WRAPMOD + bitOffset: 10 + bitWidth: 1 + WFDIS: + description: Write FIFO disable + bitOffset: 21 + bitWidth: 1 + access: read-write diff --git a/devices/patches/fsmc/sramfix_common.yaml b/devices/patches/fsmc/sramfix_common.yaml new file mode 100644 index 000000000..f8b2b616d --- /dev/null +++ b/devices/patches/fsmc/sramfix_common.yaml @@ -0,0 +1,14 @@ +BCR?: + _add: + CPSIZE: + description: CRAM page size + bitOffset: 16 + bitWidth: 3 + access: read-write +BWTR?: + _add: + BUSTURN: + description: Bus turnaround phase duration + bitOffset: 16 + bitWidth: 4 + access: read-write diff --git a/devices/patches/fsmc/sramfix_v3.yaml b/devices/patches/fsmc/sramfix_v3.yaml new file mode 100644 index 000000000..66f8d3364 --- /dev/null +++ b/devices/patches/fsmc/sramfix_v3.yaml @@ -0,0 +1,8 @@ +_include: + - sramfix_common.yaml +BCR1: + _add: + WRAPMOD: + description: WRAPMOD + bitOffset: 10 + bitWidth: 1 diff --git a/devices/patches/fsmc/u5.yaml b/devices/patches/fsmc/u5.yaml new file mode 100644 index 000000000..7e84ed7a0 --- /dev/null +++ b/devices/patches/fsmc/u5.yaml @@ -0,0 +1,6 @@ +# PCR TAR is incorrectly defined as 3 bits wide in the SVD + +PCR: + _modify: + TAR: + bitWidth: 4 diff --git a/devices/patches/gpio/add_r_suffix.yaml b/devices/patches/gpio/add_r_suffix.yaml new file mode 100644 index 000000000..afe59ccec --- /dev/null +++ b/devices/patches/gpio/add_r_suffix.yaml @@ -0,0 +1,208 @@ +# The SVD is just quite different to the RM for all these registers. +# We'll go with the RM convention even though it is inconsistent too. +MODER: + _modify: + MODE0: + name: MODER0 + MODE1: + name: MODER1 + MODE2: + name: MODER2 + MODE3: + name: MODER3 + MODE4: + name: MODER4 + MODE5: + name: MODER5 + MODE6: + name: MODER6 + MODE7: + name: MODER7 + MODE8: + name: MODER8 + MODE9: + name: MODER9 + MODE10: + name: MODER10 + MODE11: + name: MODER11 + MODE12: + name: MODER12 + MODE13: + name: MODER13 + MODE14: + name: MODER14 + MODE15: + name: MODER15 +OSPEEDR: + _modify: + OSPEED0: + name: OSPEEDR0 + OSPEED1: + name: OSPEEDR1 + OSPEED2: + name: OSPEEDR2 + OSPEED3: + name: OSPEEDR3 + OSPEED4: + name: OSPEEDR4 + OSPEED5: + name: OSPEEDR5 + OSPEED6: + name: OSPEEDR6 + OSPEED7: + name: OSPEEDR7 + OSPEED8: + name: OSPEEDR8 + OSPEED9: + name: OSPEEDR9 + OSPEED10: + name: OSPEEDR10 + OSPEED11: + name: OSPEEDR11 + OSPEED12: + name: OSPEEDR12 + OSPEED13: + name: OSPEEDR13 + OSPEED14: + name: OSPEEDR14 + OSPEED15: + name: OSPEEDR15 +PUPDR: + _modify: + PUPD0: + name: PUPDR0 + PUPD1: + name: PUPDR1 + PUPD2: + name: PUPDR2 + PUPD3: + name: PUPDR3 + PUPD4: + name: PUPDR4 + PUPD5: + name: PUPDR5 + PUPD6: + name: PUPDR6 + PUPD7: + name: PUPDR7 + PUPD8: + name: PUPDR8 + PUPD9: + name: PUPDR9 + PUPD10: + name: PUPDR10 + PUPD11: + name: PUPDR11 + PUPD12: + name: PUPDR12 + PUPD13: + name: PUPDR13 + PUPD14: + name: PUPDR14 + PUPD15: + name: PUPDR15 +IDR: + _modify: + ID0: + name: IDR0 + ID1: + name: IDR1 + ID2: + name: IDR2 + ID3: + name: IDR3 + ID4: + name: IDR4 + ID5: + name: IDR5 + ID6: + name: IDR6 + ID7: + name: IDR7 + ID8: + name: IDR8 + ID9: + name: IDR9 + ID10: + name: IDR10 + ID11: + name: IDR11 + ID12: + name: IDR12 + ID13: + name: IDR13 + ID14: + name: IDR14 + ID15: + name: IDR15 +ODR: + _modify: + OD0: + name: ODR0 + OD1: + name: ODR1 + OD2: + name: ODR2 + OD3: + name: ODR3 + OD4: + name: ODR4 + OD5: + name: ODR5 + OD6: + name: ODR6 + OD7: + name: ODR7 + OD8: + name: ODR8 + OD9: + name: ODR9 + OD10: + name: ODR10 + OD11: + name: ODR11 + OD12: + name: ODR12 + OD13: + name: ODR13 + OD14: + name: ODR14 + OD15: + name: ODR15 +AFRL: + _modify: + AFSEL0: + name: AFR0 + AFSEL1: + name: AFR1 + AFSEL2: + name: AFR2 + AFSEL3: + name: AFR3 + AFSEL4: + name: AFR4 + AFSEL5: + name: AFR5 + AFSEL6: + name: AFR6 + AFSEL7: + name: AFR7 +AFRH: + _modify: + AFSEL8: + name: AFR8 + AFSEL9: + name: AFR9 + AFSEL10: + name: AFR10 + AFSEL11: + name: AFR11 + AFSEL12: + name: AFR12 + AFSEL13: + name: AFR13 + AFSEL14: + name: AFR14 + AFSEL15: + name: AFR15 diff --git a/devices/patches/gpio/f3_reset_values.yaml b/devices/patches/gpio/f3_reset_values.yaml new file mode 100644 index 000000000..409404e9f --- /dev/null +++ b/devices/patches/gpio/f3_reset_values.yaml @@ -0,0 +1,63 @@ +# Some F3 SVDs (stm32f302, stm32f303, stm32f373, stm32f3x8) have wrong reset +# values for some of the GPIO registers. +# +# We want the following reset values (omitted values are 0x0000_0000): +# +# GPIOA: +# MODER: 0xA800_0000 +# OSPEEDR: 0x0C00_0000 +# PUPDR: 0x6400_0000 +# +# GPIOB: +# MODER: 0x0000_0280 +# OSPEEDR: 0x0000_00C0 +# PUPDR: 0x0000_0100 +# +# To this end, this patch ensures there are three different GPIO peripherals, +# GPIOA, GPIOB, and GPIOC. GPIOC has all-zero reset values and all other GPIO +# peripherals derive from that. + +# In some SVDs GPIOC is derived from GPIOB, so we need to delete and re-add +# to be able to modify its reset values. +_delete: + - GPIOC +_copy: + GPIOC: + from: GPIOA +_modify: + GPIOC: + baseAddress: "0x48000800" + +_derive: + GPIOD: GPIOC + GPIOE: GPIOC + GPIOF: GPIOC + GPIOG: GPIOC + GPIOH: GPIOC + +GPIOA: + _modify: + MODER: + resetValue: "0xa8000000" + OSPEEDR: + resetValue: "0x0C000000" + PUPDR: + resetValue: "0x64000000" + +GPIOB: + _modify: + MODER: + resetValue: "0x00000280" + OSPEEDR: + resetValue: "0x000000C0" + PUPDR: + resetValue: "0x00000100" + +GPIOC: + _modify: + MODER: + resetValue: "0x00000000" + OSPEEDR: + resetValue: "0x00000000" + PUPDR: + resetValue: "0x00000000" diff --git a/devices/patches/gpio/h7_ijk.yaml b/devices/patches/gpio/h7_ijk.yaml new file mode 100644 index 000000000..33532615d --- /dev/null +++ b/devices/patches/gpio/h7_ijk.yaml @@ -0,0 +1,8 @@ +# Fix the reset values for H7 devices with GPIOI, GPIOJ and GPIOK peripherals +_include: + - h7_reset_values_common.yaml + +_derive: + GPIOI: GPIOC + GPIOJ: GPIOC + GPIOK: GPIOC diff --git a/devices/patches/gpio/h7_jk.yaml b/devices/patches/gpio/h7_jk.yaml new file mode 100644 index 000000000..6183867cc --- /dev/null +++ b/devices/patches/gpio/h7_jk.yaml @@ -0,0 +1,37 @@ +# Fix the reset values for H7 devices with GPIOJ and GPIOK peripherals (RM0468) +_include: + - h7_reset_values_common.yaml + +# We cannot derive GPIOJ and GPIOK from GPIOC, since their MODER register +# has a different reset value +_delete: + - GPIOJ + - GPIOK +_copy: + GPIOJ: + from: GPIOA + GPIOK: + from: GPIOA +_modify: + GPIOJ: + baseAddress: "0x58022400" + GPIOK: + baseAddress: "0x58022800" + +GPIOJ: + _modify: + MODER: + resetValue: "0x00ff0000" + OSPEEDR: + resetValue: "0x00000000" + PUPDR: + resetValue: "0x00000000" + +GPIOK: + _modify: + MODER: + resetValue: "0x0000003f" + OSPEEDR: + resetValue: "0x00000000" + PUPDR: + resetValue: "0x00000000" diff --git a/devices/patches/gpio/h7_mnop.yaml b/devices/patches/gpio/h7_mnop.yaml new file mode 100644 index 000000000..1262551ee --- /dev/null +++ b/devices/patches/gpio/h7_mnop.yaml @@ -0,0 +1,10 @@ +# Fix the reset values for H7 devices with GPIOI, GPIOJ and GPIOK peripherals +_include: + - h7_reset_values_common.yaml + +_derive: + GPIOM: GPIOC + GPION: GPIOC + GPIOO: GPIOC + GPIOP: GPIOC + diff --git a/devices/patches/gpio/h7_reset_values_common.yaml b/devices/patches/gpio/h7_reset_values_common.yaml new file mode 100644 index 000000000..06db59c1f --- /dev/null +++ b/devices/patches/gpio/h7_reset_values_common.yaml @@ -0,0 +1,71 @@ +# In the H7 SVDs all GPIOs are derived from GPIOA, +# but this leads to wrong reset values for some of the GPIO registers. +# +# We want the following reset values (omitted values are 0x0000_0000): +# +# GPIOA: +# MODER: 0xABFF_FFFF +# OSPEEDR: 0x0C00_0000 +# PUPDR: 0x6400_0000 +# +# GPIOB: +# MODER: 0xFFFF_FEBF +# OSPEEDR: 0x0000_00C0 +# PUPDR: 0x0000_0100 +# +# To this end, this patch ensures there are three different GPIO peripherals, +# GPIOA, GPIOB, and GPIOC. GPIOC has all-zero reset values and all other GPIO +# peripherals derive from that. +# This file only derives the common GPIO peripherals, so don't include +# this directly but through one of the other h7_xxx.yaml files. + +# Since GPIOC and GPIOC are derived from GPIOA, we need to delete and re-add +# to be able to modify their reset values. +_delete: + - GPIOB + - GPIOC +_copy: + GPIOB: + from: GPIOA + GPIOC: + from: GPIOA +_modify: + GPIOB: + baseAddress: "0x58020400" + GPIOC: + baseAddress: "0x58020800" + +# These GPIO's are common to all H7 devices +_derive: + GPIOD: GPIOC + GPIOE: GPIOC + GPIOF: GPIOC + GPIOG: GPIOC + GPIOH: GPIOC + +GPIOA: + _modify: + MODER: + resetValue: "0xabffffff" + OSPEEDR: + resetValue: "0x0c000000" + PUPDR: + resetValue: "0x64000000" + +GPIOB: + _modify: + MODER: + resetValue: "0xfffffebf" + OSPEEDR: + resetValue: "0x000000c0" + PUPDR: + resetValue: "0x00000100" + +GPIOC: + _modify: + MODER: + resetValue: "0xffffffff" + OSPEEDR: + resetValue: "0x00000000" + PUPDR: + resetValue: "0x00000000" diff --git a/devices/patches/gpio/l4_ascr.yaml b/devices/patches/gpio/l4_ascr.yaml new file mode 100644 index 000000000..cd950ab7c --- /dev/null +++ b/devices/patches/gpio/l4_ascr.yaml @@ -0,0 +1,16 @@ +_add: + ASCR: + description: GPIO port analog switch control register + addressOffset: 0x2C + fields: + ASC: + description: These bits are written by software to configure the analog connection of the IOs. + access: read-write + bitOffset: 0 + bitWidth: 16 +ASCR: + _split: [ASC] + ASC*: + _write: + NoAction: [0, Disconnect analog switch to the ADC input] + Reset: [1, " Connect analog switch to the ADC input"] diff --git a/devices/patches/gpio/l4_brr.yaml b/devices/patches/gpio/l4_brr.yaml new file mode 100644 index 000000000..e2f00b88d --- /dev/null +++ b/devices/patches/gpio/l4_brr.yaml @@ -0,0 +1,12 @@ +_add: + BRR: + description: GPIO port bit reset register + addressOffset: 0x28 + fields: + BR: + description: These bits are write-only. A read to these bits returns the value 0x0000 + access: write-only + bitOffset: 0 + bitWidth: 16 +BRR: + _split: [BR] diff --git a/devices/patches/gpio/with_OSPEEDER.yaml b/devices/patches/gpio/with_OSPEEDER.yaml new file mode 100644 index 000000000..0fa45c0ed --- /dev/null +++ b/devices/patches/gpio/with_OSPEEDER.yaml @@ -0,0 +1,6 @@ +# This is a GPIO patch for the OSPEEDER typo + +_modify: + OSPEEDER: + name: OSPEEDR + displayName: OSPEEDR diff --git a/devices/patches/h743_hrtim_common.yaml b/devices/patches/h743_hrtim_common.yaml new file mode 100644 index 000000000..527a014df --- /dev/null +++ b/devices/patches/h743_hrtim_common.yaml @@ -0,0 +1,4 @@ +HRTIM_Common: + _modify: + BDMADR: + addressOffset: 0x70 diff --git a/devices/patches/h7_common_highmemory.yaml b/devices/patches/h7_common_highmemory.yaml new file mode 100644 index 000000000..74df12c89 --- /dev/null +++ b/devices/patches/h7_common_highmemory.yaml @@ -0,0 +1,146 @@ +# Common SVD errors for high memory density parts h7a3/h7b3/h7b0 +# +# See RM0455 + +# Rename in accordance with other devices and reference manual. +_modify: + Flash: + name: FLASH + TT_FDCAN: + name: FDCAN1 + FDCAN: + name: FDCAN2 + DAC: + name: DAC1 + +# The ADC3 interrupt doesn't exist (no ADC3 peripheral), but the slot was +# re-used for DAC2 +ADC1: + _delete: + _interrupts: + - ADC3 + +# Work around the DMA_STR? interrupt mess in the SVD. +# Some interrupts are on DMA2 instead on DMA1 and/or called DMA_STR? without +# the numeral. +# +# Since it is not possible to modify a derivedFrom peripheral, we delete it first + +_delete: + - UART4 + - UART5 + - UART7 + - UART8 + - USART9 + - USART10 + +_add: + UART4: + derivedFrom: USART1 + baseAddress: 0x40004C00 + interrupts: + UART4: + description: UART4 global interrupt + value: 52 + UART5: + derivedFrom: USART1 + baseAddress: 0x40005000 + interrupts: + UART5: + description: UART5 global interrupt + value: 53 + UART7: + derivedFrom: USART1 + baseAddress: 0x40007800 + interrupts: + UART7: + description: UART7 global interrupt + value: 82 + UART8: + derivedFrom: USART1 + baseAddress: 0x40007C00 + interrupts: + UART8: + description: UART8 global interrupt + value: 83 + UART9: + derivedFrom: USART1 + baseAddress: 0x40011800 + interrupts: + UART9: + description: UART9 global interrupt + value: 140 + USART10: + derivedFrom: USART1 + baseAddress: 0x40011C00 + interrupts: + USART10: + description: USART10 global interrupt + value: 141 + +DMA1: + _interrupts: + _modify: + DMA_STR0: + name: DMA1_STR0 + DMA_STR1: + name: DMA1_STR1 + DMA_STR2: + name: DMA1_STR2 + DMA_STR3: + name: DMA1_STR3 + DMA_STR4: + name: DMA1_STR4 + DMA_STR5: + name: DMA1_STR5 + DMA_STR6: + name: DMA1_STR6 + DMA_STR7: + name: DMA1_STR7 + +DMA2: + _add: + _interrupts: + DMA2_STR0: + value: 56 + description: DMA2 Stream0 + DMA2_STR1: + value: 57 + description: DMA2 Stream1 + DMA2_STR2: + value: 58 + description: DMA2 Stream2 + DMA2_STR3: + value: 59 + description: DMA2 Stream3 + DMA2_STR4: + value: 60 + description: DMA2 Stream4 + DMA2_STR5: + value: 68 + description: DMA2 Stream5 + DMA2_STR6: + value: 69 + description: DMA2 Stream6 + DMA2_STR7: + value: 70 + description: DMA2 Stream7 + +SYSCFG: + _modify: + SYSCFG_BRK_LOCKUPR: + name: CFGR + addressOffset: 0x18 + PMCR: + _delete: # Functionality not available on these parts + - BOOSTE + - EPIS + +HRTIM_Common: + _modify: + BDMADR: + addressOffset: 0x70 + +HRTIM_TIMA: + _delete: + _interrupts: DMA2_* diff --git a/devices/common_patches/h7_spdifrx.yaml b/devices/patches/h7_spdifrx.yaml similarity index 100% rename from devices/common_patches/h7_spdifrx.yaml rename to devices/patches/h7_spdifrx.yaml diff --git a/devices/patches/hash/hash_l4+.yaml b/devices/patches/hash/hash_l4+.yaml new file mode 100644 index 000000000..aa4c29655 --- /dev/null +++ b/devices/patches/hash/hash_l4+.yaml @@ -0,0 +1,63 @@ +_modify: + HR0: + name: HRA0 + displayName: HRA0 + # strip doesn't work because otherwise we end up with two HRA0 registers... + HASH_HR0: + name: HR0 + HASH_HR1: + name: HR1 + HASH_HR2: + name: HR2 + HASH_HR3: + name: HR3 + HASH_HR4: + name: HR4 + HASH_HR5: + name: HR5 + HASH_HR6: + name: HR6 + HASH_HR7: + name: HR7 + +_add: + HRA1: + displayName: HRA1 + description: digest registers + addressOffset: 0x10 + resetValue: 0x0 + fields: + H1: + description: H1 + bitOffset: 0 + bitWidth: 32 + HRA2: + displayName: HRA2 + description: digest registers + addressOffset: 0x14 + resetValue: 0x0 + fields: + H1: + description: H2 + bitOffset: 0 + bitWidth: 32 + HRA3: + displayName: HRA3 + description: digest registers + addressOffset: 0x18 + resetValue: 0x0 + fields: + H1: + description: H3 + bitOffset: 0 + bitWidth: 32 + HRA4: + displayName: HRA4 + description: digest registers + addressOffset: 0x1C + resetValue: 0x0 + fields: + H1: + description: H4 + bitOffset: 0 + bitWidth: 32 diff --git a/devices/patches/hrtim/f3_interrupts.yaml b/devices/patches/hrtim/f3_interrupts.yaml new file mode 100644 index 000000000..c4fd4f0a7 --- /dev/null +++ b/devices/patches/hrtim/f3_interrupts.yaml @@ -0,0 +1,46 @@ +HRTIM_Common: + _modify: + _interrupts: + HRTIM1_FLT: + name: HRTIM_FLT + value: 73 + +HRTIM_Master: + _modify: + _interrupts: + HRTIM1_MST: + name: HRTIM_MST + value: 67 + +HRTIM_TIMA: + _modify: + _interrupts: + HRTIM1_TIMA: + value: 68 + name: HRTIM_TIMA + +HRTIM_TIMB: + _modify: + _interrupts: + HRTIM_TIMB: + value: 69 + +HRTIM_TIMC: + _modify: + _interrupts: + HRTIM1_TIMC: + name: HRTIM_TIMC + value: 70 + +HRTIM_TIMD: + _modify: + _interrupts: + HRTIM1_TIMD: + name: HRTIM_TIMD + value: 71 + +HRTIM_TIME: + _modify: + _interrupts: + HRTIM_TIME: + value: 72 diff --git a/devices/patches/hrtim/h7.yaml b/devices/patches/hrtim/h7.yaml new file mode 100644 index 000000000..eb22b477e --- /dev/null +++ b/devices/patches/hrtim/h7.yaml @@ -0,0 +1,68 @@ +_include: v1.yaml + +HRTIM_Common: + _delete: + - DLLCR + _modify: + BDTxUPR: + name: BDTAUPR + + "BMTRG,BMTRGR": + _add: + TAEEV7: + description: Timer A period following External Event 7 + bitOffset: 27 + bitWidth: 1 + TDEEV8: + description: Timer D period following External Event 8 + bitOffset: 28 + bitWidth: 1 + EEV7: + description: External Event 7 (TIMA filters applied) + bitOffset: 29 + bitWidth: 1 + EEV8: + description: External Event 8 (TIMD filters applied) + bitOffset: 30 + bitWidth: 1 + + EECR3: + _delete: + - EE*SNS + - EE*POL + - EE*SRC + _add: + EE6F: + description: External event 6 filter + bitOffset: 0 + bitWidth: 4 + EE7F: + description: External event 7 filter + bitOffset: 6 + bitWidth: 4 + EE8F: + description: External event 8 filter + bitOffset: 12 + bitWidth: 4 + EE9F: + description: External event 9 filter + bitOffset: 18 + bitWidth: 4 + EE10F: + description: External event 10 filter + bitOffset: 24 + bitWidth: 4 + EEVSD: + description: External event sampling clock division + bitOffset: 30 + bitWidth: 2 + + ISR: + _delete: + - DLLRDY + IER: + _delete: + - DLLRDYIE + ICR: + _delete: + - DLLRDYC diff --git a/devices/patches/hrtim/master.yaml b/devices/patches/hrtim/master.yaml new file mode 100644 index 000000000..3487cd736 --- /dev/null +++ b/devices/patches/hrtim/master.yaml @@ -0,0 +1,27 @@ +_strip: M +_modify: + PER: + name: PERR + REP: + name: REPR +CR: + _modify: + SYNC_SRC: + name: SYNCSRC + SYNC_OUT: + name: SYNCOUT + SYNC_IN: + name: SYNCIN + CK_PSC: + name: CKPSC + SYNCRSTM: + name: SYNCRST + SYNCSTRTM: + name: SYNCSTRT +"ISR,ICR,DIER,CNTR,PERR,REPR,CMP[1-4]R": + _strip: M + +CMP[1-4]R: + _modify: + CMP[1-4]: + name: CMP diff --git a/devices/patches/hrtim/strip.yaml b/devices/patches/hrtim/strip.yaml new file mode 100644 index 000000000..40549302f --- /dev/null +++ b/devices/patches/hrtim/strip.yaml @@ -0,0 +1,134 @@ +_strip: TIM + +_modify: + "[A-F]CR": + name: CR + "[A-F]ISR": + name: ISR + "[A-F]ICR": + name: ICR + "CNTR,CNT[ACDEF]R": + name: CNTR + "PER[A-F]R": + name: PERR + "REP[A-F]R": + name: REPR + "CMP1[A-F]R": + name: CMP1R + "CMP2[A-F]R": + name: CMP2R + "CMP3[A-F]R": + name: CMP3R + "CMP4[A-F]R": + name: CMP4R + "CMP1C[A-F]R": + name: CMP1CR + "CPT1[A-F]R": + name: CPT1R + "CPT2[A-F]R": + name: CPT2R + "DT[A-F]R": + name: DTR + "SET[A-F]1R": + name: SET1R + "SET[A-F]2R": + name: SET2R + "RST[A-F]1R": + name: RST1R + "RST[A-F]2R": + name: RST2R + "EEF[A-F]R1": + name: EEFR1 + "EEF[A-F]R2": + name: EEFR2 + "RST[A-F]R": + name: RSTR + "CHP[A-F]R": + name: CHPR + "CPT1[A-F]CR": + name: CPT1CR + "CPT2[A-F]CR": + name: CPT2CR + "OUT[A-F]R": + name: OUTR + "FLT[A-F]R": + name: FLTR + +"CNTR,PERR,REPR,CMP[1-4]R,CMP1CR,CPT[12]R,DTR": + _strip_end: x + +CR: + _modify: + CK_PSCx: + name: CKPSC + SYNCSTRTx: + name: SYNCSTRT + SYNCRSTx: + name: SYNCRST + TxREPU: + name: TREPU + TxRSTU: + name: TRSTU + +ISR: + _modify: + "RSTx1,RST1x": + name: RST1 + "RSTx2,RST2x": + name: RST2 + "SETx1,SET1x": + name: SET1 + "SETx2,SET2x": + name: SET2 + +ICR: + _modify: + "RSTx1C,RST1xC": + name: RST1C + "RSTx2C,RST2xC": + name: RST2C + "SETx1C,SET1xC": + name: SET1C + "SETx2C,SET2xC": + name: SET2C + +DIER: + _modify: + "RSTx1DE,RST1xDE": + name: RST1DE + "RSTx2DE,RST2xDE": + name: RST2DE + "SETx1DE,SET1xDE": + name: SET1DE + "SETx2DE,SET2xDE": + name: SET2DE + "RSTx1IE,RST1xIE": + name: RST1IE + "RSTx2IE,RST2xIE": + name: RST2IE + "SET1xIE,SETx1IE": + name: SET1IE + "SETx2IE,SET2xIE": + name: SET2IE + +CHPR: + _modify: + CHPDTY: + name: CARDTY + CHPFRQ: + name: CARFRQ + +CPT[12]R: + _modify: + CPT[12]: + name: CPT + +CMP[1-4]R: + _modify: + CMP[1-4]: + name: CMP + +"CPT[12]CR": + _modify: + UDPCPT: + name: UPDCPT diff --git a/devices/patches/hrtim/v1.yaml b/devices/patches/hrtim/v1.yaml new file mode 100644 index 000000000..767a488f6 --- /dev/null +++ b/devices/patches/hrtim/v1.yaml @@ -0,0 +1,198 @@ +HRTIM_Common: + _modify: + BDMUPDR: + name: BDMUPR + "BMTRG,BMTRGR": + name: BMTRGR + "BMCMPR6,BMCMPR": + name: BMCMPR + OENR: + access: read-write + "DISR,ODISR": + name: ODISR + access: write-only + IER: + _modify: + SYSFLTE: + name: SYSFLTIE + ICR: + _modify: + SYSFLTC: + access: write-only + ADC[1234]R: + _strip: + - AD?T + - AD? + + BDT[A-F]UPR: + _strip: TIMx + _modify: + "DTxR,_DTxR": + name: DTR + +HRTIM_Master: + _include: master.yaml + _modify: + DIER4: + name: DIER + +HRTIM_TIMA: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMBCMP1 + description: Timer B Compare 1 + TIMEVNT2: + name: TIMBCMP2 + description: Timer B Compare 2 + TIMEVNT3: + name: TIMBCMP4 + description: Timer B Compare 4 + TIMEVNT4: + name: TIMCCMP2 + description: Timer C Compare 2 + TIMEVNT5: + name: TIMCCMP3 + description: Timer C Compare 3 + TIMEVNT6: + name: TIMDCMP1 + description: Timer D Compare 1 + TIMEVNT7: + name: TIMDCMP2 + description: Timer D Compare 2 + TIMEVNT8: + name: TIMECMP3 + description: Timer E Compare 3 + TIMEVNT9: + name: TIMECMP4 + description: Timer E Compare 4 + +HRTIM_TIMB: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP1 + description: Timer A Compare 1 + TIMEVNT2: + name: TIMACMP2 + description: Timer A Compare 2 + TIMEVNT3: + name: TIMACMP4 + description: Timer A Compare 4 + TIMEVNT4: + name: TIMCCMP3 + description: Timer C Compare 3 + TIMEVNT5: + name: TIMCCMP4 + description: Timer C Compare 4 + TIMEVNT6: + name: TIMDCMP3 + description: Timer D Compare 3 + TIMEVNT7: + name: TIMDCMP4 + description: Timer D Compare 4 + TIMEVNT8: + name: TIMECMP1 + description: Timer E Compare 1 + TIMEVNT9: + name: TIMECMP2 + description: Timer E Compare 2 + +HRTIM_TIMC: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP2 + description: Timer A Compare 2 + TIMEVNT2: + name: TIMACMP3 + description: Timer A Compare 3 + TIMEVNT3: + name: TIMBCMP2 + description: Timer B Compare 2 + TIMEVNT4: + name: TIMBCMP3 + description: Timer B Compare 3 + TIMEVNT5: + name: TIMDCMP2 + description: Timer D Compare 2 + TIMEVNT6: + name: TIMDCMP4 + description: Timer D Compare 4 + TIMEVNT7: + name: TIMECMP2 + description: Timer E Compare 2 + TIMEVNT8: + name: TIMECMP3 + description: Timer E Compare 3 + TIMEVNT9: + name: TIMECMP4 + description: Timer E Compare 4 + +HRTIM_TIMD: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP1 + description: Timer A Compare 1 + TIMEVNT2: + name: TIMACMP4 + description: Timer A Compare 4 + TIMEVNT3: + name: TIMBCMP2 + description: Timer B Compare 2 + TIMEVNT4: + name: TIMBCMP4 + description: Timer B Compare 4 + TIMEVNT5: + name: TIMCCMP1 + description: Timer C Compare 1 + TIMEVNT6: + name: TIMCCMP3 + description: Timer C Compare 3 + TIMEVNT7: + name: TIMCCMP4 + description: Timer C Compare 4 + TIMEVNT8: + name: TIMECMP1 + description: Timer E Compare 1 + TIMEVNT9: + name: TIMECMP2 + description: Timer E Compare 2 + +HRTIM_TIME: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP3 + description: Timer A Compare 3 + TIMEVNT2: + name: TIMACMP4 + description: Timer A Compare 4 + TIMEVNT3: + name: TIMBCMP3 + description: Timer B Compare 3 + TIMEVNT4: + name: TIMBCMP4 + description: Timer B Compare 4 + TIMEVNT5: + name: TIMCCMP1 + description: Timer C Compare 1 + TIMEVNT6: + name: TIMCCMP2 + description: Timer C Compare 2 + TIMEVNT7: + name: TIMDCMP1 + description: Timer D Compare 1 + TIMEVNT8: + name: TIMDCMP2 + description: Timer D Compare 2 + TIMEVNT9: + name: TIMDCMP4 + description: Timer D Compare 4 + +"HRTIM_TIM[A-F]": + _include: strip.yaml + _modify: + "[A-F]DIER5": + name: DIER diff --git a/devices/patches/hrtim/v2.yaml b/devices/patches/hrtim/v2.yaml new file mode 100644 index 000000000..230c93256 --- /dev/null +++ b/devices/patches/hrtim/v2.yaml @@ -0,0 +1,364 @@ +HRTIM_Common: + _modify: + BDMUPDR: + name: BDMUPR + BMTRG: + name: BMTRGR + IER: + _modify: + SYSFLTE: + name: SYSFLTIE + OENR: + _modify: + TF1ODS: + name: TF1OEN + description: Bit 10 - Timer F Output 1 Enable + TF2ODS: + name: TF2OEN + description: Bit 11 - Timer F Output 2 Enable + ADC1R: + _strip: + - AD1T + - AD1 + + _modify: + EC2: + name: FRST + description: Bit 28 - ADC trigger 1 on timer F reset and counter roll-over + + DC2: + name: FPER + description: Bit 24 - ADC trigger 1 on timer F period + + CC2: + name: FC4 + description: Bit 20 - ADC trigger 1 on timer F compare 4 + + BC2: + name: FC3 + description: Bit 15 - ADC trigger 1 on timer F compare 3 + + AC2: + name: FC2 + description: Bit 10 - ADC trigger 1 on timer F compare 2 + + ADC3R: + _strip: + - AD1T + - AD1 + + _modify: + EC2: + name: FRST + description: Bit 28 - ADC trigger 3 on timer F reset and counter roll-over + + DC2: + name: FPER + description: Bit 24 - ADC trigger 3 on timer F period + + CC2: + name: FC4 + description: Bit 20 - ADC trigger 3 on timer F compare 4 + + BC2: + name: FC3 + description: Bit 15 - ADC trigger 3 on timer F compare 3 + + AC2: + name: FC2 + description: Bit 10 - ADC trigger 3 on timer F compare 2 + + ADC2R: + _strip: + - AD2T + - AD2 + + _modify: + DC3: + name: FPER + description: Bit 24 - ADC trigger 2 on timer F period + + CC3: + name: FC4 + description: Bit 19 - ADC trigger 2 on timer F compare 4 + + BC3: + name: FC3 + description: Bit 15 - ADC trigger 2 on timer F compare 3 + + AC3: + name: FC2 + description: Bit 11 - ADC trigger 3 on timer F compare 2 + + ADC4R: + _strip: + - AD2T + - AD2 + + _modify: + DC3: + name: FPER + description: Bit 24 - ADC trigger 2 on timer F period + + CC3: + name: FC4 + description: Bit 19 - ADC trigger 2 on timer F compare 4 + + BC3: + name: FC3 + description: Bit 15 - ADC trigger 2 on timer F compare 3 + + AC3: + name: FC2 + description: Bit 11 - ADC trigger 3 on timer F compare 2 + + BMTRGR: + _modify: + TDEEV7: + name: TAEEV7 + description: Timer A period following external event 7 + TERST: + name: TFCMP1 + description: Timer F compare 1 event + TDCMP1: + name: TFREP + description: Timer F repetition + TCCMP2: + name: TFRST + description: Timer F reset + + BDT[A-F]UPR: + _strip: TIMx + + FLTINR2: + _modify: + FLT6SRC_0: + name: FLT6SRC + +HRTIM_Master: + _include: master.yaml + +HRTIM_TIMA: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMBCMP1 + description: Timer B Compare 1 + TIMEVNT2: + name: TIMBCMP2 + description: Timer B Compare 2 + TIMEVNT3: + name: TIMCCMP2 + description: Timer C Compare 2 + TIMEVNT4: + name: TIMCCMP3 + description: Timer C Compare 3 + TIMEVNT5: + name: TIMDCMP1 + description: Timer D Compare 1 + TIMEVNT6: + name: TIMDCMP2 + description: Timer D Compare 2 + TIMEVNT7: + name: TIMECMP3 + description: Timer E Compare 3 + TIMEVNT8: + name: TIMECMP4 + description: Timer E Compare 4 + TIMEVNT9: + name: TIMFCMP4 + description: Timer F Compare 4 + RST[A-F]R,RSTR: + _modify: + TIMFCPM2: + name: TIMFCMP2 + +HRTIM_TIMB: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP1 + description: Timer A Compare 1 + TIMEVNT2: + name: TIMACMP2 + description: Timer A Compare 2 + TIMEVNT3: + name: TIMCCMP3 + description: Timer C Compare 3 + TIMEVNT4: + name: TIMCCMP4 + description: Timer C Compare 4 + TIMEVNT5: + name: TIMDCMP3 + description: Timer D Compare 3 + TIMEVNT6: + name: TIMDCMP4 + description: Timer D Compare 4 + TIMEVNT7: + name: TIMECMP1 + description: Timer E Compare 1 + TIMEVNT8: + name: TIMECMP2 + description: Timer E Compare 2 + TIMEVNT9: + name: TIMFCMP3 + description: Timer F Compare 3 + RST[A-F]R,RSTR: + _modify: + TIMFCPM2: + name: TIMFCMP2 + +HRTIM_TIMC: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP2 + description: Timer A Compare 2 + TIMEVNT2: + name: TIMACMP3 + description: Timer A Compare 3 + TIMEVNT3: + name: TIMBCMP2 + description: Timer B Compare 2 + TIMEVNT4: + name: TIMBCMP3 + description: Timer B Compare 3 + TIMEVNT5: + name: TIMDCMP2 + description: Timer D Compare 2 + TIMEVNT6: + name: TIMDCMP4 + description: Timer D Compare 4 + TIMEVNT7: + name: TIMECMP3 + description: Timer E Compare 3 + TIMEVNT8: + name: TIMECMP4 + description: Timer E Compare 4 + TIMEVNT9: + name: TIMFCMP2 + description: Timer F Compare 2 + RST[A-F]R,RSTR: + _modify: + TIMFCPM2: + name: TIMFCMP2 + +HRTIM_TIMD: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP1 + description: Timer A Compare 1 + TIMEVNT2: + name: TIMACMP4 + description: Timer A Compare 4 + TIMEVNT3: + name: TIMBCMP2 + description: Timer B Compare 2 + TIMEVNT4: + name: TIMBCMP4 + description: Timer B Compare 4 + TIMEVNT5: + name: TIMCCMP4 + description: Timer C Compare 4 + TIMEVNT6: + name: TIMECMP1 + description: Timer E Compare 1 + TIMEVNT7: + name: TIMECMP4 + description: Timer E Compare 4 + TIMEVNT8: + name: TIMFCMP1 + description: Timer F Compare 1 + TIMEVNT9: + name: TIMFCMP3 + description: Timer F Compare 3 + RST[A-F]R,RSTR: + _modify: + TIMFCPM2: + name: TIMFCMP2 + +HRTIM_TIME: + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP4 + description: Timer A Compare 4 + TIMEVNT2: + name: TIMBCMP3 + description: Timer B Compare 3 + TIMEVNT3: + name: TIMBCMP4 + description: Timer B Compare 4 + TIMEVNT4: + name: TIMCCMP1 + description: Timer C Compare 1 + TIMEVNT5: + name: TIMCCMP2 + description: Timer C Compare 2 + TIMEVNT6: + name: TIMDCMP1 + description: Timer D Compare 1 + TIMEVNT7: + name: TIMDCMP2 + description: Timer D Compare 2 + TIMEVNT8: + name: TIMFCMP3 + description: Timer F Compare 3 + TIMEVNT9: + name: TIMFCMP4 + description: Timer F Compare 4 + RST[A-F]R,RSTR: + _modify: + TIMFCPM2: + name: TIMFCMP2 + +HRTIM_TIMF: + _modify: + RSTE1R: + name: RSTF1R + "RST[A-F][12]R,SET[A-F][12]R": + _modify: + TIMEVNT1: + name: TIMACMP3 + description: Timer A Compare 3 + TIMEVNT2: + name: TIMBCMP1 + description: Timer B Compare 1 + TIMEVNT3: + name: TIMBCMP4 + description: Timer B Compare 4 + TIMEVNT4: + name: TIMCCMP1 + description: Timer C Compare 1 + TIMEVNT5: + name: TIMCCMP4 + description: Timer C Compare 4 + TIMEVNT6: + name: TIMDCMP3 + description: Timer D Compare 3 + TIMEVNT7: + name: TIMDCMP4 + description: Timer D Compare 4 + TIMEVNT8: + name: TIMECMP2 + description: Timer E Compare 2 + TIMEVNT9: + name: TIMECMP3 + description: Timer E Compare 3 + RST[A-F]R,RSTR: + _modify: + TIMFCMP1: + name: TIMECMP1 + TIMFCPM2: + name: TIMECMP2 + +"HRTIM_TIM[A-F]": + _include: strip.yaml + _modify: + "[A-F]DIER": + name: DIER + "[A-F]CR2": + name: CR2 + "[A-F]EEFR3": + name: EEFR3 diff --git a/devices/patches/hsem/h7_dual.yaml b/devices/patches/hsem/h7_dual.yaml new file mode 100644 index 000000000..b0eee704f --- /dev/null +++ b/devices/patches/hsem/h7_dual.yaml @@ -0,0 +1,8 @@ +C[12]IER: + _split: ISE +C[12]ICR: + _split: ISC +C[12]ISR: + _split: ISF +C[12]MISR: + _split: MISF diff --git a/devices/patches/hsem/h7_dual_cm4.yaml b/devices/patches/hsem/h7_dual_cm4.yaml new file mode 100644 index 000000000..f8260f598 --- /dev/null +++ b/devices/patches/hsem/h7_dual_cm4.yaml @@ -0,0 +1,6 @@ +_modify: + _interrupts: + HSEM0: + name: HSEM1 + description: HSEM global interrupt 2 + value: 126 diff --git a/devices/patches/hsem/h7_single.yaml b/devices/patches/hsem/h7_single.yaml new file mode 100644 index 000000000..7848382af --- /dev/null +++ b/devices/patches/hsem/h7_single.yaml @@ -0,0 +1,9 @@ +_modify: + ICR: + access: read-write +CR: + _modify: + "?~MASTERID": + bitWidth: 4 + "?~COREID": + name: MASTERID diff --git a/devices/patches/hsem/isem.yaml b/devices/patches/hsem/isem.yaml new file mode 100644 index 000000000..cb15690b8 --- /dev/null +++ b/devices/patches/hsem/isem.yaml @@ -0,0 +1,12 @@ +IER: + _strip: ISEM + _prefix: ISE +ICR: + _strip: ISEM + _prefix: ISC +ISR: + _strip: ISEM + _prefix: ISF +MISR: + _strip: ISEM + _prefix: MISF diff --git a/devices/patches/i2c/f4_fmpi2c.yaml b/devices/patches/i2c/f4_fmpi2c.yaml new file mode 100644 index 000000000..f3f5cce6a --- /dev/null +++ b/devices/patches/i2c/f4_fmpi2c.yaml @@ -0,0 +1,18 @@ +# Fix incorrect fields names in FMPI2C +CR1: + _modify: + TCDMAEN: + name: TXDMAEN + ADDRE: + name: ADDRIE +CR2: + _merge: + - SADD* +OAR2: + _modify: + OA21_7: + name: OA2 +ICR: + _modify: + "ALERTC,ALERTCF": + name: ALERTCF diff --git a/devices/patches/i2c/g0.yaml b/devices/patches/i2c/g0.yaml new file mode 100644 index 000000000..090195928 --- /dev/null +++ b/devices/patches/i2c/g0.yaml @@ -0,0 +1,10 @@ +OAR1: + _delete: + - OA1_0 + - OA1_7_1 + - OA1_8_9 + _add: + OA1: + description: Interface address + bitOffset: 0 + bitWidth: 10 diff --git a/devices/patches/i2c/merge_CR2_SADDx_fields.yaml b/devices/patches/i2c/merge_CR2_SADDx_fields.yaml new file mode 100644 index 000000000..5483994d1 --- /dev/null +++ b/devices/patches/i2c/merge_CR2_SADDx_fields.yaml @@ -0,0 +1,4 @@ +# Merge together I2C CR2 wrongly separated SADDx fields + +CR2: + _merge: SADD* diff --git a/devices/patches/i2c/merge_OAR1_OA1x_fields.yaml b/devices/patches/i2c/merge_OAR1_OA1x_fields.yaml new file mode 100644 index 000000000..218748757 --- /dev/null +++ b/devices/patches/i2c/merge_OAR1_OA1x_fields.yaml @@ -0,0 +1,5 @@ +# Merge together I2C OAR1 wrongly separated 0A1x fields + +OAR1: + _merge: + OA1: OA1_? diff --git a/devices/patches/i2c/v1_fltr.yaml b/devices/patches/i2c/v1_fltr.yaml new file mode 100644 index 000000000..54fc2860d --- /dev/null +++ b/devices/patches/i2c/v1_fltr.yaml @@ -0,0 +1,16 @@ +_add: + # FLTR register (defined in RM0368 for example) + FLTR: + description: FLTR register + addressOffset: 0x24 + access: read-write + resetValue: 0x0000 + fields: + ANOFF: + description: Analog noise filter + bitOffset: 4 + bitWidth: 1 + DNF: + description: Digital noise filter + bitOffset: 0 + bitWidth: 4 diff --git a/devices/patches/icache/l5.yaml b/devices/patches/icache/l5.yaml new file mode 100644 index 000000000..b7998c91b --- /dev/null +++ b/devices/patches/icache/l5.yaml @@ -0,0 +1,7 @@ +_modify: + ICache: + name: ICACHE + +ICACHE: + _strip: + - ICACHE_ diff --git a/devices/patches/iwdg/add_onf.yaml b/devices/patches/iwdg/add_onf.yaml new file mode 100644 index 000000000..9c2926756 --- /dev/null +++ b/devices/patches/iwdg/add_onf.yaml @@ -0,0 +1,9 @@ +SR: + _add: + ONF: + description: "Watchdog enable status bit. + Set to ‘1’ by hardware as soon as the IWDG is started. In software mode, it remains to '1' until + the IWDG is reset. In hardware mode, this bit is always set to '1'." + bitOffset: 8 + bitWidth: 1 + access: read-only \ No newline at end of file diff --git a/devices/patches/lcd/ram_segment_40.yaml b/devices/patches/lcd/ram_segment_40.yaml new file mode 100644 index 000000000..6543b6474 --- /dev/null +++ b/devices/patches/lcd/ram_segment_40.yaml @@ -0,0 +1,45 @@ +# LCD RAM_COM registers are 64 bit wide, not 32. +_add: + RAM_COM0: + displayName: RAM_COM0 + description: LCD display memory + addressOffset: 0x14 + size: 0x40 + access: read-write + resetValue: 0 + fields: + SEGS: + description: "Segment states, one bit per segment, LSB: S00, MSB: S39" + bitOffset: 0 + bitWidth: 40 + RAM_COM4: + displayName: RAM_COM4 + description: LCD display memory + addressOffset: 0x34 + size: 0x40 + access: read-write + resetValue: 0 + fields: + SEGS: + description: "Segment states, one bit per segment, LSB: S00, MSB: S43" + bitOffset: 0 + bitWidth: 44 +_derive: + RAM_COM1: + _from: RAM_COM0 + addressOffset: 0x1C + RAM_COM2: + _from: RAM_COM0 + addressOffset: 0x24 + RAM_COM3: + _from: RAM_COM0 + addressOffset: 0x2C + RAM_COM5: + _from: RAM_COM4 + addressOffset: 0x3C + RAM_COM6: + _from: RAM_COM4 + addressOffset: 0x44 + RAM_COM7: + _from: RAM_COM4 + addressOffset: 0x4C diff --git a/devices/patches/lcd/ram_segment_48.yaml b/devices/patches/lcd/ram_segment_48.yaml new file mode 100644 index 000000000..2b3b2275a --- /dev/null +++ b/devices/patches/lcd/ram_segment_48.yaml @@ -0,0 +1,45 @@ +# LCD RAM_COM registers are 64 bit wide, not 32. +_add: + RAM_COM0: + displayName: RAM_COM0 + description: LCD display memory + addressOffset: 0x14 + size: 0x40 + access: read-write + resetValue: 0 + fields: + SEGS: + description: "Segment states, one bit per segment, LSB: S00, MSB: S47" + bitOffset: 0 + bitWidth: 48 + RAM_COM4: + displayName: RAM_COM4 + description: LCD display memory + addressOffset: 0x34 + size: 0x40 + access: read-write + resetValue: 0 + fields: + SEGS: + description: "Segment states, one bit per segment, LSB: S00, MSB: S51" + bitOffset: 0 + bitWidth: 52 +_derive: + RAM_COM1: + _from: RAM_COM0 + addressOffset: 0x1C + RAM_COM2: + _from: RAM_COM0 + addressOffset: 0x24 + RAM_COM3: + _from: RAM_COM0 + addressOffset: 0x2C + RAM_COM5: + _from: RAM_COM4 + addressOffset: 0x3C + RAM_COM6: + _from: RAM_COM4 + addressOffset: 0x44 + RAM_COM7: + _from: RAM_COM4 + addressOffset: 0x4C diff --git a/devices/patches/ltdc/f4_f7_ltdc_bccr.yaml b/devices/patches/ltdc/f4_f7_ltdc_bccr.yaml new file mode 100644 index 000000000..d951b630e --- /dev/null +++ b/devices/patches/ltdc/f4_f7_ltdc_bccr.yaml @@ -0,0 +1,18 @@ +BCCR: + # Some F4 and F7 SVDs have a single field BC of width 24 + # Split this into one field per channel, according to the RM + _delete: + - BC + _add: + BCBLUE: + description: Background color blue value + bitOffset: 0 + bitWidth: 8 + BCGREEN: + description: Background color green value + bitOffset: 8 + bitWidth: 8 + BCRED: + description: Background color red value + bitOffset: 16 + bitWidth: 8 diff --git a/devices/patches/ltdc/f7_ltdc_interrupts.yaml b/devices/patches/ltdc/f7_ltdc_interrupts.yaml new file mode 100644 index 000000000..98d808f43 --- /dev/null +++ b/devices/patches/ltdc/f7_ltdc_interrupts.yaml @@ -0,0 +1,14 @@ +# The LTDC interrupts are both named "LCD-TFT" in the SVD files and the reference manuals. + +_delete: + _interrupts: + - "*" + +_add: + _interrupts: + LTDC: + description: LTDC global interrupt + value: 88 + LTDC_ER: + description: LTDC global error interrupt + value: 89 diff --git a/devices/patches/ltdc/ltdc.yaml b/devices/patches/ltdc/ltdc.yaml new file mode 100644 index 000000000..42ba30b96 --- /dev/null +++ b/devices/patches/ltdc/ltdc.yaml @@ -0,0 +1,22 @@ +SSCR: + _modify: + HSW: + # SVD says 10; RM says 12 + bitWidth: 12 +BPCR: + _modify: + AHBP: + # SVD says 10; RM says 12 + bitWidth: 12 +AWCR: + _modify: + AAV: + name: AAW + description: Accumulated Active Width (in units of pixel clock period) + # SVD says 10; RM says 12 + bitWidth: 12 +TWCR: + _modify: + TOTALW: + # SVD says 10; RM says 12 + bitWidth: 12 diff --git a/devices/patches/ltdc/rename.yaml b/devices/patches/ltdc/rename.yaml new file mode 100644 index 000000000..06af82973 --- /dev/null +++ b/devices/patches/ltdc/rename.yaml @@ -0,0 +1,8 @@ +# Several devices have the LTDC peripheral misnamed as LTCD. + +_modify: + _peripherals: + LTCD: + name: LTDC + groupName: LTDC + description: LCD-TFT display controller diff --git a/devices/patches/mpu_unprefix_registers.yaml b/devices/patches/mpu_unprefix_registers.yaml new file mode 100644 index 000000000..61d1bb53e --- /dev/null +++ b/devices/patches/mpu_unprefix_registers.yaml @@ -0,0 +1,160 @@ +ADC: + _strip: ADC_ + +ADC?: + _strip: + - ADC_ + - ADC?_ + +AXIMC_Mx: + _strip: AXIMC_ + +BSEC: + _strip: BSEC_ + +CCU: + _strip: FCCAN_CCU_ + +CRC?: + _strip: CRC_ + +CRYP?: + _strip: CRYP_ + +DAC?: + _strip: DAC_ + +DCMI: + _strip: DCMI_ + +DDRCTRL: + _strip: DDRCTRL_ + +DDRPERFM: + _strip: DDRPERFM_ + +DDRPHYC: + _strip: DDRPHYC_ + +DFSDM?: + _strip: DFSDM_ + +DLYB*: + _strip: DLYB_ + +DMA?: + _strip: DMA_ + +DMAMUX?: + _strip: DMAMUX_ + +DTS: + _strip: DTS_ + +ETH_DMA: + _strip: ETH_ + +ETH_MAC_MMC: + _strip: ETH_ + +ETH_MTL: + _strip: ETH_ + +ETZPC: + _strip: ETZPC_ + +EXTI: + _strip: EXTI_ + +FDCAN?: + _strip: FDCAN_ + +FMC: + _strip: FMC_ + +GIC?: + _strip: GIC?_ + +GPIO?: + _strip: GPIO?_ + +HASH?: + _strip: HASH_ + +HDMI_CEC: + _strip: CEC_ + +HDP: + _strip: HDP_ + +HSEM: + _strip: HSEM_ + +I2C?: + _strip: I2C_ + +IPCC: + _strip: IPCC_ + +LPTIM?: + _strip: LPTIM_ + +LTDC: + _strip: LTDC_ + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + +OTG: + _strip: OTG_ + +PWR: + _strip: PWR_ + +QUADSPI: + _strip: QUADSPI_ + +RCC: + _strip: RCC_ + +RNG?: + _strip: RNG_ + +RTC: + _strip: RTC_ + +SAI?: + _strip: SAI_ + +SDMMC?: + _strip: SDMMC_ + +SPDIFRX: + _strip: SPDIFRX_ + +SPI?: + _strip: SPI_ + +STGEN?: + _strip: STGEN?_ + +SYSCFG: + _strip: SYSCFG_ + +TAMP: + _strip: TAMP_ + +TIM*: + _strip: TIM*_ + +TZC: + _strip: TZC_ + +USBPHYC: + _strip: USBPHYC_ + +VREFBUF: + _strip: VREFBUF_ diff --git a/devices/common_patches/2_nvic_prio_bits.yaml b/devices/patches/nvic/2_prio_bits.yaml similarity index 100% rename from devices/common_patches/2_nvic_prio_bits.yaml rename to devices/patches/nvic/2_prio_bits.yaml diff --git a/devices/common_patches/4_nvic_prio_bits.yaml b/devices/patches/nvic/4_prio_bits.yaml similarity index 100% rename from devices/common_patches/4_nvic_prio_bits.yaml rename to devices/patches/nvic/4_prio_bits.yaml diff --git a/devices/common_patches/l0_nvic_prio_bits.yaml b/devices/patches/nvic/l0_prio_bits.yaml similarity index 100% rename from devices/common_patches/l0_nvic_prio_bits.yaml rename to devices/patches/nvic/l0_prio_bits.yaml diff --git a/devices/patches/octospi/add_wrap.yaml b/devices/patches/octospi/add_wrap.yaml new file mode 100644 index 000000000..99f886708 --- /dev/null +++ b/devices/patches/octospi/add_wrap.yaml @@ -0,0 +1,92 @@ +_add: + WPCCR: + description: wrap communication configuration register + addressOffset: 0x140 + resetValue: 0x00000000 + fields: + DQSE: + description: DQS enable + bitOffset: 29 + bitWidth: 1 + DDTR: + description: Data double transfer rate + bitOffset: 27 + bitWidth: 1 + DMODE: + description: Data mode + bitOffset: 24 + bitWidth: 3 + ABSIZE: + description: Alternate bytes size + bitOffset: 20 + bitWidth: 2 + ABDTR: + description: Alternate bytes double transfer rate + bitOffset: 19 + bitWidth: 1 + ABMODE: + description: Alternate-byte mode + bitOffset: 16 + bitWidth: 3 + ADSIZE: + description: Address size + bitOffset: 12 + bitWidth: 2 + ADDTR: + description: Address double transfer rate + bitOffset: 11 + bitWidth: 1 + ADMODE: + description: Address mode + bitOffset: 8 + bitWidth: 3 + ISIZE: + description: Instruction size + bitOffset: 4 + bitWidth: 2 + IDTR: + description: Instruction double transfer rate + bitOffset: 3 + bitWidth: 1 + IMODE: + description: Instruction mode + bitOffset: 0 + bitWidth: 3 + + WPTCR: + description: Wrap timing configuration register + addressOffset: 0x148 + resetValue: 0x00000000 + fields: + SSHIFT: + description: Sample shift + bitOffset: 30 + bitWidth: 1 + DHQC: + description: Delay hold quarter cycle + bitOffset: 28 + bitWidth: 1 + DCYC: + description: Number of dummy cycles + bitOffset: 0 + bitWidth: 5 + + WPIR: + description: Wrap instruction register + addressOffset: 0x150 + resetValue: 0x00000000 + fields: + INSTRUCTION: + description: Instruction + bitOffset: 0 + bitWidth: 32 + + WPABR: + description: Wrap alternate bytes register + addressOffset: 0x160 + resetValue: 0x00000000 + fields: + ALTERNATE: + description: Alternate bytes + bitOffset: 0 + bitWidth: 32 diff --git a/devices/patches/octospi/address.yaml b/devices/patches/octospi/address.yaml new file mode 100644 index 000000000..6c6094161 --- /dev/null +++ b/devices/patches/octospi/address.yaml @@ -0,0 +1,4 @@ +AR: + _modify: + ADRESS: + name: ADDRESS diff --git a/devices/patches/octospi/ddm.yaml b/devices/patches/octospi/ddm.yaml new file mode 100644 index 000000000..3f651642e --- /dev/null +++ b/devices/patches/octospi/ddm.yaml @@ -0,0 +1,5 @@ +CR: + _modify: + DQM: + name: DMM + description: Dual-memory configuration diff --git a/devices/patches/octospi/h7.yaml b/devices/patches/octospi/h7.yaml new file mode 100644 index 000000000..03f57e13b --- /dev/null +++ b/devices/patches/octospi/h7.yaml @@ -0,0 +1,19 @@ +# OCTOSPI v1 peripheral on at least H7 + +_include: + - address.yaml + - ddm.yaml + +DCR1: + _add: + DLYBYP: + description: Delay block bypass + bitWidth: 1 + bitOffset: 3 + _modify: + MTYP: + bitWidth: 3 +DCR4: + _modify: + REFRESH: + bitWidth: 32 diff --git a/devices/patches/octospi/l4+.yaml b/devices/patches/octospi/l4+.yaml new file mode 100644 index 000000000..6b550b141 --- /dev/null +++ b/devices/patches/octospi/l4+.yaml @@ -0,0 +1,49 @@ +_include: + - ddm.yaml + - add_wrap.yaml + +_delete: + - HWCFGR + - VER + - ID + - MID + +_add: + DCR4: + displayName: DCR4 + description: device configuration register 4 + addressOffset: 0x14 + access: read-write + resetValue: 0x00000000 + fields: + REFRESH: + description: Refresh rate + bitOffset: 0 + bitWidth: 32 + +_modify: + SR: + access: read-only + +DCR1: + _modify: + MTYP: + bitWidth: 3 + CSHT: + bitWidth: 6 + + _add: + DLYBYP: + description: Delay block bypass + bitOffset: 3 + bitWidth: 1 + +DCR3: + _add: + MAXTRAN: + description: Maximum transfer + bitOffset: 0 + bitWidth: 8 + +WCCR: + _delete: SIOO diff --git a/devices/patches/octospi/u5.yaml b/devices/patches/octospi/u5.yaml new file mode 100644 index 000000000..be81eca1b --- /dev/null +++ b/devices/patches/octospi/u5.yaml @@ -0,0 +1,10 @@ +CR: + _modify: + FTHRES: + description: FIFO threshold level + FSEL: + name: MSEL + description: External memory select + DQM: + name: DMM + description: Dual-memory configuration diff --git a/devices/patches/octospi/u535_u545.yaml b/devices/patches/octospi/u535_u545.yaml new file mode 100644 index 000000000..f7f73d7d2 --- /dev/null +++ b/devices/patches/octospi/u535_u545.yaml @@ -0,0 +1,9 @@ +_include: + - u5.yaml + +"*CCR": + _add: + ADSIZE: + description: Address size + bitOffset: 12 + bitWidth: 2 diff --git a/devices/patches/octospim/l4+.yaml b/devices/patches/octospim/l4+.yaml new file mode 100644 index 000000000..75c2b72f5 --- /dev/null +++ b/devices/patches/octospim/l4+.yaml @@ -0,0 +1,14 @@ +_add: + CR: + description: configuration register + addressOffset: 0x0 + resetValue: 0x0 + fields: + MUXEN: + description: Multiplexed mode enable + bitOffset: 0 + bitWidth: 1 + REQ2ACK_TIME: + description: REQ to ACK time + bitOffset: 16 + bitWidth: 8 diff --git a/devices/common_patches/f3_opamp12.yaml b/devices/patches/opamp/f3_opamp12.yaml similarity index 100% rename from devices/common_patches/f3_opamp12.yaml rename to devices/patches/opamp/f3_opamp12.yaml diff --git a/devices/common_patches/f3_opamp1234.yaml b/devices/patches/opamp/f3_opamp1234.yaml similarity index 100% rename from devices/common_patches/f3_opamp1234.yaml rename to devices/patches/opamp/f3_opamp1234.yaml diff --git a/devices/common_patches/f3_opamp2.yaml b/devices/patches/opamp/f3_opamp2.yaml similarity index 99% rename from devices/common_patches/f3_opamp2.yaml rename to devices/patches/opamp/f3_opamp2.yaml index 910b0280a..2a1d3a088 100644 --- a/devices/common_patches/f3_opamp2.yaml +++ b/devices/patches/opamp/f3_opamp2.yaml @@ -20,7 +20,7 @@ _add: access: read-write OPAMP: - "OPAMP*_CSR": + OPAMP*_CSR: _add: FORCE_VP: description: FORCE_VP diff --git a/devices/patches/pssi/pssi.yaml b/devices/patches/pssi/pssi.yaml new file mode 100644 index 000000000..b5e28797c --- /dev/null +++ b/devices/patches/pssi/pssi.yaml @@ -0,0 +1,134 @@ +_add: + PSSI: + baseAddress: 0x50050400 + description: Parallel synchronous slave interface + groupName: PSSI + addressBlock: + offset: 0x0 + size: 0x400 + usage: registers + + registers: + CR: + description: PSSI control register + addressOffset: 0x0 + size: 0x20 + access: read-write + resetValue: 0x40000000 + fields: + OUTEN: + description: Data direction selection bit + bitOffset: 31 + bitWidth: 1 + DMAEN: + description: DMA enable bit + bitOffset: 30 + bitWidth: 1 + DERDYCFG: + description: Data enable and ready configuration + bitOffset: 18 + bitWidth: 3 + ENABLE: + description: PSSI enable + bitOffset: 14 + bitWidth: 1 + EDM: + description: Extended data mode + bitOffset: 10 + bitWidth: 2 + RDYPOL: + description: Ready (PSSI_RDY) polarity + bitOffset: 8 + bitWidth: 1 + DEPOL: + description: Data enable (PSSI_DE) polarity + bitOffset: 6 + bitWidth: 1 + CKPOL: + description: Parallel data clock polarity + bitOffset: 5 + bitWidth: 1 + + SR: + description: PSSI status register + addressOffset: 0x4 + size: 0x20 + access: read-only + resetValue: 0x00000000 + fields: + RTT1B: + description: FIFO is ready to transfer one byte + bitOffset: 3 + bitWidth: 1 + RTT4B: + description: FIFO is ready to transfer four bytes + bitOffset: 2 + bitWidth: 1 + + RIS: + description: PSSI raw interrupt status register + addressOffset: 0x8 + size: 0x20 + access: read-only + resetValue: 0x00000000 + fields: + OVR_RIS: + description: Data buffer overrun/underrun raw interrupt status + bitOffset: 1 + bitWidth: 1 + + IER: + description: PSSI interrupt enable register + addressOffset: 0xC + size: 0x20 + access: read-write + resetValue: 0x00000000 + fields: + OVR_IE: + description: Data buffer overrun/underrun interrupt enable + bitOffset: 1 + bitWidth: 1 + + MIS: + description: PSSI masked interrupt status register + addressOffset: 0x10 + size: 0x20 + access: read-only + resetValue: 0x00000000 + fields: + OVR_MIS: + description: Data buffer overrun/underrun masked interrupt status + bitOffset: 1 + bitWidth: 1 + + ICR: + description: PSSI interrupt clear register + addressOffset: 0x14 + size: 0x20 + access: write-only + resetValue: 0x00000000 + fields: + OVR_ISC: + description: Data buffer overrun/underrun interrupt status clear + bitOffset: 1 + bitWidth: 1 + + DR: + description: PSSI data register + addressOffset: 0x28 + size: 0x20 + access: read-write + resetValue: 0x00000000 + fields: + BYTE3: + bitOffset: 24 + bitWidth: 8 + BYTE2: + bitOffset: 16 + bitWidth: 8 + BYTE1: + bitOffset: 8 + bitWidth: 8 + BYTE0: + bitOffset: 0 + bitWidth: 8 diff --git a/devices/patches/pwr/add_cr5.yaml b/devices/patches/pwr/add_cr5.yaml new file mode 100644 index 000000000..427a81901 --- /dev/null +++ b/devices/patches/pwr/add_cr5.yaml @@ -0,0 +1,5 @@ +_add: + CR5: + addressOffset: 0xAC + size: 0x20 + resetValue: 0x00000000 diff --git a/devices/patches/pwr/add_ewup.yaml b/devices/patches/pwr/add_ewup.yaml new file mode 100644 index 000000000..4f7ade5e6 --- /dev/null +++ b/devices/patches/pwr/add_ewup.yaml @@ -0,0 +1,14 @@ +CSR: + _modify: + EWUP: + name: EWUP1 + description: Enable WKUP1 pin (PA0) + _add: + EWUP2: + description: Enable WKUP1 pin (PC0) + bitOffset: 7 + bitWidth: 1 + EWUP3: + description: Enable WKUP1 pin (PC1) + bitOffset: 6 + bitWidth: 1 diff --git a/devices/patches/pwr/add_sleep.yaml b/devices/patches/pwr/add_sleep.yaml new file mode 100644 index 000000000..d25805891 --- /dev/null +++ b/devices/patches/pwr/add_sleep.yaml @@ -0,0 +1,18 @@ +CR: + _add: + FISSR: + description: Flash Interface Stop while System Run + bitOffset: 21 + bitWidth: 1 + FMSSR: + description: Flash Memory Sleep System Run + bitOffset: 20 + bitWidth: 1 + MRLVDS: + description: Main regulator Low Voltage in Deep Sleep + bitOffset: 11 + bitWidth: 1 + LPLVDS: + description: Low-power regulator Low Voltage in Deep Sleep + bitOffset: 10 + bitWidth: 1 diff --git a/devices/patches/pwr/add_step_down.yaml b/devices/patches/pwr/add_step_down.yaml new file mode 100644 index 000000000..4540a6d78 --- /dev/null +++ b/devices/patches/pwr/add_step_down.yaml @@ -0,0 +1,14 @@ +CR3: + _add: + SDEXTHP: + description: SMPS step-down converter forced ON and in High Power MR mode + bitOffset: 3 + bitWidth: 1 + SDLEVEL: + description: SMPS step-down converter voltage output level selection + bitOffset: 4 + bitWidth: 2 + SDEXTRDY: + description: SMPS step-down converter external supply ready + bitOffset: 16 + bitWidth: 1 diff --git a/devices/patches/pwr/f4.yaml b/devices/patches/pwr/f4.yaml new file mode 100644 index 000000000..50c20e550 --- /dev/null +++ b/devices/patches/pwr/f4.yaml @@ -0,0 +1,4 @@ +CSR: + _modify: + VOSRDY: + access: read-only diff --git a/devices/patches/pwr/h7_dual.yaml b/devices/patches/pwr/h7_dual.yaml new file mode 100644 index 000000000..00c542019 --- /dev/null +++ b/devices/patches/pwr/h7_dual.yaml @@ -0,0 +1,67 @@ +_modify: + CPUCR: + name: CPU1CR + displayName: CPU1CR +CPU1CR: + _add: + HOLD2F: + description: CPU2 in hold wakeup flag. This flag also generates a CPU1 interrupt. CPU1 has been woken up from a CPU2 wakeup source with CPU2 on hold. This flag is set by hardware and cleared only by a system reset or by setting the CPU1 CSSF bit. + bitOffset: 4 + bitWidth: 1 + HOLD2: + description: Hold the CPU2 and allocated peripherals when exiting from Stop mode. + bitOffset: 10 + bitWidth: 1 +_add: + _registers: + CPU2CR: + displayname: CPU2CR + description: This register allows controlling CPU2 power + addressOffset: 0x14 + size: 0x20 + resetValue: 0x00000000 + fields: + PDDS_D1: + description: D1 domain Power Down Deepsleep selection. This bit allows CPU2 to define the Deepsleep mode for D1 domain + bitOffset: 0 + bitWidth: 1 + PDDS_D2: + description: D2 domain Power Down Deepsleep selection. This bit allows CPU2 to define the Deepsleep mode for D2 domain + bitOffset: 1 + bitWidth: 1 + PDDS_D3: + description: D3 domain Power Down Deepsleep selection. This bit allows CPU2 to define the Deepsleep mode for D3 domain + bitOffset: 2 + bitWidth: 1 + HOLD1F: + description: CPU1 in hold wakeup flag. This flag also generates a CPU2 interrupt. CPU2 has been woken up from a CPU1 wakeup source with CPU1 on hold. This flag is set by hardware and cleared only by a system reset or by setting the CPU2 CSSF bit. + bitOffset: 4 + bitWidth: 1 + STOPF: + description: Stop Flag. This bit is set by hardware and cleared only by any reset or by setting the CPU2 CSSF bit. + bitOffset: 5 + bitWidth: 1 + SBF: + description: System Standby flag. This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU2 CSSF bit + bitOffset: 6 + bitWidth: 1 + SBF_D1: + description: D1 domain DStandby flag. This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU2 CSSF bit + bitOffset: 7 + bitWidth: 1 + SBF_D2: + description: D2 domain DStandby flag. This bit is set by hardware and cleared by any Reset or by setting the CPU2 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode. + bitOffset: 8 + bitWidth: 1 + CSSF: + description: Clear D2 domain CPU2 Standby, Stop and HOLD flags (always read as 0) + bitOffset: 9 + bitWidth: 1 + HOLD1: + description: Hold the CPU1 and allocated peripherals when exiting from Stop mode. + bitOffset: 10 + bitWidth: 1 + RUN_D3: + description: Keep D3 domain in Run mode regardless of the other CPU subsystems modes. + bitOffset: 11 + bitWidth: 1 diff --git a/devices/patches/pwr/wkupc1246.yaml b/devices/patches/pwr/wkupc1246.yaml new file mode 100644 index 000000000..793683e55 --- /dev/null +++ b/devices/patches/pwr/wkupc1246.yaml @@ -0,0 +1,24 @@ +WKUPCR: + _delete: + - WKUPC + _add: + WKUPC1: + description: Clear Wakeup pin flag for WKUPC1 + bitWidth: 1 + bitOffset: 0 + WKUPC2: + description: Clear Wakeup pin flag for WKUPC2 + bitWidth: 1 + bitOffset: 1 + WKUPC4: + description: Clear Wakeup pin flag for WKUPC4 + bitWidth: 1 + bitOffset: 3 + WKUPC6: + description: Clear Wakeup pin flag for WKUPC6 + bitWidth: 1 + bitOffset: 5 +WKUPFR: + _delete: + - WKUPF3 + - WKUPF5 diff --git a/devices/patches/quadspi/dr_multi_access.yaml b/devices/patches/quadspi/dr_multi_access.yaml new file mode 100644 index 000000000..bd159846e --- /dev/null +++ b/devices/patches/quadspi/dr_multi_access.yaml @@ -0,0 +1,24 @@ +_modify: + DR: + description: "Data register: full word (32 bit) access" +_add: + DR16: + addressOffset: 0x20 + alternateRegister: DR + size: 0x10 + description: "Data register: half word (16 bit) access" + fields: + DATA: + description: Data + bitOffset: 0 + bitWidth: 16 + DR8: + addressOffset: 0x20 + alternateRegister: DR + size: 0x08 + description: "Data register: one byte (8 bit) access" + fields: + DATA: + description: Data + bitOffset: 0 + bitWidth: 8 diff --git a/devices/patches/ramecc/h7.yaml b/devices/patches/ramecc/h7.yaml new file mode 100644 index 000000000..816173393 --- /dev/null +++ b/devices/patches/ramecc/h7.yaml @@ -0,0 +1,7 @@ +IER: + _modify: + GECCSEIE_: + name: GECCSEIE +_modify: + M?FECR: + access: read-only diff --git a/devices/patches/rcc/LSECSSC_LSECSSF.yaml b/devices/patches/rcc/LSECSSC_LSECSSF.yaml new file mode 100644 index 000000000..bbd3fa60a --- /dev/null +++ b/devices/patches/rcc/LSECSSC_LSECSSF.yaml @@ -0,0 +1,15 @@ +CIR: + _add: + LSECSSC: + description: LSE Clock security system interrupt clear + bitOffset: 22 + bitWidth: 1 + access: write-only + LSECSSF: + description: LSE Clock security system interrupt flag + bitOffset: 6 + bitWidth: 1 + LSECSSIE: + description: LSE clock security system interrupt enable + bitOffset: 14 + bitWidth: 1 diff --git a/devices/patches/rcc/add_gpiojk.yaml b/devices/patches/rcc/add_gpiojk.yaml new file mode 100644 index 000000000..62b02d084 --- /dev/null +++ b/devices/patches/rcc/add_gpiojk.yaml @@ -0,0 +1,30 @@ +AHB1RSTR: + _add: + GPIOJRST: + description: IO port J reset + bitOffset: 9 + bitWidth: 1 + GPIOKRST: + description: IO port K reset + bitOffset: 10 + bitWidth: 1 +AHB1ENR: + _add: + GPIOJEN: + description: IO port J clock enable + bitOffset: 9 + bitWidth: 1 + GPIOKEN: + description: IO port K clock enable + bitOffset: 10 + bitWidth: 1 +AHB1LPENR: + _add: + GPIOJLPEN: + description: IO port J clock enable during Sleep mode + bitOffset: 9 + bitWidth: 1 + GPIOKLPEN: + description: IO port K clock enable during Sleep mode + bitOffset: 10 + bitWidth: 1 diff --git a/devices/patches/rcc/add_plli2sm.yaml b/devices/patches/rcc/add_plli2sm.yaml new file mode 100644 index 000000000..3059f5191 --- /dev/null +++ b/devices/patches/rcc/add_plli2sm.yaml @@ -0,0 +1,6 @@ +PLLI2SCFGR: + _add: + PLLI2SM: + description: Division factor for the audio PLL (PLLI2S) input clock + bitOffset: 0 + bitWidth: 6 diff --git a/devices/patches/rcc/add_plli2sp.yaml b/devices/patches/rcc/add_plli2sp.yaml new file mode 100644 index 000000000..87b4f2af8 --- /dev/null +++ b/devices/patches/rcc/add_plli2sp.yaml @@ -0,0 +1,6 @@ +PLLI2SCFGR: + _add: + PLLI2SP: + description: PLLI2S division factor for SPDIFRX clock + bitOffset: 16 + bitWidth: 2 diff --git a/devices/patches/rcc/add_plli2sq_sai.yaml b/devices/patches/rcc/add_plli2sq_sai.yaml new file mode 100644 index 000000000..e701663b0 --- /dev/null +++ b/devices/patches/rcc/add_plli2sq_sai.yaml @@ -0,0 +1,6 @@ +PLLI2SCFGR: + _add: + PLLI2SQ: + description: PLLI2S division factor for SAI1 clock + bitOffset: 24 + bitWidth: 4 diff --git a/devices/patches/rcc/dma2d_ltdc.yaml b/devices/patches/rcc/dma2d_ltdc.yaml new file mode 100644 index 000000000..1fc1e70c4 --- /dev/null +++ b/devices/patches/rcc/dma2d_ltdc.yaml @@ -0,0 +1,31 @@ +# Add missing reset/enable bits for the LCD controller and 2D-DMA +AHB1RSTR: + _add: + DMA2DRST: + description: DMA2D reset + bitOffset: 23 + bitWidth: 1 +APB2RSTR: + _add: + LTDCRST: + description: LTDC reset + bitOffset: 26 + bitWidth: 1 +AHB1ENR: + _add: + DMA2DEN: + description: DMA2D clock enable + bitOffset: 23 + bitWidth: 1 +AHB1LPENR: + _add: + DMA2DLPEN: + description: DMA2D clock enable during Sleep mode + bitOffset: 23 + bitWidth: 1 +APB2LPENR: + _add: + LTDCLPEN: + description: LTDC clock enable during Sleep mode + bitOffset: 26 + bitWidth: 1 diff --git a/devices/patches/rcc/f0_dmaen.yaml b/devices/patches/rcc/f0_dmaen.yaml new file mode 100644 index 000000000..5eeae1c00 --- /dev/null +++ b/devices/patches/rcc/f0_dmaen.yaml @@ -0,0 +1,5 @@ +AHBENR: + _modify: + DMA1EN: + name: DMAEN + description: DMA clock enable diff --git a/devices/patches/rcc/f0_gpioe.yaml b/devices/patches/rcc/f0_gpioe.yaml new file mode 100644 index 000000000..7e3b13bcc --- /dev/null +++ b/devices/patches/rcc/f0_gpioe.yaml @@ -0,0 +1,12 @@ +AHBENR: + _add: + IOPEEN: + description: I/O port E clock enable + bitOffset: 21 + bitWidth: 1 +AHBRSTR: + _add: + IOPERST: + description: I/O port E reset + bitOffset: 21 + bitWidth: 1 diff --git a/devices/patches/rcc/f0_hsi48cal.yaml b/devices/patches/rcc/f0_hsi48cal.yaml new file mode 100644 index 000000000..697f3adf2 --- /dev/null +++ b/devices/patches/rcc/f0_hsi48cal.yaml @@ -0,0 +1,4 @@ +CR2: + _modify: + HSI48CAL: + bitWidth: 8 diff --git a/devices/patches/rcc/f0_no_hdmi_cec.yaml b/devices/patches/rcc/f0_no_hdmi_cec.yaml new file mode 100644 index 000000000..dda892c73 --- /dev/null +++ b/devices/patches/rcc/f0_no_hdmi_cec.yaml @@ -0,0 +1,3 @@ +CFGR3: + _delete: + - CECSW diff --git a/devices/patches/rcc/f0_usart3.yaml b/devices/patches/rcc/f0_usart3.yaml new file mode 100644 index 000000000..825b70d85 --- /dev/null +++ b/devices/patches/rcc/f0_usart3.yaml @@ -0,0 +1,6 @@ +CFGR3: + _add: + USART3SW: + description: USART3 clock source + bitOffset: 18 + bitWidth: 2 diff --git a/devices/patches/rcc/f0_usart6.yaml b/devices/patches/rcc/f0_usart6.yaml new file mode 100644 index 000000000..94f3b5a17 --- /dev/null +++ b/devices/patches/rcc/f0_usart6.yaml @@ -0,0 +1,14 @@ +APB2RSTR: + _add: + USART6RST: + description: USART6 reset + bitOffset: 5 + bitWidth: 1 +APB2ENR: + _delete: + - USART6EN + _add: + USART6EN: + description: USART6 clock enable + bitOffset: 5 + bitWidth: 1 diff --git a/devices/patches/rcc/f0_usart78.yaml b/devices/patches/rcc/f0_usart78.yaml new file mode 100644 index 000000000..e8924d990 --- /dev/null +++ b/devices/patches/rcc/f0_usart78.yaml @@ -0,0 +1,23 @@ +APB2RSTR: + _add: + USART8RST: + description: USART8 reset + bitOffset: 7 + bitWidth: 1 + USART7RST: + description: USART7 reset + bitOffset: 6 + bitWidth: 1 +APB2ENR: + _delete: + - USART8EN + - USART7EN + _add: + USART8EN: + description: USART8 clock enable + bitOffset: 7 + bitWidth: 1 + USART7EN: + description: USART7 clock enable + bitOffset: 6 + bitWidth: 1 diff --git a/devices/patches/rcc/f0_usben.yaml b/devices/patches/rcc/f0_usben.yaml new file mode 100644 index 000000000..e6274e217 --- /dev/null +++ b/devices/patches/rcc/f0_usben.yaml @@ -0,0 +1,4 @@ +APB1ENR: + _modify: + USBRST: + name: USBEN diff --git a/devices/patches/rcc/f0_v18pwrrstf.yaml b/devices/patches/rcc/f0_v18pwrrstf.yaml new file mode 100644 index 000000000..056029ad6 --- /dev/null +++ b/devices/patches/rcc/f0_v18pwrrstf.yaml @@ -0,0 +1,7 @@ +CSR: + _add: + V18PWRRSTF: + description: 1.8 V domain reset flag + bitOffset: 23 + bitWidth: 1 + access: read-write diff --git a/devices/patches/rcc/f1_uart45.yaml b/devices/patches/rcc/f1_uart45.yaml new file mode 100644 index 000000000..006401320 --- /dev/null +++ b/devices/patches/rcc/f1_uart45.yaml @@ -0,0 +1,6 @@ +APB1RSTR: + _modify: + USART5RST: + name: UART5RST + USART4RST: + name: UART4RST diff --git a/devices/patches/rcc/f2.yaml b/devices/patches/rcc/f2.yaml new file mode 100644 index 000000000..710f96340 --- /dev/null +++ b/devices/patches/rcc/f2.yaml @@ -0,0 +1,14 @@ +CFGR: + _merge: + - "MCO1[01]" + - "MCO1PRE[012]" + - "MCO2PRE[012]" + - "MCO2[01]" + - "RTCPRE[01234]" + - "PPRE2[012]" + - "PPRE1[0123]" + - "HPRE[0123]" +PLLI2SCFGR: + _merge: + - "PLLI2SR[012]" + - "PLLI2SN[012345678]" diff --git a/devices/patches/rcc/f3.yaml b/devices/patches/rcc/f3.yaml new file mode 100644 index 000000000..be20f26f1 --- /dev/null +++ b/devices/patches/rcc/f3.yaml @@ -0,0 +1,18 @@ +APB1RSTR: + _modify: + DACRST: + name: DAC1RST +AHBENR: + _modify: + DMAEN: + name: DMA1EN +APB1ENR: + _modify: + DACEN: + name: DAC1EN +CSR: + _add: + V18PWRRSTF: + description: Reset flag of the 1.8 V domain + bitOffset: 23 + bitWidth: 1 diff --git a/devices/patches/rcc/f3_cfgr3_tim.yaml b/devices/patches/rcc/f3_cfgr3_tim.yaml new file mode 100644 index 000000000..4c2c3637f --- /dev/null +++ b/devices/patches/rcc/f3_cfgr3_tim.yaml @@ -0,0 +1,22 @@ +CFGR3: + _add: + TIM15SW: + description: Timer15 clock source selection + bitOffset: 10 + bitWidth: 1 + TIM16SW: + description: Timer16 clock source selection + bitOffset: 11 + bitWidth: 1 + TIM17SW: + description: Timer17 clock source selection + bitOffset: 13 + bitWidth: 1 + TIM2SW: + description: Timer2 clock source selection + bitOffset: 24 + bitWidth: 1 + TIM34SW: + description: Timer34 clock source selection + bitOffset: 25 + bitWidth: 1 diff --git a/devices/patches/rcc/f3_dac3_dac2.yaml b/devices/patches/rcc/f3_dac3_dac2.yaml new file mode 100644 index 000000000..d5112d19e --- /dev/null +++ b/devices/patches/rcc/f3_dac3_dac2.yaml @@ -0,0 +1,8 @@ +APB1RSTR: + _modify: + DAC3RST: + name: DAC2RST +APB1ENR: + _modify: + DAC3EN: + name: DAC2EN diff --git a/devices/patches/rcc/f3_delete_cec.yaml b/devices/patches/rcc/f3_delete_cec.yaml new file mode 100644 index 000000000..19fccc8a2 --- /dev/null +++ b/devices/patches/rcc/f3_delete_cec.yaml @@ -0,0 +1,9 @@ +APB1RSTR: + _delete: + - CECRST +APB1ENR: + _delete: + - CECEN +CFGR3: + _delete: + - CECSW diff --git a/devices/patches/rcc/f3_delete_tim8.yaml b/devices/patches/rcc/f3_delete_tim8.yaml new file mode 100644 index 000000000..e20a68f6e --- /dev/null +++ b/devices/patches/rcc/f3_delete_tim8.yaml @@ -0,0 +1,9 @@ +APB2RSTR: + _delete: + - TIM8RST +APB2ENR: + _delete: + - TIM8EN +CFGR3: + _delete: + - TIM8SW diff --git a/devices/patches/rcc/f3_i2c3.yaml b/devices/patches/rcc/f3_i2c3.yaml new file mode 100644 index 000000000..897098fba --- /dev/null +++ b/devices/patches/rcc/f3_i2c3.yaml @@ -0,0 +1,19 @@ +# Add missing reset/enable bits for I2C 3 +APB1RSTR: + _add: + I2C3RST: + description: I2C3 reset + bitOffset: 30 + bitWidth: 1 +APB1ENR: + _add: + I2C3EN: + description: I2C3 clock enable + bitOffset: 30 + bitWidth: 1 +CFGR3: + _add: + I2C3SW: + description: I2C3 clock source selection + bitOffset: 6 + bitWidth: 1 diff --git a/devices/patches/rcc/f3_mco.yaml b/devices/patches/rcc/f3_mco.yaml new file mode 100644 index 000000000..f5242848c --- /dev/null +++ b/devices/patches/rcc/f3_mco.yaml @@ -0,0 +1,12 @@ +CFGR: + _delete: + - MCOF + _add: + MCOPRE: + description: Microcontroller Clock Output Prescaler + bitOffset: 28 + bitWidth: 3 + PLLNODIV: + description: Do not divide PLL to MCO + bitOffset: 31 + bitWidth: 1 diff --git a/devices/patches/rcc/f3_spi4.yaml b/devices/patches/rcc/f3_spi4.yaml new file mode 100644 index 000000000..a9114c242 --- /dev/null +++ b/devices/patches/rcc/f3_spi4.yaml @@ -0,0 +1,13 @@ +# Add missing reset/enable bits for SPI 4 +APB2RSTR: + _add: + SPI4RST: + description: SPI4 reset + bitOffset: 15 + bitWidth: 1 +APB2ENR: + _add: + SPI4EN: + description: SPI4 clock enable + bitOffset: 15 + bitWidth: 1 diff --git a/devices/patches/rcc/f3_tim20.yaml b/devices/patches/rcc/f3_tim20.yaml new file mode 100644 index 000000000..bb2bb7682 --- /dev/null +++ b/devices/patches/rcc/f3_tim20.yaml @@ -0,0 +1,18 @@ +APB2RSTR: + _add: + TIM20RST: + description: TIM20 timer reset + bitOffset: 20 + bitWidth: 1 +APB2ENR: + _add: + TIM20EN: + description: TIM20 timer clock enable + bitOffset: 20 + bitWidth: 1 +CFGR3: + _add: + TIM20SW: + description: Timer20 clock source selection + bitOffset: 15 + bitWidth: 1 diff --git a/devices/patches/rcc/f3_usb.yaml b/devices/patches/rcc/f3_usb.yaml new file mode 100644 index 000000000..c7aedfdff --- /dev/null +++ b/devices/patches/rcc/f3_usb.yaml @@ -0,0 +1,4 @@ +CFGR: + _modify: + USBPRES: + name: USBPRE diff --git a/devices/patches/rcc/f41x_bdcr_lsemod.yaml b/devices/patches/rcc/f41x_bdcr_lsemod.yaml new file mode 100644 index 000000000..03f6ba348 --- /dev/null +++ b/devices/patches/rcc/f41x_bdcr_lsemod.yaml @@ -0,0 +1,6 @@ +BDCR: + _add: + LSEMOD: + description: External low speed oscillator + bitOffset: 3 + bitWidth: 1 diff --git a/devices/patches/rcc/f4_dckcfgr.yaml b/devices/patches/rcc/f4_dckcfgr.yaml new file mode 100644 index 000000000..aa24ce6f5 --- /dev/null +++ b/devices/patches/rcc/f4_dckcfgr.yaml @@ -0,0 +1,12 @@ +_add: + DCKCFGR: + description: RCC Dedicated Clock Configuration Register + addressOffset: 0x8C + size: 0x20 + access: read-write + resetValue: 0x00000000 + fields: + TIMPRE: + description: Timers clocks prescalers selection + bitOffset: 24 + bitWidth: 1 diff --git a/devices/patches/rcc/f4_fmpi2c.yaml b/devices/patches/rcc/f4_fmpi2c.yaml new file mode 100644 index 000000000..11da3aaba --- /dev/null +++ b/devices/patches/rcc/f4_fmpi2c.yaml @@ -0,0 +1,16 @@ +# Rename I2C4 to FMPI2C1 +APB1RSTR: + _modify: + I2C4RST,I2CFMP1RST: + name: FMPI2C1RST + description: FMPI2C1 reset +APB1ENR: + _modify: + I2C4EN,I2CFMP1EN: + name: FMPI2C1EN + description: FMPI2C1 clock enable +APB1LPENR: + _modify: + I2C4LPEN,I2CFMP1LPEN: + name: FMPI2C1LPEN + description: FMPI2C1 clock enable during Sleep diff --git a/devices/patches/rcc/f730_f7x2_f7x3.yaml b/devices/patches/rcc/f730_f7x2_f7x3.yaml new file mode 100644 index 000000000..91da81b8e --- /dev/null +++ b/devices/patches/rcc/f730_f7x2_f7x3.yaml @@ -0,0 +1,17 @@ +APB1RSTR: + _delete: + - CECRST +AHB1LPENR: + _delete: + - ETH* + - DMA2DLPEN + - GPIOKLPEN + - GPIOJLPEN +APB1LPENR: + _delete: + - CAN2LPEN + _add: + RTCAPBLPEN: + description: RTCAPB clock enable during Sleep mode + bitOffset: 10 + bitWidth: 1 diff --git a/devices/patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml b/devices/patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml new file mode 100644 index 000000000..b629d5277 --- /dev/null +++ b/devices/patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml @@ -0,0 +1,18 @@ +AHB1ENR: + _modify: + CCMDATARAMEN: + name: DTCMRAMEN +APB1ENR: + _modify: + LPTMI1EN: + name: LPTIM1EN +AHB1LPENR: + _add: + AXILPEN: + description: AXI to AHB bridge clock enable during Sleep mode + bitOffset: 13 + bitWidth: 1 + DTCMLPEN: + description: DTCM RAM interface clock enable during Sleep mode + bitOffset: 20 + bitWidth: 1 diff --git a/devices/patches/rcc/f765_f7x7_f7x9_common.yaml b/devices/patches/rcc/f765_f7x7_f7x9_common.yaml new file mode 100644 index 000000000..dcb4751f0 --- /dev/null +++ b/devices/patches/rcc/f765_f7x7_f7x9_common.yaml @@ -0,0 +1,72 @@ +APB2RSTR: + _add: + MDIORST: + description: MDIO reset + bitOffset: 30 + bitWidth: 1 + DFSDM1RST: + description: DFSDM 1 reset + bitOffset: 29 + bitWidth: 1 + DSIRST: + description: DSI reset + bitOffset: 27 + bitWidth: 1 + SDMMC2RST: + description: SDMMC2 module reset + bitOffset: 7 + bitWidth: 1 +AHB2ENR: + _add: + JPEGEN: + description: JPEG enable + bitOffset: 1 + bitWidth: 1 +APB2ENR: + _add: + MDIOEN: + description: MDIO clock enable + bitOffset: 30 + bitWidth: 1 + DFSDM1EN: + description: DFSDM1 clock enable + bitOffset: 29 + bitWidth: 1 + DSIEN: + description: DSI clock enable + bitOffset: 27 + bitWidth: 1 + SDMMC2EN: + description: SDMMC2 clock enable + bitOffset: 7 + bitWidth: 1 +AHB2LPENR: + _add: + JPEGLPEN: + description: JPEG module enabled during Sleep mode + bitOffset: 1 + bitWidth: 1 +APB1LPENR: + _add: + CAN3LPEN: + description: CAN 3 clock enable during Sleep mode + bitOffset: 13 + bitWidth: 1 +APB2LPENR: + _add: + MDIOLPEN: + description: MDIO clock enable during Sleep mode + bitOffset: 30 + bitWidth: 1 + DFSDM1LPEN: + description: DFSDM1 clock enable during Sleep mode + bitOffset: 29 + bitWidth: 1 + DSILPEN: + description: DSI clock enable during Sleep mode + bitOffset: 27 + bitWidth: 1 + SDMMC2LPEN: + description: SDMMC2 clock enable during Sleep mode + bitOffset: 7 + bitWidth: 1 diff --git a/devices/patches/rcc/f7_apbenr.yaml b/devices/patches/rcc/f7_apbenr.yaml new file mode 100644 index 000000000..e4eab2357 --- /dev/null +++ b/devices/patches/rcc/f7_apbenr.yaml @@ -0,0 +1,14 @@ +APB1ENR: + _modify: + UART7ENR: + name: UART7EN + UART8ENR: + name: UART8EN +APB2ENR: + _modify: + SPI4ENR: + name: SPI4EN + SPI5ENR: + name: SPI5EN + SPI6ENR: + name: SPI6EN diff --git a/devices/patches/rcc/f7_dckcfgr.yaml b/devices/patches/rcc/f7_dckcfgr.yaml new file mode 100644 index 000000000..86905775a --- /dev/null +++ b/devices/patches/rcc/f7_dckcfgr.yaml @@ -0,0 +1,7 @@ +_modify: + DCKCFGR[12]: + resetValue: 0x00000000 +DCKCFGR1: + _modify: + PLLI2SDIV: + name: PLLI2SDIVQ diff --git a/devices/patches/rcc/f7_dckcfgr_RM0410.yaml b/devices/patches/rcc/f7_dckcfgr_RM0410.yaml new file mode 100644 index 000000000..8d1b44aba --- /dev/null +++ b/devices/patches/rcc/f7_dckcfgr_RM0410.yaml @@ -0,0 +1,10 @@ +DCKCFGR1: + _add: + DFSDM1SEL: + description: DFSDM1 clock source selection + bitOffset: 25 + bitWidth: 1 + ADFSDM1SEL: + description: DFSDM1 AUDIO clock source selection + bitOffset: 26 + bitWidth: 1 diff --git a/devices/patches/rcc/f7_dckcfgr_sdmmc1.yaml b/devices/patches/rcc/f7_dckcfgr_sdmmc1.yaml new file mode 100644 index 000000000..b49ab94e3 --- /dev/null +++ b/devices/patches/rcc/f7_dckcfgr_sdmmc1.yaml @@ -0,0 +1,4 @@ +DCKCFGR2: + _modify: + SDMMCSEL: + name: SDMMC1SEL diff --git a/devices/patches/rcc/f7_lsedrv.yaml b/devices/patches/rcc/f7_lsedrv.yaml new file mode 100644 index 000000000..4cd8b5f02 --- /dev/null +++ b/devices/patches/rcc/f7_lsedrv.yaml @@ -0,0 +1,7 @@ +BDCR: + _add: + LSEDRV: + description: LSE oscillator drive capability + bitOffset: 3 + bitWidth: 2 + access: read-write diff --git a/devices/patches/rcc/f7_rename_dckcfgr.yaml b/devices/patches/rcc/f7_rename_dckcfgr.yaml new file mode 100644 index 000000000..8bfb196c5 --- /dev/null +++ b/devices/patches/rcc/f7_rename_dckcfgr.yaml @@ -0,0 +1,5 @@ +_modify: + DKCFGR1: + name: DCKCFGR1 + DKCFGR2: + name: DCKCFGR2 diff --git a/devices/patches/rcc/f7x23_dckcfgr.yaml b/devices/patches/rcc/f7x23_dckcfgr.yaml new file mode 100644 index 000000000..1a652e7ff --- /dev/null +++ b/devices/patches/rcc/f7x23_dckcfgr.yaml @@ -0,0 +1,10 @@ +DCKCFGR2: + _modify: + UART1SEL: + name: USART1SEL + UART2SEL: + name: USART2SEL + UART3SEL: + name: USART3SEL + UART6SEL: + name: USART6SEL diff --git a/devices/patches/rcc/f7x23_pllsai.yaml b/devices/patches/rcc/f7x23_pllsai.yaml new file mode 100644 index 000000000..ca3bd16e3 --- /dev/null +++ b/devices/patches/rcc/f7x23_pllsai.yaml @@ -0,0 +1,4 @@ +CR: + _modify: + PLLSAIRDY: + access: read-only diff --git a/devices/patches/rcc/g0.yaml b/devices/patches/rcc/g0.yaml new file mode 100644 index 000000000..10d4eda40 --- /dev/null +++ b/devices/patches/rcc/g0.yaml @@ -0,0 +1,16 @@ +# G0 parts other that G0Bx/G0Cx + +_modify: + PLLSYSCFGR: + name: PLLCFGR + +CFGR: + _delete: + # these are only present on G0Bx/G0Cx + - MCO2PRE + - MCO2SEL + +CCIPR: + _modify: + I2S2SEL: + name: I2S1SEL diff --git a/devices/patches/rcc/g0_no_aes.yaml b/devices/patches/rcc/g0_no_aes.yaml new file mode 100644 index 000000000..66b70ec12 --- /dev/null +++ b/devices/patches/rcc/g0_no_aes.yaml @@ -0,0 +1,5 @@ +CCIPR: + _delete: + # these are only present on parts with AES support + - RNGDIV + - RNGSEL diff --git a/devices/patches/rcc/g0b.yaml b/devices/patches/rcc/g0b.yaml new file mode 100644 index 000000000..17b6aa6ad --- /dev/null +++ b/devices/patches/rcc/g0b.yaml @@ -0,0 +1,7 @@ +# G0Bx/G0Cx parts + +CCIPR: + _modify: + I2S2SEL: + name: I2C2SEL + diff --git a/devices/patches/rcc/g0x0_delete.yaml b/devices/patches/rcc/g0x0_delete.yaml new file mode 100644 index 000000000..c19337119 --- /dev/null +++ b/devices/patches/rcc/g0x0_delete.yaml @@ -0,0 +1,31 @@ +_delete: CCIPR2 +AHBRSTR: + _delete: + - DMA2RST +APBRSTR1: + _delete: + - TIM4RST + - USART[56]RST + - SPI3RST + - I2C3RST + - USBRST +AHBENR: + _delete: + - DMA2EN +APBENR1: + _delete: + - TIM4EN + - USART[56]EN + - SPI3EN + - I2C3EN + - USBEN +AHBSMENR: + _delete: + - DMA2SMEN +APBSMENR1: + _delete: + - TIM4SMEN + - USART[56]SMEN + - SPI3SMEN + - I2C3SMEN + - USBSMEN diff --git a/devices/patches/rcc/h5.yaml b/devices/patches/rcc/h5.yaml new file mode 100644 index 000000000..4ca69f801 --- /dev/null +++ b/devices/patches/rcc/h5.yaml @@ -0,0 +1,40 @@ +APB2ENR: + _modify: + USBFSEN: + name: USBEN + description: USB clock enable + +APB2LPENR: + _modify: + USBFSLPEN: + name: USBLPEN + description: USB clock enable during sleep mode + +APB2RSTR: + _modify: + USBFSRST: + name: USBRST + description: USB block reset + +CFGR1: + _modify: + SW: + bitWidth: 2 + SWS: + bitWidth: 2 + +#PLL1CFGR: +# _modify: +# DIVM1: +# name: PLL1M + +#PLL2CFGR: +# _modify: +# DIVM2: +# name: PLL2M + +CCIPR4: + _modify: + USBFSSEL: + name: USBSEL + description: USB kernel clock source selection diff --git a/devices/patches/rcc/h503.yaml b/devices/patches/rcc/h503.yaml new file mode 100644 index 000000000..6f9c6efb2 --- /dev/null +++ b/devices/patches/rcc/h503.yaml @@ -0,0 +1,70 @@ +_include: h5.yaml +_add: + PRIVCFGR: + description: RCC privilege configuration register + addressOffset: 0x114 + access: read-write + fields: + PRIV: + description: RCC functions privilege configuration + bitOffset: 1 + bitWidth: 1 + access: read-write + +APB1HENR: + _modify: + FDCAN1EN: + name: FDCANEN + description: FDCAN peripheral clock enable + +APB1HLPENR: + _modify: + FDCAN1LPEN: + name: FDCANLPEN + description: FDCAN peripheral clock enable during sleep mode + +APB1HRSTR: + _modify: + FDCAN1RST: + name: FDCANRST + description: FDCAN block reset + +AHB1ENR: + _add: + GTZC1EN: + description: GTZC1 clock enable + bitOffset: 24 + bitWidth: 1 + access: read-write + +AHB1LPENR: + _add: + GTZC1LPEN: + description: GTZC1 clock enable during sleep mode + bitOffset: 24 + bitWidth: 1 + access: read-write + +AHB2ENR: + _modify: + ADC1EN: + name: ADCEN + description: ADC peripherals clock enabled + +AHB2LPENR: + _modify: + ADC1LPEN: + name: ADCLPEN + description: ADC peripherals clock enable during sleep mode + +AHB2RSTR: + _modify: + ADC1RST: + name: ADCRST + description: ADC block reset + +CCIPR5: + _modify: + FDCAN1SEL: + name: FDCANSEL + description: FDCAN kernel clock source selection diff --git a/devices/patches/rcc/h523_h533.yaml b/devices/patches/rcc/h523_h533.yaml new file mode 100644 index 000000000..ee0944284 --- /dev/null +++ b/devices/patches/rcc/h523_h533.yaml @@ -0,0 +1,4 @@ +APB3ENR: + _modify: + VREFBUFEN: + name: VREFEN diff --git a/devices/patches/rcc/h56x_h57x.yaml b/devices/patches/rcc/h56x_h57x.yaml new file mode 100644 index 000000000..43d5f36a2 --- /dev/null +++ b/devices/patches/rcc/h56x_h57x.yaml @@ -0,0 +1,99 @@ +_include: h5.yaml +PLL1CFGR: + _modify: + DIVM1: + name: PLL1M +PLL2CFGR: + _modify: + DIVM2: + name: PLL2M +PLL3CFGR: + _modify: + DIVM3: + name: PLL3M +CCIPR2: + _modify: + USART12SEL: + name: UART12SEL +CCIPR4: + _add: + I3C2SEL: + description: I3C2 kernel clock source selection + bitOffset: 26 + bitWidth: 2 + access: read-write +AHB2ENR: + _modify: + DAC12EN: + name: DAC1EN + description: DAC clock enable + ADC12EN: + name: ADCEN + description: ADC1 and 2 peripherals clock enable +AHB2LPENR: + _modify: + DAC12LPEN: + name: DAC1LPEN + description: DAC clock enable during sleep mode + ADC12LPEN: + name: ADCLPEN + description: ADC1 and 2 peripherals clock enable during sleep mode +AHB2RSTR: + _modify: + DAC12RST: + name: DAC1RST + description: DAC block reset + ADC12RST: + name: ADCRST + description: ADC1 and 2 blocks reset +APB1HENR: + _modify: + UCPDEN: + name: UCPD1EN + description: UCPD1 clock enable + FDCAN12EN: + name: FDCANEN + description: FDCAN1 and FDCAN2 peripheral clock enable +APB1HLPENR: + _modify: + UCPDLPEN: + name: UCPD1LPEN + description: UCPD1 clock enable during sleep mode + FDCAN12LPEN: + name: FDCANLPEN + description: FDCAN1 and FDCAN2 peripheral clock enable during sleep mode +APB1HRSTR: + _modify: + UCPDRST: + name: UCPD1RST + description: UCPD1 block reset + FDCAN12RST: + name: FDCANRST + description: FDCAN1 and FDCAN2 blocks reset +APB3ENR: + _add: + I3C2EN: + description: I3C2 clock enable + bitOffset: 9 + bitWidth: 1 + access: read-write +APB3LPENR: + _add: + I3C2LPEN: + description: I3C2 clock enable during sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write +APB3RSTR: + _add: + I3C2RST: + description: I3C2 block reset + bitOffset: 9 + bitWidth: 1 + access: read-write + +CCIPR5: + _modify: + FDCAN12SEL: + name: FDCANSEL + description: FDCAN kernel clock source selection diff --git a/devices/patches/rcc/h7+.yaml b/devices/patches/rcc/h7+.yaml new file mode 100644 index 000000000..7c7d3d119 --- /dev/null +++ b/devices/patches/rcc/h7+.yaml @@ -0,0 +1,94 @@ +CFGR: + _modify: + MCO1SEL: + name: MCO1 + MCO2SEL: + name: MCO2 + +PLLCFGR: + _modify: + PLL1DIVPEN: + name: DIVP1EN + PLL1DIVQEN: + name: DIVQ1EN + PLL1DIVREN: + name: DIVR1EN + PLL1DIVSEN: + name: DIVS1EN + PLL1DIVTEN: + name: DIVT1EN + PLL1FRACLE: + name: PLL1FRACEN + + PLL2DIVPEN: + name: DIVP2EN + PLL2DIVQEN: + name: DIVQ2EN + PLL2DIVREN: + name: DIVR2EN + PLL2DIVSEN: + name: DIVS2EN + PLL2DIVTEN: + name: DIVT2EN + PLL2FRACLE: + name: PLL2FRACEN + + PLL3DIVPEN: + name: DIVP3EN + PLL3DIVQEN: + name: DIVQ3EN + PLL3DIVREN: + name: DIVR3EN + PLL3DIVSEN: + name: DIVS3EN + PLL3DIVTEN: + name: DIVT3EN + PLL3FRACLE: + name: PLL3FRACEN + +BMCFGR: + _modify: + BMPRE: + name: HPRE + +AHB1RSTR: + _modify: + ETH1RST: + name: ETH1MACRST + +AHB5RSTR: + _modify: + IOMNGRRST: + name: XSPIMRST + +AHB5ENR: + _modify: + IOMNGREN: + name: XSPIMEN + +CCIPR2: + _modify: + I2C1_I3C1SEL: + name: I2C1I3C1SEL + +_modify: + AHBPERCKSELR: + name: CCIPR1 + APB1PERCKSELR: + name: CCIPR2 + APB2PERCKSELR: + name: CCIPR3 + APB45PERCKSELR: + name: CCIPR4 + APB1RSTR1: + name: APB1LRSTR + APB1RSTR2: + name: APB1HRSTR + APB1ENR1: + name: APB1LENR + APB1ENR2: + name: APB1HENR + APB1LPENR1: + name: APB1LLPENR + APB1LPENR2: + name: APB1HLPENR diff --git a/devices/patches/rcc/h735.yaml b/devices/patches/rcc/h735.yaml new file mode 100644 index 000000000..df7a9bc6b --- /dev/null +++ b/devices/patches/rcc/h735.yaml @@ -0,0 +1,46 @@ +_include: h7_usb1otghs.yaml +_modify: + CIFR: + access: read-only +CR: + _modify: + RC48ON: + name: HSI48ON + RC48RDY: + name: HSI48RDY +CIER: + _modify: + RC48RDYIE: + name: HSI48RDYIE +CIFR: + _modify: + RC48RDYF: + name: HSI48RDYF +CICR: + _modify: + RC48RDYC: + name: HSI48RDYC +APB1LRSTR: + _modify: + USART7RST: + name: UART7RST + description: UART7 block reset + USART8RST: + name: UART8RST + description: UART8 block reset +APB1LLPENR: + _modify: + USART7LPEN: + name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + USART8LPEN: + name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode +C1_APB1LLPENR: + _modify: + USART7LPEN: + name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + USART8LPEN: + name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode diff --git a/devices/patches/rcc/h7_common_dualcore.yaml b/devices/patches/rcc/h7_common_dualcore.yaml new file mode 100644 index 000000000..3d2cee2bc --- /dev/null +++ b/devices/patches/rcc/h7_common_dualcore.yaml @@ -0,0 +1,185 @@ +_modify: + CIFR: + access: read-only + +D3CFGR: + _delete: "*" + _add: + D3PPRE: + description: D3 domain APB4 prescaler + bitOffset: 4 + bitWidth: 3 +D1CCIPR: + _add: + DSISEL: + description: kernel clock source selection + bitOffset: 8 + bitWidth: 1 + +CSICFGR: + _modify: + CSICAL: + bitWidth: 10 +CR: + _modify: + RC48ON: + name: HSI48ON + RC48RDY: + name: HSI48RDY +CRRCR: + _modify: + RC48CAL: + name: HSI48CAL +CFGR: + _modify: + MCO1SEL: + name: MCO1 + MCO2SEL: + name: MCO2 +CIER: + _modify: + RC48RDYIE: + name: HSI48RDYIE +CIFR: + _modify: + RC48RDYF: + name: HSI48RDYF +CICR: + _modify: + RC48RDYC: + name: HSI48RDYC +BDCR: + _modify: + VSWRST: + name: BDRST + RTCSRC: + name: RTCSEL +GCR: + _add: + WW2RSC: + description: WWDG2 reset scope control + bitOffset: 1 + bitWidth: 1 + BOOT_C1: + description: Force allow CPU1 to boot + bitOffset: 2 + bitWidth: 1 + BOOT_C2: + description: Force allow CPU2 to boot + bitOffset: 3 + bitWidth: 1 +APB1LRSTR: + _modify: + USART7RST: + name: UART7RST + description: UART7 block reset + USART8RST: + name: UART8RST + description: UART8 block reset + HDMICECRST: + name: CECRST +APB1LENR,C1_APB1LENR: + _add: + WWDG2EN: + description: WWDG2 peripheral clock enable + bitOffset: 11 + bitWidth: 1 + _modify: + USART7EN: + name: UART7EN + description: UART7 Peripheral Clocks Enable + USART8EN: + name: UART8EN + description: UART8 Peripheral Clocks Enable + HDMICECEN: + name: CECEN +APB1LLPENR,C1_APB1LLPENR: + _add: + WWDG2LPEN: + description: WWDG2 peripheral Clocks Enable During CSleep Mode + bitOffset: 11 + bitWidth: 1 + _modify: + USART7LPEN: + name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + USART8LPEN: + name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode + HDMICECLPEN: + name: CECLPEN +APB3ENR,C1_APB3ENR: + _add: + DSIEN: + description: DSI Peripheral clocks enable + bitOffset: 4 + bitWidth: 1 +APB3LPENR,C1_APB3LPENR: + _add: + DSILPEN: + description: DSI Peripheral Clock Enable During CSleep Mode + bitOffset: 4 + bitWidth: 1 +APB3RSTR: + _add: + DSIRST: + description: DSI block reset + bitOffset: 4 + bitWidth: 1 +AHB1RSTR: + _add: + ARTRST: + description: ART block reset + bitOffset: 14 + bitWidth: 1 +AHB1ENR,C1_AHB1ENR: + _add: + ARTEN: + description: ART Clock Enable + bitOffset: 14 + bitWidth: 1 +AHB2ENR,C1_AHB2ENR: + _modify: + CAMITFEN: + name: DCMIEN + description: DCMI peripheral clock +AHB1LPENR: + _add: + ARTLPEN: + description: ART Clock Enable During CSleep Mode + bitOffset: 14 + bitWidth: 1 +C1_AHB1LPENR: + _add: + ARTLPEN: + description: ART Clock Enable During CSleep Mode + bitOffset: 14 + bitWidth: 1 +AHB2LPENR,C1_AHB2LPENR: + _modify: + CAMITFLPEN: + name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode +AHB3ENR: + _add: + DTCM1EN: + description: D1 DTCM1 block enable + bitOffset: 28 + bitWidth: 1 + DTCM2EN: + description: D1 DTCM2 block enable + bitOffset: 29 + bitWidth: 1 + ITCM1EN: + description: D1 ITCM block enable + bitOffset: 30 + bitWidth: 1 + AXISRAMEN: + description: AXISRAM block enable + bitOffset: 31 + bitWidth: 1 +C1_AHB3LPENR: + _modify: + FLITFLPEN: + name: FLASHPREN + description: Flash interface clock enable during csleep mode diff --git a/devices/patches/rcc/h7_common_highmemory.yaml b/devices/patches/rcc/h7_common_highmemory.yaml new file mode 100644 index 000000000..b6f23cc51 --- /dev/null +++ b/devices/patches/rcc/h7_common_highmemory.yaml @@ -0,0 +1,44 @@ +_add: + # This doesn't exist in RM0455 Rev 3, but the WW1RSC field is + # referenced in Section 8.7.42. So we assume it does exist in the same + # place as the other parts in the family. + GCR: + description: Global Control Register + addressOffset: 0x00A0 + resetValue: 0x00000000 + access: read-write + fields: + WW1RSC: + description: WWDG1 reset scope control + bitOffset: 0 + bitWidth: 1 + +CFGR: + _modify: + MCO1SEL: + name: MCO1 + MCO2SEL: + name: MCO2 +AHB3ENR: + _add: + DTCM1EN: + description: D1 DTCM1 block enable + bitOffset: 28 + bitWidth: 1 + DTCM2EN: + description: D1 DTCM2 block enable + bitOffset: 29 + bitWidth: 1 + ITCM1EN: + description: D1 ITCM block enable + bitOffset: 30 + bitWidth: 1 + AXISRAMEN: + description: AXISRAM block enable + bitOffset: 31 + bitWidth: 1 +AHB3LPENR: + _modify: + FLITFLPEN: + name: FLASHPREN + description: Flash interface clock enable during csleep mode diff --git a/devices/patches/rcc/h7_common_singlecore.yaml b/devices/patches/rcc/h7_common_singlecore.yaml new file mode 100644 index 000000000..ea13b93da --- /dev/null +++ b/devices/patches/rcc/h7_common_singlecore.yaml @@ -0,0 +1,93 @@ +_include: h7_usb1otghs.yaml +_modify: + CIFR: + access: read-only +CR: + _modify: + RC48ON: + name: HSI48ON + RC48RDY: + name: HSI48RDY +CRRCR: + _modify: + RC48CAL: + name: HSI48CAL +CFGR: + _modify: + MCO1SEL: + name: MCO1 + MCO2SEL: + name: MCO2 +CIER: + _modify: + RC48RDYIE: + name: HSI48RDYIE +CIFR: + _modify: + RC48RDYF: + name: HSI48RDYF +CICR: + _modify: + RC48RDYC: + name: HSI48RDYC +BDCR: + _modify: + VSWRST: + name: BDRST + RTCSRC: + name: RTCSEL +APB1LRSTR: + _modify: + USART7RST: + name: UART7RST + description: UART7 block reset + USART8RST: + name: UART8RST + description: UART8 block reset +APB1LENR,C1_APB1LENR: + _modify: + USART7EN: + name: UART7EN + description: UART7 Peripheral Clocks Enable + USART8EN: + name: UART8EN + description: UART8 Peripheral Clocks Enable +APB1LLPENR: + _modify: + USART7LPEN: + name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + USART8LPEN: + name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode +C1_APB1LLPENR: + _modify: + USART7LPEN: + name: UART7LPEN + description: UART7 Peripheral Clocks Enable During CSleep Mode + USART8LPEN: + name: UART8LPEN + description: UART8 Peripheral Clocks Enable During CSleep Mode +C1_APB1LENR: + _modify: + HDMICECEN: + name: CECEN +AHB2ENR,C1_AHB2ENR: + _modify: + CAMITFEN: + name: DCMIEN + description: DCMI peripheral clock +APB1LLPENR,C1_APB1LLPENR: + _modify: + HDMICECLPEN: + name: CECLPEN +AHB2LPENR,C1_AHB2LPENR: + _modify: + CAMITFLPEN: + name: DCMILPEN + description: DCMI peripheral clock enable during csleep mode +C1_AHB3LPENR: + _modify: + FLITFLPEN: + name: FLASHPREN + description: Flash interface clock enable during csleep mode diff --git a/devices/patches/rcc/h7_hsicfgr_csicfgr_735.yaml b/devices/patches/rcc/h7_hsicfgr_csicfgr_735.yaml new file mode 100644 index 000000000..8adc35540 --- /dev/null +++ b/devices/patches/rcc/h7_hsicfgr_csicfgr_735.yaml @@ -0,0 +1,4 @@ +CSICFGR: + _modify: + CSICAL: + bitWidth: 10 diff --git a/devices/patches/rcc/h7_hsicfgr_csicfgr_rev_v.yaml b/devices/patches/rcc/h7_hsicfgr_csicfgr_rev_v.yaml new file mode 100644 index 000000000..077e0b696 --- /dev/null +++ b/devices/patches/rcc/h7_hsicfgr_csicfgr_rev_v.yaml @@ -0,0 +1,29 @@ +_delete: + - ICSCR +_add: + HSICFGR: + description: RCC HSI configuration register + addressOffset: 0x0004 + access: read-write + fields: + HSITRIM: + description: HSI clock trimming + bitOffset: 24 + bitWidth: 7 + HSICAL: + description: HSI clock calibration + bitOffset: 0 + bitWidth: 12 + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 diff --git a/devices/patches/rcc/h7_src_sel.yaml b/devices/patches/rcc/h7_src_sel.yaml new file mode 100644 index 000000000..93c70c800 --- /dev/null +++ b/devices/patches/rcc/h7_src_sel.yaml @@ -0,0 +1,21 @@ +# Rename *SRC to *SEL in H7 domain kernel clock configuration registers (DxCCIPR) + +# Applies only to RM0433 and RM0399 + +_include: + - h7_src_sel_common.yaml + +D1CCIPR: + _modify: + QSPISRC: + name: QSPISEL +D2CCIP1R: + _modify: + SWPSRC: + name: SWPSEL +D2CCIP2R: + _modify: + I2C123SRC: + name: I2C123SEL + USART16SRC: + name: USART16SEL diff --git a/devices/patches/rcc/h7_src_sel_common.yaml b/devices/patches/rcc/h7_src_sel_common.yaml new file mode 100644 index 000000000..77988e1a1 --- /dev/null +++ b/devices/patches/rcc/h7_src_sel_common.yaml @@ -0,0 +1,58 @@ +# Rename *SRC to *SEL in H7 domain kernel clock configuration registers (DxCCIPR) + +# Applies only to RM0433, RM0399 and RM0468 parts + +D1CCIPR: + _modify: + CKPERSRC: + name: CKPERSEL + SDMMCSRC: + name: SDMMCSEL + FMCSRC: + name: FMCSEL +D2CCIP1R: + _modify: + FDCANSRC: + name: FDCANSEL + DFSDM1SRC: + name: DFSDM1SEL + SPDIFSRC: + name: SPDIFSEL + SPI45SRC: + name: SPI45SEL + SPI123SRC: + name: SPI123SEL + SAI23SRC: + name: SAI23SEL + SAI1SRC: + name: SAI1SEL +D2CCIP2R: + _modify: + LPTIM1SRC: + name: LPTIM1SEL + CECSRC: + name: CECSEL + USBSRC: + name: USBSEL + RNGSRC: + name: RNGSEL + USART234578SRC: + name: USART234578SEL +D3CCIPR: + _modify: + SPI6SRC: + name: SPI6SEL + SAI4BSRC: + name: SAI4BSEL + SAI4ASRC: + name: SAI4ASEL + ADCSRC: + name: ADCSEL + LPTIM345SRC: + name: LPTIM345SEL + LPTIM2SRC: + name: LPTIM2SEL + I2C4SRC: + name: I2C4SEL + LPUART1SRC: + name: LPUART1SEL diff --git a/devices/patches/rcc/h7_usb1otghs.yaml b/devices/patches/rcc/h7_usb1otghs.yaml new file mode 100644 index 000000000..d2d148e91 --- /dev/null +++ b/devices/patches/rcc/h7_usb1otghs.yaml @@ -0,0 +1,10 @@ +AHB1LPENR,C1_AHB1LPENR: + _modify: + "?~USB1OTGHSLPEN": + name: USB1OTGLPEN + "?~USB1ULPILPEN,USB1OTGHSULPILPEN": + name: USB1OTGULPILPEN +AHB1ENR,C1_AHB1ENR: + _modify: + USB1ULPIEN,USB1OTGHSULPIEN: + name: USB1OTGULPIEN diff --git a/devices/patches/rcc/h7_usb2otghs.yaml b/devices/patches/rcc/h7_usb2otghs.yaml new file mode 100644 index 000000000..f500613cf --- /dev/null +++ b/devices/patches/rcc/h7_usb2otghs.yaml @@ -0,0 +1,12 @@ +AHB1LPENR,C1_AHB1LPENR: + _modify: + "?~USB2OTGHSLPEN": + name: USB2OTGLPEN + "?~USB2ULPILPEN,USB2OTGHSULPILPEN": + name: USB2OTGULPILPEN +AHB1ENR,C1_AHB1ENR: + _delete: + USB2OTGHSULPIEN + _modify: + USB2ULPIEN: + name: USB2OTGULPIEN diff --git a/devices/patches/rcc/l4+.yaml b/devices/patches/rcc/l4+.yaml new file mode 100644 index 000000000..5fd610f00 --- /dev/null +++ b/devices/patches/rcc/l4+.yaml @@ -0,0 +1,132 @@ +_add: + DLYCFGR: + description: delay configuration register + addressOffset: 0xA4 + resetValue: 0x0 + fields: + OCTOSPI2_DLY: + description: Delay sampling configuration on OCTOSPI2 to be used for internal sampling clock (called feedback clock) or for DQS data strobe + bitOffset: 4 + bitWidth: 4 + OCTOSPI1_DLY: + description: Delay sampling configuration on OCTOSPI1 to be used for internal sampling clock (called feedback clock) or for DQS data strobe + bitOffset: 0 + bitWidth: 4 + +_modify: + APB1ENR1: + resetValue: 0x00000400 + AHB1SMENR: + resetValue: 0x00071307 + AHB2SMENR: + resetValue: 0x005777FF + AHB3SMENR: + resetValue: 0x00000301 + APB1SMENR1: + resetValue: 0xF3FECC3F + APB1SMENR2: + resetValue: 0x00000023 + APB2SMENR: + resetValue: 0x0D677801 + +AHB1RSTR: + _add: + GFXMMURST: + description: GFXMMU reset + bitOffset: 18 + bitWidth: 1 + +AHB2RSTR: + _add: + SDMMC2RST: + description: SDMMC2 reset + bitOffset: 23 + bitWidth: 1 + PKARST: + description: PKA reset + bitOffset: 15 + bitWidth: 1 + +AHB3RSTR: + _add: + OSPI1RST: + description: OctoSPI1 memory interface reset + bitOffset: 8 + bitWidth: 1 + +AHB1ENR: + _add: + GFXMMUEN: + description: Graphic MMU clock enable + bitOffset: 18 + bitWidth: 1 + +AHB2ENR: + _add: + SDMMC2EN: + description: SDMMC2 clock enable + bitOffset: 23 + bitWidth: 1 + PKAEN: + description: PKA clock enable + bitOffset: 15 + bitWidth: 1 + +AHB3ENR: + _add: + OSPI1EN: + description: OctoSPI1 memory interface clock enable + bitOffset: 8 + bitWidth: 1 + +APB1ENR1: + _modify: + SP3EN: + name: SPI3EN + +AHB1SMENR: + _add: + GFXMMUSMEN: + description: GFXMMU clock enable during Sleep and Stop modes + bitOffset: 18 + bitWidth: 1 + +AHB2SMENR: + _add: + SDMMC2SMEN: + description: SDMMC2 clocks enable during Sleep and Stop modes + bitOffset: 23 + bitWidth: 1 + PKASMEN: + description: PKA clocks enable during Sleep and Stop modes + bitOffset: 15 + bitWidth: 1 + + _modify: + ADCFSSMEN: + name: ADCSMEN + +AHB3SMENR: + _add: + OSPI1SMEN: + description: OctoSPI1 memory interface clocks enable during Sleep and Stop modes + bitOffset: 8 + bitWidth: 1 + +BDCR: + _add: + LSESYSDIS: + description: Disable the Clock LSE propagation to the system + bitOffset: 7 + bitWidth: 1 + +CSR: + _add: + LSIPREDIV: + description: Internal low-speed oscillator predivided by 128 + bitOffset: 4 + bitWidth: 1 + + _modify: + LPWRSTF: + name: LPWRRSTF diff --git a/devices/patches/rcc/l4_crrcr.yaml b/devices/patches/rcc/l4_crrcr.yaml new file mode 100644 index 000000000..e2a343ecf --- /dev/null +++ b/devices/patches/rcc/l4_crrcr.yaml @@ -0,0 +1,20 @@ +_add: + CRRCR: + description: Clock recovery RC register + addressOffset: 0x98 + fields: + HSI48CAL: + description: These bits are initialized at startup with the factory-programmed HSI48 calibration trim value. + access: read-only + bitOffset: 7 + bitWidth: 9 + HSI48RDY: + description: Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is enabled by software by setting HSI48ON. + access: read-only + bitOffset: 1 + bitWidth: 1 + HSI48ON: + description: Set and cleared by software. Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes. + access: read-write + bitOffset: 0 + bitWidth: 1 diff --git a/devices/patches/rcc/pllsai.yaml b/devices/patches/rcc/pllsai.yaml new file mode 100644 index 000000000..2537de2de --- /dev/null +++ b/devices/patches/rcc/pllsai.yaml @@ -0,0 +1,13 @@ +# Add missing PLLSAIRDY, PLLSAION bits to RCC_CR +CR: + _add: + PLLSAIRDY: + description: PLLSAI clock ready flag + bitOffset: 29 + bitWidth: 1 + access: read-only + PLLSAION: + description: PLLSAI enable + bitOffset: 28 + bitWidth: 1 + access: read-write diff --git a/devices/patches/rcc/rcc_merge_rtcsel.yaml b/devices/patches/rcc/rcc_merge_rtcsel.yaml new file mode 100644 index 000000000..108d9529b --- /dev/null +++ b/devices/patches/rcc/rcc_merge_rtcsel.yaml @@ -0,0 +1,4 @@ +# Applicable at least to STM32F4 and STM32F7. + +BDCR: + _merge: ["RTCSEL[01]"] diff --git a/devices/patches/rcc/rcc_merge_sw_sws.yaml b/devices/patches/rcc/rcc_merge_sw_sws.yaml new file mode 100644 index 000000000..f84a1b6f0 --- /dev/null +++ b/devices/patches/rcc/rcc_merge_sw_sws.yaml @@ -0,0 +1,4 @@ +# Applicable at least to some STM32F4 and STM32F7. + +CFGR: + _merge: ["SW[01]", "SWS[01]"] diff --git a/devices/patches/rcc/rename_CIR_HSI14RDYIE_field.yaml b/devices/patches/rcc/rename_CIR_HSI14RDYIE_field.yaml new file mode 100644 index 000000000..625ff1b04 --- /dev/null +++ b/devices/patches/rcc/rename_CIR_HSI14RDYIE_field.yaml @@ -0,0 +1,4 @@ +CIR: + _modify: + HSI14RDYE: + name: HSI14RDYIE diff --git a/devices/patches/rcc/rename_plli2scfgr.yaml b/devices/patches/rcc/rename_plli2scfgr.yaml new file mode 100644 index 000000000..b913a705c --- /dev/null +++ b/devices/patches/rcc/rename_plli2scfgr.yaml @@ -0,0 +1,6 @@ +PLLI2SCFGR: + _modify: + PLLI2SRx: + name: PLLI2SR + PLLI2SNx: + name: PLLI2SN diff --git a/devices/patches/rcc/sai.yaml b/devices/patches/rcc/sai.yaml new file mode 100644 index 000000000..b1b4054a5 --- /dev/null +++ b/devices/patches/rcc/sai.yaml @@ -0,0 +1,17 @@ +# Add missing reset/enable bits for the SAI clock and PLL +CR: + _modify: + PLLSAIRDY: + access: read-only +APB2RSTR: + _add: + SAI1RST: + description: SAI1 reset + bitOffset: 22 + bitWidth: 1 +APB2LPENR: + _add: + SAI1LPEN: + description: SAI1 clock enable during Sleep mode + bitOffset: 22 + bitWidth: 1 diff --git a/devices/patches/rcc/spi4.yaml b/devices/patches/rcc/spi4.yaml new file mode 100644 index 000000000..6da46e862 --- /dev/null +++ b/devices/patches/rcc/spi4.yaml @@ -0,0 +1,19 @@ +# Add missing reset/enable bits for SPI 4 +APB2RSTR: + _add: + SPI4RST: + description: SPI4 reset + bitOffset: 13 + bitWidth: 1 +APB2ENR: + _add: + SPI4EN: + description: SPI4 clock enable + bitOffset: 13 + bitWidth: 1 +APB2LPENR: + _add: + SPI4LPEN: + description: SPI4 clock enable during Sleep mode + bitOffset: 13 + bitWidth: 1 diff --git a/devices/patches/rcc/spi5.yaml b/devices/patches/rcc/spi5.yaml new file mode 100644 index 000000000..389e2a7c5 --- /dev/null +++ b/devices/patches/rcc/spi5.yaml @@ -0,0 +1,19 @@ +# Add missing reset/enable bits for SPI 5 +APB2RSTR: + _add: + SPI5RST: + description: SPI5 reset + bitOffset: 20 + bitWidth: 1 +APB2ENR: + _add: + SPI5EN: + description: SPI5 clock enable + bitOffset: 20 + bitWidth: 1 +APB2LPENR: + _add: + SPI5LPEN: + description: SPI5 clock enable during Sleep mode + bitOffset: 20 + bitWidth: 1 diff --git a/devices/patches/rng/h503.yaml b/devices/patches/rng/h503.yaml new file mode 100644 index 000000000..1ff439e21 --- /dev/null +++ b/devices/patches/rng/h503.yaml @@ -0,0 +1,30 @@ +_add: + NSCR: + description: RNG noise source control register + addressOffset: 0x0C + resetValue: 0x0003FFFF + fields: + EN_OSC1: + description: Each bit drives one oscillator enable signal input of instance number 1, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + bitOffset: 0 + bitWidth: 3 + EN_OSC2: + description: Each bit drives one oscillator enable signal input of instance number 2, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + bitOffset: 3 + bitWidth: 3 + EN_OSC3: + description: Each bit drives one oscillator enable signal input of instance number 3, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + bitOffset: 6 + bitWidth: 3 + EN_OSC4: + description: Each bit drives one oscillator enable signal input of instance number 4, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + bitOffset: 9 + bitWidth: 3 + EN_OSC5: + description: Each bit drives one oscillator enable signal input of instance number 5, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + bitOffset: 12 + bitWidth: 3 + EN_OSC6: + description: Each bit drives one oscillator enable signal input of instance number 6, gated with the RNGEN bit in RNG_CR (set bit to enable the oscillator). + bitOffset: 15 + bitWidth: 3 diff --git a/devices/patches/rng/h735.yaml b/devices/patches/rng/h735.yaml new file mode 100644 index 000000000..1c18bbb7d --- /dev/null +++ b/devices/patches/rng/h735.yaml @@ -0,0 +1,40 @@ +_add: + HTCR: + description: health test control register + addressOffset: 0x10 + resetValue: 0x00005A4E + fields: + HTCFG: + description: health test configuration + bitOffset: 0 + bitWidth: 32 +CR: + _add: + CONFIGLOCK: + description: RNG Config lock + bitOffset: 31 + bitWidth: 1 + CONDRST: + description: Conditioning soft reset + bitOffset: 30 + bitWidth: 1 + RNG_CONFIG1: + description: RNG configuration 1 + bitOffset: 20 + bitWidth: 6 + CLKDIV: + description: Clock divider factor + bitOffset: 16 + bitWidth: 4 + RNG_CONFIG2: + description: RNG configuration 2 + bitOffset: 13 + bitWidth: 3 + NISTC: + description: Non NIST compliant + bitOffset: 12 + bitWidth: 1 + RNG_CONFIG3: + description: RNG configuration 3 + bitOffset: 8 + bitWidth: 4 diff --git a/devices/patches/rng/l4+.yaml b/devices/patches/rng/l4+.yaml new file mode 100644 index 000000000..8a07e8548 --- /dev/null +++ b/devices/patches/rng/l4+.yaml @@ -0,0 +1,9 @@ +_include: + - ./h735.yaml + +CR: + _add: + CED: + description: Clock error detection + bitOffset: 5 + bitWidth: 1 diff --git a/devices/patches/rtc/alarm.yaml b/devices/patches/rtc/alarm.yaml new file mode 100644 index 000000000..06b02bcab --- /dev/null +++ b/devices/patches/rtc/alarm.yaml @@ -0,0 +1,38 @@ +# remove reference to "Alarm A" and "Alarm B" from descriptions +_modify: + ALRM?R: + description: Alarm register + ALRM?SSR: + description: Alarm sub-second register + +_derive: + TSTR: TR + TSDR: DR + TSSSR: SSR + +ALRM?R: + _modify: + SU: + description: Second units in BCD format + ST: + description: Second tens in BCD format + MSK1: + description: Alarm seconds mask + MNU: + description: Minute units in BCD format + MNT: + description: Minute tens in BCD format + MSK2: + description: Alarm minutes mask + HU: + description: Hour units in BCD format + HT: + description: Hour tens in BCD format + MSK3: + description: Alarm hours mask + DU: + description: Date units or day in BCD format + DT: + description: Date tens in BCD format + MSK4: + description: Alarm date mask diff --git a/devices/patches/rtc/f4_cr.yaml b/devices/patches/rtc/f4_cr.yaml new file mode 100644 index 000000000..ebf030015 --- /dev/null +++ b/devices/patches/rtc/f4_cr.yaml @@ -0,0 +1,12 @@ +CR: + _add: + BYPSHAD: + description: Bypass the shadow registers + bitOffset: 5 + bitWidth: 1 + access: read-write + COSEL: + description: Calibration output selection + bitOffset: 19 + bitWidth: 1 + access: read-write diff --git a/devices/patches/rtc/l0.yaml b/devices/patches/rtc/l0.yaml new file mode 100644 index 000000000..dd9b32793 --- /dev/null +++ b/devices/patches/rtc/l0.yaml @@ -0,0 +1,37 @@ +# Fix RTC bits for L0 + +ISR: + _add: + RECALPF: + description: Recalibration pending flag + bitWidth: 1 + bitOffset: 16 + TAMP3F: + description: RTC_TAMP3 detection flag + bitWidth: 1 + bitOffset: 15 +TAMPCR: + _modify: + TAMP2_TRG: + name: TAMP2TRG + _add: + TAMP3MF: + description: Tamper 3 mask flag + bitWidth: 1 + bitOffset: 24 + TAMP3NOERASE: + description: Tamper 3 no erase + bitWidth: 1 + bitOffset: 23 + TAMP3IE: + description: Tamper 3 interrupt enable + bitWidth: 1 + bitOffset: 22 + TAMP3TRG: + description: Active level for RTC_TAMP3 input + bitWidth: 1 + bitOffset: 6 + TAMP3E: + description: RTC_TAMP3 detection enable + bitWidth: 1 + bitOffset: 5 diff --git a/devices/patches/rtc/rtc_cr.yaml b/devices/patches/rtc/rtc_cr.yaml new file mode 100644 index 000000000..37563ec18 --- /dev/null +++ b/devices/patches/rtc/rtc_cr.yaml @@ -0,0 +1,5 @@ +CR: + _modify: + WCKSEL: + name: WUCKSEL + description: Wakeup clock selection diff --git a/devices/patches/rtc/rtc_register_descriptions.yaml b/devices/patches/rtc/rtc_register_descriptions.yaml new file mode 100644 index 000000000..ad167c902 --- /dev/null +++ b/devices/patches/rtc/rtc_register_descriptions.yaml @@ -0,0 +1,41 @@ +_modify: + TR: + description: Time register + DR: + description: Date register + SSR: + description: Sub second register + ICSR: + description: Initialization control and status register + PRER: + description: Pre-scaler register + WUTR: + description: Wakeup timer register + CR: + description: Control register + WPR: + description: Write protection register + CALR: + description: Calibration register + SHIFTR: + description: Shift control register + TSTR: + description: Timestamp time register + TSDR: + description: Timestamp date register + TSSSR: + description: Timestamp sub second register + ALRMAR: + description: Alarm A register + ALRMASSR: + description: Alarm A sub second register + ALRMBR: + description: Alarm B register + ALRMBSSR: + description: Alarm B sub second register + SR: + description: Status register (interrupts) + MISR: + description: Masked interrupt status register + SCR: + description: Status clear register (interrupts) diff --git a/devices/patches/rtc/tamp_wl.yaml b/devices/patches/rtc/tamp_wl.yaml new file mode 100644 index 000000000..6ff4e97d0 --- /dev/null +++ b/devices/patches/rtc/tamp_wl.yaml @@ -0,0 +1,21 @@ +_modify: + BKP10R: + addressOffset: 0x128 + BKP11R: + addressOffset: 0x12C + BKP12R: + addressOffset: 0x130 + BKP13R: + addressOffset: 0x134 + BKP14R: + addressOffset: 0x138 + BKP15R: + addressOffset: 0x13C + BKP16R: + addressOffset: 0x140 + BKP17R: + addressOffset: 0x144 + BKP18R: + addressOffset: 0x148 + BKP19R: + addressOffset: 0x14C diff --git a/devices/patches/rtc/wl.yaml b/devices/patches/rtc/wl.yaml new file mode 100644 index 000000000..58128853a --- /dev/null +++ b/devices/patches/rtc/wl.yaml @@ -0,0 +1,34 @@ +_modify: + ALRM?R: + description: Alarm register + ALRM?SSR: + description: Alarm sub-second register + ALRBBINR: + description: Alarm binary mode register + +ALRM?R: + _modify: + SU: + description: Second units in BCD format + ST: + description: Second tens in BCD format + MSK1: + description: Alarm seconds mask + MNU: + description: Minute units in BCD format + MNT: + description: Minute tens in BCD format + MSK2: + description: Alarm minutes mask + HU: + description: Hour units in BCD format + HT: + description: Hour tens in BCD format + MSK3: + description: Alarm hours mask + DU: + description: Date units or day in BCD format + DT: + description: Date tens in BCD format + MSK4: + description: Alarm date mask diff --git a/devices/patches/sai/fsdef-rw.yaml b/devices/patches/sai/fsdef-rw.yaml new file mode 100644 index 000000000..aca69550a --- /dev/null +++ b/devices/patches/sai/fsdef-rw.yaml @@ -0,0 +1,4 @@ +"?FRCR": + _modify: + FSDEF: + access: read-write diff --git a/devices/patches/sai/h7.yaml b/devices/patches/sai/h7.yaml new file mode 100644 index 000000000..d899dae17 --- /dev/null +++ b/devices/patches/sai/h7.yaml @@ -0,0 +1,14 @@ +_include: fsdef-rw.yaml +"?CR1": + _modify: + SAI?EN: + name: SAIEN + MCKDIV: + bitWidth: 6 + _delete: + - NOMCK + _add: + NODIV: + description: No fixed divider between MCLK and FS + bitOffset: 19 + bitWidth: 1 diff --git a/devices/patches/sai/h7_mcken.yaml b/devices/patches/sai/h7_mcken.yaml new file mode 100644 index 000000000..d2ae12b47 --- /dev/null +++ b/devices/patches/sai/h7_mcken.yaml @@ -0,0 +1,8 @@ +# Applies to H7 RM0399, RM0455, RM0468 + +"?CR1": + _add: + MCKEN: + description: Master clock generation enable + bitOffset: 27 + bitWidth: 1 diff --git a/devices/patches/sai/sai_l4+.yaml b/devices/patches/sai/sai_l4+.yaml new file mode 100644 index 000000000..a5f7663ae --- /dev/null +++ b/devices/patches/sai/sai_l4+.yaml @@ -0,0 +1,57 @@ +_add: + GCR: + description: Global configuration register + addressOffset: 0x0 + resetValue: 0x0 + fields: + SYNCOUT: + description: Synchronization outputs + bitOffset: 4 + bitWidth: 2 + SYNCIN: + description: Synchronization inputs + bitOffset: 0 + bitWidth: 2 + +GCR: + SYNCOUT: + Disabled: + [ + 0, + "No synchronization output signals. SYNCOUT[1:0] should be configured as “No synchronization output signals” when audio block is configured as SPDIF", + ] + BlockA: [1, Block A used for further synchronization for others SAI] + BlockB: [2, Block B used for further synchronization for others SAI] + +?CR1: + _add: + OSR: + description: Oversampling ratio for master clock + bitOffset: 26 + bitWidth: 1 + + _modify: + NODIV: + name: NOMCK + MCJDIV: + name: MCKDIV + bitWidth: 6 + + OSR: + Multiplier256: [0, "Master clock frequency = FFS x 256"] + Multiplier512: [1, "Master clock frequency = FFS x 512"] + MCKDIV: [0, 0x3F] + +?CR2: + _modify: + MUTECN: + name: MUTECNT + + MUTECNT: [0, 0x3F] + TRIS: + DrivenWhileInactive: [0, SD output line is still driven by the SAI when a slot is inactive] + HighZ: + [ + 1, + SD output line is released (HI-Z) at the end of the last data bit of the last active slot if the next one is inactive, + ] diff --git a/devices/patches/sai/sai_v1.yaml b/devices/patches/sai/sai_v1.yaml new file mode 100644 index 000000000..5f4d2d95a --- /dev/null +++ b/devices/patches/sai/sai_v1.yaml @@ -0,0 +1,59 @@ +_include: v1_common.yaml +_modify: + "?SR": + access: read-only + "?CLRFR": + access: write-only + +"?CR1": + _modify: + OutDri: + name: OUTDRIV + "MCKDIV,MCJDIV": + name: MCKDIV +"?CR2": + _modify: + FTH: + access: read-write + TRIS: + access: read-write + MUTE: + access: read-write + MUTEVAL: + access: read-write + CPL: + access: read-write + COMP: + access: read-write +"?FRCR": + _modify: + FRL: + access: read-write + FSALL: + access: read-write + FSDEF: + access: read-write + FSPOL: + access: read-write + FSOFF: + access: read-write +"?IM": + _modify: + WCKCFG: + name: WCKCFGIE + MUTEDET: + name: MUTEDETIE + "LFSDET,LFSDETIE": + name: LFSDETIE +"?CLRFR": + _modify: + LFSDET: + name: CLFSDET + CNRDY: + name: CCNRDY + WCKCFG: + name: CWCKCFG + MUTEDET: + name: CMUTEDET + OVRUDR: + name: COVRUDR diff --git a/devices/patches/sai/v1_common.yaml b/devices/patches/sai/v1_common.yaml new file mode 100644 index 000000000..5bc7b4b10 --- /dev/null +++ b/devices/patches/sai/v1_common.yaml @@ -0,0 +1,15 @@ +_modify: + "?SR": + resetValue: 8 +"?CR1": + _modify: + SAI?EN: + name: SAIEN +"*CR2": + _modify: + FFLUS: + name: FFLUSH + access: write-only + MUTECN,MUTECNT: + name: MUTECNT + access: read-write diff --git a/devices/patches/sbs/fmplus.yaml b/devices/patches/sbs/fmplus.yaml new file mode 100644 index 000000000..ea72a1973 --- /dev/null +++ b/devices/patches/sbs/fmplus.yaml @@ -0,0 +1,9 @@ +PMCR: + # Rename these fields on H503 to match other H5 processors + _modify: + PB6_FMPLUS: + name: PB6_FMP + PB7_FMPLUS: + name: PB7_FMP + PB8_FMPLUS: + name: PB8_FMP diff --git a/devices/patches/sbs/h7+.yaml b/devices/patches/sbs/h7+.yaml new file mode 100644 index 000000000..8cbc7882b --- /dev/null +++ b/devices/patches/sbs/h7+.yaml @@ -0,0 +1,25 @@ +CCCSR: + _modify: + COMP_EN: + name: EN + COMP_CODESEL: + name: CS + COMP_RDY: + name: READY + IOHSLV: + name: HSLV + +# align names of EXTI configuration registers with other H7 devices +_modify: + EXTICR3: + name: EXTICR4 + access: read-write + EXTICR2: + name: EXTICR3 + access: read-write + EXTICR1: + name: EXTICR2 + access: read-write + EXTICR0: + name: EXTICR1 + access: read-write diff --git a/devices/patches/sbs/sbs.yaml b/devices/patches/sbs/sbs.yaml new file mode 100644 index 000000000..3ae86983b --- /dev/null +++ b/devices/patches/sbs/sbs.yaml @@ -0,0 +1,5 @@ +FPUIMR: + _split: + FPU_IE: + name: FPU_IE%s + description: FPU interrupt enable diff --git a/devices/patches/sdio_sdmmc/cardstatus.yaml b/devices/patches/sdio_sdmmc/cardstatus.yaml new file mode 100644 index 000000000..0b4851371 --- /dev/null +++ b/devices/patches/sdio_sdmmc/cardstatus.yaml @@ -0,0 +1,5 @@ +RESP?,RESP?R: + _modify: + CARDSTATUS?: + name: CARDSTATUS + description: Status of a card, which is part of the received response diff --git a/devices/patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml b/devices/patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml new file mode 100644 index 000000000..e28352507 --- /dev/null +++ b/devices/patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml @@ -0,0 +1,17 @@ +CMD: + _delete: + - CE_ATACMD + - nIEN + - ENCMDcompl +STA: + _delete: + - CEATAEND + - STBITERR +ICR: + _delete: + - CEATAENDC + - STBITERRC +MASK: + _delete: + - CEATAENDIE + - STBITERRIE diff --git a/devices/patches/spi/dr8.yaml b/devices/patches/spi/dr8.yaml new file mode 100644 index 000000000..34ffa3d60 --- /dev/null +++ b/devices/patches/spi/dr8.yaml @@ -0,0 +1,15 @@ +_add: + DR8: + access: read-write + addressOffset: 0xC + alternateRegister: DR + description: Direct 8-bit access to data register + size: 0x8 + fields: + DR: + bitOffset: 0 + bitWidth: 8 + description: Data register + +DR8: + DR: [0, 0xff] diff --git a/devices/patches/spi/g0_rename_registers.yaml b/devices/patches/spi/g0_rename_registers.yaml new file mode 100644 index 000000000..505351209 --- /dev/null +++ b/devices/patches/spi/g0_rename_registers.yaml @@ -0,0 +1,5 @@ +_include: rename_dff_tifrfe.yaml +I2SCFGR: + _modify: + SE2: + name: I2SE diff --git a/devices/patches/spi/h7.yaml b/devices/patches/spi/h7.yaml new file mode 100644 index 000000000..1b8e3d71c --- /dev/null +++ b/devices/patches/spi/h7.yaml @@ -0,0 +1,27 @@ +_modify: + "CGFR,I2SCFGR": + name: I2SCFGR + TXCRC: + access: read-only + RXCRC: + access: read-only + +CR1: + _modify: + CSTART: + access: read-write + TCRCI: + name: TCRCINI + RCRCI: + name: RCRCINI +IER: + _modify: + DPXPIE: + name: DXPIE + access: read-write + TXPIE: + access: read-write +CFG1: + _modify: + FTHVL: + name: FTHLV diff --git a/devices/patches/spi/h7_2.yaml b/devices/patches/spi/h7_2.yaml new file mode 100644 index 000000000..4266b2d8a --- /dev/null +++ b/devices/patches/spi/h7_2.yaml @@ -0,0 +1,10 @@ +_include: h7.yaml + +CR1: + _modify: + IOLOCK: + access: read-write +CR2: + _modify: + TSER: + access: read-write diff --git a/devices/patches/spi/rename_dff_tifrfe.yaml b/devices/patches/spi/rename_dff_tifrfe.yaml new file mode 100644 index 000000000..79409054b --- /dev/null +++ b/devices/patches/spi/rename_dff_tifrfe.yaml @@ -0,0 +1,13 @@ +# Rename SPI fields +# CR1.CRCL field is documented, but in SVD as DFF. +# SR.FRE field is documented, but in SVD as TIFRFE. +CR1: + _modify: + DFF: + name: CRCL + description: CRC length +SR: + _modify: + TIFRFE: + name: FRE + description: Frame format error diff --git a/devices/patches/spi/rxtxdr.yaml b/devices/patches/spi/rxtxdr.yaml new file mode 100644 index 000000000..325078205 --- /dev/null +++ b/devices/patches/spi/rxtxdr.yaml @@ -0,0 +1,50 @@ +_add: + TXDR16: + access: write-only + addressOffset: 0x20 + alternateRegister: TXDR + description: Direct 16-bit access to transmit data register + size: 0x10 + fields: + TXDR: + bitOffset: 0 + bitWidth: 16 + description: Transmit data register + TXDR8: + access: write-only + addressOffset: 0x20 + alternateRegister: TXDR + description: Direct 8-bit access to transmit data register + size: 0x8 + fields: + TXDR: + bitOffset: 0 + bitWidth: 8 + description: Transmit data register + RXDR16: + access: read-only + addressOffset: 0x30 + alternateRegister: RXDR + description: Direct 16-bit access to receive data register + size: 0x10 + fields: + RXDR: + bitOffset: 0 + bitWidth: 16 + description: Receive data register + RXDR8: + access: read-only + addressOffset: 0x30 + alternateRegister: RXDR + description: Direct 8-bit access to receive data register + size: 0x8 + fields: + RXDR: + bitOffset: 0 + bitWidth: 8 + description: Receive data register + +TXDR16: + TXDR: [0, 0xffff] +TXDR8: + TXDR: [0, 0xff] diff --git a/devices/patches/spi/u5.yaml b/devices/patches/spi/u5.yaml new file mode 100644 index 000000000..2d0d101c5 --- /dev/null +++ b/devices/patches/spi/u5.yaml @@ -0,0 +1,12 @@ +CFG1: + _modify: + FTHVL: + name: FTHLV +CFG2: + _modify: + RDIMM: + name: RDIOM +IER: + _modify: + DPXPIE: + name: DXPIE diff --git a/devices/patches/syscfg/f0.yaml b/devices/patches/syscfg/f0.yaml new file mode 100644 index 000000000..d90f70cca --- /dev/null +++ b/devices/patches/syscfg/f0.yaml @@ -0,0 +1,15 @@ +CFGR1: + _delete: + - I2C2_FM_plus + - SPI2_DMA_RMP + - USART2_DMA_RMP + - I2C1_DMA_RMP + - TIM1_DMA_RMP + - TIM2_DMA_RMP + - TIM3_DMA_RMP +CFGR2: + _delete: + - PVD_LOCK + +_include: + - f0_common.yaml diff --git a/devices/patches/syscfg/f0_common.yaml b/devices/patches/syscfg/f0_common.yaml new file mode 100644 index 000000000..341719d7f --- /dev/null +++ b/devices/patches/syscfg/f0_common.yaml @@ -0,0 +1,29 @@ +CFGR1: + _add: + PA11_PA12_RMP: + description: PA11 and PA12 remapping bit for small packages (28 and 20 pins) + bitOffset: 4 + bitWidth: 1 + I2C_PA9_FMP: + description: "Fast Mode Plus (FM+) driving capability activation bits" + bitOffset: 22 + bitWidth: 1 + I2C_PA10_FMP: + description: "Fast Mode Plus (FM+) driving capability activation bits" + bitOffset: 23 + bitWidth: 1 + _modify: + I2C_PB6_FM: + name: I2C_PB6_FMP + I2C_PB7_FM: + name: I2C_PB7_FMP + I2C_PB8_FM: + name: I2C_PB8_FMP + I2C_PB9_FM: + name: I2C_PB9_FMP + I2C1_FM_plus: + name: I2C1_FMP +CFGR2: + _modify: + LOCUP_LOCK: + name: LOCKUP_LOCK diff --git a/devices/patches/syscfg/f3.yaml b/devices/patches/syscfg/f3.yaml new file mode 100644 index 000000000..bd54157bd --- /dev/null +++ b/devices/patches/syscfg/f3.yaml @@ -0,0 +1,53 @@ +_strip: SYSCFG_ +_delete: + - OPAMP* + - COMP* +CFGR1: + _modify: + "?~TIM1_ITR_RMP": + name: TIM1_ITR3_RMP + I2C_PB6_FM: + name: I2C_PB6_FMP + I2C_PB7_FM: + name: I2C_PB7_FMP + I2C_PB8_FM: + name: I2C_PB8_FMP + I2C_PB9_FM: + name: I2C_PB9_FMP + I2C1_FM: + name: I2C1_FMP + I2C2_FM: + name: I2C2_FMP + _delete: + - FPU_IT + _add: + FPU_IE5: + description: Inexact interrupt enable + bitOffset: 31 + bitWidth: 1 + access: read-write + FPU_IE4: + description: Input denormal interrupt enable + bitOffset: 30 + bitWidth: 1 + access: read-write + FPU_IE3: + description: Overflow interrupt enable + bitOffset: 29 + bitWidth: 1 + access: read-write + FPU_IE2: + description: Underflow interrupt enable + bitOffset: 28 + bitWidth: 1 + access: read-write + FPU_IE1: + description: Devide-by-zero interrupt enable + bitOffset: 27 + bitWidth: 1 + access: read-write + FPU_IE0: + description: Invalid operation interrupt enable + bitOffset: 26 + bitWidth: 1 + access: read-write diff --git a/devices/patches/syscfg/f3_cfgr1_adc2_dac1_rmp.yaml b/devices/patches/syscfg/f3_cfgr1_adc2_dac1_rmp.yaml new file mode 100644 index 000000000..43de247c3 --- /dev/null +++ b/devices/patches/syscfg/f3_cfgr1_adc2_dac1_rmp.yaml @@ -0,0 +1,8 @@ +# Modify names to fit the name in the register documentation +# instead of the register map name. +CFGR1: + _modify: + ADC24_DMA_RMP: + name: ADC2_DMA_RMP + DAC_TRIG_RMP: + name: DAC1_TRIG_RMP diff --git a/devices/patches/syscfg/f3_cfgr1_dac2_ch1_dma_rmp.yaml b/devices/patches/syscfg/f3_cfgr1_dac2_ch1_dma_rmp.yaml new file mode 100644 index 000000000..d1db026ed --- /dev/null +++ b/devices/patches/syscfg/f3_cfgr1_dac2_ch1_dma_rmp.yaml @@ -0,0 +1,7 @@ +CFGR1: + _add: + DAC2_CH1_DMA_RMP: + description: DAC2 channel1 DMA remap + bitOffset: 15 + bitWidth: 1 + access: read-write diff --git a/devices/patches/syscfg/f3_cfgr1_i2c3_fmp.yaml b/devices/patches/syscfg/f3_cfgr1_i2c3_fmp.yaml new file mode 100644 index 000000000..edbffd555 --- /dev/null +++ b/devices/patches/syscfg/f3_cfgr1_i2c3_fmp.yaml @@ -0,0 +1,7 @@ +CFGR1: + _add: + I2C3_FMP: + description: I2C3 Fast Mode Plus + bitOffset: 24 + bitWidth: 1 + access: read-write diff --git a/devices/patches/syscfg/f3_cfgr1_mem_mode_3.yaml b/devices/patches/syscfg/f3_cfgr1_mem_mode_3.yaml new file mode 100644 index 000000000..fba4cac21 --- /dev/null +++ b/devices/patches/syscfg/f3_cfgr1_mem_mode_3.yaml @@ -0,0 +1,4 @@ +CFGR1: + _modify: + MEM_MODE: + bitWidth: 3 diff --git a/devices/patches/syscfg/f3_cfgr1_timx_dacx_chx_dma_rmp.yaml b/devices/patches/syscfg/f3_cfgr1_timx_dacx_chx_dma_rmp.yaml new file mode 100644 index 000000000..e6dd4cfff --- /dev/null +++ b/devices/patches/syscfg/f3_cfgr1_timx_dacx_chx_dma_rmp.yaml @@ -0,0 +1,8 @@ +# Modify names to fit the name in the register documentation +# instead of the register map name. +CFGR1: + _modify: + TIM7_DAC2_DMA_RMP: + name: TIM7_DAC1_CH2_DMA_RMP + TIM6_DAC1_DMA_RMP: + name: TIM6_DAC1_CH1_DMA_RMP diff --git a/devices/patches/syscfg/f3_rcr_page8-15.yaml b/devices/patches/syscfg/f3_rcr_page8-15.yaml new file mode 100644 index 000000000..b5e9c094c --- /dev/null +++ b/devices/patches/syscfg/f3_rcr_page8-15.yaml @@ -0,0 +1,34 @@ +RCR: + _add: + PAGE8_WP: + description: CCM SRAM page write protection bit + bitOffset: 8 + bitWidth: 1 + PAGE9_WP: + description: CCM SRAM page write protection bit + bitOffset: 9 + bitWidth: 1 + PAGE10_WP: + description: CCM SRAM page write protection bit + bitOffset: 10 + bitWidth: 1 + PAGE11_WP: + description: CCM SRAM page write protection bit + bitOffset: 11 + bitWidth: 1 + PAGE12_WP: + description: CCM SRAM page write protection bit + bitOffset: 12 + bitWidth: 1 + PAGE13_WP: + description: CCM SRAM page write protection bit + bitOffset: 13 + bitWidth: 1 + PAGE14_WP: + description: CCM SRAM page write protection bit + bitOffset: 14 + bitWidth: 1 + PAGE15_WP: + description: CCM SRAM page write protection bit + bitOffset: 15 + bitWidth: 1 diff --git a/devices/patches/syscfg/f4_common.yaml b/devices/patches/syscfg/f4_common.yaml new file mode 100644 index 000000000..89acb1b2f --- /dev/null +++ b/devices/patches/syscfg/f4_common.yaml @@ -0,0 +1,9 @@ +_modify: + MEMRM: + name: MEMRMP +CMPCR: + _modify: + READY: + access: read-only + CMP_PD: + access: read-write diff --git a/devices/patches/syscfg/f730_f7x2_f7x3.yaml b/devices/patches/syscfg/f730_f7x2_f7x3.yaml new file mode 100644 index 000000000..a0d4bf1e9 --- /dev/null +++ b/devices/patches/syscfg/f730_f7x2_f7x3.yaml @@ -0,0 +1,14 @@ +PMC: + _add: + ADC3DC2: + description: ADC3DC2 + bitOffset: 18 + bitWidth: 1 + ADC2DC2: + description: ADC2DC2 + bitOffset: 17 + bitWidth: 1 + _modify: + ADCDC2: + name: ADC1DC2 + bitWidth: 1 diff --git a/devices/patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml b/devices/patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml new file mode 100644 index 000000000..b47b80797 --- /dev/null +++ b/devices/patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml @@ -0,0 +1,8 @@ +_modify: + MEMRM: + name: MEMRMP +MEMRMP: + _modify: + MEM_MODE: + name: MEM_BOOT + bitWidth: 1 diff --git a/devices/patches/syscfg/f765_f7x7_f7x9.yaml b/devices/patches/syscfg/f765_f7x7_f7x9.yaml new file mode 100644 index 000000000..7f5272498 --- /dev/null +++ b/devices/patches/syscfg/f765_f7x7_f7x9.yaml @@ -0,0 +1,34 @@ +PMC: + _add: + PB9_FMP: + description: PB9_FMP Fast Mode + Enable + bitOffset: 7 + bitWidth: 1 + PB8_FMP: + description: PB8_FMP Fast Mode + Enable + bitOffset: 6 + bitWidth: 1 + PB7_FMP: + description: PB7_FMP Fast Mode + Enable + bitOffset: 5 + bitWidth: 1 + PB6_FMP: + description: PB6_FMP Fast Mode + Enable + bitOffset: 4 + bitWidth: 1 + I2C4_FMP: + description: I2C4 Fast Mode + Enable + bitOffset: 3 + bitWidth: 1 + I2C3_FMP: + description: I2C3 Fast Mode + Enable + bitOffset: 2 + bitWidth: 1 + I2C2_FMP: + description: I2C2 Fast Mode + Enable + bitOffset: 1 + bitWidth: 1 + I2C1_FMP: + description: I2C1 Fast Mode + Enable + bitOffset: 0 + bitWidth: 1 diff --git a/devices/patches/syscfg/h73x.yaml b/devices/patches/syscfg/h73x.yaml new file mode 100644 index 000000000..541bd4b3c --- /dev/null +++ b/devices/patches/syscfg/h73x.yaml @@ -0,0 +1,94 @@ +_add: + CFGR: + description: Timer break lockup register + addressOffset: 0x18 + resetValue: 0x00000000 + fields: + PVDL: + description: Programmable voltage detector lockup bit + bitOffset: 2 + bitWidth: 1 + FLASHL: + description: FLASH double error lockup bit + bitOffset: 3 + bitWidth: 1 + CM7L: + description: CPU lockup bit + bitOffset: 6 + bitWidth: 1 + BKRAML: + description: Backup RAM Double error lockup bit + bitOffset: 7 + bitWidth: 1 + SRAM4L: + description: SRAM4 Double error lockup bit + bitOffset: 9 + bitWidth: 1 + SRAM2L: + description: SRAM2 Double error lockup bit + bitOffset: 11 + bitWidth: 1 + SRAM1L: + description: SRAM1 Double error lockup bit + bitOffset: 12 + bitWidth: 1 + DTCML: + description: DTCM-RAM Double error lockup bit + bitOffset: 13 + bitWidth: 1 + ITCML: + description: ITCM-RAM Double error lockup bit + bitOffset: 14 + bitWidth: 1 + AXIRAML: + description: AXISRAM Double error lockup bit + bitOffset: 15 + bitWidth: 1 + ADC2ALT: + description: ADC2 internal input alternate connection + addressOffset: 0x30 + resetValue: 0x00000000 + fields: + ADC2_ROUT1: + description: ADC2 V_INP17 alternate connection + bitOffset: 1 + bitWidth: 1 + ADC2_ROUT0: + description: ADC2 V_INP16 alternate connection + bitOffset: 0 + bitWidth: 1 + UR18: + description: SYSCFG user register 18 + addressOffset: 0x348 + access: read-only + fields: + CPU_FREQ_BOOST: + description: CPU maximum frequency boost + bitOffset: 0 + bitWidth: 1 +_delete: + - UR8 # Only one flash bank + - UR9 + - UR10 +PMCR: + _add: + BOOSTVDDSEL: + description: Analog switch supply voltage selection + bitWidth: 1 + bitOffset: 9 + I2C5FMP: + description: I2C5 Fm+ + bitWidth: 1 + bitOffset: 10 +UR0: + _delete: + - BKS +UR11: + _delete: + - SA_END_2 +UR17: + _add: + TCM_AXI_SHARED_CFG: + description: ITCM-RAM/AXI-SRAM size + bitOffset: 16 + bitWidth: 2 diff --git a/devices/patches/syscfg/h74x_pwrcr.yaml b/devices/patches/syscfg/h74x_pwrcr.yaml new file mode 100644 index 000000000..2355b0c2b --- /dev/null +++ b/devices/patches/syscfg/h74x_pwrcr.yaml @@ -0,0 +1,5 @@ +PWRCR: + _modify: + ODEN: + bitWidth: 1 + description: Overdrive enable diff --git a/devices/patches/syscfg/l0_cfgr.yaml b/devices/patches/syscfg/l0_cfgr.yaml new file mode 100644 index 000000000..e02845a15 --- /dev/null +++ b/devices/patches/syscfg/l0_cfgr.yaml @@ -0,0 +1,50 @@ +# Add SYSCFG registers +CFGR1: + _add: + UFB: + description: User bank swapping + bitOffset: 3 + bitWidth: 1 +CFGR2: + _add: + I2C3_FMP: + description: I2C3 Fm+ drive capability enable bit + bitOffset: 14 + bitWidth: 1 + FWDIS: + description: Firewall disable bit + bitOffset: 0 + bitWidth: 1 + _delete: + - CAPA + - FWDISEN +CFGR3: + _delete: + - REF_LOCK + - VREFINT_COMP_RDYF + - VREFINT_ADC_RDYF + - SENSOR_ADC_RDYF + - REF_RC48MHz_RDYF + - ENREF_RC48MHz + - ENBUF_VREFINT_COMP + - ENBUF_BGAP_ADC + - EN_BGAP + _add: + # REF_LOCK is wrongly marked as write-only, but it's "rs" - read/set + REF_LOCK: + description: SYSCFG_CFGR3 lock bit + bitOffset: 31 + bitWidth: 1 + access: read-write + ENBUF_VREFINT_COMP2: + description: VREFINT reference for COMP2 scaler enable bit + bitOffset: 12 + bitWidth: 1 + ENBUF_VREFINT_ADC: + description: VREFINT reference for ADC enable bit + bitOffset: 8 + bitWidth: 1 + EN_VREFINT: + description: VREFINT enable and scaler control for COMP2 enable bit + bitOffset: 0 + bitWidth: 1 diff --git a/devices/patches/syscfg/l4+.yaml b/devices/patches/syscfg/l4+.yaml new file mode 100644 index 000000000..0091b0b60 --- /dev/null +++ b/devices/patches/syscfg/l4+.yaml @@ -0,0 +1,186 @@ +_add: + SWPR2: + description: write protection register 2 + addressOffset: 0x28 + resetValue: 0x0 + fields: + P63WP: + description: SRAM2 page x write protection + bitOffset: 31 + bitWidth: 1 + P62WP: + description: SRAM2 page x write protection + bitOffset: 30 + bitWidth: 1 + P61WP: + description: SRAM2 page x write protection + bitOffset: 29 + bitWidth: 1 + P60WP: + description: SRAM2 page x write protection + bitOffset: 28 + bitWidth: 1 + P59WP: + description: SRAM2 page x write protection + bitOffset: 27 + bitWidth: 1 + P58WP: + description: SRAM2 page x write protection + bitOffset: 26 + bitWidth: 1 + P57WP: + description: SRAM2 page x write protection + bitOffset: 25 + bitWidth: 1 + P56WP: + description: SRAM2 page x write protection + bitOffset: 24 + bitWidth: 1 + P55WP: + description: SRAM2 page x write protection + bitOffset: 23 + bitWidth: 1 + P54WP: + description: SRAM2 page x write protection + bitOffset: 22 + bitWidth: 1 + P53WP: + description: SRAM2 page x write protection + bitOffset: 21 + bitWidth: 1 + P52WP: + description: SRAM2 page x write protection + bitOffset: 20 + bitWidth: 1 + P51WP: + description: SRAM2 page x write protection + bitOffset: 19 + bitWidth: 1 + P50WP: + description: SRAM2 page x write protection + bitOffset: 18 + bitWidth: 1 + P49WP: + description: SRAM2 page x write protection + bitOffset: 17 + bitWidth: 1 + P48WP: + description: SRAM2 page x write protection + bitOffset: 16 + bitWidth: 1 + P47WP: + description: SRAM2 page x write protection + bitOffset: 15 + bitWidth: 1 + P46WP: + description: SRAM2 page x write protection + bitOffset: 14 + bitWidth: 1 + P45WP: + description: SRAM2 page x write protection + bitOffset: 13 + bitWidth: 1 + P44WP: + description: SRAM2 page x write protection + bitOffset: 12 + bitWidth: 1 + P43WP: + description: SRAM2 page x write protection + bitOffset: 11 + bitWidth: 1 + P42WP: + description: SRAM2 page x write protection + bitOffset: 10 + bitWidth: 1 + P41WP: + description: SRAM2 page x write protection + bitOffset: 9 + bitWidth: 1 + P40WP: + description: SRAM2 page x write protection + bitOffset: 8 + bitWidth: 1 + P39WP: + description: SRAM2 page x write protection + bitOffset: 7 + bitWidth: 1 + P38WP: + description: SRAM2 page x write protection + bitOffset: 6 + bitWidth: 1 + P37WP: + description: SRAM2 page x write protection + bitOffset: 5 + bitWidth: 1 + P36WP: + description: SRAM2 page x write protection + bitOffset: 4 + bitWidth: 1 + P35WP: + description: SRAM2 page x write protection + bitOffset: 3 + bitWidth: 1 + P34WP: + description: SRAM2 page x write protection + bitOffset: 2 + bitWidth: 1 + P33WP: + description: SRAM2 page x write protection + bitOffset: 1 + bitWidth: 1 + P32WP: + description: SRAM2 page x write protection + bitOffset: 0 + bitWidth: 1 + +MEMRMP: + _delete: + - QFS + +CFGR1: + _delete: + - FPU_IE + + _add: + FPU_IE5: + description: Inexact interrupt enable + bitOffset: 31 + bitWidth: 1 + FPU_IE4: + description: Input denormal interrupt enable + bitOffset: 30 + bitWidth: 1 + FPU_IE3: + description: Overflow interrupt enable + bitOffset: 29 + bitWidth: 1 + FPU_IE2: + description: Underflow interrupt enable + bitOffset: 28 + bitWidth: 1 + FPU_IE1: + description: Divide-by-zero interrupt enable + bitOffset: 27 + bitWidth: 1 + FPU_IE0: + description: Invalid operation interrupt enable + bitOffset: 26 + bitWidth: 1 + ANASWVDD: + description: GPIO analog switch control voltage selection when at least one analog peripheral supplied by VDDA is enabled (COMP, OPAMP, VREFBUF, ADC,...) + bitOffset: 9 + bitWidth: 1 + I2C4_FMP: + description: I2C3 Fast-mode Plus driving capability activation + bitOffset: 23 + bitWidth: 1 + +EXTICR?: + _modify: + EXTI*: + bitWidth: 4 + +SCSR: + _modify: + SRAM2BSY: + name: SRAM2BS diff --git a/devices/patches/tim/add_dither16.yaml b/devices/patches/tim/add_dither16.yaml new file mode 100644 index 000000000..604cb3bd5 --- /dev/null +++ b/devices/patches/tim/add_dither16.yaml @@ -0,0 +1,24 @@ +ARR: + _add: + INTEGER: + description: Integer part in dithering mode + bitOffset: 4 + bitWidth: 16 + access: read-write + DITHER: + description: Dithered part in dithering mode + bitOffset: 0 + bitWidth: 4 + access: read-write +"?~CCR?": + _add: + INTEGER: + description: Integer part in dithering mode + bitOffset: 4 + bitWidth: 16 + access: read-write + DITHER: + description: Dithered part in dithering mode + bitOffset: 0 + bitWidth: 4 + access: read-write diff --git a/devices/patches/tim/add_dither32.yaml b/devices/patches/tim/add_dither32.yaml new file mode 100644 index 000000000..7b63b32f2 --- /dev/null +++ b/devices/patches/tim/add_dither32.yaml @@ -0,0 +1,24 @@ +ARR: + _add: + INTEGER: + description: Integer part in dithering mode + bitOffset: 4 + bitWidth: 28 + access: read-write + DITHER: + description: Dithered part in dithering mode + bitOffset: 0 + bitWidth: 4 + access: read-write +CCR?: + _add: + INTEGER: + description: Integer part in dithering mode + bitOffset: 4 + bitWidth: 28 + access: read-write + DITHER: + description: Dithered part in dithering mode + bitOffset: 0 + bitWidth: 4 + access: read-write diff --git a/devices/patches/tim/ccmr1_alternate.yaml b/devices/patches/tim/ccmr1_alternate.yaml new file mode 100644 index 000000000..d39b8d111 --- /dev/null +++ b/devices/patches/tim/ccmr1_alternate.yaml @@ -0,0 +1,8 @@ +_modify: + "CCMR1,CCMR1_input,CCMR1_INPUT": + name: CCMR1_Input + displayName: CCMR1_Input + "CCMR1_output,CCMR1_ALTERNATE*,CCMR1_OUTPUT": + name: CCMR1_Output + displayName: CCMR1_Output + alternateRegister: CCMR1_Input diff --git a/devices/patches/tim/ccmr2_alternate.yaml b/devices/patches/tim/ccmr2_alternate.yaml new file mode 100644 index 000000000..3bf09b039 --- /dev/null +++ b/devices/patches/tim/ccmr2_alternate.yaml @@ -0,0 +1,8 @@ +_modify: + "CCMR2,CCMR2_input,CCMR2_INPUT": + name: CCMR2_Input + displayName: CCMR2_Input + "CCMR2_output,CCMR2_ALTERNATE*,CCMR2_OUTPUT": + name: CCMR2_Output + displayName: CCMR2_Output + alternateRegister: CCMR2_Input diff --git a/devices/patches/tim/ccmr3.yaml b/devices/patches/tim/ccmr3.yaml new file mode 100644 index 000000000..dea8741af --- /dev/null +++ b/devices/patches/tim/ccmr3.yaml @@ -0,0 +1,4 @@ +_modify: + CCMR3: + name: CCMR3_Output + displayName: CCMR3_Output diff --git a/devices/patches/tim/dmab_32.yaml b/devices/patches/tim/dmab_32.yaml new file mode 100644 index 000000000..55ccd1b71 --- /dev/null +++ b/devices/patches/tim/dmab_32.yaml @@ -0,0 +1,6 @@ +DMAR: + _modify: + # Self-inconsistency between the register map and the + # specific register field documentation in RMs + DMAB: + bitWidth: 32 diff --git a/devices/patches/tim/g0_tim1_ts.yaml b/devices/patches/tim/g0_tim1_ts.yaml new file mode 100644 index 000000000..682d31539 --- /dev/null +++ b/devices/patches/tim/g0_tim1_ts.yaml @@ -0,0 +1,6 @@ +SMCR: + _modify: + TS: + name: TS2 + TS_4: + name: TS diff --git a/devices/patches/tim/group.yaml b/devices/patches/tim/group.yaml new file mode 100644 index 000000000..170ec0bd1 --- /dev/null +++ b/devices/patches/tim/group.yaml @@ -0,0 +1,3 @@ +_modify: + TIM*: + groupName: TIM diff --git a/devices/patches/tim/icpsc.yaml b/devices/patches/tim/icpsc.yaml new file mode 100644 index 000000000..40f337254 --- /dev/null +++ b/devices/patches/tim/icpsc.yaml @@ -0,0 +1,6 @@ +CCMR1_Input: + _modify: + "ICPCS,IC1PCS": + name: IC1PSC + "?~IC2PCS": + name: IC2PSC diff --git a/devices/patches/tim/l1_ccs.yaml b/devices/patches/tim/l1_ccs.yaml new file mode 100644 index 000000000..38bb97515 --- /dev/null +++ b/devices/patches/tim/l1_ccs.yaml @@ -0,0 +1,4 @@ +CCMR?_Output: + _modify: + CC?S: + bitWidth: 2 diff --git a/devices/patches/tim/l1_tim9_ccer.yaml b/devices/patches/tim/l1_tim9_ccer.yaml new file mode 100644 index 000000000..cd166039a --- /dev/null +++ b/devices/patches/tim/l1_tim9_ccer.yaml @@ -0,0 +1,33 @@ +_add: + CCER: + displayName: CCER + description: capture/compare enable register + addressOffset: 0x20 + size: 0x20 + access: read-write + resetValue: 0x0000 + fields: + CC2NP: + description: Capture/Compare 2 complementary output Polarity + bitOffset: 7 + bitWidth: 1 + CC2P: + description: Capture/Compare 2 output Polarity + bitOffset: 5 + bitWidth: 1 + CC2E: + description: Capture/Compare 2 output enable + bitOffset: 4 + bitWidth: 1 + CC1NP: + description: Capture/Compare 1 complementary output Polarity + bitOffset: 3 + bitWidth: 1 + CC1P: + description: Capture/Compare 1 output Polarity + bitOffset: 1 + bitWidth: 1 + CC1E: + description: Capture/Compare 1 output enable + bitOffset: 0 + bitWidth: 1 diff --git a/devices/patches/tim/l4_tim15_ch2.yaml b/devices/patches/tim/l4_tim15_ch2.yaml new file mode 100644 index 000000000..0141717d9 --- /dev/null +++ b/devices/patches/tim/l4_tim15_ch2.yaml @@ -0,0 +1,64 @@ +# TIM15 channel 2 for STM32L4x +CCER: + _add: + CC2E: + description: Capture/Compare 2 output enable + bitWidth: 1 + bitOffset: 4 + CC2P: + description: Capture/Compare 2 output polarity + bitWidth: 1 + bitOffset: 5 + CC2NP: + description: Capture/Compare 2 complementary output polarity + bitWidth: 1 + bitOffset: 7 + +CCMR1_Input: + _add: + CC2S: + description: Capture/Compare 2 selection + bitWidth: 2 + bitOffset: 8 + IC2PSC: + description: Input capture 2 prescaler + bitWidth: 2 + bitOffset: 10 + IC2F: + description: Input capture 2 filter + bitWidth: 4 + bitOffset: 12 + +CCMR1_Output: + _add: + CC2S: + description: Capture/Compare 2 selection + bitWidth: 2 + bitOffset: 8 + OC2FE: + description: Output Compare 2 fast enable + bitWidth: 1 + bitOffset: 10 + OC2PE: + description: Capture/Compare 2 selection + bitWidth: 1 + bitOffset: 11 + OC2M: + description: Output Compare 2 mode + bitWidth: 3 + bitOffset: 12 + OC2M_3: + description: Output Compare 2 mode - bit 3 + bitWidth: 1 + bitOffset: 24 + +_add: + CCR2: + description: Channel 2 capture/compare register + addressOffset: 0x38 + fields: + CCR2: + description: Capture/Compare 2 value + access: read-write + bitOffset: 0 + bitWidth: 16 diff --git a/devices/patches/tim/mms.yaml b/devices/patches/tim/mms.yaml new file mode 100644 index 000000000..d2c9fa1bf --- /dev/null +++ b/devices/patches/tim/mms.yaml @@ -0,0 +1,4 @@ +CR2: + _modify: + "MMS1,MMS0_2": + name: MMS diff --git a/devices/patches/tim/omp.yaml b/devices/patches/tim/omp.yaml new file mode 100644 index 000000000..9b8106108 --- /dev/null +++ b/devices/patches/tim/omp.yaml @@ -0,0 +1,4 @@ +CR1: + _modify: + OMP: + name: OPM diff --git a/devices/patches/tim/rename_TIM2_CCR3_CCR3.yaml b/devices/patches/tim/rename_TIM2_CCR3_CCR3.yaml new file mode 100644 index 000000000..92e0ae8ca --- /dev/null +++ b/devices/patches/tim/rename_TIM2_CCR3_CCR3.yaml @@ -0,0 +1,6 @@ +# Rename badly named + +CCR3: + _modify: + CCR1: + name: CCR3 diff --git a/devices/patches/tim/rep_16b.yaml b/devices/patches/tim/rep_16b.yaml new file mode 100644 index 000000000..04d324d56 --- /dev/null +++ b/devices/patches/tim/rep_16b.yaml @@ -0,0 +1,4 @@ +RCR: + _modify: + REP: + bitWidth: 16 diff --git a/devices/patches/tim/size16b.yaml b/devices/patches/tim/size16b.yaml new file mode 100644 index 000000000..b24521c31 --- /dev/null +++ b/devices/patches/tim/size16b.yaml @@ -0,0 +1,6 @@ +# Per RM0367,RM0376, RM0377 all timers have 16 bit registers for CNT,ARR,CCRx +_modify: + CNT: + size: 16 + ARR: + size: 16 diff --git a/devices/patches/tim/sms.yaml b/devices/patches/tim/sms.yaml new file mode 100644 index 000000000..220dc6447 --- /dev/null +++ b/devices/patches/tim/sms.yaml @@ -0,0 +1,6 @@ +SMCR: + _modify: + "SMS,SMS1": + name: SMS + "SMS2,SMS_bit3,SMS_[12],SMS3_0": + name: SMS_3 diff --git a/devices/patches/tim/tim10_14_missing_opm.yaml b/devices/patches/tim/tim10_14_missing_opm.yaml new file mode 100644 index 000000000..adf940413 --- /dev/null +++ b/devices/patches/tim/tim10_14_missing_opm.yaml @@ -0,0 +1,6 @@ +CR1: + _add: + OPM: + bitOffset: 3 + bitWidth: 1 + description: One-pulse mode diff --git a/devices/patches/tim/tim1_mms_ts_sms.yaml b/devices/patches/tim/tim1_mms_ts_sms.yaml new file mode 100644 index 000000000..fce91bc09 --- /dev/null +++ b/devices/patches/tim/tim1_mms_ts_sms.yaml @@ -0,0 +1,12 @@ +# Applicable to H5 +# The MMS, TS, SMS fields in the CR2 and SMCR registers are +# extended in the general purpose and advanced timers + +CR2: + _modify: + MMS_1: + name: MMS_3 + +_include: + - sms.yaml + - ts.yaml diff --git a/devices/patches/tim/tim2_arr.yaml b/devices/patches/tim/tim2_arr.yaml new file mode 100644 index 000000000..0c792ec11 --- /dev/null +++ b/devices/patches/tim/tim2_arr.yaml @@ -0,0 +1,32 @@ +CCR1: + _modify: + "CCR1H,CCR1_H": + name: CCR1H + description: Capture/Compare 1 value + "CCR1L,CCR1_L": + name: CCR1L + _merge: CCR1* +CCR2: + _modify: + "CCR2H,CCR2_H": + name: CCR2H + description: Capture/Compare 2 value + "CCR2L,CCR2_L": + name: CCR2L + _merge: CCR2* +CCR3: + _modify: + "CCR3H,CCR3_H": + name: CCR3H + description: Capture/Compare 3 value + "CCR3L,CCR3_L": + name: CCR3L + _merge: CCR3* +CCR4: + _modify: + "CCR4H,CCR4_H": + name: CCR4H + description: Capture/Compare 4 value + "CCR4L,CCR4_L": + name: CCR4L + _merge: CCR4* diff --git a/devices/patches/tim/tim2_cnt_32bit.yaml b/devices/patches/tim/tim2_cnt_32bit.yaml new file mode 100644 index 000000000..ded3b5080 --- /dev/null +++ b/devices/patches/tim/tim2_cnt_32bit.yaml @@ -0,0 +1,8 @@ +CNT: + _modify: + CNT_H: + name: CNTH + description: Counter value + CNT_L: + name: CNTL + _merge: CNT* diff --git a/devices/patches/tim/tim2_common_32bit.yaml b/devices/patches/tim/tim2_common_32bit.yaml new file mode 100644 index 000000000..0c5f2e7d7 --- /dev/null +++ b/devices/patches/tim/tim2_common_32bit.yaml @@ -0,0 +1,21 @@ +# 32bit TIM2 peripheral +# Applies to Advanced-control (ac) and General-purpose (gp) timers + +# TIM2 is present on all devices except stm32f410 and stm32f0x0. +# TIM2 is 16bit on STM32F1 family. +# TIM3 is present on all devices with TIM2 except STML4x3 family. +# TIM3 is present on stm32f0x0. + +CNT: + # Actualy a 32bit register + _modify: + "CNTH,CNT_H": + name: CNTH + description: Counter value + "CNTL,CNT_L": + name: CNTL + _merge: CNT* + +_include: + - tim2_arr.yaml + - tim2_cr.yaml diff --git a/devices/patches/tim/tim2_cr.yaml b/devices/patches/tim/tim2_cr.yaml new file mode 100644 index 000000000..200be09f9 --- /dev/null +++ b/devices/patches/tim/tim2_cr.yaml @@ -0,0 +1,9 @@ +ARR: + # Actualy a 32bit register + _modify: + "ARRH,ARR_H": + name: ARRH + description: Auto-reload value + "ARRL,ARR_L": + name: ARRL + _merge: ARR* diff --git a/devices/patches/tim/tim2_itr1_rmp.yaml b/devices/patches/tim/tim2_itr1_rmp.yaml new file mode 100644 index 000000000..494f617fb --- /dev/null +++ b/devices/patches/tim/tim2_itr1_rmp.yaml @@ -0,0 +1,12 @@ +# TIM2 peripheral on STM32F405/415, STM32F407/F417, STM32F427/437, STM32F429/439 +# can remap ITR1 to internal trigger signals +# +# + +OR: + ITR1_RMP: + _replace_enum: + TIM8_TRGOUT: [0, TIM8 trigger output is connected to TIM2_ITR1 input] + PTP: [1, Ethernet PTP clock is connected to TIM2_ITR1 input] + OTG_FS_SOF: [2, OTG FS SOF is connected to the TIM2_ITR1 input] + OTG_HS_SOF: [3, OTG HS SOF is connected to the TIM2_ITR1 input] diff --git a/devices/patches/tim/tim2_mms_ts_sms.yaml b/devices/patches/tim/tim2_mms_ts_sms.yaml new file mode 100644 index 000000000..cdcd405fb --- /dev/null +++ b/devices/patches/tim/tim2_mms_ts_sms.yaml @@ -0,0 +1,14 @@ +# Applicable to H5 +# The MMS, TS, SMS fields in the CR2 and SMCR registers are +# extended in the general purpose and advanced timers + +CR2: + _modify: + "?~MMS1": + name: MMS + "MMS_1,MMS2": + name: MMS_3 + +_include: + - sms.yaml + - ts.yaml diff --git a/devices/patches/tim/tim9_ic1f.yaml b/devices/patches/tim/tim9_ic1f.yaml new file mode 100644 index 000000000..e34fcbd3f --- /dev/null +++ b/devices/patches/tim/tim9_ic1f.yaml @@ -0,0 +1,4 @@ +CCMR1_Input: + _modify: + IC?F: + bitWidth: 4 diff --git a/devices/patches/tim/tim_ccrx_16bit.yaml b/devices/patches/tim/tim_ccrx_16bit.yaml new file mode 100644 index 000000000..d3c650e98 --- /dev/null +++ b/devices/patches/tim/tim_ccrx_16bit.yaml @@ -0,0 +1,6 @@ +CCR?: + _modify: + "CCR?": + name: CCR + description: Capture/Compare value + bitWidth: 16 diff --git a/devices/patches/tim/tim_ch_16bit_l.yaml b/devices/patches/tim/tim_ch_16bit_l.yaml new file mode 100644 index 000000000..8860c9bfc --- /dev/null +++ b/devices/patches/tim/tim_ch_16bit_l.yaml @@ -0,0 +1,24 @@ +# 16bit timer peripheral with one channel +# For 16bit timers where the SVD names fields ending "L" or "_L" +# Applies to Advanced-control (ac) and General-purpose (gp) timers + +CNT: + _modify: + "CNT_L,CNTL": + name: CNT + description: Counter value + _delete: "CNT_H,CNTH,CNT_bit31" +ARR: + _modify: + "ARR_L,ARRL": + name: ARR + description: Auto-reload value + ARR: + bitWidth: 16 + _delete: "ARR_H,ARRH" +CCR?: + _modify: + "CCR?,CCR?_L,CCR?L": + name: CCR + description: Capture/Compare value + _delete: "CCR?_H,CCR?H" diff --git a/devices/patches/tim/tim_cnt_16bit_l.yaml b/devices/patches/tim/tim_cnt_16bit_l.yaml new file mode 100644 index 000000000..4b7e62698 --- /dev/null +++ b/devices/patches/tim/tim_cnt_16bit_l.yaml @@ -0,0 +1,10 @@ +CNT: + _modify: + CNT_L: + name: CNT + description: Counter value + _delete: "CNT_H,CNTH" +ARR: + _modify: + ARR: + bitWidth: 16 diff --git a/devices/patches/tim/tim_o24ce.yaml b/devices/patches/tim/tim_o24ce.yaml new file mode 100644 index 000000000..88a240d2b --- /dev/null +++ b/devices/patches/tim/tim_o24ce.yaml @@ -0,0 +1,4 @@ +CCMR2_Output: + _modify: + O24CE: + name: OC4CE diff --git a/devices/patches/tim/tim_uifremap.yaml b/devices/patches/tim/tim_uifremap.yaml new file mode 100644 index 000000000..245f273db --- /dev/null +++ b/devices/patches/tim/tim_uifremap.yaml @@ -0,0 +1,17 @@ +# Applicable to the H5 family +# The MSB of the 32-bit CNT register on TIM2 and TIM5 stores a read-only copy of +# the UIF flag, UIFCPY, if UIFREMAP is set. This adds a field to access it and fix +# the description of CNT when applied. +CNT: + _modify: + CNT: + description: "Non-dithering mode (DITHEN = 0)\n + The register holds the counter value.\n + Dithering mode (DITHEN = 1)\n + The register holds the non-dithered part. The fractional part is not available." + _add: + UIFCPY: + description: Read-only copy of the UIF bit of the TIMx_ISR register + bitOffset: 31 + bitWidth: 1 + access: read-only diff --git a/devices/patches/tim/ts.yaml b/devices/patches/tim/ts.yaml new file mode 100644 index 000000000..15dd7e519 --- /dev/null +++ b/devices/patches/tim/ts.yaml @@ -0,0 +1,6 @@ +SMCR: + _modify: + "TS,TS1,TS_2_0": + name: TS + "TS2,TS3_4,TS_4_3,TS_[12],TS4_3": + name: TS2 diff --git a/devices/patches/tim/v2/add_af.yaml b/devices/patches/tim/v2/add_af.yaml new file mode 100644 index 000000000..d1ec9a10f --- /dev/null +++ b/devices/patches/tim/v2/add_af.yaml @@ -0,0 +1,39 @@ +_add: + AF1: + description: alternate function option register 1 + addressOffset: 0x60 + size: 0x20 + resetValue: 0x00000001 + access: read-write + fields: + BKINE: + description: BRK BKIN input enable + bitOffset: 0 + bitWidth: 1 + BKDFBKE: + description: BRK DFSDM_BREAK[0] enable + bitOffset: 8 + bitWidth: 1 + BKINP: + description: BRK BKIN input polarity + bitOffset: 9 + bitWidth: 1 + AF2: + description: alternate function option register 2 + addressOffset: 0x64 + size: 0x20 + resetValue: 0x00000001 + access: read-write + fields: + BK2INE: + description: BRK2 BKIN input enable + bitOffset: 0 + bitWidth: 1 + BK2DFBKE: + description: BRK2 DFSDM_BREAK[0] enable + bitOffset: 8 + bitWidth: 1 + BK2INP: + description: BRK2 BKIN input polarity + bitOffset: 9 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_bkf.yaml b/devices/patches/tim/v2/add_bkf.yaml new file mode 100644 index 000000000..3126283c9 --- /dev/null +++ b/devices/patches/tim/v2/add_bkf.yaml @@ -0,0 +1,18 @@ +BDTR: + _add: + BKF: + description: Break filter + bitOffset: 16 + bitWidth: 4 + BK2F: + description: Break 2 filter + bitOffset: 20 + bitWidth: 4 + BK2E: + description: Break 2 enable + bitOffset: 24 + bitWidth: 1 + BK2P: + description: Break 2 polarity + bitOffset: 25 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_cc4np.yaml b/devices/patches/tim/v2/add_cc4np.yaml new file mode 100644 index 000000000..9eec3ad43 --- /dev/null +++ b/devices/patches/tim/v2/add_cc4np.yaml @@ -0,0 +1,6 @@ +CCER: + _add: + CC4NP: + description: Capture/Compare 4 complementary output polarity + bitOffset: 15 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_cc5.yaml b/devices/patches/tim/v2/add_cc5.yaml new file mode 100644 index 000000000..23c082f6c --- /dev/null +++ b/devices/patches/tim/v2/add_cc5.yaml @@ -0,0 +1,52 @@ +CR2: + _add: + OIS5: + description: Output Idle state 5 (OC5 output) + bitOffset: 16 + bitWidth: 1 + OIS6: + description: Output Idle state 6 (OC6 output) + bitOffset: 18 + bitWidth: 1 + MMS2: + description: Master mode selection 2 + bitOffset: 20 + bitWidth: 4 +SR: + _add: + B2IF: + description: Break 2 interrupt flag + bitOffset: 8 + bitWidth: 1 + CC5IF: + description: Compare 5 interrupt flag + bitOffset: 16 + bitWidth: 1 + CC6IF: + description: Compare 6 interrupt flag + bitOffset: 17 + bitWidth: 1 +EGR: + _add: + B2G: + description: Break 2 generation + bitOffset: 8 + bitWidth: 1 +CCER: + _add: + CC5E: + description: Capture/Compare 5 output enable + bitOffset: 16 + bitWidth: 1 + CC5P: + description: Capture/Compare 5 output polarity + bitOffset: 17 + bitWidth: 1 + CC6E: + description: Capture/Compare 6 output enable + bitOffset: 20 + bitWidth: 1 + CC6P: + description: Capture/Compare 6 output polarity + bitOffset: 21 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_cc5if.yaml b/devices/patches/tim/v2/add_cc5if.yaml new file mode 100644 index 000000000..a1c8134c0 --- /dev/null +++ b/devices/patches/tim/v2/add_cc5if.yaml @@ -0,0 +1,10 @@ +SR: + _add: + CC5IF: + description: Compare 5 interrupt flag + bitOffset: 16 + bitWidth: 1 + CC6IF: + description: Compare 6 interrupt flag + bitOffset: 17 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_ocm1_bit3.yaml b/devices/patches/tim/v2/add_ocm1_bit3.yaml new file mode 100644 index 000000000..050d345fe --- /dev/null +++ b/devices/patches/tim/v2/add_ocm1_bit3.yaml @@ -0,0 +1,6 @@ +CCMR1_Output: + _add: + OC1M_3: + description: "Output Compare 1 mode, bit 3" + bitOffset: 16 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_ocm2_bit3.yaml b/devices/patches/tim/v2/add_ocm2_bit3.yaml new file mode 100644 index 000000000..963dfb33a --- /dev/null +++ b/devices/patches/tim/v2/add_ocm2_bit3.yaml @@ -0,0 +1,6 @@ +CCMR1_Output: + _add: + OC2M_3: + description: "Output Compare 2 mode, bit 3" + bitOffset: 24 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_ocm_bit3.yaml b/devices/patches/tim/v2/add_ocm_bit3.yaml new file mode 100644 index 000000000..3ac378750 --- /dev/null +++ b/devices/patches/tim/v2/add_ocm_bit3.yaml @@ -0,0 +1,14 @@ +_include: + - add_ocm1_bit3.yaml + - add_ocm2_bit3.yaml + +CCMR2_Output: + _add: + OC3M_3: + description: "Output Compare 3 mode, bit 3" + bitOffset: 16 + bitWidth: 1 + OC4M_3: + description: "Output Compare 4 mode, bit 3" + bitOffset: 24 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_sms_bit3.yaml b/devices/patches/tim/v2/add_sms_bit3.yaml new file mode 100644 index 000000000..39b81cf1b --- /dev/null +++ b/devices/patches/tim/v2/add_sms_bit3.yaml @@ -0,0 +1,6 @@ +SMCR: + _add: + SMS_3: + description: Slave mode selection - bit 3 + bitOffset: 16 + bitWidth: 1 diff --git a/devices/patches/tim/v2/add_uifcpy.yaml b/devices/patches/tim/v2/add_uifcpy.yaml new file mode 100644 index 000000000..e28713b54 --- /dev/null +++ b/devices/patches/tim/v2/add_uifcpy.yaml @@ -0,0 +1,10 @@ +CNT: + _add: + UIFCPY: + description: > + UIF copy + This bit is a read-only copy of the UIF bit of the TIMx_ISR register. + If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0 + bitOffset: 31 + bitWidth: 1 + access: read-only diff --git a/devices/patches/tim/v2/arr_20bit.yaml b/devices/patches/tim/v2/arr_20bit.yaml new file mode 100644 index 000000000..af2f7f37e --- /dev/null +++ b/devices/patches/tim/v2/arr_20bit.yaml @@ -0,0 +1,4 @@ +ARR: + _modify: + ARR: + bitWidth: 20 diff --git a/devices/patches/tim/v2/g0_tim1_ccmr_input.yaml b/devices/patches/tim/v2/g0_tim1_ccmr_input.yaml new file mode 100644 index 000000000..6acd0c847 --- /dev/null +++ b/devices/patches/tim/v2/g0_tim1_ccmr_input.yaml @@ -0,0 +1,38 @@ +CCMR1_Input: + _delete: OC* + _add: + IC1PSC: + description: Input capture 1 prescaler + bitOffset: 2 + bitWidth: 2 + IC1F: + description: Input capture 1 filter + bitOffset: 4 + bitWidth: 4 + IC2PSC: + description: Input capture 2 prescaler + bitOffset: 10 + bitWidth: 2 + IC2F: + description: Input capture 2 filter + bitOffset: 12 + bitWidth: 4 +CCMR2_Input: + _delete: OC* + _add: + IC3PSC: + description: Input capture 3 prescaler + bitOffset: 2 + bitWidth: 2 + IC3F: + description: Input capture 3 filter + bitOffset: 4 + bitWidth: 4 + IC4PSC: + description: Input capture 4 prescaler + bitOffset: 10 + bitWidth: 2 + IC4F: + description: Input capture 4 filter + bitOffset: 12 + bitWidth: 4 diff --git a/devices/patches/tim/v2/oc1m.yaml b/devices/patches/tim/v2/oc1m.yaml new file mode 100644 index 000000000..795d73475 --- /dev/null +++ b/devices/patches/tim/v2/oc1m.yaml @@ -0,0 +1,6 @@ +CCMR1_Output: + _modify: + OC1M1: + name: OC1M + OC1M2: + name: OC1M_3 diff --git a/devices/patches/tim/v2/oc1m1.yaml b/devices/patches/tim/v2/oc1m1.yaml new file mode 100644 index 000000000..113b68818 --- /dev/null +++ b/devices/patches/tim/v2/oc1m1.yaml @@ -0,0 +1,4 @@ +CCMR1_Output: + _modify: + OC1M1: + name: OC1M diff --git a/devices/patches/tim/v2/oc2m.yaml b/devices/patches/tim/v2/oc2m.yaml new file mode 100644 index 000000000..6c95b696d --- /dev/null +++ b/devices/patches/tim/v2/oc2m.yaml @@ -0,0 +1,6 @@ +CCMR1_Output: + _modify: + OC2M1: + name: OC2M + OC2M2: + name: OC2M_3 diff --git a/devices/patches/tim/v2/oc3m.yaml b/devices/patches/tim/v2/oc3m.yaml new file mode 100644 index 000000000..d274c5328 --- /dev/null +++ b/devices/patches/tim/v2/oc3m.yaml @@ -0,0 +1,10 @@ +CCMR2_Output: + _modify: + OC3M1: + name: OC3M + OC3M2: + name: OC3M_3 + OC4M1: + name: OC4M + OC4M2: + name: OC4M_3 diff --git a/devices/patches/tim/v2/oc4m_bit3.yaml b/devices/patches/tim/v2/oc4m_bit3.yaml new file mode 100644 index 000000000..93355e9a9 --- /dev/null +++ b/devices/patches/tim/v2/oc4m_bit3.yaml @@ -0,0 +1,4 @@ +CCMR2_Output: + _modify: + OC4M_4: + name: OC4M_3 diff --git a/devices/patches/tim/v2/oc5m.yaml b/devices/patches/tim/v2/oc5m.yaml new file mode 100644 index 000000000..35027756b --- /dev/null +++ b/devices/patches/tim/v2/oc5m.yaml @@ -0,0 +1,10 @@ +CCMR3_Output: + _modify: + OC5M1: + name: OC5M + OC5M2: + name: OC5M_3 + OC6M1: + name: OC6M + OC6M2: + name: OC6M_3 diff --git a/devices/patches/tim/v2/oc5m_bit3.yaml b/devices/patches/tim/v2/oc5m_bit3.yaml new file mode 100644 index 000000000..e9de98f3b --- /dev/null +++ b/devices/patches/tim/v2/oc5m_bit3.yaml @@ -0,0 +1,8 @@ +CCMR3_Output: + _modify: + "OC5M3,OC5M_bit3,OC5M_1": + name: OC5M_3 + bitWidth: 1 + "OC6M3,OC6M_bit3,OC6M_1": + name: OC6M_3 + bitWidth: 1 diff --git a/devices/patches/tim/v2/ocm1_bit3.yaml b/devices/patches/tim/v2/ocm1_bit3.yaml new file mode 100644 index 000000000..05363821f --- /dev/null +++ b/devices/patches/tim/v2/ocm1_bit3.yaml @@ -0,0 +1,6 @@ +CCMR1_Output: + _modify: + "OC1M_bit3,OC1M_1": + name: OC1M_3 + "OC2M_bit3,OC2M_1": + name: OC2M_3 diff --git a/devices/patches/tim/v2/ocm_bit3.yaml b/devices/patches/tim/v2/ocm_bit3.yaml new file mode 100644 index 000000000..f82832d70 --- /dev/null +++ b/devices/patches/tim/v2/ocm_bit3.yaml @@ -0,0 +1,8 @@ +_include: ocm1_bit3.yaml + +CCMR2_Output: + _modify: + "OC3M_bit3,OC3M_1": + name: OC3M_3 + "OC4M_bit3,OC4M_1": + name: OC4M_3 diff --git a/devices/patches/tim/v2/tim12_from_tim2.yaml b/devices/patches/tim/v2/tim12_from_tim2.yaml new file mode 100644 index 000000000..405ac0540 --- /dev/null +++ b/devices/patches/tim/v2/tim12_from_tim2.yaml @@ -0,0 +1,39 @@ +_delete: + - CCMR2* + - CCR[34] + - DCR + - DMAR + - AF? + +CR1: + _delete: [CMS, DIR] + +CR2: + _delete: CCDS + +SMCR: + _delete: [ETP, ECE, ETPS, ETF] + +DIER: + _delete: + - TDE + - CC?DE + - UDE + - CC[34]IE + +SR: + _delete: + - CC[34]OF + - CC[34]IF + +EGR: + _delete: + - CC[34]G + +CCER: + _delete: + - CC[34]* + +TISEL: + _delete: + - TI[34]SEL diff --git a/devices/patches/tim/v2/tim13_from_tim2.yaml b/devices/patches/tim/v2/tim13_from_tim2.yaml new file mode 100644 index 000000000..4b8dfcc6a --- /dev/null +++ b/devices/patches/tim/v2/tim13_from_tim2.yaml @@ -0,0 +1,48 @@ +_delete: + - CR2 + - SMCR + - CCMR2* + - CCR[234] + - DCR + - DMAR + - AF? + +CR1: + _delete: [CMS, DIR] + +DIER: + _delete: + - TDE + - CC?DE + - UDE + - TIE + - CC[234]IE + +SR: + _delete: + - CC[234]OF + - TIF + - CC[234]IF + +EGR: + _delete: + - TG + - CC[234]G + +CCMR1_Input: + _delete: + - IC2* + - CC2S + +CCMR1_Output: + _delete: + - OC2* + - CC2S + +CCER: + _delete: + - CC[234]* + +TISEL: + _delete: + - TI[234]SEL diff --git a/devices/patches/tim/v2/tim_20bit.yaml b/devices/patches/tim/v2/tim_20bit.yaml new file mode 100644 index 000000000..103a375d1 --- /dev/null +++ b/devices/patches/tim/v2/tim_20bit.yaml @@ -0,0 +1,12 @@ +CNT: + _modify: + CNT: + bitWidth: 16 +ARR: + _modify: + ARR: + bitWidth: 20 +CCR?: + _modify: + CCR?: + bitWidth: 20 diff --git a/devices/patches/tim/v2/tim_32bit.yaml b/devices/patches/tim/v2/tim_32bit.yaml new file mode 100644 index 000000000..78d6be842 --- /dev/null +++ b/devices/patches/tim/v2/tim_32bit.yaml @@ -0,0 +1,13 @@ +CNT: + _modify: + CNT: + bitWidth: 32 +ARR: + _modify: + ARR: + bitWidth: 32 +CCR?: + _modify: + CCR?: + name: CCR + bitWidth: 32 diff --git a/devices/patches/tim/v2/uifremap_fix.yaml b/devices/patches/tim/v2/uifremap_fix.yaml new file mode 100644 index 000000000..0b20c21ed --- /dev/null +++ b/devices/patches/tim/v2/uifremap_fix.yaml @@ -0,0 +1,7 @@ +CR1: + _delete: UIFREMAP + _add: + UIFREMAP: + description: UIF status bit remapping + bitOffset: 11 + bitWidth: 1 diff --git a/devices/patches/tim/v3/add_dithen.yaml b/devices/patches/tim/v3/add_dithen.yaml new file mode 100644 index 000000000..dd87fe201 --- /dev/null +++ b/devices/patches/tim/v3/add_dithen.yaml @@ -0,0 +1,6 @@ +CR1: + _add: + DITHEN: + description: Dithering Enable + bitOffset: 12 + bitWidth: 1 diff --git a/devices/patches/ucpd/cfgr_missing_r.yaml b/devices/patches/ucpd/cfgr_missing_r.yaml new file mode 100644 index 000000000..fea5056f4 --- /dev/null +++ b/devices/patches/ucpd/cfgr_missing_r.yaml @@ -0,0 +1,7 @@ +_modify: + CFG1: + name: CFGR1 + CFG2: + name: CFGR2 + ?~CFG3: + name: CFGR3 diff --git a/devices/patches/ucpd/rxordseten_split.yaml b/devices/patches/ucpd/rxordseten_split.yaml new file mode 100644 index 000000000..4bbfdc5ef --- /dev/null +++ b/devices/patches/ucpd/rxordseten_split.yaml @@ -0,0 +1,39 @@ +CFGR1: + _delete: RXORDSETEN + _add: + RXORDSETEN0: + description: SOP detection + bitOffset: 20 + bitWidth: 1 + RXORDSETEN1: + description: SOP' detection + bitOffset: 21 + bitWidth: 1 + RXORDSETEN2: + description: SOP'' detection + bitOffset: 22 + bitWidth: 1 + RXORDSETEN3: + description: Hard Reset detection + bitOffset: 23 + bitWidth: 1 + RXORDSETEN4: + description: Cable Detect reset + bitOffset: 24 + bitWidth: 1 + RXORDSETEN5: + description: SOP'_Debug + bitOffset: 25 + bitWidth: 1 + RXORDSETEN6: + description: SOP'' Debug + bitOffset: 26 + bitWidth: 1 + RXORDSETEN7: + description: "SOP extension #1" + bitOffset: 27 + bitWidth: 1 + RXORDSETEN8: + description: "SOP extension #2" + bitOffset: 28 + bitWidth: 1 diff --git a/devices/patches/ucpd/tx_rx_missing_r.yaml b/devices/patches/ucpd/tx_rx_missing_r.yaml new file mode 100644 index 000000000..81a237e3d --- /dev/null +++ b/devices/patches/ucpd/tx_rx_missing_r.yaml @@ -0,0 +1,13 @@ +_modify: + TX_ORDSET: + name: TX_ORDSETR + TX_PAYSZ: + name: TX_PAYSZR + RX_ORDSET: + name: RX_ORDSETR + RX_PAYSZ: + name: RX_PAYSZR + RX_ORDEXT1: + name: RX_ORDEXTR1 + RX_ORDEXT2: + name: RX_ORDEXTR2 diff --git a/devices/patches/usart/add_udr.yaml b/devices/patches/usart/add_udr.yaml new file mode 100644 index 000000000..7118f2233 --- /dev/null +++ b/devices/patches/usart/add_udr.yaml @@ -0,0 +1,7 @@ +ISR: + _add: + UDR: + description: "SPI slave underrun error flag\nIn Slave transmission mode, this flag is set when the first clock pulse for data transmission appears while the software has not yet loaded any value into USART_TDR. This flag is reset by setting UDRCF bit in the USART_ICR register.\nNote: If the USART does not support the SPI slave mode, this bit is reserved and kept at reset value. Refer to ." + bitOffset: 13 + bitWidth: 1 + access: read-only diff --git a/devices/patches/usart/dedt0.yaml b/devices/patches/usart/dedt0.yaml new file mode 100644 index 000000000..fcc6af8fb --- /dev/null +++ b/devices/patches/usart/dedt0.yaml @@ -0,0 +1,4 @@ +CR1: + _modify: + DEDT0: + name: DEDT diff --git a/devices/patches/usart/f4_add_UART_GTPR.yaml b/devices/patches/usart/f4_add_UART_GTPR.yaml new file mode 100644 index 000000000..372e97ba1 --- /dev/null +++ b/devices/patches/usart/f4_add_UART_GTPR.yaml @@ -0,0 +1,11 @@ +_add: + GTPR: + description: Guard Time and Prescaler Register + addressOffset: 0x18 + access: read-write + size: 16 + fields: + PSC: + description: IrDA Low-Power pulse width peripheral clock prescaler + bitOffset: 0 + bitWidth: 8 diff --git a/devices/patches/usart/g0.yaml b/devices/patches/usart/g0.yaml new file mode 100644 index 000000000..012947cd2 --- /dev/null +++ b/devices/patches/usart/g0.yaml @@ -0,0 +1,21 @@ +CR2: + _delete: + - ADD0_3 + - ADD4_7 + _add: + ADD: + description: Address of the USART node + bitOffset: 24 + bitWidth: 8 + _modify: + TAINV: + name: DATAINV +BRR: + _delete: + - BRR_0_3 + - BRR_4_15 + _add: + BRR: + description: Baud rate + bitOffset: 0 + bitWidth: 16 diff --git a/devices/patches/usart/g0_CR1.yaml b/devices/patches/usart/g0_CR1.yaml new file mode 100644 index 000000000..7c8eaf64c --- /dev/null +++ b/devices/patches/usart/g0_CR1.yaml @@ -0,0 +1,14 @@ +_delete: + - CR1_FIFO_DISABLED + - ISR_FIFO_DISABLED +_modify: + CR1_FIFO_ENABLED: + name: CR1 + ISR_FIFO_ENABLED: + name: ISR +CR1: + _modify: + TXFNFIE: + name: TXEIE + RXFNEIE: + name: RXNEIE diff --git a/devices/patches/usart/merge_BRR_fields.yaml b/devices/patches/usart/merge_BRR_fields.yaml new file mode 100644 index 000000000..dec6ccfbc --- /dev/null +++ b/devices/patches/usart/merge_BRR_fields.yaml @@ -0,0 +1,4 @@ +# Merge BRR fields together +BRR: + _merge: + BRR: "BRR_0_3,BRR_4_15,DIV_Mantissa,DIV_Fraction" diff --git a/devices/patches/usart/merge_CR1_DEATx_fields.yaml b/devices/patches/usart/merge_CR1_DEATx_fields.yaml new file mode 100644 index 000000000..c8488a537 --- /dev/null +++ b/devices/patches/usart/merge_CR1_DEATx_fields.yaml @@ -0,0 +1,5 @@ +# Merge USART CR1 DEATx fields + +CR1: + _merge: + - DEAT* diff --git a/devices/patches/usart/merge_CR1_DEDTx_fields.yaml b/devices/patches/usart/merge_CR1_DEDTx_fields.yaml new file mode 100644 index 000000000..9351563bf --- /dev/null +++ b/devices/patches/usart/merge_CR1_DEDTx_fields.yaml @@ -0,0 +1,5 @@ +# Merge USART CR1 DEDTx fields + +CR1: + _merge: + - DEDT* diff --git a/devices/patches/usart/merge_CR2_ABRMODx_fields.yaml b/devices/patches/usart/merge_CR2_ABRMODx_fields.yaml new file mode 100644 index 000000000..bcaddd6f0 --- /dev/null +++ b/devices/patches/usart/merge_CR2_ABRMODx_fields.yaml @@ -0,0 +1,5 @@ +# Merge USART CR2 ABRMODx fields + +CR2: + _merge: + ABRMOD: ABRMOD* diff --git a/devices/patches/usart/merge_CR2_ADDx_fields.yaml b/devices/patches/usart/merge_CR2_ADDx_fields.yaml new file mode 100644 index 000000000..a91eac42b --- /dev/null +++ b/devices/patches/usart/merge_CR2_ADDx_fields.yaml @@ -0,0 +1,5 @@ +# Merge USART CR2 ADDx fields + +CR2: + _merge: + ADD: "ADD[04],ADD[0347]_[0347]" diff --git a/devices/patches/usart/merge_CR3_WUS_field.yaml b/devices/patches/usart/merge_CR3_WUS_field.yaml new file mode 100644 index 000000000..bbbe69ef3 --- /dev/null +++ b/devices/patches/usart/merge_CR3_WUS_field.yaml @@ -0,0 +1,3 @@ +CR3: + _merge: + - WUS* diff --git a/devices/patches/usart/rename_CR1_ISR_enabled_disabled.yaml b/devices/patches/usart/rename_CR1_ISR_enabled_disabled.yaml new file mode 100644 index 000000000..81205d754 --- /dev/null +++ b/devices/patches/usart/rename_CR1_ISR_enabled_disabled.yaml @@ -0,0 +1,18 @@ +_modify: + "CR1_enabled,CR1_ENABLED,CR1": + name: CR1 + "ISR_enabled,ISR_ENABLED,ISR": + name: ISR +_delete: + - "*CR1_disabled" + - "*CR1_DISABLED" + - "*CR1_ALTERNATE*" + - "*ISR_disabled" + - "*ISR_DISABLED" + - "*ISR_ALTERNATE*" +CR1: + _modify: + TXFNFIE: + name: TXEIE + RXFNEIE: + name: RXNEIE diff --git a/devices/patches/usart/rename_CR1_M0_field.yaml b/devices/patches/usart/rename_CR1_M0_field.yaml new file mode 100644 index 000000000..97225ffa1 --- /dev/null +++ b/devices/patches/usart/rename_CR1_M0_field.yaml @@ -0,0 +1,6 @@ +# Rename USART CR1 M to M0 + +CR1: + _modify: + M: + name: M0 diff --git a/devices/patches/usart/rename_CR2_DATAINV_field.yaml b/devices/patches/usart/rename_CR2_DATAINV_field.yaml new file mode 100644 index 000000000..4f774a1a8 --- /dev/null +++ b/devices/patches/usart/rename_CR2_DATAINV_field.yaml @@ -0,0 +1,7 @@ +# Rename USART CR2 DATAINV field +# Other families has it. + +CR2: + _modify: + TAINV: + name: DATAINV diff --git a/devices/patches/usart/rename_CR3_SCARCNT_field.yaml b/devices/patches/usart/rename_CR3_SCARCNT_field.yaml new file mode 100644 index 000000000..36a6b66c4 --- /dev/null +++ b/devices/patches/usart/rename_CR3_SCARCNT_field.yaml @@ -0,0 +1,6 @@ +# Rename USART CR3 SCARNT2_0 to SCARCNT + +CR3: + _modify: + SCARCNT2_0: + name: SCARCNT diff --git a/devices/patches/usart/tcbgtc.yaml b/devices/patches/usart/tcbgtc.yaml new file mode 100644 index 000000000..2119899d8 --- /dev/null +++ b/devices/patches/usart/tcbgtc.yaml @@ -0,0 +1,4 @@ +ICR: + _modify: + TCBGTC: + name: TCBGTCF diff --git a/devices/patches/usart/v1.yaml b/devices/patches/usart/v1.yaml new file mode 100644 index 000000000..1f92ba1b5 --- /dev/null +++ b/devices/patches/usart/v1.yaml @@ -0,0 +1,5 @@ +_modify: + SR: + resetValue: 0xC0 + "?*": + size: 16 diff --git a/devices/patches/usb/add_bcdr.yaml b/devices/patches/usb/add_bcdr.yaml new file mode 100644 index 000000000..2a9cd41fd --- /dev/null +++ b/devices/patches/usb/add_bcdr.yaml @@ -0,0 +1,53 @@ +# Battery Charging Detector register is missing so add it +_add: + _registers: + BCDR: + description: Battery Charging Detector + addressOffset: 0x58 + resetValue: 0x0000 + fields: + DPPU: + description: DP pull-up control + access: read-write + bitOffset: 15 + bitWidth: 1 + PS2DET: + description: DM pull-up detection status + access: read-only + bitOffset: 7 + bitWidth: 1 + SDET: + description: Secondary detection status + access: read-only + bitOffset: 6 + bitWidth: 1 + PDET: + description: Primary detection status + access: read-only + bitOffset: 5 + bitWidth: 1 + DCDET: + description: Data contact detection status + access: read-only + bitOffset: 4 + bitWidth: 1 + SDEN: + description: Secondary detection mode enable + access: read-write + bitOffset: 3 + bitWidth: 1 + PDEN: + description: Primary detection mode enable + access: read-write + bitOffset: 2 + bitWidth: 1 + DCDEN: + description: Data contact detection mode enable + access: read-write + bitOffset: 1 + bitWidth: 1 + BCDEN: + description: Battery charging detector mode enable + access: read-write + bitOffset: 0 + bitWidth: 1 diff --git a/devices/patches/usb/merge_add.yaml b/devices/patches/usb/merge_add.yaml new file mode 100644 index 000000000..80b624713 --- /dev/null +++ b/devices/patches/usb/merge_add.yaml @@ -0,0 +1,7 @@ +DADDR: + _delete: ["ADD,ADD?"] + _add: + ADD: + description: Device address + bitOffset: 0 + bitWidth: 7 diff --git a/devices/patches/usb/rename_EPxR_EPTYPE_field.yaml b/devices/patches/usb/rename_EPxR_EPTYPE_field.yaml new file mode 100644 index 000000000..4d5aad165 --- /dev/null +++ b/devices/patches/usb/rename_EPxR_EPTYPE_field.yaml @@ -0,0 +1,6 @@ +# Rename EPTYPE to EP_TYPE + +EP*R: + _modify: + EPTYPE: + name: EP_TYPE diff --git a/devices/patches/usb/rename_USB_FS_peripheral_to_USB.yaml b/devices/patches/usb/rename_USB_FS_peripheral_to_USB.yaml new file mode 100644 index 000000000..5c7998f46 --- /dev/null +++ b/devices/patches/usb/rename_USB_FS_peripheral_to_USB.yaml @@ -0,0 +1,11 @@ +# Rename USB_FS peripheral to USB peripheral +# Allow all devices with USB to have same peripheral name + +_modify: + _peripherals: + USB_FS*: + name: USB + groupName: USB + USB_DRD_FS: + name: USB + groupName: USB diff --git a/devices/patches/usb_otg/epena_stall.yaml b/devices/patches/usb_otg/epena_stall.yaml new file mode 100644 index 000000000..050f9cc38 --- /dev/null +++ b/devices/patches/usb_otg/epena_stall.yaml @@ -0,0 +1,7 @@ +"DIEPCTL*,DOEPCTL*": + _modify: + EPENA: + access: read-write + "Stall,STALL": + name: STALL + description: STALL handshake diff --git a/devices/patches/usb_otg/fs_fixes_446_469.yaml b/devices/patches/usb_otg/fs_fixes_446_469.yaml new file mode 100644 index 000000000..6bffef13c --- /dev/null +++ b/devices/patches/usb_otg/fs_fixes_446_469.yaml @@ -0,0 +1,19 @@ +GCCFG: + _delete: + - DCDET + - PDET + - SDET + - PS2DET + - BCDEN + - DCDEN + - PDEN + - SDEN + +_delete: + - "*GI2CCTL" + - "*GPWRDN" + - "*GADPCTL" + +_modify: + CID: + resetValue: 0x2000 diff --git a/devices/patches/usb_otg/fs_host_addr.yaml b/devices/patches/usb_otg/fs_host_addr.yaml new file mode 100644 index 000000000..9983c1558 --- /dev/null +++ b/devices/patches/usb_otg/fs_host_addr.yaml @@ -0,0 +1,17 @@ +_modify: + HCCHAR8: { addressOffset: 0x200 } + HCINT8: { addressOffset: 0x208 } + HCINTMSK8: { addressOffset: 0x20C } + HCTSIZ8: { addressOffset: 0x210 } + HCCHAR9: { addressOffset: 0x220 } + HCINT9: { addressOffset: 0x228 } + HCINTMSK9: { addressOffset: 0x22C } + HCTSIZ9: { addressOffset: 0x230 } + HCCHAR10: { addressOffset: 0x240 } + HCINT10: { addressOffset: 0x248 } + HCINTMSK10: { addressOffset: 0x24C } + HCTSIZ10: { addressOffset: 0x250 } + HCCHAR11: { addressOffset: 0x260 } + HCINT11: { addressOffset: 0x268 } + HCINTMSK11: { addressOffset: 0x26C } + HCTSIZ11: { addressOffset: 0x270 } diff --git a/devices/patches/usb_otg/fs_l4+_device.yaml b/devices/patches/usb_otg/fs_l4+_device.yaml new file mode 100644 index 000000000..ed659c4d0 --- /dev/null +++ b/devices/patches/usb_otg/fs_l4+_device.yaml @@ -0,0 +1,79 @@ +DCFG: + _add: + ERRATIM: + description: Erratic error interrupt mask + bitOffset: 15 + bitWidth: 1 + +DCTL: + _add: + DSBESLRJCT: + description: Deep sleep BESL reject + bitOffset: 18 + bitWidth: 1 + access: read-write + +DSTS: + _add: + DEVLNSTS: + description: Device line status + bitOffset: 22 + bitWidth: 2 + +DIEPMSK: + _add: + NAKM: + description: NAK interrupt mask + bitOffset: 13 + bitWidth: 1 + +DOEPMSK: + _add: + OUTPKTERRM: + description: Out packet error mask + bitOffset: 8 + bitWidth: 1 + BERRM: + description: Babble error interrupt mask + bitOffset: 12 + bitWidth: 1 + NAKMSK: + description: NAK interrupt mask + bitOffset: 13 + bitWidth: 1 + +DIEPINT?: + _add: + INEPNM: + description: IN token received with EP mismatch + bitOffset: 5 + bitWidth: 1 + access: read-write + PKTDRPSTS: + description: Packet dropped status + bitOffset: 11 + bitWidth: 1 + access: read-write + NAK: + description: NAK input + bitOffset: 13 + bitWidth: 1 + access: read-write + +DOEPINT?: + _delete: + - B2BSTUP + + _add: + STSPHSRX: + description: Status phase received for control write + bitOffset: 5 + bitWidth: 1 + BERR: + description: Babble error interrupt + bitOffset: 12 + bitWidth: 1 + NAK: + description: NAK input + bitOffset: 13 + bitWidth: 1 diff --git a/devices/patches/usb_otg/fs_l4+_global.yaml b/devices/patches/usb_otg/fs_l4+_global.yaml new file mode 100644 index 000000000..923b34a2a --- /dev/null +++ b/devices/patches/usb_otg/fs_l4+_global.yaml @@ -0,0 +1,320 @@ +GOTGCTL: + _add: + VBVALOEN: + description: VBUS valid override enable + bitOffset: 2 + bitWidth: 1 + access: read-write + VBVALOVAL: + description: VBUS valid override value + bitOffset: 3 + bitWidth: 1 + access: read-write + AVALOEN: + description: A-peripheral session valid override enable + bitOffset: 4 + bitWidth: 1 + access: read-write + AVALOVAL: + description: A-peripheral session valid override value + bitOffset: 5 + bitWidth: 1 + access: read-write + BVALOEN: + description: B-peripheral session valid override enable + bitOffset: 6 + bitWidth: 1 + access: read-write + BVALOVAL: + description: B-peripheral session valid override value + bitOffset: 7 + bitWidth: 1 + access: read-write + EHEN: + description: Embedded host enable + bitOffset: 12 + bitWidth: 1 + access: read-write + OTGVER: + description: OTG version + bitOffset: 20 + bitWidth: 1 + access: read-write + CURMOD: + description: Current mode of operation + bitOffset: 21 + bitWidth: 1 + access: read-only + +GAHBCFG: + _modify: + GINT: + name: GINTMSK + +GUSBCFG: + _delete: + - CTXPKT + +GINTSTS: + _add: + RSTDET: + description: Reset detected interrupt + bitOffset: 23 + bitWidth: 1 + LPMINT: + description: LPM interrupt + bitOffset: 27 + bitWidth: 1 + +GINTMSK: + _add: + RSTDETM: + description: Reset detected interrupt mask + bitOffset: 23 + bitWidth: 1 + LPMINTM: + description: LPM interrupt mask + bitOffset: 27 + bitWidth: 1 + +GCCFG: + _delete: + - VBUSASEN + - VBUSBSEN + - SOFOUTEN + + _add: + DCDET: + description: Data contact detection (DCD) status + bitOffset: 0 + bitWidth: 1 + access: read-only + PDET: + description: Primary detection (PD) status + bitOffset: 1 + bitWidth: 1 + access: read-only + SDET: + description: Secondary detection (SD) status + bitOffset: 2 + bitWidth: 1 + access: read-only + PS2DET: + description: DM pull-up detection status + bitOffset: 3 + bitWidth: 1 + access: read-only + BCDEN: + description: Battery charging detector (BCD) enable + bitOffset: 17 + bitWidth: 1 + access: read-write + DCDEN: + description: Data contact detection (DCD) mode enable + bitOffset: 18 + bitWidth: 1 + access: read-write + PDEN: + description: Primary detection (PD) mode enable + bitOffset: 19 + bitWidth: 1 + access: read-write + SDEN: + description: Secondary detection (SD) mode enable + bitOffset: 20 + bitWidth: 1 + access: read-write + VBDEN: + description: USB VBUS detection enable + bitOffset: 21 + bitWidth: 1 + access: read-write + +GRXSTSR_Device: + _add: + STSPHST: + description: Status phase start + bitOffset: 27 + bitWidth: 1 + +GRXSTSP_Device: + _add: + STSPHST: + description: ?? + bitOffset: 27 + bitWidth: 1 + +_add: + GLPMCFG: + description: OTG core LPM configuration register + addressOffset: 0x54 + resetValue: 0x0 + fields: + LPMEN: + description: LPM support enable + bitOffset: 0 + bitWidth: 1 + access: read-write + LPMACK: + description: LPM token acknowledge enable + bitOffset: 1 + bitWidth: 1 + access: read-write + BESL: + description: Best effort service latency + bitOffset: 2 + bitWidth: 4 + access: read-write + REMWAKE: + description: bRemoteWake value + bitOffset: 6 + bitWidth: 1 + access: read-write + L1SSEN: + description: L1 Shallow Sleep enable + bitOffset: 7 + bitWidth: 1 + access: read-write + BESLTHRS: + description: BESL threshold + bitOffset: 8 + bitWidth: 4 + access: read-write + L1DSEN: + description: L1 deep sleep enable + bitOffset: 12 + bitWidth: 1 + access: read-write + LPMRSP: + description: LPM response + bitOffset: 13 + bitWidth: 2 + access: read-only + SLPSTS: + description: Port sleep status + bitOffset: 15 + bitWidth: 1 + access: read-only + L1RSMOK: + description: Sleep state resume OK + bitOffset: 16 + bitWidth: 1 + access: read-only + LPMCHIDX: + description: LPM Channel Index + bitOffset: 17 + bitWidth: 4 + access: read-write + LPMRCNT: + description: LPM retry count + bitOffset: 21 + bitWidth: 3 + SNDLPM: + description: Send LPM transaction + bitOffset: 24 + bitWidth: 1 + access: read-write + LPMRCNTSTS: + description: LPM retry count status + bitOffset: 25 + bitWidth: 3 + access: read-only + ENBESL: + description: Enable best effort service latency + bitOffset: 28 + bitWidth: 1 + access: read-write + GPWRDN: + description: OTG power down register + addressOffset: 0x58 + resetValue: 0x0 + access: read-write + fields: + ADPMEN: + description: ADP module enable + bitOffset: 0 + bitWidth: 1 + ADPIF: + description: ADP interrupt flag + bitOffset: 23 + bitWidth: 1 + GADPCTL: + description: OTG ADP timer, control and status register + addressOffset: 0x60 + resetValue: 0x0 + fields: + PRBDSCHG: + description: Probe discharge + bitOffset: 0 + bitWidth: 2 + access: read-write + PRBDELTA: + description: Probe delta + bitOffset: 2 + bitWidth: 2 + access: read-write + PRBPER: + description: Probe period + bitOffset: 0 + bitWidth: 4 + access: read-write + RTIM: + description: Ramp time + bitOffset: 6 + bitWidth: 11 + access: read-only + ENAPRB: + description: Enable probe + bitOffset: 17 + bitWidth: 1 + access: read-write + ENASNS: + description: Enable sense + bitOffset: 18 + bitWidth: 1 + access: read-write + ADPRST: + description: ADP reset + bitOffset: 19 + bitWidth: 1 + access: read-write + ADPEN: + description: ADP enable + bitOffset: 20 + bitWidth: 1 + access: read-write + ADPPRBIF: + description: ADP probe interrupt flag + bitOffset: 21 + bitWidth: 1 + access: read-write + ADPSNSIF: + description: ADP sense interrupt flag + bitOffset: 22 + bitWidth: 1 + access: read-write + ADPTOIF: + description: ADP timeout interrupt flag + bitOffset: 23 + bitWidth: 1 + access: read-write + ADPPRBIM: + description: ADP probe interrupt mask + bitOffset: 24 + bitWidth: 1 + access: read-write + ADPSNSIM: + description: ADP sense interrupt mask + bitOffset: 25 + bitWidth: 1 + access: read-write + ADPTOIM: + description: ADP timeout interrupt mask + bitOffset: 26 + bitWidth: 1 + access: read-write + AR: + description: Access request + bitOffset: 27 + bitWidth: 2 + access: read-write diff --git a/devices/patches/usb_otg/fs_l4+_host.yaml b/devices/patches/usb_otg/fs_l4+_host.yaml new file mode 100644 index 000000000..8a9cd6777 --- /dev/null +++ b/devices/patches/usb_otg/fs_l4+_host.yaml @@ -0,0 +1,17 @@ +HFIR: + _add: + RLDCTRL: + description: Reload control + bitOffset: 16 + bitWidth: 1 + +HCINTMSK*: + _delete: + - NYET + +HCTSIZ*: + _add: + DOPNG: + description: Do Ping + bitOffset: 31 + bitWidth: 1 diff --git a/devices/patches/usb_otg/fs_l4+_pwrclk.yaml b/devices/patches/usb_otg/fs_l4+_pwrclk.yaml new file mode 100644 index 000000000..59b495c2e --- /dev/null +++ b/devices/patches/usb_otg/fs_l4+_pwrclk.yaml @@ -0,0 +1,17 @@ +PCGCCTL: + _add: + ENL1GTG: + description: Enable sleep clock gating + bitOffset: 5 + bitWidth: 1 + access: read-write + PHYSLEEP: + description: PHY in Sleep + bitOffset: 6 + bitWidth: 1 + access: read-only + SUSP: + description: Deep Sleep + bitOffset: 7 + bitWidth: 1 + access: read-only diff --git a/devices/patches/usb_otg/fs_v1_device.yaml b/devices/patches/usb_otg/fs_v1_device.yaml new file mode 100644 index 000000000..98348c102 --- /dev/null +++ b/devices/patches/usb_otg/fs_v1_device.yaml @@ -0,0 +1,8 @@ +DAINTMSK: + _modify: + OEPINT: + name: OEPM + description: OUT EP interrupt mask bits + +_include: + - epena_stall.yaml diff --git a/devices/patches/usb_otg/fs_v1_device_ext.yaml b/devices/patches/usb_otg/fs_v1_device_ext.yaml new file mode 100644 index 000000000..f44adec13 --- /dev/null +++ b/devices/patches/usb_otg/fs_v1_device_ext.yaml @@ -0,0 +1,44 @@ +_copy: + DIEPCTL4: + _from: DIEPCTL1 + addressOffset: 0x180 + DIEPINT4: + _from: DIEPINT1 + addressOffset: 0x188 + DIEPTSIZ4: + _from: DIEPTSIZ1 + addressOffset: 0x190 + DTXFSTS4: + _from: DTXFSTS1 + addressOffset: 0x198 + DIEPCTL5: + _from: DIEPCTL1 + addressOffset: 0x1A0 + DIEPINT5: + _from: DIEPINT1 + addressOffset: 0x1A8 + DIEPTSIZ5: + _from: DIEPTSIZ1 + addressOffset: 0x1B0 + DTXFSTS5: + _from: DTXFSTS1 + addressOffset: 0x1B8 + + DOEPCTL4: + _from: DOEPCTL1 + addressOffset: 0x380 + DOEPINT4: + _from: DOEPINT1 + addressOffset: 0x388 + DOEPTSIZ4: + _from: DOEPTSIZ1 + addressOffset: 0x390 + DOEPCTL5: + _from: DOEPCTL1 + addressOffset: 0x3A0 + DOEPINT5: + _from: DOEPINT1 + addressOffset: 0x3A8 + DOEPTSIZ5: + _from: DOEPTSIZ1 + addressOffset: 0x3B0 diff --git a/devices/patches/usb_otg/fs_v1_global.yaml b/devices/patches/usb_otg/fs_v1_global.yaml new file mode 100644 index 000000000..46cf531a6 --- /dev/null +++ b/devices/patches/usb_otg/fs_v1_global.yaml @@ -0,0 +1,80 @@ +GINTMSK: + _modify: + PRTIM: + access: read-write + +GRXSTSR_Host: + _delete: + - FRMNUM + _modify: + EPNUM: + name: CHNUM + description: Channel number +_add: + GRXSTSP_Device: + description: OTG status read and pop (device mode) + addressOffset: 0x20 + size: 32 + resetValue: 0x00000000 + access: read-only + fields: + FRMNUM: + description: Frame number + bitOffset: 21 + bitWidth: 4 + PKTSTS: + description: Packet status + bitOffset: 17 + bitWidth: 4 + DPID: + description: Data PID + bitOffset: 15 + bitWidth: 2 + BCNT: + description: Byte count + bitOffset: 4 + bitWidth: 11 + EPNUM: + description: Endpoint number + bitOffset: 0 + bitWidth: 4 + GRXSTSP_Host: + description: OTG status read and pop (host mode) + addressOffset: 0x20 + size: 32 + resetValue: 0x00000000 + access: read-only + alternateRegister: GRXSTSP_Device + fields: + PKTSTS: + description: Packet status + bitOffset: 17 + bitWidth: 4 + DPID: + description: Data PID + bitOffset: 15 + bitWidth: 2 + BCNT: + description: Byte count + bitOffset: 4 + bitWidth: 11 + CHNUM: + description: Channel number + bitOffset: 0 + bitWidth: 4 +_modify: + GRXSTSR_Host: + description: OTG status debug read (host mode) + addressOffset: 0x1C + size: 32 + resetValue: 0x00000000 + access: read-only + alternateRegister: GRXSTSR_Device + GNPTXFSIZ_Device: + name: DIEPTXF0 + displayName: DIEPTXF0 + + GNPTXFSIZ_Host: + name: HNPTXFSIZ + displayName: HNPTXFSIZ + alternateRegister: DIEPTXF0 diff --git a/devices/patches/usb_otg/fs_v1_global_ext.yaml b/devices/patches/usb_otg/fs_v1_global_ext.yaml new file mode 100644 index 000000000..d5cd63db2 --- /dev/null +++ b/devices/patches/usb_otg/fs_v1_global_ext.yaml @@ -0,0 +1,7 @@ +_copy: + DIEPTXF4: + _from: DIEPTXF1 + addressOffset: 0x110 + DIEPTXF5: + _from: DIEPTXF1 + addressOffset: 0x114 diff --git a/devices/patches/usb_otg/fs_v1_host.yaml b/devices/patches/usb_otg/fs_v1_host.yaml new file mode 100644 index 000000000..ec994b51d --- /dev/null +++ b/devices/patches/usb_otg/fs_v1_host.yaml @@ -0,0 +1,4 @@ +HCFG: + _modify: + FSLSS: + access: read-write diff --git a/devices/patches/usb_otg/fs_v1_host_ext.yaml b/devices/patches/usb_otg/fs_v1_host_ext.yaml new file mode 100644 index 000000000..964343955 --- /dev/null +++ b/devices/patches/usb_otg/fs_v1_host_ext.yaml @@ -0,0 +1,49 @@ +_copy: + HCCHAR8: + _from: HCCHAR0 + addressOffset: 0x200 + HCINT8: + _from: HCINT0 + addressOffset: 0x208 + HCINTMSK8: + _from: HCINTMSK0 + addressOffset: 0x20C + HCTSIZ8: + _from: HCTSIZ0 + addressOffset: 0x210 + HCCHAR9: + _from: HCCHAR0 + addressOffset: 0x220 + HCINT9: + _from: HCINT0 + addressOffset: 0x228 + HCINTMSK9: + _from: HCINTMSK0 + addressOffset: 0x22C + HCTSIZ9: + _from: HCTSIZ0 + addressOffset: 0x230 + HCCHAR10: + _from: HCCHAR0 + addressOffset: 0x240 + HCINT10: + _from: HCINT0 + addressOffset: 0x248 + HCINTMSK10: + _from: HCINTMSK0 + addressOffset: 0x24C + HCTSIZ10: + _from: HCTSIZ0 + addressOffset: 0x250 + HCCHAR11: + _from: HCCHAR0 + addressOffset: 0x260 + HCINT11: + _from: HCINT0 + addressOffset: 0x268 + HCINTMSK11: + _from: HCINTMSK0 + addressOffset: 0x26C + HCTSIZ11: + _from: HCTSIZ0 + addressOffset: 0x270 diff --git a/devices/patches/usb_otg/fs_v1_novbussens.yaml b/devices/patches/usb_otg/fs_v1_novbussens.yaml new file mode 100644 index 000000000..cd7215687 --- /dev/null +++ b/devices/patches/usb_otg/fs_v1_novbussens.yaml @@ -0,0 +1,6 @@ +GCCFG: + _add: + NOVBUSSENS: + description: Vbus sensing disable option + bitOffset: 21 + bitWidth: 1 diff --git a/devices/patches/usb_otg/fs_v2_device.yaml b/devices/patches/usb_otg/fs_v2_device.yaml new file mode 100644 index 000000000..32c1f0799 --- /dev/null +++ b/devices/patches/usb_otg/fs_v2_device.yaml @@ -0,0 +1,20 @@ +_modify: + DIEPTSIZ4: + addressOffset: 0x190 + "DIEPTSIZ55,DIEPTSIZ5": + name: DIEPTSIZ5 + "DTXFSTS55,DTXFSTS5": + name: DTXFSTS5 + DOEPCTL4: + addressOffset: 0x380 + DOEPCTL5: + addressOffset: 0x3A0 + +DAINTMSK: + _modify: + OEPINT: + name: OEPM + description: OUT EP interrupt mask bits + +_include: + - epena_stall.yaml diff --git a/devices/patches/usb_otg/fs_v2_global.yaml b/devices/patches/usb_otg/fs_v2_global.yaml new file mode 100644 index 000000000..eb2b4af47 --- /dev/null +++ b/devices/patches/usb_otg/fs_v2_global.yaml @@ -0,0 +1,28 @@ +_modify: + GLPMCFG: + resetValue: 0x0 + GRXSTSR_Host: + alternateRegister: GRXSTSR_Device + GRXSTSP_Host: + alternateRegister: GRXSTSP_Device + DIEPTXF0_Device: + name: DIEPTXF0 + HNPTXFSIZ_Host: + alternateRegister: DIEPTXF0 +GOTGCTL: + _add: + CURMOD: + description: Current mode of operation + bitOffset: 21 + bitWidth: 1 + access: read-only +GINTMSK: + _modify: + PRTIM: + access: read-write +"GRXSTSR_Host,GRXSTSP_Host": + _add: + STSPHST: + description: Status phase start + bitOffset: 27 + bitWidth: 1 diff --git a/devices/patches/usb_otg/fs_v2_host.yaml b/devices/patches/usb_otg/fs_v2_host.yaml new file mode 100644 index 000000000..ec994b51d --- /dev/null +++ b/devices/patches/usb_otg/fs_v2_host.yaml @@ -0,0 +1,4 @@ +HCFG: + _modify: + FSLSS: + access: read-write diff --git a/devices/patches/usb_otg/gotgctl.yaml b/devices/patches/usb_otg/gotgctl.yaml new file mode 100644 index 000000000..e31df499e --- /dev/null +++ b/devices/patches/usb_otg/gotgctl.yaml @@ -0,0 +1,42 @@ +GOTGCTL: + _add: + VBVALOEN: + description: V_BUS valid override enable + bitOffset: 2 + bitWidth: 1 + access: read-write + VBVALOVAL: + description: V_BUS valid override value + bitOffset: 3 + bitWidth: 1 + access: read-write + AVALOEN: + description: A-peripheral session valid override enable + bitOffset: 4 + bitWidth: 1 + access: read-write + AVALOVAL: + description: A-peripheral session valid override value + bitOffset: 5 + bitWidth: 1 + access: read-write + BVALOEN: + description: B-peripheral session valid override enable + bitOffset: 6 + bitWidth: 1 + access: read-write + BVALOVAL: + description: B-peripheral session valid override value + bitOffset: 7 + bitWidth: 1 + access: read-write + OTGVER: + description: OTG version + bitOffset: 20 + bitWidth: 1 + access: read-write + CURMOD: + description: Current mode of operation + bitOffset: 21 + bitWidth: 1 + access: read-only diff --git a/devices/patches/usb_otg/hs_f73_device.yaml b/devices/patches/usb_otg/hs_f73_device.yaml new file mode 100644 index 000000000..713795d1d --- /dev/null +++ b/devices/patches/usb_otg/hs_f73_device.yaml @@ -0,0 +1,21 @@ +_delete: + - DIEPDMA5 + - DIEPDMA9 + - DIEPDMA10 + - DIEPDMA11 + - DIEPDMA12 + - DIEPDMA13 + - DIEPDMA14 + - DIEPDMA15 + - DOEPDMA9 + - DOEPDMA10 + - DOEPDMA11 + - DOEPDMA12 + - DOEPDMA13 + - DOEPDMA14 + - DOEPDMA15 +_copy: + DIEPDMA5: + _from: DIEPDMA1 + description: OTG_HS device endpoint-5 DMA address register + addressOffset: 0x1B4 diff --git a/devices/patches/usb_otg/hs_fixes_446_469.yaml b/devices/patches/usb_otg/hs_fixes_446_469.yaml new file mode 100644 index 000000000..0d9fe2f3e --- /dev/null +++ b/devices/patches/usb_otg/hs_fixes_446_469.yaml @@ -0,0 +1,14 @@ +GCCFG: + _delete: + - DCDET + - PDET + - SDET + - PS2DET + - BCDEN + - DCDEN + - PDEN + - SDEN + +_modify: + CID: + resetValue: 0x2100 diff --git a/devices/patches/usb_otg/hs_v1_device.yaml b/devices/patches/usb_otg/hs_v1_device.yaml new file mode 100644 index 000000000..1af51354e --- /dev/null +++ b/devices/patches/usb_otg/hs_v1_device.yaml @@ -0,0 +1,69 @@ +_delete: + _registers: + - DIEPCTL6 + - DIEPCTL7 + - DIEPINT6 + - DIEPINT7 + - DOEPINT6 + - DOEPINT7 + +_copy: + DIEPDMA0: + _from: DIEPDMA1 + description: OTG_HS device endpoint-0 DMA address register + addressOffset: 0x114 + DOEPCTL4: + _from: DOEPCTL1 + description: device endpoint-4 control register + addressOffset: 0x380 + DOEPCTL5: + _from: DOEPCTL1 + description: device endpoint-5 control register + addressOffset: 0x3A0 + DOEPTSIZ5: + _from: DOEPTSIZ1 + description: OTG_HS device endpoint-5 transfer size register + addressOffset: 0x3B0 + DOEPDMA0: + _from: DIEPDMA1 + description: OTG_HS device endpoint-0 DMA address register + addressOffset: 0x314 + DOEPDMA1: + _from: DIEPDMA1 + description: OTG_HS device endpoint-1 DMA address register + addressOffset: 0x334 + DOEPDMA2: + _from: DIEPDMA1 + description: OTG_HS device endpoint-2 DMA address register + addressOffset: 0x354 + DOEPDMA3: + _from: DIEPDMA1 + description: OTG_HS device endpoint-3 DMA address register + addressOffset: 0x374 + DOEPDMA4: + _from: DIEPDMA1 + description: OTG_HS device endpoint-4 DMA address register + addressOffset: 0x394 + DOEPDMA5: + _from: DIEPDMA1 + description: OTG_HS device endpoint-5 DMA address register + addressOffset: 0x3B4 +_modify: + DIEPDMA1: + addressOffset: 0x134 + DIEPDMA2: + addressOffset: 0x154 + DIEPDMA3: + addressOffset: 0x174 + DIEPDMA4: + addressOffset: 0x194 + DIEPDMA5: + addressOffset: 0x1B4 + + DIEPEACHMSK1: + addressOffset: 0x44 + DOEPEACHMSK1: + addressOffset: 0x84 + +_include: + - epena_stall.yaml diff --git a/devices/patches/usb_otg/hs_v1_f4_host.yaml b/devices/patches/usb_otg/hs_v1_f4_host.yaml new file mode 100644 index 000000000..5dac0f71e --- /dev/null +++ b/devices/patches/usb_otg/hs_v1_f4_host.yaml @@ -0,0 +1,17 @@ +_delete: + - "HCCHAR1[2-5]" + - "HCSPLT1[2-5]" + - "HCINT1[2-5]" + - "HCINTMSK1[2-5]" + - "HCTSIZ1[2-5]" + - "HCDMA1[2-5]" +HCINT0: + _add: + AHBERR: + description: AHB error + bitOffset: 2 + bitWidth: 1 + NYET: + description: Response received interrupt + bitOffset: 6 + bitWidth: 1 diff --git a/devices/patches/usb_otg/hs_v1_global.yaml b/devices/patches/usb_otg/hs_v1_global.yaml new file mode 100644 index 000000000..dadb712c5 --- /dev/null +++ b/devices/patches/usb_otg/hs_v1_global.yaml @@ -0,0 +1,32 @@ +_delete: + _registers: + - DIEPTXF6 + - DIEPTXF7 + +_modify: + GNPTXFSIZ_Host: + name: HNPTXFSIZ + displayName: HNPTXFSIZ + + GNPTXSTS: + name: HNPTXSTS + + TX0FSIZ_Peripheral: + name: DIEPTXF0 + displayName: DIEPTXF0 + alternateRegister: HNPTXFSIZ + + GRXSTSR_Peripheral: + name: GRXSTSR_Device + alternateRegister: GRXSTSR_Host + + GRXSTSP_Peripheral: + name: GRXSTSP_Device + alternateRegister: GRXSTSP_Host + + DIEPTXF3: + addressOffset: 0x10C + DIEPTXF4: + addressOffset: 0x110 + DIEPTXF5: + addressOffset: 0x114 diff --git a/devices/patches/usb_otg/hs_v1_pwrclk.yaml b/devices/patches/usb_otg/hs_v1_pwrclk.yaml new file mode 100644 index 000000000..40ae4ba17 --- /dev/null +++ b/devices/patches/usb_otg/hs_v1_pwrclk.yaml @@ -0,0 +1,4 @@ +_modify: + PCGCR: + name: PCGCCTL + displayName: PCGCCTL diff --git a/devices/patches/usb_otg/hsdevice.yaml b/devices/patches/usb_otg/hsdevice.yaml new file mode 100644 index 000000000..f2a03a821 --- /dev/null +++ b/devices/patches/usb_otg/hsdevice.yaml @@ -0,0 +1,200 @@ +_copy: + DIEPDMA0: + _from: DIEPDMA1 + description: OTG_HS device endpoint-0 DMA address register + addressOffset: 0x114 + DIEPDMA6: + _from: DIEPDMA1 + description: OTG_HS device endpoint-6 DMA address register + addressOffset: 0x1D4 + DIEPDMA7: + _from: DIEPDMA1 + description: OTG_HS device endpoint-7 DMA address register + addressOffset: 0x1F4 + DIEPCTL8: + _from: DIEPCTL1 + description: OTG_FS device control IN endpoint 8 control register + addressOffset: 0x200 + DIEPINT8: + _from: DIEPINT1 + description: device endpoint-8 interrupt register + addressOffset: 0x208 + DIEPTSIZ8: + _from: DIEPTSIZ1 + description: device endpoint-8 transfer size register + addressOffset: 0x210 + DIEPDMA8: + _from: DIEPDMA1 + description: OTG_HS device endpoint-8 DMA address register + addressOffset: 0x214 + DTXFSTS8: + _from: DTXFSTS1 + description: OTG_FS device IN endpoint transmit FIFO status register + addressOffset: 0x218 + + DOEPDMA0: + _from: DIEPDMA1 + description: OTG_HS device endpoint-0 DMA address register + addressOffset: 0x314 + DOEPDMA1: + _from: DIEPDMA1 + description: OTG_HS device endpoint-1 DMA address register + addressOffset: 0x334 + DOEPDMA2: + _from: DIEPDMA1 + description: OTG_HS device endpoint-2 DMA address register + addressOffset: 0x354 + DOEPDMA3: + _from: DIEPDMA1 + description: OTG_HS device endpoint-3 DMA address register + addressOffset: 0x374 + DOEPDMA4: + _from: DIEPDMA1 + description: OTG_HS device endpoint-4 DMA address register + addressOffset: 0x394 + DOEPDMA5: + _from: DIEPDMA1 + description: OTG_HS device endpoint-5 DMA address register + addressOffset: 0x3B4 + DOEPDMA6: + _from: DIEPDMA1 + description: OTG_HS device endpoint-6 DMA address register + addressOffset: 0x3D4 + DOEPDMA7: + _from: DIEPDMA1 + description: OTG_HS device endpoint-7 DMA address register + addressOffset: 0x3F4 + DOEPCTL8: + _from: DOEPCTL1 + description: device endpoint-8 control register + addressOffset: 0x400 + DOEPINT8: + _from: DOEPINT1 + description: device endpoint-8 interrupt register + addressOffset: 0x408 + DOEPTSIZ8: + _from: DOEPTSIZ1 + description: OTG_HS device endpoint-8 transfer size register + addressOffset: 0x410 + DOEPDMA8: + _from: DIEPDMA1 + description: OTG_HS device endpoint-8 DMA address register + addressOffset: 0x414 + +_add: + DIEPEACHMSK1: + addressOffset: 0x44 + size: 32 + access: read-write + resetValue: 0 + fields: + XFRCM: + description: Transfer completed interrupt mask + bitOffset: 0 + bitWidth: 1 + EPDM: + description: Endpoint disabled interrupt mask + bitOffset: 1 + bitWidth: 1 + AHBERRM: + description: AHB error mask + bitOffset: 2 + bitWidth: 1 + TOM: + description: Timeout condition mask (Non-isochronous endpoints) + bitOffset: 3 + bitWidth: 1 + ITTXFEMSK: + description: IN token received when TxFIFO empty mask + bitOffset: 4 + bitWidth: 1 + INEPNEM: + description: IN endpoint NAK effective mask + bitOffset: 6 + bitWidth: 1 + TXFURM: + description: FIFO underrun mask + bitOffset: 8 + bitWidth: 1 + BNAM: + description: BNA interrupt mask + bitOffset: 9 + bitWidth: 1 + NAKM: + description: NAK interrupt mask + bitOffset: 13 + bitWidth: 1 + + DOEPEACHMSK1: + addressOffset: 0x84 + size: 32 + access: read-write + resetValue: 0 + fields: + XFRCM: + description: Transfer completed interrupt mask + bitOffset: 0 + bitWidth: 1 + EPDM: + description: Endpoint disabled interrupt mask + bitOffset: 1 + bitWidth: 1 + AHBERRM: + description: AHB error mask + bitOffset: 2 + bitWidth: 1 + STUPM: + description: SETUP phase done mask + bitOffset: 3 + bitWidth: 1 + OTEPDM: + description: OUT token received when endpoint disabled mask + bitOffset: 4 + bitWidth: 1 + B2BSTUPM: + description: Back-to-back SETUP packets received mask + bitOffset: 6 + bitWidth: 1 + OUTPKTERRM: + description: Out packet error mask + bitOffset: 8 + bitWidth: 1 + BNAM: + description: BNA interrupt mask + bitOffset: 9 + bitWidth: 1 + BERRM: + description: Babble error interrupt mask + bitOffset: 12 + bitWidth: 1 + NAKMSK: + description: NAK interrupt mask + bitOffset: 13 + bitWidth: 1 + NYETMSK: + description: NYET interrupt mask + bitOffset: 14 + bitWidth: 1 + +_modify: + DIEPDMA1: + addressOffset: 0x134 + DIEPDMA2: + addressOffset: 0x154 + DIEPDMA3: + addressOffset: 0x174 + DIEPDMA4: + addressOffset: 0x194 + DIEPDMA5: + addressOffset: 0x1B4 + DIEPTSIZ6: + addressOffset: 0x1D0 + DIEPTSIZ7: + addressOffset: 0x1F0 + DTXFSTS6: + addressOffset: 0x1D8 + DTXFSTS7: + addressOffset: 0x1F8 + +_include: + - epena_stall.yaml diff --git a/devices/patches/usb_otg/hsglobal.yaml b/devices/patches/usb_otg/hsglobal.yaml new file mode 100644 index 000000000..0044f04b4 --- /dev/null +++ b/devices/patches/usb_otg/hsglobal.yaml @@ -0,0 +1,35 @@ +_copy: + DIEPTXF8: + _from: DIEPTXF1 + addressOffset: 0x120 +_modify: + HNPTXFSIZ_Host: + name: HNPTXFSIZ + DIEPTXF0_Device: + name: DIEPTXF0 + alternateRegister: HNPTXFSIZ + GNPTXSTS,HNPTXSTS: + name: HNPTXSTS + GRXSTSR_Device: + alternateRegister: GRXSTSR_Host + GRXSTSP_Device: + alternateRegister: GRXSTSP_Host + DIEPTXF2: + resetValue: 0x02000600 + DIEPTXF3: + addressOffset: 0x10C + resetValue: 0x02000800 + DIEPTXF4: + addressOffset: 0x110 + resetValue: 0x02000A00 + DIEPTXF5: + addressOffset: 0x114 + resetValue: 0x02000C00 + DIEPTXF6: + addressOffset: 0x118 + resetValue: 0x02000E00 + DIEPTXF7: + addressOffset: 0x11C + resetValue: 0x02001000 + DIEPTXF8: + resetValue: 0x02001200 diff --git a/devices/patches/usb_otg/hsglobal2.yaml b/devices/patches/usb_otg/hsglobal2.yaml new file mode 100644 index 000000000..f92f98143 --- /dev/null +++ b/devices/patches/usb_otg/hsglobal2.yaml @@ -0,0 +1,17 @@ +_modify: + OTG_DIEPTXF8: + name: DIEPTXF8 + resetValue: 0x02001200 + HNPTXFSIZ_Host: + name: HNPTXFSIZ + DIEPTXF0_Device: + name: DIEPTXF0 + alternateRegister: HNPTXFSIZ + GNPTXSTS,HNPTXSTS: + name: HNPTXSTS + GRXSTSR_Device: + alternateRegister: GRXSTSR_Host + GRXSTSP_Device: + alternateRegister: GRXSTSP_Host + DIEPTXF7: + addressOffset: 0x11C diff --git a/devices/patches/usb_otg/hshost_address_12_15.yaml b/devices/patches/usb_otg/hshost_address_12_15.yaml new file mode 100644 index 000000000..791460b99 --- /dev/null +++ b/devices/patches/usb_otg/hshost_address_12_15.yaml @@ -0,0 +1,25 @@ +_modify: + HCCHAR12: { addressOffset: 0x280 } + HCCHAR13: { addressOffset: 0x2A0 } + HCCHAR14: { addressOffset: 0x2C0 } + HCCHAR15: { addressOffset: 0x2E0 } + HCSPLT12: { addressOffset: 0x284 } + HCSPLT13: { addressOffset: 0x2A4 } + HCSPLT14: { addressOffset: 0x2C4 } + HCSPLT15: { addressOffset: 0x2E4 } + HCINT12: { addressOffset: 0x288 } + HCINT13: { addressOffset: 0x2A8 } + HCINT14: { addressOffset: 0x2C8 } + HCINT15: { addressOffset: 0x2E8 } + HCINTMSK12: { addressOffset: 0x28C } + HCINTMSK13: { addressOffset: 0x2AC } + HCINTMSK14: { addressOffset: 0x2CC } + HCINTMSK15: { addressOffset: 0x2EC } + HCTSIZ12: { addressOffset: 0x290 } + HCTSIZ13: { addressOffset: 0x2B0 } + HCTSIZ14: { addressOffset: 0x2D0 } + HCTSIZ15: { addressOffset: 0x2F0 } + HCDMA12: { addressOffset: 0x294 } + HCDMA13: { addressOffset: 0x2B4 } + HCDMA14: { addressOffset: 0x2D4 } + HCDMA15: { addressOffset: 0x2F4 } diff --git a/devices/patches/wwdg/h7.yaml b/devices/patches/wwdg/h7.yaml new file mode 100644 index 000000000..f18611630 --- /dev/null +++ b/devices/patches/wwdg/h7.yaml @@ -0,0 +1,6 @@ +_include: ../16bit.yaml + +CFR: + _modify: + WDGTB: + bitWidth: 3 diff --git a/devices/stm32c011.yaml b/devices/stm32c011.yaml new file mode 100644 index 000000000..af40dd0e8 --- /dev/null +++ b/devices/stm32c011.yaml @@ -0,0 +1,156 @@ +_svd: ../svd/stm32c011.svd + +_clear_fields: "*" + +_modify: + name: STM32C011 + +ADC: + _include: + - patches/adc/c0.yaml + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - patches/crc/idr.yaml + - fields/crc/v3_idr32.yaml + +DBG: + _strip: DBG_ + +DMA: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _strip: EXTI_ + _modify: + _interrupts: + EXTI4_5: + name: EXTI4_15 + description: EXTI line 4 to 15 interrupt + +FLASH: + _strip: FLASH_ + +GPIO?: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCDF]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/basic.yaml + #- collect/rtc/alarm.yaml + +SPI1: + _strip: SPI?_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _strip: SYSCFG_ + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - patches/tim/v2/oc5m.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM3: + _strip: TIM3_ + _modify: + CNT_alternate: + name: CNT_remap + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM14: + _strip: TIM14_ + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _strip: TIM1?_ + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/B.yaml + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml diff --git a/devices/stm32c031.yaml b/devices/stm32c031.yaml new file mode 100644 index 000000000..fd42bbf36 --- /dev/null +++ b/devices/stm32c031.yaml @@ -0,0 +1,160 @@ +_svd: ../svd/stm32c031.svd + +_clear_fields: "*" + +_modify: + name: STM32C031 + SPI: + name: SPI1 + I2C: + name: I2C1 + +ADC: + _include: + - patches/adc/c0.yaml + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - patches/crc/idr.yaml + - fields/crc/v3_idr32.yaml + +DBG: + _strip: DBG_ + +DMA: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _strip: EXTI_ + _modify: + _interrupts: + EXTI4_5: + name: EXTI4_15 + description: EXTI line 4 to 15 interrupt + +FLASH: + _strip: FLASH_ + +GPIO?: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCDF]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/basic.yaml + #- collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _strip: SYSCFG_ + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - patches/tim/v2/oc5m.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM3: + _strip: TIM3_ + _modify: + CNT_alternate: + name: CNT_remap + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM14: + _strip: TIM14_ + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _strip: TIM1?_ + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/B.yaml + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml diff --git a/devices/stm32c071.yaml b/devices/stm32c071.yaml new file mode 100644 index 000000000..3427528ba --- /dev/null +++ b/devices/stm32c071.yaml @@ -0,0 +1,203 @@ +_svd: ../svd/stm32c071.svd + +_clear_fields: "*" + +_modify: + name: STM32C071 + TIM*: + groupName: TIM + GPIO?: + groupName: GPIO + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELR: + name: CHSELR0 + CHSELR_ALTERNATE1: + name: CHSELR1 + alternateRegister: CHSELR0 + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DBG: + _strip: DBG_ + +DMA: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _strip: EXTI_ + _modify: + _interrupts: + EXTI4_5: + name: EXTI4_15 + description: EXTI line 4 to 15 interrupt + +FLASH: + _strip: FLASH_ + +GPIO?: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCDF]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/basic.yaml + #- collect/rtc/alarm.yaml + +SPI1: + _strip: SPI?_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _strip: SYSCFG_ + +TIM[123]: + _strip: TIM?_ + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + SMCR: + _modify: + TS: + name: TS1 + TS_1: + name: TS2 + SMS: + name: SMS1 + SMS_1: + name: SMS2 + +TIM1: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _modify: + CNT_ALTERNATE1: + name: CNT_remap + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _modify: + CNT_ALTERNATE1: + name: CNT_remap + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM14: + _strip: TIM14_ + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_1: + name: OC1M_3 + +TIM1[67]: + _strip: TIM1?_ + _modify: + CCMR1: + name: CCMR1_Input + CCMR1_ALTERNATE1: + name: CCMR1_Output + CCMR1_Output: + _modify: + OC1M_1: + name: OC1M_3 + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml diff --git a/devices/stm32f0x0.yaml b/devices/stm32f0x0.yaml index c95ac74c5..7b53cf0a4 100644 --- a/devices/stm32f0x0.yaml +++ b/devices/stm32f0x0.yaml @@ -1,15 +1,77 @@ _svd: ../svd/stm32f0x0.svd ADC: + _include: + - patches/adc/f0_cfgr2_ckmode.yaml + - patches/adc/f0_fixes.yaml + - fields/adc/adc_aditf4_v1_1.yaml + - collect/adc/f0_l0.yaml CCR: _delete: - VBATEN + CFGR1: + EXTSEL: + TIM1_TRGO: [0, Timer 1 TRGO Event] + TIM1_CC4: [1, Timer 1 CC4 event] + TIM3_TRGO: [3, Timer 3 TRGO event] + TIM15_TRGO: [4, Timer 15 TRGO event] + +CRC: + _include: + - patches/crc/f0_init_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v2.yaml + - fields/crc/crc_idr_8bit.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml + +Flash: + OBR: + _modify: + RAM_PARITY_CHECK_: + name: RAM_PARITY_CHECK + _include: + - fields/flash/flash_f0.yaml + +GPIO?: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[F]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: + _include: + - fields/pwr/pwr_v1.yaml RCC: AHBENR: _add: IOPDEN: - description: "I/O port D clock enable" + description: I/O port D clock enable bitOffset: 20 bitWidth: 1 CFGR: @@ -17,65 +79,101 @@ RCC: PLLSRC: bitOffset: 16 bitWidth: 1 + _include: + - patches/rcc/rename_CIR_HSI14RDYIE_field.yaml + - patches/rcc/f0_no_hdmi_cec.yaml + - patches/rcc/f0_v18pwrrstf.yaml + - patches/rcc/f0_usart3.yaml + - patches/rcc/f0_usart6.yaml + - patches/rcc/f0_dmaen.yaml + - patches/rcc/f0_usben.yaml + - patches/rcc/f0_hsi48cal.yaml + - fields/rcc/rcc_f0x0.yaml + +RTC: + _derive: + TSTR: TR + TSDR: DR + _include: + - fields/rtc/v2/basic.yaml + #- collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml SPI1: SR: _delete: - CHSIDE - UDR + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +SYSCFG: + _include: + - patches/syscfg/f0.yaml + - fields/syscfg/syscfg_f0.yaml + - fields/exti/derive.yaml + + EXTICR1: + EXTI0: + PA: [0, Select PAx as the source input for the EXTIx external interrupt] + PB: [1, Select PBx as the source input for the EXTIx external interrupt] + PC: [2, Select PCx as the source input for the EXTIx external interrupt] + PD: [3, Select PDx as the source input for the EXTIx external interrupt] + PF: [5, Select PFx as the source input for the EXTIx external interrupt] + +TIM1: + _include: + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM14: + _include: + - fields/tim/v1/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - fields/tim/v1/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v1/tim16.yaml + - collect/tim/ccr.yaml + +USART1: + _include: + - patches/usart/rename_CR1_M0_field.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/rename_RCC_CIR_HSI14RDYIE_field.yaml - - ./common_patches/rename_f0_SPI_registers.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/f0_no_hdmi_cec.yaml - - ./common_patches/f0_v18pwrrstf.yaml - - ./common_patches/f0_adc_cfgr2_ckmode.yaml - - ./common_patches/f0_adc_fixes.yaml - - ./common_patches/f0_usart3.yaml - - ./common_patches/f0_usart6.yaml - - ./common_patches/f0_dmaen.yaml - - ./common_patches/f0_usben.yaml - - ./common_patches/f0_hsi48cal.yaml - - ./common_patches/f0_syscfg.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR1_M0_field.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim1_16bit.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim14_16bit.yaml - - ../peripherals/tim/tim15_16bit.yaml - - ../peripherals/tim/tim16_16bit.yaml - - common_patches/tim/tim1_16bit_l.yaml - - common_patches/tim/tim2345_16bit_l.yaml - - common_patches/tim/tim14_16bit_l.yaml - - common_patches/tim/tim15_16bit_l.yaml - - common_patches/tim/tim16_16bit_l.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/rcc/rcc_f0x0.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - ../peripherals/syscfg/syscfg_f0.yaml - - ../peripherals/adc/adc_aditf4_v1_1.yaml - - ../peripherals/spi/spi_v2_without_UDR_CHSIDE.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb_with_LPM.yaml - - common_patches/f0_ram_parity_check.yaml - - ../peripherals/flash/flash_f0.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ./common_patches/2_nvic_prio_bits.yaml - - ./common_patches/f0_crc_init_addr_fix.yaml + - patches/tim/group.yaml + - patches/nvic/2_prio_bits.yaml diff --git a/devices/stm32f0x1.yaml b/devices/stm32f0x1.yaml index d1a9b52a4..02848b218 100644 --- a/devices/stm32f0x1.yaml +++ b/devices/stm32f0x1.yaml @@ -1,72 +1,189 @@ _svd: ../svd/stm32f0x1.svd +# TIM3 is 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + +ADC: + _include: + - patches/adc/f0_cfgr2_ckmode.yaml + - patches/adc/f0_fixes.yaml + - fields/adc/adc_aditf4_v1_1_RM0091.yaml + - collect/adc/f0_l0.yaml + +CAN: + _strip: CAN_ + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - patches/cec/cfgr.yaml + - fields/hdmi_cec.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/f0_init_addr_fix.yaml + - patches/crc/crc_add_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/f0.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml + Flash: OBR: _modify: # The SVD says this field is 0 bits, but RM0091 says it's 1 bit. RAM_PARITY_CHECK: bitWidth: 1 + _include: + - fields/flash/flash_f04x_f09x.yaml -# TIM3 is 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 +GPIO?: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[F]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: + _include: + - patches/rcc/rename_CIR_HSI14RDYIE_field.yaml + - patches/rcc/f0_v18pwrrstf.yaml + - patches/rcc/f0_gpioe.yaml + - patches/rcc/f0_usart3.yaml + - patches/rcc/f0_usart6.yaml + - patches/rcc/f0_usart78.yaml + - patches/rcc/f0_dmaen.yaml + - patches/rcc/f0_usben.yaml + - patches/rcc/f0_hsi48cal.yaml + - fields/rcc/rcc_f0x128.yaml + +RTC: + _derive: + TSTR: TR + TSDR: DR + _include: + - fields/rtc/v2/basic.yaml + #- collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - fields/syscfg/syscfg_f0x128.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM14: + _include: + - fields/tim/v1/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - fields/tim/v1/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v1/tim16.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/rename_CR1_M0_field.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/rename_RCC_CIR_HSI14RDYIE_field.yaml - - ./common_patches/rename_f0_SPI_registers.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/f0_v18pwrrstf.yaml - - ./common_patches/f0_adc_cfgr2_ckmode.yaml - - ./common_patches/f0_adc_fixes.yaml - - ./common_patches/f0_gpioe.yaml - - ./common_patches/f0_usart3.yaml - - ./common_patches/f0_usart6.yaml - - ./common_patches/f0_usart78.yaml - - ./common_patches/f0_dmaen.yaml - - ./common_patches/f0_usben.yaml - - ./common_patches/f0_hsi48cal.yaml - - ./common_patches/f0_syscfg_comp.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR1_M0_field.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can_remove_prefix.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/rcc/rcc_f0x128.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - ../peripherals/syscfg/syscfg_f0x128.yaml - - ../peripherals/comp/comp_f0.yaml - - ../peripherals/adc/adc_aditf4_v1_1_RM0091.yaml - - ../peripherals/spi/spi_v2.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb_with_LPM.yaml - - common_patches/f0_ram_parity_check.yaml - - ../peripherals/flash/flash_f04x_f09x.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ./common_patches/2_nvic_prio_bits.yaml - - ./common_patches/f0_crc_init_addr_fix.yaml + - patches/f0_syscfg_comp.yaml + - patches/tim/group.yaml + - fields/comp/comp_f0.yaml + - patches/nvic/2_prio_bits.yaml diff --git a/devices/stm32f0x2.yaml b/devices/stm32f0x2.yaml index 50b43aa93..d9075d296 100644 --- a/devices/stm32f0x2.yaml +++ b/devices/stm32f0x2.yaml @@ -1,90 +1,202 @@ _svd: ../svd/stm32f0x2.svd +# TIM3 is 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + +ADC: + _include: + - patches/adc/f0_cfgr2_ckmode.yaml + - patches/adc/f0_fixes.yaml + - fields/adc/adc_aditf4_v1_1_RM0091.yaml + - collect/adc/f0_l0.yaml + +CAN: + _strip: CAN_ + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - patches/cec/cfgr.yaml + - fields/hdmi_cec.yaml + +CRC: + _include: + - patches/crc/f0_init_addr_fix.yaml + - patches/crc/crc_add_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/f0.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _add: + _interrupts: + DMA1_CH2_3: + description: DMA channel 2 and 3 interrupts + value: 10 + + DMA1_CH4_5_6_7: + description: "DMA channel 4, 5, 6 and 7 interrupts" + value: 11 + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml + +Flash: + _include: + - fields/flash/flash_f04x_f09x.yaml + +GPIO?: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[F]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + RCC: APB1RSTR: _add: USART5RST: - description: "USART5 reset" + description: USART5 reset bitOffset: 20 bitWidth: 1 APB1ENR: _add: USART5EN: - description: "USART5 clock enable" + description: USART5 clock enable bitOffset: 20 bitWidth: 1 + _include: + - patches/rcc/rename_CIR_HSI14RDYIE_field.yaml + - patches/rcc/f0_v18pwrrstf.yaml + - patches/rcc/f0_gpioe.yaml + - patches/rcc/f0_usart3.yaml + - patches/rcc/f0_usart6.yaml + - patches/rcc/f0_dmaen.yaml + - patches/rcc/f0_usben.yaml + - patches/rcc/f0_hsi48cal.yaml + - fields/rcc/rcc_f0x128.yaml -DMA1: - _add: - _interrupts: - DMA1_CH2_3: - description: "DMA channel 2 and 3 interrupts" - value: 10 +RTC: + _derive: + TSTR: TR + TSDR: DR + _include: + - fields/rtc/v2/basic.yaml + #- collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml - DMA1_CH4_5_6_7: - description: "DMA channel 4, 5, 6 and 7 interrupts" - value: 11 +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2.yaml -# TIM3 is 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 +SYSCFG: + _include: + - fields/syscfg/syscfg_f0x128.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM14: + _include: + - fields/tim/v1/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - fields/tim/v1/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v1/tim16.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/rename_CR1_M0_field.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/rename_RCC_CIR_HSI14RDYIE_field.yaml - - ./common_patches/rename_f0_SPI_registers.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/f0_v18pwrrstf.yaml - - ./common_patches/f0_adc_cfgr2_ckmode.yaml - - ./common_patches/f0_adc_fixes.yaml - - ./common_patches/f0_gpioe.yaml - - ./common_patches/f0_usart3.yaml - - ./common_patches/f0_usart6.yaml - - ./common_patches/f0_dmaen.yaml - - ./common_patches/f0_usben.yaml - - ./common_patches/f0_hsi48cal.yaml - - ./common_patches/f0_syscfg_comp.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR1_M0_field.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can_remove_prefix.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/rcc/rcc_f0x128.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - ../peripherals/syscfg/syscfg_f0x128.yaml - - ../peripherals/comp/comp_f0.yaml - - ../peripherals/adc/adc_aditf4_v1_1_RM0091.yaml - - ../peripherals/spi/spi_v2.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb_with_LPM.yaml - - ../peripherals/usb/usb_array.yaml - - common_patches/f0_ram_parity_check.yaml - - ../peripherals/flash/flash_f04x_f09x.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ./common_patches/2_nvic_prio_bits.yaml - - ./common_patches/f0_crc_init_addr_fix.yaml + - patches/f0_syscfg_comp.yaml + - patches/tim/group.yaml + - fields/comp/comp_f0.yaml + - patches/nvic/2_prio_bits.yaml diff --git a/devices/stm32f0x8.yaml b/devices/stm32f0x8.yaml index ae82c49a6..51e163896 100644 --- a/devices/stm32f0x8.yaml +++ b/devices/stm32f0x8.yaml @@ -5,61 +5,181 @@ _copy: TIM3: from: TIM2 +ADC: + _include: + - patches/adc/f0_cfgr2_ckmode.yaml + - patches/adc/f0_fixes.yaml + - fields/adc/adc_aditf4_v1_1_RM0091.yaml + - collect/adc/f0_l0.yaml + +CAN: + _strip: CAN_ + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - patches/cec/cfgr.yaml + - fields/hdmi_cec.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/f0_init_addr_fix.yaml + - patches/crc/crc_add_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/f0.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml + +Flash: + _include: + - fields/flash/flash_f04x_f09x.yaml + +GPIO?: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[F]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: + _include: + - patches/rcc/rename_CIR_HSI14RDYIE_field.yaml + - patches/rcc/f0_v18pwrrstf.yaml + - patches/rcc/f0_gpioe.yaml + - patches/rcc/f0_usart3.yaml + - patches/rcc/f0_usart6.yaml + - patches/rcc/f0_usart78.yaml + - patches/rcc/f0_dmaen.yaml + - patches/rcc/f0_usben.yaml + - patches/rcc/f0_hsi48cal.yaml + - fields/rcc/rcc_f0x128.yaml + +RTC: + _derive: + TSTR: TR + TSDR: DR + _include: + - fields/rtc/v2/basic.yaml + - fields/rtc/v2/wakeup.yaml + #- collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - fields/syscfg/syscfg_f0x128.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM14: + _include: + - fields/tim/v1/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - fields/tim/v1/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v1/tim16.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/rename_CR1_M0_field.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + _include: - - ./common_patches/rename_RCC_CIR_HSI14RDYIE_field.yaml - - ./common_patches/rename_f0_SPI_registers.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/f0_v18pwrrstf.yaml - - ./common_patches/f0_adc_cfgr2_ckmode.yaml - - ./common_patches/f0_adc_fixes.yaml - - ./common_patches/f0_gpioe.yaml - - ./common_patches/f0_usart3.yaml - - ./common_patches/f0_usart6.yaml - - ./common_patches/f0_usart78.yaml - - ./common_patches/f0_dmaen.yaml - - ./common_patches/f0_usben.yaml - - ./common_patches/f0_hsi48cal.yaml - - ./common_patches/f0_syscfg_comp.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR1_M0_field.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can_remove_prefix.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/rcc/rcc_f0x128.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - ../peripherals/syscfg/syscfg_f0x128.yaml - - ../peripherals/comp/comp_f0.yaml - - ../peripherals/adc/adc_aditf4_v1_1_RM0091.yaml - - ../peripherals/spi/spi_v2.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb_with_LPM.yaml - - common_patches/f0_ram_parity_check.yaml - - ../peripherals/flash/flash_f04x_f09x.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ./common_patches/2_nvic_prio_bits.yaml - - ./common_patches/f0_crc_init_addr_fix.yaml + - patches/f0_syscfg_comp.yaml + - patches/tim/group.yaml + - fields/comp/comp_f0.yaml + - patches/nvic/2_prio_bits.yaml diff --git a/devices/stm32f100.yaml b/devices/stm32f100.yaml index 79ca9fc28..581c6a4cc 100644 --- a/devices/stm32f100.yaml +++ b/devices/stm32f100.yaml @@ -3,7 +3,176 @@ _svd: ../svd/stm32f100.svd _derive: UART5: UART4 +ADC1: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AFIO: + _include: + - fields/exti/derive.yaml + - fields/exti/abcdefg.yaml + +BKP: + _include: + - fields/bkp/bkp.yaml + - collect/bkp/dr.yaml + +CEC: {} + +CRC: + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: [1, Timer 3 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim5Trgo: [3, Timer 5 or Timer 15 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Software: [7, Software trigger] + _include: + - fields/dac/v2.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: {} + +FSMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_v3.yaml + - fields/fsmc/sram.yaml + - collect/fsmc/sram.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIOA: + _include: + - fields/gpio/v1/common.yaml + - collect/gpio/f1.yaml + - collect/gpio/f1_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +MPU: + _strip: MPU_ + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: + _include: + - patches/rcc/f1_uart45.yaml + - fields/rcc/rcc_f1.yaml + - fields/rcc/rcc_cfgr2_prediv.yaml + +RTC: + _include: + - fields/rtc/v1/f1.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/dff.yaml + +TIM1: + CCMR[12]_Input: + _modify: + IC[24]F: + bitOffset: 12 + _include: + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM12: + _include: + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - fields/tim/v1/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - fields/tim/v1/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v1/tim16.yaml + - collect/tim/ccr.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v1/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v1/usart.yaml + WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml # EWIF is named incorrectly in the SVD compared to its name in RM0008 SR: _modify: @@ -11,37 +180,6 @@ WWDG: name: EWIF _include: - - ./common_patches/f1_uart45.yaml - - ./common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - common_patches/bkp/bkp.yaml - - ../peripherals/bkp/bkp.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/gpio/gpio_f1.yaml - - ../peripherals/spi/spi_v1_without_FRF_FRE_UDR_CHSIDE.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/rcc/rcc_f1.yaml - - ../peripherals/rcc/rcc_cfgr2_prediv.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu_rename.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/adc/adc_f1_common.yaml + - patches/bkp/bkp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/rename.yaml diff --git a/devices/stm32f101.yaml b/devices/stm32f101.yaml index ec3fad857..9d73ea9c7 100644 --- a/devices/stm32f101.yaml +++ b/devices/stm32f101.yaml @@ -1,5 +1,8 @@ _svd: ../svd/stm32f101.svd +_delete: + - CAN[12] + _derive: UART5: UART4 @@ -7,18 +10,6 @@ _copy: ADC3: from: ADC2 -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - _modify: # Fix case on Ethernet peripherals to match other devices ETHERNET_DMA: @@ -30,51 +21,251 @@ _modify: ETHERNET_PTP: name: Ethernet_PTP +ADC1: + DR: + _add: + ADC2DATA: + description: ADC2 data + bitOffset: 16 + bitWidth: 16 + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - fields/adc/adc1_f1.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC2: + CR1: + _delete: DUALMOD + _include: + - patches/adc/smpx_17.yaml + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/v1/adc2_derive.yaml + +ADC3: + CR1: + _delete: DUALMOD + _include: + - patches/adc/smpx_17.yaml + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc3_f1.yaml + - collect/adc/jofr_jdr.yaml + +ADC[3]: + _include: collect/adc/v1/adc3_derive.yaml + +AFIO: + _include: + - fields/exti/derive.yaml + - fields/exti/abcdefg.yaml + +BKP: + _include: + - fields/bkp/bkp.yaml + - collect/bkp/dr.yaml + +CRC: + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + _include: + - fields/dac/f1.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +Ethernet_DMA: {} +Ethernet_MAC: {} +Ethernet_MMC: {} +Ethernet_PTP: {} + +EXTI: + _include: + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - fields/flash/flash_f1.yaml + +FSMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_v3.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIOA: + _include: + - fields/gpio/v1/common.yaml + - collect/gpio/f1.yaml + - collect/gpio/f1_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +MPU: + _strip: MPU_ + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + RCC: APB2RSTR: _delete: - ADC2RST + _include: + - fields/rcc/rcc_f1.yaml + +RTC: + _include: + - fields/rtc/v1/f1.yaml + +SDIO: + _modify: + RESPI1: + name: RESP1 + displayName: RESP1 + DCTRL: + _modify: + PWSTART: + name: RWSTART + PWSTOP: + name: RWSTOP + FIFOCNT: + _modify: + FIF0COUNT: + name: FIFOCOUNT + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1_without_FRF_FRE.yaml + +TIM1: + CCMR[12]_Input: + _modify: + IC[24]F: + bitOffset: 12 + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/tim_o24ce.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _add: + OC1FE: + description: Output compare 1 fast enable + bitOffset: 2 + bitWidth: 1 + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v1/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v1/usart.yaml + +USB: + _include: + - fields/usb/v1.yaml + - collect/usb/epxr.yaml WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml # EWIF is named incorrectly in the SVD compared to its name in RM0008 SR: _modify: EWI: name: EWIF + _include: - - ./common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/bkp/bkp.yaml - - ../peripherals/bkp/bkp.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/gpio/gpio_f1.yaml - - ../peripherals/spi/spi_v1_without_FRF_FRE.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/rcc/rcc_f1.yaml - - ../peripherals/rtc/rtc_f1.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - common_patches/dbgmcu_rename.yaml - - ../peripherals/flash/flash_f1.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/adc/adc_f1.yaml + - patches/bkp/bkp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/rename.yaml diff --git a/devices/stm32f102.yaml b/devices/stm32f102.yaml index 8ddb79066..f65a19d8c 100644 --- a/devices/stm32f102.yaml +++ b/devices/stm32f102.yaml @@ -1,5 +1,8 @@ _svd: ../svd/stm32f102.svd +_delete: + - CAN[12] + _rebase: UART4: UART5 @@ -7,115 +10,275 @@ _copy: ADC3: from: ADC2 -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": +_derive: + TIM4: TIM2 + TIM5: TIM2 + TIM10: TIM13 + TIM11: TIM13 + +_add: + USART3: + derivedFrom: USART1 + baseAddress: "0x40004800" + interrupts: + USART3: + description: USART3 global interrupt + value: 39 + +ADC1: + DR: + _add: + ADC2DATA: + description: ADC2 data + bitOffset: 16 + bitWidth: 16 + _include: + - patches/adc/smpx_17.yaml + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - fields/adc/adc1_f1.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC2: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/v1/adc2_derive.yaml + +ADC3: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc3_f1.yaml + - collect/adc/jofr_jdr.yaml + +ADC[3]: + _include: collect/adc/v1/adc3_derive.yaml + +AFIO: + _include: + - fields/exti/derive.yaml + - fields/exti/abcdefg.yaml + +BKP: + _include: + - fields/bkp/bkp.yaml + - collect/bkp/dr.yaml + +CRC: + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - fields/flash/flash_f1.yaml + +FSMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_v3.yaml + - fields/fsmc/sram.yaml + - collect/fsmc/sram.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIOA: + _include: + - fields/gpio/v1/common.yaml + - collect/gpio/f1.yaml + - collect/gpio/f1_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: _merge: - - "FB*" + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +MPU: + _strip: MPU_ + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml RCC: APB1RSTR: _add: USBRST: - description: "USB reset" + description: USB reset bitOffset: 23 bitWidth: 1 I2C2RST: - description: "I2C2 reset" + description: I2C2 reset bitOffset: 22 bitWidth: 1 USART3RST: - description: "USART3 reset" + description: USART3 reset bitOffset: 18 bitWidth: 1 SPI2RST: - description: "SPI2 reset" + description: SPI2 reset bitOffset: 14 bitWidth: 1 TIM4RST: - description: "TIM4 timer reset" + description: TIM4 timer reset bitOffset: 2 bitWidth: 1 APB1ENR: _add: USBEN: - description: "USB clock enable" + description: USB clock enable bitOffset: 23 bitWidth: 1 I2C2EN: - description: "I2C2 clock enable" + description: I2C2 clock enable bitOffset: 22 bitWidth: 1 USART3EN: - description: "USART3 clock enable" + description: USART3 clock enable bitOffset: 18 bitWidth: 1 SPI2EN: - description: "SPI2 clock enable" + description: SPI2 clock enable bitOffset: 14 bitWidth: 1 TIM4EN: - description: "TIM4 Timer clock enable" + description: TIM4 Timer clock enable bitOffset: 2 bitWidth: 1 + _include: + - fields/rcc/rcc_f1.yaml -_add: - USART3: - derivedFrom: USART1 - baseAddress: "0x40004800" - interrupts: - USART3: - description: USART3 global interrupt - value: 39 +RTC: + _include: + - fields/rtc/v1/f1.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI[12]: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/dff.yaml + +TIM8: + CCMR[12]_Input: + _modify: + IC[24]F: + bitOffset: 12 + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/tim_o24ce.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - fields/tim/v1/tim13.yaml + - collect/tim/ccr.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v1/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v1/usart.yaml + +USB: + _include: + - fields/usb/v1.yaml + - collect/usb/epxr.yaml WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml # EWIF is named incorrectly in the SVD compared to its name in RM0008 SR: _modify: EWI: name: EWIF + _include: - - ./common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/bkp/bkp.yaml - - ../peripherals/bkp/bkp.yaml - - common_patches/can/can_remove_prefix.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/gpio/gpio_f1.yaml - - ../peripherals/spi/spi_v1_without_FRF_FRE_UDR_CHSIDE.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/rcc/rcc_f1.yaml - - ../peripherals/rtc/rtc_f1.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - common_patches/dbgmcu_rename.yaml - - ../peripherals/flash/flash_f1.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/adc/adc_f1.yaml + - patches/bkp/bkp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/rename.yaml diff --git a/devices/stm32f103.yaml b/devices/stm32f103.yaml index ae92626b1..bb9f65344 100644 --- a/devices/stm32f103.yaml +++ b/devices/stm32f103.yaml @@ -7,19 +7,14 @@ _copy: ADC3: from: ADC2 -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" +# Only one CAN on STM32F103 +_delete: + - CAN2 _modify: + # Only one CAN on STM32F103 + CAN1: + name: CAN # Fix case on Ethernet peripherals to match other devices ETHERNET_DMA: name: Ethernet_DMA @@ -30,6 +25,149 @@ _modify: ETHERNET_PTP: name: Ethernet_PTP +ADC1: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - fields/adc/adc1_f1.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC2: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/v1/adc2_derive.yaml + +ADC3: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc3_f1.yaml + - collect/adc/jofr_jdr.yaml + +ADC[3]: + _include: collect/adc/v1/adc3_derive.yaml + +AFIO: + MAPR: + _modify: + CAN_REMAP: + description: CAN remapping + _include: + - fields/exti/derive.yaml + - fields/exti/abcdefg.yaml + +BKP: + _include: + - fields/bkp/bkp.yaml + - collect/bkp/dr.yaml + +CAN: + _strip: CAN_ + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + _include: + - fields/dac/f1.yaml + - collect/dac/v2.yaml + +DBGMCU: + CR: + _modify: + DBG_CAN1_STOP: + name: DBG_CAN_STOP + description: DBG_CAN_STOP + _delete: DBG_CAN2_STOP + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +Ethernet_DMA: {} +Ethernet_MAC: {} +Ethernet_MMC: {} +Ethernet_PTP: {} + +EXTI: + _include: + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - fields/flash/flash_f1.yaml + +FSMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_v3.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIOA: + _include: + - fields/gpio/v1/common.yaml + - collect/gpio/f1.yaml + - collect/gpio/f1_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +MPU: + _strip: MPU_ + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + RCC: CFGR: _modify: @@ -37,55 +175,106 @@ RCC: OTGFSPRE: name: USBPRE description: USB prescaler + _include: + - fields/rcc/rcc_f1.yaml + - fields/rcc/rcc_f1_f3_usb.yaml + +RTC: + _include: + - fields/rtc/v1/f1.yaml + +SDIO: + _modify: + RESPI1: + name: RESP1 + displayName: RESP1 + DCTRL: + _modify: + PWSTART: + name: RWSTART + PWSTOP: + name: RWSTOP + FIFOCNT: + _modify: + FIF0COUNT: + name: FIFOCOUNT + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1_without_FRF_FRE.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/tim_o24ce.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _add: + OC1FE: + description: Output compare 1 fast enable + bitOffset: 2 + bitWidth: 1 + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v1/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v1/usart.yaml + +USB: + _include: + - fields/usb/v1.yaml + - collect/usb/epxr.yaml WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml # EWIF is named incorrectly in the SVD compared to its name in RM0008 SR: _modify: EWI: name: EWIF + _include: - - ./common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/bkp/bkp.yaml - - ../peripherals/bkp/bkp.yaml - - common_patches/can/can_remove_prefix.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/crc/crc_basic.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/gpio/gpio_f1.yaml - - ../peripherals/spi/spi_v1_without_FRF_FRE.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/rcc/rcc_f1.yaml - - ../peripherals/rcc/rcc_f1_f3_usb.yaml - - ../peripherals/rtc/rtc_f1.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/usb/usb_array.yaml - - ../peripherals/sdio/sdio.yaml - - ../peripherals/adc/adc_array.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - common_patches/dbgmcu_rename.yaml - - ../peripherals/flash/flash_f1.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/adc/adc_f1.yaml + - patches/bkp/bkp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/rename.yaml diff --git a/devices/stm32f107.yaml b/devices/stm32f107.yaml index 4346b435c..270d54d52 100644 --- a/devices/stm32f107.yaml +++ b/devices/stm32f107.yaml @@ -2,23 +2,15 @@ _svd: ../svd/stm32f107.svd _derive: UART5: UART4 + TIM11: TIM13 + TIM14: TIM13 + TIM8: TIM1 + CAN2: CAN1 _copy: ADC3: from: ADC2 -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -CAN1: - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - _modify: # Fix case on Ethernet peripherals to match other devices ETHERNET_DMA: @@ -29,53 +21,258 @@ _modify: name: Ethernet_MMC ETHERNET_PTP: name: Ethernet_PTP + USB_OTG_HOST: + name: OTG_FS_HOST + groupName: USB_OTG_FS + USB_OTG_GLOBAL: + name: OTG_FS_GLOBAL + groupName: USB_OTG_FS + USB_OTG_DEVICE: + name: OTG_FS_DEVICE + groupName: USB_OTG_FS + USB_OTG_PWRCLK: + name: OTG_FS_PWRCLK + groupName: USB_OTG_FS + +ADC1: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - fields/adc/adc1_f1.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC2: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc_f1_common.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/v1/adc2_derive.yaml + +ADC3: + _include: + - fields/adc/adc_f1_f37x.yaml + - fields/adc/adc3_f1.yaml + - collect/adc/jofr_jdr.yaml + +ADC[3]: + _include: collect/adc/v1/adc3_derive.yaml + +AFIO: + _include: + - fields/exti/derive.yaml + - fields/exti/abcdefg.yaml + +BKP: + _include: + - fields/bkp/bkp.yaml + - collect/bkp/dr.yaml + +CAN1: + _strip: CAN_ + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: [1, Timer 3 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim5Trgo: [3, Timer 5 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Software: [7, Software trigger] + _include: + - fields/dac/v1.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +#Ethernet_DMA: {} + +Ethernet_MAC: + MACA2LR: + _modify: + MACA2L: + bitWidth: 32 + +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - fields/flash/flash_f1.yaml + +FSMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_v3.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIOA: + _include: + - fields/gpio/v1/common.yaml + - collect/gpio/f1.yaml + - collect/gpio/f1_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +MPU: + _strip: MPU_ + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + GUSBCFG: + _modify: + PHYSEL: + bitOffset: 6 + _include: + - patches/usb_otg/fs_v1_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: + _include: + - patches/rcc/f1_uart45.yaml + - fields/rcc/rcc_f107.yaml + - fields/rcc/rcc_f1_f3_usb.yaml + - fields/rcc/rcc_cfgr2_f107.yaml + +RTC: + _include: + - fields/rtc/v1/f1.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1_without_FRF_FRE.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - fields/tim/v1/tim13.yaml + - collect/tim/ccr.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v1/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v1/usart.yaml + +USB: + _include: + - fields/usb/v1.yaml + - collect/usb/epxr.yaml WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml # EWIF is named incorrectly in the SVD compared to its name in RM0008 SR: _modify: EWI: name: EWIF + _include: - - common_patches/f1_uart45.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/bkp/bkp.yaml - - ../peripherals/bkp/bkp.yaml - - common_patches/can/can_remove_prefix.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/gpio/gpio_f1.yaml - - ../peripherals/spi/spi_v1_without_FRF_FRE.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/rcc/rcc_f107.yaml - - ../peripherals/rcc/rcc_f1_f3_usb.yaml - - ../peripherals/rcc/rcc_cfgr2_f107.yaml - - ../peripherals/rtc/rtc_f1.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/usb_otg/otg_fs_fixes_107.yaml - - ../peripherals/usb/usb.yaml - - common_patches/dbgmcu_rename.yaml - - ../peripherals/flash/flash_f1.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/adc/adc_f1.yaml - - common_patches/f1_ethernet.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mmc_common.yaml + - patches/bkp/bkp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/rename.yaml + - patches/ethernet/f1.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mmc_common.yaml diff --git a/devices/stm32f215.yaml b/devices/stm32f215.yaml index 34dfe3d39..34c81f161 100644 --- a/devices/stm32f215.yaml +++ b/devices/stm32f215.yaml @@ -8,79 +8,274 @@ _rebase: I2C1: I2C3 USART1: USART6 -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml -"CAN2": - _cluster: - "FB%s": - description: "CAN Filter Bank cluster" - "F*R1": {} - "F*R2": {} +ADC[1]: + _include: collect/adc/derive_sq.yaml +CAN2: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v1.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +#Ethernet_DMA: {} +#Ethernet_MAC: {} +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_8_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - collect/flash/optcr/nwrp.yaml + +FSMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_v3.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v1.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: _merge: - - "IV*" + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +MPU: + _strip: MPU_ + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_v1_novbussens.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_v1_device.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hs_v1_global.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: + _include: + - patches/usb_otg/hs_v1_pwrclk.yaml + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST + _include: + - patches/rcc/f2.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _derive: + TSTR: TR + TSDR: DR + _include: + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/basic.yaml + - fields/rtc/v2/wakeup.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + +SYSCFG: {} + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/dma_fcr_wo.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/can/can.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v1.yaml - - common_patches/f2_rcc.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - common_patches/fsmc/fsmc_nand_v1.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - common_patches/f2_f4_ethernet.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v1.yaml - - common_patches/hash/hash_v1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v1.yaml + - patches/ethernet/f2_f4.yaml + - patches/ethernet/mmc.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f217.yaml b/devices/stm32f217.yaml index 2081bc20f..461d68dd0 100644 --- a/devices/stm32f217.yaml +++ b/devices/stm32f217.yaml @@ -8,78 +8,275 @@ _rebase: I2C1: I2C3 USART1: USART6 -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml -"CAN2": - _cluster: - "FB%s": - description: "CAN Filter Bank cluster" - "F*R1": {} - "F*R2": {} +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN2: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v1.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +#Ethernet_DMA: {} +#Ethernet_MAC: {} +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_8_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - collect/flash/optcr/nwrp.yaml + +FSMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_v3.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v1.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: _merge: - - "IV*" + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +MPU: + _strip: MPU_ + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_v1_novbussens.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_v1_device.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hs_v1_global.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: + _include: + - patches/usb_otg/hs_v1_pwrclk.yaml + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST + _include: + - patches/rcc/f2.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _derive: + TSTR: TR + TSDR: DR + _include: + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/basic.yaml + - fields/rtc/v2/wakeup.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + +SYSCFG: {} + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/dma_fcr_wo.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/can/can.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v1.yaml - - common_patches/f2_rcc.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - common_patches/fsmc/fsmc_nand_v1.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - common_patches/f2_f4_ethernet.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v1.yaml - - common_patches/hash/hash_v1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v1.yaml + - patches/ethernet/f2_f4.yaml + - patches/ethernet/mmc.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f301.yaml b/devices/stm32f301.yaml index 9c82b848a..837ce625e 100644 --- a/devices/stm32f301.yaml +++ b/devices/stm32f301.yaml @@ -1,32 +1,40 @@ _svd: ../svd/stm32f301.svd +_delete: + - EXTI + _copy: - TIM1: - from: ../svd/stm32f302.svd:TIM1 ADC1_2: - from: ADC - -_add: - I2C3: - derivedFrom: I2C1 - baseAddress: "0x40007800" - interrupts: - I2C3_EV_IRQ: - description: I2C3 event interrupt / EXTI Line27 interrupt - value: 72 - I2C3_ER_IRQ: - description: I2C3 error interrupt - value: 73 + from: ../svd/stm32f302.svd:ADC1_2 + EXTI: + from: ../svd/stm32f302.svd:EXTI _modify: ADC: name: ADC1 ADC1_2: description: ADC Common registers - baseAddress: "0x50000300" # Rename in accordance with other devices and reference manual. Flash: name: FLASH + SYSCFG_COMP_OPAMP: + name: SYSCFG + groupName: SYSCFG + description: System configuration controller + +ADC1_2: + _delete: + - CDR + CCR: + _delete: + - MDMA + - DMACFG + - DELAY + - DUAL + - MULT + _include: + - fields/adc/adc_v3_common_single.yaml + - fields/adc/adc_v3_common_f3_single.yaml ADC1: _delete: @@ -34,42 +42,129 @@ ADC1: - CRR CR: _modify: - '*': + "*": access: read-write + JADST: + name: JADSTP + _include: + - patches/adc/offset_en.yaml + - patches/adc/split.yaml + - fields/adc/adc_v3_f3.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [1, 18] -ADC1_2: +ADC[1]: + _include: collect/adc/derive_sq.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +DAC1: + CR: + TSEL1: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim15Trgo: [3, Timer 15 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Exti9: [6, EXTI line 9] + Software: [7, Software trigger] + _include: + - fields/dac/v2.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/f3_offset.yaml + - fields/exti/common.yaml _delete: - - I?R - - CR - - CFGR - - SMPR* - - TR* - - '*SQR*' - - '*DR*' - - OFR* - - AWD*CR - - DIFSEL - - CALFACT + _interrupts: + - UART4_EXTI34 + - UART5_EXTI35 _modify: - CSR: - alternateRegister: "" - CRR: - name: CCR - displayName: CCR - alternateRegister: "" - -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0366 - TIFRFE: - name: "FRE" + IMR2: + resetValue: "0xFFFFFFFE" + +FLASH: + _include: + - patches/flash/f3.yaml + - fields/flash/flash_f3_common.yaml + - fields/flash/acr/hlfcya.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/f3.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +OPAMP: {} + +PWR: + _add: + _interrupts: + PVD: + description: PVD through EXTI line detection interrupt + value: 1 RCC: CFGR3: _modify: TIM17SW: bitWidth: 1 + _include: + - patches/rcc/f3.yaml + - patches/rcc/f3_i2c3.yaml + - patches/rcc/f3_delete_cec.yaml + - fields/rcc/rcc_f3.yaml + - fields/rcc/rcc_f3_i2s.yaml + - fields/rcc/rcc_pllsrc_1bit.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/f3.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI2: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0366 + TIFRFE: + name: FRE SYSCFG: _delete: @@ -87,68 +182,85 @@ SYSCFG: - SRAM_PARITY_LOCK - BYP_ADD_PAR - SRAM_PEF + _include: + - patches/syscfg/f3.yaml + - patches/syscfg/f3_cfgr1_i2c3_fmp.yaml + - fields/syscfg/syscfg_f3.yaml + - fields/syscfg/syscfg_f301.yaml + - fields/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + CCMR3_Output: + _modify: + OC5M3: + name: OC5M_3 + OC6M3: + name: OC6M_3 + +TIM2: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + DIER: + _add: + COMDE: + description: COM DMA request enable + bitOffset: 13 + bitWidth: 1 + access: read-write + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + DIER: + _add: + COMDE: + description: COM DMA request enable + bitOffset: 13 + bitWidth: 1 + access: read-write + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/f3_adc.yaml - - ./common_patches/f3_rcc.yaml - - ./common_patches/f3_rcc_i2c3.yaml - - ./common_patches/f3_rcc_delete_cec.yaml - - ./common_patches/f3_syscfg.yaml - - ./common_patches/f3_syscfg_cfgr1_i2c3_fmp.yaml - - ./common_patches/f3_opamp2.yaml - - ./common_patches/f3_comp246.yaml - - ./common_patches/f3_comp2_inp_dac.yaml - - ../peripherals/syscfg/syscfg_f3.yaml - - ../peripherals/syscfg/syscfg_f301.yaml - - ../peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ./common_patches/unprefix_USB_registers.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/rcc/rcc_f3.yaml - - ../peripherals/rcc/rcc_f3_i2s.yaml - - ../peripherals/rcc/rcc_pllsrc_1bit.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - common_patches/f3_dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/comp/comp_f3.yaml - - ../peripherals/opamp/opamp_f3.yaml - - ../peripherals/adc/adc_v3_f3.yaml - - ../peripherals/adc/adc_v3_common_single.yaml - - ../peripherals/adc/adc_v3_common_f3_single.yaml - - ../peripherals/dac/dac_common_1ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - common_patches/f3_flash.yaml - - ../peripherals/flash/flash_f3_common.yaml - - ../peripherals/flash/flash_f3_acr_hlfcya.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_f3.yaml + - patches/nvic/4_prio_bits.yaml + - patches/opamp/f3_opamp2.yaml + - patches/comp/f3_comp246.yaml + - patches/comp/f3_comp2_inp_dac.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f3.yaml + - fields/comp/comp_f3.yaml + - fields/opamp/opamp_f3.yaml diff --git a/devices/stm32f302.yaml b/devices/stm32f302.yaml index bb696db6a..91d603daf 100644 --- a/devices/stm32f302.yaml +++ b/devices/stm32f302.yaml @@ -1,16 +1,143 @@ _svd: ../svd/stm32f302.svd +_delete: + - ADC3 + - ADC4 + - ADC3_4 + +# TIM3, TIM4 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + +_derive: + TIM4: TIM3 + _modify: # Rename in accordance with other devices and reference manual. Flash: name: FLASH -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0365 - TIFRFE: - name: "FRE" + # Rename DAC to DAC1 in accordance with the reference manual. + DAC: + name: DAC1 + SYSCFG_COMP_OPAMP: + name: SYSCFG + groupName: SYSCFG + description: System configuration controller + +ADC1_2: + _include: + - patches/adc/f3_multi_dual.yaml + - fields/adc/adc_v3_common_f3.yaml + +ADC1: + _include: + - patches/adc/offset_en.yaml + - patches/adc/f3.yaml + - patches/adc/jdata.yaml + - patches/adc/split.yaml + - fields/adc/adc_v3_f3.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [1, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +DAC1: + CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: + [1, Timer 3 TRGO event depending on the value of DAC_TRIG_RMP bit in SYSCFG_CFGR1 register (STM32F302x6/8 only)] + Tim15Trgo: [3, Timer 15 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event (STM32F302x6/8 only)] + Exti9: [6, EXTI line 9] + Software: [7, Software trigger] + _include: + - fields/dac/v2.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/f3_offset.yaml + - fields/exti/common.yaml + +FLASH: + _include: + - patches/flash/f3.yaml + - patches/flash/f3_obr_rdptr.yaml + - fields/flash/flash_f3_common.yaml + - fields/flash/acr/hlfcya.yaml + - fields/flash/flash_f3_obr_sram_parity_check.yaml + +FMC: + BCR1: + _add: + WRAPMOD: + description: Wrapped burst mode support + bitOffset: 10 + bitWidth: 1 + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/f3.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +OPAMP: {} + +PWR: {} RCC: APB1RSTR: @@ -67,6 +194,43 @@ RCC: CFGR2: _delete: - ADC34PRES + _include: + - patches/rcc/f3.yaml + - patches/rcc/f3_mco.yaml + - patches/rcc/f3_usb.yaml + - patches/rcc/f3_i2c3.yaml + - patches/rcc/f3_spi4.yaml + - patches/rcc/f3_delete_tim8.yaml + - patches/rcc/f3_cfgr3_tim.yaml + - fields/rcc/rcc_f3.yaml + - fields/rcc/rcc_f3_i2s.yaml + - fields/rcc/rcc_pllsrc_2bit.yaml + - fields/rcc/rcc_f1_f3_usb.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/f3.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0365 + TIFRFE: + name: FRE + +I2S2ext: + _include: + - fields/spi/spi_v2_i2s.yaml + - fields/spi/spi_SR_UDR_CHSIDE.yaml SYSCFG: _delete: @@ -75,93 +239,100 @@ SYSCFG: CFGR1: _delete: - TIM7_DAC2_DMA_RMP + CFGR2: + _modify: + LOCUP_LOCK: + name: LOCKUP_LOCK + BYP_ADD_PAR: + name: BYP_ADDR_PAR + _include: + - patches/syscfg/f3.yaml + - patches/syscfg/f3_cfgr1_mem_mode_3.yaml + - patches/syscfg/f3_cfgr1_i2c3_fmp.yaml + - patches/syscfg/f3_cfgr1_adc2_dac1_rmp.yaml + - fields/syscfg/syscfg_f3.yaml + - fields/syscfg/syscfg_f302.yaml + - fields/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml -_delete: - - ADC3 - - ADC4 - - ADC3_4 +TIM[18]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml -# TIM3, TIM4 are 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 - TIM4: - from: TIM2 +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM2: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + CNT: + _modify: + CNT_or_UIFCPY: + name: UIFCPY + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _strip: USB_ + _include: + - patches/usb/merge_add.yaml + - fields/usb/v1.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/f3_adc.yaml - - ./common_patches/f3_adc_multi_dual.yaml - - ./common_patches/f3_gpio_reset_values.yaml - - ./common_patches/f3_rcc.yaml - - ./common_patches/f3_rcc_mco.yaml - - ./common_patches/f3_rcc_usb.yaml - - ./common_patches/f3_rcc_i2c3.yaml - - ./common_patches/f3_rcc_spi4.yaml - - ./common_patches/f3_rcc_delete_tim8.yaml - - ./common_patches/f3_rcc_cfgr3_tim.yaml - - ./common_patches/f3_syscfg.yaml - - ./common_patches/f3_syscfg_cfgr1_mem_mode_3.yaml - - ./common_patches/f3_syscfg_cfgr1_i2c3_fmp.yaml - - ./common_patches/f3_syscfg_cfgr2.yaml - - ./common_patches/f3_syscfg_cfgr1_adc2_dac1_rmp.yaml - - ./common_patches/f3_opamp12.yaml - - ./common_patches/f3_comp1246.yaml - - ./common_patches/f3_comp2_inp_dac.yaml - - ../peripherals/syscfg/syscfg_f3.yaml - - ../peripherals/syscfg/syscfg_f302.yaml - - ../peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml - - ./common_patches/unprefix_USB_registers.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/rcc/rcc_f3.yaml - - ../peripherals/rcc/rcc_f3_i2s.yaml - - ../peripherals/rcc/rcc_pllsrc_2bit.yaml - - ../peripherals/rcc/rcc_f1_f3_usb.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - common_patches/f3_dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/comp/comp_f3.yaml - - ../peripherals/opamp/opamp_f3.yaml - - ../peripherals/adc/adc_v3_f3.yaml - - ../peripherals/adc/adc_v3_common_f3.yaml - - common_patches/f3_flash.yaml - - common_patches/f3_flash_obr_rdptr.yaml - - ../peripherals/flash/flash_f3_common.yaml - - ../peripherals/flash/flash_f3_obr_sram_parity_check.yaml - - ../peripherals/flash/flash_f3_acr_hlfcya.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_f3.yaml + - patches/nvic/4_prio_bits.yaml + - patches/gpio/f3_reset_values.yaml + - patches/opamp/f3_opamp12.yaml + - patches/comp/f3_comp1246.yaml + - patches/comp/f3_comp2_inp_dac.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f3.yaml + - fields/comp/comp_f3.yaml + - fields/opamp/opamp_f3.yaml diff --git a/devices/stm32f303.yaml b/devices/stm32f303.yaml index 32e6d9b2c..87ec17f7e 100644 --- a/devices/stm32f303.yaml +++ b/devices/stm32f303.yaml @@ -1,16 +1,158 @@ _svd: ../svd/stm32f303.svd +_add: + # DAC2 exists on F303x6/8 and F328x8 devices, and only has one channel. + DAC2: + derivedFrom: DAC1 + baseAddress: "0x40009800" + +# TIM3, TIM4 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + +_derive: + TIM4: TIM3 + _modify: # Rename in accordance with other devices and reference manual. Flash: name: FLASH -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0316 - TIFRFE: - name: "FRE" + # Rename DAC to DAC1 in accordance with the reference manual. + DAC: + name: DAC1 + SYSCFG_COMP_OPAMP: + name: SYSCFG + groupName: SYSCFG + description: System configuration controller + +ADC1_2: + _include: + - patches/adc/f3_multi_dual.yaml + - fields/adc/adc_v3_common_f3.yaml + +ADC1: + _include: + - patches/adc/offset_en.yaml + - patches/adc/f3.yaml + - patches/adc/jdata.yaml + - patches/adc/split.yaml + - fields/adc/adc_v3_f3.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [1, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +DAC1: + CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: [1, Timer 3 TRGO event depending on the value of DAC_TRIG_RMP bit in SYSCFG_CFGR1 register] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim15Trgo: [3, Timer 15 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Software: [7, Software trigger] + _include: + - fields/dac/v2.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/f3_offset.yaml + - fields/exti/common.yaml + +FLASH: + _include: + - patches/flash/f3.yaml + - patches/flash/f3_obr_rdptr.yaml + - fields/flash/flash_f3_common.yaml + - fields/flash/acr/hlfcya.yaml + - fields/flash/flash_f3_obr_sram_parity_check.yaml + +FMC: + BCR1: + _add: + WRAPMOD: + description: Wrapped burst mode support + bitOffset: 10 + bitWidth: 1 + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/f3.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +OPAMP: {} + +PWR: + CSR: + _add: + VREFINTRDYF: + description: Internal voltage reference ready flag + bitOffset: 3 + bitWidth: 1 + access: read-only + EWUP3: + description: Enable WKUP3 pin + bitOffset: 10 + bitWidth: 1 + access: read-write + _include: + - fields/pwr/pwr_v1.yaml RCC: APB1RSTR: @@ -25,128 +167,140 @@ RCC: name: UART4EN USART5EN: name: UART5EN + _include: + - patches/rcc/f3.yaml + - patches/rcc/f3_mco.yaml + - patches/rcc/f3_usb.yaml + - patches/rcc/f3_spi4.yaml + - patches/rcc/f3_tim20.yaml + - patches/rcc/f3_cfgr3_tim.yaml + - fields/rcc/rcc_f3.yaml + - fields/rcc/rcc_f3_i2s.yaml + - fields/rcc/rcc_pllsrc_2bit.yaml + - fields/rcc/rcc_f1_f3_usb.yaml -SYSCFG: - _delete: - _interrupts: - - "COMP*" +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/f3.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0316 + TIFRFE: + name: FRE + +I2S2ext: + _include: + - fields/spi/spi_v2_i2s.yaml + - fields/spi/spi_SR_UDR_CHSIDE.yaml SYSCFG: - _strip: - - SYSCFG_ - _add: - CFGR3: - description: configuration register 3 - addressOffset: 0x50 - size: 0x20 - resetValue: 0x00000200 - access: read-write - fields: - SPI1_RX_DMA_RMP: - description: SPI1_RX DMA remapping bit - bitOffset: 0 - bitWidth: 2 - SPI1_TX_DMA_RMP: - description: SPI1_TX DMA remapping bit - bitOffset: 2 - bitWidth: 2 - I2C1_RX_DMA_RMP: - description: I2C1_RX DMA remapping bit - bitOffset: 4 - bitWidth: 2 - I2C1_TX_DMA_RMP: - description: I2C1_TX DMA remapping bit - bitOffset: 6 - bitWidth: 2 - ADC2_DMA_RMP: - description: ADC2 DMA remapping bit - bitOffset: 8 - bitWidth: 2 + CFGR2: + _modify: + LOCUP_LOCK: + name: LOCKUP_LOCK + BYP_ADD_PAR: + name: BYP_ADDR_PAR + _include: + - patches/syscfg/f3.yaml + - patches/syscfg/f3_cfgr1_mem_mode_3.yaml + - patches/syscfg/f3_cfgr1_dac2_ch1_dma_rmp.yaml + - patches/syscfg/f3_cfgr1_i2c3_fmp.yaml + - patches/syscfg/f3_cfgr1_timx_dacx_chx_dma_rmp.yaml + - patches/syscfg/f3_cfgr1_adc2_dac1_rmp.yaml + - patches/syscfg/f3_rcr_page8-15.yaml + - fields/syscfg/syscfg_f3.yaml + - fields/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml + - fields/syscfg/syscfg_f303_3x8.yaml -# TIM3, TIM4 are 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 - TIM4: - from: TIM2 +TIM[18]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM2: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + CNT: + _modify: + CNT_or_UIFCPY: + name: UIFCPY + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _strip: USB_ + _include: + - patches/usb/merge_add.yaml + - fields/usb/v1.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/f3_adc.yaml - - ./common_patches/f3_adc_multi_dual.yaml - - ./common_patches/f3_gpio_reset_values.yaml - - ./common_patches/f3_rcc.yaml - - ./common_patches/f3_rcc_mco.yaml - - ./common_patches/f3_rcc_usb.yaml - - ./common_patches/f3_rcc_spi4.yaml - - ./common_patches/f3_rcc_tim20.yaml - - ./common_patches/f3_rcc_cfgr3_tim.yaml - - ./common_patches/f3_syscfg.yaml - - ./common_patches/f3_syscfg_cfgr1_mem_mode_3.yaml - - ./common_patches/f3_syscfg_cfgr1_dac2_ch1_dma_rmp.yaml - - ./common_patches/f3_syscfg_cfgr1_i2c3_fmp.yaml - - ./common_patches/f3_syscfg_cfgr1_timx_dacx_chx_dma_rmp.yaml - - ./common_patches/f3_syscfg_cfgr1_adc2_dac1_rmp.yaml - - ./common_patches/f3_syscfg_cfgr2.yaml - - ./common_patches/f3_syscfg_cfgr4.yaml - - ./common_patches/f3_syscfg_rcr_page8-15.yaml - - ../peripherals/syscfg/syscfg_f3.yaml - - ../peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml - - ../peripherals/syscfg/syscfg_f303_3x8.yaml - - ./common_patches/f3_opamp1234.yaml - - ./common_patches/f3_comp1234567.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml - - ./common_patches/unprefix_USB_registers.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/rcc/rcc_f3.yaml - - ../peripherals/rcc/rcc_f3_i2s.yaml - - ../peripherals/rcc/rcc_pllsrc_2bit.yaml - - ../peripherals/rcc/rcc_f1_f3_usb.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - common_patches/f3_dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/comp/comp_f3.yaml - - ../peripherals/opamp/opamp_f3.yaml - - ../peripherals/adc/adc_v3_f3.yaml - - ../peripherals/adc/adc_v3_common_f3.yaml - - common_patches/f3_flash.yaml - - common_patches/f3_flash_obr_rdptr.yaml - - ../peripherals/flash/flash_f3_common.yaml - - ../peripherals/flash/flash_f3_obr_sram_parity_check.yaml - - ../peripherals/flash/flash_f3_acr_hlfcya.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_f3.yaml + - patches/nvic/4_prio_bits.yaml + - patches/gpio/f3_reset_values.yaml + - patches/opamp/f3_opamp1234.yaml + - patches/comp/f3_comp1234567.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f3.yaml + - fields/comp/comp_f3.yaml + - fields/opamp/opamp_f3.yaml diff --git a/devices/stm32f373.yaml b/devices/stm32f373.yaml index 4f350ef27..8634ff581 100644 --- a/devices/stm32f373.yaml +++ b/devices/stm32f373.yaml @@ -8,6 +8,8 @@ _copy: from: GPIOB _modify: + DAC2: + groupName: DAC ADC: name: ADC1 # Rename in accordance with other devices and reference manual. @@ -15,6 +17,186 @@ _modify: name: FLASH GPIOD: baseAddress: 0x48000C00 + SYSCFG_COMP_OPAMP: + name: SYSCFG + groupName: SYSCFG + description: System configuration controller + +ADC1: + _include: + - fields/adc/adc_f1_f37x.yaml + - collect/adc/jofr_jdr.yaml + CR2: + EXTSEL: + Tim19Trgo: [0, Timer 19 TRGO event] + Tim19Cc3: [1, Timer 19 CC3 event] + Tim19Cc4: [2, Timer 19 CC4 event] + Tim2Cc2: [3, Timer 2 CC2 event] + Tim3Trgo: [4, Timer 3 TRGO event] + Tim4Cc4: [5, Timer 4 CC4 event] + Exti11: [6, EXTI line 11] + Swstart: [7, SWSTART] + JEXTSEL: + Tim19Cc1: [0, Timer 19 CC1 event] + Tim19Cc2: [1, Timer 19 CC2 event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim2Cc1: [3, Timer 2 CC1 event] + Tim3Cc4: [4, Timer 3 CC4 event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti15: [6, EXTI line15] + Jswstart: [7, JSWSTART] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN: + _delete: + _interrupts: + - COMP1_2 + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - patches/cec/cfgr.yaml + - fields/hdmi_cec.yaml + +COMP: + _add: + _interrupts: + COMP1_2_3: + description: COMP1_2_3 interrupt combined with EXTI lines 21, 22 + value: 64 + CSR: + _add: + COMP1_INP_DAC: + description: Comparator 1 non inverting input connection to DAC output + bitOffset: 1 + bitWidth: 1 + access: read-write + +CRC: + _include: + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +DAC1: + CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: [1, Timer 3 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim5Trgo: [3, Timer 5 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Software: [7, Software trigger] + +DAC2: + CR: + _merge: + WAVE1: WAVE* + MAMP1: MAMP* + TSEL1: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: [1, Timer 3 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim18Trgo: [3, Timer 18 TRGO event] + Tim2Trgo: [4, Timer 2 TRGO event] + Tim4Trgo: [5, Timer 4 TRGO event] + Exti9: [6, EXTI line 9] + Software: [7, Software trigger] + +DAC[12]: + _include: + - fields/dac/v2.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + +FLASH: + _modify: + OBR: + resetValue: 0xFFFFFF0F + SR: + _modify: + WRPRT: + name: WRPRTERR + CR: + _modify: + FORCE_OPTLOAD: + name: OBL_LAUNCH + OBR: + _modify: + BOOT1: + name: nBOOT1 + _include: + - patches/flash/f3_obr_rdptr.yaml + - fields/flash/flash_f3_common.yaml + - fields/flash/flash_f3_obr_sram_parity_check.yaml + - fields/flash/flash_f3_obr_vdd_monitor.yaml + +GPIOA: + _modify: + MODER: + resetValue: "0xa8000000" + OSPEEDR: + resetValue: "0x0C000000" + PUPDR: + resetValue: "0x64000000" + +GPIOB: + _modify: + MODER: + resetValue: "0x00000280" + OSPEEDR: + resetValue: "0x000000C0" + PUPDR: + resetValue: "0x00000100" + +GPIOD: + _modify: + MODER: + resetValue: "0x00000000" + OSPEEDR: + resetValue: "0x00000000" + PUPDR: + resetValue: "0x00000000" + +GPIO[ABCD]: + _include: + - fields/gpio/v2/f3.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCD]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: {} RCC: APB2RSTR: @@ -35,6 +217,29 @@ RCC: name: SDADC2EN SDAD3EN: name: SDADC3EN + _include: + - patches/rcc/f3.yaml + - patches/rcc/f3_dac3_dac2.yaml + - fields/rcc/rcc_f373.yaml + - fields/rcc/rcc_pllsrc_1bit.yaml + - fields/rcc/rcc_f1_f3_usb.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/f3.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDADC1: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml SYSCFG: _delete: @@ -66,121 +271,81 @@ SYSCFG: CFGR2: _delete: - BYP_ADD_PAR + _modify: + LOCUP_LOCK: + name: LOCKUP_LOCK + _include: + - patches/syscfg/f3.yaml + - fields/syscfg/syscfg_f3.yaml + - fields/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml + - fields/syscfg/syscfg_f37x.yaml -COMP: - _add: - _interrupts: - COMP1_2_3: - description: COMP1_2_3 interrupt combined with EXTI lines 21, 22 - value: 64 - CSR: - _add: - COMP1_INP_DAC: - description: Comparator 1 non inverting input connection to DAC output - bitOffset: 1 - bitWidth: 1 - access: read-write +TIM[25]: + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml -CAN: - _delete: - _interrupts: - - COMP1_2 +TIM5: + _include: collect/tim/tim5_derive.yaml -FLASH: - SR: - _modify: - WRPRT: - name: "WRPRTERR" - CR: - _modify: - FORCE_OPTLOAD: - name: "OBL_LAUNCH" - OBR: - _modify: - resetValue: 0xFFFFFF0F - BOOT1: - name: "nBOOT1" +TIM3: + _include: + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml -GPIOA: - _modify: - MODER: - resetValue: "0xa8000000" - OSPEEDR: - resetValue: "0x0C000000" - PUPDR: - resetValue: "0x64000000" +TIM6: + _include: + - fields/tim/v1/tim6.yaml -GPIOB: - _modify: - MODER: - resetValue: "0x00000280" - OSPEEDR: - resetValue: "0x000000C0" - PUPDR: - resetValue: "0x00000100" +TIM12: + _include: + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml -GPIOD: - _modify: - MODER: - resetValue: "0x00000000" - OSPEEDR: - resetValue: "0x00000000" - PUPDR: - resetValue: "0x00000000" +TIM13: + _include: + - fields/tim/v1/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - fields/tim/v1/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v1/tim16.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _strip: USB_ + _include: + - patches/usb/merge_add.yaml + - fields/usb/v1.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/f3_rcc.yaml - - ./common_patches/f3_rcc_usb.yaml - - ./common_patches/f3_rcc_dac3_dac2.yaml - - ./common_patches/f3_syscfg.yaml - - ./common_patches/f3_syscfg_cfgr2.yaml - - ../peripherals/syscfg/syscfg_f3.yaml - - ../peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml - - ../peripherals/syscfg/syscfg_f37x.yaml - - ./common_patches/f0_comp_common.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ./common_patches/unprefix_USB_registers.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/gpio/gpio_v2_f373.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed.yaml - - ../peripherals/rcc/rcc_f373.yaml - - ../peripherals/rcc/rcc_pllsrc_1bit.yaml - - ../peripherals/rcc/rcc_f1_f3_usb.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - ../peripherals/adc/adc_array.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - common_patches/f3_dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/adc/adc_f37x.yaml - - common_patches/f3_flash_obr_rdptr.yaml - - ../peripherals/flash/flash_f3_common.yaml - - ../peripherals/flash/flash_f3_obr_sram_parity_check.yaml - - ../peripherals/flash/flash_f3_obr_vdd_monitor.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_f3.yaml + - patches/nvic/4_prio_bits.yaml + - patches/comp/f0_common.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f3.yaml diff --git a/devices/stm32f3x4.yaml b/devices/stm32f3x4.yaml index b45a235c6..63f3bf123 100644 --- a/devices/stm32f3x4.yaml +++ b/devices/stm32f3x4.yaml @@ -5,9 +5,118 @@ _modify: Flash: name: FLASH + ADC_Common: + name: ADC1_2 + SYSCFG_COMP_OPAMP: + name: SYSCFG + groupName: SYSCFG + description: System configuration controller + _rebase: SPI1: SPI3 +ADC1_2: + _strip: ADC1_ + _include: fields/adc/adc_v3_common_f3.yaml + +ADC1: + _include: + - patches/adc/offset_en.yaml + - patches/adc/f3.yaml + - patches/adc/jdata.yaml + - patches/adc/split.yaml + - fields/adc/adc_v3_f3.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [1, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN: + _delete: + _interrupts: + - CAN_SCE + _add: + _interrupts: + CAN_SCE: + description: CAN_SCE interrupt + value: 22 + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC1: + CR: + TSEL?: + Tim6Trgo: [0, Timer 6 TRGO event] + Tim3Trgo: [1, Timer 3 TRGO event] + Tim7Trgo: [2, Timer 7 TRGO event] + Tim15Trgo: [3, Timer15 TRGO or HRTM1_DACTRG1 event] + Tim2Trgo: [4, Timer 2 TRGO event] + DacTrg2: [5, HRTIM1_DACTRG2 (DAC1) or HRTM1_DACTRG3 (DAC2) event] + Exti9: [6, EXTI line 9] + Software: [7, Software trigger] + _include: + - fields/dac/v2.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/f3_offset.yaml + - fields/exti/common.yaml + +FLASH: + _include: + - patches/flash/f3.yaml + - patches/flash/f3_obr_rdptr.yaml + - fields/flash/acr/hlfcya.yaml + - fields/flash/flash_f3_common.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/f3.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - patches/i2c/merge_OAR1_OA1x_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +OPAMP: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + RCC: CFGR: _delete: @@ -47,8 +156,6 @@ RCC: _delete: - SPI2EN - SPI3EN - - UART4EN - - UART5EN - I2C2EN - USBEN - TIM4EN @@ -75,14 +182,51 @@ RCC: - USART3SW - UART4SW - UART5SW + _include: + - patches/rcc/f3.yaml + - patches/rcc/f3_mco.yaml + - patches/rcc/f3_delete_tim8.yaml + - fields/rcc/rcc_f3.yaml + - fields/rcc/rcc_pllsrc_1bit.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/f3.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI2: + CR1: + _modify: + DFF: + name: CRCL + description: CRC length + +SPI[12]: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + SR: + _modify: + TIFRFE: + name: FRE + description: Frame format error SYSCFG: - _strip: - - SYSCFG_ CFGR1: _delete: - USB_IT_RMP - ADC24_DMA_RMP + CFGR2: + _modify: + LOCUP_LOCK: + name: LOCKUP_LOCK + BYP_ADD_PAR: + name: BYP_ADDR_PAR CFGR3: _delete: - ADC2_DMA_RMP* @@ -97,189 +241,81 @@ SYSCFG: bitWidth: 2 RCR: _delete: - - PAGE4_WP - - PAGE5_WP - - PAGE6_WP - - PAGE7_WP - -ADC_Common: - _strip: - - ADC1_ - -HRTIM_Common: - _modify: - BDMUPDR: - name: BDMUPR - _interrupts: - HRTIM1_FLT: - name: HRTIM_FLT - value: 73 - IER: - _modify: - SYSFLTE: - name: SYSFLTIE - ICR: - _modify: - SYSFLTC: - access: write-only + - PAGE[4-7]_WP + _include: + - patches/syscfg/f3.yaml + - patches/syscfg/f3_cfgr1_dac2_ch1_dma_rmp.yaml + - patches/syscfg/f3_cfgr1_timx_dacx_chx_dma_rmp.yaml + - fields/syscfg/syscfg_f3.yaml + - fields/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml + - fields/syscfg/syscfg_f3x4.yaml -HRTIM_Master: - _modify: - MDIER4: - name: MDIER - _interrupts: - HRTIM1_MST: - name: HRTIM_MST - value: 67 - MCR: - _modify: - SYNC_SRC: - name: SYNCSRC - SYNC_OUT: - name: SYNCOUT - SYNC_IN: - name: SYNCIN - CK_PSC: - name: CKPSC - -HRTIM_TIMA: - _modify: - _interrupts: - HRTIM1_TIMA: - value: 68 - name: HRTIM_TIMA -HRTIM_TIMB: - _modify: - _interrupts: - HRTIM_TIMB: - value: 69 -HRTIM_TIMC: - _modify: - _interrupts: - HRTIM1_TIMC: - name: HRTIM_TIMC - value: 70 -HRTIM_TIMD: - _modify: - _interrupts: - HRTIM1_TIMD: - name: HRTIM_TIMD - value: 71 -HRTIM_TIME: - _modify: - _interrupts: - HRTIM_TIME: - value: 72 - -"HRTIM_TIM[ABCDE]": - _modify: - TIMADIER5: - name: TIMADIER - TIMBDIER5: - name: TIMBDIER - TIMCDIER5: - name: TIMCDIER - TIMDDIER5: - name: TIMDDIER - TIMEDIER5: - name: TIMEDIER - CNTR: - name: CNTBR - "TIM[ABCDE]CR": - _modify: - CK_PSCx: - name: CKPSCx - "TIM[ABCDE]DIER": - _modify: - SET1xDE: - name: SETx1DE - SET1xIE: - name: SETx1IE - "CHP[ABCDE]R": - _modify: - CHPDTY: - name: CARDTY - CHPFRQ: - name: CARFRQ - "CPT[12][ABCDE]CR": - _modify: - UDPCPT: - name: UPDCPT +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml -CAN: - _delete: - _interrupts: - - CAN_SCE - _add: - _interrupts: - CAN_SCE: - description: CAN_SCE interrupt - value: 22 +TIM2: + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/rename_f0_SPI_registers.yaml - - ./common_patches/f3_adc.yaml - - ./common_patches/f3_rcc.yaml - - ./common_patches/f3_rcc_mco.yaml - - ./common_patches/f3_rcc_delete_tim8.yaml - - ./common_patches/f3_syscfg.yaml - - ./common_patches/f3_syscfg_cfgr1_dac2_ch1_dma_rmp.yaml - - ./common_patches/f3_syscfg_cfgr1_timx_dacx_chx_dma_rmp.yaml - - ./common_patches/f3_syscfg_cfgr2.yaml - - ../peripherals/syscfg/syscfg_f3.yaml - - ../peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml - - ../peripherals/syscfg/syscfg_f3x4.yaml - - ./common_patches/f3_opamp2.yaml - - ./common_patches/f3_comp246.yaml - - ./common_patches/f3_comp246_inmsel3.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/rcc/rcc_f3.yaml - - ../peripherals/rcc/rcc_pllsrc_1bit.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/f3_dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/comp/comp_f3.yaml - - ../peripherals/opamp/opamp_f3.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/adc/adc_v3_f3.yaml - - ../peripherals/adc/adc_v3_common_f3.yaml - - ../peripherals/hrtim/hrtim.yaml - - common_patches/f3_flash.yaml - - common_patches/f3_flash_obr_rdptr.yaml - - ../peripherals/flash/flash_f3_common.yaml - - ../peripherals/flash/flash_f3_acr_hlfcya.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_f3.yaml + - patches/nvic/4_prio_bits.yaml + - patches/opamp/f3_opamp2.yaml + - patches/comp/f3_comp246.yaml + - patches/comp/f3_comp246_inmsel3.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f3.yaml + - fields/comp/comp_f3.yaml + - fields/opamp/opamp_f3.yaml + - patches/hrtim/v1.yaml + - patches/hrtim/f3_interrupts.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_f3.yaml + - collect/hrtim/f3.yaml diff --git a/devices/stm32f3x8.yaml b/devices/stm32f3x8.yaml deleted file mode 100644 index 90d77c3af..000000000 --- a/devices/stm32f3x8.yaml +++ /dev/null @@ -1,261 +0,0 @@ -_svd: ../svd/stm32f3x8.svd - -_modify: - # Rename in accordance with other devices and reference manual. - Flash: - name: FLASH - -_delete: - - ADC1 - - ADC2 - -_copy: - ADC1: - from: ../svd/stm32f303.svd:ADC1 - ADC2: - from: ../svd/stm32f303.svd:ADC2 - ADC3: - from: ../svd/stm32f303.svd:ADC3 - ADC4: - from: ../svd/stm32f303.svd:ADC4 - ADC1_2: - from: ../svd/stm32f303.svd:ADC1_2 - ADC3_4: - from: ../svd/stm32f303.svd:ADC3_4 - -RCC: - CFGR: - _delete: - - ADCPRE - - SDPRE - _add: - I2SSRC: - description: I2S external clock source selection - bitOffset: 23 - bitWidth: 1 - _modify: - PLLSRC: - bitOffset: 15 - bitWidth: 2 - APB2RSTR: - _delete: - - ADCRST - - TIM19RST - - SDAD?RST - _add: - TIM1RST: - description: TIM1 timer reset - bitOffset: 11 - bitWidth: 1 - TIM8RST: - description: TIM8 timer reset - bitOffset: 13 - bitWidth: 1 - APB1RSTR: - _delete: - - TIM5RST - - TIM12RST - - TIM13RST - - TIM14RST - - TIM18RST - _add: - UART4RST: - description: UART4 reset - bitOffset: 19 - bitWidth: 1 - UART5RST: - description: UART5 reset - bitOffset: 20 - bitWidth: 1 - AHBENR: - _add: - IOPHEN: - description: I/O port H clock enable - bitOffset: 16 - bitWidth: 1 - IOPGEN: - description: I/O port G clock enable - bitOffset: 23 - bitWidth: 1 - ADC12EN: - description: ADC1 and ADC2 enable - bitOffset: 28 - bitWidth: 1 - ADC34EN: - description: ADC3 and ADC4 enable - bitOffset: 29 - bitWidth: 1 - APB2ENR: - _delete: - - ADCEN - - TIM19EN - - DBGMCUEN - - SDAD?EN - _add: - TIM8EN: - description: TIM8 timer clock enable - bitOffset: 13 - bitWidth: 1 - APB1ENR: - _delete: - - TIM5EN - - TIM12EN - - TIM13EN - - TIM14EN - - TIM18EN - _add: - UART4EN: - description: UART4 clock enable - bitOffset: 19 - bitWidth: 1 - UART5EN: - description: UART5 clock enable - bitOffset: 20 - bitWidth: 1 - AHBRSTR: - _add: - IOPHRST: - description: I/O port H reset - bitOffset: 16 - bitWidth: 1 - IOPGRST: - description: I/O port G reset - bitOffset: 23 - bitWidth: 1 - ADC12RST: - description: ADC1 and ADC2 reset - bitOffset: 28 - bitWidth: 1 - ADC34RST: - description: ADC3 and ADC4 reset - bitOffset: 29 - bitWidth: 1 - CFGR2: - _add: - ADC12PRES: - description: ADC1 and ADC2 reset - bitOffset: 4 - bitWidth: 5 - ADC34PRES: - description: ADC3 and ADC4 reset - bitOffset: 9 - bitWidth: 5 - CFGR3: - _add: - TIM1SW: - description: Timer1 clock source selection - bitOffset: 8 - bitWidth: 1 - TIM8SW: - description: Timer8 clock source selection - bitOffset: 9 - bitWidth: 1 - UART4SW: - description: UART4 clock source selection - bitOffset: 20 - bitWidth: 2 - UART5SW: - description: UART5 clock source selection - bitOffset: 22 - bitWidth: 2 - -SYSCFG: - _strip: - - SYSCFG_ - CFGR3: - _delete: - - ADC2_DMA_RMP* - - DAC1_TRIG* - _add: - I2C1_TX_DMA_RMP: - description: I2C1_TX DMA remapping bit - bitOffset: 6 - bitWidth: 2 - ADC2_DMA_RMP: - description: ADC2 DMA remapping bit - bitOffset: 8 - bitWidth: 2 - -EXTI: - _delete: - _interrupts: - - COMP7 - -_include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_I2C_CR2_SADDx_fields.yaml - - ./common_patches/merge_I2C_OAR1_OA1x_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/f3_adc.yaml - - ./common_patches/f3_adc_multi_dual.yaml - - ./common_patches/f3_gpio_reset_values.yaml - - ./common_patches/f3_rcc.yaml - - ./common_patches/f3_rcc_mco.yaml - - ./common_patches/f3_rcc_usb.yaml - - ./common_patches/f3_rcc_i2c3.yaml - - ./common_patches/f3_rcc_spi4.yaml - - ./common_patches/f3_rcc_tim20.yaml - - ./common_patches/f3_rcc_dac3_dac2.yaml - - ./common_patches/f3_rcc_delete_cec.yaml - - ./common_patches/f3_rcc_cfgr3_tim.yaml - - ./common_patches/f3_syscfg.yaml - - ./common_patches/f3_syscfg_cfgr1_mem_mode_3.yaml - - ./common_patches/f3_syscfg_cfgr1_dac2_ch1_dma_rmp.yaml - - ./common_patches/f3_syscfg_cfgr1_i2c3_fmp.yaml - - ./common_patches/f3_syscfg_cfgr1_timx_dacx_chx_dma_rmp.yaml - - ./common_patches/f3_syscfg_cfgr2.yaml - - ./common_patches/f3_syscfg_cfgr4.yaml - - ./common_patches/f3_syscfg_rcr_page8-15.yaml - - ./common_patches/f3_syscfg_cfgr1_adc2_dac1_rmp.yaml - - ./common_patches/f3_opamp1234.yaml - - ./common_patches/f3_comp1234567.yaml - - ../peripherals/syscfg/syscfg_f3.yaml - - ../peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml - - ../peripherals/syscfg/syscfg_f303_3x8.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - ./common_patches/unprefix_USB_registers.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/rcc/rcc_f3.yaml - - ../peripherals/rcc/rcc_f3_i2s.yaml - - ../peripherals/rcc/rcc_pllsrc_2bit.yaml - - ../peripherals/rcc/rcc_f1_f3_usb.yaml - - common_patches/dma/dma_v1.yaml - - ../peripherals/dma/dma_v1.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - common_patches/f3_dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/comp/comp_f3.yaml - - ../peripherals/opamp/opamp_f3.yaml - - ../peripherals/adc/adc_v3_f3.yaml - - ../peripherals/adc/adc_v3_common_f3.yaml - - common_patches/f3_flash.yaml - - common_patches/f3_flash_obr_rdptr.yaml - - ../peripherals/flash/flash_f3_common.yaml - - ../peripherals/flash/flash_f3_acr_hlfcya.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_f3.yaml diff --git a/devices/stm32f401.yaml b/devices/stm32f401.yaml index 3a144c15b..37a944c13 100644 --- a/devices/stm32f401.yaml +++ b/devices/stm32f401.yaml @@ -1,16 +1,33 @@ _svd: ../svd/stm32f401.svd +_delete: + - TIM8 + _rebase: # Make I2C1 the base type I2C1: I2C3 SPI1: I2S2ext -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0368 - TIFRFE: - name: "FRE" +ADC_Common: + CCR: + _delete: + - DMA + - DDS + - DELAY + _delete: + - CSR + _include: + - fields/adc/adc_v2_common.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_b.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml CRC: # The SVD calls the RESET field "CR", fix per RM0368 @@ -18,126 +35,213 @@ CRC: _modify: CR: name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml -USART1: - # Add the missing USART interrupts - _add: +DBGMCU: {} + +DMA2: + _include: + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr/sprmod.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + +GPIOC: + _delete: _interrupts: - USART1: - description: USART1 global interrupt - value: 37 - USART2: - description: USART2 global interrupt - value: 38 - USART6: - description: USART6 global interrupt - value: 71 + - TIM1_UP_TIM10 + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - patches/i2c/v1_fltr.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_v1_novbussens.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + CR: + _add: + MRLVDS: + description: Main regulator Low Voltage in Deep Sleep + bitOffset: 11 + bitWidth: 1 + LPLVDS: + description: Low-power regulator Low Voltage in Deep Sleep + bitOffset: 10 + bitWidth: 1 + _include: + - patches/pwr/f4.yaml + - fields/pwr/pwr_f401.yaml +RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + _include: + - patches/rcc/spi4.yaml + - patches/rcc/rename_plli2scfgr.yaml + - patches/rcc/f4_dckcfgr.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0368 + TIFRFE: + name: FRE + +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f401_f411.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml TIM3: - # Add the missing TIM4 and TIM5 interrupts - _add: - _interrupts: - TIM4: - description: TIM4 global interrupt - value: 30 - TIM5: - description: TIM5 global interrupt - value: 50 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml -DMA2: - # Add the missing DMA1_STREAM0..7 and DMA2_STREAM0..7 interruptsinterrupts - _add: - _interrupts: - DMA1_STREAM0: - description: DMA1_STREAM0 global interrupt - value: 11 - DMA1_STREAM1: - description: DMA1_STREAM1 global interrupt - value: 12 - DMA1_STREAM2: - description: DMA1_STREAM2 global interrupt - value: 13 - DMA1_STREAM3: - description: DMA1_STREAM3 global interrupt - value: 14 - DMA1_STREAM4: - description: DMA1_STREAM4 global interrupt - value: 15 - DMA1_STREAM5: - description: DMA1_STREAM5 global interrupt - value: 16 - DMA1_STREAM6: - description: DMA1_STREAM6 global interrupt - value: 17 - DMA1_STREAM7: - description: DMA1_STREAM7 global interrupt - value: 47 - DMA2_STREAM0: - description: DMA2_STREAM0 global interrupt - value: 56 - DMA2_STREAM1: - description: DMA2_STREAM1 global interrupt - value: 57 - DMA2_STREAM2: - description: DMA2_STREAM2 global interrupt - value: 58 - DMA2_STREAM3: - description: DMA2_STREAM3 global interrupt - value: 59 - DMA2_STREAM4: - description: DMA2_STREAM4 global interrupt - value: 60 - DMA2_STREAM5: - description: DMA2_STREAM5 global interrupt - value: 68 - DMA2_STREAM6: - description: DMA2_STREAM6 global interrupt - value: 69 - DMA2_STREAM7: - description: DMA2_STREAM7 global interrupt - value: 70 +TIM9: + _delete: CR2 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: collect/tim/tim11_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/rcc_spi4.yaml - - common_patches/rcc_rename_plli2scfgr.yaml - - common_patches/f4_rcc_dckcfgr.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/f4_adc_no_csr.yaml - - common_patches/f4_adc_single_ccr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_fixes_v1.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/flash/flash_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/sdio/sdio_f4.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml + - patches/i2c/v1_fltr.yaml diff --git a/devices/stm32f405.yaml b/devices/stm32f405.yaml index b54f2315e..832c151db 100644 --- a/devices/stm32f405.yaml +++ b/devices/stm32f405.yaml @@ -1,5 +1,12 @@ _svd: ../svd/stm32f405.svd +_delete: + # STM32F405 doesn't have ethernet, but the SVD does + - Ethernet_MAC + - Ethernet_MMC + - Ethernet_DMA + - Ethernet_PTP + _rebase: # Make I2C1 the base type I2C1: I2C3 @@ -10,15 +17,313 @@ _modify: # we'll prefer the more sensible (and better for sorting) ADC_Common C_ADC: name: ADC_Common + SAI1: + groupName: SAI + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + # The SVD calls the RESET field "CR", fix per RM0090 + CR: + _modify: + CR: + name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_8_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - collect/flash/optcr/nwrp.yaml + +FSMC: + _modify: + BWTR3: + addressOffset: 0x114 + alternateRegister: "" + BWTR4: + _from: BWTR1 + addressOffset: 0x11C + alternateRegister: "" + _include: + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + - collect/fsmc/sd.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_v1_novbussens.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_v1_device.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hs_v1_global.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hs_v1_f4_host.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: + _include: + - patches/usb_otg/hs_v1_pwrclk.yaml -"SPI*": +PWR: + CR: + _add: + VOS: + description: Regulator voltage scaling output selection + bitOffset: 14 + bitWidth: 1 + _include: + - patches/pwr/f4.yaml + - fields/pwr/pwr_f405_f415_f407_f417.yaml + +# All of these fields and registers only concern Ethernet. +# They are present in the SVD for stm32f405, but the stm32f405 +# doesn't actually have ethernet. +RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST + AHB1ENR: + _delete: + - ETHMACPTPEN + - ETHMACRXEN + - ETHMACTXEN + - ETHMACEN + AHB1LPENR: + _delete: + - ETHMACPTPLPEN + - ETHMACRXLPEN + - ETHMACTXLPEN + - ETHMACLPEN + AHB1RSTR: + _delete: + - ETHMACRST + _include: + - patches/rcc/rename_plli2scfgr.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + +RNG: + _include: fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/f4_cr.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml SR: _modify: # This field has the wrong name in the SVD compared to RM0090 TIFRFE: - name: "FRE" + name: FRE + +SYSCFG: + # The PMC register is used to configure MII or RMII mode + # for ethernet, which stm32f405 doesn't have. + _delete: PMC + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f405.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +# We need to patch ITR1_RMP because it contains a +# PTP variant, but stm32f405 doesn't have PTP. +TIM2: + OR: + ITR1_RMP: + _replace_enum: + TIM8_TRGOUT: [0, TIM8 trigger output is connected to TIM2_ITR1 input] + OTG_FS_SOF: [2, OTG FS SOF is connected to the TIM2_ITR1 input] + OTG_HS_SOF: [3, OTG HS SOF is connected to the TIM2_ITR1 input] + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml -"TIM1[01]": +TIM9: + _delete: CR2 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml CR1: _add: # This field is missing from TIM10 and TIM11 compared to RM0090 @@ -28,94 +333,31 @@ _modify: bitWidth: 1 access: read-write -CRC: - # The SVD calls the RESET field "CR", fix per RM0090 - CR: - _modify: - CR: - name: RESET +TIM11: + _include: collect/tim/tim11_derive.yaml -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v2.yaml - - common_patches/rcc_rename_plli2scfgr.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - common_patches/fsmc/fsmc_nand_v1.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/sdio/sdio_f4.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_opm.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/hash/hash.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_fixes_v1.yaml - - common_patches/usb_otg/otg_hs_remove_prefix.yaml - - common_patches/usb_otg/otg_hs_fixes_v1.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/rng/rng_v1.yaml - - common_patches/f4_rtc_cr.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f407.yaml b/devices/stm32f407.yaml index e86621cdc..f98c0fa91 100644 --- a/devices/stm32f407.yaml +++ b/devices/stm32f407.yaml @@ -10,15 +10,290 @@ _modify: # we'll prefer the more sensible (and better for sorting) ADC_Common C_ADC: name: ADC_Common + SAI1: + groupName: SAI -"SPI*": +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + # The SVD calls the RESET field "CR", fix per RM0090 + CR: + _modify: + CR: + name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +#Ethernet_DMA: {} +#Ethernet_MAC: {} +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +FLASH: + _include: + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_8_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - collect/flash/optcr/nwrp.yaml + +FSMC: + _modify: + BWTR3: + addressOffset: 0x114 + alternateRegister: "" + BWTR4: + _from: BWTR1 + addressOffset: 0x11C + alternateRegister: "" + _include: + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + - collect/fsmc/sd.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_v1_novbussens.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_v1_device.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hs_v1_global.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hs_v1_f4_host.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: + _include: + - patches/usb_otg/hs_v1_pwrclk.yaml + +PWR: + CR: + _add: + VOS: + description: Regulator voltage scaling output selection + bitOffset: 14 + bitWidth: 1 + _include: + - patches/pwr/f4.yaml + - fields/pwr/pwr_f405_f415_f407_f417.yaml + +RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST + _include: + - patches/rcc/rename_plli2scfgr.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + +RNG: + _include: fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/f4_cr.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml SR: _modify: # This field has the wrong name in the SVD compared to RM0090 TIFRFE: - name: "FRE" + name: FRE + +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f415_f407_f417.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: patches/tim/tim2_itr1_rmp.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml -"TIM1[01]": +TIM9: + _delete: CR2 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml CR1: _add: # This field is missing from TIM10 and TIM11 compared to RM0090 @@ -28,103 +303,42 @@ _modify: bitWidth: 1 access: read-write -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" +TIM11: + _include: collect/tim/tim11_derive.yaml -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml -CRC: - # The SVD calls the RESET field "CR", fix per RM0090 - CR: - _modify: - CR: - name: RESET +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/f2_f4_ethernet.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v2.yaml - - common_patches/rcc_rename_plli2scfgr.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - common_patches/fsmc/fsmc_nand_v1.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_opm.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/flash/flash_v1.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/hash/hash.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_fixes_v1.yaml - - common_patches/usb_otg/otg_hs_remove_prefix.yaml - - common_patches/usb_otg/otg_hs_fixes_v1.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/rng/rng_v1.yaml - - common_patches/f4_rtc_cr.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/sdio/sdio_f4.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/ethernet/f2_f4.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/dbgmcu/dbgmcu.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f410.yaml b/devices/stm32f410.yaml index 5f66e553e..4e53a1212 100644 --- a/devices/stm32f410.yaml +++ b/devices/stm32f410.yaml @@ -6,186 +6,296 @@ _rebase: # Make DMA1 the base type DMA1: DMA2 -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0401 - TIFRFE: - name: "FRE" - _add: - _interrupts: - SPI5: - description: "SPI 5 global interrupt" - value: 85 - - _modify: I2C4: # Rename I2C4 to FMPI2C1 to disambiguate from non-FMP I2C name: FMPI2C1 +ADC_Common: + CSR: + _delete: + - "*2" + - "*3" + CCR: + _delete: + - DMA + - DDS + - DELAY + _include: + - fields/adc/adc_v2_common_single.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_a.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + CRC: # The SVD calls the RESET field "CR", fix per RM0401 CR: _modify: CR: name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + CR: + _delete: "*2" + TSEL?: + Tim5Trgo: [3, Timer 5 TRGO event] + Exti9: [6, EXTI line 9] + SOFTWARE: [7, Software trigger] + _include: + - fields/dac/v2.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + _add: + _interrupts: + EXTI19: + description: EXTI Line 19 interrupt + value: 62 + EXTI20: + description: EXTI Line 20 interrupt + value: 76 + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + +FMPI2C1: + _include: + - fields/i2c/v2.yaml + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - patches/i2c/v1_fltr.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +PWR: + _include: + - patches/pwr/f4.yaml + - patches/pwr/add_sleep.yaml + - fields/pwr/pwr_f410_f412_f413_f423.yaml # Add missing reset/enable bits for SPI 5 (SPI5EN is present) RCC: PLLCFGR: _merge: - - "PLLR*" + - PLLR* _modify: - "PLLR*": - description: "PLL division factor for I2S and System clocks" + PLLR*: + description: PLL division factor for I2S and System clocks + APB1RSTR: + _modify: + UART2RST: + name: USART2RST APB2RSTR: _add: SPI5RST: - description: "SPI5 reset" + description: SPI5 reset bitOffset: 20 bitWidth: 1 APB2LPENR: _add: SPI5LPEN: - description: "SPI5 clock enable during Sleep mode" + description: SPI5 clock enable during Sleep mode bitOffset: 20 bitWidth: 1 DCKCFGR2: _modify: I2C4SEL: name: FMPI2C1SEL - description: "FMPI2C1 kernel clock source selection" + description: FMPI2C1 kernel clock source selection + _include: + - patches/rcc/f4_fmpi2c.yaml + - patches/rcc/f41x_bdcr_lsemod.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/bdcr_lsemod.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/cfgr_mcoen.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + - fields/rcc/v2/dckcfgr_i2ssrc.yaml + - fields/rcc/v2/dckcfgr2_lptimsel.yaml + - fields/rcc/v2/dckcfgr2_i2csel.yaml -USART1: -# Add missing USART interrupts +RNG: + _include: fields/rng/v1.yaml + CR: + _add: + CED: + description: Clock error detection + bitOffset: 5 + bitWidth: 1 + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0401 + TIFRFE: + name: FRE + +SPI5: _add: _interrupts: - USART1: - description: "USART1 global interrupt" - value: 37 - USART2: - description: "USART2 global interrupt" - value: 38 - USART6: - description: "USART6 global interrupt" - value: 71 + SPI5: + description: SPI 5 global interrupt + value: 85 -DMA1: +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f410.yaml _add: - _interrupts: - DMA1_Stream0: - description: "DMA1 stream0 global interrupt" - value: 11 - DMA1_Stream1: - description: "DMA1 stream1 global interrupt" - value: 12 - DMA1_Stream2: - description: "DMA1 stream2 global interrupt" - value: 13 - DMA1_Stream3: - description: "DMA1 stream3 global interrupt" - value: 14 - DMA1_Stream4: - description: "DMA1 stream4 global interrupt" - value: 15 - DMA1_Stream5: - description: "DMA1 stream5 global interrupt" - value: 16 - DMA1_Stream6: - description: "DMA1 stream6 global interrupt" - value: 17 - DMA1_Stream7: - description: "DMA1 stream7 global interrupt" - value: 47 - DMA2_Stream0: - description: "DMA2 stream0 global interrupt" - value: 56 - DMA2_Stream1: - description: "DMA2 stream1 global interrupt" - value: 57 - DMA2_Stream2: - description: "DMA2 stream2 global interrupt" - value: 58 - DMA2_Stream3: - description: "DMA2 stream3 global interrupt" - value: 59 - DMA2_Stream4: - description: "DMA2 stream4 global interrupt" - value: 60 - DMA2_Stream5: - description: "DMA2 stream5 global interrupt" - value: 68 - DMA2_Stream6: - description: "DMA2 stream6 global interrupt" - value: 69 - DMA2_Stream7: - description: "DMA2 stream7 global interrupt" - value: 70 + CFGR2: + description: ADC Common status register + addressOffset: 0x1C + access: read-write + resetValue: 0x00000000 + fields: + PVDL: + description: PVD lock + bitOffset: 2 + bitWidth: 1 + CLL: + description: core lockup lock + bitOffset: 0 + bitWidth: 1 + CFGR: + _modify: + FMPI2C1_SDA: + name: FMPI2C4_SDA + FMPI2C1_SCL: + name: FMPI2C4_SCL + +TIM1: + _include: + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml TIM5: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml _add: _interrupts: TIM5: - description: "TIM5 global interrupt" + description: TIM5 global interrupt value: 50 -EXTI: - _add: - _interrupts: - EXTI19: - description: "EXTI Line 19 interrupt" - value: 62 - EXTI20: - description: "EXTI Line 20 interrupt" - value: 76 +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _delete: CR2 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _add: _interrupts: WWDG: - description: "Window watchdog interrupt" + description: Window watchdog interrupt value: 0 +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted + _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/f4_rcc_fmpi2c.yaml - - common_patches/f4_adc_single_csr.yaml - - common_patches/f4_adc_single_ccr.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml - - ../peripherals/rcc/rcc_v2_cfgr_mcoen.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2ssrc.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_lptimsel.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_i2csel.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_single.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/i2c/i2c_v2_fmp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f411.yaml b/devices/stm32f411.yaml index a190744d5..4e999dea9 100644 --- a/devices/stm32f411.yaml +++ b/devices/stm32f411.yaml @@ -8,12 +8,26 @@ _rebase: # Make DMA1 the base type DMA1: DMA2 -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0383 - TIFRFE: - name: "FRE" +ADC_Common: + CCR: + _delete: + - DMA + - DDS + - DELAY + _delete: + - CSR + _include: + - fields/adc/adc_v2_common.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_b.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml CRC: # The SVD calls the RESET field "CR", fix per RM0383 @@ -21,145 +35,224 @@ CRC: _modify: CR: name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DBGMCU: {} -# Add missing interrupts DMA1: - _add: - _interrupts: - DMA1_Stream0: - description: "DMA1 stream0 global interrupt" - value: 11 - DMA1_Stream1: - description: "DMA1 stream1 global interrupt" - value: 12 - DMA1_Stream2: - description: "DMA1 stream2 global interrupt" - value: 13 - DMA1_Stream3: - description: "DMA1 stream3 global interrupt" - value: 14 - DMA1_Stream4: - description: "DMA1 stream4 global interrupt" - value: 15 - DMA1_Stream5: - description: "DMA1 stream5 global interrupt" - value: 16 - DMA1_Stream6: - description: "DMA1 stream6 global interrupt" - value: 17 - DMA1_Stream7: - description: "DMA1 stream7 global interrupt" - value: 47 - DMA2_Stream0: - description: "DMA2 stream0 global interrupt" - value: 56 - DMA2_Stream1: - description: "DMA2 stream1 global interrupt" - value: 57 - DMA2_Stream2: - description: "DMA2 stream2 global interrupt" - value: 58 - DMA2_Stream3: - description: "DMA2 stream3 global interrupt" - value: 59 - DMA2_Stream4: - description: "DMA2 stream4 global interrupt" - value: 60 - DMA2_Stream5: - description: "DMA2 stream5 global interrupt" - value: 68 - DMA2_Stream6: - description: "DMA2 stream6 global interrupt" - value: 69 - DMA2_Stream7: - description: "DMA2 stream7 global interrupt" - value: 70 -SPI1: - _add: - _interrupts: - SPI5: - description: "SPI5 global interrupt" - value: 85 -TIM3: - _add: - _interrupts: - TIM4: - description: "TIM4 global interrupt" - value: 30 -TIM5: - _add: - _interrupts: - TIM5: - description: "TIM5 global interrupt" - value: 50 -USART1: - _add: - _interrupts: - USART1: - description: "USART1 global interrupt" - value: 37 - USART2: - description: "USART2 global interrupt" - value: 38 - USART6: - description: "USART6 global interrupt" - value: 71 -WWDG: - _add: - _interrupts: - WWDG: - description: "Window watchdog interrupt" - value: 0 + _include: + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr/sprmod.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - patches/i2c/v1_fltr.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_v1_novbussens.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/f4.yaml + - patches/pwr/add_sleep.yaml + - fields/pwr/pwr_f411.yaml # Add missing reset bit for SPI 4 (enable bits are present) RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST APB2RSTR: _add: SPI4RST: description: SPI4 reset bitOffset: 13 bitWidth: 1 + _include: + - patches/rcc/spi5.yaml + - patches/rcc/rename_plli2scfgr.yaml + - patches/rcc/add_plli2sm.yaml + - patches/rcc/f4_dckcfgr.yaml + - patches/rcc/f41x_bdcr_lsemod.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/bdcr_lsemod.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + - fields/rcc/v2/i2s_pllm.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0383 + TIFRFE: + name: FRE + +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f401_f411.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + _delete: + _interrupts: + - TIM1_UP_TIM10 + - TIM1_TRG_COM_TIM11 + _add: + _interrupts: + TIM1_UP_TIM10: + value: 25 + description: TIM1 Update interrupt and TIM10 global interrupt + TIM1_TRG_COM_TIM11: + value: 26 + description: TIM1 Trigger and Commutation interrupts and TIM11 global interrupt + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _delete: + _interrupts: + - DMA2_Stream7 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM9: + _delete: CR2 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: collect/tim/tim11_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/rcc_spi5.yaml - - common_patches/rcc_rename_plli2scfgr.yaml - - common_patches/rcc_add_plli2sm.yaml - - common_patches/f4_rcc_dckcfgr.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/f4_adc_no_csr.yaml - - common_patches/f4_adc_single_ccr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllm.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_fixes_v1.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/sdio/sdio_f4.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f412.yaml b/devices/stm32f412.yaml index 9f0a19faf..0e6e39291 100644 --- a/devices/stm32f412.yaml +++ b/devices/stm32f412.yaml @@ -1,16 +1,18 @@ _svd: ../svd/stm32f412.svd +_copy: + DFSDM: + from: ../svd/stm32f413.svd:DFSDM2 + _rebase: # Make I2C1 the base type I2C1: I2C3 SPI1: I2S2ext -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0402 - TIFRFE: - name: "FRE" +_derive: + TIM9: TIM12 + TIM13: TIM10 + TIM14: TIM10 _modify: I2C4: @@ -18,8 +20,106 @@ _modify: name: FMPI2C1 FSMC: - # ST got the base address of the FSMC peripheral wrong - baseAddress: "0xA0000000" + # ST got the base address of the FSMC peripheral wrong + baseAddress: "0xA0000000" + +ADC_Common: + CSR: + _delete: + - "*2" + - "*3" + CCR: + _delete: + - DMA + - DDS + - DELAY + _include: + - fields/adc/adc_v2_common_single.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + # The SVD calls the RESET field "CR", fix per RM0402 + CR: + _modify: + CR: + name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DBGMCU: {} + +DFSDM: + _include: + - patches/dfsdm/dfsdm_v1.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DMA2: + _include: + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr/sprmod.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + +FMPI2C1: + _add: + _interrupts: + I2CFMP1_event: + description: I2CFMP1 event interrupt + value: 95 + OAR1: + _delete: [OA1, OA11_7, OA18_9] + _add: + OA1: + description: Interface own slave address + bitOffset: 0 + bitWidth: 10 + _include: + - patches/i2c/f4_fmpi2c.yaml + - fields/i2c/v2.yaml # FSMC register fixes FSMC: @@ -33,404 +133,278 @@ FSMC: resetValue: "0x000030D2" BCR4: resetValue: "0x000030D2" - "BTR?": + BTR?: resetValue: "0x0fffffff" # Delete registers not present on the STM32F412 _delete: - - "PCR?" - - "SR?" - - "PMEM?" - - "PATT?" - - "ECCR?" + - PCR? + - SR? + - PMEM? + - PATT? + - ECCR? - PIO4 BCR1: # Extra fields in BCR1 _add: WFDIS: - description: "Write FIFO disable" + description: Write FIFO disable bitOffset: 21 bitWidth: 1 CCLKEN: - description: "Continuous clock enable" + description: Continuous clock enable bitOffset: 20 bitWidth: 1 - WFDIS: - Enabled: [0, "Write FIFO enabled"] - Disabled: [1, "Write FIFO disabled"] - CCLKEN: - Enabled: [1, "FSMC_CLK is generated continuously during asynchronous and synchronous access"] - Disabled: [0, "FSMC_CLK is only generated during the synchronous memory access"] # Delete WRAPMOD field from BCR1, BCR2, BCR3, BCR4 - "BCR?": + BCR?: _delete: - WRAPMOD # Delete DATLAT and CLKDIV fields from BWTR1, BWTR2, BWTR3, BWTR4 - "BWTR?": + BWTR?: _delete: - DATLAT - CLKDIV - # Add the missing interrupt - _add: - _interrupts: - FSMC: - description: FSMC global interrupt - value: 48 + _include: + - patches/fsmc/sramfix_common.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - collect/fsmc/sram.yaml -CRC: - # The SVD calls the RESET field "CR", fix per RM0402 - CR: - _modify: - CR: - name: RESET +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml -# Merge the thousands of individual bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - patches/i2c/v1_fltr.yaml + - fields/i2c/v1.yaml + OAR1: _merge: - - "FB*" + ADD: "ADD[07],ADD10" + +I2C3: + _delete: + _interrupts: + - I2CFMP1_event + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/f4.yaml + - patches/pwr/add_sleep.yaml + - patches/pwr/add_ewup.yaml + - fields/pwr/pwr_f410_f412_f413_f423.yaml + +QUADSPI: + _modify: + _interrupts: + Quad_SP: + name: Quad_SPI + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml # Add missing reset bit for SPI 4 (enable bits are present) RCC: - PLLCFGR: - _add: - PLLR: - description: Main PLL division factor for I2S, DFSDM clocks - bitOffset: 28 - bitWidth: 3 - APB2RSTR: - _add: - SPI4RST: - description: SPI4 reset - bitOffset: 13 - bitWidth: 1 - PLLI2SCFGR: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + APB1ENR: + _modify: + RTCAPB: + name: RTCAPBEN + DCKCFGR2: + _modify: + I2CFMP1SEL: + name: FMPI2C1SEL + bitWidth: 2 + CKSDIOSEL: + name: SDIOSEL + _include: + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/bdcr_lsemod.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s_pll.yaml + - fields/rcc/v2/i2s_pllsrc.yaml + - fields/rcc/v2/i2s_pllq.yaml + - fields/rcc/v2/i2s_pllm.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + - fields/rcc/v2/dckcfgr_i2s12src.yaml + - fields/rcc/v2/dckcfgr_dfsdm_f4.yaml + - fields/rcc/v2/dckcfgr2_48m_sd.yaml + - fields/rcc/v2/dckcfgr2_i2csel.yaml + - fields/rcc/v2/ckgatenr.yaml + +RNG: + _include: fields/rng/v1.yaml + CR: _add: - PLLI2SSRC: - description: "PLLI2S entry clock source" - bitOffset: 22 + CED: + description: Clock error detection + bitOffset: 5 bitWidth: 1 + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0402 + TIFRFE: + name: FRE + +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f412.yaml + _modify: + I2C_BUFOUT: + name: CFGR + displayName: CFGR + description: Configuration register _add: - DCKCFGR: - description: Dedicated Clock Configuration Register - addressOffset: 0x8C - size: 0x20 + CFGR2: + description: ADC Common status register + addressOffset: 0x1C access: read-write resetValue: 0x00000000 fields: - CKDFSDM1ASEL: - description: DFSDM1 audio clock selection - bitOffset: 15 - bitWidth: 5 - TIMPRE: - description: Timers clocks prescalers selection - bitOffset: 24 - bitWidth: 1 - I2S1SRC: - description: I2S APB1 clocks source selection (I2S2/3) - bitOffset: 25 - bitWidth: 2 - I2S2SRC: - description: I2S APB2 clocks source selection (I2S1/4/5) - bitOffset: 27 - bitWidth: 2 - CKDFSDM1SEL: - description: DFSDM1 Kernel clock selection - bitOffset: 31 - bitWidth: 1 - DCKCFGR2: - description: Dedicated Clock Configuration Register - addressOffset: 0x94 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - FMPI2C1SEL: - description: FMPI2C1 kernel clock source selection - bitOffset: 22 - bitWidth: 2 - CK48MSEL: - description: SDIO/USBFS clock selection - bitOffset: 27 - bitWidth: 1 - SDIOSEL: - description: SDIO clock selection - bitOffset: 28 - bitWidth: 1 - CKGATENR: - description: Clocks gated enable register - addressOffset: 0x90 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - AHB2APB1_CKEN: - description: AHB to APB1 Bridge clock enable - bitOffset: 0 - bitWidth: 1 - AHB2APB2_CKEN: - description: AHB to APB2 Bridge clock enable - bitOffset: 1 - bitWidth: 1 - CM4DBG_CKEN: - description: Cortex M4 ETM clock enable + PVDL: + description: PVD lock bitOffset: 2 bitWidth: 1 - SPARE_CKEN: - description: Spare clock enable - bitOffset: 3 - bitWidth: 1 - SRAM_CKEN: - description: SRAM controller clock enable - bitOffset: 4 - bitWidth: 1 - FLITF_CKEN: - description: Flash interface clock enable - bitOffset: 5 - bitWidth: 1 - RCC_CKEN: - description: RCC clock enable - bitOffset: 6 - bitWidth: 1 - EVTCL_CKEN: - description: EVTCL clock enable - bitOffset: 7 - bitWidth: 1 - # Add missing reset and enable registers for AHB3 - AHB3RSTR: - description: RCC AHB3 peripheral reset register - addressOffset: 0x18 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - FSMCRST: - description: Flexible static memory controller module reset - bitOffset: 0 - bitWidth: 1 - QSPIRST: - description: QUADSPI module reset - bitOffset: 1 - bitWidth: 1 - AHB3ENR: - description: RCC AHB3 peripheral clock enable register - addressOffset: 0x38 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - FSMCEN: - description: Flexible static memory controller module clock enable + CLL: + description: core lockup lock bitOffset: 0 bitWidth: 1 - QSPIEN: - description: QUADSPI memory controller module clock enable - bitOffset: 1 - bitWidth: 1 + CFGR: + _modify: + I2C4SDA: + name: I2CFMP1_SDA + I2C4SCL: + name: I2CFMP1_SCL -# Add missing interrupts defined in RM0402 -WWDG: - _add: - _interrupts: - WWDG: - description: Window Watchdog interrupt - value: 0 -TIM2: - _add: - _interrupts: - TIM4: - description: TIM4 global interrupt - value: 30 -USART1: - _add: - _interrupts: - USART1: - description: USART1 global interrupt - value: 37 - USART2: - description: USART2 global interrupt - value: 38 - USART3: - description: USART3 global interrupt - value: 39 - USART6: - description: USART6 global interrupt - value: 71 TIM1: - _add: - _interrupts: - TIM8_CC: - description: TIM8 Cap/Com interrupt - value: 46 + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + TIM5: - _add: - _interrupts: - TIM5: - description: TIM5 global interrupt - value: 50 -SPI1: - _add: - _interrupts: - SPI3: - description: SPI3 global interrupt - value: 51 - SPI5: - description: SPI5 global interrupt - value: 85 -DMA2: - _add: - _interrupts: - DMA1_Stream0: - description: DMA1 Stream0 global interrupt - value: 11 - DMA1_Stream1: - description: DMA1 Stream1 global interrupt - value: 12 - DMA1_Stream2: - description: DMA1 Stream2 global interrupt - value: 13 - DMA1_Stream3: - description: DMA1 Stream3 global interrupt - value: 14 - DMA1_Stream4: - description: DMA1 Stream4 global interrupt - value: 15 - DMA1_Stream5: - description: DMA1 Stream5 global interrupt - value: 16 - DMA1_Stream6: - description: DMA1 Stream6 global interrupt - value: 17 - DMA1_Stream7: - description: DMA1 global interrupt Channel 7 - value: 47 - DMA2_Stream0: - description: DMA2 Stream0 global interrupt - value: 56 - DMA2_Stream1: - description: DMA2 Stream1 global interrupt - value: 57 - DMA2_Stream2: - description: DMA2 Stream2 global interrupt - value: 58 - DMA2_Stream3: - description: DMA2 Stream3 global interrupt - value: 59 - DMA2_Stream4: - description: DMA2 Stream4 global interrupt - value: 60 - DMA2_Stream5: - description: DMA2 Stream5 global interrupt - value: 68 - DMA2_Stream6: - description: DMA2 Stream6 global interrupt - value: 69 - DMA2_Stream7: - description: DMA2 Stream7 global interrupt - value: 70 -DFSDM: - _add: - _interrupts: - DFSDM1_FLT0: - description: SD filter0 global interrupt - value: 61 - DFSDM1_FLT1: - description: SD filter1 global interrupt - value: 62 -CAN1: - _add: - _interrupts: - CAN2_TX: - description: CAN2 TX interrupt - value: 63 - CAN2_RX0: - description: BXCAN2 RX0 interrupt - value: 64 - CAN2_RX1: - description: BXCAN2 RX1 interrupt - value: 65 - CAN2_SCE: - description: CAN2 SCE interrupt - value: 66 -QUADSPI: - _add: - _interrupts: - Quad_SPI: - description: Quad-SPI global interrupt - value: 92 -FMPI2C1: - _add: - _interrupts: - I2CFMP1_event: - description: I2CFMP1 event interrupt - value: 95 - I2CFMP1_error: - description: I2CFMP1 error interrupt - value: 96 + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _modify: + CNT: + access: read-write + CR1: + _delete: UIFREMAP + CNT: + _delete: UIFCPY + _modify: + CNT: + access: "" + _include: + - fields/tim/v1/tim6.yaml + +TIM12: + _include: + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: collect/tim/tim11_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/rcc_spi5.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/dfsdm/dfsdm_v2.yaml - - common_patches/rcc_rename_plli2scfgr.yaml - - common_patches/rcc_add_plli2sq_usb.yaml - - common_patches/rcc_add_plli2sm.yaml - - common_patches/f4_rcc_fmpi2c.yaml - - common_patches/f4_fmpi2c.yaml - - common_patches/f4_adc_single_csr.yaml - - common_patches/f4_adc_single_ccr.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_common.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllsrc.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllq.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllm.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2s12src.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f4.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_48m_sd.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_i2csel.yaml - - ../peripherals/rcc/rcc_v2_ckgatenr.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_single.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/i2c/i2c_v2_fmp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/sdio/sdio_f4.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f413.yaml b/devices/stm32f413.yaml index eee8b54f2..10212655f 100644 --- a/devices/stm32f413.yaml +++ b/devices/stm32f413.yaml @@ -6,21 +6,91 @@ _rebase: SPI1: SPI5 USART1: USART3 +_derive: + TIM9: TIM12 + TIM13: TIM10 + TIM14: TIM10 + UART5: UART4 + UART7: UART4 + UART8: UART4 + UART9: UART4 + UART10: UART4 + +# The UART peripherals are erroneously derived from a fully-featured USART +# (with extra features, and register fields which UARTs lack). They also have +# incorrect interrupt definitions. +_delete: + - UART4 + - UART5 + - UART7 + - UART8 + +_copy: + UART4: + from: ../svd/stm32f469.svd:UART4 + UART5: + from: ../svd/stm32f469.svd:UART5 + UART7: + from: ../svd/stm32f469.svd:UART7 + UART8: + from: ../svd/stm32f469.svd:UART8 + UART9: + from: UART8 + UART10: + from: UART8 + _modify: FMPI2C: # Rename FMPI2C to FMPI2C1 name: FMPI2C1 FSMC: - # ST got the base address of the FSMC peripheral wrong - baseAddress: "0xA0000000" + # ST got the base address of the FSMC peripheral wrong + baseAddress: "0xA0000000" -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0430 - TIFRFE: - name: "FRE" +_add: + # I2S*ext are missing + I2S2ext: + derivedFrom: SPI1 + baseAddress: "0x40003400" + I2S3ext: + derivedFrom: SPI1 + baseAddress: "0x40004000" + +ADC_Common: + CSR: + _delete: + - "*2" + - "*3" + CCR: + _delete: + - DMA + - DDS + - DELAY + _include: + - fields/adc/adc_v2_common_single.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - patches/aes/l4.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml CRC: # The SVD calls the RESET field "CR", fix per RM0430 @@ -28,31 +98,177 @@ CRC: _modify: CR: name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DFSDM2: + _include: + - patches/dfsdm/dfsdm_v1.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr/sprmod.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + +FMPI2C1: + OAR1: + _delete: [OA1, OA11_7, OA18_9] + _add: + OA1: + description: Interface own slave address + bitOffset: 0 + bitWidth: 10 + _include: + - patches/i2c/f4_fmpi2c.yaml + - fields/i2c/v2.yaml + +FSMC: + _include: + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - collect/fsmc/sram.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABF]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BF]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: _merge: - - "FB*" + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +LPTIM: + _include: + - fields/lptim/v1.yaml + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _delete: + _interrupts: + - USART10 + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml + +# Fix invalid formatting on this alternateRegister field +OTG_FS_GLOBAL: + _add: + _interrupts: + OTG_FS: + description: USB OTG FS Interrupt + value: 67 + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - collect/usb_otg/fs_global.yaml + +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml + +OTG_FS_PWRCLK: + _delete: + _interrupts: + - USART9 + +PWR: + _include: + - patches/pwr/f4.yaml + - patches/pwr/add_sleep.yaml + - patches/pwr/add_ewup.yaml + - fields/pwr/pwr_f410_f412_f413_f423.yaml + +QUADSPI: + _add: + _interrupts: + QuadSPI: + value: 92 + description: Quad-SPI global interrupt + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml # Add missing RCC reset/enable bits RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + USART4RST: + name: UART4RST + description: UART4 reset + USART5RST: + name: UART5RST + description: UART5 reset APB2RSTR: - _add: - UART9RST: + _modify: + USART9RST: + name: UART9RST description: UART9 reset - bitOffset: 6 - bitWidth: 1 - UART10RST: + SART10RST: + name: UART10RST description: UART10 reset - bitOffset: 7 - bitWidth: 1 APB1ENR: _modify: RTCAPB: @@ -71,19 +287,22 @@ RCC: _modify: RTCAPBEN: name: RTCAPBLPEN + USART4LPEN: + name: UART4LPEN + description: UART4 clock enable during Sleep mode + USART5LPEN: + name: UART5LPEN + description: UART5 clock enable during Sleep mode APB2LPENR: _modify: EXTITEN: name: EXTITLPEN - _add: - UART9LPEN: + USART9LPEN: + name: UART9LPEN description: UART9 clock enable during Sleep mode - bitOffset: 6 - bitWidth: 1 - UART10LPEN: + USART10LPEN: + name: UART10LPEN description: UART10 clock enable during Sleep mode - bitOffset: 7 - bitWidth: 1 DCKCFGR: _delete: - LPTIMER1SEL @@ -124,73 +343,304 @@ RCC: bitWidth: 2 CKSDIOSEL: name: SDIOSEL + _include: + - patches/rcc/f4_fmpi2c.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s_pll.yaml + - fields/rcc/v2/i2s_pllsrc.yaml + - fields/rcc/v2/i2s_pllq.yaml + - fields/rcc/v2/i2s_pllm.yaml + - fields/rcc/v2/bdcr_lsemod.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + - fields/rcc/v2/dckcfgr_i2s_sai_f4.yaml + - fields/rcc/v2/dckcfgr_i2s12src.yaml + - fields/rcc/v2/dckcfgr_dfsdm_f4.yaml + - fields/rcc/v2/dckcfgr2_48m_sd.yaml + - fields/rcc/v2/dckcfgr2_lptimsel.yaml + - fields/rcc/v2/dckcfgr2_i2csel.yaml + - fields/rcc/v2/ckgatenr.yaml -# Fix invalid formatting on this alternateRegister field -OTG_FS_GLOBAL: +RNG: {} + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0430 + TIFRFE: + name: FRE + +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f413_f423.yaml _modify: - FS_GNPTXFSIZ_Host: - alternateRegister: GNPTXFSIZ_Device + I2C_BUFOUT: + name: CFGR + displayName: CFGR + description: Configuration register + _add: + CFGR2: + description: ADC Common status register + addressOffset: 0x1C + access: read-write + resetValue: 0x00000000 + fields: + PVDL: + description: PVD lock + bitOffset: 2 + bitWidth: 1 + CLL: + description: core lockup lock + bitOffset: 0 + bitWidth: 1 + MCHDLYCR: + description: DFSDM Multi-channel delay control register + addressOffset: 0x30 + access: read-write + resetValue: 0x00000000 + fields: + DFSDM2_CKOSEL: + description: Source selection for DFSDM2_CKOUT + bitOffset: 18 + bitWidth: 1 + DFSDM2_CFG: + description: CkIn source selection for DFSDM2 + bitOffset: 17 + bitWidth: 1 + DFSDM2_CK37SEL: + description: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 + bitOffset: 16 + bitWidth: 1 + DFSDM2_CK26SEL: + description: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC2 + bitOffset: 15 + bitWidth: 1 + DFSDM2_CK15SEL: + description: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC3 + bitOffset: 14 + bitWidth: 1 + DFSDM2_CK04SEL: + description: Distribution of the DFSDM2 bitstream clock gated by TIM3 OC4 + bitOffset: 13 + bitWidth: 1 + DFSDM2_D6SEL: + description: Source selection for DatIn6 of DFSDM2 + bitOffset: 12 + bitWidth: 1 + DFSDM2_D4SEL: + description: Source selection for DatIn4 of DFSDM2 + bitOffset: 11 + bitWidth: 1 + DFSDM2_D2SEL: + description: Source selection for DatIn2 of DFSDM2 + bitOffset: 10 + bitWidth: 1 + DFSDM2_D0SEL: + description: Source selection for DatIn0 of DFSDM2 + bitOffset: 9 + bitWidth: 1 + MCHDLYEN2: + description: MCHDLY clock enable for DFSDM2 + bitOffset: 8 + bitWidth: 1 + DFSDM1_CKOSEL: + description: Source selection for DFSDM1_CKOUT + bitOffset: 7 + bitWidth: 1 + DFSDM1_CFG: + description: CkIn source selection for DFSDM1 + bitOffset: 6 + bitWidth: 1 + DFSDM1_CK13SEL: + description: Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 + bitOffset: 5 + bitWidth: 1 + DFSDM1_CK02SEL: + description: Distribution of the DFSDM1 bitstream clock gated by TIM4 OC2 + bitOffset: 4 + bitWidth: 1 + DFSDM1_D2SEL: + description: Source selection for DatIn2 of DFSDM1 + bitOffset: 3 + bitWidth: 1 + DFSDM1_D0SEL: + description: Source selection for DatIn0 of DFSDM1 + bitOffset: 2 + bitWidth: 1 + MCHDLYEN1: + description: MCHDLY clock enable for DFSDM1 + bitOffset: 1 + bitWidth: 1 + BSCKSEL: + description: Bitstream clock source selection + bitOffset: 0 + bitWidth: 1 + CFGR: + _modify: + I2C4SDA: + name: I2CFMP1_SDA + I2C4SCL: + name: I2CFMP1_SCL + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM7: + _modify: + CNT: + access: read-write + CR1: + _delete: UIFREMAP + CNT: + _delete: UIFCPY + _modify: + CNT: + access: "" + _include: + - fields/tim/v1/tim6.yaml + +TIM12: + _include: + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: collect/tim/tim11_derive.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART6: + _add: + _interrupts: + USART6: + description: USART 6 global interrupt + value: 71 + +UART9: + _add: + _interrupts: + UART9: + description: UART 9 global interrupt + value: 88 + _delete: + _interrupts: + - USART8 + +UART10: + _add: + _interrupts: + UART10: + description: UART 10 global interrupt + value: 89 + _delete: + _interrupts: + - UART5 + +# The USART peripheral definitions in the svd have a random array of unrelated +# incorrect interrupt definitions. +USART1: + _add: + _interrupts: + USART1: + description: USART 1 global interrupt + value: 37 + _delete: + _interrupts: + - USART7 + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +USART2: + _add: + _interrupts: + USART2: + description: USART 2 global interrupt + value: 38 + _delete: + _interrupts: + - USART3 + +USART3: + _add: + _interrupts: + USART3: + description: USART 3 global interrupt + value: 39 + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/dfsdm/dfsdm_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/f4_rcc_fmpi2c.yaml - - common_patches/f4_fmpi2c.yaml - - common_patches/f4_adc_single_csr.yaml - - common_patches/f4_adc_single_ccr.yaml - - common_patches/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllsrc.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllq.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllm.yaml - - ../peripherals/rcc/rcc_v2_bdcr_lsemod.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f4.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2s12src.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f4.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_48m_sd.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_lptimsel.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_i2csel.yaml - - ../peripherals/rcc/rcc_v2_ckgatenr.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_single.yaml - - common_patches/dma/dma_v21.yaml - - ../peripherals/dma/dma_v21.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/i2c/i2c_v2_fmp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/sai/sai.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/sdio/sdio_f4.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f427.yaml b/devices/stm32f427.yaml index 660a8dd86..9e62ef9d0 100644 --- a/devices/stm32f427.yaml +++ b/devices/stm32f427.yaml @@ -13,12 +13,30 @@ _modify: FMC: name: FSMC -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0090 - TIFRFE: - name: "FRE" +_derive: + UART7: UART4 + UART8: UART4 + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml CRC: # The SVD calls the RESET field "CR", fix per RM0090 @@ -26,37 +44,83 @@ CRC: _modify: CR: name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +DMA2D: + _strip: DMA2D_ + +#Ethernet_DMA: {} +#Ethernet_MAC: {} +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr1/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer_mer1.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/bfb2.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/db1m.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optcr1/nwrp.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + - collect/flash/optcr1/nwrp.yaml # Offset of BWTR3 and BWTR4 is incorrect -"FMC,FSMC": +FSMC: _modify: BWTR3: - addressOffset: "0x114" + addressOffset: 0x114 alternateRegister: "" BWTR4: - addressOffset: "0x11C" + addressOffset: 0x11C alternateRegister: "" "BCR[2-4]": _add: @@ -64,173 +128,265 @@ CRYP: description: CCLKEN bitOffset: 20 bitWidth: 1 - "BWTR?": + BWTR?: _add: CLKDIV: description: CLKDIV bitOffset: 20 bitWidth: 4 - DATAST: - description: DATAST - bitOffset: 8 - bitWidth: 8 SDCR2: - _add: - RPIPE: - description: "Read pipe" - bitOffset: 13 - bitWidth: 2 - RBURST: - description: "Burst read" - bitOffset: 12 - bitWidth: 1 + _modify: + CLK: + name: SDCLK + _include: + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + - collect/fsmc/sd.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_v1_novbussens.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_v1_device.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hs_v1_global.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hs_v1_f4_host.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: + _include: + - patches/usb_otg/hs_v1_pwrclk.yaml + +PWR: + CR: + _modify: + MRLVDS: + name: MRUDS + description: Main regulator in deepsleep under-drive mode + LPLVDS: + name: LPUDS + description: Low-power regulator in deepsleep under-drive mode + _include: + - patches/pwr/f4.yaml + - fields/pwr/pwr_f427_f437_f429_f439.yaml # Fix RCC enable bits naming RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST APB1ENR: _modify: UART7ENR: name: UART7EN UART8ENR: name: UART8EN - APB2ENR: + _include: + - patches/rcc/sai.yaml + - patches/rcc/dma2d_ltdc.yaml + - patches/rcc/rename_plli2scfgr.yaml + - patches/rcc/add_plli2sq_sai.yaml + - patches/rcc/add_gpiojk.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + - fields/rcc/v2/i2s_pllq.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + - fields/rcc/v2/dckcfgr_i2s_sai_f4.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/f4_cr.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: _modify: - SPI4ENR: - name: SPI4EN - SPI5ENR: - name: SPI5EN - SPI6ENR: - name: SPI6EN - _add: - PLLSAICFGR: - description: RCC PLL configuration register - addressOffset: 0x88 - size: 0x20 - access: read-write - resetValue: 0x24003000 - fields: - PLLSAIR: - description: PLLSAI division factor for LCD clock - bitOffset: 28 - bitWidth: 3 - PLLSAIQ: - description: PLLSAI division factor for SAI1 clock - bitOffset: 24 - bitWidth: 4 - PLLSAIN: - description: PLLSAI division factor for VCO - bitOffset: 6 - bitWidth: 9 - DCKCFGR: - description: RCC Dedicated Clock Configuration Register - addressOffset: 0x8C - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - PLLI2SDIVQ: - description: PLLI2S division factor for SAI1 clock - bitOffset: 0 - bitWidth: 5 - PLLSAIDIVQ: - description: PLLSAI division factor for SAI1 clock - bitOffset: 8 - bitWidth: 5 - PLLSAIDIVR: - description: division factor for LCD_CLK - bitOffset: 16 - bitWidth: 2 - SAI1ASRC: - description: SAI1-A clock source selection - bitOffset: 20 - bitWidth: 2 - SAI1BSRC: - description: SAI1-B clock source selection - bitOffset: 22 - bitWidth: 2 - TIMPRE: - description: Timers clocks prescalers selection - bitOffset: 24 - bitWidth: 1 + # This field has the wrong name in the SVD compared to RM0090 + TIFRFE: + name: FRE + +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f427_f437_f429_f439.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: patches/tim/tim2_itr1_rmp.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _delete: CR2 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: collect/tim/tim11_derive.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/f2_f4_ethernet.yaml - - common_patches/rcc_sai.yaml - - common_patches/rcc_dma2d_ltdc.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/rcc_rename_plli2scfgr.yaml - - common_patches/rcc_add_plli2sq_sai.yaml - - common_patches/rcc_add_gpiojk.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_nand_v1.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllq.yaml - - ../peripherals/rcc/rcc_v2_sai_pllr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f4.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/hash/hash.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_fixes_v1.yaml - - common_patches/usb_otg/otg_hs_remove_prefix.yaml - - common_patches/usb_otg/otg_hs_fixes_v1.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/rng/rng_v1.yaml - - common_patches/f4_rtc_cr.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/sdio/sdio_f4.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/ethernet/f2_f4.yaml + - patches/adc/adc_common_group_name.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f429.yaml b/devices/stm32f429.yaml index 521d23710..a2ea9c671 100644 --- a/devices/stm32f429.yaml +++ b/devices/stm32f429.yaml @@ -11,12 +11,30 @@ _modify: C_ADC: name: ADC_Common -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0090 - TIFRFE: - name: "FRE" +_derive: + UART7: UART4 + UART8: UART4 + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml CRC: # The SVD calls the RESET field "CR", fix per RM0090 @@ -24,173 +42,346 @@ CRC: _modify: CR: name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +DMA2D: {} + +#Ethernet_DMA: {} +#Ethernet_MAC: {} +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr1/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer_mer1.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/bfb2.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/db1m.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optcr1/nwrp.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + - collect/flash/optcr1/nwrp.yaml # Offset of BWTR3 and BWTR4 is incorrect FMC: _modify: BWTR3: - addressOffset: "0x114" + addressOffset: 0x114 alternateRegister: "" BWTR4: - addressOffset: "0x11C" + addressOffset: 0x11C alternateRegister: "" + SDCR2: + _modify: + CLK: + name: SDCLK + _include: + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + - collect/fsmc/sd.yaml -# Add missing RCC reset/enable bits -RCC: - AHB1LPENR: +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABK]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BK]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +LTDC: + _include: + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_v1_novbussens.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_v1_device.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hs_v1_global.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hs_v1_f4_host.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: + _include: + - patches/usb_otg/hs_v1_pwrclk.yaml + +PWR: + CR: _add: - SRAM3LPEN: - description: SRAM3 interface clock enable during Sleep mode - bitOffset: 19 + ADCDC1: + bitOffset: 13 bitWidth: 1 + _modify: + MRLVDS: + name: MRUDS + description: Main regulator in deepsleep under-drive mode + LPLVDS: + name: LPUDS + description: Low-power regulator in deepsleep under-drive mode + _include: + - patches/pwr/f4.yaml + - fields/pwr/pwr_f427_f437_f429_f439.yaml + +# Add missing RCC reset/enable bits +RCC: APB1RSTR: - _add: - UART7RST: - description: UART7 reset - bitOffset: 30 - bitWidth: 1 - UART8RST: - description: UART8 reset - bitOffset: 31 - bitWidth: 1 + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST APB1ENR: - _add: - UART7EN: - description: UART7 clock enable - bitOffset: 30 - bitWidth: 1 - UART8EN: - description: UART8 clock enable - bitOffset: 31 - bitWidth: 1 - APB1LPENR: - _add: - UART7LPEN: - description: UART7 clock enable during Sleep mode - bitOffset: 30 - bitWidth: 1 - UART8LPEN: - description: UART8 clock enable during Sleep mode - bitOffset: 31 - bitWidth: 1 - APB2RSTR: - _add: - SPI6RST: - description: SPI6 reset - bitOffset: 21 - bitWidth: 1 - APB2ENR: - _add: - SPI6EN: - description: SPI6 clock enable - bitOffset: 21 - bitWidth: 1 - APB2LPENR: - _add: - SPI6LPEN: - description: SPI6 clock enable during Sleep mode - bitOffset: 21 - bitWidth: 1 + _modify: + UART7ENR: + name: UART7EN + UART8ENR: + name: UART8EN + _include: + - patches/rcc/sai.yaml + - patches/rcc/dma2d_ltdc.yaml + - patches/rcc/add_gpiojk.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - patches/rcc/rename_plli2scfgr.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + - fields/rcc/v2/dckcfgr_i2s_sai_f4.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/f4_cr.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0090 + TIFRFE: + name: FRE + +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f427_f437_f429_f439.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: patches/tim/tim2_itr1_rmp.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _delete: CR2 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: collect/tim/tim11_derive.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/f2_f4_ethernet.yaml - - common_patches/rcc_sai.yaml - - common_patches/rcc_dma2d_ltdc.yaml - - common_patches/rcc_spi4.yaml - - common_patches/rcc_spi5.yaml - - common_patches/rcc_add_gpiojk.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllq.yaml - - ../peripherals/rcc/rcc_v2_sai_pllr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f4.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/hash/hash.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_fixes_v1.yaml - - common_patches/usb_otg/otg_hs_remove_prefix.yaml - - common_patches/usb_otg/otg_hs_fixes_v1.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_v3.yaml - - common_patches/fsmc/fsmc_nand_v1.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/rng/rng_v1.yaml - - common_patches/f4_rtc_cr.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/sdio/sdio_f4.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/ethernet/f2_f4.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/dbgmcu/dbgmcu.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f446.yaml b/devices/stm32f446.yaml index b9bddd526..521c8cfb6 100644 --- a/devices/stm32f446.yaml +++ b/devices/stm32f446.yaml @@ -1,5 +1,20 @@ _svd: ../svd/stm32f446.svd +_copy: + OTG_FS_GLOBAL: + from: ../svd/stm32f777.svd:OTG_FS_GLOBAL + OTG_FS_HOST: + from: ../svd/stm32f777.svd:OTG_FS_HOST + OTG_FS_DEVICE: + from: ../svd/stm32f777.svd:OTG_FS_DEVICE + + OTG_HS_GLOBAL: + from: ../svd/stm32f777.svd:OTG_HS_GLOBAL + OTG_HS_HOST: + from: ../svd/stm32f777.svd:OTG_HS_HOST + OTG_HS_DEVICE: + from: ../svd/stm32f777.svd:OTG_HS_DEVICE + _rebase: # Make I2C1 the base type I2C1: I2C3 @@ -13,13 +28,29 @@ _modify: # Remove underscore to be consistent with other parts and RM SPDIF_RX: name: SPDIFRX + FMPI2C: + name: FMPI2C1 -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0390 - TIFRFE: - name: "FRE" +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml CRC: # The SVD calls the RESET field "CR", fix per RM0390 @@ -27,18 +58,195 @@ CRC: _modify: CR: name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/nand_v1.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +FMPI2C1: + _modify: + ISR: + access: "" + TXDR: + access: read-write + CR2: + _delete: SADD* + _add: + SADD: + description: Slave address bit (master mode) + bitOffset: 0 + bitWidth: 10 + OAR1: + _delete: + - OA1_* + _add: + OA1: + description: Interface address + bitOffset: 0 + bitWidth: 10 + ISR: + _modify: + "TXE,TXIS": + access: read-write + "RXNE,ADDR,NACKF,STOPF,TC,TCR,BERR,ARLO,OVR,PECERR,TIMEOUT,ALERT,BUSY,DIR,ADDCODE": + access: read-only + _include: + - fields/i2c/v2.yaml + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +HDMI_CEC: {} + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: _merge: - - "FB*" + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +OTG_FS_DEVICE: + _strip: OTG_FS_ + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _strip: OTG_FS_ + _include: + - patches/usb_otg/fs_fixes_446_469.yaml + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _strip: OTG_FS_ + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: + _strip: FS_ + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hs_fixes_446_469.yaml + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + CR: + _delete: + - LPLVDS + - MRLVDS + _add: + MRUDS: + description: Main regulator in deepsleep under-drive mode + bitOffset: 11 + bitWidth: 1 + LPUDS: + description: Low-power regulator in deepsleep under-drive mode + bitOffset: 10 + bitWidth: 1 + CSR: + _modify: + EWUP: + name: EWUP1 + description: Enable WKUP1 pin + _include: + - patches/pwr/f4.yaml + - fields/pwr/pwr_f446.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml # Fix misnamed RCC enable bits, add PLLSAI clock RCC: @@ -54,6 +262,12 @@ RCC: bitOffset: 28 bitWidth: 1 access: read-write + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST APB1ENR: _modify: CEC: @@ -66,8 +280,71 @@ RCC: _modify: SPDIFSEL: name: SPDIFRXSEL + PLLCFGR: + _add: + PLLR: + description: Main PLL division factor for I2Ss, SAIs, SYSTEM and SPDIF-Rx clocks + bitOffset: 28 + bitWidth: 3 + _include: + - patches/rcc/f4_fmpi2c.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/i2s_pllq.yaml + - fields/rcc/v2/i2s_pllm.yaml + - fields/rcc/v2/sai_pllp.yaml + - fields/rcc/v2/bdcr_lsemod.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + - fields/rcc/v2/dckcfgr_i2s_sai_f446.yaml + - fields/rcc/v2/dckcfgr_i2s12src.yaml + - fields/rcc/v2/dckcfgr2_48m_sd.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + - fields/rcc/v2/dckcfgr2_i2csel.yaml + - fields/rcc/v2/dckcfgr2_spdifrxsel.yaml + - fields/rcc/v2/ckgatenr.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/f4_cr.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0390 + TIFRFE: + name: FRE SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f446.yaml _add: # Add missing SYSCFG CFGR CFGR: @@ -86,489 +363,85 @@ SYSCFG: description: Forces FM+ drive capability on I2CFMP1_SCL pin bitOffset: 1 bitWidth: 1 + MEMRMP: + _delete: + - FB_MODE + PMC: + _delete: + - MII_RMII_SEL -# Add missing FMPI2C1 peripheral -_add: - FMPI2C1: - description: fast-mode Inter-integrated circuit - groupName: I2C - baseAddress: 0x40006000 - addressBlock: - offset: 0x0 - size: 0x400 - usage: registers - registers: - CR1: - description: Control register 1 - addressOffset: 0x0 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - PE: - description: Peripheral enable - bitOffset: 0 - bitWidth: 1 - TXIE: - description: TX Interrupt enable - bitOffset: 1 - bitWidth: 1 - RXIE: - description: RX Interrupt enable - bitOffset: 2 - bitWidth: 1 - ADDRIE: - description: Address match interrupt enable (slave only) - bitOffset: 3 - bitWidth: 1 - NACKIE: - description: Not acknowledge received interrupt enable - bitOffset: 4 - bitWidth: 1 - STOPIE: - description: STOP detection Interrupt enable - bitOffset: 5 - bitWidth: 1 - TCIE: - description: Transfer Complete interrupt enable - bitOffset: 6 - bitWidth: 1 - ERRIE: - description: Error interrupt enable - bitOffset: 7 - bitWidth: 1 - DNF: - description: Digital noise filter - bitOffset: 8 - bitWidth: 4 - ANFOFF: - description: Analog noise filter OFF - bitOffset: 12 - bitWidth: 1 - TXDMAEN: - description: DMA transmission requests enable - bitOffset: 14 - bitWidth: 1 - RXDMAEN: - description: DMA reception requests enable - bitOffset: 15 - bitWidth: 1 - SBC: - description: Slave byte control - bitOffset: 16 - bitWidth: 1 - NOSTRETCH: - description: Clock stretching disable - bitOffset: 17 - bitWidth: 1 - WUPEN: - description: Wakeup from STOP enable - bitOffset: 18 - bitWidth: 1 - GCEN: - description: General call enable - bitOffset: 19 - bitWidth: 1 - SMBHEN: - description: SMBus Host address enable - bitOffset: 20 - bitWidth: 1 - SMBDEN: - description: SMBus Device Default address enable - bitOffset: 21 - bitWidth: 1 - ALERTEN: - description: SMBus alert enable - bitOffset: 22 - bitWidth: 1 - PECEN: - description: PEC enable - bitOffset: 23 - bitWidth: 1 - CR2: - description: Control register 2 - addressOffset: 0x4 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - SADD: - description: Slave address bit (master mode) - bitOffset: 0 - bitWidth: 10 - RD_WRN: - description: Transfer direction (master mode) - bitOffset: 10 - bitWidth: 1 - ADD10: - description: 10-bit addressing mode (master mode) - bitOffset: 11 - bitWidth: 1 - HEAD10R: - description: 10-bit address header only read direction (master receiver mode) - bitOffset: 12 - bitWidth: 1 - START: - description: Start generation - bitOffset: 13 - bitWidth: 1 - STOP: - description: Stop generation (master mode) - bitOffset: 14 - bitWidth: 1 - NACK: - description: NACK generation (slave mode) - bitOffset: 15 - bitWidth: 1 - NBYTES: - description: Number of bytes - bitOffset: 16 - bitWidth: 8 - RELOAD: - description: NBYTES reload mode - bitOffset: 24 - bitWidth: 1 - AUTOEND: - description: Automatic end mode (master mode) - bitOffset: 25 - bitWidth: 1 - PECBYTE: - description: Packet error checking byte - bitOffset: 26 - bitWidth: 1 - OAR1: - description: Own address register 1 - addressOffset: 0x8 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - OA1: - description: Interface address - bitOffset: 0 - bitWidth: 10 - OA1MODE: - description: Own Address 1 10-bit mode - bitOffset: 10 - bitWidth: 1 - OA1EN: - description: Own Address 1 enable - bitOffset: 15 - bitWidth: 1 - OAR2: - description: Own address register 2 - addressOffset: 0xC - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - OA2: - description: Interface address - bitOffset: 1 - bitWidth: 7 - OA2MSK: - description: Own Address 2 masks - bitOffset: 8 - bitWidth: 3 - OA2EN: - description: Own Address 2 enable - bitOffset: 15 - bitWidth: 1 - TIMINGR: - description: Timing register - addressOffset: 0x10 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - SCLL: - description: SCL low period (master mode) - bitOffset: 0 - bitWidth: 8 - SCLH: - description: SCL high period (master mode) - bitOffset: 8 - bitWidth: 8 - SDADEL: - description: Data hold time - bitOffset: 16 - bitWidth: 4 - SCLDEL: - description: Data setup time - bitOffset: 20 - bitWidth: 4 - PRESC: - description: Timing prescaler - bitOffset: 28 - bitWidth: 4 - TIMEOUTR: - description: Timeout register - addressOffset: 0x14 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - TIMEOUTA: - description: Bus timeout A - bitOffset: 0 - bitWidth: 12 - TIDLE: - description: Idle clock timeout detection - bitOffset: 12 - bitWidth: 1 - TIMOUTEN: - description: Clock timeout enable - bitOffset: 15 - bitWidth: 1 - TIMEOUTB: - description: Bus timeout B - bitOffset: 16 - bitWidth: 12 - TEXTEN: - description: Extended clock timeout enable - bitOffset: 31 - bitWidth: 1 - ISR: - description: Interrupt and Status register - addressOffset: 0x18 - size: 0x20 - resetValue: 0x00000001 - fields: - TXE: - description: Transmit data register empty (transmitters) - bitOffset: 0 - bitWidth: 1 - access: read-write - TXIS: - description: Transmit interrupt status (transmitters) - bitOffset: 1 - bitWidth: 1 - access: read-write - RXNE: - description: Receive data register not empty (receivers) - bitOffset: 2 - bitWidth: 1 - access: read-only - ADDR: - description: Address matched (slave mode) - bitOffset: 3 - bitWidth: 1 - access: read-only - NACKF: - description: Not acknowledge received flag - bitOffset: 4 - bitWidth: 1 - access: read-only - STOPF: - description: Stop detection flag - bitOffset: 5 - bitWidth: 1 - access: read-only - TC: - description: Transfer Complete (master mode) - bitOffset: 6 - bitWidth: 1 - access: read-only - TCR: - description: Transfer Complete Reload - bitOffset: 7 - bitWidth: 1 - access: read-only - BERR: - description: Bus error - bitOffset: 8 - bitWidth: 1 - access: read-only - ARLO: - description: Arbitration lost - bitOffset: 9 - bitWidth: 1 - access: read-only - OVR: - description: Overrun/Underrun (slave mode) - bitOffset: 10 - bitWidth: 1 - access: read-only - PECERR: - description: PEC Error in reception - bitOffset: 11 - bitWidth: 1 - access: read-only - TIMEOUT: - description: Timeout or t_low detection flag - bitOffset: 12 - bitWidth: 1 - access: read-only - ALERT: - description: SMBus alert - bitOffset: 13 - bitWidth: 1 - access: read-only - BUSY: - description: Bus busy - bitOffset: 15 - bitWidth: 1 - access: read-only - DIR: - description: Transfer direction (Slave mode) - bitOffset: 16 - bitWidth: 1 - access: read-only - ADDCODE: - description: Address match code (Slave mode) - bitOffset: 17 - bitWidth: 7 - access: read-only - ICR: - description: Interrupt clear register - addressOffset: 0x1C - size: 0x20 - access: write-only - resetValue: 0x00000000 - fields: - ADDRCF: - description: Address Matched flag clear - bitOffset: 3 - bitWidth: 1 - NACKCF: - description: Not Acknowledge flag clear - bitOffset: 4 - bitWidth: 1 - STOPCF: - description: Stop detection flag clear - bitOffset: 5 - bitWidth: 1 - BERRCF: - description: Bus error flag clear - bitOffset: 8 - bitWidth: 1 - ARLOCF: - description: Arbitration lost flag clear - bitOffset: 9 - bitWidth: 1 - OVRCF: - description: Overrun/Underrun flag clear - bitOffset: 10 - bitWidth: 1 - PECCF: - description: PEC Error flag clear - bitOffset: 11 - bitWidth: 1 - TIMOUTCF: - description: Timeout detection flag clear - bitOffset: 12 - bitWidth: 1 - ALERTCF: - description: Alert flag clear - bitOffset: 13 - bitWidth: 1 - PECR: - description: PEC register - addressOffset: 0x20 - size: 0x20 - access: read-only - resetValue: 0x00000000 - fields: - PEC: - description: Packet error checking register - bitOffset: 0 - bitWidth: 8 - RXDR: - description: Receive data register - addressOffset: 0x24 - size: 0x20 - access: read-only - resetValue: 0x00000000 - fields: - RXDATA: - description: 8-bit receive data - bitOffset: 0 - bitWidth: 8 - TXDR: - description: Transmit data register - addressOffset: 0x28 - size: 0x20 - access: read-write - resetValue: 0x00000000 - fields: - TXDATA: - description: 8-bit transmit data - bitOffset: 0 - bitWidth: 8 +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _delete: CR2 + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: collect/tim/tim11_derive.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml + +UART[4]: + _derive: + CR3: USART1.CR3 + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/f4_rcc_fmpi2c.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllp.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllq.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllm.yaml - - ../peripherals/rcc/rcc_v2_sai_pllp.yaml - - ../peripherals/rcc/rcc_v2_bdcr_lsemod.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f446.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2s12src.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_48m_sd.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_i2csel.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_spdifrxsel.yaml - - ../peripherals/rcc/rcc_v2_ckgatenr.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/i2c/i2c_v2_fmp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_hs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_fixes_v1_446_469.yaml - - common_patches/usb_otg/otg_hs_fixes_v1.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix.yaml - - common_patches/fsmc/fsmc_nand_v1.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/sai/sai.yaml - - common_patches/f4_rtc_cr.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - common_patches/sdio_f446.yaml - - ../peripherals/sdio/sdio.yaml - - ../peripherals/sdio/sdio_f4_common.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f469.yaml b/devices/stm32f469.yaml index 0ace58ae3..a0408da58 100644 --- a/devices/stm32f469.yaml +++ b/devices/stm32f469.yaml @@ -1,5 +1,20 @@ _svd: ../svd/stm32f469.svd +_copy: + OTG_FS_GLOBAL: + from: ../svd/stm32f777.svd:OTG_FS_GLOBAL + OTG_FS_HOST: + from: ../svd/stm32f777.svd:OTG_FS_HOST + OTG_FS_DEVICE: + from: ../svd/stm32f777.svd:OTG_FS_DEVICE + + OTG_HS_GLOBAL: + from: ../svd/stm32f777.svd:OTG_HS_GLOBAL + OTG_HS_HOST: + from: ../svd/stm32f777.svd:OTG_HS_HOST + OTG_HS_DEVICE: + from: ../svd/stm32f777.svd:OTG_HS_DEVICE + _rebase: # Make I2C1 the base type I2C1: I2C3 @@ -10,13 +25,33 @@ _modify: # we'll prefer the more sensible (and better for sorting) ADC_Common C_ADC: name: ADC_Common + DSIHOST: + name: DSI -"SPI*": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0386 - TIFRFE: - name: "FRE" +_derive: + UART7: UART4 + UART8: UART4 + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_c.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml CRC: # The SVD calls the RESET field "CR", fix per RM0386 @@ -24,31 +59,198 @@ CRC: _modify: CR: name: RESET + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +DSI: + _clear_fields: "*" + _add: + _interrupts: + DSIHOST: + description: DSI host global interrupt + value: 92 + _strip: DSI_ + _include: + - collect/dsi/isr.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +#Ethernet_DMA: {} +#Ethernet_MAC: {} +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr1/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - fields/flash/acr/common_f2_f4.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer_mer1.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/bfb2.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/db1m.yaml + - fields/flash/optcr/sprmod.yaml + - fields/flash/optcr/wdg.yaml + - fields/flash/optcr1/nwrp.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/pgserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + - collect/flash/optcr1/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABK]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BK]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: _merge: - - "IV*" + ADD: "ADD[07],ADD10" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +LTDC: + _include: + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +OTG_FS_DEVICE: + _strip: OTG_FS_ + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _strip: OTG_FS_ + _include: + - patches/usb_otg/fs_fixes_446_469.yaml + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _strip: OTG_FS_ + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: + _strip: FS_ + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hs_fixes_446_469.yaml + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + CR: + _add: + ADCDC1: + bitOffset: 13 + bitWidth: 1 + _include: + - patches/pwr/f4.yaml + - fields/pwr/pwr_f469_f479.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml # Fix misnamed RCC enable bits RCC: + APB1RSTR: + _modify: + UART2RST: + name: USART2RST + UART3RST: + name: USART3RST APB1ENR: _modify: UART7ENR: @@ -71,82 +273,156 @@ RCC: name: CK48MSEL SDMMCSEL: name: SDIOSEL + _include: + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/common.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s.yaml + - fields/rcc/v2/i2s_pll.yaml + - fields/rcc/v2/i2s_pllq.yaml + - fields/rcc/v2/sai_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/bdcr_lsemod.yaml + - fields/rcc/v2/dckcfgr_timpre.yaml + - fields/rcc/v2/dckcfgr_i2s_sai_f4.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr_48m_sd.yaml + - fields/rcc/v2/dckcfgr_dsisel.yaml + +RNG: + _include: fields/rng/v1.yaml + CR: + _add: + CED: + description: Clock error detection + bitOffset: 5 + bitWidth: 1 + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/f4_cr.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI: + _delete: + - GCR + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDIO: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + SR: + _modify: + # This field has the wrong name in the SVD compared to RM0386 + TIFRFE: + name: FRE + +SYSCFG: + _include: + - patches/syscfg/f4_common.yaml + - fields/syscfg/f4/syscfg_f469_f479.yaml + MEMRMP: + _delete: + - FB_MODE + PMC: + _delete: + - MII_RMII_SEL + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[01]: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: collect/tim/tim11_derive.yaml + +UART4: + _include: + - patches/usart/v1.yaml + - patches/usart/f4_add_UART_GTPR.yaml + - fields/usart/v2/uart.yaml + +UART[4]: + _include: collect/usart/v1_v2_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# NOTE: Core peripherals (NVIC, MPU, FPU, SCB, etc.) were deleted _include: - - common_patches/4_nvic_prio_bits.yaml - - common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/f2_f4_ethernet.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_v2.yaml - - ../peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml - - ../peripherals/rcc/rcc_v2_i2s.yaml - - ../peripherals/rcc/rcc_v2_i2s_pll.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllq.yaml - - ../peripherals/rcc/rcc_v2_sai_pllp.yaml - - ../peripherals/rcc/rcc_v2_sai_pllr.yaml - - ../peripherals/rcc/rcc_v2_bdcr_lsemod.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f4.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_48m_sd.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dsisel.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/dma/dma2d_v1.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/usart/uart_common.yaml - - ../peripherals/usart/uart_sample.yaml - - ../peripherals/usart/uart_uart.yaml - - ../peripherals/usart/uart_usart.yaml - - ../peripherals/i2c/i2c_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - common_patches/hash/hash.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/usb_otg/otg_hs_remove_prefix.yaml - - common_patches/usb_otg/otg_fs_remove_prefix.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/sai/sai.yaml - - common_patches/f4_rtc_cr.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/sdio/sdio_f4.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/ethernet/f2_f4.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/dbgmcu/dbgmcu.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f722.yaml b/devices/stm32f722.yaml new file mode 100644 index 000000000..b189a97de --- /dev/null +++ b/devices/stm32f722.yaml @@ -0,0 +1,303 @@ +_svd: ../svd/stm32f722.svd + +_derive: + USART3: USART1 + +_rebase: + SPI1: SPI5 + +_modify: + # The SVD calls this C_ADC in some devices and ADC_Common in others, + # we'll prefer the more sensible (and better for sorting) ADC_Common + C_ADC: + name: ADC_Common + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC2: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: {} + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + IMR: + _modify: + MI9: + name: IM9 + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr2/pcrop.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/cr/rderrie.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optcr2/common.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + - collect/flash/optcr2/pcrop.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sdfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_f73_device.yaml + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _delete: + - GI2CCTL + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _include: + - patches/rcc/f7x23_pllsai.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7x23_dckcfgr.yaml + - patches/rcc/f730_f7x2_f7x3.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/v1_common.yaml + # - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f730_f7x2_f7x3.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_cc5if.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - fields/usart/v3/C.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f723.yaml b/devices/stm32f723.yaml new file mode 100644 index 000000000..c5ae2bceb --- /dev/null +++ b/devices/stm32f723.yaml @@ -0,0 +1,302 @@ +_svd: ../svd/stm32f723.svd + +_derive: + USART3: USART1 + +_rebase: + SPI1: SPI5 + +_modify: + # The SVD calls this C_ADC in some devices and ADC_Common in others, + # we'll prefer the more sensible (and better for sorting) ADC_Common + C_ADC: + name: ADC_Common + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC2: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: {} + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + IMR: + _modify: + MI9: + name: IM9 + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr2/pcrop.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/cr/rderrie.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optcr2/common.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + - collect/flash/optcr2/pcrop.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sdfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_f73_device.yaml + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _delete: + - GI2CCTL + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _include: + - patches/rcc/f7x23_pllsai.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7x23_dckcfgr.yaml + - patches/rcc/f730_f7x2_f7x3.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/v1_common.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPI?: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f730_f7x2_f7x3.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_cc5if.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - fields/usart/v3/C.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f730.yaml b/devices/stm32f730.yaml index f6c35c568..500f8b954 100644 --- a/devices/stm32f730.yaml +++ b/devices/stm32f730.yaml @@ -12,62 +12,297 @@ _modify: C_ADC: name: ADC_Common +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC2: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + IMR: + _modify: + MI9: + name: IM9 + +FLASH: + OPTCR2: + _modify: + PCROPi: + name: PCROP + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr2/pcrop.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/cr/rderrie.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optcr2/common.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + - collect/flash/optcr2/pcrop.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sdfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_f73_device.yaml + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _delete: + - GI2CCTL + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _include: + - patches/rcc/f7x23_pllsai.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7x23_dckcfgr.yaml + - patches/rcc/f730_f7x2_f7x3.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/v1_common.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f730_f7x2_f7x3.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_cc5if.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - fields/usart/v3/C.yaml + +USBPHYC: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + _include: - - common_patches/f7x23_pllsai.yaml - - common_patches/dma_fcr_wo.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/f7_rcc_lsedrv.yaml - - common_patches/f7_rcc_dckcfgr.yaml - - common_patches/f7x23_rcc_dckcfgr.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_f7.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_f7.yaml - - ../peripherals/pwr/pwr_v2.yaml - - ../peripherals/flash/flash_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2_without_wakeup.yaml - - ../peripherals/usart/usart_v2C.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sdfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f732.yaml b/devices/stm32f732.yaml new file mode 100644 index 000000000..5bd47e614 --- /dev/null +++ b/devices/stm32f732.yaml @@ -0,0 +1,302 @@ +_svd: ../svd/stm32f732.svd + +_derive: + USART3: USART1 + +_rebase: + SPI1: SPI5 + +_modify: + # The SVD calls this C_ADC in some devices and ADC_Common in others, + # we'll prefer the more sensible (and better for sorting) ADC_Common + C_ADC: + name: ADC_Common + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC2: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: {} + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + IMR: + _modify: + MI9: + name: IM9 + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr2/pcrop.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/cr/rderrie.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optcr2/common.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + - collect/flash/optcr2/pcrop.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sdfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_f73_device.yaml + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _delete: + - GI2CCTL + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _include: + - patches/rcc/f7x23_pllsai.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7x23_dckcfgr.yaml + - patches/rcc/f730_f7x2_f7x3.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/v1_common.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f730_f7x2_f7x3.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_cc5if.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - fields/usart/v3/C.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f733.yaml b/devices/stm32f733.yaml new file mode 100644 index 000000000..6f2586cfc --- /dev/null +++ b/devices/stm32f733.yaml @@ -0,0 +1,302 @@ +_svd: ../svd/stm32f733.svd + +_derive: + USART3: USART1 + +_rebase: + SPI1: SPI5 + +_modify: + # The SVD calls this C_ADC in some devices and ADC_Common in others, + # we'll prefer the more sensible (and better for sorting) ADC_Common + C_ADC: + name: ADC_Common + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC2: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[2]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: {} + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + IMR: + _modify: + MI9: + name: IM9 + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optcr2/pcrop.yaml + - patches/flash/sr/rderr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/cr/rderrie.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optcr2/common.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - fields/flash/sr/rderr.yaml + - collect/flash/optcr/nwrp.yaml + - collect/flash/optcr2/pcrop.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sdfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABH]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hs_f73_device.yaml + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _delete: + - GI2CCTL + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _include: + - patches/rcc/f7x23_pllsai.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7x23_dckcfgr.yaml + - patches/rcc/f730_f7x2_f7x3.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +SAI1: + _include: + - patches/sai/v1_common.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f730_f7x2_f7x3.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_cc5if.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - fields/usart/v3/C.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/adc/adc_common_group_name.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f745.yaml b/devices/stm32f745.yaml index 4d638d8ae..c210d0c69 100644 --- a/devices/stm32f745.yaml +++ b/devices/stm32f745.yaml @@ -5,6 +5,15 @@ _svd: ../svd/stm32f745.svd _rebase: USART1: USART6 +_derive: + SPI3: SPI1 + SPI6: SPI1 + TIM4: TIM3 + +_copy: + TIM5: + from: TIM2 + _modify: # The SVD calls this C_ADC in some devices and ADC_Common in others, # we'll prefer the more sensible (and better for sorting) ADC_Common @@ -14,47 +23,89 @@ _modify: SPDIF_RX: name: SPDIFRX -"SPI3": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0410 - "[_]FRE": - name: "FRE" +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml -"GPIO*": - _modify: - # SVD calls call OSPEEDR regs GPIOB_OSPEEDR, so fix that. - GPIOB_OSPEEDR: - name: OSPEEDR +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml -FLASH: - OPTKEYR: - _modify: - OPTKEY: - name: OPTKEYR +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - fields/hdmi_cec.yaml CRC: - # The SVD calls the RESET field "CR", and misses some fields, fix per RM0410 - CR: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + _add: + _interrupts: + PVD: + description: PVD through EXTI line detection interrupt + value: 1 + +Ethernet_DMA: + DMABMR: _modify: - CR: - name: RESET - _add: - REV_OUT: - description: Reverse output data - bitOffset: 7 - bitWidth: 1 - access: read-write - REV_IN: - description: Reverse input data - bitOffset: 5 - bitWidth: 2 - access: read-write - POLYSIZE: - description: Polynomial size - bitOffset: 3 - bitWidth: 2 - access: read-write + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM Ethernet_MAC: MACFFR: @@ -80,116 +131,316 @@ Ethernet_MAC: MBCA3L: name: MACA3L -Ethernet_DMA: - DMABMR: +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + DCKCFGR1: + _delete: + - ADFSDM1SEL + - DFSDM1SEL + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_sdmmc1.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + "MEMRM,MEMRMP": + _delete: + - FB_MODE + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_bkf.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: _modify: - # This field is named incorrectly in the SVD compared to the RM - RTPR: - name: PM + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/f7_interrupts.yaml - - common_patches/f7_lptim_interrupt.yaml - - common_patches/f7_ltdc_interrupts.yaml - - common_patches/pllsai.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/rcc_add_plli2sp.yaml - - common_patches/f7_rcc_apbenr.yaml - - common_patches/f7_rcc_lsedrv.yaml - - common_patches/f7_rcc_rename_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr_sdmmc1.yaml - - common_patches/f7_rcc_dckcfgr_RM0410.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_f7.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllp.yaml - - ../peripherals/rcc/rcc_v2_sai_pllr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f7.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dsisel.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_f7.yaml - - ../peripherals/pwr/pwr_v2.yaml - - ../peripherals/flash/flash_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/hash/hash.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/dma/dma2d_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml + - patches/f7_interrupts.yaml + - patches/f7_lptim_interrupt.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/adc/adc_common_group_name.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f746.yaml b/devices/stm32f746.yaml new file mode 100644 index 000000000..80b0c4642 --- /dev/null +++ b/devices/stm32f746.yaml @@ -0,0 +1,419 @@ +_svd: ../svd/stm32f746.svd + +_rebase: + USART1: USART6 + +_derive: + SPI2: SPI1 + TIM4: TIM3 + +_copy: + TIM5: + from: TIM2 + +_modify: + # The SVD calls this C_ADC in some devices and ADC_Common in others, + # we'll prefer the more sensible (and better for sorting) ADC_Common + C_ADC: + name: ADC_Common + # Remove underscore to be consistent with other parts and RM + SPDIF_RX: + name: SPDIFRX + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - fields/hdmi_cec.yaml + +CRC: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +Ethernet_DMA: + DMABMR: + _modify: + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM + +Ethernet_MAC: + MACFFR: + _modify: + # This field should be 2 bits wide but is only 1 bit in the SVD + PCF: + bitWidth: 2 + # All these fields are named incorrectly in the SVD compared to RM0090 + MACA2HR: + _modify: + MAC2AH: + name: MACA2H + MACA2LR: + _modify: + MACA2L: + bitWidth: 32 + +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/erserr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_sdmmc1.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + "MEMRM,MEMRMP": + _delete: + - FB_MODE + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_bkf.yaml + - patches/tim/v2/add_af.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/f7_lptim_interrupt.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/adc/adc_common_group_name.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f750.yaml b/devices/stm32f750.yaml new file mode 100644 index 000000000..cd73da123 --- /dev/null +++ b/devices/stm32f750.yaml @@ -0,0 +1,402 @@ +_svd: ../svd/stm32f750.svd + +_rebase: + USART1: USART6 + +_derive: + SPI2: SPI1 + TIM4: TIM3 + +_copy: + TIM5: + from: TIM2 + +_modify: + # The SVD calls this C_ADC in some devices and ADC_Common in others, + # we'll prefer the more sensible (and better for sorting) ADC_Common + C_ADC: + name: ADC_Common + # Remove underscore to be consistent with other parts and RM + SPDIF_RX: + name: SPDIFRX + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - fields/hdmi_cec.yaml + +CRC: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +#Ethernet_DMA: {} +#Ethernet_MAC: {} +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/erserr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_sdmmc1.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + "MEMRM,MEMRMP": + _delete: + - FB_MODE + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_bkf.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/adc/adc_common_group_name.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/ethernet/f2_f4.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f756.yaml b/devices/stm32f756.yaml new file mode 100644 index 000000000..ff336dcf8 --- /dev/null +++ b/devices/stm32f756.yaml @@ -0,0 +1,427 @@ +_svd: ../svd/stm32f756.svd + +_rebase: + USART1: USART6 + +_derive: + SPI2: SPI1 + TIM4: TIM3 + +_copy: + TIM5: + from: TIM2 + +_modify: + # The SVD calls this C_ADC in some devices and ADC_Common in others, + # we'll prefer the more sensible (and better for sorting) ADC_Common + C_ADC: + name: ADC_Common + # Remove underscore to be consistent with other parts and RM + SPDIF_RX: + name: SPDIFRX + +ADC_Common: + _include: + - patches/adc/multi.yaml + - fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - fields/hdmi_cec.yaml + +CRC: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v2.yaml + - fields/dma/dma_v2.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +Ethernet_DMA: + DMABMR: + _modify: + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM + +Ethernet_MAC: + MACFFR: + _modify: + # This field should be 2 bits wide but is only 1 bit in the SVD + PCF: + bitWidth: 2 + # All these fields are named incorrectly in the SVD compared to RM0090 + MACA1LR: + _modify: + MACA1LR: + name: MACA1L + MACA2HR: + _modify: + MAC2AH: + name: MACA2H + MACA2LR: + _modify: + MACA2L: + bitWidth: 32 + MACA3LR: + _modify: + MBCA3L: + name: MACA3L + +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/erserr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_sdmmc1.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + "MEMRM,MEMRMP": + _delete: + - FB_MODE + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_bkf.yaml + - patches/tim/v2/add_af.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/f7_lptim_interrupt.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/adc/adc_common_group_name.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml diff --git a/devices/stm32f765.yaml b/devices/stm32f765.yaml index 6794bed46..ba2d5647a 100644 --- a/devices/stm32f765.yaml +++ b/devices/stm32f765.yaml @@ -5,6 +5,15 @@ _svd: ../svd/stm32f765.svd _rebase: USART1: USART6 +_derive: + SPI3: SPI1 + SPI6: SPI1 + TIM4: TIM3 + +_copy: + TIM5: + from: TIM2 + _modify: # The SVD calls this C_ADC in some devices and ADC_Common in others, # we'll prefer the more sensible (and better for sorting) ADC_Common @@ -14,56 +23,76 @@ _modify: SPDIF_RX: name: SPDIFRX -"SPI3": - SR: - _modify: - # This field has the wrong name in the SVD compared to RM0410 - "[_]FRE": - name: "FRE" +ADC_Common: + _include: fields/adc/adc_v2_multi.yaml -"GPIO*": - _modify: - # SVD calls call OSPEEDR regs GPIOB_OSPEEDR, so fix that. - GPIOB_OSPEEDR: - name: OSPEEDR +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml -FLASH: - OPTKEYR: - _modify: - OPTKEY: - name: OPTKEYR +ADC[1]: + _include: collect/adc/derive_sq.yaml -RCC: - PLLCFGR: - _add: - PLLR: - description: PLL division factor for DSI clock - bitOffset: 28 - bitWidth: 3 - access: read-write +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - fields/hdmi_cec.yaml CRC: - # The SVD calls the RESET field "CR", and misses some fields, fix per RM0410 - CR: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +Ethernet_DMA: + DMABMR: _modify: - CR: - name: RESET - _add: - REV_OUT: - description: Reverse output data - bitOffset: 7 - bitWidth: 1 - access: read-write - REV_IN: - description: Reverse input data - bitOffset: 5 - bitWidth: 2 - access: read-write - POLYSIZE: - description: Polynomial size - bitOffset: 3 - bitWidth: 2 - access: read-write + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM Ethernet_MAC: MACFFR: @@ -89,117 +118,335 @@ Ethernet_MAC: MBCA3L: name: MACA3L -Ethernet_DMA: - DMABMR: +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + _add: + _interrupts: + PVD: + description: PVD through EXTI line detection interrupt + value: 1 + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/cr/mer1_mer2.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer1_mer2.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr/ndbank_ndboot.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + PLLCFGR: + _add: + PLLR: + description: PLL division factor for DSI clock + bitOffset: 28 + bitWidth: 3 + access: read-write + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_RM0410.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/f765_f7x7_f7x9_common.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr_dfsdm_f7.yaml + - fields/rcc/v2/dckcfgr_dsisel.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/syscfg/f765_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_bkf.yaml + - patches/tim/v2/add_af.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP _modify: - # This field is named incorrectly in the SVD compared to the RM - RTPR: - name: PM + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/f7_interrupts.yaml - - common_patches/f7_lptim_interrupt.yaml - - common_patches/f7_ltdc_interrupts.yaml - - common_patches/pllsai.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/rcc_add_plli2sp.yaml - - common_patches/f7_rcc_apbenr.yaml - - common_patches/f7_rcc_lsedrv.yaml - - common_patches/f7_rcc_rename_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr_sdmmc1.yaml - - common_patches/f7_rcc_dckcfgr_RM0410.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_f7.yaml - - ../peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllp.yaml - - ../peripherals/rcc/rcc_v2_sai_pllr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f7.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dsisel.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v21.yaml - - ../peripherals/dma/dma_v21.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_f7.yaml - - ../peripherals/pwr/pwr_v2.yaml - - ../peripherals/flash/flash_v2_dual_bank.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/hash/hash.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/dma/dma2d_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml + - patches/f7_interrupts.yaml + - patches/f7_lptim_interrupt.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - patches/adc/adc_common_group_name.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/dbgmcu.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f767.yaml b/devices/stm32f767.yaml new file mode 100644 index 000000000..2f61984f6 --- /dev/null +++ b/devices/stm32f767.yaml @@ -0,0 +1,484 @@ +_svd: ../svd/stm32f767.svd + +_delete: + - DBGMCU + +_rebase: + USART1: USART6 + +_derive: + TIM4: TIM3 + +_copy: + TIM5: + from: TIM2 + +_modify: + # Fix typo in the name of the LTDC peripheral + LTCD: + name: LTDC + Flash: + name: FLASH + +ADC_Common: + _include: fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _add: + _interrupts: + HDMI_CEC: + description: HDMI-CEC global interrupt + value: 94 + _include: + - fields/hdmi_cec.yaml + +CRC: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _strip: DFSDM_ + _modify: + DFSDM3_CR1: + addressOffset: 0x280 + _include: + - patches/dfsdm/f7.yaml + - fields/dfsdm/f7.yaml + - collect/dfsdm/f7.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +DSI: + _strip: DSI_ + _include: + - patches/dsi/f7_wpcr.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMABMR: + _modify: + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM + +Ethernet_MAC: + MACFFR: + _modify: + # This field should be 2 bits wide but is only 1 bit in the SVD + PCF: + bitWidth: 2 + # All these fields are named incorrectly in the SVD compared to RM0090 + MACA1LR: + _modify: + MACA1LR: + name: MACA1L + MACA2HR: + _modify: + MAC2AH: + name: MACA2H + MACA2LR: + _modify: + MACA2L: + bitWidth: 32 + MACA3LR: + _modify: + MBCA3L: + name: MACA3L + +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/cr/mer1_mer2.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/erserr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer1_mer2.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr/ndbank_ndboot.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: + _strip: JPEG_ + _include: + - collect/jpeg/ram_f7.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + _include: + - collect/mdios/dinr_doutr.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _modify: + OTG_DIEPTXF8: + name: DIEPTXF8 + HNPTXFSIZ_Host: + name: HNPTXFSIZ + DIEPTXF0_Device: + name: DIEPTXF0 + alternateRegister: HNPTXFSIZ + GNPTXSTS: + name: HNPTXSTS + _include: + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + PLLCFGR: + _add: + PLLR: + description: PLL division factor for DSI clock + bitOffset: 28 + bitWidth: 3 + access: read-write + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_RM0410.yaml + - patches/rcc/f765_f7x7_f7x9_common.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr_dfsdm_f7.yaml + - fields/rcc/v2/dckcfgr_dsisel.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/syscfg/f765_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/ltdc/rename.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f7.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f769.yaml b/devices/stm32f769.yaml new file mode 100644 index 000000000..4b9a72d70 --- /dev/null +++ b/devices/stm32f769.yaml @@ -0,0 +1,488 @@ +_svd: ../svd/stm32f769.svd + +_rebase: + USART1: USART6 + +_copy: + DFSDM: + from: ../svd/stm32f767.svd:DFSDM + TIM5: + from: TIM2 + +_derive: + TIM4: TIM3 + +_modify: + # Fix typo in the name of the LTDC peripheral + LTCD: + name: LTDC + Flash: + name: FLASH + +ADC_Common: + _include: fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - fields/hdmi_cec.yaml + +CRC: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +# TODO: fix DBG +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _strip: DFSDM_ + _modify: + DFSDM3_CR1: + addressOffset: 0x280 + _include: + - patches/dfsdm/f7.yaml + - fields/dfsdm/f7.yaml + - collect/dfsdm/f7.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +DSI: + _strip: DSI_ + _include: + - patches/dsi/f7_wpcr.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMABMR: + _modify: + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM + +Ethernet_MAC: + MACFFR: + _modify: + # This field should be 2 bits wide but is only 1 bit in the SVD + PCF: + bitWidth: 2 + # All these fields are named incorrectly in the SVD compared to RM0090 + MACA1LR: + _modify: + MACA1LR: + name: MACA1L + MACA2HR: + _modify: + MAC2AH: + name: MACA2H + MACA2LR: + _modify: + MACA2L: + bitWidth: 32 + MACA3LR: + _modify: + MBCA3L: + name: MACA3L + +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/cr/mer1_mer2.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/erserr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer1_mer2.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr/ndbank_ndboot.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C2: + _add: + _interrupts: + I2C2_EV: + description: I2C2 event interrupt + value: 33 + I2C2_ER: + description: I2C2 error interrupt + value: 34 + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: + _strip: JPEG_ + _include: + - collect/jpeg/ram_f7.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _add: + _interrupts: + LCD_TFT_1: + description: LCD-TFT global error interrupt + value: 89 + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + _include: + - collect/mdios/dinr_doutr.yaml + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + PLLCFGR: + _add: + PLLR: + description: PLL division factor for DSI clock + bitOffset: 28 + bitWidth: 3 + access: read-write + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_RM0410.yaml + - patches/rcc/f765_f7x7_f7x9_common.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr_dfsdm_f7.yaml + - fields/rcc/v2/dckcfgr_dsisel.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/syscfg/f765_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_bkf.yaml + - patches/tim/v2/add_af.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/ltdc/rename.yaml + - patches/f7_lptim_interrupt.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f7.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f777.yaml b/devices/stm32f777.yaml new file mode 100644 index 000000000..2252826d7 --- /dev/null +++ b/devices/stm32f777.yaml @@ -0,0 +1,475 @@ +_svd: ../svd/stm32f777.svd + +_delete: + - DBGMCU + +_rebase: + USART1: USART6 + +_derive: + TIM4: TIM3 + +_copy: + TIM5: + from: TIM2 + +_modify: + # Fix typo in the name of the LTDC peripheral + LTCD: + name: LTDC + Flash: + name: FLASH + +ADC_Common: + _include: fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _add: + _interrupts: + HDMI_CEC: + description: HDMI-CEC global interrupt + value: 94 + _include: + - fields/hdmi_cec.yaml + +CRC: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _strip: DFSDM_ + _modify: + DFSDM3_CR1: + addressOffset: 0x280 + _include: + - patches/dfsdm/f7.yaml + - fields/dfsdm/f7.yaml + - collect/dfsdm/f7.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +DSI: + _strip: DSI_ + _include: + - patches/dsi/f7_wpcr.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMABMR: + _modify: + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM + +Ethernet_MAC: + MACFFR: + _modify: + # This field should be 2 bits wide but is only 1 bit in the SVD + PCF: + bitWidth: 2 + # All these fields are named incorrectly in the SVD compared to RM0090 + MACA1LR: + _modify: + MACA1LR: + name: MACA1L + MACA2HR: + _modify: + MAC2AH: + name: MACA2H + MACA2LR: + _modify: + MACA2L: + bitWidth: 32 + MACA3LR: + _modify: + MBCA3L: + name: MACA3L + +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/cr/mer1_mer2.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/erserr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer1_mer2.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr/ndbank_ndboot.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: + _strip: JPEG_ + _include: + - collect/jpeg/ram_f7.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + _include: + - collect/mdios/dinr_doutr.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + PLLCFGR: + _add: + PLLR: + description: PLL division factor for DSI clock + bitOffset: 28 + bitWidth: 3 + access: read-write + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_RM0410.yaml + - patches/rcc/f765_f7x7_f7x9_common.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr_dfsdm_f7.yaml + - fields/rcc/v2/dckcfgr_dsisel.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/syscfg/f765_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/ltdc/rename.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f7.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f778.yaml b/devices/stm32f778.yaml new file mode 100644 index 000000000..5d42e53fe --- /dev/null +++ b/devices/stm32f778.yaml @@ -0,0 +1,488 @@ +_svd: ../svd/stm32f778.svd + +_rebase: + USART1: USART6 + +_copy: + DFSDM: + from: ../svd/stm32f767.svd:DFSDM + TIM5: + from: TIM2 + +_derive: + TIM4: TIM3 + +_modify: + # Fix typo in the name of the LTDC peripheral + LTCD: + name: LTDC + Flash: + name: FLASH + +ADC_Common: + _include: fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - fields/hdmi_cec.yaml + +CRC: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +# TODO fix DBG +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _strip: DFSDM_ + _modify: + DFSDM3_CR1: + addressOffset: 0x280 + _include: + - patches/dfsdm/f7.yaml + - fields/dfsdm/f7.yaml + - collect/dfsdm/f7.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +DSI: + _strip: DSI_ + _include: + - patches/dsi/f7_wpcr.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMABMR: + _modify: + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM + +Ethernet_MAC: + MACFFR: + _modify: + # This field should be 2 bits wide but is only 1 bit in the SVD + PCF: + bitWidth: 2 + # All these fields are named incorrectly in the SVD compared to RM0090 + MACA1LR: + _modify: + MACA1LR: + name: MACA1L + MACA2HR: + _modify: + MAC2AH: + name: MACA2H + MACA2LR: + _modify: + MACA2L: + bitWidth: 32 + MACA3LR: + _modify: + MBCA3L: + name: MACA3L + +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/cr/mer1_mer2.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/erserr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer1_mer2.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr/ndbank_ndboot.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C2: + _add: + _interrupts: + I2C2_EV: + description: I2C2 event interrupt + value: 33 + I2C2_ER: + description: I2C2 error interrupt + value: 34 + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: + _strip: JPEG_ + _include: + - collect/jpeg/ram_f7.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _add: + _interrupts: + LCD_TFT_1: + description: LCD-TFT global error interrupt + value: 89 + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + _include: + - collect/mdios/dinr_doutr.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + PLLCFGR: + _add: + PLLR: + description: PLL division factor for DSI clock + bitOffset: 28 + bitWidth: 3 + access: read-write + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_RM0410.yaml + - patches/rcc/f765_f7x7_f7x9_common.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr_dfsdm_f7.yaml + - fields/rcc/v2/dckcfgr_dsisel.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/syscfg/f765_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_bkf.yaml + - patches/tim/v2/add_af.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/ltdc/rename.yaml + - patches/f7_lptim_interrupt.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f7.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f779.yaml b/devices/stm32f779.yaml new file mode 100644 index 000000000..93a01395a --- /dev/null +++ b/devices/stm32f779.yaml @@ -0,0 +1,488 @@ +_svd: ../svd/stm32f779.svd + +_rebase: + USART1: USART6 + +_copy: + DFSDM: + from: ../svd/stm32f767.svd:DFSDM + TIM5: + from: TIM2 + +_derive: + TIM4: TIM3 + +_modify: + # Fix typo in the name of the LTDC peripheral + LTCD: + name: LTDC + Flash: + name: FLASH + +ADC_Common: + _include: fields/adc/adc_v2_multi.yaml + +ADC1: + _include: + - patches/adc/smpx_18.yaml + - fields/adc/adc_v2.yaml + - fields/adc/adc_v2/adc_v2_extsel_d.yaml + - collect/adc/jofr_jdr.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +CEC: + _include: + - fields/hdmi_cec.yaml + +CRC: + _modify: + INIT: + addressOffset: 0x10 + POL: + addressOffset: 0x14 + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/f7_polysize_rev_in_rev_out.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRYP: + _include: + - patches/cryp/merge_fields.yaml + - collect/cryp/v2.yaml + +DAC: + _include: + - fields/dac/f2_4_7.yaml + - collect/dac/v2.yaml + +# TODO fix DBG +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v1.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _strip: DFSDM_ + _modify: + DFSDM3_CR1: + addressOffset: 0x280 + _include: + - patches/dfsdm/f7.yaml + - fields/dfsdm/f7.yaml + - collect/dfsdm/f7.yaml + +DMA2: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/dma_v21.yaml + - fields/dma/dma_v21.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +DSI: + _strip: DSI_ + _include: + - patches/dsi/f7_wpcr.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMABMR: + _modify: + # This field is named incorrectly in the SVD compared to the RM + RTPR: + name: PM + +Ethernet_MAC: + MACFFR: + _modify: + # This field should be 2 bits wide but is only 1 bit in the SVD + PCF: + bitWidth: 2 + # All these fields are named incorrectly in the SVD compared to RM0090 + MACA1LR: + _modify: + MACA1LR: + name: MACA1L + MACA2HR: + _modify: + MAC2AH: + name: MACA2H + MACA2LR: + _modify: + MACA2L: + bitWidth: 32 + MACA3LR: + _modify: + MBCA3L: + name: MACA3L + +#Ethernet_MMC: {} +#Ethernet_PTP: {} + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +FLASH: + _include: + - patches/flash/acr/latency_16_states.yaml + - patches/flash/cr/mer1_mer2.yaml + - patches/flash/optcr/nwrp.yaml + - patches/flash/optkeyr/optkeyr.yaml + - patches/flash/sr/erserr.yaml + - fields/flash/acr/common_f7.yaml + - fields/flash/acr/latency_16_states.yaml + - fields/flash/cr/common_f2_f4_f7.yaml + - fields/flash/cr/errie.yaml + - fields/flash/cr/mer1_mer2.yaml + - fields/flash/keyr/common.yaml + - fields/flash/optcr/common.yaml + - fields/flash/optcr/iwdg_wwdg.yaml + - fields/flash/optcr/ndbank_ndboot.yaml + - fields/flash/optcr1/boot.yaml + - fields/flash/optkeyr/common.yaml + - fields/flash/sr/common_f2_f4_f7.yaml + - fields/flash/sr/erserr.yaml + - collect/flash/optcr/nwrp.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABD]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BD]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C2: + _add: + _interrupts: + I2C2_EV: + description: I2C2 event interrupt + value: 33 + I2C2_ER: + description: I2C2 error interrupt + value: 34 + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: + _strip: JPEG_ + _include: + - collect/jpeg/ram_f7.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LTDC: + _add: + _interrupts: + LCD_TFT_1: + description: LCD-TFT global error interrupt + value: 89 + _include: + - patches/ltdc/f7_ltdc_interrupts.yaml + - patches/ltdc/ltdc.yaml + - patches/ltdc/f4_f7_ltdc_bccr.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + _include: + - collect/mdios/dinr_doutr.yaml + +OTG_FS_*: + _strip: OTG_FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v2_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v2_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_host_addr.yaml + - patches/usb_otg/fs_v2_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +OTG_HS_*: + _strip: OTG_HS_ + +OTG_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG_HS_PWRCLK: {} + +PWR: + _include: + - fields/pwr/pwr_f7.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + PLLCFGR: + _add: + PLLR: + description: PLL division factor for DSI clock + bitOffset: 28 + bitWidth: 3 + access: read-write + _include: + - patches/rcc/pllsai.yaml + - patches/rcc/add_plli2sp.yaml + - patches/rcc/f7_apbenr.yaml + - patches/rcc/f7_lsedrv.yaml + - patches/rcc/f7_rename_dckcfgr.yaml + - patches/rcc/f7_dckcfgr.yaml + - patches/rcc/f7_dckcfgr_RM0410.yaml + - patches/rcc/f765_f7x7_f7x9_common.yaml + - patches/rcc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/rcc/rcc_merge_sw_sws.yaml + - patches/rcc/rcc_merge_rtcsel.yaml + - fields/rcc/v2/f7.yaml + - fields/rcc/v2/pllcfgr_pllr.yaml + - fields/rcc/v2/i2s_pllp.yaml + - fields/rcc/v2/sai_pllr.yaml + - fields/rcc/v2/dckcfgr_saidivr.yaml + - fields/rcc/v2/dckcfgr_dfsdm_f7.yaml + - fields/rcc/v2/dckcfgr_dsisel.yaml + - fields/rcc/v2/dckcfgr2_cecsel.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1.yaml + - collect/sdio/resp.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - patches/syscfg/f745_f750_f765_f7x6_f7x7_f7x9.yaml + - patches/syscfg/f765_f7x7_f7x9.yaml + +TIM1: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_cc4np.yaml + - patches/tim/v2/add_bkf.yaml + - patches/tim/v2/add_af.yaml + - patches/tim/v2/add_cc5.yaml + - patches/tim/dmab_32.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + CRR6: + name: CCR6 + +TIM[25]: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + _modify: + OR1: + name: OR + _delete: + - OR2 + +TIM2: + OR: + _delete: + - TI4_RMP + - ETR1_RMP + _modify: + ITR1_RMP: + bitOffset: 10 + bitWidth: 2 + +TIM5: + _include: collect/tim/tim5_derive.yaml + OR: + _modify: + TI4_RMP: + bitOffset: 6 + _delete: + - ETR1_RMP + - ITR1_RMP + +TIM3: + _include: + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + _delete: + - OR1 + - OR2 + +TIM6: + _include: + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v2/tim6.yaml + +TIM9: + _include: + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - patches/tim/v2/add_ocm2_bit3.yaml + - patches/tim/v2/add_sms_bit3.yaml + - patches/tim/tim9_ic1f.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/uifremap_fix.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/v2/add_ocm1_bit3.yaml + - fields/tim/v2/tim10.yaml + - collect/tim/ccr.yaml + _delete: + - SMCR + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/ltdc/rename.yaml + - patches/f7_lptim_interrupt.yaml + - patches/ethernet/mac_regs.yaml + - patches/ethernet/mmc.yaml + - fields/eth/eth_dma_common.yaml + - fields/eth/eth_dma_mb_edfe_dmarswtr.yaml + - fields/eth/eth_mac_common.yaml + - fields/eth/eth_mac_cstf.yaml + - fields/eth/eth_mmc_common.yaml + - fields/eth/eth_mmc_mcfhp_mcp.yaml + - patches/tim/group.yaml + - patches/dbgmcu/f7.yaml + - patches/ethernet/f4_f7.yaml + - fields/eth/eth_ptp_ppsfreq.yaml diff --git a/devices/stm32f7x2.yaml b/devices/stm32f7x2.yaml deleted file mode 100644 index 9737f14fb..000000000 --- a/devices/stm32f7x2.yaml +++ /dev/null @@ -1,74 +0,0 @@ -_svd: ../svd/stm32f7x2.svd - -_derive: - USART3: USART1 - -_rebase: - SPI1: SPI5 - -_modify: - # The SVD calls this C_ADC in some devices and ADC_Common in others, - # we'll prefer the more sensible (and better for sorting) ADC_Common - C_ADC: - name: ADC_Common - -_include: - - common_patches/f7x23_pllsai.yaml - - common_patches/dma_fcr_wo.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/f7_rcc_lsedrv.yaml - - common_patches/f7_rcc_dckcfgr.yaml - - common_patches/f7x23_rcc_dckcfgr.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_f7.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v21.yaml - - ../peripherals/dma/dma_v21.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_f7.yaml - - ../peripherals/pwr/pwr_v2.yaml - - ../peripherals/flash/flash_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2_without_wakeup.yaml - - ../peripherals/usart/usart_v2C.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sdfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml diff --git a/devices/stm32f7x3.yaml b/devices/stm32f7x3.yaml deleted file mode 100644 index 2f907b321..000000000 --- a/devices/stm32f7x3.yaml +++ /dev/null @@ -1,84 +0,0 @@ -_svd: ../svd/stm32f7x3.svd - -_derive: - USART3: USART1 - -_rebase: - SPI1: SPI5 - -_modify: - # The SVD calls this C_ADC in some devices and ADC_Common in others, - # we'll prefer the more sensible (and better for sorting) ADC_Common - C_ADC: - name: ADC_Common - -# Registers name are prefixed with WWDG_. Use common names. -WWDG: - _modify: - WWDG_CR: - name: CR - WWDG_CFR: - name: CFR - WWDG_SR: - name: SR - -_include: - - common_patches/f7x23_pllsai.yaml - - common_patches/dma_fcr_wo.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/f7_rcc_lsedrv.yaml - - common_patches/f7_rcc_dckcfgr.yaml - - common_patches/f7x23_rcc_dckcfgr.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_f7.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v21.yaml - - ../peripherals/dma/dma_v21.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_f7.yaml - - ../peripherals/pwr/pwr_v2.yaml - - ../peripherals/flash/flash_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2_without_wakeup.yaml - - ../peripherals/usart/usart_v2C.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sdfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml diff --git a/devices/stm32f7x6.yaml b/devices/stm32f7x6.yaml deleted file mode 100644 index 24de5b14f..000000000 --- a/devices/stm32f7x6.yaml +++ /dev/null @@ -1,183 +0,0 @@ -_svd: ../svd/stm32f7x6.svd - -_rebase: - USART1: USART6 - -_modify: - # The SVD calls this C_ADC in some devices and ADC_Common in others, - # we'll prefer the more sensible (and better for sorting) ADC_Common - C_ADC: - name: ADC_Common - # Remove underscore to be consistent with other parts and RM - SPDIF_RX: - name: SPDIFRX - -"GPIO*": - _modify: - # SVD calls call OSPEEDR regs GPIOB_OSPEEDR, so fix that. - GPIOB_OSPEEDR: - name: OSPEEDR - -FLASH: - OPTKEYR: - _modify: - OPTKEY: - name: OPTKEYR - -CRC: - # The SVD calls the RESET field "CR", and misses some fields, fix per RM0410 - CR: - _modify: - CR: - name: RESET - _add: - REV_OUT: - description: Reverse output data - bitOffset: 7 - bitWidth: 1 - access: read-write - REV_IN: - description: Reverse input data - bitOffset: 5 - bitWidth: 2 - access: read-write - POLYSIZE: - description: Polynomial size - bitOffset: 3 - bitWidth: 2 - access: read-write - -Ethernet_MAC: - MACFFR: - _modify: - # This field should be 2 bits wide but is only 1 bit in the SVD - PCF: - bitWidth: 2 - # All these fields are named incorrectly in the SVD compared to RM0090 - MACA1LR: - _modify: - MACA1LR: - name: MACA1L - MACA2HR: - _modify: - MAC2AH: - name: MACA2H - MACA2LR: - _modify: - MACA2L: - bitWidth: 32 - MACA3LR: - _modify: - MBCA3L: - name: MACA3L - -Ethernet_DMA: - DMABMR: - _modify: - # This field is named incorrectly in the SVD compared to the RM - RTPR: - name: PM - -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" - -_include: - - common_patches/f7_interrupts.yaml - - common_patches/f7_lptim_interrupt.yaml - - common_patches/f7_ltdc_interrupts.yaml - - common_patches/pllsai.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/rcc_add_plli2sp.yaml - - common_patches/f7_rcc_apbenr.yaml - - common_patches/f7_rcc_lsedrv.yaml - - common_patches/f7_rcc_rename_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr_sdmmc1.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_f7.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllp.yaml - - ../peripherals/rcc/rcc_v2_sai_pllr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v2.yaml - - ../peripherals/dma/dma_v2.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_f7.yaml - - ../peripherals/pwr/pwr_v2.yaml - - ../peripherals/flash/flash_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/hash/hash.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dbgmcu.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/dma/dma2d_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml diff --git a/devices/stm32f7x7.yaml b/devices/stm32f7x7.yaml deleted file mode 100644 index eeec0ef74..000000000 --- a/devices/stm32f7x7.yaml +++ /dev/null @@ -1,353 +0,0 @@ -_svd: ../svd/stm32f7x7.svd - -_rebase: - USART1: USART6 - -_add: - # This SVD is missing the ADC_Common peripheral that most other parts with - # this ADC contain; consequently it's missing the CSR and CCR and CDR regs - # from RM0410. - ADC_Common: - description: ADC common registers - groupName: ADC - baseAddress: 0x40012300 - addressBlock: - offset: 0x0 - size: 0x400 - usage: registers - registers: - CSR: - description: ADC common status register - addressOffset: 0x0 - access: read-only - resetValue: 0x00000000 - fields: - OVR3: - description: Overrun flag of ADC3 - bitOffset: 21 - bitWidth: 1 - STRT3: - description: Regular channel Start flag of ADC3 - bitOffset: 20 - bitWidth: 1 - JSTRT3: - description: Injected channel Start flag of ADC3 - bitOffset: 19 - bitWidth: 1 - JEOC3: - description: Injected channel end of conversion of ADC3 - bitOffset: 18 - bitWidth: 1 - EOC3: - description: End of conversion of ADC3 - bitOffset: 17 - bitWidth: 1 - AWD3: - description: Analog watchdog flag of ADC3 - bitOffset: 16 - bitWidth: 1 - - OVR2: - description: Overrun flag of ADC2 - bitOffset: 13 - bitWidth: 1 - STRT2: - description: Regular channel Start flag of ADC2 - bitOffset: 12 - bitWidth: 1 - JSTRT2: - description: Injected channel Start flag of ADC2 - bitOffset: 11 - bitWidth: 1 - JEOC2: - description: Injected channel end of conversion of ADC2 - bitOffset: 10 - bitWidth: 1 - EOC2: - description: End of conversion of ADC2 - bitOffset: 9 - bitWidth: 1 - AWD2: - description: Analog watchdog flag of ADC2 - bitOffset: 8 - bitWidth: 1 - - OVR1: - description: Overrun flag of ADC1 - bitOffset: 5 - bitWidth: 1 - STRT1: - description: Regular channel Start flag of ADC1 - bitOffset: 4 - bitWidth: 1 - JSTRT1: - description: Injected channel Start flag of ADC1 - bitOffset: 3 - bitWidth: 1 - JEOC1: - description: Injected channel end of conversion of ADC1 - bitOffset: 2 - bitWidth: 1 - EOC1: - description: End of conversion of ADC1 - bitOffset: 1 - bitWidth: 1 - AWD1: - description: Analog watchdog flag of ADC1 - bitOffset: 0 - bitWidth: 1 - - CCR: - description: ADC common control register - addressOffset: 0x04 - access: read-write - resetValue: 0x00000000 - fields: - TSVREFE: - description: Temperature sensor and V_REFINT enable - bitOffset: 23 - bitWidth: 1 - VBATE: - description: V_BAT enable - bitOffset: 22 - bitWidth: 1 - ADCPRE: - description: ADC prescaler - bitOffset: 16 - bitWidth: 2 - DMA: - description: Direct memory access mode for multi ADC mode - bitOffset: 14 - bitWidth: 2 - DDS: - description: DMA disable selection (for multi-ADC mode) - bitOffset: 13 - bitWidth: 1 - DELAY: - description: Delay between 2 sampling phases - bitOffset: 8 - bitWidth: 4 - MULTI: - description: Multi ADC mode selection - bitOffset: 0 - bitWidth: 4 - - CDR: - description: ADC common regular data register for dual and triple modes - addressOffset: 0x08 - access: read-only - resetValue: 0x00000000 - fields: - DATA2: - description: 2nd data item of a pair of regular conversions - bitOffset: 16 - bitWidth: 16 - DATA1: - description: 1st data item of a pair of regular conversions - bitOffset: 0 - bitWidth: 16 - - -_modify: - # Fix typo in the name of the LTDC peripheral - "LTCD": - name: "LTDC" - "Flash": - name: "FLASH" - -"GPIO*": - _modify: - # SVD calls call OSPEEDR regs GPIOB_OSPEEDR, so fix that. - GPIOB_OSPEEDR: - name: OSPEEDR - -FLASH: - OPTKEYR: - _modify: - OPTKEY: - name: OPTKEYR - -RCC: - AHB1ENR: - _add: - DTCMRAMEN: - description: DTCM data RAM clock enable - bitOffset: 20 - bitWidth: 1 - APB2ENR: - _add: - MDIOEN: - description: MDIO clock enable - bitOffset: 30 - bitWidth: 1 - PLLCFGR: - _add: - PLLR: - description: PLL division factor for DSI clock - bitOffset: 28 - bitWidth: 3 - access: read-write - -CRC: - # The SVD calls the RESET field "CR", and misses some fields, fix per RM0410 - CR: - _modify: - CR: - name: RESET - _add: - REV_OUT: - description: Reverse output data - bitOffset: 7 - bitWidth: 1 - access: read-write - REV_IN: - description: Reverse input data - bitOffset: 5 - bitWidth: 2 - access: read-write - POLYSIZE: - description: Polynomial size - bitOffset: 3 - bitWidth: 2 - access: read-write - -Ethernet_MAC: - MACFFR: - _modify: - # This field should be 2 bits wide but is only 1 bit in the SVD - PCF: - bitWidth: 2 - # All these fields are named incorrectly in the SVD compared to RM0090 - MACA1LR: - _modify: - MACA1LR: - name: MACA1L - MACA2HR: - _modify: - MAC2AH: - name: MACA2H - MACA2LR: - _modify: - MACA2L: - bitWidth: 32 - MACA3LR: - _modify: - MBCA3L: - name: MACA3L - -Ethernet_DMA: - DMABMR: - _modify: - # This field is named incorrectly in the SVD compared to the RM - RTPR: - name: PM - -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" - -_include: - - common_patches/rename_ltcd.yaml - - common_patches/f7_interrupts.yaml - - common_patches/f7_ltdc_interrupts.yaml - - common_patches/pllsai.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/rcc_add_plli2sp.yaml - - common_patches/f7_rcc_apbenr.yaml - - common_patches/f7_rcc_lsedrv.yaml - - common_patches/f7_rcc_rename_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr_sdmmc1.yaml - - common_patches/f7_rcc_dckcfgr_RM0410.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_f7.yaml - - ../peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllp.yaml - - ../peripherals/rcc/rcc_v2_sai_pllr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f7.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dsisel.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/adc/adc_v2_smpr.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v21.yaml - - ../peripherals/dma/dma_v21.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_f7.yaml - - ../peripherals/pwr/pwr_v2.yaml - - ../peripherals/flash/flash_v2_dual_bank.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/hash/hash.yaml - - common_patches/mdios/mdios.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/f7_dbgmcu.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/dma/dma2d_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml diff --git a/devices/stm32f7x9.yaml b/devices/stm32f7x9.yaml deleted file mode 100644 index 1748f5a4d..000000000 --- a/devices/stm32f7x9.yaml +++ /dev/null @@ -1,348 +0,0 @@ -_svd: ../svd/stm32f7x9.svd - -_rebase: - USART1: USART6 - -_add: - # This SVD is missing the ADC_Common peripheral that most other parts with - # this ADC contain; consequently it's missing the CSR and CCR and CDR regs - # from RM0410. - ADC_Common: - description: ADC common registers - groupName: ADC - baseAddress: 0x40012300 - addressBlock: - offset: 0x0 - size: 0x400 - usage: registers - registers: - CSR: - description: ADC common status register - addressOffset: 0x0 - access: read-only - resetValue: 0x00000000 - fields: - OVR3: - description: Overrun flag of ADC3 - bitOffset: 21 - bitWidth: 1 - STRT3: - description: Regular channel Start flag of ADC3 - bitOffset: 20 - bitWidth: 1 - JSTRT3: - description: Injected channel Start flag of ADC3 - bitOffset: 19 - bitWidth: 1 - JEOC3: - description: Injected channel end of conversion of ADC3 - bitOffset: 18 - bitWidth: 1 - EOC3: - description: End of conversion of ADC3 - bitOffset: 17 - bitWidth: 1 - AWD3: - description: Analog watchdog flag of ADC3 - bitOffset: 16 - bitWidth: 1 - - OVR2: - description: Overrun flag of ADC2 - bitOffset: 13 - bitWidth: 1 - STRT2: - description: Regular channel Start flag of ADC2 - bitOffset: 12 - bitWidth: 1 - JSTRT2: - description: Injected channel Start flag of ADC2 - bitOffset: 11 - bitWidth: 1 - JEOC2: - description: Injected channel end of conversion of ADC2 - bitOffset: 10 - bitWidth: 1 - EOC2: - description: End of conversion of ADC2 - bitOffset: 9 - bitWidth: 1 - AWD2: - description: Analog watchdog flag of ADC2 - bitOffset: 8 - bitWidth: 1 - - OVR1: - description: Overrun flag of ADC1 - bitOffset: 5 - bitWidth: 1 - STRT1: - description: Regular channel Start flag of ADC1 - bitOffset: 4 - bitWidth: 1 - JSTRT1: - description: Injected channel Start flag of ADC1 - bitOffset: 3 - bitWidth: 1 - JEOC1: - description: Injected channel end of conversion of ADC1 - bitOffset: 2 - bitWidth: 1 - EOC1: - description: End of conversion of ADC1 - bitOffset: 1 - bitWidth: 1 - AWD1: - description: Analog watchdog flag of ADC1 - bitOffset: 0 - bitWidth: 1 - - CCR: - description: ADC common control register - addressOffset: 0x04 - access: read-write - resetValue: 0x00000000 - fields: - TSVREFE: - description: Temperature sensor and V_REFINT enable - bitOffset: 23 - bitWidth: 1 - VBATE: - description: V_BAT enable - bitOffset: 22 - bitWidth: 1 - ADCPRE: - description: ADC prescaler - bitOffset: 16 - bitWidth: 2 - DMA: - description: Direct memory access mode for multi ADC mode - bitOffset: 14 - bitWidth: 2 - DDS: - description: DMA disable selection (for multi-ADC mode) - bitOffset: 13 - bitWidth: 1 - DELAY: - description: Delay between 2 sampling phases - bitOffset: 8 - bitWidth: 4 - MULTI: - description: Multi ADC mode selection - bitOffset: 0 - bitWidth: 4 - - CDR: - description: ADC common regular data register for dual and triple modes - addressOffset: 0x08 - access: read-only - resetValue: 0x00000000 - fields: - DATA2: - description: 2nd data item of a pair of regular conversions - bitOffset: 16 - bitWidth: 16 - DATA1: - description: 1st data item of a pair of regular conversions - bitOffset: 0 - bitWidth: 16 - - -_modify: - # Fix typo in the name of the LTDC peripheral - "LTCD": - name: "LTDC" - "Flash": - name: "FLASH" - -"GPIO*": - _modify: - # SVD calls call OSPEEDR regs GPIOB_OSPEEDR, so fix that. - GPIOB_OSPEEDR: - name: OSPEEDR - -FLASH: - OPTKEYR: - _modify: - OPTKEY: - name: OPTKEYR - -RCC: - PLLCFGR: - _add: - PLLR: - description: PLL division factor for DSI clock - bitOffset: 28 - bitWidth: 3 - access: read-write - -CRC: - # The SVD calls the RESET field "CR", and misses some fields, fix per RM0410 - CR: - _modify: - CR: - name: RESET - _add: - REV_OUT: - description: Reverse output data - bitOffset: 7 - bitWidth: 1 - access: read-write - REV_IN: - description: Reverse input data - bitOffset: 5 - bitWidth: 2 - access: read-write - POLYSIZE: - description: Polynomial size - bitOffset: 3 - bitWidth: 2 - access: read-write - -Ethernet_MAC: - MACFFR: - _modify: - # This field should be 2 bits wide but is only 1 bit in the SVD - PCF: - bitWidth: 2 - # All these fields are named incorrectly in the SVD compared to RM0090 - MACA1LR: - _modify: - MACA1LR: - name: MACA1L - MACA2HR: - _modify: - MAC2AH: - name: MACA2H - MACA2LR: - _modify: - MACA2L: - bitWidth: 32 - MACA3LR: - _modify: - MBCA3L: - name: MACA3L - -Ethernet_DMA: - DMABMR: - _modify: - # This field is named incorrectly in the SVD compared to the RM - RTPR: - name: PM - -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" - -LTDC: - _add: - _interrupts: - LCD_TFT_1: - description: LCD-TFT global error interrupt - value: 89 - -_include: - - common_patches/rename_ltcd.yaml - - common_patches/f7_interrupts.yaml - - common_patches/f7_lptim_interrupt.yaml - - common_patches/f7_ltdc_interrupts.yaml - - common_patches/pllsai.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/ethernet_mac_regs.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/cryp/cryp_v2.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/rcc_add_plli2sp.yaml - - common_patches/f7_rcc_apbenr.yaml - - common_patches/f7_rcc_lsedrv.yaml - - common_patches/f7_rcc_rename_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr.yaml - - common_patches/f7_rcc_dckcfgr_sdmmc1.yaml - - common_patches/f7_rcc_dckcfgr_RM0410.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/rcc/rcc_merge_sw_sws.yaml - - ../peripherals/rcc/rcc_f7.yaml - - ../peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml - - ../peripherals/rcc/rcc_v2_i2s_pllp.yaml - - ../peripherals/rcc/rcc_v2_sai_pllr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f7.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr_dsisel.yaml - - ../peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml - - ../peripherals/rcc/rcc_merge_rtcsel.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/spi/spi_v2.yaml - - ../peripherals/adc/adc_v2_multi.yaml - - common_patches/dma/dma_v21.yaml - - ../peripherals/dma/dma_v21.yaml - - ../peripherals/eth/eth_dma_common.yaml - - ../peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml - - ../peripherals/eth/eth_mac_common.yaml - - ../peripherals/eth/eth_mac_cstf.yaml - - ../peripherals/eth/eth_mmc_common.yaml - - ../peripherals/eth/eth_mmc_mcfhp_mcp.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_f7.yaml - - ../peripherals/pwr/pwr_v2.yaml - - ../peripherals/flash/flash_v2_dual_bank.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/hash/hash.yaml - - common_patches/mdios/mdios.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/f7_dbgmcu.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - common_patches/fsmc/fsmc_sd.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/fsmc/fsmc_sd.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/dma/dma2d_v1.yaml - - common_patches/rtc/rtc_cr.yaml - - ../peripherals/rtc/rtc_common.yaml diff --git a/devices/stm32g030.yaml b/devices/stm32g030.yaml index 2b45ed653..cd61b2876 100644 --- a/devices/stm32g030.yaml +++ b/devices/stm32g030.yaml @@ -1,9 +1,194 @@ _svd: ../svd/stm32g030.svd +_delete: + - TIM3 + _modify: name: STM32G030 + TIM2: + name: TIM3 + baseAddress: 0x40000400 + +_clear_fields: "*" + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELR_0: + name: CHSELR0 + CHSELR_1: + name: CHSELR1 + alternateRegister: CHSELR0 + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DBG: + APB_FZ1: + _delete: DBG_TIM2_STOP + +DMA1: + _strip: DMA_ + _include: + - patches/dma/g0_5ch.yaml + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_add_csr06.yaml + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/g0.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +PWR: {} + +RCC: + _include: + - patches/rcc/g0x0_delete.yaml + - patches/rcc/g0.yaml + - fields/rcc/rcc_g0.yaml + APBRSTR1: + _delete: + - TIM[67]RST + - USART[34]RST + APBRSTR2: + _delete: + - TIM15RST + APBENR1: + _delete: + - TIM[67]EN + - USART[34]EN + APBENR2: + _delete: + - TIM15EN + APBSMENR1: + _delete: + - TIM[67]SMEN + - USART[34]SMEN + APBSMENR2: + _delete: + - TIM15SMEN + CCIPR: + _delete: + - TIM15SEL + - USART3SEL + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/g0_rename_registers.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart2.yaml + _delete: + - ITLINE8 + - ITLINE17 + - ITLINE18 + - ITLINE20 + - ITLINE29 + ITLINE16: + _delete: TIM4 + ITLINE24: + _delete: I2C3 + ITLINE26: + _delete: SPI3 + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/g0_tim1_ts.yaml + - patches/tim/v2/g0_tim1_ccmr_input.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM3: + _delete: + _interrupts: TIM2 + _include: + - patches/tim/ts.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM14: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +USART1: + _include: + - patches/usart/g0.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml _include: - - ./common_patches/2_nvic_prio_bits.yaml - - ../peripherals/exti/exti_g0.yaml - - ./common_patches/g0_dma_5ch.yaml + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_5ch_only.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g031.yaml b/devices/stm32g031.yaml index d440a5334..c78780e89 100644 --- a/devices/stm32g031.yaml +++ b/devices/stm32g031.yaml @@ -3,7 +3,184 @@ _svd: ../svd/stm32g031.svd _modify: name: STM32G031 +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + baseAddress: 0x40000400 + +_delete: + # in v1.5 the ITLINE* registers were moved to SYSCFG + # but for this part they forgot to remove the old SYSCFG_ITLINE + - SYSCFG_ITLINE + +ADC: + _strip: ADC_ + SMPR: + _split: + - SMPSEL + CHSELR0: + _split: + - CHSEL + AWD2CR: + _split: + - AWD2CH + AWD3CR: + _split: + - AWD3CH + _include: + - patches/adc/g0.yaml + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DBG: {} + +DMA1: + _strip: DMA_ + _include: + - patches/dma/g0_5ch.yaml + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_add_csr06.yaml + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + _delete: + _interrupts: + # in v1.5 the PVD interrupt was moved to PWR + # but for this part they forgot to remove it from EXTI + - PVD + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/g0.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART: + _include: + - patches/usart/dedt0.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: {} + +RCC: + _include: + - patches/rcc/g0.yaml + - patches/rcc/g0_no_aes.yaml + - fields/rcc/rcc_g0.yaml + - fields/rcc/rcc_g0x1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/g0_rename_registers.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart2.yaml + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/g0_tim1_ts.yaml + - patches/tim/v2/g0_tim1_ccmr_input.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM14: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +USART1: + _include: + - patches/usart/g0.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/2_nvic_prio_bits.yaml - - ../peripherals/exti/exti_g0.yaml - - ./common_patches/g0_dma_5ch.yaml + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_5ch_only.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g041.yaml b/devices/stm32g041.yaml index 10de1d019..4274a429f 100644 --- a/devices/stm32g041.yaml +++ b/devices/stm32g041.yaml @@ -3,7 +3,189 @@ _svd: ../svd/stm32g041.svd _modify: name: STM32G041 +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + baseAddress: 0x40000400 + +_delete: + # in v1.5 the ITLINE* registers were moved to SYSCFG + # but for this part they forgot to remove the old SYSCFG_ITLINE + - SYSCFG_ITLINE + +ADC: + _strip: ADC_ + SMPR: + _split: + - SMPSEL + CHSELR0: + _split: + - CHSEL + AWD2CR: + _split: + - AWD2CH + AWD3CR: + _split: + - AWD3CH + _include: + - patches/adc/g0.yaml + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DBG: {} + +DMA1: + _strip: DMA_ + _include: + - patches/dma/g0_5ch.yaml + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_add_csr06.yaml + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + _delete: + _interrupts: + # in v1.5 the PVD interrupt was moved to PWR + # but for this part they forgot to remove it from EXTI + - PVD + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/g0.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART: + _include: + - patches/usart/dedt0.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: {} + +RCC: + _include: + - patches/rcc/g0.yaml + - fields/rcc/rcc_g0.yaml + - fields/rcc/rcc_g0x1.yaml + - fields/rcc/rcc_g0x1_aes.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/g0_rename_registers.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart2.yaml + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/g0_tim1_ts.yaml + - patches/tim/v2/g0_tim1_ccmr_input.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM14: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +USART1: + _include: + - patches/usart/g0.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/2_nvic_prio_bits.yaml - - ../peripherals/exti/exti_g0.yaml - - ./common_patches/g0_dma_5ch.yaml + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_5ch_only.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g050.yaml b/devices/stm32g050.yaml new file mode 100644 index 000000000..600b6d9bc --- /dev/null +++ b/devices/stm32g050.yaml @@ -0,0 +1,190 @@ +_svd: ../svd/stm32g050.svd + +_modify: + name: STM32G050 + +_clear_fields: "*" + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELR_0: + name: CHSELR0 + CHSELR_1: + name: CHSELR1 + alternateRegister: CHSELR0 + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DBG: + _strip: DBG_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _delete: + _interrupts: + # in v1.5 this was moved to DMA1 + # but for this part they forgot to remove it from DMAMUX + - DMA1_Channel4_5_6_7_DMAMUX_DMA2_Channel1_2_3_4_5 + CFR: + _modify: + CSOF*: + access: write-only + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +RCC: + _include: + - patches/rcc/g0x0_delete.yaml + - patches/rcc/g0.yaml + - fields/rcc/rcc_g0.yaml + APBRSTR1: + _delete: + - USART[34]RST + APBENR1: + _delete: + - USART[34]EN + APBSMENR1: + _delete: + - USART[34]SMEN + CCIPR: + _delete: + - USART3SEL + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart2.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + CNT: + _modify: + CNT_L: + name: CNT + description: Counter value + _delete: "CNT_H,CNTH" + ARR: + _modify: + ARR: + bitWidth: 16 + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM14: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +USART1: + _include: + - patches/usart/g0_CR1.yaml + - fields/usart/v4/B.yaml + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_7ch_only.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g051.yaml b/devices/stm32g051.yaml new file mode 100644 index 000000000..f04850566 --- /dev/null +++ b/devices/stm32g051.yaml @@ -0,0 +1,206 @@ +_svd: ../svd/stm32g051.svd + +_modify: + name: STM32G051 + +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + baseAddress: 0x40000400 + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +COMP: {} + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/g0.yaml + - collect/dac/v3.yaml + +DBG: + _strip: DBG_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +HDMI_CEC: + _strip: CEC_ + +LPTIM1: + _strip: LPTIM_ + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: {} + +RCC: + _include: + - patches/rcc/g0.yaml + - patches/rcc/g0_no_aes.yaml + - fields/rcc/rcc_g0.yaml + - fields/rcc/rcc_g0x1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart2.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + _interrupts: + TIM1_BRK_UP_TRG_COM: + description: TIM1 break, update, trigger and commutation interrupts + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim2_cnt_32bit.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim_cnt_16bit_l.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM14: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +USART1: + _include: + - patches/usart/g0_CR1.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_7ch_only.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g061.yaml b/devices/stm32g061.yaml new file mode 100644 index 000000000..529cf3de2 --- /dev/null +++ b/devices/stm32g061.yaml @@ -0,0 +1,217 @@ +_svd: ../svd/stm32g061.svd + +_modify: + name: STM32G061 + +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + baseAddress: 0x40000400 + SPI1: + from: ../svd/stm32g051.svd:SPI1 + SPI2: + from: ../svd/stm32g051.svd:SPI2 + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +AES: + _strip: AES_ + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/g0.yaml + - collect/dac/v3.yaml + +DBG: + _strip: DBG_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +HDMI_CEC: + _strip: CEC_ + +LPTIM1: + _strip: LPTIM_ + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: {} + +RCC: + _include: + - patches/rcc/g0.yaml + - fields/rcc/rcc_g0.yaml + - fields/rcc/rcc_g0x1.yaml + - fields/rcc/rcc_g0x1_aes.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart2.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + _interrupts: + TIM1_BRK_UP_TRG_COM: + description: TIM1 break, update, trigger and commutation interrupts + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim2_cnt_32bit.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim_cnt_16bit_l.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM14: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +USART1: + _include: + - patches/usart/g0_CR1.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_7ch_only.yaml + # SPI* are missing upstream + - patches/tim/group.yaml diff --git a/devices/stm32g070.yaml b/devices/stm32g070.yaml index 4d75eaa37..468793abd 100644 --- a/devices/stm32g070.yaml +++ b/devices/stm32g070.yaml @@ -1,8 +1,18 @@ _svd: ../svd/stm32g070.svd +_clear_fields: "*" + _modify: name: STM32G070 + # Remove TIM3 and rename TIM2 to TIM3. Because TIM3 was derive from TIM2 + TIM2: + name: TIM3 + baseAddress: "0x40000400" + + SYSCFG_VREFBUF: + name: SYSCFG + _delete: - TIM3 - LPTIM1 @@ -12,99 +22,146 @@ _delete: - LPUART - UCPD1 - UCPD2 - - SYSCFG_VREFBUF - - RNG - HDMI_CEC -# deleted so we can re-add them without interrupts - - TIM7 - - USART3 -# Remove TIM3 (above) and rename TIM2 to TIM3. Because TIM3 was derive from TIM2 -_modify: - TIM2: - name: TIM3 - baseAddress: "0x40000400" -# After changing the name, remove TIM2 interrupt from TIM3 block (it already has the TIM3 interrupt) -TIM3: - _delete: - _interrupts: - - TIM2 +_derive: + TIM7: TIM6 + USART3: USART1 -RCC: - AHBRSTR: - _delete: - - AESRST - - RNGRST - APBRSTR1: - _delete: - - TIM2RST - - LPUART1RST - - CECRST - - UCPD1RST - - UCPD2RST - - DAC1RST - - LPTIM2RST - - LPTIM1RST - AHBENR: - _delete: - - AESEN - - RNGEN - APBENR1: - _delete: - - TIM2EN - - LPUART1EN - - CECEN - - UCPD1EN - - UCPD2EN - - DAC1EN - - LPTIM2EN - - LPTIM1EN - AHBSMENR: - _delete: - - AESSMEN - - RNGSMEN - APBSMENR1: - _delete: - - TIM2SMEN - - LPUART1SMEN - - CECSMEN - - UCPD1SMEN - - UCPD2SMEN - - DAC1SMEN - - LPTIM2SMEN - - LPTIM1SMEN - CCIPR: - _delete: - - CECSEL - - LPUART1SEL - - LPTIM2SEL - - RNGSEL - - RNGDIV - - LPTIM1SEL +ADC: + _strip: ADC_ + _modify: + _interrupts: + ADC_COMP: + name: ADC + description: ADC Interrupt + CHSELR_0: + name: CHSELR0 + CHSELR_1: + name: CHSELR1 + alternateRegister: CHSELR0 + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DBG: {} + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml _delete: - VERR - IPIDR - SIDR -# Fix interrupts, see RM454 Rev3 11.3 Table 42 +FLASH: + _include: + - patches/flash/g0.yaml -ADC: +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/g0.yaml + - fields/i2c/v2.yaml + +IWDG: _modify: - _interrupts: - ADC_COMP: - name: ADC - description: ADC Interrupt + "KR,PR,RLR,SR,WINR": + size: 16 + _include: fields/iwdg/iwdg_with_WINR.yaml + +PWR: {} + +RCC: + _include: + - patches/rcc/g0x0_delete.yaml + - patches/rcc/g0.yaml + - fields/rcc/rcc_g0.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/spi/dr8.yaml + - patches/spi/g0_rename_registers.yaml + - fields/spi/spi_v2.yaml + _modify: + "CR1,CR2,SR,DR,CRCPR,RXCRCR,TXCRCR,I2SCFGR,I2SPR": + size: 16 + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart4.yaml + _delete: + - VREFBUF_CSR + - VREFBUF_CCR + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml TIM1: + _include: + - patches/tim/g0_tim1_ts.yaml + - patches/tim/v2/g0_tim1_ccmr_input.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml _modify: _interrupts: TIM1_BRK_UP_TRG_COMP: name: TIM1_BRK_UP_TRG_COM - description: IM1 break, update, trigger and commutation interrupts + description: TIM1 break, update, trigger and commutation interrupts + +# After changing the name, remove TIM2 interrupt from TIM3 block (it already has the TIM3 interrupt) +TIM3: + _delete: + _interrupts: + - TIM2 + _include: + - patches/tim/ts.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml TIM6: + _include: + - fields/tim/v2/tim6.yaml _modify: _interrupts: TIM6_DAC_LPTIM1: @@ -116,30 +173,55 @@ TIM6: description: TIM7 global interrupt value: 18 +TIM7: + _delete: + _interrupts: "*" + +TIM14: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + USART1: _add: _interrupts: USART3_USART4: description: USART3 + USART4 interrupt value: 29 + _include: + - patches/usart/g0.yaml + - fields/usart/v4/B.yaml -# Remove interrupts from derived Peripherals (after we renamed and moved them to the base peripherals) -# Since it is not possible to modify a derivedFrom peripheral, we delete it first -# and then add it again without the interrupts. -_add: - TIM7: - derivedFrom: TIM6 - baseAddress: "0x40001400" - USART3: - derivedFrom: USART1 - baseAddress: "0x40004800" - - +USART3: + _delete: + _interrupts: "*" +WWDG: + _modify: + "CR,CFR,SR": + size: 16 + _include: fields/wwdg/wwdg_v2.yaml _include: - - ./common_patches/2_nvic_prio_bits.yaml - - ../peripherals/exti/exti_g0.yaml - - ./common_patches/g0_adc_typo.yaml - - ./common_patches/g0_dma_7ch.yaml - + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_7ch_only.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g071.yaml b/devices/stm32g071.yaml index 18c969d74..fa47c7d88 100644 --- a/devices/stm32g071.yaml +++ b/devices/stm32g071.yaml @@ -2,11 +2,112 @@ _svd: ../svd/stm32g071.svd _modify: name: STM32G071 + COMP: + groupName: COMP -_delete: - - RNG +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + baseAddress: 0x40000400 + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/g0.yaml + - collect/dac/v3.yaml + +DBG: {} + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + _delete: + - VERR + - IPIDR + - SIDR + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/g0.yaml + - fields/i2c/v2.yaml + +IWDG: + _modify: + "KR,PR,RLR,SR,WINR": + size: 16 + _include: fields/iwdg/iwdg_with_WINR.yaml + +HDMI_CEC: + _strip: CEC_ + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART: + _include: + - patches/usart/dedt0.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: {} RCC: + _include: + - patches/rcc/g0.yaml + - patches/rcc/g0_no_aes.yaml + - fields/rcc/rcc_g0.yaml + - fields/rcc/rcc_g0x1.yaml + - fields/rcc/rcc_g0x1_cec.yaml AHBRSTR: _delete: - AESRST @@ -19,26 +120,107 @@ RCC: _delete: - AESSMEN - RNGSMEN - CCIPR: - _delete: - - RNGSEL - - RNGDIV -EXTI: - _delete: - - VERR - - IPIDR - - SIDR +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/spi/dr8.yaml + - patches/spi/g0_rename_registers.yaml + - fields/spi/spi_v2.yaml + _modify: + "CR1,CR2,SR,DR,CRCPR,RXCRCR,TXCRCR,I2SCFGR,I2SPR": + size: 16 + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart4.yaml + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml TIM1: + _include: + - patches/tim/g0_tim1_ts.yaml + - patches/tim/v2/g0_tim1_ccmr_input.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml _modify: _interrupts: TIM1_BRK_UP_TRG_COMP: name: TIM1_BRK_UP_TRG_COM - description: IM1 break, update, trigger and commutation interrupts + description: TIM1 break, update, trigger and commutation interrupts + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM14: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v2.yaml + +USART1: + _include: + - patches/usart/g0.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _modify: + "CR,CFR,SR": + size: 16 + _include: fields/wwdg/wwdg_v2.yaml _include: - - ./common_patches/2_nvic_prio_bits.yaml - - ../peripherals/exti/exti_g0.yaml - - ./common_patches/g0_adc_typo.yaml - - ./common_patches/g0_dma_7ch.yaml + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_7ch_only.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g081.yaml b/devices/stm32g081.yaml index 98601874a..d694fc786 100644 --- a/devices/stm32g081.yaml +++ b/devices/stm32g081.yaml @@ -2,16 +2,218 @@ _svd: ../svd/stm32g081.svd _modify: name: STM32G081 + COMP: + groupName: COMP + +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + baseAddress: 0x40000400 + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/g0.yaml + - collect/dac/v3.yaml + +DBG: {} + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/i2c/g0.yaml + - fields/i2c/v2.yaml + +IWDG: + _modify: + "KR,PR,RLR,SR,WINR": + size: 16 + _include: fields/iwdg/iwdg_with_WINR.yaml + +HDMI_CEC: + _strip: CEC_ + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART: + _include: + - patches/usart/dedt0.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: {} + +RCC: + _include: + - patches/rcc/g0.yaml + - fields/rcc/rcc_g0.yaml + - fields/rcc/rcc_g0x1.yaml + - fields/rcc/rcc_g0x1_aes.yaml + - fields/rcc/rcc_g0x1_cec.yaml + +RNG: {} + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/spi/dr8.yaml + - patches/spi/g0_rename_registers.yaml + - fields/spi/spi_v2.yaml + _modify: + "CR1,CR2,SR,DR,CRCPR,RXCRCR,TXCRCR,I2SCFGR,I2SPR": + size: 16 + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart4.yaml + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml TIM1: + _include: + - patches/tim/g0_tim1_ts.yaml + - patches/tim/v2/g0_tim1_ccmr_input.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml _modify: _interrupts: TIM1_BRK_UP_TRG_COMP: name: TIM1_BRK_UP_TRG_COM - description: IM1 break, update, trigger and commutation interrupts + description: TIM1 break, update, trigger and commutation interrupts + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM14: + _include: + - patches/tim/icpsc.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v2.yaml + +USART1: + _include: + - patches/usart/g0.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _modify: + "CR,CFR,SR": + size: 16 + _include: fields/wwdg/wwdg_v2.yaml _include: - - ./common_patches/2_nvic_prio_bits.yaml - - ../peripherals/exti/exti_g0.yaml - - ./common_patches/g0_adc_typo.yaml - - ./common_patches/g0_dma_7ch.yaml + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma1_7ch_only.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g0b0.yaml b/devices/stm32g0b0.yaml new file mode 100644 index 000000000..c2da11681 --- /dev/null +++ b/devices/stm32g0b0.yaml @@ -0,0 +1,189 @@ +_svd: ../svd/stm32g0b0.svd + +_modify: + name: STM32G0B0 + +_clear_fields: "*" + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELR_0: + name: CHSELR0 + CHSELR_1: + name: CHSELR1 + alternateRegister: CHSELR0 + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DBG: + _strip: DBG_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMA2: + _strip: DMA_ + _include: + - patches/dma/g0_5ch.yaml + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +RCC: + _modify: + PLLSYSCFGR: + name: PLLCFGR + _include: + - patches/rcc/g0b.yaml + - fields/rcc/rcc_g0b.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart4.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + _interrupts: + TIM1_BRK_UP_TRG_COM: + description: TIM1 break, update, trigger and commutation interrupts + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim_cnt_16bit_l.yaml + - patches/tim/tim_ccrx_16bit.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM14: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +USART1: + _include: + - patches/usart/g0_CR1.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + CNTR: + _modify: + L1RES: + name: L1RESUME + L2RES: + name: L2RESUME + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma2_5ch.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g0b1.yaml b/devices/stm32g0b1.yaml new file mode 100644 index 000000000..6dac1e4c0 --- /dev/null +++ b/devices/stm32g0b1.yaml @@ -0,0 +1,230 @@ +_svd: ../svd/stm32g0b1.svd + +_modify: + name: STM32G0B1 + +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + baseAddress: 0x40000400 + +_derive: + TIM4: TIM3 + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELR: + name: CHSELR0 + CHSELR_1: + name: CHSELR1 + alternateRegister: CHSELR0 + +COMP: {} + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/g0.yaml + - collect/dac/v3.yaml + +DBG: + _strip: DBG_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMA2: + _strip: DMA_ + _include: + - patches/dma/g0_5ch.yaml + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +HDMI_CEC: + _strip: CEC_ + +LPTIM1: + _strip: LPTIM_ + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: {} + +RCC: + _include: + - patches/rcc/g0b.yaml + - fields/rcc/rcc_g0b1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart4.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + _interrupts: + TIM1_BRK_UP_TRG_COM: + description: TIM1 break, update, trigger and commutation interrupts + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim2_cnt_32bit.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim_cnt_16bit_l.yaml + - patches/tim/tim_ccrx_16bit.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM14: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v2.yaml + +USART1: + _include: + - patches/usart/g0_CR1.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma2_5ch.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g0c1.yaml b/devices/stm32g0c1.yaml new file mode 100644 index 000000000..18ce9f939 --- /dev/null +++ b/devices/stm32g0c1.yaml @@ -0,0 +1,243 @@ +_svd: ../svd/stm32g0c1.svd + +_modify: + name: STM32G0C1 + +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + baseAddress: 0x40000400 + +ADC: + _strip: ADC_ + _include: + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + CHSELR: + name: CHSELR0 + CHSELR_1: + name: CHSELR1 + alternateRegister: CHSELR0 + +AES: + _strip: AES_ + _include: + - fields/aes/v2.yaml + +COMP: {} + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/g0.yaml + - collect/dac/v3.yaml + +DBG: + _strip: DBG_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMA2: + _strip: DMA_ + _include: + - patches/dma/g0_5ch.yaml + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + - fields/exti/exti_g0.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _include: + - patches/flash/g0.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +HDMI_CEC: + _strip: CEC_ + +LPTIM1: + _strip: LPTIM_ + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: {} + +RCC: + CCIPR2: + _modify: + USBSEL: + # mistakenly set to 1 upstream + bitWidth: 2 + _include: + - patches/rcc/g0b.yaml + - fields/rcc/rcc_g0b1.yaml + - fields/rcc/rcc_g0x1_aes.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: fields/syscfg/syscfg_g0_usart4.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + _modify: + _interrupts: + TIM1_BRK_UP_TRG_COM: + description: TIM1 break, update, trigger and commutation interrupts + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim2_cnt_32bit.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/tim_cnt_16bit_l.yaml + - patches/tim/tim_ccrx_16bit.yaml + - patches/tim/v2/oc1m1.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM14: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v2.yaml + +USART1: + _include: + - patches/usart/g0_CR1.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/nvic/2_prio_bits.yaml + - patches/dma/g0_dma2_5ch.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g431.yaml b/devices/stm32g431.yaml index 52ff9609e..a01b0625b 100644 --- a/devices/stm32g431.yaml +++ b/devices/stm32g431.yaml @@ -1,11 +1,240 @@ _svd: ../svd/stm32g431.svd +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + TIM4: TIM3 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FMAC: {} + +FLASH: + _include: + - fields/flash/flash_g4.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: {} + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/g4_rcc.yaml - - ./common_patches/g4_exti.yaml - - ./common_patches/g4_adc_common.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/adc/adc_v3_g4.yaml - - ../peripherals/adc/adc_v3_common_g4.yaml - - ./common_patches/g4_comp.yaml - - ./common_patches/g4_adc.yaml + - patches/comp/g4.yaml + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g441.yaml b/devices/stm32g441.yaml index 31e676b98..5fe8cdc97 100644 --- a/devices/stm32g441.yaml +++ b/devices/stm32g441.yaml @@ -1,12 +1,238 @@ _svd: ../svd/stm32g441.svd +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + TIM4: TIM3 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FLASH: + _include: + - fields/flash/flash_g4.yaml + +FMAC: {} + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/g4_rcc.yaml - - ./common_patches/g4_exti.yaml - - ./common_patches/g4_adc_common.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/adc/adc_v3_g4.yaml - - ../peripherals/adc/adc_v3_common_g4.yaml - - ./common_patches/g4_comp.yaml - - ./common_patches/g4_adc.yaml - \ No newline at end of file + - patches/comp/g4.yaml + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g471.yaml b/devices/stm32g471.yaml index bf75b867f..434b6f66a 100644 --- a/devices/stm32g471.yaml +++ b/devices/stm32g471.yaml @@ -1,12 +1,255 @@ _svd: ../svd/stm32g471.svd +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + ADC3: ADC1 + TIM4: TIM3 + SPI4: SPI1 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FLASH: + _include: + - patches/flash/g4_dual_bank.yaml + - patches/flash/g4_dual_bank_optr.yaml + - fields/flash/flash_g4.yaml + - fields/flash/flash_g4_dual_bank.yaml + +FMAC: {} + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: + _copy: + OPAMP6_CSR: + _from: OPAMP1_CSR + addressOffset: 0x14 + description: OPAMP6 control/status register + OPAMP6_TCMR: + _from: OPAMP1_TCMR + addressOffset: 0x2C + description: OPAMP6 control/status register + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/g4_rcc.yaml - - ./common_patches/g4_exti.yaml - - ./common_patches/g4_adc_common.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/adc/adc_v3_g4.yaml - - ../peripherals/adc/adc_v3_common_g4.yaml - - ./common_patches/g4_comp.yaml - - ./common_patches/g4_adc.yaml - \ No newline at end of file + - patches/comp/g4.yaml + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - fields/opamp/opamp_g4_opamp6.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g473.yaml b/devices/stm32g473.yaml index 06c238249..47ec8a651 100644 --- a/devices/stm32g473.yaml +++ b/devices/stm32g473.yaml @@ -1,12 +1,271 @@ _svd: ../svd/stm32g473.svd +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + ADC3: ADC1 + TIM4: TIM3 + SPI4: SPI1 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FDCAN1: {} + +FLASH: + _include: + - patches/flash/g4_dual_bank.yaml + - fields/flash/flash_g4.yaml + - fields/flash/flash_g4_dual_bank.yaml + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: {} + +PWR: + _strip: PWR_ + +QUADSPI: + CCR: + _add: + DHHC: + description: DDR hold + bitOffset: 30 + bitWidth: 1 + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/g4_rcc.yaml - - ./common_patches/g4_exti.yaml - - ./common_patches/g4_adc_common.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/adc/adc_v3_g4.yaml - - ../peripherals/adc/adc_v3_common_g4.yaml - - ./common_patches/g4_comp.yaml - - ./common_patches/g4_adc.yaml - \ No newline at end of file + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - fields/opamp/opamp_g4_opamp4_5.yaml + - fields/opamp/opamp_g4_opamp6.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g474.yaml b/devices/stm32g474.yaml index d60665c19..d05a39778 100644 --- a/devices/stm32g474.yaml +++ b/devices/stm32g474.yaml @@ -1,12 +1,267 @@ _svd: ../svd/stm32g474.svd +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + ADC3: ADC1 + TIM4: TIM3 + SPI4: SPI1 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FLASH: + _include: + - patches/flash/g4_dual_bank.yaml + - patches/flash/g4_dual_bank_optr.yaml + - fields/flash/flash_g4.yaml + - fields/flash/flash_g4_dual_bank.yaml + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: {} + +PWR: + _strip: PWR_ + +QUADSPI: + CCR: + _add: + DHHC: + description: DDR hold + bitOffset: 30 + bitWidth: 1 + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/g4_rcc.yaml - - ./common_patches/g4_exti.yaml - - ./common_patches/g4_adc_common.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/adc/adc_v3_g4.yaml - - ../peripherals/adc/adc_v3_common_g4.yaml - - ./common_patches/g4_comp.yaml - - ./common_patches/g4_adc.yaml - \ No newline at end of file + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - fields/opamp/opamp_g4_opamp4_5.yaml + - fields/opamp/opamp_g4_opamp6.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/hrtim/v2.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_v2.yaml + - collect/hrtim/v2.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g483.yaml b/devices/stm32g483.yaml index b7261c63c..db575faf7 100644 --- a/devices/stm32g483.yaml +++ b/devices/stm32g483.yaml @@ -1,12 +1,270 @@ _svd: ../svd/stm32g483.svd +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + ADC3: ADC1 + TIM4: TIM3 + SPI4: SPI1 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FLASH: + _include: + - patches/flash/g4_dual_bank.yaml + - patches/flash/g4_dual_bank_optr.yaml + - fields/flash/flash_g4.yaml + - fields/flash/flash_g4_dual_bank.yaml + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: {} + +PWR: + _strip: PWR_ + +QUADSPI: + CCR: + _add: + DHHC: + description: DDR hold + bitOffset: 30 + bitWidth: 1 + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/g4_rcc.yaml - - ./common_patches/g4_exti.yaml - - ./common_patches/g4_adc_common.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/adc/adc_v3_g4.yaml - - ../peripherals/adc/adc_v3_common_g4.yaml - - ./common_patches/g4_comp.yaml - - ./common_patches/g4_adc.yaml - \ No newline at end of file + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - fields/opamp/opamp_g4_opamp4_5.yaml + - fields/opamp/opamp_g4_opamp6.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g484.yaml b/devices/stm32g484.yaml index b5f56a647..1f154b52e 100644 --- a/devices/stm32g484.yaml +++ b/devices/stm32g484.yaml @@ -1,12 +1,274 @@ _svd: ../svd/stm32g484.svd +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + ADC3: ADC1 + TIM4: TIM3 + SPI4: SPI1 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FLASH: + _include: + - patches/flash/g4_dual_bank.yaml + - patches/flash/g4_dual_bank_optr.yaml + - fields/flash/flash_g4.yaml + - fields/flash/flash_g4_dual_bank.yaml + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: {} + +PWR: + _strip: PWR_ + +QUADSPI: + CCR: + _add: + DHHC: + description: DDR hold + bitOffset: 30 + bitWidth: 1 + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - ./common_patches/g4_rcc.yaml - - ./common_patches/g4_exti.yaml - - ./common_patches/g4_adc_common.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/adc/adc_v3_g4.yaml - - ../peripherals/adc/adc_v3_common_g4.yaml - - ./common_patches/g4_comp.yaml - - ./common_patches/g4_adc.yaml - \ No newline at end of file + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - fields/opamp/opamp_g4_opamp4_5.yaml + - fields/opamp/opamp_g4_opamp6.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/hrtim/v2.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_v2.yaml + - collect/hrtim/v2.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g491.yaml b/devices/stm32g491.yaml new file mode 100644 index 000000000..cd20f682f --- /dev/null +++ b/devices/stm32g491.yaml @@ -0,0 +1,262 @@ +_svd: ../svd/stm32g491.svd + +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + ADC3: ADC1 + TIM4: TIM3 + FDCAN2: + _from: FDCAN + baseAddress: 0x40006800 + TIM20: + _from: TIM1 + baseAddress: 0x40015000 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FDCAN2: + _add: + _interrupts: + FDCAN2_intr0: + description: FDCAN2_intr0 + value: 86 + FDCAN2_intr1: + description: FDCAN2_intr1 + value: 87 + +FLASH: + _include: + - fields/flash/flash_g4.yaml + +FMAC: {} + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: + _copy: + OPAMP6_CSR: + _from: OPAMP1_CSR + addressOffset: 0x14 + description: OPAMP6 control/status register + OPAMP6_TCMR: + _from: OPAMP1_TCMR + addressOffset: 0x2C + description: OPAMP6 control/status register + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/comp/g4.yaml + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - fields/opamp/opamp_g4_opamp6.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32g4a1.yaml b/devices/stm32g4a1.yaml new file mode 100644 index 000000000..f3205c13b --- /dev/null +++ b/devices/stm32g4a1.yaml @@ -0,0 +1,265 @@ +_svd: ../svd/stm32g4a1.svd + +_clear_fields: "*" + +_copy: + TIM3: + from: TIM2 + +_derive: + ADC3: ADC1 + TIM4: TIM3 + FDCAN2: + _from: FDCAN + baseAddress: 0x40006800 + TIM20: + _from: TIM1 + baseAddress: 0x40015000 + +ADC1: + _include: + - patches/adc/g4.yaml + - fields/adc/adc_v3_g4.yaml + - fields/adc/adc_v3.yaml + - collect/adc/v3.yaml + SQR*: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC12_Common: + _include: fields/adc/adc_v3_common_g4.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: + _strip: COMP_ + +CORDIC: + _include: + - patches/cordic/g4.yaml + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/g4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - patches/exti/g4.yaml + - fields/exti/common.yaml + +FDCAN: + _strip: FDCAN_ + +FDCAN2: + _add: + _interrupts: + FDCAN2_intr0: + description: FDCAN2_intr0 + value: 86 + FDCAN2_intr1: + description: FDCAN2_intr1 + value: 87 + +FLASH: + _include: + - fields/flash/flash_g4.yaml + +FMAC: {} + +GPIO[ABC]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIMER1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: + _copy: + OPAMP6_CSR: + _from: OPAMP1_CSR + addressOffset: 0x14 + description: OPAMP6 control/status register + OPAMP6_TCMR: + _from: OPAMP1_TCMR + addressOffset: 0x2C + description: OPAMP6 control/status register + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + _include: + - fields/rcc/g4.yaml + - fields/rcc/rcc_g4.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2_without_UDR_CHSIDE.yaml + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_32bit.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/v2/tim_20bit.yaml + - fields/tim/v3/tim16.yaml + - collect/tim/ccr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +"UART4,USART1": + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/comp/g4.yaml + - collect/comp/csr.yaml + - fields/opamp/opamp_g4_common.yaml + - fields/opamp/opamp_g4_opamp6.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32h503.yaml b/devices/stm32h503.yaml new file mode 100644 index 000000000..3ee0e1936 --- /dev/null +++ b/devices/stm32h503.yaml @@ -0,0 +1,248 @@ +_svd: ../svd/stm32h503.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + +_modify: + ADC: + name: ADC1 + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_19.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +COMP: {} + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/v6.yaml + - collect/dac/v3.yaml + MCR: + _merge: HFSEL? + CR: + TSEL?: + Software: [0, Software trigger] + Tim1Trgo: [1, Timer 1 TRGO event] + Tim2Trgo: [2, Timer 2 TRGO event] + Tim3Trgo: [3, Timer 4 TRGO event] + Tim6Trgo: [5, Timer 6 TRGO event] + Tim7Trgo: [6, Timer 7 TRGO event] + Tim8Trgo: [7, Timer 8 TRGO event] + Lptim1Ch1: [11, LPTIM1 CH1 event] + Lptim2Ch1: [12, LPTIM2 CH1 event] + Exti9: [13, EXTI line 9] + +DBGMCU: + _strip: DBGMCU_ + +DTS: + _strip: DTS_ + +EXTI: + _strip: EXTI_ + _include: + - patches/exti/exti4_5.yaml + - fields/exti/common.yaml + - fields/exti/exti_priv.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +GPDMA1: + _strip: GPDMA_ + _include: + - fields/dma/gpdma/h5.yaml + - collect/dma/gpdma/h5.yaml + +GPIOC: + _strip: GPIO_ + +GPIO[ABCH]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCH]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1: + _strip: GTZC1_ + _array: + MPCBB1_PRIVCFGR*: + description: SRAM1 MPCBB privileged configuration for super-block %s register + _array: + PRIV*: {} + MPCBB2_PRIVCFGR*: + description: SRAM2 MPCBB privileged configuration for super-block %s register + _array: + PRIV*: {} + +HASH: + _strip: HASH_ + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +I3C1: + _strip: I3C_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + _include: + - patches/iwdg/add_onf.yaml + - patches/16bit_with_mask.yaml + - fields/iwdg/h5.yaml + +LPTIM1: + _strip: LPTIM_ + +LPUART: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP1: {} + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_h5.yaml + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + _include: + - patches/rcc/h503.yaml + - fields/rcc/v3/h503.yaml + +RNG: + _strip: RNG_ + _include: + - patches/rng/h503.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SBS: + _strip: SBS_ + _include: + - patches/sbs/fmplus.yaml + - patches/sbs/sbs.yaml + - fields/sbs/sbs.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + - fields/spi/spi_v3_i2s.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM1: + _include: + - patches/tim/ccmr3.yaml + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/tim1_advanced.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/tim_uifremap.yaml + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32h523.yaml b/devices/stm32h523.yaml new file mode 100644 index 000000000..d007d0e00 --- /dev/null +++ b/devices/stm32h523.yaml @@ -0,0 +1,356 @@ +_svd: ../svd/stm32h523.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + LPTIM2: LPTIM1 + +_modify: + size: 0x20 + GPIO?: + groupName: GPIO + GTZC*: + groupName: GTZC + LPTIM?: + groupName: LPTIM + TIM?*: + groupName: TIM + ADC: + name: ADC1 + ADC_S: + name: ADC1_S + FDCAN: + name: FDCAN1 + FDCAN_S: + name: FDCAN1_S + GPDMA: + name: GPDMA1 + GPDMA_S: + name: GPDMA1_S + I2C: + name: I2C1 + I2C_S: + name: I2C1_S + I3C: + name: I3C1 + I3C_S: + name: I3C1_S + SDMMC: + name: SDMMC1 + SDMMC_S: + name: SDMMC1_S + SPI: + name: SPI1 + SPI_S: + name: SPI1_S + UCPD: + name: UCPD1 + UCPD_S: + name: UCPD1_S + USART: + name: USART1 + USART_S: + name: USART1_S + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_19.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADCC: + _strip: ADC_ + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/h5.yaml + - collect/dac/v3.yaml + +DBGMCU: + _strip: DBGMCU_ + +DCACHE: + _strip: DCACHE_ + +DCMI: + _strip: DCMI_ + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DTS: + _strip: DTS_ + +EXTI: + _strip: EXTI_ + _include: + - patches/exti/exti4_5.yaml + - fields/exti/common.yaml + - fields/exti/exti_priv.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + # - collect/flash/secbbr.yaml + +FMC: + _strip: FMC_ + PCR: + _merge: TAR* + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - fields/dma/gpdma/h5.yaml + - collect/dma/gpdma/h5.yaml + +GPIO[ABCDEFGHI]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCDEFGHI]: + _include: collect/gpio/v2r_derive.yaml + +#GTZC1_MPCBB?: # Seems to be completely missing from svd +# _strip: GTZC1_MPCBB?_ +# _include: +# - collect/gtzc/h5_u5.yaml + +GTZC1_TZIC: + _strip: GTZC1_TZIC_ + +GTZC1_TZSC: + _strip: GTZC1_TZSC_ + +HASH: + _strip: HASH_ + +I2C?: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +I3C1: + _strip: I3C_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/iwdg/h5.yaml + +LPTIM[12]: + _strip: + - LPTIM_ + - LPTIM?_ + +LPUART: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OCTOSPI: + _strip: OCTOSPI_ + _include: + - fields/octospi/u5.yaml + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_h5.yaml + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + _include: + - patches/rcc/h523_h533.yaml + - fields/rcc/v3/h56x_h57x.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SBS: + _strip: SBS_ + _include: + - patches/sbs/sbs.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - collect/sdio/respr.yaml + - collect/sdio/fifo.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + - fields/spi/spi_v3_i2s.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM1?: + _strip: TIM1?_ + +TIM[18]: + _include: + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM[25]: + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/tim_uifremap.yaml + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + CNT: + _modify: + CNT: + bitOffset: 0 + bitWidth: 32 + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM[34]: + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _include: collect/tim/tim4_derive.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim9.yaml + - collect/tim/ccr.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + #- fields/ucpd/ucpd_v1.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +USBSRAM: + _strip: USBSRAM_CHEP_ + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32h533.yaml b/devices/stm32h533.yaml new file mode 100644 index 000000000..9d056edd2 --- /dev/null +++ b/devices/stm32h533.yaml @@ -0,0 +1,383 @@ +_svd: ../svd/stm32h533.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + LPTIM2: LPTIM1 + +_modify: + size: 0x20 + GPIO?: + groupName: GPIO + GTZC*: + groupName: GTZC + LPTIM?: + groupName: LPTIM + TIM?*: + groupName: TIM + OTFDEC: + name: OTFDEC1 + OTFDEC_S: + name: OTFDEC1_S + ADC: + name: ADC1 + ADC_S: + name: ADC1_S + FDCAN: + name: FDCAN1 + FDCAN_S: + name: FDCAN1_S + GPDMA: + name: GPDMA1 + GPDMA_S: + name: GPDMA1_S + I2C: + name: I2C1 + I2C_S: + name: I2C1_S + I3C: + name: I3C1 + I3C_S: + name: I3C1_S + SDMMC: + name: SDMMC1 + SDMMC_S: + name: SDMMC1_S + SPI: + name: SPI1 + SPI_S: + name: SPI1_S + UCPD: + name: UCPD1 + UCPD_S: + name: UCPD1_S + USART: + name: USART1 + USART_S: + name: USART1_S + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_19.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADCC: + _strip: ADC_ + +AES: + _strip: AES_ + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/h5.yaml + - collect/dac/v3.yaml + +DBGMCU: + _strip: DBGMCU_ + +DCACHE: + _strip: DCACHE_ + +DCMI: + _strip: DCMI_ + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DTS: + _strip: DTS_ + +EXTI: + _strip: EXTI_ + _include: + - patches/exti/exti4_5.yaml + - fields/exti/common.yaml + - fields/exti/exti_priv.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _strip: + FLASH_ + # - collect/flash/secbbr.yaml + +FMC: + _strip: FMC_ + PCR: + _merge: TAR* + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - fields/dma/gpdma/h5.yaml + - collect/dma/gpdma/h5.yaml + +GPIO[ABCDEFGHI]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCDEFGHI]: + _include: collect/gpio/v2r_derive.yaml + +#GTZC1_MPCBB?: # Seems to be completely missing from svd +# _strip: GTZC1_MPCBB?_ +# _include: +# - collect/gtzc/h5_u5.yaml + +GTZC1_TZIC: + _strip: GTZC1_TZIC_ + +GTZC1_TZSC: + _strip: GTZC1_TZSC_ + +HASH: + _strip: HASH_ + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +I3C1: + _strip: I3C_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/iwdg/h5.yaml + +LPTIM[12]: + _strip: + - LPTIM_ + - LPTIM?_ + +LPUART: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OCTOSPI: + _strip: OCTOSPI_ + _include: + - fields/octospi/u5.yaml + +OTFDEC1: + _strip: OTFDEC_ + +PKA: + _strip: PKA_ + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_h5.yaml + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + _include: + - patches/rcc/h523_h533.yaml + - fields/rcc/v3/h56x_h57x.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAES: + _strip: SAES_ + +SBS: + _strip: SBS_ + _include: + - patches/sbs/sbs.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - collect/sdio/respr.yaml + - collect/sdio/fifo.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + - fields/spi/spi_v3_i2s.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM1?: + _strip: TIM1?_ + +TIM[18]: + _include: + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM[25]: + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/tim_uifremap.yaml + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + CNT: + _modify: + CNT: + bitOffset: 0 + bitWidth: 32 + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM[34]: + _include: + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _include: collect/tim/tim4_derive.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM12: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/mms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v3/tim9.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim9.yaml + - collect/tim/ccr.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + #- fields/ucpd/ucpd_v1.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +USBSRAM: + _strip: USBSRAM_CHEP_ + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32h562.yaml b/devices/stm32h562.yaml new file mode 100644 index 000000000..e38b32cec --- /dev/null +++ b/devices/stm32h562.yaml @@ -0,0 +1,351 @@ +_svd: ../svd/stm32h562.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_19.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADCC: + _strip: ADC_ + +CORDIC: + _strip: CORDIC_ + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - patches/crc/idr.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/h5.yaml + - collect/dac/v3.yaml + MCR: + _merge: HFSEL? + +DBGMCU: + _strip: DBGMCU_ + +DCACHE: + _strip: DCACHE_ + +DCMI: + _strip: DCMI_ + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DTS: + _strip: DTS_ + +EXTI: + _strip: EXTI_ + _include: + - patches/exti/exti4_5.yaml + - fields/exti/common.yaml + - fields/exti/exti_priv.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + # - collect/flash/secbbr.yaml + +FMAC: + _strip: FMAC_ + +FMC: + _strip: FMC_ + PCR: + _merge: TAR* + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - fields/dma/gpdma/h5.yaml + - collect/dma/gpdma/h5.yaml + +GPIOC: + _strip: GPIO_ + +GPIO[ABCHI]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHI]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[123]: + _strip: GTZC1_MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC1_TZIC: + _strip: GTZC1_TZIC_ + +GTZC1_TZSC: + _strip: GTZC1_TZSC_ + +HASH: + _strip: HASH_ + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +I3C: + _strip: I3C_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + _include: + - patches/iwdg/add_onf.yaml + - patches/16bit_with_mask.yaml + - fields/iwdg/h5.yaml + +LPTIM1: + _strip: LPTIM_ + +LPUART: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OCTOSPI: + _strip: OCTOSPI_ + CR: + _modify: + FSEL: + name: MSEL + description: External memory select + _include: + - fields/octospi/u5.yaml + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_h5.yaml + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + _include: + - patches/rcc/h56x_h57x.yaml + - fields/rcc/v3/h56x_h57x.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _strip: SAI_ + _include: + - fields/sai/sai.yaml + - patches/sai/fsdef-rw.yaml + +SBS: + _strip: SBS_ + _include: + - patches/sbs/fmplus.yaml + - patches/sbs/sbs.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - collect/sdio/respr.yaml + - collect/sdio/fifo.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + - fields/spi/spi_v3_i2s.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM1?: + _strip: TIM1?_ + +TIM[18]: + _include: + - patches/tim/ccmr3.yaml + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/tim1_advanced.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM[25]: + _include: + - patches/tim/tim_uifremap.yaml + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM[34]: + _include: + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _include: collect/tim/tim4_derive.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM12: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/mms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v3/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[34]: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v3/tim13.yaml + - collect/tim/ccr.yaml + +TIM14: + _include: collect/tim/tim14_derive.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32h563.yaml b/devices/stm32h563.yaml new file mode 100644 index 000000000..80b30e5b9 --- /dev/null +++ b/devices/stm32h563.yaml @@ -0,0 +1,354 @@ +_svd: ../svd/stm32h563.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_19.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADCC: + _strip: ADC_ + +CORDIC: + _strip: CORDIC_ + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - patches/crc/idr.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/h5.yaml + - collect/dac/v3.yaml + MCR: + _merge: HFSEL? + +DBGMCU: + _strip: DBGMCU_ + +DCACHE: + _strip: DCACHE_ + +DCMI: + _strip: DCMI_ + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DTS: + _strip: DTS_ + +ETH: + _strip: ETH_ + +EXTI: + _strip: EXTI_ + _include: + - patches/exti/exti4_5.yaml + - fields/exti/common.yaml + - fields/exti/exti_priv.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + # - collect/flash/secbbr.yaml + +FMAC: + _strip: FMAC_ + +FMC: + _strip: FMC_ + PCR: + _merge: TAR* + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - fields/dma/gpdma/h5.yaml + - collect/dma/gpdma/h5.yaml + +GPIOC: + _strip: GPIO_ + +GPIO[ABCHI]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHI]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[123]: + _strip: GTZC1_MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC1_TZIC: + _strip: GTZC1_TZIC_ + +GTZC1_TZSC: + _strip: GTZC1_TZSC_ + +HASH: + _strip: HASH_ + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +I3C: + _strip: I3C_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + _include: + - patches/iwdg/add_onf.yaml + - patches/16bit_with_mask.yaml + - fields/iwdg/h5.yaml + +LPTIM1: + _strip: LPTIM_ + +LPUART: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OCTOSPI: + _strip: OCTOSPI_ + CR: + _modify: + FSEL: + name: MSEL + description: External memory select + _include: + - fields/octospi/u5.yaml + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_h5.yaml + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + _include: + - patches/rcc/h56x_h57x.yaml + - fields/rcc/v3/h56x_h57x.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _strip: SAI_ + _include: + - fields/sai/sai.yaml + - patches/sai/fsdef-rw.yaml + +SBS: + _strip: SBS_ + _include: + - patches/sbs/fmplus.yaml + - patches/sbs/sbs.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - collect/sdio/respr.yaml + - collect/sdio/fifo.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + - fields/spi/spi_v3_i2s.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM1?: + _strip: TIM1?_ + +TIM[18]: + _include: + - patches/tim/ccmr3.yaml + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/tim1_advanced.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM[25]: + _include: + - patches/tim/tim_uifremap.yaml + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM[34]: + _include: + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _include: collect/tim/tim4_derive.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM12: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/mms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v3/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[34]: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v3/tim13.yaml + - collect/tim/ccr.yaml + +TIM14: + _include: collect/tim/tim14_derive.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32h573.yaml b/devices/stm32h573.yaml new file mode 100644 index 000000000..1db7b610e --- /dev/null +++ b/devices/stm32h573.yaml @@ -0,0 +1,369 @@ +_svd: ../svd/stm32h573.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_19.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADCC: + _strip: ADC_ + +AES: + _strip: AES_ + _include: + - fields/aes/v3.yaml + +CORDIC: + _strip: CORDIC_ + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - patches/crc/idr.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/h5.yaml + - collect/dac/v3.yaml + MCR: + _merge: HFSEL? + +DBGMCU: + _strip: DBGMCU_ + +DCACHE: + _strip: DCACHE_ + +DCMI: + _strip: DCMI_ + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DTS: + _strip: DTS_ + +ETH: + _strip: ETH_ + +EXTI: + _strip: EXTI_ + _include: + - patches/exti/exti4_5.yaml + - fields/exti/common.yaml + - fields/exti/exti_priv.yaml + +FDCAN1: + _strip: + FDCAN_ + # - collect/flash/secbbr.yaml + +FLASH: + _strip: FLASH_ + +FMAC: + _strip: FMAC_ + +FMC: + _strip: FMC_ + PCR: + _merge: TAR* + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - fields/dma/gpdma/h5.yaml + - collect/dma/gpdma/h5.yaml + +GPIOC: + _strip: GPIO_ + +GPIO[ABCHI]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHI]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[123]: + _strip: GTZC1_MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC1_TZIC: + _strip: GTZC1_TZIC_ + +GTZC1_TZSC: + _strip: GTZC1_TZSC_ + +HASH: + _strip: HASH_ + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +I3C: + _strip: I3C_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + _include: + - patches/iwdg/add_onf.yaml + - patches/16bit_with_mask.yaml + - fields/iwdg/h5.yaml + +LPTIM1: + _strip: LPTIM_ + +LPUART: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OCTOSPI: + _strip: OCTOSPI_ + CR: + _modify: + FSEL: + name: MSEL + description: External memory select + _include: + - fields/octospi/u5.yaml + +OTFDEC1: + _strip: OTFDEC_ + +PKA: + _strip: PKA_ + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_h5.yaml + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + _include: + - patches/rcc/h56x_h57x.yaml + - fields/rcc/v3/h56x_h57x.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAES: + _strip: SAES_ + +SAI1: + _strip: SAI_ + _include: + - fields/sai/sai.yaml + - patches/sai/fsdef-rw.yaml + +SBS: + _strip: SBS_ + _include: + - patches/sbs/fmplus.yaml + - patches/sbs/sbs.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - collect/sdio/respr.yaml + - collect/sdio/fifo.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + - fields/spi/spi_v3_i2s.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM1?: + _strip: TIM1?_ + +TIM[18]: + _include: + - patches/tim/ccmr3.yaml + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/tim1_advanced.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM[25]: + _include: + - patches/tim/tim_uifremap.yaml + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM[34]: + _include: + - patches/tim/tim2_mms_ts_sms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - patches/tim/v2/oc3m.yaml + - fields/tim/tim_common_ext.yaml + - fields/tim/v3/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _include: collect/tim/tim4_derive.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM12: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/mms.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v3/tim9.yaml + - collect/tim/ccr.yaml + +TIM1[34]: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v3/tim13.yaml + - collect/tim/ccr.yaml + +TIM14: + _include: collect/tim/tim14_derive.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/oc1m.yaml + - patches/tim/v2/oc2m.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - patches/tim/v2/oc1m.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32h723.yaml b/devices/stm32h723.yaml new file mode 100644 index 000000000..85f967525 --- /dev/null +++ b/devices/stm32h723.yaml @@ -0,0 +1,497 @@ +_svd: ../svd/stm32h723.svd + +_clear_fields: "*" + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +# Fix invalid groupName +_modify: + COMP1: + groupName: COMP + OctoSPII_O_Manager: + groupName: OctoSPII_O_Manager + DMAMUX3: + name: DMAMUX2 + description: DMAMUX2 + ADC1: + addressBlock: + offset: 0x0 + size: 0x100 + usage: registers + Flash: + name: FLASH + groupName: FLASH + +ADC3_Common: + _strip: ADC_ + +ADC12_Common,ADC3_Common: + #_include: fields/adc/adc_v3_common_h7.yaml + CCR: + _modify: + "VSENSEEN,TSEN": + name: VSENSEEN + +ADC3: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL? + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/offset.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CORDIC: + _strip: CORDIC_ + _include: + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h73x.yaml + - collect/dac/v3.yaml + +# Modify the DBGMCU.CR register fields names to be consistent with RM0468. +# TODO: Interesting aside: the svd lists these controls additionally for D2 and +# D3, while the RM0468 specifies those as reserved bits, while still having +# clock controls specified for D2, D3. Thus, it may not be unthinkable that +# the same name changes need to be done for D2, D3, even though the reference +# manual does not specify them. OR: perhaps remove the D2, D3 fields instead? +DBGMCU: + CR: + _modify: + DBGSTBD1: + name: DBGSTBY_D1 + DBGSTPD1: + name: DBGSTOP_D1 + DBGSLPD1: + name: DBGSLEEP_D1 + +DCMI: + _include: + - patches/dcmi/dcmi.yaml + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_DMA: {} + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + OPTKEYR: + access: write-only + +FMAC: + _strip: FMAC_ + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABCJK]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCJK]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: + - HSEM_ + - C1 + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _add: + _interrupts: + LTDC_ERR: + value: 89 + description: LCD-TFT global Error interrupt + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +# OCTOSPI blocks +OCTOSPI1: + _include: + - patches/octospi/address.yaml + - patches/octospi/ddm.yaml + - fields/octospi/l4.yaml + +OctoSPII_O_Manager: {} + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + _add: + _interrupts: + OTG_HS_EP1_OUT: + value: 74 + description: USB OTG_HS OUT endpoint1 global interrupt + OTG_HS_EP1_IN: + value: 75 + description: USB OTG_HS IN endpoint1 global interrupt + OTG_HS_WKUP: + value: 76 + description: USB OTG_HS wakeup Interrupt through EXTI line + OTG_HS: + value: 77 + description: USB OTG_HS global interrupt + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +# PWR block +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/wkupc1246.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +# RCC block +RCC: + _modify: + # Fix reset values for these registers. + # Note that the rename operation to remove C1 happens alongside this + # modification, so we have to use the original names. + C1_APB1LLPENR: + resetValue: "0xE8FFCBFF" + C1_APB4ENR: + resetValue: "0x00010000" + C1_APB4LPENR: + resetValue: "0x0421DEAA" + _include: + - patches/rcc/h735.yaml + - patches/rcc/h7_hsicfgr_csicfgr_735.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - patches/rng/h735.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +# SYSCFG block +SYSCFG: + _include: + - patches/syscfg/h73x.yaml + +TIM1: + _modify: + _interrupts: + TIM_CC: + name: TIM1_CC + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +# ----------------------------------------------------------------------------- + +_include: + - patches/ethernet/h7_combined_desc.yaml + - patches/gpio/h7_jk.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h725.yaml b/devices/stm32h725.yaml new file mode 100644 index 000000000..afe010648 --- /dev/null +++ b/devices/stm32h725.yaml @@ -0,0 +1,500 @@ +_svd: ../svd/stm32h725.svd + +_clear_fields: "*" + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +# Fix invalid groupName +_modify: + COMP1: + groupName: COMP + OctoSPII_O_Manager: + groupName: OctoSPII_O_Manager + DMAMUX3: + name: DMAMUX2 + description: DMAMUX2 + ADC1: + addressBlock: + offset: 0x0 + size: 0x100 + usage: registers + Flash: + name: FLASH + groupName: FLASH + +ADC3_Common: + _strip: ADC_ + +ADC12_Common,ADC3_Common: + #_include: fields/adc/adc_v3_common_h7.yaml + CCR: + _modify: + "VSENSEEN,TSEN": + name: VSENSEEN + +ADC3: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL? + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/offset.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CORDIC: + _strip: CORDIC_ + _include: + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h73x.yaml + - collect/dac/v3.yaml + +# Modify the DBGMCU.CR register fields names to be consistent with RM0468. +# TODO: Interesting aside: the svd lists these controls additionally for D2 and +# D3, while the RM0468 specifies those as reserved bits, while still having +# clock controls specified for D2, D3. Thus, it may not be unthinkable that +# the same name changes need to be done for D2, D3, even though the reference +# manual does not specify them. OR: perhaps remove the D2, D3 fields instead? +DBGMCU: + CR: + _modify: + DBGSTBD1: + name: DBGSTBY_D1 + DBGSTPD1: + name: DBGSTOP_D1 + DBGSLPD1: + name: DBGSLEEP_D1 + +DCMI: + _include: + - patches/dcmi/dcmi.yaml + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_DMA: {} + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + OPTKEYR: + access: write-only + +FMAC: + _strip: FMAC_ + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABCJK]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCJK]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: + - HSEM_ + - C1 + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _add: + _interrupts: + LTDC_ERR: + value: 89 + description: LCD-TFT global Error interrupt + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +# OCTOSPI blocks +OCTOSPI1: + _include: + - patches/octospi/address.yaml + - patches/octospi/ddm.yaml + - fields/octospi/l4.yaml + +OctoSPII_O_Manager: {} + +OPAMP: {} + +OTFDEC1: + _strip: OTFDEC_ + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + _add: + _interrupts: + OTG_HS_EP1_OUT: + value: 74 + description: USB OTG_HS OUT endpoint1 global interrupt + OTG_HS_EP1_IN: + value: 75 + description: USB OTG_HS IN endpoint1 global interrupt + OTG_HS_WKUP: + value: 76 + description: USB OTG_HS wakeup Interrupt through EXTI line + OTG_HS: + value: 77 + description: USB OTG_HS global interrupt + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +# PWR block +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/wkupc1246.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +# RCC block +RCC: + _modify: + # Fix reset values for these registers. + # Note that the rename operation to remove C1 happens alongside this + # modification, so we have to use the original names. + C1_APB1LLPENR: + resetValue: "0xE8FFCBFF" + C1_APB4ENR: + resetValue: "0x00010000" + C1_APB4LPENR: + resetValue: "0x0421DEAA" + _include: + - patches/rcc/h735.yaml + - patches/rcc/h7_hsicfgr_csicfgr_735.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - patches/rng/h735.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +# SYSCFG block +SYSCFG: + _include: + - patches/syscfg/h73x.yaml + +TIM1: + _modify: + _interrupts: + TIM_CC: + name: TIM1_CC + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +# ----------------------------------------------------------------------------- + +_include: + - patches/ethernet/h7_combined_desc.yaml + - patches/gpio/h7_jk.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h730.yaml b/devices/stm32h730.yaml new file mode 100644 index 000000000..95012ca3c --- /dev/null +++ b/devices/stm32h730.yaml @@ -0,0 +1,508 @@ +_svd: ../svd/stm32h730.svd + +_clear_fields: "*" + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +# Fix invalid groupName +_modify: + COMP1: + groupName: COMP + OctoSPII_O_Manager: + groupName: OctoSPII_O_Manager + DMAMUX3: + name: DMAMUX2 + description: DMAMUX2 + ADC1: + addressBlock: + offset: 0x0 + size: 0x100 + usage: registers + Flash: + name: FLASH + groupName: FLASH + +ADC3_Common: + _strip: ADC_ + +ADC12_Common,ADC3_Common: + #_include: fields/adc/adc_v3_common_h7.yaml + CCR: + _modify: + "VSENSEEN,TSEN": + name: VSENSEEN + +ADC3: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL? + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/offset.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CORDIC: + _strip: CORDIC_ + _include: + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +# Merge the hundreds of individual bit fields into single fields for the +# crypt key/iv registers. +CRYP: + "K[0123][LR]R": + _merge: k* + "IV[01][LR]R": + _merge: IV* + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h73x.yaml + - collect/dac/v3.yaml + +# Modify the DBGMCU.CR register fields names to be consistent with RM0468. +# TODO: Interesting aside: the svd lists these controls additionally for D2 and +# D3, while the RM0468 specifies those as reserved bits, while still having +# clock controls specified for D2, D3. Thus, it may not be unthinkable that +# the same name changes need to be done for D2, D3, even though the reference +# manual does not specify them. OR: perhaps remove the D2, D3 fields instead? +DBGMCU: + CR: + _modify: + DBGSTBD1: + name: DBGSTBY_D1 + DBGSTPD1: + name: DBGSTOP_D1 + DBGSLPD1: + name: DBGSLEEP_D1 + +DCMI: + _include: + - patches/dcmi/dcmi.yaml + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_DMA: {} + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + OPTKEYR: + access: write-only + +FMAC: + _strip: FMAC_ + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABCJK]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCJK]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: + - HSEM_ + - C1 + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _add: + _interrupts: + LTDC_ERR: + value: 89 + description: LCD-TFT global Error interrupt + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +# OCTOSPI blocks +OCTOSPI1: + _include: + - patches/octospi/address.yaml + - patches/octospi/ddm.yaml + - fields/octospi/l4.yaml + +OctoSPII_O_Manager: {} + +OPAMP: {} + +OTFDEC1: + _strip: OTFDEC_ + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + _add: + _interrupts: + OTG_HS_EP1_OUT: + value: 74 + description: USB OTG_HS OUT endpoint1 global interrupt + OTG_HS_EP1_IN: + value: 75 + description: USB OTG_HS IN endpoint1 global interrupt + OTG_HS_WKUP: + value: 76 + description: USB OTG_HS wakeup Interrupt through EXTI line + OTG_HS: + value: 77 + description: USB OTG_HS global interrupt + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +# PWR block +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/wkupc1246.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +# RCC block +RCC: + _modify: + # Fix reset values for these registers. + # Note that the rename operation to remove C1 happens alongside this + # modification, so we have to use the original names. + C1_APB1LLPENR: + resetValue: "0xE8FFCBFF" + C1_APB4ENR: + resetValue: "0x00010000" + C1_APB4LPENR: + resetValue: "0x0421DEAA" + _include: + - patches/rcc/h735.yaml + - patches/rcc/h7_hsicfgr_csicfgr_735.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - patches/rng/h735.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +# SYSCFG block +SYSCFG: + _include: + - patches/syscfg/h73x.yaml + +TIM1: + _modify: + _interrupts: + TIM_CC: + name: TIM1_CC + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +# ----------------------------------------------------------------------------- + +_include: + - patches/ethernet/h7_combined_desc.yaml + - patches/gpio/h7_jk.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h733.yaml b/devices/stm32h733.yaml new file mode 100644 index 000000000..14a9f8827 --- /dev/null +++ b/devices/stm32h733.yaml @@ -0,0 +1,508 @@ +_svd: ../svd/stm32h733.svd + +_clear_fields: "*" + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +# Fix invalid groupName +_modify: + COMP1: + groupName: COMP + OctoSPII_O_Manager: + groupName: OctoSPII_O_Manager + DMAMUX3: + name: DMAMUX2 + description: DMAMUX2 + ADC1: + addressBlock: + offset: 0x0 + size: 0x100 + usage: registers + Flash: + name: FLASH + groupName: FLASH + +ADC3_Common: + _strip: ADC_ + +ADC12_Common,ADC3_Common: + #_include: fields/adc/adc_v3_common_h7.yaml + CCR: + _modify: + "VSENSEEN,TSEN": + name: VSENSEEN + +ADC3: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL? + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/offset.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CORDIC: + _strip: CORDIC_ + _include: + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +# Merge the hundreds of individual bit fields into single fields for the +# crypt key/iv registers. +CRYP: + "K[0123][LR]R": + _merge: k* + "IV[01][LR]R": + _merge: IV* + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h73x.yaml + - collect/dac/v3.yaml + +# Modify the DBGMCU.CR register fields names to be consistent with RM0468. +# TODO: Interesting aside: the svd lists these controls additionally for D2 and +# D3, while the RM0468 specifies those as reserved bits, while still having +# clock controls specified for D2, D3. Thus, it may not be unthinkable that +# the same name changes need to be done for D2, D3, even though the reference +# manual does not specify them. OR: perhaps remove the D2, D3 fields instead? +DBGMCU: + CR: + _modify: + DBGSTBD1: + name: DBGSTBY_D1 + DBGSTPD1: + name: DBGSTOP_D1 + DBGSLPD1: + name: DBGSLEEP_D1 + +DCMI: + _include: + - patches/dcmi/dcmi.yaml + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_DMA: {} + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + OPTKEYR: + access: write-only + +FMAC: + _strip: FMAC_ + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABCJK]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCJK]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: + - HSEM_ + - C1 + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _add: + _interrupts: + LTDC_ERR: + value: 89 + description: LCD-TFT global Error interrupt + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +# OCTOSPI blocks +OCTOSPI1: + _include: + - patches/octospi/address.yaml + - patches/octospi/ddm.yaml + - fields/octospi/l4.yaml + +OctoSPII_O_Manager: {} + +OPAMP: {} + +OTFDEC1: + _strip: OTFDEC_ + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + _add: + _interrupts: + OTG_HS_EP1_OUT: + value: 74 + description: USB OTG_HS OUT endpoint1 global interrupt + OTG_HS_EP1_IN: + value: 75 + description: USB OTG_HS IN endpoint1 global interrupt + OTG_HS_WKUP: + value: 76 + description: USB OTG_HS wakeup Interrupt through EXTI line + OTG_HS: + value: 77 + description: USB OTG_HS global interrupt + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +# PWR block +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/wkupc1246.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +# RCC block +RCC: + _modify: + # Fix reset values for these registers. + # Note that the rename operation to remove C1 happens alongside this + # modification, so we have to use the original names. + C1_APB1LLPENR: + resetValue: "0xE8FFCBFF" + C1_APB4ENR: + resetValue: "0x00010000" + C1_APB4LPENR: + resetValue: "0x0421DEAA" + _include: + - patches/rcc/h735.yaml + - patches/rcc/h7_hsicfgr_csicfgr_735.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - patches/rng/h735.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +# SYSCFG block +SYSCFG: + _include: + - patches/syscfg/h73x.yaml + +TIM1: + _modify: + _interrupts: + TIM_CC: + name: TIM1_CC + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +# ----------------------------------------------------------------------------- + +_include: + - patches/ethernet/h7_combined_desc.yaml + - patches/gpio/h7_jk.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h735.yaml b/devices/stm32h735.yaml new file mode 100644 index 000000000..164fdde39 --- /dev/null +++ b/devices/stm32h735.yaml @@ -0,0 +1,505 @@ +_svd: ../svd/stm32h735.svd + +_clear_fields: "*" + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +# Fix invalid groupName +_modify: + COMP1: + groupName: COMP + OctoSPII_O_Manager: + groupName: OctoSPII_O_Manager + DMAMUX3: + name: DMAMUX2 + description: DMAMUX2 + ADC1: + addressBlock: + offset: 0x0 + size: 0x100 + usage: registers + Flash: + name: FLASH + groupName: FLASH + +ADC3_Common: + _strip: ADC_ + +ADC12_Common,ADC3_Common: + #_include: fields/adc/adc_v3_common_h7.yaml + CCR: + _modify: + "VSENSEEN,TSEN": + name: VSENSEEN + +ADC3: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_h5.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL? + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/offset.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CORDIC: + _strip: CORDIC_ + _include: + - fields/cordic/v1.yaml + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +# Merge the hundreds of individual bit fields into single fields for the +# crypt key/iv registers. +CRYP: + "K[0123][LR]R": + _merge: k* + "IV[01][LR]R": + _merge: IV* + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h73x.yaml + - collect/dac/v3.yaml + +# Modify the DBGMCU.CR register fields names to be consistent with RM0468. +# TODO: Interesting aside: the svd lists these controls additionally for D2 and +# D3, while the RM0468 specifies those as reserved bits, while still having +# clock controls specified for D2, D3. Thus, it may not be unthinkable that +# the same name changes need to be done for D2, D3, even though the reference +# manual does not specify them. OR: perhaps remove the D2, D3 fields instead? +DBGMCU: + CR: + _modify: + DBGSTBD1: + name: DBGSTBY_D1 + DBGSTPD1: + name: DBGSTOP_D1 + DBGSLPD1: + name: DBGSLEEP_D1 + +DCMI: + _include: + - patches/dcmi/dcmi.yaml + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_DMA: {} + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + OPTKEYR: + access: write-only + +FMAC: + _strip: FMAC_ + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABCJK]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCJK]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: + - HSEM_ + - C1 + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _add: + _interrupts: + LTDC_ERR: + value: 89 + description: LCD-TFT global Error interrupt + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +# OCTOSPI blocks +OCTOSPI1: + _include: + - patches/octospi/address.yaml + - patches/octospi/ddm.yaml + - fields/octospi/l4.yaml + +OctoSPII_O_Manager: {} + +OPAMP: {} + +OTFDEC1: + _strip: OTFDEC_ + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + _add: + _interrupts: + OTG_HS_EP1_OUT: + value: 74 + description: USB OTG_HS OUT endpoint1 global interrupt + OTG_HS_EP1_IN: + value: 75 + description: USB OTG_HS IN endpoint1 global interrupt + OTG_HS_WKUP: + value: 76 + description: USB OTG_HS wakeup Interrupt through EXTI line + OTG_HS: + value: 77 + description: USB OTG_HS global interrupt + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +# PWR block +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/wkupc1246.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +# RCC block +RCC: + _modify: + # Fix reset values for these registers. + # Note that the rename operation to remove C1 happens alongside this + # modification, so we have to use the original names. + C1_APB1LLPENR: + resetValue: "0xE8FFCBFF" + C1_APB4ENR: + resetValue: "0x00010000" + C1_APB4LPENR: + resetValue: "0x0421DEAA" + _include: + - patches/rcc/h735.yaml + - patches/rcc/h7_hsicfgr_csicfgr_735.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - patches/rng/h735.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +# SYSCFG block +SYSCFG: + _include: + - patches/syscfg/h73x.yaml + +TIM1: + _modify: + _interrupts: + TIM_CC: + name: TIM1_CC + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +# ----------------------------------------------------------------------------- +_include: + - patches/ethernet/h7_combined_desc.yaml + - patches/gpio/h7_jk.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h742.yaml b/devices/stm32h742.yaml new file mode 100644 index 000000000..e7fd65240 --- /dev/null +++ b/devices/stm32h742.yaml @@ -0,0 +1,432 @@ +_svd: ../svd/stm32h742.svd + +_clear_fields: "*" + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + groupName: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_1.yaml + - fields/adc/adc_h7_revision_y.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_DMA: {} + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + PRAR_PRG2: + addressOffset: 0x12C + alternateRegister: "" + KEYR[12]: + access: write-only + OPTKEYR: + access: write-only + BOOT_PRGR: + access: read-write + CR1: + _add: + # CR2 only. Needed for clusterization + SPSS: + description: Bank 2 special sector selection bit + bitOffset: 14 + bitWidth: 1 + SR1: + _delete: CRCRDERR1 + CCR1: + _delete: CLR_CRCRDERR1 + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: {} + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _include: + - patches/rcc/h7_usb2otghs.yaml + - patches/rcc/h7_common_singlecore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_y.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _delete: [VER, ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _delete: + _interrupts: + - TIM4 + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _add: + _interrupts: + TIM4: + description: TIM4 global interrupt + value: 30 + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/ethernet/h7_desc.yaml + - patches/dbgmcu/h7.yaml + - patches/ethernet/h7_dma_mr.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml + - patches/h743_hrtim_common.yaml diff --git a/devices/stm32h743.yaml b/devices/stm32h743.yaml index 3826cf8ef..52c4352ab 100644 --- a/devices/stm32h743.yaml +++ b/devices/stm32h743.yaml @@ -1,68 +1,436 @@ _svd: ../svd/stm32h743.svd +_clear_fields: "*" + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + groupName: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + DFSDM: + from: ../svd/stm32h753.svd:DFSDM + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_1.yaml + - fields/adc/adc_h7_revision_y.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_DMA: {} + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + PRAR_PRG2: + addressOffset: 0x12C + alternateRegister: "" + KEYR[12]: + access: write-only + OPTKEYR: + access: write-only + BOOT_PRGR: + access: read-write + CR1: + _add: + # CR2 only. Needed for clusterization + SPSS: + description: Bank 2 special sector selection bit + bitOffset: 14 + bitWidth: 1 + SR1: + _delete: CRCRDERR1 + CCR1: + _delete: CLR_CRCRDERR1 + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: {} + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _include: + - patches/rcc/h7_usb2otghs.yaml + - patches/rcc/h7_common_singlecore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_y.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _delete: [VER, ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _delete: + _interrupts: + - TIM4 + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _add: + _interrupts: + TIM4: + description: TIM4 global interrupt + value: 30 + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - common_patches/h7_common_singlecore.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/dma/bdma.yaml - - common_patches/dma/dma_v3.yaml - - common_patches/fsmc/fsmc_sdram_cluster.yaml - - common_patches/h7_rcc_src_sel.yaml - - common_patches/h7_ethernet_desc.yaml - - common_patches/h7_exti_singlecore.yaml - - common_patches/h7_dbgmcu.yaml - - common_patches/h7_dmacr.yaml - - common_patches/h7_dmamux.yaml - - common_patches/dma/dma2d_v2.yaml - - common_patches/h7_adc.yaml - - common_patches/h7_spdifrx.yaml - - common_patches/h7_otg.yaml - - common_patches/flash/flash_dual_bank.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/merge_I2C_CR2_SADDx_fields.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/h7_sai.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/ramecc/ramecc_new.yaml - - ../peripherals/adc/adc_v3_h7.yaml - - ../peripherals/adc/adc_v3_common_h7.yaml - - ../peripherals/adc/adc_h7_revision_y.yaml - - ../peripherals/axi/axi_v1.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dma/bdma.yaml - - ../peripherals/dma/dma_v3.yaml - - ../peripherals/dma/dmamux_v1.yaml - - ../peripherals/dma/dma2d_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/rcc/rcc_h7.yaml - - ../peripherals/rcc/rcc_h7_revision_y.yaml - - ../peripherals/rng/rng_v1.yaml - - ../peripherals/rng/rng_v1_ced.yaml - - ../peripherals/spi/spi_v3.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_gp1.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/tim/tim_h7.yaml - - common_patches/tim/tim_h7.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti_h7.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/tim/tim1234_1567_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/ethernet/h7_desc.yaml + - patches/dbgmcu/h7.yaml + - patches/ethernet/h7_dma_mr.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml + - patches/h743_hrtim_common.yaml diff --git a/devices/stm32h743v.yaml b/devices/stm32h743v.yaml index 60040140c..052320d34 100644 --- a/devices/stm32h743v.yaml +++ b/devices/stm32h743v.yaml @@ -1,70 +1,438 @@ _svd: ../svd/stm32h743v.svd +_clear_fields: "*" + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + groupName: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + DFSDM: + from: ../svd/stm32h753.svd:DFSDM + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_1.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_DMA: {} + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + PRAR_PRG2: + addressOffset: 0x12C + alternateRegister: "" + KEYR[12]: + access: write-only + OPTKEYR: + access: write-only + BOOT_PRGR: + access: read-write + CR1: + _add: + # CR2 only. Needed for clusterization + SPSS: + description: Bank 2 special sector selection bit + bitOffset: 14 + bitWidth: 1 + SR1: + _delete: CRCRDERR1 + CCR1: + _delete: CLR_CRCRDERR1 + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: {} + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _include: + - patches/rcc/h7_usb2otghs.yaml + - patches/rcc/h7_common_singlecore.yaml + - patches/rcc/h7_src_sel.yaml + - patches/rcc/h7_hsicfgr_csicfgr_rev_v.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _delete: [VER, ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _delete: + _interrupts: + - TIM4 + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _add: + _interrupts: + TIM4: + description: TIM4 global interrupt + value: 30 + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - common_patches/h7_common_singlecore.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/dma/bdma.yaml - - common_patches/dma/dma_v3.yaml - - common_patches/fsmc/fsmc_sdram_cluster.yaml - - common_patches/h7_rcc_src_sel.yaml - - common_patches/h7_ethernet_desc.yaml - - common_patches/h7_exti_singlecore.yaml - - common_patches/h7_dbgmcu.yaml - - common_patches/h7_dmacr.yaml - - common_patches/h7_dmamux.yaml - - common_patches/dma/dma2d_v2.yaml - - common_patches/h7_adc.yaml - - common_patches/h7_adc_boost_rev_v.yaml - - common_patches/h7_spdifrx.yaml - - common_patches/h7_otg.yaml - - common_patches/flash/flash_dual_bank.yaml - - common_patches/h7_hsicfgr_csicfgr_rev_v.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/merge_I2C_CR2_SADDx_fields.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/h7_sai.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/ramecc/ramecc_new.yaml - - ../peripherals/adc/adc_v3_h7.yaml - - ../peripherals/adc/adc_v3_common_h7.yaml - - ../peripherals/adc/adc_h7_revision_v.yaml - - ../peripherals/axi/axi_v1.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dma/bdma.yaml - - ../peripherals/dma/dma_v3.yaml - - ../peripherals/dma/dmamux_v1.yaml - - ../peripherals/dma/dma2d_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/rcc/rcc_h7.yaml - - ../peripherals/rcc/rcc_h7_revision_v.yaml - - ../peripherals/rng/rng_v1.yaml - - ../peripherals/rng/rng_v1_ced.yaml - - ../peripherals/spi/spi_v3.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_gp1.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/tim/tim_h7.yaml - - common_patches/tim/tim_h7.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti_h7.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/tim/tim1234_1567_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/ethernet/h7_dma_mr.yaml + - patches/ethernet/h7_desc.yaml + - patches/dbgmcu/h7.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml + - patches/h743_hrtim_common.yaml diff --git a/devices/stm32h745cm4.yaml b/devices/stm32h745cm4.yaml new file mode 100644 index 000000000..416e1ee9b --- /dev/null +++ b/devices/stm32h745cm4.yaml @@ -0,0 +1,425 @@ +_svd: ../svd/stm32h745cm4.svd + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ART: {} + +AXI: + _strip: AXI_ + +BDMA: + _include: + - patches/dma/bdma.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +DSIHOST: + _strip: DSI_ + _include: + - patches/dsi/h7-desc.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_dualcore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/h7_dual.yaml + - patches/hsem/h7_dual_cm4.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/h7_dual.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _delete: + - ICSCR + _add: + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_dualcore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + - fields/syscfg/syscfg_h747.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/h743_hrtim_common.yaml + - patches/ethernet/h7_combined_desc.yaml + - patches/flash/h7_dualcore.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h745cm7.yaml b/devices/stm32h745cm7.yaml new file mode 100644 index 000000000..4c1484bab --- /dev/null +++ b/devices/stm32h745cm7.yaml @@ -0,0 +1,426 @@ +_svd: ../svd/stm32h745cm7.svd + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ART: {} + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _include: + - patches/dma/bdma.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +DSIHOST: + _strip: DSI_ + _include: + - patches/dsi/h7-desc.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_dualcore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/h7_dual.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/h7_dual.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _delete: + - ICSCR + _add: + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_dualcore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + - fields/syscfg/syscfg_h747.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/h743_hrtim_common.yaml + - patches/ethernet/h7_combined_desc.yaml + - patches/flash/h7_dualcore.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h747cm4.yaml b/devices/stm32h747cm4.yaml index c65854bb9..f5546174a 100644 --- a/devices/stm32h747cm4.yaml +++ b/devices/stm32h747cm4.yaml @@ -1,86 +1,423 @@ _svd: ../svd/stm32h747cm4.svd -# Applies to the H745/H747/H755/H757 -# CRYP and HASH are unavailable on the H745/H747 - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ART: {} + +AXI: + _strip: AXI_ + +BDMA: + _include: + - patches/dma/bdma.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +DSIHOST: + _strip: DSI_ + _include: + - patches/dsi/h7-desc.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_dualcore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/h7_dual.yaml + - patches/hsem/h7_dual_cm4.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/h7_dual.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _delete: + - ICSCR + _add: + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_dualcore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + - fields/syscfg/syscfg_h747.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml _include: - - common_patches/h7_common_dualcore.yaml - - common_patches/4_nvic_prio_bits.yaml # Specifically for CM4 core - - common_patches/dma_fcr_wo.yaml - - common_patches/dma/bdma.yaml - - common_patches/dma/dma_v3.yaml - - common_patches/fsmc/fsmc_sdram_cluster.yaml - - common_patches/h7_rcc_src_sel.yaml - - common_patches/h7_ethernet_combined_desc.yaml - - common_patches/h7_exti_dualcore.yaml - - common_patches/h7_dbgmcu.yaml - - common_patches/h7_dbgmcu_dualcore.yaml - - common_patches/h7_dmamux.yaml - - common_patches/dma/dma2d_v2.yaml - - common_patches/h7_adc.yaml - - common_patches/h7_dsi.yaml - - common_patches/h7_adc_boost_rev_v.yaml - - common_patches/h7_dualcore_flash.yaml - - common_patches/h7_hsicfgr_csicfgr_rev_v.yaml - - common_patches/h7_sai.yaml - - common_patches/h7_spdifrx.yaml - - common_patches/h7_otg.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/flash/flash_dual_bank.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/merge_I2C_CR2_SADDx_fields.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/ramecc/ramecc_new.yaml - - ../peripherals/adc/adc_v3_h7.yaml - - ../peripherals/adc/adc_v3_common_h7.yaml - - ../peripherals/adc/adc_h7_revision_v.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dma/bdma.yaml - - ../peripherals/dma/dma_v3.yaml - - ../peripherals/dma/dmamux_v1.yaml - - ../peripherals/dma/dma2d_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/rcc/rcc_h7.yaml - - ../peripherals/rcc/rcc_h7_revision_v.yaml - - ../peripherals/rng/rng_v1.yaml - - ../peripherals/rng/rng_v1_ced.yaml - - ../peripherals/spi/spi_v3.yaml - - ../peripherals/syscfg/syscfg_h747.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_gp1.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - common_patches/tim/tim_h7.yaml - - ../peripherals/tim/tim_h7.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti_h7.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/tim/tim1234_1567_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/h743_hrtim_common.yaml + - patches/ethernet/h7_combined_desc.yaml + - patches/flash/h7_dualcore.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h747cm7.yaml b/devices/stm32h747cm7.yaml index 8cea42ba4..4793755bc 100644 --- a/devices/stm32h747cm7.yaml +++ b/devices/stm32h747cm7.yaml @@ -1,87 +1,428 @@ _svd: ../svd/stm32h747cm7.svd -# Applies to the H745/H747/H755/H757 -# CRYP and HASH are unavailable on the H745/H747 - -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ART: {} + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _include: + - patches/dma/bdma.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +DSIHOST: + _strip: DSI_ + _include: + - patches/dsi/h7-desc.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_dualcore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/h7_dual.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/h7_dual.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _delete: + - ICSCR + _add: + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_dualcore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + - fields/syscfg/syscfg_h747.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml _include: - - common_patches/h7_common_dualcore.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/dma/bdma.yaml - - common_patches/dma/dma_v3.yaml - - common_patches/fsmc/fsmc_sdram_cluster.yaml - - common_patches/h7_rcc_src_sel.yaml - - common_patches/h7_ethernet_combined_desc.yaml - - common_patches/h7_exti_dualcore.yaml - - common_patches/h7_dbgmcu.yaml - - common_patches/h7_dbgmcu_dualcore.yaml - - common_patches/h7_dmacr.yaml - - common_patches/h7_dmamux.yaml - - common_patches/dma/dma2d_v2.yaml - - common_patches/h7_adc.yaml - - common_patches/h7_dsi.yaml - - common_patches/h7_adc_boost_rev_v.yaml - - common_patches/h7_dualcore_flash.yaml - - common_patches/h7_hsicfgr_csicfgr_rev_v.yaml - - common_patches/h7_sai.yaml - - common_patches/h7_spdifrx.yaml - - common_patches/h7_otg.yaml - - common_patches/flash/flash_dual_bank.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/merge_I2C_CR2_SADDx_fields.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/ramecc/ramecc_new.yaml - - ../peripherals/adc/adc_v3_h7.yaml - - ../peripherals/adc/adc_v3_common_h7.yaml - - ../peripherals/adc/adc_h7_revision_v.yaml - - ../peripherals/axi/axi_v1.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dma/bdma.yaml - - ../peripherals/dma/dma_v3.yaml - - ../peripherals/dma/dmamux_v1.yaml - - ../peripherals/dma/dma2d_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/rcc/rcc_h7.yaml - - ../peripherals/rcc/rcc_h7_revision_v.yaml - - ../peripherals/rng/rng_v1.yaml - - ../peripherals/rng/rng_v1_ced.yaml - - ../peripherals/spi/spi_v3.yaml - - ../peripherals/syscfg/syscfg_h747.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_gp1.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - common_patches/tim/tim_h7.yaml - - ../peripherals/tim/tim_h7.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti_h7.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/tim/tim1234_1567_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/h743_hrtim_common.yaml + - patches/ethernet/h7_combined_desc.yaml + - patches/flash/h7_dualcore.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h750.yaml b/devices/stm32h750.yaml new file mode 100644 index 000000000..bea5035b4 --- /dev/null +++ b/devices/stm32h750.yaml @@ -0,0 +1,432 @@ +_svd: ../svd/stm32h750.svd + +_clear_fields: "*" + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + groupName: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_1.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _strip: CEC_ + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +CRYP: {} + +DAC: + _strip: DAC_ + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _strip: DMA2D_ + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _strip: DMAMUX?_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +ETH: + _strip: ETH_ + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + PRAR_PRG2: + addressOffset: 0x12C + alternateRegister: "" + KEYR[12]: + access: write-only + OPTKEYR: + access: write-only + BOOT_PRGR: + access: read-write + CR1: + _add: + # CR2 only. Needed for clusterization + SPSS: + description: Bank 2 special sector selection bit + bitOffset: 14 + bitWidth: 1 + SR1: + _delete: CRCRDERR1 + CCR1: + _delete: CLR_CRCRDERR1 + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _strip: FMC_ + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _strip: GPIO_ + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _strip: I2C_ + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: + _strip: JPEG_ + +LPTIM1: + _strip: LPTIM_ + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PWR: + _strip: PWR_ + +QUADSPI: + _strip: QUADSPI_ + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _include: + - patches/rcc/h7_common_singlecore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_y.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _delete: [SDMMC_VER, SDMMC_ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: {} + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/dbgmcu/h7.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/h743_hrtim_common.yaml diff --git a/devices/stm32h753.yaml b/devices/stm32h753.yaml index 5baf5f753..7da0e75c5 100644 --- a/devices/stm32h753.yaml +++ b/devices/stm32h753.yaml @@ -1,77 +1,446 @@ _svd: ../svd/stm32h753.svd +_clear_fields: "*" + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + groupName: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_1.yaml + - fields/adc/adc_h7_revision_y.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + # Merge the hundreds of individual bit fields into single fields for the # crypt key/iv registers. CRYP: "K[0123][LR]R": - _merge: - - "K*" + _merge: K* "IV[01][LR]R": - _merge: - - "IV*" + _merge: IV* + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_DMA: {} + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + PRAR_PRG2: + addressOffset: 0x12C + alternateRegister: "" + KEYR[12]: + access: write-only + OPTKEYR: + access: write-only + BOOT_PRGR: + access: read-write + CR1: + _add: + # CR2 only. Needed for clusterization + SPSS: + description: Bank 2 special sector selection bit + bitOffset: 14 + bitWidth: 1 + SR1: + _delete: CRCRDERR1 + CCR1: + _delete: CLR_CRCRDERR1 + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: {} + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _include: + - patches/rcc/h7_usb2otghs.yaml + - patches/rcc/h7_common_singlecore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_y.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _delete: [VER, ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _delete: + _interrupts: + - TIM4 + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _add: + _interrupts: + TIM4: + description: TIM4 global interrupt + value: 30 + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml _include: - - common_patches/h7_common_singlecore.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/dma/bdma.yaml - - common_patches/dma/dma_v3.yaml - - common_patches/fsmc/fsmc_sdram_cluster.yaml - - common_patches/h7_rcc_src_sel.yaml - - common_patches/h7_ethernet_desc.yaml - - common_patches/h7_exti_singlecore.yaml - - common_patches/h7_dbgmcu.yaml - - common_patches/h7_dmacr.yaml - - common_patches/h7_dmamux.yaml - - common_patches/dma/dma2d_v2.yaml - - common_patches/h7_adc.yaml - - common_patches/h7_spdifrx.yaml - - common_patches/h7_otg.yaml - - common_patches/flash/flash_dual_bank.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/merge_I2C_CR2_SADDx_fields.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/h7_sai.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/ramecc/ramecc_new.yaml - - ../peripherals/adc/adc_v3_h7.yaml - - ../peripherals/adc/adc_v3_common_h7.yaml - - ../peripherals/adc/adc_h7_revision_y.yaml - - ../peripherals/axi/axi_v1.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dma/bdma.yaml - - ../peripherals/dma/dma_v3.yaml - - ../peripherals/dma/dmamux_v1.yaml - - ../peripherals/dma/dma2d_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/rcc/rcc_h7.yaml - - ../peripherals/rcc/rcc_h7_revision_y.yaml - - ../peripherals/rng/rng_v1.yaml - - ../peripherals/rng/rng_v1_ced.yaml - - ../peripherals/spi/spi_v3.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_gp1.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/tim/tim_h7.yaml - - common_patches/tim/tim_h7.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti_h7.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/tim/tim1234_1567_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/ethernet/h7_dma_mr.yaml + - patches/ethernet/h7_desc.yaml + - patches/dbgmcu/h7.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml + - patches/h743_hrtim_common.yaml diff --git a/devices/stm32h753v.yaml b/devices/stm32h753v.yaml index e4d99e288..337c0fe9b 100644 --- a/devices/stm32h753v.yaml +++ b/devices/stm32h753v.yaml @@ -1,80 +1,446 @@ _svd: ../svd/stm32h753v.svd +_clear_fields: "*" + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + groupName: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_1.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _strip: BDMA_ + _include: + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + # Merge the hundreds of individual bit fields into single fields for the # crypt key/iv registers. CRYP: "K[0123][LR]R": - _merge: - - "K*" + _merge: K* "IV[01][LR]R": - _merge: - - "IV*" + _merge: IV* + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +Ethernet_DMA: {} + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _modify: + PRAR_PRG2: + addressOffset: 0x12C + alternateRegister: "" + KEYR[12]: + access: write-only + OPTKEYR: + access: write-only + BOOT_PRGR: + access: read-write + CR1: + _add: + # CR2 only. Needed for clusterization + SPSS: + description: Bank 2 special sector selection bit + bitOffset: 14 + bitWidth: 1 + SR1: + _delete: CRCRDERR1 + CCR1: + _delete: CLR_CRCRDERR1 + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: {} + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml + +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - collect/usb_otg/hs_global.yaml + +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml + +OTG1_HS_PWRCLK: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _include: + - patches/rcc/h7_usb2otghs.yaml + - patches/rcc/h7_common_singlecore.yaml + - patches/rcc/h7_src_sel.yaml + - patches/rcc/h7_hsicfgr_csicfgr_rev_v.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _delete: [VER, ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _delete: + _interrupts: + - TIM4 + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/tim_o24ce.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _add: + _interrupts: + TIM4: + description: TIM4 global interrupt + value: 30 + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml _include: - - common_patches/h7_common_singlecore.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/dma/bdma.yaml - - common_patches/dma/dma_v3.yaml - - common_patches/fsmc/fsmc_sdram_cluster.yaml - - common_patches/h7_rcc_src_sel.yaml - - common_patches/h7_ethernet_desc.yaml - - common_patches/h7_exti_singlecore.yaml - - common_patches/h7_dbgmcu.yaml - - common_patches/h7_dmacr.yaml - - common_patches/h7_dmamux.yaml - - common_patches/dma/dma2d_v2.yaml - - common_patches/h7_adc.yaml - - common_patches/h7_adc_boost_rev_v.yaml - - common_patches/h7_spdifrx.yaml - - common_patches/h7_otg.yaml - - common_patches/flash/flash_dual_bank.yaml - - common_patches/h7_hsicfgr_csicfgr_rev_v.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/merge_I2C_CR2_SADDx_fields.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/h7_sai.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - common_patches/ramecc/ramecc_new.yaml - - ../peripherals/adc/adc_v3_h7.yaml - - ../peripherals/adc/adc_v3_common_h7.yaml - - ../peripherals/adc/adc_h7_revision_v.yaml - - ../peripherals/axi/axi_v1.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dma/bdma.yaml - - ../peripherals/dma/dma_v3.yaml - - ../peripherals/dma/dmamux_v1.yaml - - ../peripherals/dma/dma2d_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/rcc/rcc_h7.yaml - - ../peripherals/rcc/rcc_h7_revision_v.yaml - - ../peripherals/rng/rng_v1.yaml - - ../peripherals/rng/rng_v1_ced.yaml - - ../peripherals/spi/spi_v3.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_gp1.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/tim/tim_h7.yaml - - common_patches/tim/tim_h7.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti_h7.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/tim/tim1234_1567_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/ethernet/h7_dma_mr.yaml + - patches/ethernet/h7_desc.yaml + - patches/dbgmcu/h7.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml + - patches/h743_hrtim_common.yaml diff --git a/devices/stm32h755cm4.yaml b/devices/stm32h755cm4.yaml new file mode 100644 index 000000000..9d83794b1 --- /dev/null +++ b/devices/stm32h755cm4.yaml @@ -0,0 +1,434 @@ +_svd: ../svd/stm32h755cm4.svd + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ART: {} + +AXI: + _strip: AXI_ + +BDMA: + _include: + - patches/dma/bdma.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +# Applies to the H745/H747/H755/H757 +# CRYP and HASH are unavailable on the H745/H747 +CRYP: + _include: patches/cryp/merge_fields.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +DSIHOST: + _strip: DSI_ + _include: + - patches/dsi/h7-desc.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_dualcore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/h7_dual.yaml + - patches/hsem/h7_dual_cm4.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/h7_dual.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _delete: + - ICSCR + _add: + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_dualcore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + - fields/syscfg/syscfg_h747.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/h743_hrtim_common.yaml + - patches/ethernet/h7_combined_desc.yaml + - patches/flash/h7_dualcore.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h755cm7.yaml b/devices/stm32h755cm7.yaml new file mode 100644 index 000000000..d59afb778 --- /dev/null +++ b/devices/stm32h755cm7.yaml @@ -0,0 +1,434 @@ +_svd: ../svd/stm32h755cm7.svd + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ART: {} + +AXI: + _strip: AXI_ + +BDMA: + _include: + - patches/dma/bdma.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +# Applies to the H745/H747/H755/H757 +# CRYP and HASH are unavailable on the H745/H747 +CRYP: + _include: patches/cryp/merge_fields.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +DSIHOST: + _strip: DSI_ + _include: + - patches/dsi/h7-desc.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_dualcore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/h7_dual.yaml + - patches/hsem/h7_dual_cm4.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/h7_dual.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _delete: + - ICSCR + _add: + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_dualcore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + - fields/syscfg/syscfg_h747.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/h743_hrtim_common.yaml + - patches/ethernet/h7_combined_desc.yaml + - patches/flash/h7_dualcore.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h757cm4.yaml b/devices/stm32h757cm4.yaml new file mode 100644 index 000000000..8d42cca8f --- /dev/null +++ b/devices/stm32h757cm4.yaml @@ -0,0 +1,434 @@ +_svd: ../svd/stm32h757cm4.svd + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ART: {} + +AXI: + _strip: AXI_ + +BDMA: + _include: + - patches/dma/bdma.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +# Applies to the H745/H747/H755/H757 +# CRYP and HASH are unavailable on the H745/H747 +CRYP: + _include: patches/cryp/merge_fields.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +DSIHOST: + _strip: DSI_ + _include: + - patches/dsi/h7-desc.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_dualcore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/h7_dual.yaml + - patches/hsem/h7_dual_cm4.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/h7_dual.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _delete: + - ICSCR + _add: + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_dualcore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + - fields/syscfg/syscfg_h747.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/h743_hrtim_common.yaml + - patches/ethernet/h7_combined_desc.yaml + - patches/flash/h7_dualcore.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h757cm7.yaml b/devices/stm32h757cm7.yaml new file mode 100644 index 000000000..0938b5362 --- /dev/null +++ b/devices/stm32h757cm7.yaml @@ -0,0 +1,435 @@ +_svd: ../svd/stm32h757cm7.svd + +_modify: + COMP1: + groupName: COMP + Flash: + name: FLASH + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC1: + from: RAMECC2 + +_derive: + TIM4: TIM3 + TIM14: TIM13 + LPTIM3: LPTIM1 + RAMECC2: RAMECC1 + +ADC3_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC3: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[3]: + _include: collect/adc/derive_sq.yaml + +ART: {} + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA: + _include: + - patches/dma/bdma.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +# Applies to the H745/H747/H755/H757 +# CRYP and HASH are unavailable on the H745/H747 +CRYP: + _include: patches/cryp/merge_fields.yaml + +DAC: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h75x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _include: + - patches/dfsdm/h735_747_753.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +DSIHOST: + _strip: DSI_ + _include: + - patches/dsi/h7-desc.yaml + - collect/dsi/isr.yaml + +Ethernet_DMA: + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write + +Ethernet_MAC: + _include: + - patches/ethernet/mac_lpiet_3.yaml + +Ethernet_MTL: {} + +EXTI: + _include: + - patches/exti/h7_dualcore.yaml + - fields/exti/exti_h7.yaml + +FDCAN1: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _include: + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/h7_dual.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG1: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PWR: + _include: + - patches/pwr/add_step_down.yaml + - patches/pwr/h7_dual.yaml + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +RAMECC[13]: + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RAMECC3: + _include: + - collect/ramecc/derive.yaml + +RCC: + _delete: + - ICSCR + _add: + CSICFGR: + description: RCC CSI configuration register + addressOffset: 0x000C + access: read-write + fields: + CSITRIM: + description: CSI clock trimming + bitOffset: 24 + bitWidth: 6 + CSICAL: + description: CSI clock calibration + bitOffset: 0 + bitWidth: 9 + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_dualcore.yaml + - patches/rcc/h7_src_sel.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/hrtim.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/h7.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI4: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: + _include: + - patches/syscfg/h74x_pwrcr.yaml + - fields/syscfg/syscfg_h747.yaml + +TIM1: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG1: + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/h743_hrtim_common.yaml + - patches/ethernet/h7_combined_desc.yaml + - patches/flash/h7_dualcore.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml + - patches/ethernet/h7_mac.yaml diff --git a/devices/stm32h7a3.yaml b/devices/stm32h7a3.yaml new file mode 100644 index 000000000..8707b4441 --- /dev/null +++ b/devices/stm32h7a3.yaml @@ -0,0 +1,476 @@ +_svd: ../svd/stm32h7a3.svd + +_clear_fields: "*" + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + CAN_CCU: + from: ../svd/stm32h7b0.svd:CAN_CCU + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC: + from: ../svd/stm32h742.svd:RAMECC2 + +_derive: + ADC2: ADC1 + TIM4: TIM3 + TIM14: TIM13 + I2C3: I2C1 + LPTIM3: LPTIM1 + +# Fix invalid groupName +_modify: + COMP1: + groupName: COMP + OctoSPII_O_Manager: + groupName: OctoSPII_O_Manager + +_rebase: + OCTOSPI1: OCTOSPI2 + +ADC12_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC1: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA1: + _include: + - patches/dma/bdma_v2.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _include: + - fields/hdmi_cec.yaml + +COMP1: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h7_high.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM1: + _strip: DFSDM_ + _include: + - patches/dfsdm/split.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX?_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +EXTI: + _delete: + _interrupts: + - ECC + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN[12]: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _strip: FLASH_ + _modify: + WPSGN_CUR1R: + name: WPSN_CUR1R + WPSGN_PRG1R: + name: WPSN_PRG1R + WPSGN_CUR2R: + name: WPSN_CUR2R + WPSGN_PRG2R: + name: WPSN_PRG2R + ECC_FA2R: + _add: + # ECC_FA1R only. Needed for clusterization + OTP_FAIL_ECC: + description: "OTP ECC error bit\nThis bit is set to 1 when one single ECC correction or double ECC detection occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in FAIL_ECC_ADDR1 bitfield." + bitOffset: 31 + bitWidth: 1 + access: read-only + _include: + - patches/flash/h7_hi_mem.yaml + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: {} + +LPTIM1: + _strip: LPTIM_ + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _include: + - collect/dma/mdma.yaml + +OCTOSPI1: + WCCR: + _modify: + IMODE: + bitWidth: 3 + IDTR: + bitOffset: 3 + ISIZE: + bitOffset: 4 + bitWidth: 2 + _include: + - patches/octospi/h7.yaml + - fields/octospi/l5.yaml + +OctoSPII_O_Manager: {} + +OPAMP: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _delete: + _interrupts: WWDG1_RST # Doesn't exist at all on these parts + +RAMECC: + _add: + _interrupts: + RAMECC: + description: ECC diagnostic global interrupt + value: 145 + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RCC: + _strip: + - RCC_ + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_highmemory.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _include: + - patches/rng/h735.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _strip: SAI_ + _add: + _interrupts: + SAI1: + description: SAI1 global interrupt + value: 87 + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _delete: [SDMMC_VER, SDMMC_ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: {} + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM8: + _modify: + CRR6: + name: CCR6 + displayName: CCR6 + +TIM[18]: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM[8]: + _include: collect/tim/tim8_derive.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART2: + _add: + _interrupts: + USART2: + description: USART2 global interrupt + value: 38 +USART3: + _add: + _interrupts: + USART3: + description: USART3 global interrupt + value: 39 +USART6: + _add: + _interrupts: + USART6: + description: USART6 global interrupt + value: 71 + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/h7_common_highmemory.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml diff --git a/devices/stm32h7b0.yaml b/devices/stm32h7b0.yaml new file mode 100644 index 000000000..9e0b43109 --- /dev/null +++ b/devices/stm32h7b0.yaml @@ -0,0 +1,472 @@ +_svd: ../svd/stm32h7b0.svd + +_clear_fields: "*" + +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC: + from: ../svd/stm32h742.svd:RAMECC2 + +_derive: + ADC2: ADC1 + TIM4: TIM3 + TIM14: TIM13 + I2C3: I2C1 + LPTIM3: LPTIM1 + +# Fix invalid groupName +_modify: + COMP1: + groupName: COMP + OctoSPII_O_Manager: + groupName: OctoSPII_O_Manager + +_rebase: + OCTOSPI1: OCTOSPI2 + +ADC12_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC1: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA2: + _strip: BDMA_ + _include: + - patches/dma/bdma_v2.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _strip: CEC_ + _include: + - fields/hdmi_cec.yaml + +COMP1: + _strip: COMP1_ + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +# Applies to the H7A3/H7B3 +# CRYP and HASH are unavailable on the H7A3 +CRYP: + _include: patches/cryp/merge_fields.yaml + +DAC1: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h7_high.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM1: + _strip: DFSDM_ + _include: + - patches/dfsdm/split.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _strip: DMA2D_ + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX?_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _strip: DMAMUX?_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +EXTI: + _delete: + _interrupts: + - ECC + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN[12]: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _strip: FLASH_ + _modify: + WPSGN_CUR1R: + name: WPSN_CUR1R + WPSGN_PRG1R: + name: WPSN_PRG1R + WPSGN_CUR2R: + name: WPSN_CUR2R + WPSGN_PRG2R: + name: WPSN_PRG2R + ECC_FA2R: + _add: + # ECC_FA1R only. Needed for clusterization + OTP_FAIL_ECC: + description: "OTP ECC error bit\nThis bit is set to 1 when one single ECC correction or double ECC detection occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in FAIL_ECC_ADDR1 bitfield." + bitOffset: 31 + bitWidth: 1 + access: read-only + _include: + - patches/flash/h7_hi_mem.yaml + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _strip: FMC_ + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: + _strip: JPEG_ + +LPTIM1: + _strip: LPTIM_ + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OCTOSPI1: + WCCR: + _modify: + IMODE: + bitWidth: 3 + IDTR: + bitOffset: 3 + ISIZE: + bitOffset: 4 + bitWidth: 2 + _include: + - patches/octospi/h7.yaml + - fields/octospi/l5.yaml + +OctoSPII_O_Manager: {} + +OPAMP: {} + +OTFDEC1: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _delete: + _interrupts: WWDG1_RST # Doesn't exist at all on these parts + +RAMECC: + _add: + _interrupts: + RAMECC: + description: ECC diagnostic global interrupt + value: 145 + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RCC: + _strip: + - RCC_ + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_highmemory.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _strip: RNG_ + _include: + - patches/rng/h735.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _delete: [SDMMC_VER, SDMMC_ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: {} + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM8: + _modify: + CRR6: + name: CCR6 + displayName: CCR6 + +TIM[18]: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM[8]: + _include: collect/tim/tim8_derive.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/h7_common_highmemory.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml diff --git a/devices/stm32h7b3.yaml b/devices/stm32h7b3.yaml index cd3002642..1f1669ec1 100644 --- a/devices/stm32h7b3.yaml +++ b/devices/stm32h7b3.yaml @@ -1,86 +1,498 @@ _svd: ../svd/stm32h7b3.svd -# Applies to the H7A3/H7B3 -# CRYP and HASH are unavailable on the H7A3 +_clear_fields: "*" -# Merge the hundreds of individual bit fields into single fields for the -# crypt key/iv registers. -CRYP: - "K[0123][LR]R": - _merge: - - "b*" - "IV[01][LR]R": - _merge: - - "IV*" +# TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit +_copy: + CAN_CCU: + from: ../svd/stm32h7b0.svd:CAN_CCU + TIM3: + from: TIM2 + TIM12: + from: TIM2 + TIM13: + from: TIM2 + RAMECC: + from: ../svd/stm32h742.svd:RAMECC2 + +_derive: + ADC2: ADC1 + TIM4: TIM3 + TIM14: TIM13 + I2C3: I2C1 + LPTIM3: LPTIM1 # Fix invalid groupName _modify: + COMP1: + groupName: COMP OctoSPII_O_Manager: groupName: OctoSPII_O_Manager +_rebase: + OCTOSPI1: OCTOSPI2 + +ADC12_Common: + _include: fields/adc/adc_v3_common_h7.yaml + +ADC1: + _include: + - patches/adc/jdata.yaml + - patches/adc/offset.yaml + - patches/adc/h7.yaml + - patches/adc/h7_2.yaml + - patches/adc/h7_boost_rev_v.yaml + - fields/adc/adc_h7_revision_v.yaml + - fields/adc/adc_v3_h7.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 19] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AXI: + _strip: AXI_ + _include: + - fields/axi/axi_v1.yaml + +BDMA1: + _strip: BDMA_ + _include: + - patches/dma/bdma_v2.yaml + - fields/dma/bdma.yaml + - collect/dma/bdma.yaml + +CAN_CCU: {} + +CEC: + _strip: CEC_ + _include: + - fields/hdmi_cec.yaml + +COMP1: + _strip: COMP1_ + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/h7_addr_fix.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +# Applies to the H7A3/H7B3 +# CRYP and HASH are unavailable on the H7A3 +CRYP: + _include: patches/cryp/merge_fields.yaml + +DAC1: + _include: + - patches/dac/tsel_4bit.yaml + - fields/dac/h7_high.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM1: + _strip: DFSDM_ + _include: + - patches/dfsdm/split.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DELAY_Block_SDMMC1: {} + +DMA1: + _include: + - patches/dma/fcr_wo.yaml + - patches/dma/h7_dmacr.yaml + - fields/dma/dma_v3.yaml + - collect/dma/st.yaml + +DMA2D: + _strip: DMA2D_ + _include: + - patches/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +DMAMUX1: + _strip: DMAMUX?_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux1_v1.yaml + - collect/dma/h7_dmamux.yaml + +DMAMUX2: + _strip: DMAMUX?_ + _include: + - patches/dma/dmamux_split.yaml + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux2_v1.yaml + - collect/dma/h7_dmamux.yaml + +EXTI: + _delete: + _interrupts: + - ECC + _include: + - patches/exti/h7_singlecore.yaml + - fields/exti/exti_h7.yaml + +FDCAN[12]: + _strip: FDCAN_ + _include: + - patches/fdcan/fdcan_h7.yaml + +FLASH: + _strip: FLASH_ + _modify: + WPSGN_CUR1R: + name: WPSN_CUR1R + WPSGN_PRG1R: + name: WPSN_PRG1R + WPSGN_CUR2R: + name: WPSN_CUR2R + WPSGN_PRG2R: + name: WPSN_PRG2R + ECC_FA2R: + _add: + # ECC_FA1R only. Needed for clusterization + OTP_FAIL_ECC: + description: "OTP ECC error bit\nThis bit is set to 1 when one single ECC correction or double ECC detection occurred during the last successful read operation from the read-only/ OTP area. The address of the ECC error is available in FAIL_ECC_ADDR1 bitfield." + bitOffset: 31 + bitWidth: 1 + access: read-only + _include: + - patches/flash/h7_hi_mem.yaml + - patches/flash/flash_dual_bank.yaml + - collect/flash/bank.yaml + +FMC: + _strip: FMC_ + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + - collect/fsmc/sd_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/add_r_suffix.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +HSEM: + _strip: HSEM_ + _include: + - patches/hsem/isem.yaml + - patches/hsem/h7_single.yaml + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - patches/i2c/merge_CR2_SADDx_fields.yaml + - fields/i2c/v2.yaml + +IWDG: + _strip: IWDG_ + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +JPEG: + _strip: JPEG_ + +LPTIM1: + _strip: LPTIM_ + _include: + - fields/lptim/v1b.yaml + +LPUART1: + _include: + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - patches/ltdc/ltdc.yaml + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +MDMA: + _strip: MDMA_ + _include: + - collect/dma/mdma.yaml + +OCTOSPI1: + WCCR: + _modify: + IMODE: + bitWidth: 3 + IDTR: + bitOffset: 3 + ISIZE: + bitOffset: 4 + bitWidth: 2 + _include: + - patches/octospi/h7.yaml + - fields/octospi/l5.yaml + +OctoSPII_O_Manager: {} + +OPAMP: {} + +OTFDEC1: {} + +OTG1_HS_*: + _strip: OTG_HS_ + +OTG1_HS_DEVICE: + _include: + - patches/usb_otg/hsdevice.yaml + - collect/usb_otg/hs_device.yaml +OTG1_HS_GLOBAL: + _include: + - patches/usb_otg/hsglobal2.yaml + - patches/usb_otg/gotgctl.yaml + - collect/usb_otg/hs_global.yaml +OTG1_HS_HOST: + _include: + - patches/usb_otg/hshost_address_12_15.yaml + - collect/usb_otg/hs_host.yaml +OTG1_HS_PWRCLK: {} + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _delete: + _interrupts: WWDG1_RST # Doesn't exist at all on these parts + +RAMECC: + _add: + _interrupts: + RAMECC: + description: ECC diagnostic global interrupt + value: 145 + _include: + - patches/ramecc/h7.yaml + - collect/ramecc/m.yaml + +RCC: + _strip: + - RCC_ + _include: + - patches/rcc/h7_usb1otghs.yaml + - patches/rcc/h7_common_highmemory.yaml + - fields/rcc/v3/h7.yaml + - fields/rcc/v3/h7_revision_v.yaml + +RNG: + _strip: RNG_ + _include: + - patches/rng/h735.yaml + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _strip: SAI_ + _add: + _interrupts: + SAI1: + description: SAI1 global interrupt + value: 87 + _include: + - patches/sai/h7.yaml + - patches/sai/h7_mcken.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _delete: [SDMMC_VER, SDMMC_ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPDIFRX: {} + +SPI1: + _include: + - patches/spi/rxtxdr.yaml + - patches/spi/h7_2.yaml + - fields/spi/spi_v3.yaml + +SWPMI: {} + +SYSCFG: {} + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM8: + _modify: + CRR6: + name: CCR6 + displayName: CCR6 + +TIM[18]: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/oc4m_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - patches/tim/rep_16b.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM[8]: + _include: collect/tim/tim8_derive.yaml + +TIM2: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM12: + _include: + - patches/tim/v2/tim12_from_tim2.yaml + - patches/tim/ts.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _include: + - patches/tim/v2/tim13_from_tim2.yaml + - patches/tim/icpsc.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/v2/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART2: + _add: + _interrupts: + USART2: + description: USART2 global interrupt + value: 38 +USART3: + _add: + _interrupts: + USART3: + description: USART3 global interrupt + value: 39 +USART6: + _add: + _interrupts: + USART6: + description: USART6 global interrupt + value: 71 + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - patches/usart/tcbgtc.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/wwdg/h7.yaml + - fields/wwdg/wwdg_v2.yaml + _include: - - common_patches/h7_common_highmemory.yaml - - common_patches/dma_fcr_wo.yaml - - common_patches/dma/bdma_v2.yaml - - common_patches/dma/dma_v3.yaml - - common_patches/fsmc/fsmc_sdram_cluster.yaml - - common_patches/h7_exti_singlecore.yaml - - common_patches/h7_dbgmcu.yaml - - common_patches/h7_dmacr.yaml - - common_patches/h7_dmamux.yaml - - common_patches/dma/dma2d_v2.yaml - - common_patches/h7_adc.yaml - - common_patches/h7_dsi.yaml - - common_patches/h7_adc_boost_rev_v.yaml - - common_patches/h7_hsicfgr_csicfgr_rev_v.yaml - - common_patches/h7_sai.yaml - - common_patches/h7_spdifrx.yaml - - common_patches/h7_otg.yaml - - common_patches/flash/flash_dual_bank.yaml - - common_patches/ltdc/ltdc.yaml - - common_patches/merge_I2C_CR2_SADDx_fields.yaml - - common_patches/merge_USART_CR1_DEATx_fields.yaml - - common_patches/merge_USART_CR1_DEDTx_fields.yaml - - common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - common_patches/merge_USART_CR2_ADDx_fields.yaml - - common_patches/rename_USART_CR2_DATAINV_field.yaml - - common_patches/merge_USART_BRR_fields.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/tim/tim_o24ce.yaml - - ../peripherals/adc/adc_v3_h7.yaml - - ../peripherals/adc/adc_v3_common_h7.yaml - - ../peripherals/adc/adc_h7_revision_v.yaml - - ../peripherals/axi/axi_v1.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dma/bdma.yaml - - ../peripherals/dma/dma_v3.yaml - #- ../peripherals/dma/dmamux_v1.yaml - - ../peripherals/dma/dma2d_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/rcc/rcc_h7.yaml - - ../peripherals/rcc/rcc_h7_revision_v.yaml - - ../peripherals/rng/rng_v1.yaml - - ../peripherals/rng/rng_v1_ced.yaml - - ../peripherals/spi/spi_v3.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_gp1.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - common_patches/tim/tim_h7.yaml - - ../peripherals/tim/tim_h7.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti_h7.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/tim/tim1234_1567_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/h7_common_highmemory.yaml + - patches/h7_spdifrx.yaml + - patches/gpio/h7_ijk.yaml + - patches/hrtim/h7.yaml + - fields/hrtim/hrtim.yaml + - fields/hrtim/common_h7.yaml + - collect/hrtim/h7.yaml + - patches/tim/group.yaml diff --git a/devices/stm32h7r.yaml b/devices/stm32h7r.yaml new file mode 100644 index 000000000..43ec5d70c --- /dev/null +++ b/devices/stm32h7r.yaml @@ -0,0 +1,329 @@ +_svd: ../svd/stm32h7r.svd + +_clear_fields: "*" + +_derive: + LPTIM2: LPTIM1 + LPTIM3: LPTIM1 + LPTIM5: LPTIM4 + + TIM3: TIM2 + TIM4: TIM2 + TIM5: TIM2 + TIM7: TIM6 + TIM12: TIM9 + TIM14: TIM13 + TIM17: TIM16 + +_modify: + FDCAN1: + groupName: FDCAN + SPI1: + groupName: SPI + +ADC12_common: + _strip: ADC_ + +ADC1: + _strip: ADC_ + CFGR: + _merge: EXTSEL* + +ADF: + _strip: ADF_ + +CEC: + _strip: CEC_ + +CORDIC: + _strip: CORDIC_ + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DBGMCU: + _strip: DBGMCU_ + +DCMIPP: + _strip: DCMIPP_ + +DLYB1: + _strip: DLYB_ + +DMA2D: + _strip: DMA2D_ + _include: + - collect/dma/dma2d_clut.yaml + +DTS: + _strip: DTS_ + +ETH: + _strip: ETH_ + +EXTI: + _strip: EXTI_ + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +FMC: + _strip: FMC_ + PCR: + _merge: TAR* + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GFXMMU: + _strip: GFXMMU_ + _include: + - collect/gfxmmu/lut.yaml + +GFXTIM: + _strip: GFXTIM_ + +GPDMA: + _strip: GPDMA_ + _include: + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABC]: + _strip: GPIO?_ + _include: + - fields/gpio/v3/common.yaml + - fields/gpio/v3/af0-15.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2r_derive.yaml + +HASH: + _strip: HASH_ + _include: + - collect/hash/v3.yaml + +HPDMA: + _strip: HPDMA_ + _include: + - collect/dma/hpdma.yaml + +I2C1_I3C1: + _strip: I2C_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + _include: patches/16bit_with_mask.yaml + +JPEG: + _strip: JPEG_ + _include: + - collect/jpeg/ram_h7rs.yaml + +LPTIM1: + _strip: LPTIM1_ + +LPTIM4: + _strip: LPTIM4_ + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +LTDC: + _strip: LTDC_ + _include: + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDIOS: + _strip: MDIOS_ + +OTG_HS: + _strip: OTG_ + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + +RAMCFG: + _strip: RAMECC_ + +RCC: + _strip: RCC_ + _include: + - patches/rcc/h7+.yaml + - fields/rcc/v3/h7rs.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/fsdef-rw.yaml + +SBS: + _strip: SBS_ + _include: + - patches/sbs/h7+.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - collect/sdmmc/fifo.yaml + +SPDIFRX: + _strip: SPDIFRX_ + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + - fields/spi/spi_v3_i2s.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _strip: TIM2_ + CNT: + _modify: + UIFCPY_CNT: + name: UIFCPY + CNT: + bitWidth: 32 + _include: + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _strip: TIM6_ + _include: + - fields/tim/v3/tim6.yaml + +TIM9: + _strip: TIM9_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _strip: TIM13_ + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v3/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _strip: TIM15_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _strip: TIM16_ + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +UCPD: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +XSPI1: + _strip: XSPI_ + +XSPIM1: + _strip: XSPIM_ + +_include: + - patches/gpio/h7_mnop.yaml diff --git a/devices/stm32h7s.yaml b/devices/stm32h7s.yaml new file mode 100644 index 000000000..a9c01ec60 --- /dev/null +++ b/devices/stm32h7s.yaml @@ -0,0 +1,353 @@ +_svd: ../svd/stm32h7s.svd + +_clear_fields: "*" + +_derive: + LPTIM2: LPTIM1 + LPTIM3: LPTIM1 + LPTIM5: LPTIM4 + + TIM3: TIM2 + TIM4: TIM2 + TIM5: TIM2 + TIM7: TIM6 + TIM12: TIM9 + TIM14: TIM13 + TIM17: TIM16 + +_modify: + FDCAN1: + groupName: FDCAN + SPI1: + groupName: SPI + +ADC12_common: + _strip: ADC_ + +ADC1: + _strip: ADC_ + CFGR: + _merge: EXTSEL* + +ADF: + _strip: ADF_ + +CEC: + _strip: CEC_ + +CORDIC: + _strip: CORDIC_ + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +CRYP: + _strip: CRYP_ + _cluster: + KEY%s: + K?LR: {} + K?RR: {} + INIT%s: + IV?LR: {} + IV?RR: {} + + _array: + CSGCMCCM?R: {} + CSGCM?R: {} + +DBGMCU: + _strip: DBGMCU_ + +DCMIPP: + _strip: DCMIPP_ + +DLYB1: + _strip: DLYB_ + +DMA2D: + _strip: DMA2D_ + _include: + - collect/dma/dma2d_clut.yaml + +DTS: + _strip: DTS_ + +ETH: + _strip: ETH_ + +EXTI: + _strip: EXTI_ + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +FMC: + _strip: FMC_ + PCR: + _merge: TAR* + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - fields/fsmc/sd.yaml + - collect/fsmc/sram.yaml + - collect/fsmc/sd.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GFXMMU: + _strip: GFXMMU_ + _include: + - collect/gfxmmu/lut.yaml + +GFXTIM: + _strip: GFXTIM_ + +GPDMA: + _strip: GPDMA_ + _include: + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABC]: + _strip: GPIO?_ + _include: + - fields/gpio/v3/common.yaml + - fields/gpio/v3/af0-15.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2r_derive.yaml + +HASH: + _strip: HASH_ + _include: + - collect/hash/v3.yaml + +HPDMA: + _strip: HPDMA_ + _include: + - collect/dma/hpdma.yaml + +I2C1_I3C1: + _strip: I2C_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + _include: patches/16bit_with_mask.yaml + +JPEG: + _strip: JPEG_ + _include: + - collect/jpeg/ram_h7rs.yaml + +LPTIM1: + _strip: LPTIM1_ + +LPTIM4: + _strip: LPTIM4_ + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +LTDC: + _strip: LTDC_ + _include: + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MCE1: + _strip: MCE_ + +MDIOS: + _strip: MDIOS_ + +OTG_HS: + _strip: OTG_ + +PKA: + _strip: PKA_ + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + +RAMCFG: + _strip: RAMECC_ + +RCC: + _strip: RCC_ + _include: + - patches/rcc/h7+.yaml + - fields/rcc/v3/h7rs.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAES: + _strip: SAES_ + +SAI1: + _strip: SAI_ + _include: + - patches/sai/fsdef-rw.yaml + +SBS: + _strip: SBS_ + _include: + - patches/sbs/h7+.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - collect/sdmmc/fifo.yaml + +SPDIFRX: + _strip: SPDIFRX_ + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + - fields/spi/spi_v3_i2s.yaml + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + _include: + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _strip: TIM2_ + CNT: + _modify: + UIFCPY_CNT: + name: UIFCPY + CNT: + bitWidth: 32 + _include: + - patches/tim/tim1_mms_ts_sms.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _strip: TIM6_ + _include: + - fields/tim/v3/tim6.yaml + +TIM9: + _strip: TIM9_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim9.yaml + - collect/tim/ccr.yaml + +TIM13: + _strip: TIM13_ + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v3/tim13.yaml + - collect/tim/ccr.yaml + +TIM15: + _strip: TIM15_ + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _strip: TIM16_ + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +UCPD: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +XSPI1: + _strip: XSPI_ + +XSPIM1: + _strip: XSPIM_ + +_include: + - patches/gpio/h7_mnop.yaml + - collect/mce/v1.yaml diff --git a/devices/stm32l0x0.yaml b/devices/stm32l0x0.yaml new file mode 100644 index 000000000..36d1f8319 --- /dev/null +++ b/devices/stm32l0x0.yaml @@ -0,0 +1,200 @@ +_svd: ../svd/stm32l0x0.svd + +_delete: + - MPU + - STK + - SCB + +_modify: + Flash: + name: FLASH + Firewall: + name: FW + +ADC: + _include: + - fields/adc/adc_l0.yaml + - collect/adc/f0_l0.yaml + CFGR1: + _modify: + AUTDLY: + name: WAIT + SMPR: + _modify: + SMPR: + name: SMP + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +DBG: + _include: + - fields/dbg/dbg_l0.yaml + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml + +FLASH: + _include: + - fields/flash/flash_l0.yaml + +FW: + _strip: FIREWALL_ + _include: + - fields/fw/fw_l0_l4.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +PWR: + _include: + - fields/pwr/pwr_l0.yaml + CR: + # LPDS only exists in the L0x0 family + LPDS: + MAIN_MODE: [0, Voltage regulator in Main mode during Deepsleep mode (Stop mode)] + LOW_POWER_MODE: [1, Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode (Stop mode)] + +RCC: + _modify: + CICR: + access: write-only + CIER: + access: read-write + CR: + _modify: + CSSLSEON: + name: CSSHSEON + CCIPR: + _merge: + - LPTIM1SEL* + - I2C3SEL* + - I2C1SEL* + - LPUART1SEL* + - USART2SEL* + - USART1SEL* + CSR: + _modify: + LPWRSTF: + name: LPWRRSTF + _delete: + - LSIIWDGLP + AHBSMENR: + _delete: + - CRYPTSMEN + APB1ENR: + _delete: + - TIM3EN + _include: + - fields/rcc/rcc_l0_l1_common.yaml + - fields/rcc/rcc_l0x0.yaml + +RTC: + _include: + - patches/rtc/l0.yaml + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/l0.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/dff.yaml + SR: + _modify: + TIFRFE: + name: FRE + +SYSCFG: + _include: + - fields/syscfg/syscfg_l0x0.yaml + +TIM2: + _modify: + CCR?: + size: 16 + _include: + - patches/tim/size16b.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim2_l0.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM2[12]: + _include: + - patches/tim/size16b.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/tim2x.yaml + - fields/tim/ccr.yaml + - fields/tim/v1/ccm.yaml + - collect/tim/ccr.yaml + +TIM21: + _include: fields/tim/tim21.yaml + +TIM22: + _include: collect/tim/tim22_derive.yaml + +USART2: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/nvic/l0_prio_bits.yaml + - fields/nvic/nvic_v1.yaml + - patches/tim/group.yaml diff --git a/devices/stm32l0x1.yaml b/devices/stm32l0x1.yaml index 082f6ca9e..641a39f86 100644 --- a/devices/stm32l0x1.yaml +++ b/devices/stm32l0x1.yaml @@ -1,12 +1,22 @@ _svd: ../svd/stm32l0x1.svd +_delete: + - MPU + - STK + - SCB + _modify: Flash: name: FLASH SYSCFG_COMP: name: SYSCFG + Firewall: + name: FW ADC: + _include: + - fields/adc/adc_l0.yaml + - collect/adc/f0_l0.yaml CFGR1: _modify: AUTDLY: @@ -18,46 +28,90 @@ ADC: CCR: # VLCDEN is only available on l0x1 and l0x3 VLCDEN: - Disabled: [0, "VLCD reading circuitry disabled"] - Enabled: [1, "VLCD reading circuitry enabled"] + Disabled: [0, VLCD reading circuitry disabled] + Enabled: [1, VLCD reading circuitry enabled] + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v1.yaml CRC: - POL: - _modify: - Polynomialcoefficients: - name: POL + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml DBG: - _modify: - DBG_APB2_FZ: - name: APB2_FZ + _include: + - fields/dbg/dbg_l0.yaml + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml FLASH: - _modify: - OBR: - name: OPTR - ACR: - _modify: - DESAB_BUF: - name: DISAB_BUF - PECR: - _modify: - FTDW: - name: FIX - OPTR: - _modify: - SPRMOD: - name: WPRMOD - RDPRT: - name: RDPROT + _include: + - patches/flash/l0.yaml + - fields/flash/flash_l0.yaml -"SPI*,I2S*": - SR: - _modify: - TIFRFE: - name: FRE +FW: + _strip: FIREWALL_ + _include: + - fields/fw/fw_l0_l4.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +PWR: + _include: + - fields/pwr/pwr_l0.yaml + CR: + # LPDS only exists in the L0x1 family + LPDS: + MAIN_MODE: [0, Voltage regulator in Main mode during Deepsleep mode (Stop mode)] + LOW_POWER_MODE: [1, Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode (Stop mode)] RCC: + _modify: + CICR: + access: write-only + CIER: + access: read-write CR: _modify: CSSLSEON: @@ -68,12 +122,12 @@ RCC: name: I2C3RST CCIPR: _merge: - - "LPTIM1SEL*" - - "I2C3SEL*" - - "I2C1SEL*" - - "LPUART1SEL*" - - "USART2SEL*" - - "USART1SEL*" + - LPTIM1SEL* + - I2C3SEL* + - I2C1SEL* + - LPUART1SEL* + - USART2SEL* + - USART1SEL* CSR: _modify: LPWRSTF: @@ -88,78 +142,84 @@ RCC: _modify: TIM3EN: bitOffset: 1 + _include: + - fields/rcc/rcc_l0_l1_common.yaml + - fields/rcc/rcc_l0.yaml -WWDG: +RTC: + _include: + - patches/rtc/l0.yaml + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/l0.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/dff.yaml + SR: + _modify: + TIFRFE: + name: FRE + +SYSCFG: + _include: + - patches/syscfg/l0_cfgr.yaml + - fields/syscfg/syscfg_l0.yaml + +TIM2: _modify: - WWDG_CR: - name: CR - WWDG_CFR: - name: CFR - WWDG_SR: - name: SR + CCR?: + size: 16 + _include: + - patches/tim/size16b.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim2_l0.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml -PWR: - CR: - # LPDS only exists in the L0x1 family - LPDS: - MAIN_MODE: [0, "Voltage regulator in Main mode during Deepsleep mode (Stop mode)"] - LOW_POWER_MODE: [1, "Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode (Stop mode)"] +TIM6: + _include: + - patches/tim/size16b.yaml + - fields/tim/v1/tim6.yaml + +TIM2[12]: + _include: + - patches/tim/size16b.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/tim2x.yaml + - fields/tim/ccr.yaml + - fields/tim/v1/ccm.yaml + - collect/tim/ccr.yaml + +TIM21: + _include: fields/tim/tim21.yaml + +TIM22: + _include: collect/tim/tim22_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/cryp/l0_aes.yaml - - ./common_patches/l0_flash.yaml - - ./common_patches/l0_firewall.yaml - - ./common_patches/l0_pwr_mode.yaml - - ./common_patches/l0_pwr_wakeup.yaml - - ./common_patches/l0_rtc.yaml - - ./common_patches/l0_tim.yaml - - ./common_patches/l0_syscfg_cfgr.yaml - - ./common_patches/l0_nvic_prio_bits.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_LPUART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/remove_l0_mpu.yaml - - ./common_patches/remove_l0_scb.yaml - - ./common_patches/remove_l0_stk.yaml - - ../peripherals/adc/adc_l0.yaml - - ../peripherals/aes/aes_l0.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dbg/dbg_l0.yaml - - ../peripherals/dma/dma_v1_with_remapping.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/flash/flash_l0.yaml - - ../peripherals/fw/fw_l0.yaml - - ../peripherals/gpio/gpio_l0.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/nvic/nvic_v1.yaml - - ../peripherals/pwr/pwr_l0.yaml - - ../peripherals/rcc/rcc_l0_l1_common.yaml - - ../peripherals/rcc/rcc_l0.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_l0.yaml - - ../peripherals/spi/spi_l0.yaml - - ../peripherals/syscfg/syscfg_l0.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/tim/tim_l0.yaml - - ../peripherals/tim/tim21.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/usart/lpuart_v2A.yaml - - ../peripherals/usart/usart_v2B1.yaml - - ../peripherals/wwdg/wwdg.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/dma/dma_v1.yaml + - patches/nvic/l0_prio_bits.yaml + - fields/nvic/nvic_v1.yaml + - patches/tim/group.yaml diff --git a/devices/stm32l0x2.yaml b/devices/stm32l0x2.yaml index 036e8a77e..6c88a80bf 100644 --- a/devices/stm32l0x2.yaml +++ b/devices/stm32l0x2.yaml @@ -8,15 +8,18 @@ _modify: name: DBG Flash: name: FLASH - Firewall: - name: FW SYSCFG_COMP: name: SYSCFG + Firewall: + name: FW _delete: - USB_SRAM ADC: + _include: + - fields/adc/adc_l0.yaml + - collect/adc/f0_l0.yaml CFGR1: _modify: AUTDLY: @@ -26,58 +29,142 @@ ADC: SMPR: name: SMP +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v1.yaml + CRC: - POL: - _modify: - Polynomialcoefficients: - name: POL + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/l0.yaml + - collect/dac/v2.yaml + +DBG: + _include: + - fields/dbg/dbg_l0.yaml + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml FLASH: - _modify: - OBR: - name: OPTR - ACR: - _modify: - DESAB_BUF: - name: DISAB_BUF - PECR: - _modify: - FTDW: - name: FIX - OPTR: - _modify: - SPRMOD: - name: WPRMOD - RDPRT: - name: RDPROT + _include: + - patches/flash/l0.yaml + - fields/flash/flash_l0.yaml -"SPI*,I2S*": - SR: - _modify: - TIFRFE: - name: FRE +FW: + _strip: FIREWALL_ + _include: + - fields/fw/fw_l0_l4.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +MPU: + _strip: MPU_ + +PWR: + _include: + - fields/pwr/pwr_l0.yaml RCC: + _modify: + CICR: + access: write-only + CIER: + access: read-write + CR: _modify: CSSLSEON: name: CSSHSEON CCIPR: _merge: - - "LPTIM1SEL*" - - "I2C1SEL*" - - "LPUART1SEL*" - - "USART2SEL*" - - "USART1SEL*" + - LPTIM1SEL* + - I2C1SEL* + - LPUART1SEL* + - USART2SEL* + - USART1SEL* CSR: _modify: LPWRSTF: name: LPWRRSTF + RMVF: + bitOffset: 23 + APB2RSTR: _modify: TM12RST: name: TIM22RST + _include: + - fields/rcc/rcc_l0_l1_common.yaml + - fields/rcc/rcc_l0.yaml + +RTC: + _include: + - patches/rtc/l0.yaml + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/l0.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/dff.yaml + SR: + _modify: + TIFRFE: + name: FRE + SYSCFG: CFGR3: _add: @@ -85,73 +172,70 @@ SYSCFG: description: VREFINT reference for HSI48 oscillator enable bit bitOffset: 13 bitWidth: 1 + _include: + - patches/syscfg/l0_cfgr.yaml + - fields/syscfg/syscfg_l0.yaml -PWR: - CR: - _add: - LPSDSR: - description: Low-power deepsleep/Sleep/Low-power run - bitOffset: 0 - bitWidth: 1 +TIM2: + _modify: + CCR?: + size: 16 + _include: + - patches/tim/size16b.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim2_l0.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/size16b.yaml + - fields/tim/v1/tim6.yaml + +TIM2[12]: + _include: + - patches/tim/size16b.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/tim2x.yaml + - fields/tim/ccr.yaml + - fields/tim/v1/ccm.yaml + - collect/tim/ccr.yaml + +TIM21: + _include: fields/tim/tim21.yaml + +TIM22: + _include: collect/tim/tim22_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _include: + - patches/usb/rename_EPxR_EPTYPE_field.yaml + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/cryp/l0_aes.yaml - - ./common_patches/l0_flash.yaml - - ./common_patches/l0_firewall.yaml - - ./common_patches/l0_pwr_wakeup.yaml - - ./common_patches/l0_rtc.yaml - - ./common_patches/l0_tim.yaml - - ./common_patches/l0_syscfg_cfgr.yaml - - ./common_patches/l0_nvic_prio_bits.yaml - - ./common_patches/tsc/tsc.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_LPUART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml - - ./common_patches/unprefix_USB_registers.yaml - - ./common_patches/rename_USB_EPxR_EPTYPE_field.yaml - - ../peripherals/adc/adc_l0.yaml - - ../peripherals/aes/aes_l0.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dbg/dbg_l0.yaml - - ../peripherals/dac/dac_common_1ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/dma/dma_v1_with_remapping.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/flash/flash_l0.yaml - - ../peripherals/fw/fw_l0.yaml - - ../peripherals/gpio/gpio_l0.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/pwr/pwr_l0.yaml - - ../peripherals/rcc/rcc_l0_l1_common.yaml - - ../peripherals/rcc/rcc_l0.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_l0.yaml - - ../peripherals/spi/spi_l0.yaml - - ../peripherals/syscfg/syscfg_l0.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/tim/tim_l0.yaml - - ../peripherals/tim/tim21.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/usart/lpuart_v2A.yaml - - ../peripherals/usart/usart_v2B1.yaml - - ../peripherals/usb/usb_with_LPM.yaml - - ../peripherals/wwdg/wwdg.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/tim/tim2345_16bit_l.yaml - - common_patches/dma/dma_v1.yaml + - patches/nvic/l0_prio_bits.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32l0x3.yaml b/devices/stm32l0x3.yaml index 584311807..db69a2e2e 100644 --- a/devices/stm32l0x3.yaml +++ b/devices/stm32l0x3.yaml @@ -8,15 +8,18 @@ _modify: name: DBG Flash: name: FLASH - Firewall: - name: FW SYSCFG_COMP: name: SYSCFG + Firewall: + name: FW _delete: - USB_SRAM ADC: + _include: + - fields/adc/adc_l0.yaml + - collect/adc/f0_l0.yaml CFGR1: _modify: AUTDLY: @@ -32,62 +35,157 @@ ADC: VLCDEN: bitOffset: 24 bitWidth: 1 - description: "VLCD reading circuitry enable" + description: VLCD reading circuitry enable VLCDEN: - Disabled: [0, "VLCD reading circuitry disabled"] - Enabled: [1, "VLCD reading circuitry enabled"] + Disabled: [0, VLCD reading circuitry disabled] + Enabled: [1, VLCD reading circuitry enabled] + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v1.yaml CRC: - POL: - _modify: - Polynomialcoefficients: - name: POL + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/l0.yaml + - collect/dac/v2.yaml + +DBG: + _include: + - fields/dbg/dbg_l0.yaml + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - fields/exti/common.yaml FLASH: - _modify: - OBR: - name: OPTR - ACR: - _modify: - DESAB_BUF: - name: DISAB_BUF - PECR: - _modify: - FTDW: - name: FIX - OPTR: - _modify: - SPRMOD: - name: WPRMOD - RDPRT: - name: RDPROT + _include: + - patches/flash/l0.yaml + - fields/flash/flash_l0.yaml -"SPI*,I2S*": - SR: - _modify: - TIFRFE: - name: FRE +FW: + _strip: FIREWALL_ + _include: + - fields/fw/fw_l0_l4.yaml + +GPIO[AB]: + _include: + - fields/gpio/gpio_g0_l0.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_48.yaml + +LPTIM: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +MPU: + _strip: MPU_ + +PWR: + _include: + - fields/pwr/pwr_l0.yaml RCC: + _modify: + CICR: + access: write-only + CIER: + access: read-write CR: _modify: CSSLSEON: name: CSSHSEON CCIPR: _merge: - - "LPTIM1SEL*" - - "I2C1SEL*" - - "LPUART1SEL*" - - "USART2SEL*" - - "USART1SEL*" + - LPTIM1SEL* + - I2C1SEL* + - LPUART1SEL* + - USART2SEL* + - USART1SEL* CSR: _modify: LPWRSTF: name: LPWRRSTF + RMVF: + bitOffset: 23 + _add: + FWRSTF: + description: Firewall reset flag + bitOffset: 24 + bitWidth: 1 APB2RSTR: _modify: TM12RST: name: TIM22RST + _include: + - fields/rcc/rcc_l0_l1_common.yaml + - fields/rcc/rcc_l0.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/l0.yaml + - patches/rtc/alarm.yaml + - fields/rtc/v2/common.yaml + - fields/rtc/v2/l0.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/dff.yaml + SR: + _modify: + TIFRFE: + name: FRE SYSCFG: CFGR3: @@ -96,73 +194,70 @@ SYSCFG: description: VREFINT reference for HSI48 oscillator enable bit bitOffset: 13 bitWidth: 1 + _include: + - patches/syscfg/l0_cfgr.yaml + - fields/syscfg/syscfg_l0.yaml -PWR: - CR: - _add: - LPSDSR: - description: Low-power deepsleep/Sleep/Low-power run - bitOffset: 0 - bitWidth: 1 +TIM2: + _modify: + CCR?: + size: 16 + _include: + - patches/tim/size16b.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim2_l0.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/size16b.yaml + - fields/tim/v1/tim6.yaml + +TIM2[12]: + _include: + - patches/tim/size16b.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/tim2x.yaml + - fields/tim/ccr.yaml + - fields/tim/v1/ccm.yaml + - collect/tim/ccr.yaml + +TIM21: + _include: fields/tim/tim21.yaml + +TIM22: + _include: collect/tim/tim22_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _include: + - patches/usb/rename_EPxR_EPTYPE_field.yaml + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/cryp/l0_aes.yaml - - ./common_patches/l0_flash.yaml - - ./common_patches/l0_firewall.yaml - - ./common_patches/l0_pwr_wakeup.yaml - - ./common_patches/l0_rtc.yaml - - ./common_patches/l0_tim.yaml - - ./common_patches/l0_syscfg_cfgr.yaml - - ./common_patches/l0_nvic_prio_bits.yaml - - ./common_patches/tsc/tsc.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_LPUART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/rename_USB_FS_peripheral_to_USB.yaml - - ./common_patches/unprefix_USB_registers.yaml - - ./common_patches/rename_USB_EPxR_EPTYPE_field.yaml - - ../peripherals/adc/adc_l0.yaml - - ../peripherals/aes/aes_l0.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/crc/crc_pol.yaml - - ../peripherals/dbg/dbg_l0.yaml - - ../peripherals/dac/dac_common_1ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/dma/dma_v1_with_remapping.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/flash/flash_l0.yaml - - ../peripherals/fw/fw_l0.yaml - - ../peripherals/gpio/gpio_l0.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/lptim/lptim_v1.yaml - - ../peripherals/pwr/pwr_l0.yaml - - ../peripherals/rcc/rcc_l0_l1_common.yaml - - ../peripherals/rcc/rcc_l0.yaml - - ../peripherals/rtc/rtc_common.yaml - - ../peripherals/rtc/rtc_l0.yaml - - ../peripherals/spi/spi_l0.yaml - - ../peripherals/syscfg/syscfg_l0.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim_ccm_v1.yaml - - ../peripherals/tim/tim_l0.yaml - - ../peripherals/tim/tim21.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/usart/lpuart_v2A.yaml - - ../peripherals/usart/usart_v2B1.yaml - - ../peripherals/usb/usb_with_LPM.yaml - - ../peripherals/wwdg/wwdg.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/tim/tim2345_16bit_l.yaml - - common_patches/dma/dma_v1.yaml + - patches/nvic/l0_prio_bits.yaml + - patches/usb/rename_USB_FS_peripheral_to_USB.yaml + - patches/tim/group.yaml diff --git a/devices/stm32l100.yaml b/devices/stm32l100.yaml index 7b4b7a945..8b438c9e0 100644 --- a/devices/stm32l100.yaml +++ b/devices/stm32l100.yaml @@ -1,5 +1,20 @@ _svd: ../svd/stm32l100.svd +ADC: + _include: + - patches/adc/l1_smpr.yaml + - collect/adc/jofr_jdr.yaml + +AD[C]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v1.yaml + +COMP: {} + CRC: DR: # The SVD calls the DR field "Data_register" @@ -11,80 +26,197 @@ CRC: _modify: Independent_data_register: name: IDR + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + _include: + - fields/dac/l1.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/split.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +Flash: {} + +FSMC: + _include: + - patches/fsmc/sramfix_common.yaml + - fields/fsmc/sram.yaml + - collect/fsmc/sram.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/with_OSPEEDER.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD_0,ADD_1_7,ADD_8_9" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +OPAMP: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml RCC: CR: - _merge: ["RTCPRE*"] + _merge: RTCPRE* AHBLPENR: _add: FSMCLPEN: - description: "FSMC clock enable during Sleep mode" + description: FSMC clock enable during Sleep mode bitOffset: 30 bitWidth: 1 AESLPEN: - description: "AES clock enable during Sleep mode" + description: AES clock enable during Sleep mode bitOffset: 27 bitWidth: 1 APB1LPENR: _add: UART5LPEN: - description: "USART 5 clock enable during Sleep mode" + description: USART 5 clock enable during Sleep mode bitOffset: 20 bitWidth: 1 UART4LPEN: - description: "USART 4 clock enable during Sleep mode" + description: USART 4 clock enable during Sleep mode bitOffset: 19 bitWidth: 1 SPI3LPEN: - description: "SPI 3 clock enable during Sleep mode" + description: SPI 3 clock enable during Sleep mode bitOffset: 15 bitWidth: 1 TIM5LPEN: - description: "Timer 5 clock enable during Sleep mode" + description: Timer 5 clock enable during Sleep mode bitOffset: 3 bitWidth: 1 CSR: _add: OBLRSTF: - description: "Options bytes loading reset flag" + description: Options bytes loading reset flag bitOffset: 25 bitWidth: 1 LSECSSD: - description: "CSS on LSE failure Detection" + description: CSS on LSE failure Detection bitOffset: 12 bitWidth: 1 LSECSSON: - description: "CSS on LSE enable" + description: CSS on LSE enable bitOffset: 11 bitWidth: 1 + _include: + - patches/rcc/LSECSSC_LSECSSF.yaml + - fields/rcc/rcc_l0_l1_common.yaml + - fields/rcc/rcc_l1.yaml + +RI: {} + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + FIFO: + _modify: + FIF0Data: + name: FIFOData + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + +SYSCFG: {} + +TIM2: + _include: + - patches/tim/rename_TIM2_CCR3_CCR3.yaml + - patches/tim/l1_ccs.yaml + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - patches/tim/omp.yaml + - patches/tim/l1_ccs.yaml + - patches/tim/l1_tim9_ccer.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v1.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/rename_TIM2_CCR3_CCR3.yaml - - ./common_patches/rcc_LSECSSC_LSECSSF.yaml - - ./common_patches/gpio_with_OSPEEDER.yaml - - ./common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/split_exti.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_common.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ./common_patches/unprefix_USB_registers.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/spi/spi_v1.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/rcc/rcc_l0_l1_common.yaml - - ../peripherals/rcc/rcc_l1.yaml - - ../peripherals/i2c/i2c_v1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - ../peripherals/tim/tim_ccm_v1.yaml + - patches/tim/group.yaml diff --git a/devices/stm32l151.yaml b/devices/stm32l151.yaml index 8e01c1349..afdaf2a28 100644 --- a/devices/stm32l151.yaml +++ b/devices/stm32l151.yaml @@ -1,5 +1,20 @@ _svd: ../svd/stm32l151.svd +ADC: + _include: + - patches/adc/l1_smpr.yaml + - collect/adc/jofr_jdr.yaml + +AD[C]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v1.yaml + +COMP: {} + CRC: DR: # The SVD calls the DR field "Data_register" @@ -11,30 +26,155 @@ CRC: _modify: Independent_data_register: name: IDR + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + _include: + - fields/dac/l1.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/split.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +Flash: {} + +FSMC: + _include: + - patches/fsmc/sramfix_common.yaml + - fields/fsmc/sram.yaml + - collect/fsmc/sram.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/with_OSPEEDER.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD_0,ADD_1_7,ADD_8_9" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +OPAMP: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: {} + +RI: {} + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + FIFO: + _modify: + FIF0Data: + name: FIFOData + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + +SYSCFG: {} + +TIM2: + _include: + - patches/tim/rename_TIM2_CCR3_CCR3.yaml + - patches/tim/l1_ccs.yaml + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - patches/tim/omp.yaml + - patches/tim/l1_ccs.yaml + - patches/tim/l1_tim9_ccer.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: + - patches/tim/icpsc.yaml + +TIM1[01]: + _delete: [CR2, CCR2] + _include: + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM1[1]: + _include: collect/tim/tim11_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v1.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/rename_TIM2_CCR3_CCR3.yaml - - ./common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/split_exti.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_common.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ./common_patches/unprefix_USB_registers.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../devices/common_patches/gpio_with_OSPEEDER.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - ../peripherals/tim/tim_ccm_v1.yaml + - patches/tim/group.yaml diff --git a/devices/stm32l152.yaml b/devices/stm32l152.yaml new file mode 100644 index 000000000..93ba3c090 --- /dev/null +++ b/devices/stm32l152.yaml @@ -0,0 +1,180 @@ +_svd: ../svd/stm32l152.svd + +ADC: + _include: + - patches/adc/l1_smpr.yaml + - collect/adc/jofr_jdr.yaml + +AD[C]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v1.yaml + +COMP: {} + +CRC: + DR: + # The SVD calls the DR field "Data_register" + _modify: + Data_register: + name: DR + IDR: + # The SVD calls the IDR field "Independet_data_register" + _modify: + Independent_data_register: + name: IDR + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + _include: + - fields/dac/l1.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/split.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +Flash: {} + +FSMC: + _include: + - patches/fsmc/sramfix_common.yaml + - fields/fsmc/sram.yaml + - collect/fsmc/sram.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/with_OSPEEDER.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD_0,ADD_1_7,ADD_8_9" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +OPAMP: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: {} + +RI: {} + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + FIFO: + _modify: + FIF0Data: + name: FIFOData + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + +SYSCFG: {} + +TIM2: + _include: + - patches/tim/rename_TIM2_CCR3_CCR3.yaml + - patches/tim/l1_ccs.yaml + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - patches/tim/omp.yaml + - patches/tim/l1_ccs.yaml + - patches/tim/l1_tim9_ccer.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM11: + _include: + - patches/tim/icpsc.yaml + +TIM1[01]: + _delete: [CR2, CCR2] + _include: + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +TIM1[1]: + _include: collect/tim/tim11_derive.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v1.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/tim/group.yaml diff --git a/devices/stm32l162.yaml b/devices/stm32l162.yaml index 5dd6cf5dc..4557f5573 100644 --- a/devices/stm32l162.yaml +++ b/devices/stm32l162.yaml @@ -1,5 +1,20 @@ _svd: ../svd/stm32l162.svd +ADC: + _include: + - patches/adc/l1_smpr.yaml + - collect/adc/jofr_jdr.yaml + +AD[C]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - fields/aes/v1.yaml + +COMP: {} + CRC: DR: # The SVD calls the DR field "Data_register" @@ -11,30 +26,149 @@ CRC: _modify: Independent_data_register: name: IDR + _include: + - fields/crc/v1.yaml + - fields/crc/crc_idr_8bit.yaml + +DAC: + _include: + - fields/dac/l1.yaml + - collect/dac/v2.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/split.yaml + - fields/exti/common.yaml + - collect/exti/farray.yaml + +Flash: {} + +FSMC: + _include: + - patches/fsmc/sramfix_common.yaml + - fields/fsmc/sram.yaml + - collect/fsmc/sram.yaml + +FSM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/with_OSPEEDER.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - patches/16bit.yaml + - fields/i2c/v1.yaml + OAR1: + _merge: + ADD: "ADD_0,ADD_1_7,ADD_8_9" + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +OPAMP: {} + +PWR: + _include: + - fields/pwr/pwr_v1.yaml + +RCC: {} + +RI: {} + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SDIO: + FIFO: + _modify: + FIF0Data: + name: FIFOData + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_v1.yaml + +SYSCFG: {} + +TIM2: + _include: + - patches/tim/rename_TIM2_CCR3_CCR3.yaml + - patches/tim/l1_ccs.yaml + - patches/tim/icpsc.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v1/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v1/tim6.yaml + +TIM9: + _include: + - patches/tim/omp.yaml + - patches/tim/l1_ccs.yaml + - patches/tim/l1_tim9_ccer.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim9.yaml + - collect/tim/ccr.yaml + +TIM10: + _include: + - patches/tim/tim10_14_missing_opm.yaml + - patches/tim/icpsc.yaml + - fields/tim/v1/tim10.yaml + - collect/tim/ccr.yaml + +USART1: + _include: + - patches/usart/v1.yaml + - fields/usart/v2/usart.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v1.yaml + - collect/usb/epxr.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - ./common_patches/rename_TIM2_CCR3_CCR3.yaml - - ./common_patches/merge_I2C_OAR1_ADDx_fields.yaml - - common_patches/split_exti.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_sramfix_common.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ./common_patches/unprefix_USB_registers.yaml - - ../peripherals/dac/dac_wavegen.yaml - - ../peripherals/dac/dac_common_2ch.yaml - - ../peripherals/dac/dac_dmaudr.yaml - - ../peripherals/crc/crc_basic.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/pwr/pwr_v1.yaml - - ../devices/common_patches/gpio_with_OSPEEDER.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_16bit.yaml - - ../peripherals/iwdg/iwdg.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tim/tim_ccr.yaml - - ../peripherals/usb/usb.yaml - - ../peripherals/tim/tim_ccm_v1.yaml + - patches/tim/group.yaml diff --git a/devices/stm32l412.yaml b/devices/stm32l412.yaml new file mode 100644 index 000000000..be6074f36 --- /dev/null +++ b/devices/stm32l412.yaml @@ -0,0 +1,316 @@ +# This SVD is a copy+paste of l4x2's. +_svd: ../svd/stm32l412.svd + +_clear_fields: "*" + +# This module is the same as l4x2, but with the RTC peripheral from L5 and G4. +# Applies to L412 and L422 MCUs. Note that the RM (RM0394) includes two separate +# RTC chapters: One that applies to L41x and L42x (Chapter 34), and one that +# applies to the rest. (Chapter 36). This module includes the Chapter 34 RTC setup. + +# TR, DR, PRER, WPR, TSSSR, SHIFTR, TSTR, TSDR, ALRMASSR,registers unchanged. +# old CR at new address, and some fields added +# WUTR has an additional WUTOCLR field. +# CR has additional fields. +# CALR, SSR, SHIFTR, ALRMAR and ALRMBR, ALRMASSR, ALRMBSSR at a diff address. +# CALR has an added field. +# ISR, TAMPCR, OR, BKP0R, and BKP31R removed. +# SCR, MISR, SR, ICSR added + +_copy: + TIM1: + from: ../svd/stm32l4x1.svd:TIM1 + TIM2: + from: ../svd/stm32l4x1.svd:TIM2 + TIM6: + from: ../svd/stm32l4x1.svd:TIM6 + TIM15: + from: ../svd/stm32l4x1.svd:TIM15 + TIM16: + from: ../svd/stm32l4x1.svd:TIM16 + +_derive: + USART3: USART1 + +_modify: + USB_SRAM: + name: USB + # without quotes, get less readable value 1073768448 + baseAddress: "0x40006800" + + # The SVD calls ADC1 ADC. + ADC: + name: ADC1 + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common.yaml + - fields/adc/adc_v3_common_l4+.yaml + +ADC12_Common: + _strip: ADC_ + _include: + - fields/adc/adc_v3_common.yaml + +ADC1: + _strip: ADC_ + _modify: + _interrupts: + ADC1: + name: ADC1_2 + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + DIFSEL: + _merge: + DIFSEL: DIFSEL* + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: {} + +GPIO[ABCH]: + BRR: + _add: + BR: + description: These bits are write-only. A read to these bits returns the value 0x0000 + access: write-only + bitOffset: 0 + bitWidth: 16 + _split: [BR] + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCH]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: patches/16bit.yaml + +LPTIM1: + _include: + - fields/lptim/v2.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +OPAMP: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + +# SVD incorrectly labels APB1ENR1 bit 18 as USART1EN instead of USART3EN. +# SVD incorrectly labels APB1ENR1 bit 26 as USBF instead of USBFSEN. +# SVD incorrectly labels APB1ENR1 bit 14 as SPI1EN instead of SPI2EN. +# SVD incorrectly omits APB1ENR1 bit 1 (TIM3RST), which is present for +# SVD incorrectly shifts CRCRST 11 bits instead of 12 +# SVD incorrectly labels APB1SMENR1 bit 17 as USART1SMEN instead of USART2SMEN +# SVD incorrectly labels APB1SMENR1 bit 18 as USART2SMEN instead of USART3SMEN +# SVD is missing label APB1SMENR1 bit 19 as UART4SMEN +# STM32L45xx and STM32L46xx devices. +RCC: + APB1ENR1: + _modify: + USBF: + name: USBFSEN + description: USB FS clock enable + APB1RSTR1: + _add: + TIM3RST: + description: TIM3 timer reset + bitOffset: 1 + bitWidth: 1 + access: read-write + AHB1RSTR: + _modify: + CRCRST: + bitOffset: 12 + APB1SMENR1: + _modify: + USART2SMEN: + bitOffset: 17 + _add: + UART4SMEN: + description: UART4 clocks enable during Sleep and Stop modes + bitOffset: 19 + bitWidth: 1 + access: read-write + _include: + - fields/rcc/rcc_l4.yaml + +RNG: + _add: + _interrupts: + RNG: + description: RNG global interrupt + value: 80 + _include: + - fields/rng/v1.yaml + +RTC: + _delete: + _interrupts: RNG + _add: + _interrupts: + RTC_TAMP_STAMP: + description: RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts + value: 2 + RTC_WKUP: + description: RTC Wakeup timer through EXTI line 20 interrupt + value: 3 + RTC_ALARM: + description: RTC alarms through EXTI line 18 interrupts + value: 41 + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SYSCFG: {} + +TIM1: + _include: + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + CCMR1_Input: + _modify: + IC2PCS: + name: IC2PSC + +TIM2: + CNT: + _modify: + CNT_H: + bitWidth: 16 + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART[12]: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + - fields/usart/v3/usart3_B2.yaml + +USB: + _add: + _interrupts: + USB_FS: + description: USB event interrupt through EXTI + value: 67 + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + #_array: + # COUNT?_RX: {} + # COUNT?_TX: {} + # ADDR?_RX: {} + # ADDR?_TX: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +# Most of the other patches for this device are common with the L4x2 device. +_include: + - patches/tim/group.yaml + - patches/adc/l4_adc_common.yaml diff --git a/devices/stm32l4p5.yaml b/devices/stm32l4p5.yaml new file mode 100644 index 000000000..2d06b64ea --- /dev/null +++ b/devices/stm32l4p5.yaml @@ -0,0 +1,427 @@ +_svd: ../svd/stm32l4p5.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + SDMMC2: SDMMC1 + +_modify: + DMAMUX1: + name: DMAMUX + # The SVD calls ADC1 ADC. + ADC: + name: ADC1 + +_delete: + - SWPMI1 + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common_l4+.yaml + - fields/adc/adc_v3_common.yaml + +ADC1: + JSQR: + _modify: + JEXTEN: + bitWidth: 2 + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - patches/adc/l4+.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - patches/aes/l4+.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/dac_l4+.yaml + - fields/dac/l4+.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/dcmi.yaml + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM1: + _strip: DFSDM_ + _include: + - patches/dfsdm/jchgr.yaml + - patches/dfsdm/dfsdm_v1.yaml + - patches/dfsdm/jextsel.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMA2D: + _include: + - patches/dma/dma2d_l4+.yaml + - fields/dma/dma2d_v1.yaml + +DMAMUX: + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/l4+.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: + ACR: + _modify: + LATENCY: + bitWidth: 4 + _include: + - patches/flash/l4+.yaml + - fields/flash/flash_l4+.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/l4+.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABCI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - patches/hash/hash_l4+.yaml + - collect/hash/v3.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _add: + OR: + description: ?? + addressOffset: 0x20 + resetValue: 0x0 + fields: + OR_0: + description: Option register bit 0 + bitOffset: 0 + bitWidth: 1 + OR_1: + description: Option register bit 1 + bitOffset: 1 + bitWidth: 1 + _include: + - fields/lptim/v1.yaml + + CR: + _add: + COUNTRST: + description: Counter reset + bitOffset: 3 + bitWidth: 1 + RSTARE: + description: Reset after read enable + bitOffset: 4 + bitWidth: 1 + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MPU: + _strip: MPU_ + +OCTOSPI1: + _include: + - patches/octospi/l4+.yaml + - fields/octospi/l4.yaml + +OCTOSPIM: + _include: + - patches/octospim/l4+.yaml + +OPAMP: {} + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - patches/usb_otg/fs_l4+_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_l4+_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - patches/usb_otg/fs_l4+_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_l4+.yaml + +RCC: + CFGR: + _modify: + MCOSEL: + bitWidth: 4 + _include: + - patches/rcc/l4+.yaml + - fields/rcc/rcc_l4+.yaml + +RNG: + _include: + - patches/rng/l4+.yaml + - fields/rng/v2.yaml + +RTC: + MISR: + _modify: + ALRMF: + name: ALRAMF + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v3/common.yaml + # - collect/rtc/alarm.yaml + +SAI1: + _include: + - patches/sai/sai_l4+.yaml + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + - collect/sdio/fifo.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SYSCFG: + _include: + - patches/syscfg/l4+.yaml + - fields/syscfg/syscfg_l4+.yaml + +TIM?: + _strip: TIM?_ + +TIM??: + _strip: TIM??_ + +TIM[18]: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + CR1: + UIFREMAP: + Disabled: [0, No remapping. UIF status bit is not copied to TIMx_CNT register bit 31] + Enabled: [1, Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31] + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM[25]: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + CR1: + UIFREMAP: + Disabled: [0, No remapping. UIF status bit is not copied to TIMx_CNT register bit 31] + Enabled: [1, Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31] + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM[34]: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + CNT: + _modify: + CNT: + bitWidth: 16 + ARR: + _modify: + ARR: + bitWidth: 16 + CR1: + UIFREMAP: + Disabled: [0, No remapping. UIF status bit is not copied to TIMx_CNT register bit 31] + Enabled: [1, Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31] + +TIM4: + _include: collect/tim/tim4_derive.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + - fields/tim/tim_uifremap.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_1: + name: OC1M_3 + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/firewall/l4+.yaml + - patches/ltdc/rename.yaml + - patches/dbgmcu/l4_apb_fzr_rename.yaml + - patches/dbgmcu/l4+.yaml + - fields/dbg/dbg_l4+.yaml + - patches/comp/l4xx_comp_reg_rename.yaml + - fields/comp/comp_l4+.yaml + - patches/tim/group.yaml + - patches/pssi/pssi.yaml diff --git a/devices/stm32l4r5.yaml b/devices/stm32l4r5.yaml new file mode 100644 index 000000000..6253dbb93 --- /dev/null +++ b/devices/stm32l4r5.yaml @@ -0,0 +1,454 @@ +_svd: ../svd/stm32l4r5.svd + +_clear_fields: "*" + +_modify: + ADC: + name: ADC1 + LTCD: + groupName: LTCD + +_copy: + TIM3: + from: TIM2 + SDMMC1: + from: ../svd/stm32l4p5.svd:SDMMC1 + +_derive: + TIM4: TIM3 + TIM7: TIM6 + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common_l4+.yaml + - fields/adc/adc_v3_common.yaml + +ADC1: + _delete: + _interrupts: + - ADC3 + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - patches/adc/l4+.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - patches/aes/l4+.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/dac_l4+.yaml + - fields/dac/l4+.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/dcmi.yaml + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM1: + _strip: DFSDM_ + _delete: + - CH7WDATR + + _copy: + CH7WDATR: + _from: CH6WDATR + addressOffset: 0xEC + description: CH7WDATR + + CH7DATINR: + _from: CH6DATINR + addressOffset: 0xF0 + description: CH7DATINR + _include: + - patches/dfsdm/jchgr.yaml + - patches/dfsdm/dfsdm_v1.yaml + - patches/dfsdm/jextsel.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMA2D: + _include: + - patches/dma/dma2d_l4+.yaml + - fields/dma/dma2d_v1.yaml + +DMAMUX1: + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/l4+.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: + ACR: + _modify: + LATENCY: + bitWidth: 4 + ECCR: + _modify: + ADDR_ECC: + bitWidth: 21 + BK_ECC: + bitOffset: 21 + SYSF_ECC: + bitOffset: 22 + _include: + - fields/flash/flash_l4+.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/l4+.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GFXMMU: + _include: + - collect/gfxmmu/lut.yaml + +GPIO[ABCI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - patches/hash/hash_l4+.yaml + - collect/hash/v3.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MPU: + _strip: MPU_ + +OCTOSPI1: + DCR2: + _add: + WRAPSIZE: + bitOffset: 16 + bitWidth: 3 + description: Wrap size + _include: + - patches/octospi/ddm.yaml + - patches/octospi/add_wrap.yaml + - fields/octospi/l4.yaml + +OCTOSPIM: + _include: + - patches/octospim/l4+.yaml + +OPAMP: {} + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - patches/usb_otg/fs_l4+_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_l4+_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - patches/usb_otg/fs_l4+_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_l4+.yaml + +# SVD incorrectly labels APB1ENR1 bit 15 as SP3EN instead of SPI3EN. +RCC: + APB1ENR1: + _modify: + SP3EN: + name: SPI3EN + description: SPI peripheral 3 clock enable + + AHB3ENR: + _add: + OSPI1EN: + description: OSPI1 memory interface clock enable + bitOffset: 8 + bitWidth: 1 + + AHB3RSTR: + _add: + OSPI1RST: + description: OSPI1 memory interface reset + bitOffset: 8 + bitWidth: 1 + + AHB3SMENR: + _add: + OSPI1SMEN: + description: OSPI1 memory interface clock enable during Sleep and Stop modes + bitOffset: 8 + bitWidth: 1 + + CFGR: + _modify: + MCOSEL: + bitWidth: 4 + + _add: + DLYCFGR: + description: Delay configuration register + addressOffset: 0xA4 + size: 0x20 + resetValue: 0x00000000 + access: read-write + fields: + OCTOSPI1_DLY: + description: Delay sampling configuration on OCTOSPI1 + bitOffset: 0 + bitWidth: 4 + OCTOSPI2_DLY: + description: Delay sampling configuration on OCTOSPI2 + bitOffset: 4 + bitWidth: 4 + _include: + - fields/rcc/rcc_l4.yaml + +RNG: + _include: + - patches/rng/l4+.yaml + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_l4+.yaml + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + - collect/sdio/fifo.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SWPMI1: {} + +SYSCFG: + _include: + - patches/syscfg/l4+.yaml + - fields/syscfg/syscfg_l4+.yaml + +TIM?: + _strip: TIM?_ + +TIM??: + _strip: TIM??_ + +TIM[18]: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM[25]: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + CNT: + _modify: + CNT: + bitWidth: 16 + ARR: + _modify: + ARR: + bitWidth: 16 + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + - fields/tim/tim_uifremap.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_1: + name: OC1M_3 + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + #- patches/usart/rename_CR2_DATAINV_field.yaml + #- patches/usart/rename_LPUART_CR2_DATAINV_field.yaml + #- patches/usart/merge_BRR_fields.yaml + - patches/ltdc/rename.yaml + - patches/tim/group.yaml + - patches/dbgmcu/l4_apb_fzr_rename.yaml diff --git a/devices/stm32l4r9.yaml b/devices/stm32l4r9.yaml new file mode 100644 index 000000000..06fb9867a --- /dev/null +++ b/devices/stm32l4r9.yaml @@ -0,0 +1,391 @@ +_svd: ../svd/stm32l4r9.svd + +_clear_fields: "*" + +_modify: + ADC: + name: ADC1 + LTCD: + groupName: LTCD + +_copy: + TIM3: + from: TIM2 + SDMMC1: + from: ../svd/stm32l4p5.svd:SDMMC1 + +_derive: + TIM4: TIM3 + TIM7: TIM6 + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common_l4+.yaml + - fields/adc/adc_v3_common.yaml + +ADC1: + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - patches/adc/l4+.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - patches/aes/l4+.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - patches/dac/dac_l4+.yaml + - fields/dac/l4+.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/dcmi.yaml + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM1: + _strip: DFSDM_ + _include: + - patches/dfsdm/jchgr.yaml + - patches/dfsdm/dfsdm_v1.yaml + - patches/dfsdm/jextsel.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMA2D: + _include: + - patches/dma/dma2d_l4+.yaml + - fields/dma/dma2d_v1.yaml + +DMAMUX1: + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +DSI: + _strip: DSI_ + _modify: + _interrupts: + DSIHSOT: + name: DSIHOST + _include: + - collect/dsi/isr.yaml + +EXTI: + _include: + - patches/exti/l4+.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: + ACR: + _modify: + LATENCY: + bitWidth: 4 + _include: + - patches/flash/l4+.yaml + - fields/flash/flash_l4+.yaml + +FMC: + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/l4+.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GFXMMU: + _include: + - collect/gfxmmu/lut.yaml + +GPIO[ABCI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - patches/hash/hash_l4+.yaml + - collect/hash/v3.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/lp_wl.yaml + +LTDC: + _include: + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MPU: + _strip: MPU_ + +OCTOSPI1: + _include: + - patches/octospi/l4+.yaml + - fields/octospi/l4.yaml + +OCTOSPIM: + _include: + - patches/octospim/l4+.yaml + +OPAMP: {} + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - patches/usb_otg/fs_l4+_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - patches/usb_otg/fs_l4+_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - patches/usb_otg/fs_l4+_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: + _strip: PWR_ + _include: + - fields/pwr/pwr_l4+.yaml + +# SVD incorrectly labels APB1ENR1 bit 15 as SP3EN instead of SPI3EN. +RCC: + APB1ENR1: + _modify: + SP3EN: + name: SPI3EN + description: SPI peripheral 3 clock enable + _include: + - fields/rcc/rcc_l4.yaml + +RNG: + _include: + - patches/rng/l4+.yaml + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_l4+.yaml + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + - collect/sdio/fifo.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SWPMI1: {} + +SYSCFG: + _include: + - patches/syscfg/l4+.yaml + - fields/syscfg/syscfg_l4+.yaml + +TIM?: + _strip: TIM?_ + +TIM??: + _strip: TIM??_ + +TIM[18]: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM[25]: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _include: collect/tim/tim5_derive.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + CNT: + _modify: + CNT: + bitWidth: 16 + ARR: + _modify: + ARR: + bitWidth: 16 + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + - fields/tim/tim_uifremap.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_1: + name: OC1M_3 + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - fields/usart/v4/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + #- patches/usart/rename_CR2_DATAINV_field.yaml + #- patches/usart/rename_LPUART_CR2_DATAINV_field.yaml + #- patches/usart/merge_BRR_fields.yaml + - patches/ltdc/rename.yaml + - patches/tim/group.yaml + - patches/dbgmcu/l4_apb_fzr_rename.yaml + - patches/adc/adc_common_group_name.yaml diff --git a/devices/stm32l4x1.yaml b/devices/stm32l4x1.yaml index 1e095c7a8..b1dfb9325 100644 --- a/devices/stm32l4x1.yaml +++ b/devices/stm32l4x1.yaml @@ -1,14 +1,166 @@ _svd: ../svd/stm32l4x1.svd +_derive: + USART3: USART1 + TIM4: TIM3 + +_modify: + # The SVD calls ADC1 ADC. + ADC: + name: ADC1 + DAC1: + name: DAC + +# TIM3 is 16-bit, whilst TIM2 is 32-bit +_copy: + TIM3: + from: TIM2 + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common.yaml + - fields/adc/adc_v3_common_l4+.yaml + +ADC123_Common: + _include: fields/adc/adc_v3_common.yaml + +ADC1: + _modify: + _interrupts: + ADC1: + name: ADC1_2 + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - patches/adc/l4+.yaml + - patches/adc/dr_rdata.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - patches/aes/l4.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/l4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DFSDM: + _strip: DFSDM_ + _include: + - patches/dfsdm/jchgr.yaml + - patches/dfsdm/dfsdm_v1.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: + _include: + - patches/flash/flash_boot0s.yaml + +GPIO[ABC]: + _include: + - patches/gpio/l4_brr.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +OPAMP: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + # SVD incorrectly labels APB1ENR1 bit 18 as USART1EN instead of USART3EN. # SVD incorrectly labels APB1ENR1 bit 14 as SPI1EN instead of SPI2EN. +# SVD incorrectly shifts CRCRST 11 bits instead of 12 +# SVD incorrectly labels APB1SMENR1 bit 17 as USART1SMEN instead of USART2SMEN +# SVD incorrectly labels APB1SMENR1 bit 18 as USART2SMEN instead of USART3SMEN +# SVD is missing label APB1SMENR1 bit 19 as UART4SMEN RCC: APB1ENR1: _modify: USART1EN: name: USART3EN description: USART3 clock enable - _modify: SPI1EN: name: SPI2EN description: SPI peripheral 2 clock enable @@ -17,63 +169,153 @@ RCC: USART1RST: name: USART3RST description: USART3 reset + AHB1RSTR: + _modify: + CRCRST: + bitOffset: 12 + APB1SMENR1: + _delete: + - USART1SMEN + _modify: + USART2SMEN: + bitOffset: 17 + _add: + USART3SMEN: + description: USART3 clocks enable during Sleep and Stop modes + bitOffset: 18 + bitWidth: 1 + access: read-write + UART4SMEN: + description: UART4 clocks enable during Sleep and Stop modes + bitOffset: 19 + bitWidth: 1 + access: read-write + _include: + - fields/rcc/rcc_l4.yaml + - fields/rcc/rcc_l4_usart2_3.yaml + - fields/rcc/rcc_l4_uart4.yaml -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" +RNG: + _include: + - fields/rng/v1.yaml -# TIM3 is 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SWPMI1: {} + +SYSCFG: {} + +TIM[18]: + _include: + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + CCMR1_Input: + _modify: + IC2PCS: + name: IC2PSC + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM2: + CNT: + _modify: + CNT_H: + bitWidth: 16 + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB_SRAM: + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_LPUART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/dfsdm/dfsdm_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/rcc/rcc_l4.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/dma/dma_v1_with_remapping.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/lpuart_v2A.yaml - - ../peripherals/usart/usart_v2B2.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/fpu_interrupt.yaml - - ./common_patches/flash/flash_boot0s.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/tim/group.yaml + - patches/adc/l4_adc_common.yaml + - patches/comp/l4xx_comp_reg_rename.yaml + - fields/comp/comp_l4x1.yaml + - fields/opamp/opamp_l4.yaml diff --git a/devices/stm32l4x2.yaml b/devices/stm32l4x2.yaml index 957a88491..aab4dde39 100644 --- a/devices/stm32l4x2.yaml +++ b/devices/stm32l4x2.yaml @@ -1,9 +1,182 @@ _svd: ../svd/stm32l4x2.svd +_clear_fields: "*" + +_delete: + - USB_FS + +_copy: + TIM1: + from: ../svd/stm32l4x1.svd:TIM1 + TIM2: + from: ../svd/stm32l4x1.svd:TIM2 + TIM3: + from: ../svd/stm32l4x1.svd:TIM2 + TIM6: + from: ../svd/stm32l4x1.svd:TIM6 + TIM15: + from: ../svd/stm32l4x1.svd:TIM15 + TIM16: + from: ../svd/stm32l4x1.svd:TIM16 + +_derive: + USART3: USART1 + +_modify: + USB_SRAM: + name: USB + # without quotes, get less readable value 1073768448 + baseAddress: "0x40006800" + + # The SVD calls ADC1 ADC. + ADC: + name: ADC1 + DAC1: + name: DAC + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common.yaml + - fields/adc/adc_v3_common_l4+.yaml + +ADC123_Common: + _strip: ADC_ + _include: fields/adc/adc_v3_common.yaml + +ADC1: + _strip: ADC_ + _modify: + _interrupts: + ADC1: + name: ADC1_2 + _include: + - patches/adc/split.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + DIFSEL: + _merge: + DIFSEL: DIFSEL* + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - patches/aes/l4.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/l4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DFSDM: + _strip: DFSDM_ + _include: + - patches/dfsdm/jchgr.yaml + - patches/dfsdm/dfsdm_v1.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: {} + +GPIO[ABC]: + _include: + - patches/gpio/l4_brr.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +LPTIM1: + _include: + - fields/lptim/v2.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +OPAMP: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml + # SVD incorrectly labels APB1ENR1 bit 18 as USART1EN instead of USART3EN. # SVD incorrectly labels APB1ENR1 bit 26 as USBF instead of USBFSEN. # SVD incorrectly labels APB1ENR1 bit 14 as SPI1EN instead of SPI2EN. # SVD incorrectly omits APB1ENR1 bit 1 (TIM3RST), which is present for +# SVD incorrectly shifts CRCRST 11 bits instead of 12 +# SVD incorrectly labels APB1SMENR1 bit 17 as USART1SMEN instead of USART2SMEN +# SVD incorrectly labels APB1SMENR1 bit 18 as USART2SMEN instead of USART3SMEN +# SVD is missing label APB1SMENR1 bit 19 as UART4SMEN # STM32L45xx and STM32L46xx devices. RCC: APB1ENR1: @@ -28,86 +201,157 @@ RCC: bitOffset: 1 bitWidth: 1 access: read-write + AHB1RSTR: + _modify: + CRCRST: + bitOffset: 12 + APB1SMENR1: + _delete: + - USART1SMEN + _modify: + USART2SMEN: + bitOffset: 17 + _add: + USART3SMEN: + description: USART3 clocks enable during Sleep and Stop modes + bitOffset: 18 + bitWidth: 1 + access: read-write + UART4SMEN: + description: UART4 clocks enable during Sleep and Stop modes + bitOffset: 19 + bitWidth: 1 + access: read-write + _include: + - fields/rcc/rcc_l4.yaml + - fields/rcc/rcc_l4_usart2_3.yaml + - fields/rcc/rcc_l4_uart4.yaml -# cf. -# we call the resulting peripheral `USB` instead of `USB-FS` -# to be aligned with `mvirkkunen/stm32f103-usb` +RNG: + _include: + - fields/rng/v1.yaml -_modify: - USB_SRAM: - name: USB - # without quotes, get less readable value 1073768448 - baseAddress: "0x40006800" +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SWPMI1: {} + +SYSCFG: {} + +TIM1: + _include: + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + CCMR1_Input: + _modify: + IC2PCS: + name: IC2PSC + +TIM2: + CNT: + _modify: + CNT_H: + bitWidth: 16 + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml USB: _add: _interrupts: - # the interrupt is listed under USB_FS, which we delete - USB: + USB_FS: description: USB event interrupt through EXTI value: 67 + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml -_delete: - - USB_FS +VREFBUF: {} -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" - -# TIM3 is 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml +# Most of the patches and includes for this device are shared with the L412, +# so update the common patch file below instead. _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_LPUART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/dfsdm/dfsdm_v2.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/rcc/rcc_l4.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/dma/dma_v1_with_remapping.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/lpuart_v2A.yaml - - ../peripherals/usart/usart_v2B2.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - common_patches/fpu_interrupt.yaml - - ../peripherals/usb/usb_array.yaml - - ../peripherals/usb/usb_with_LPM.yaml - - ./common_patches/flash/flash_boot0s.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml + - patches/tim/group.yaml + - patches/adc/l4_adc_common.yaml + - patches/comp/l4xx_comp_reg_rename.yaml + - fields/comp/comp_l4x1.yaml + - fields/opamp/opamp_l4.yaml diff --git a/devices/stm32l4x3.yaml b/devices/stm32l4x3.yaml index 75c9fd70b..576f7c1a2 100644 --- a/devices/stm32l4x3.yaml +++ b/devices/stm32l4x3.yaml @@ -1,5 +1,143 @@ _svd: ../svd/stm32l4x3.svd +_copy: + TIM1: + from: ../svd/stm32l4x1.svd:TIM1 + TIM2: + from: ../svd/stm32l4x1.svd:TIM2 + TIM6: + from: ../svd/stm32l4x1.svd:TIM6 + TIM15: + from: ../svd/stm32l4x1.svd:TIM15 + TIM16: + from: ../svd/stm32l4x1.svd:TIM16 + +_modify: + # The SVD calls ADC1 ADC. + ADC: + name: ADC1 + DAC1: + name: DAC + USB: + baseAddress: "0x40006800" + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common.yaml + - fields/adc/adc_v3_common_l4+.yaml + +ADC123_Common: + _include: fields/adc/adc_v3_common.yaml + +ADC1: + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - patches/adc/l4+.yaml + - patches/adc/dr_rdata.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - patches/aes/l4.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - patches/can/l4x3_missing_regs.yaml + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/l4.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: + _include: + - patches/flash/flash_boot0s.yaml + +GPIO[ABC]: + _include: + - patches/gpio/l4_brr.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +OPAMP: {} + +PWR: {} + # SVD incorrectly labels APB1ENR1 bit 26 as USBF instead of USBFSEN. RCC: APB1ENR1: @@ -7,62 +145,151 @@ RCC: SP3EN: name: SPI3EN description: SPI peripheral 3 clock enable - _modify: USBF: name: USBFSEN description: USB FS clock enable -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" + # SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN 11 bits instead of 12 + AHB1ENR: + _modify: + CRCEN: + bitOffset: 12 + AHB1RSTR: + _modify: + CRCRST: + bitOffset: 12 + AHB1SMENR: + _modify: + CRCSMEN: + bitOffset: 12 + + APB1RSTR1: + _add: + USBFSRST: + description: USB FS reset + bitOffset: 26 + bitWidth: 1 + _include: + - fields/rcc/rcc_l4.yaml + - fields/rcc/rcc_l4_usart2_3.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SWPMI1: {} + +SYSCFG: {} + +TIM1: + _include: + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + CCMR1_Input: + _modify: + IC2PCS: + name: IC2PSC + +TIM2: + CNT: + _modify: + CNT_H: + bitWidth: 16 + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + _add: + _interrupts: + USB_FS: + description: USB event interrupt through EXTI + value: 67 + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_LPUART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - ./common_patches/l4_crrcr.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/rcc/rcc_l4.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2_32bit.yaml - - common_patches/tim/tim2_32bit.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/dma/dma_v1_with_remapping.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/lpuart_v2A.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - ./common_patches/flash/flash_boot0s.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - common_patches/dma_interrupt_names.yaml + - patches/tim/group.yaml + - patches/dma/interrupt_names.yaml + - patches/adc/l4_adc_common.yaml + - patches/comp/l4xx_comp_reg_rename.yaml + - fields/comp/comp_l4x6.yaml + - fields/opamp/opamp_l4.yaml diff --git a/devices/stm32l4x5.yaml b/devices/stm32l4x5.yaml index 8fea4a827..81bbbac0b 100644 --- a/devices/stm32l4x5.yaml +++ b/devices/stm32l4x5.yaml @@ -1,20 +1,205 @@ _svd: ../svd/stm32l4x5.svd -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" +_copy: + TIM1: + from: ../svd/stm32l4x1.svd:TIM1 + TIM2: + from: ../svd/stm32l4x1.svd:TIM2 + TIM3: + from: ../svd/stm32l4x1.svd:TIM2 + TIM6: + from: ../svd/stm32l4x1.svd:TIM6 + TIM8: + from: ../svd/stm32l4x1.svd:TIM8 + TIM15: + from: ../svd/stm32l4x1.svd:TIM15 + TIM16: + from: ../svd/stm32l4x1.svd:TIM16 + +_derive: + TIM4: TIM3 + +_modify: + # The SVD calls this ADC123_Common and ADC_Common in the rest, + # we'll prefer the more sensible (and better for sorting) ADC_Common + ADC123_Common: + name: ADC_Common + DAC1: + name: DAC + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common.yaml + - fields/adc/adc_v3_common_l4+.yaml + CCR: + _modify: + MULT: + name: DUAL + description: Dual ADC mode selection + TSEN: + name: CH18SEL + description: CH18 selection (Vbat) + VBATEN: + name: CH17SEL + description: CH17 selection (temperature) + _add: + PRESC: + description: ADC prescaler + bitOffset: 18 + bitWidth: 4 + access: read-write + +ADC1: + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - patches/adc/l4_smpr.yaml + - patches/adc/l4_sqr1.yaml + - patches/adc/l4+.yaml + - patches/adc/dr_rdata.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +# Add correct AES interrupt at 79 +AES: + _add: + _interrupts: + AES: + description: AES global interrupt + value: 79 + _include: + - patches/aes/fields.yaml + - patches/aes/l4.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - patches/can/l4x3_missing_regs.yaml + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/l45x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DFSDM: + _strip: DFSDM_ + _include: + - patches/dfsdm/jchgr.yaml + - patches/dfsdm/dfsdm_v1.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: + _include: + - patches/flash/flash_boot0s.yaml + +FMC: + BCR?: + _delete: WRAPMOD + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_common.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABC]: + _include: + - patches/gpio/l4_ascr.yaml + - patches/gpio/l4_brr.yaml + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BC]: + _include: collect/gpio/v2_derive.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +OPAMP: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml # SVD incorrectly labels APB1ENR1 bit 15 as SP3EN instead of SPI3EN. # SVD does not include APB1ENR1 bit 10, RTCAPBEN # SVD does not include APB1SMENR1 bit 10, RTCAPBSMEN +# SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN 11 bits instead of 12 RCC: APB1ENR1: _modify: @@ -27,6 +212,11 @@ RCC: bitOffset: 10 bitWidth: 1 access: read-write + CRSEN: + description: Clock Recovery System clock enable (this bit is reserved for STM32L47x/L48x devices) + bitOffset: 24 + bitWidth: 1 + access: read-write APB1SMENR1: _add: RTCAPBSMEN: @@ -34,46 +224,24 @@ RCC: bitOffset: 10 bitWidth: 1 access: read-write - -# TIM3, TIM4 are 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 - TIM4: - from: TIM2 - -"FMC,FSMC": - BCR1: - _add: - WRAPMOD: - description: WRAPMOD - bitOffset: 10 - bitWidth: 1 - "BCR[2-4]": - _add: - WFDIS: - description: Write FIFO disable - bitOffset: 21 - bitWidth: 1 - access: read-write - CCLKEN: - description: CCLKEN - bitOffset: 20 - bitWidth: 1 - BCR?: - _add: - CPSIZE: - description: CRAM page size - bitOffset: 16 - bitWidth: 3 - access: read-write - BWTR?: - _add: - BUSTURN: - description: Bus turnaround phase duration - bitOffset: 16 - bitWidth: 4 - access: read-write + AHB1ENR: + _modify: + CRCEN: + bitOffset: 12 + AHB1RSTR: + _modify: + CRCRST: + bitOffset: 12 + AHB1SMENR: + _modify: + CRCSMEN: + bitOffset: 12 + _include: + - patches/rcc/l4_crrcr.yaml + - fields/rcc/rcc_l4.yaml + - fields/rcc/rcc_l4_usart2_3.yaml + - fields/rcc/rcc_l4_uart4.yaml + - fields/rcc/rcc_l4_uart5.yaml # RNG interrupt is incorrectly listed as 79 instead of 80 RNG: @@ -81,62 +249,131 @@ RNG: _interrupts: RNG: value: 80 + _include: + - fields/rng/v1.yaml -# Add correct AES interrupt at 79 -AES: - _add: - _interrupts: - AES: - description: AES global interrupt - value: 79 +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml -_include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_LPUART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - common_patches/dfsdm/dfsdm_v2.yaml - - ./common_patches/l4_crrcr.yaml - - common_patches/fsmc/fsmc_sram.yaml - - common_patches/fsmc/fsmc_nand_v2.yaml - - ../peripherals/fsmc/fsmc_sram.yaml - - ../peripherals/fsmc/fsmc_wfdis.yaml - - ../peripherals/fsmc/fsmc_nand.yaml - - ../peripherals/gpio/gpio_v2.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/rcc/rcc_l4.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/dma/dma_v1_with_remapping.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/lpuart_v2A.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - ./common_patches/flash/flash_boot0s.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - common_patches/dma_interrupt_names.yaml +SDMMC: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SWPMI1: {} + +SYSCFG: {} + +TIM[18]: + _include: + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + CCMR1_Input: + _modify: + IC2PCS: + name: IC2PSC + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM2: + CNT: + _modify: + CNT_H: + bitWidth: 16 + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml +TIM3: + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USB: + _include: + - patches/usb/add_bcdr.yaml + - fields/usb/v2.yaml + - collect/usb/epxr.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - patches/tim/group.yaml + - patches/dma/interrupt_names.yaml + - patches/adc/adc_common_group_name.yaml + - patches/adc/adc_common_group_name.yaml + - patches/dbgmcu/l4_apb_fzr_rename.yaml + - patches/adc/adc_common_group_name.yaml + - patches/comp/l4xx_comp_reg_rename.yaml + - fields/comp/comp_l4x6.yaml + - fields/opamp/opamp_l4.yaml diff --git a/devices/stm32l4x6.yaml b/devices/stm32l4x6.yaml index 734a694a6..c351a0dcd 100644 --- a/devices/stm32l4x6.yaml +++ b/devices/stm32l4x6.yaml @@ -1,16 +1,200 @@ _svd: ../svd/stm32l4x6.svd -# Merge the thousands of individal bit fields into a single field for each -# CAN filter register. This is not only much easier to use but also saves -# a huge amount of filespace and compilation time etc -- as much as 30% of all -# fields in many devices are just these CAN filter bank fields. -"CAN*": - "F?R?": - _merge: - - "FB*" - "F??R?": - _merge: - - "FB*" +_clear_fields: "*" + +_copy: + TIM1: + from: ../svd/stm32l4x1.svd:TIM1 + TIM2: + from: ../svd/stm32l4x1.svd:TIM2 + TIM3: + from: ../svd/stm32l4x1.svd:TIM2 + TIM6: + from: ../svd/stm32l4x1.svd:TIM6 + TIM8: + from: ../svd/stm32l4x1.svd:TIM8 + TIM15: + from: ../svd/stm32l4x1.svd:TIM15 + TIM16: + from: ../svd/stm32l4x1.svd:TIM16 + +_derive: + TIM4: TIM3 + USART2: USART1 + USART3: USART1 + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common_l4+.yaml + - fields/adc/adc_v3_common.yaml + +ADC1: + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - patches/adc/l4+.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + _include: + - patches/aes/fields.yaml + - patches/aes/l4.yaml + - fields/aes/v2.yaml + +CAN1: + _include: + - fields/can/can.yaml + - collect/can/can.yaml + - collect/can/filter_bank.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/crc_rename_pol.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr8.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _include: + - fields/dac/l45x.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCMI: + _include: + - patches/dcmi/byte.yaml + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DFSDM: + _strip: DFSDM_ + _include: + - patches/dfsdm/jchgr.yaml + - patches/dfsdm/dfsdm_v1.yaml + - fields/dfsdm/v1.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _include: + - fields/dma/dma_v1_with_remapping.yaml + - collect/dma/v1.yaml + +DMA2D: + _include: + - fields/dma/dma2d_v1.yaml + +EXTI: + _include: + - patches/exti/add_fpu_interrupt.yaml + - fields/exti/common.yaml + +FIREWALL: + _include: + - fields/fw/fw_l0_l4.yaml + +FLASH: {} + +FMC: + BCR?: + _delete: WRAPMOD + _include: + - patches/fsmc/bwtr_clean.yaml + - patches/fsmc/sramfix_common.yaml + - patches/fsmc/nand.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABCI]: + _include: + - fields/gpio/v2/common.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCI]: + _include: collect/gpio/v2_derive.yaml + +HASH: + _include: + - collect/hash/v2.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg_with_WINR.yaml + +LCD: + _strip: LCD_ + _delete: LCD_RAM* + _include: + - patches/lcd/ram_segment_40.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +LPUART1: + _include: + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v3/lp_A.yaml + +OPAMP: {} + +OTG_FS_*: + _strip: FS_ + +OTG_FS_DEVICE: + _include: + - patches/usb_otg/fs_v1_device_ext.yaml + - patches/usb_otg/fs_v1_device.yaml + - collect/usb_otg/fs_device.yaml +OTG_FS_GLOBAL: + _include: + - patches/usb_otg/fs_v1_global_ext.yaml + - patches/usb_otg/fs_v1_global.yaml + - collect/usb_otg/fs_global.yaml +OTG_FS_HOST: + _include: + - patches/usb_otg/fs_v1_host_ext.yaml + - patches/usb_otg/fs_v1_host.yaml + - collect/usb_otg/fs_host.yaml +OTG_FS_PWRCLK: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_dual_flash.yaml # SVD incorrectly labels APB1ENR1 bit 15 as SP3EN instead of SPI3EN. RCC: @@ -19,54 +203,150 @@ RCC: SP3EN: name: SPI3EN description: SPI peripheral 3 clock enable + _include: + - patches/rcc/l4_crrcr.yaml + - fields/rcc/rcc_l4.yaml + - fields/rcc/rcc_l4_usart2_3.yaml + - fields/rcc/rcc_l4_uart4.yaml + - fields/rcc/rcc_l4_uart5.yaml -# TIM3, TIM4 are 16-bit, whilst TIM2 is 32-bit -_copy: - TIM3: - from: TIM2 - TIM4: - from: TIM2 +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + +SDMMC1: + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - fields/sdio/v1-ata.yaml + - collect/sdio/resp.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SWPMI1: {} + +SYSCFG: {} + +TIM[18]: + _include: + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + CCMR1_Input: + _modify: + IC2PCS: + name: IC2PSC + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM2: + CNT: + _modify: + CNT_H: + bitWidth: 16 + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim_ch_16bit_l.yaml + - fields/tim/tim_mms_ts_sms.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +UART4: + CR2: + _delete: + - ADD0_3 + - ADD4_7 + _add: + ADD: + description: Address of the USART node + bitOffset: 24 + bitWidth: 8 + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +USART1: + CR3: + _strip_end: _ + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - patches/usart/merge_BRR_fields.yaml + - fields/usart/v3/B.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml _include: - - common_patches/4_nvic_prio_bits.yaml - - ./common_patches/merge_USART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_CR2_ABRMODx_fields.yaml - - ./common_patches/merge_USART_CR1_DEDTx_fields.yaml - - ./common_patches/merge_USART_CR1_DEATx_fields.yaml - - ./common_patches/rename_USART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR1_DEATx_fields.yaml - - ./common_patches/merge_LPUART_CR1_DEDTx_fields.yaml - - ./common_patches/rename_LPUART_CR2_DATAINV_field.yaml - - ./common_patches/merge_LPUART_CR2_ADDx_fields.yaml - - ./common_patches/merge_USART_BRR_fields.yaml - - common_patches/can/can.yaml - - common_patches/can/can_filter_bank.yaml - - ../peripherals/can/can.yaml - - common_patches/sai/sai_v1.yaml - - ./common_patches/l4_crrcr.yaml - - ../peripherals/gpio/gpio_v2.yaml - - ../peripherals/gpio/gpio_with_brr.yaml - - common_patches/crc/crc_rename_init.yaml - - ../peripherals/crc/crc_advanced.yaml - - ../peripherals/crc/crc_with_polysize.yaml - - ../peripherals/wwdg/wwdg.yaml - - ../peripherals/rcc/rcc_l4.yaml - - ../peripherals/tim/tim_basic.yaml - - ../peripherals/tim/tim16.yaml - - ../peripherals/tim/tim6.yaml - - ../peripherals/tim/tim2345_mixed.yaml - - common_patches/tim/tim2345_mixed_l.yaml - - ../peripherals/tim/tim_advanced.yaml - - ../peripherals/dma/dma_v1_with_remapping.yaml - - ../peripherals/iwdg/iwdg_with_WINR.yaml - - ../peripherals/exti/exti.yaml - - ../peripherals/i2c/i2c_v2.yaml - - ../peripherals/usart/lpuart_v2A.yaml - - ../peripherals/usart/usart_v2B1.yaml - - common_patches/rtc/rtc_bkpr.yaml - - common_patches/tsc/tsc.yaml - - common_patches/tim/tim_ccr.yaml - - ./common_patches/flash/flash_boot0s.yaml - - ../peripherals/tim/tim_ccm_v2.yaml - - ../peripherals/sai/sai.yaml - - ../peripherals/dma/dma2d_v1.yaml + - patches/tim/group.yaml + - patches/dbgmcu/l4_apb_fzr_rename.yaml + - patches/adc/adc_common_group_name.yaml + - patches/comp/l4xx_comp_reg_rename.yaml + - fields/comp/comp_l4x6.yaml + - fields/opamp/opamp_l4.yaml diff --git a/devices/stm32l552.yaml b/devices/stm32l552.yaml index 54e0e2e1d..77e77edf7 100644 --- a/devices/stm32l552.yaml +++ b/devices/stm32l552.yaml @@ -1,4 +1,344 @@ _svd: ../svd/stm32l552.svd +_derive: + ADC2: ADC1 + TIM5: TIM2 + SEC_TIM5: TIM2 + TIM7: TIM6 + TIM4: TIM3 + +_modify: + cpu: + name: CM33 + revision: r0p1 + endian: little + mpuPresent: "true" + fpuPresent: "true" + nvicPrioBits: 3 + vendorSystickConfig: "false" + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common_l4+.yaml + - fields/adc/adc_v3_common.yaml + CCR: + _modify: + DELAY: + bitOffset: 8 + bitWidth: 4 + +ADC1: + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + _modify: + AWDCH1CH: + name: AWD1CH + DIFSEL: + _merge: + DIFSEL: DIFSEL* + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +COMP: {} + +CRC: + POL: + _modify: + Polynomialcoefficients: + name: POL + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/l5.yaml + - collect/dac/v3.yaml + CR: + _merge: + - TSEL1? + - TSEL2? + +DBGMCU: {} + +DCB: {} + +DMA1: + _delete: CSELR + _include: + - fields/dma/v1.yaml + - collect/dma/l5.yaml + +DMAMUX1: + C5CR: + _modify: + OIE: + name: SOIE + RGCFR: + _strip: CS + _prefix: C + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +DFSDM1: + _include: + - patches/dfsdm/split.yaml + - patches/dfsdm/jextsel.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _include: + - collect/flash/secbbr.yaml + +FMC: + _strip: FMC_ + _modify: + BCR[2-4]: + description: SRAM/NOR-Flash chip-select control register %s + BTR?: + description: SRAM/NOR-flash chip-select timing registers for bank %s + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABCH]: + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCH]: + _include: collect/gpio/v2_derive.yaml + +GTZC_MPCBB[12]: + _strip: MPCBB?_ + +GTZC_TZIC: {} + +GTZC_TZSC: + _strip: TZSC_ + +HASH: {} + +I2C1: {} + +ICACHE: {} + +IWDG: + _include: patches/16bit.yaml + +LPTIM1: + _include: + - fields/lptim/v2.yaml + +LPUART1: + _include: + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OCTOSPI1: + DCR1: + _modify: + MTYP: + bitWidth: 3 + _include: + - patches/octospi/ddm.yaml + - fields/octospi/l5.yaml + +OPAMP: {} + +PWR: {} + +RCC: + _include: + - fields/rcc/rcc_l5.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _delete: [SDMMC_VER, SDMMC_ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM[18]: + CR2: + _modify: + OIS6: + bitOffset: 18 + OIS5: + bitOffset: 16 + _include: + - patches/tim/sms.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _add: + _interrupts: + TIM5: + description: TIM5 global interrupt + value: 48 + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _delete: + _interrupts: + - TIM5 + +TIM6: + CNT: + _modify: + CNT_bit0: + name: CNT + ARR: + _modify: + ARR_bit0: + name: ARR + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + _include: - - common_patches/dma_interrupt_names.yaml + - patches/dma/interrupt_names.yaml + - patches/icache/l5.yaml + - collect/icache/crr.yaml + - patches/adc/adc_common_group_name.yaml diff --git a/devices/stm32l562.yaml b/devices/stm32l562.yaml index a952458e2..5dd971cfd 100644 --- a/devices/stm32l562.yaml +++ b/devices/stm32l562.yaml @@ -1,4 +1,360 @@ _svd: ../svd/stm32l562.svd +_derive: + ADC2: ADC1 + TIM5: TIM2 + SEC_TIM5: TIM2 + TIM7: TIM6 + TIM4: TIM3 + +_modify: + cpu: + name: CM33 + revision: r0p1 + endian: little + mpuPresent: "true" + fpuPresent: "true" + nvicPrioBits: 3 + vendorSystickConfig: "false" + +ADC_Common: + _include: + - patches/adc/l4+common.yaml + - fields/adc/adc_v3_common.yaml + - fields/adc/adc_v3_common_l4+.yaml + CCR: + _modify: + DELAY: + bitOffset: 8 + bitWidth: 4 + +ADC1: + _include: + - patches/adc/split.yaml + - patches/adc/offset_en.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + CFGR: + _merge: EXTSEL* + _modify: + AWDCH1CH: + name: AWD1CH + DIFSEL: + _merge: + DIFSEL: DIFSEL* + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +AES: + SUSP?R: + _modify: + AES_SUSP?R: + name: SUSP + _include: + - fields/aes/v2.yaml + +COMP: {} + +CRC: + POL: + _modify: + Polynomialcoefficients: + name: POL + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/l5.yaml + - collect/dac/v3.yaml + CR: + _merge: + - TSEL1? + - TSEL2? + +DBGMCU: {} + +DCB: {} + +DFSDM1: + _include: + - patches/dfsdm/split.yaml + - patches/dfsdm/jextsel.yaml + - fields/dfsdm/v1+.yaml + - collect/dfsdm/v1.yaml + +DMA1: + _delete: CSELR + _include: + - fields/dma/v1.yaml + - collect/dma/l5.yaml + +DMAMUX1: + C5CR: + _modify: + OIE: + name: SOIE + RGCFR: + _strip: CS + _prefix: C + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/exti_rename.yaml + +FDCAN1: + _strip: FDCAN_ + +FLASH: + _include: + - collect/flash/secbbr.yaml + +FMC: + _strip: FMC_ + _modify: + BCR[2-4]: + description: SRAM/NOR-Flash chip-select control register %s + BTR?: + description: SRAM/NOR-flash chip-select timing registers for bank %s + _include: + - patches/fsmc/bcr_clean.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/bcr1.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPIO[ABCH]: + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCH]: + _include: collect/gpio/v2_derive.yaml + +GTZC_MPCBB[12]: + _strip: MPCBB?_ + _array: + VCTR*: + name: VCTR%s + +GTZC_TZIC: {} + +GTZC_TZSC: + _strip: TZSC_ + +HASH: {} + +I2C1: {} + +ICACHE: {} + +IWDG: + _include: patches/16bit.yaml + +LPTIM1: + _include: + - fields/lptim/v2.yaml + +LPUART1: + _include: + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/lp_wl.yaml + +OCTOSPI1: + DCR1: + _modify: + MTYP: + bitWidth: 3 + _include: + - patches/octospi/ddm.yaml + - fields/octospi/l5.yaml + +OPAMP: {} + +OTFDEC1: {} + +PKA: + _strip: PKA_ + +PWR: {} + +RCC: + _include: + - fields/rcc/rcc_l5.yaml + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SDMMC1: + _strip: SDMMC_ + _delete: [SDMMC_VER, SDMMC_ID] + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/respr.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM[18]: + CR2: + _modify: + OIS6: + bitOffset: 18 + OIS5: + bitOffset: 16 + _include: + - patches/tim/sms.yaml + - patches/tim/icpsc.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/rep_16b.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM8: + _include: collect/tim/tim8_derive.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM5: + _add: + _interrupts: + TIM5: + description: TIM5 global interrupt + value: 48 + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/v2/add_uifcpy.yaml + - patches/tim/tim_ch_16bit_l.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM4: + _delete: + _interrupts: + - TIM5 + +TIM6: + CNT: + _modify: + CNT_bit0: + name: CNT + ARR: + _modify: + ARR_bit0: + name: ARR + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/cfgr_missing_r.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + +VREFBUF: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + _include: - - common_patches/dma_interrupt_names.yaml + - patches/dma/interrupt_names.yaml + - patches/icache/l5.yaml + - collect/icache/crr.yaml + - patches/adc/adc_common_group_name.yaml diff --git a/devices/stm32mp153.yaml b/devices/stm32mp153.yaml new file mode 100644 index 000000000..782b8e44c --- /dev/null +++ b/devices/stm32mp153.yaml @@ -0,0 +1,51 @@ +_svd: ../svd/stm32mp153.svd + +_modify: + name: STM32MP153 + cpu: + name: CM4 + revision: r0p1 + endian: little + mpuPresent: "false" + fpuPresent: "true" + nvicPrioBits: 4 + vendorSystickConfig: "false" + +IWDG1: + _strip: IWDG_ + _modify: + "KR,PR,RLR,SR,WINR": + size: 16 + +RCC: + BDCR: + _modify: + DIGBYP: + access: read-write + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/fsdef-rw.yaml + +SPI?: + _include: patches/spi/rxtxdr.yaml + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +WWDG1: + _strip: WWDG_ + _modify: + "CR,CFR,SR": + size: 16 + +_include: + - patches/mpu_unprefix_registers.yaml diff --git a/devices/stm32mp157.yaml b/devices/stm32mp157.yaml index 477e0a0e2..ba5e6459a 100644 --- a/devices/stm32mp157.yaml +++ b/devices/stm32mp157.yaml @@ -2,3 +2,57 @@ _svd: ../svd/stm32mp157.svd _modify: name: STM32MP157 + cpu: + name: CM4 + revision: r0p1 + endian: little + mpuPresent: "false" + fpuPresent: "true" + nvicPrioBits: 4 + vendorSystickConfig: "false" + DSIHOST1: + name: DSI + +DSI: + _strip: DSI_ + _include: + - collect/dsi/isr.yaml + +IWDG1: + _strip: IWDG_ + _modify: + "KR,PR,RLR,SR,WINR": + size: 16 + +RCC: + BDCR: + _modify: + DIGBYP: + access: read-write + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _strip: SAI_ + _include: + - patches/sai/fsdef-rw.yaml + +SPI?: + _include: patches/spi/rxtxdr.yaml + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +WWDG1: + _strip: WWDG_ + _modify: + "CR,CFR,SR": + size: 16 + +_include: + - patches/mpu_unprefix_registers.yaml diff --git a/devices/stm32n645.yaml b/devices/stm32n645.yaml new file mode 100644 index 000000000..ea3c614f0 --- /dev/null +++ b/devices/stm32n645.yaml @@ -0,0 +1,210 @@ +_svd: ../svd/stm32n645.svd + +_clear_fields: "*" + +ADC1: + _strip: ADC_ + +ADC12: + _strip: ADC12_ + +ADF: + _strip: ADF_ + +BSEC: + _strip: BSEC_ + _include: + - collect/bsec/n6.yaml + +CACHEAXI: + _strip: CACHEAXI_ + +CRC: + _strip: CRC_ + +CSI: + _strip: CSI_ + +DBGMCU: + _strip: DBGMCU_ + +DCMI: + _strip: DCMI_ + +DCMIPP: + _strip: DCMIPP_ + +DLYBSD: + _strip: DLYBSD_ + +DMA2D: + _strip: DMA2D_ + +DTS: + _strip: DTS_ + +ETH: + _strip: ETH_ + +EXTI: + _strip: EXTI_ + +FDCAN1: + _strip: FDCAN_ + +FMC1: + _strip: FMC_ + +GFXMMU: + _strip: GFXMMU_ + _include: + - collect/gfxmmu/lut.yaml + +GFXTIM: + _strip: GFXTIM_ + +GPDMA: + _strip: GPDMA_ + +GPIO[A-Q]: + _strip: GPIO?_ + +HASH: + _strip: HASH_ + +HDP: + _strip: HDP_ + +HPDMA: + _strip: HPDMA_ + +I2C1: + _strip: I2C_ + +I3C1: + _strip: I3C_ + +IAC: + _strip: IAC_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + +JPEG: + _strip: JPEG_ + +LPTIM[12345]: + _strip: LPTIM?_ + +LPUART1: + _strip: LPUART_ + +LTDC: + _strip: LTDC_ + +MDF1: + _strip: MDF_ + +MDIOS: + _strip: MDIOS_ + +OTG1: + _strip: OTG_ + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + +RIFSC: + _strip: RIFSC_ + +RISAF: + _strip: RISAF_ + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + +SAI1: + _strip: SAI_ + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + +SPDIFRX: + _strip: SPDIFRX_ + +SPI1: + _strip: SPI_ + +SYSCFG: + _strip: SYSCFG_ + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM*: + _strip: + - TIM?_ + - TIM??_ + +TIM[18]: {} + +TIM[25]: {} + +TIM[34]: {} + +"TIM[67],TIM18": {} + +"TIM9,TIM12": {} + +TIM1[34]: {} + +TIM15: {} + +TIM1[67]: {} + +UCPD: + _strip: UCPD_ + +USART1: + _strip: USART_ + +VENC: + _strip: VENC_ + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +XSPI1: + _strip: XSPI_ + +XSPIM: + _strip: XSPIM_ diff --git a/devices/stm32n647.yaml b/devices/stm32n647.yaml new file mode 100644 index 000000000..559fb6162 --- /dev/null +++ b/devices/stm32n647.yaml @@ -0,0 +1,210 @@ +_svd: ../svd/stm32n647.svd + +_clear_fields: "*" + +ADC1: + _strip: ADC_ + +ADC12: + _strip: ADC12_ + +ADF: + _strip: ADF_ + +BSEC: + _strip: BSEC_ + _include: + - collect/bsec/n6.yaml + +CACHEAXI: + _strip: CACHEAXI_ + +CRC: + _strip: CRC_ + +CSI: + _strip: CSI_ + +DBGMCU: + _strip: DBGMCU_ + +DCMI: + _strip: DCMI_ + +DCMIPP: + _strip: DCMIPP_ + +DLYBSD: + _strip: DLYBSD_ + +DMA2D: + _strip: DMA2D_ + +DTS: + _strip: DTS_ + +ETH: + _strip: ETH_ + +EXTI: + _strip: EXTI_ + +FDCAN1: + _strip: FDCAN_ + +FMC1: + _strip: FMC_ + +GFXMMU: + _strip: GFXMMU_ + _include: + - collect/gfxmmu/lut.yaml + +GFXTIM: + _strip: GFXTIM_ + +GPDMA: + _strip: GPDMA_ + +GPIO[A-Q]: + _strip: GPIO?_ + +HASH: + _strip: HASH_ + +HDP: + _strip: HDP_ + +HPDMA: + _strip: HPDMA_ + +I2C1: + _strip: I2C_ + +I3C1: + _strip: I3C_ + +IAC: + _strip: IAC_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + +JPEG: + _strip: JPEG_ + +LPTIM[12345]: + _strip: LPTIM?_ + +LPUART1: + _strip: LPUART_ + +LTDC: + _strip: LTDC_ + +MDF1: + _strip: MDF_ + +MDIOS: + _strip: MDIOS_ + +OTG1: + _strip: OTG_ + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + +RIFSC: + _strip: RIFSC_ + +RISAF: + _strip: RISAF_ + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + +SAI1: + _strip: SAI_ + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + +SPDIFRX: + _strip: SPDIFRX_ + +SPI1: + _strip: SPI_ + +SYSCFG: + _strip: SYSCFG_ + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM*: + _strip: + - TIM?_ + - TIM??_ + +TIM[18]: {} + +TIM[25]: {} + +TIM[34]: {} + +"TIM[67],TIM18": {} + +"TIM9,TIM12": {} + +TIM1[34]: {} + +TIM15: {} + +TIM1[67]: {} + +UCPD: + _strip: UCPD_ + +USART1: + _strip: USART_ + +VENC: + _strip: VENC_ + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +XSPI1: + _strip: XSPI_ + +XSPIM: + _strip: XSPIM_ diff --git a/devices/stm32n655.yaml b/devices/stm32n655.yaml new file mode 100644 index 000000000..db95665e7 --- /dev/null +++ b/devices/stm32n655.yaml @@ -0,0 +1,222 @@ +_svd: ../svd/stm32n655.svd + +_clear_fields: "*" + +ADC1: + _strip: ADC_ + +ADC12: + _strip: ADC12_ + +ADF: + _strip: ADF_ + +BSEC: + _strip: BSEC_ + _include: + - collect/bsec/n6.yaml + +CACHEAXI: + _strip: CACHEAXI_ + +CRC: + _strip: CRC_ + +CRYP: + _strip: CRYP_ + +CSI: + _strip: CSI_ + +DBGMCU: + _strip: DBGMCU_ + +DCMI: + _strip: DCMI_ + +DCMIPP: + _strip: DCMIPP_ + +DLYBSD: + _strip: DLYBSD_ + +DMA2D: + _strip: DMA2D_ + +DTS: + _strip: DTS_ + +ETH: + _strip: ETH_ + +EXTI: + _strip: EXTI_ + +FDCAN1: + _strip: FDCAN_ + +FMC1: + _strip: FMC_ + +GFXMMU: + _strip: GFXMMU_ + _include: + - collect/gfxmmu/lut.yaml + +GFXTIM: + _strip: GFXTIM_ + +GPDMA: + _strip: GPDMA_ + +GPIO[A-Q]: + _strip: GPIO?_ + +HASH: + _strip: HASH_ + +HDP: + _strip: HDP_ + +HPDMA: + _strip: HPDMA_ + +I2C1: + _strip: I2C_ + +I3C1: + _strip: I3C_ + +IAC: + _strip: IAC_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + +JPEG: + _strip: JPEG_ + +LPTIM[12345]: + _strip: LPTIM?_ + +LPUART1: + _strip: LPUART_ + +LTDC: + _strip: LTDC_ + +MCE1: + _strip: MCE_ + +MDF1: + _strip: MDF_ + +MDIOS: + _strip: MDIOS_ + +OTG1: + _strip: OTG_ + +PKA: + _strip: PKA_ + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + +RIFSC: + _strip: RIFSC_ + +RISAF: + _strip: RISAF_ + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + +SAES: + _strip: SAES_ + +SAI1: + _strip: SAI_ + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + +SPDIFRX: + _strip: SPDIFRX_ + +SPI1: + _strip: SPI_ + +SYSCFG: + _strip: SYSCFG_ + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM*: + _strip: + - TIM?_ + - TIM??_ + +TIM[18]: {} + +TIM[25]: {} + +TIM[34]: {} + +"TIM[67],TIM18": {} + +"TIM9,TIM12": {} + +TIM1[34]: {} + +TIM15: {} + +TIM1[67]: {} + +UCPD: + _strip: UCPD_ + +USART1: + _strip: USART_ + +VENC: + _strip: VENC_ + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +XSPI1: + _strip: XSPI_ + +XSPIM: + _strip: XSPIM_ diff --git a/devices/stm32n657.yaml b/devices/stm32n657.yaml new file mode 100644 index 000000000..a8de3ffc8 --- /dev/null +++ b/devices/stm32n657.yaml @@ -0,0 +1,222 @@ +_svd: ../svd/stm32n657.svd + +_clear_fields: "*" + +ADC1: + _strip: ADC_ + +ADC12: + _strip: ADC12_ + +ADF: + _strip: ADF_ + +BSEC: + _strip: BSEC_ + _include: + - collect/bsec/n6.yaml + +CACHEAXI: + _strip: CACHEAXI_ + +CRC: + _strip: CRC_ + +CRYP: + _strip: CRYP_ + +CSI: + _strip: CSI_ + +DBGMCU: + _strip: DBGMCU_ + +DCMI: + _strip: DCMI_ + +DCMIPP: + _strip: DCMIPP_ + +DLYBSD: + _strip: DLYBSD_ + +DMA2D: + _strip: DMA2D_ + +DTS: + _strip: DTS_ + +ETH: + _strip: ETH_ + +EXTI: + _strip: EXTI_ + +FDCAN1: + _strip: FDCAN_ + +FMC1: + _strip: FMC_ + +GFXMMU: + _strip: GFXMMU_ + _include: + - collect/gfxmmu/lut.yaml + +GFXTIM: + _strip: GFXTIM_ + +GPDMA: + _strip: GPDMA_ + +GPIO[A-Q]: + _strip: GPIO?_ + +HASH: + _strip: HASH_ + +HDP: + _strip: HDP_ + +HPDMA: + _strip: HPDMA_ + +I2C1: + _strip: I2C_ + +I3C1: + _strip: I3C_ + +IAC: + _strip: IAC_ + +ICACHE: + _strip: ICACHE_ + +IWDG: + _strip: IWDG_ + +JPEG: + _strip: JPEG_ + +LPTIM[12345]: + _strip: LPTIM?_ + +LPUART1: + _strip: LPUART_ + +LTDC: + _strip: LTDC_ + +MCE1: + _strip: MCE_ + +MDF1: + _strip: MDF_ + +MDIOS: + _strip: MDIOS_ + +OTG1: + _strip: OTG_ + +PKA: + _strip: PKA_ + +PSSI: + _strip: PSSI_ + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + +RAMCFG: + _strip: RAMCFG_ + +RCC: + _strip: RCC_ + +RIFSC: + _strip: RIFSC_ + +RISAF: + _strip: RISAF_ + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + +SAES: + _strip: SAES_ + +SAI1: + _strip: SAI_ + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + +SPDIFRX: + _strip: SPDIFRX_ + +SPI1: + _strip: SPI_ + +SYSCFG: + _strip: SYSCFG_ + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM*: + _strip: + - TIM?_ + - TIM??_ + +TIM[18]: {} + +TIM[25]: {} + +TIM[34]: {} + +"TIM[67],TIM18": {} + +"TIM9,TIM12": {} + +TIM1[34]: {} + +TIM15: {} + +TIM1[67]: {} + +UCPD: + _strip: UCPD_ + +USART1: + _strip: USART_ + +VENC: + _strip: VENC_ + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml + +XSPI1: + _strip: XSPI_ + +XSPIM: + _strip: XSPIM_ diff --git a/devices/stm32u031.yaml b/devices/stm32u031.yaml new file mode 100644 index 000000000..4ac94f833 --- /dev/null +++ b/devices/stm32u031.yaml @@ -0,0 +1,194 @@ +_svd: ../svd/stm32u031.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + +_modify: + TIM?*: + groupName: TIM + +ADC: + _strip: ADC_ + +COMP1: {} + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/u0.yaml + - collect/dac/v3.yaml + +DBGMCU: + _strip: DBGMCU_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _strip: EXTI_ + +FLASH: + _strip: FLASH_ + +GPIO[ABCDEF]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCDEF]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/u0.yaml + +IWDG: + _strip: IWDG_ + +LPTIM[12]: + _strip: LPTIM?_ + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: {} + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SYSCFG: + _strip: SYSCFG_ + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM??: + _strip: TIM??_ + +TIM1: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TSC: + _strip: TSC_ + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u073.yaml b/devices/stm32u073.yaml new file mode 100644 index 000000000..02b8ad36f --- /dev/null +++ b/devices/stm32u073.yaml @@ -0,0 +1,213 @@ +_svd: ../svd/stm32u073.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + +_modify: + LCD: + groupName: LCD + TIM?*: + groupName: TIM + +ADC: + _strip: ADC_ + +COMP1: {} + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/u0.yaml + - collect/dac/v3.yaml + +DBGMCU: + _strip: DBGMCU_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _strip: EXTI_ + +FLASH: + _strip: FLASH_ + +GPIO[ABCDEF]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCDEF]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/u0.yaml + +IWDG: + _strip: IWDG_ + +LCD: + _delete: LCD_RAM* + _strip: LCD_ + _include: + - patches/lcd/ram_segment_48.yaml + +LPTIM[123]: + _strip: LPTIM?_ + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: {} + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SYSCFG: + _strip: SYSCFG_ + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM??: + _strip: TIM??_ + +TIM1: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TSC: + _strip: TSC_ + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u083.yaml b/devices/stm32u083.yaml new file mode 100644 index 000000000..fe1434306 --- /dev/null +++ b/devices/stm32u083.yaml @@ -0,0 +1,216 @@ +_svd: ../svd/stm32u083.svd + +_clear_fields: "*" + +_derive: + TIM7: TIM6 + +_modify: + LCD: + groupName: LCD + TIM?*: + groupName: TIM + +ADC: + _strip: ADC_ + +AES: + _strip: AES_ + +COMP: {} + +CRC: + _strip: CRC_ + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _strip: CRS_ + _include: + - fields/crs/crs.yaml + +DAC: + _strip: DAC_ + _include: + - fields/dac/u0.yaml + - collect/dac/v3.yaml + +DBGMCU: + _strip: DBGMCU_ + +DMA1: + _strip: DMA_ + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX: + _strip: DMAMUX_ + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _strip: EXTI_ + +FLASH: + _strip: FLASH_ + +GPIO[ABCDEF]: + _strip: GPIO?_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCDEF]: + _include: collect/gpio/v2r_derive.yaml + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/u0.yaml + +IWDG: + _strip: IWDG_ + +LCD: + _delete: LCD_RAM* + _strip: LCD_ + _include: + - patches/lcd/ram_segment_48.yaml + +LPTIM[123]: + _strip: LPTIM?_ + +LPUART1: + _strip: LPUART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/lp_wl.yaml + +OPAMP: {} + +PWR: + _strip: PWR_ + +RCC: + _strip: RCC_ + +RNG: + _strip: RNG_ + _include: + - fields/rng/v2.yaml + +RTC: + _strip: RTC_ + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SYSCFG: + _strip: SYSCFG_ + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM?: + _strip: TIM?_ + +TIM??: + _strip: TIM??_ + +TIM1: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/v2/oc5m_bit3.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v2/tim2.yaml + - collect/tim/ccr.yaml + +TIM3: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/ccmr2_alternate.yaml + - patches/tim/v2/ocm_bit3.yaml + - fields/tim/v2/tim3.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v2/tim6.yaml + +TIM15: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr1_alternate.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v2/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + _include: + - patches/tim/ccmr1_alternate.yaml + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TSC: + _strip: TSC_ + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _strip: USART_ + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/merge_CR3_WUS_field.yaml + - fields/usart/v4/B.yaml + +USB: + _strip: USB_ + _include: + - fields/usb/v3.yaml + - collect/usb/chepr.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _strip: WWDG_ + _include: + - patches/16bit_with_mask.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u535.yaml b/devices/stm32u535.yaml new file mode 100644 index 000000000..f83e918b4 --- /dev/null +++ b/devices/stm32u535.yaml @@ -0,0 +1,321 @@ +_svd: ../svd/stm32u535.svd + +_clear_fields: "*" + +_modify: + ICache: + name: ICACHE + +ADC12_Common: + _strip: ADC12_ + _include: + - fields/adc/adc_u5_common.yaml + CCR: + _delete: [DAMDF, DELAY, DUAL] + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_12.yaml + - collect/adc/v3.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC4: + _strip: ADC_ + _include: + - patches/adc/u5_access.yaml + - patches/adc/u5_vsensesel.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_4.yaml + - fields/adc/adc_u5_common.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + PWR: + name: PWRR + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +ADF1: + _strip: ADF_ + +COMP: {} + +CORDIC: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/u5.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCACHE: + _strip: DCACHE_ + +DCB: {} + +DCMI: + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS: + _strip: DLYB_ + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/exti_u5.yaml + +FDCAN1_RAM: + _strip: FDCAN_ + +FMAC: {} + +FLASH: + _strip: FLASH_ + +GPDMA1: + _strip: GPDMA_ + _include: + - patches/dma/gpdma_u5_tr1.yaml + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABCH]: + _strip: GPIO_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCH]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[12]: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC2_MPCBB4: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC[12]_TZIC: {} + +GTZC1_TZSC: + _strip: TZSC_ + +GTZC2_TZSC: {} + +HASH: {} + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +ICACHE: + _strip: ICACHE_ + +IWDG: + _include: patches/16bit.yaml + +LPDMA1: + _strip: LPDMA_ + _include: + - collect/dma/lpdma.yaml + +LPGPIO1: + _strip: LPGPIO_ + _include: + - collect/lpgpio/lp.yaml + +LPTIM[14]: {} + +LPUART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + # TODO: fields + +MDF1: + _strip: MDF_ + _include: + - collect/mdf/u5.yaml + +OPAMP: {} + +OCTOSPI1: + _include: + - patches/octospi/u535_u545.yaml + - fields/octospi/u5.yaml + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _delete: [PUCRF, PUCRI, PUCRJ] + CR1: + _delete: SRAM5PD + VOSR: + _delete: [USBBOOSTEN, USBPWREN, USBBOOSTRDY] + UCPDR: + _delete: [UCPD_STBY, UCPD_DBDIS] + CR4: + _delete: SRAM5PDS* + _include: + - patches/pwr/add_cr5.yaml + - fields/pwr/pwr_u5.yaml + +RAMCFG: {} + +RCC: + _strip: RCC_ + _include: + - fields/rcc/rcc_u5.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/resp.yaml + - collect/sdio/fifo.yaml + +SPI1: + CFG1: + _add: + DSIZE: + description: Number of bits in at single SPI data frame + bitOffset: 0 + bitWidth: 5 + access: read-write + _include: + - patches/spi/u5.yaml + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + CCMR2_Output: + _modify: + CC3S_1_0: + name: CC3S + CC4S_1_0: + name: CC4S + OC3M_2_0: + name: OC3M + OC4M_3_0: + name: OC4M + OC4M_bit3: + name: OC4M_3 + CCMR3_Output: + _modify: + OC6M: + name: OC6M_3 + OC6M1: + name: OC6M + OC5M1: + name: OC5M + OC5M2: + name: OC5M_3 + _include: + - patches/tim/mms.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm1_bit3.yaml + - patches/tim/icpsc.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - patches/tim/v3/add_dithen.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/C.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u545.yaml b/devices/stm32u545.yaml new file mode 100644 index 000000000..928b48ec5 --- /dev/null +++ b/devices/stm32u545.yaml @@ -0,0 +1,335 @@ +_svd: ../svd/stm32u545.svd + +_clear_fields: "*" + +_modify: + ICache: + name: ICACHE + +ADC12_Common: + _strip: ADC12_ + _include: + - fields/adc/adc_u5_common.yaml + CCR: + _delete: [DAMDF, DELAY, DUAL] + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_12.yaml + - collect/adc/v3.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC4: + _strip: ADC_ + _include: + - patches/adc/u5_access.yaml + - patches/adc/u5_vsensesel.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_4.yaml + - fields/adc/adc_u5_common.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + PWR: + name: PWRR + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +ADF1: + _strip: ADF_ + +AES: + SUSP?R: + _modify: + SUSP?: + name: SUSP + _include: + - fields/aes/v3.yaml + +COMP: {} + +CORDIC: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/u5.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCACHE: + _strip: DCACHE_ + +DCB: {} + +DCMI: + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS: + _strip: DLYB_ + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/exti_u5.yaml + +FDCAN1_RAM: + _strip: FDCAN_ + +FMAC: {} + +FLASH: + _strip: FLASH_ + +GPDMA1: + _strip: GPDMA_ + _include: + - patches/dma/gpdma_u5_tr1.yaml + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABCH]: + _strip: GPIO_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCH]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[12]: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC2_MPCBB4: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC[12]_TZIC: {} + +GTZC1_TZSC: + _strip: TZSC_ + +GTZC2_TZSC: {} + +HASH: {} + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +ICACHE: + _strip: ICACHE_ + +IWDG: + _include: patches/16bit.yaml + +LPDMA1: + _strip: LPDMA_ + _include: + - collect/dma/lpdma.yaml + +LPGPIO1: + _strip: LPGPIO_ + _include: + - collect/lpgpio/lp.yaml + +LPTIM[14]: {} + +LPUART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + # TODO: fields + +MDF1: + _strip: MDF_ + _include: + - collect/mdf/u5.yaml + +OPAMP: {} + +OTFDEC1: {} + +OCTOSPI1: + _include: + - patches/octospi/u535_u545.yaml + - fields/octospi/u5.yaml + +PKA: {} + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _delete: [PUCRF, PUCRI, PUCRJ] + CR1: + _delete: SRAM5PD + VOSR: + _delete: [USBBOOSTEN, USBPWREN, USBBOOSTRDY] + UCPDR: + _delete: [UCPD_STBY, UCPD_DBDIS] + CR4: + _delete: SRAM5PDS* + _include: + - patches/pwr/add_cr5.yaml + - fields/pwr/pwr_u5.yaml + +RAMCFG: {} + +RCC: + _strip: RCC_ + _include: + - fields/rcc/rcc_u5.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAES: {} + +SAI1: + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/resp.yaml + - collect/sdio/fifo.yaml + +SPI1: + CFG1: + _add: + DSIZE: + description: Number of bits in at single SPI data frame + bitOffset: 0 + bitWidth: 5 + access: read-write + _include: + - patches/spi/u5.yaml + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + CCMR2_Output: + _modify: + CC3S_1_0: + name: CC3S + CC4S_1_0: + name: CC4S + OC3M_2_0: + name: OC3M + OC4M_3_0: + name: OC4M + OC4M_bit3: + name: OC4M_3 + CCMR3_Output: + _modify: + OC6M: + name: OC6M_3 + OC6M1: + name: OC6M + OC5M1: + name: OC5M + OC5M2: + name: OC5M_3 + _include: + - patches/tim/mms.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm1_bit3.yaml + - patches/tim/icpsc.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - patches/tim/v3/add_dithen.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/C.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u575.yaml b/devices/stm32u575.yaml new file mode 100644 index 000000000..3e0a3d7d7 --- /dev/null +++ b/devices/stm32u575.yaml @@ -0,0 +1,383 @@ +_svd: ../svd/stm32u575.svd + +_clear_fields: "*" + +_copy: + LPGPIO1: + from: ../svd/stm32u535.svd:LPGPIO1 + +# This SVD calls this ADC12, but ADC12_Common in most others +_modify: + ADC12: + name: ADC12_Common + ICache: + name: ICACHE + +ADC12_Common: + _strip: ADC12_ + _include: + - fields/adc/adc_u5_common.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_12.yaml + - collect/adc/v3.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC4: + _strip: ADC_ + _include: + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_4.yaml + - fields/adc/adc_u5_common.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + PWR: + name: PWRR + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +ADF1: + _strip: ADF_ + +COMP: {} + +CORDIC: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/u5.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCACHE: + _strip: DCACHE_ + +DCB: {} + +DCMI: + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DMA2D: + _include: + - fields/dma/dma2d_v2.yaml + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/exti_u5.yaml + +FDCAN1_RAM: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/u5.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABCHI]: + _strip: GPIO_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHI]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[123]: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC2_MPCBB4: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC[12]_TZIC: {} + +GTZC1_TZSC: + _strip: TZSC_ + +GTZC2_TZSC: {} + +HASH: {} + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +ICACHE: + _strip: ICACHE_ + +IWDG: + _include: patches/16bit.yaml + +LPDMA1: + _strip: LPDMA_ + _include: + - collect/dma/lpdma.yaml + +LPGPIO1: + _strip: LPGPIO_ + _include: + - collect/lpgpio/lp.yaml + +LPTIM[14]: {} + +LPUART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + # TODO: fields + +MDF1: + _strip: MDF_ + _include: + - collect/mdf/u5.yaml + +OCTOSPI[12]: + _include: + - patches/octospi/u5.yaml + - fields/octospi/u5.yaml + +OPAMP: {} + +OTFDEC1: {} + +OTG_FS: {} + +PKA: {} + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + CR2: + _remove: PKARAMPDS + _add: + CR4: + displayName: PWR control register 4 + addressOffset: 0xA8 + size: 0x20 + resetValue: 0x00000000 + access: read-write + fields: + SRAM1PDS4: + bitOffset: 0 + bitWidth: 1 + SRAM1PDS5: + bitOffset: 1 + bitWidth: 1 + SRAM1PDS6: + bitOffset: 2 + bitWidth: 1 + SRAM1PDS7: + bitOffset: 3 + bitWidth: 1 + SRAM1PDS8: + bitOffset: 4 + bitWidth: 1 + SRAM1PDS9: + bitOffset: 5 + bitWidth: 1 + SRAM1PDS10: + bitOffset: 6 + bitWidth: 1 + SRAM1PDS11: + bitOffset: 7 + bitWidth: 1 + SRAM1PDS12: + bitOffset: 8 + bitWidth: 1 + SRAM3PDS9: + bitOffset: 10 + bitWidth: 1 + SRAM3PDS10: + bitOffset: 11 + bitWidth: 1 + SRAM3PDS11: + bitOffset: 12 + bitWidth: 1 + SRAM3PDS12: + bitOffset: 13 + bitWidth: 1 + SRAM3PDS13: + bitOffset: 14 + bitWidth: 1 + _include: + - patches/pwr/add_cr5.yaml + - fields/pwr/pwr_u5.yaml + +RAMCFG: {} + +RCC: + _strip: RCC_ + _include: + - fields/rcc/rcc_u5.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAES: {} + +SAI1: + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/resp.yaml + - collect/sdio/fifo.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + +SYSCFG: {} + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _strip: TIM1_ + CCMR2_Output: + _modify: + CC3S_1_0: + name: CC3S + CC4S_1_0: + name: CC4S + OC3M_2_0: + name: OC3M + OC4M_3_0: + name: OC4M + OC4M_bit3: + name: OC4M_3 + _include: + - patches/tim/mms.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm1_bit3.yaml + - patches/tim/v2/oc5m.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - patches/tim/v3/add_dithen.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/C.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u585.yaml b/devices/stm32u585.yaml new file mode 100644 index 000000000..cd2305e4d --- /dev/null +++ b/devices/stm32u585.yaml @@ -0,0 +1,390 @@ +_svd: ../svd/stm32u585.svd + +_clear_fields: "*" + +_copy: + LPGPIO1: + from: ../svd/stm32u535.svd:LPGPIO1 + +# This SVD calls this ADC12, but ADC12_Common in most others +_modify: + ADC12: + name: ADC12_Common + ICache: + name: ICACHE + +ADC12_Common: + _strip: ADC12_ + _include: + - fields/adc/adc_u5_common.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_12.yaml + - collect/adc/v3.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC4: + _strip: ADC_ + _include: + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_4.yaml + - fields/adc/adc_u5_common.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + PWR: + name: PWRR + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +ADF1: + _strip: ADF_ + +AES: + SUSP?R: + _modify: + SUSP?: + name: SUSP + _include: + - fields/aes/v3.yaml + +COMP: {} + +CORDIC: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/u5.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCACHE: + _strip: DCACHE_ + +DCB: {} + +DCMI: + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DMA2D: + _include: + - fields/dma/dma2d_v2.yaml + - fields/dma/dma2d_v2.yaml + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/exti_u5.yaml + +FDCAN1_RAM: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/u5.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABCHI]: + _strip: GPIO_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHI]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[123]: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC2_MPCBB4: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC[12]_TZIC: {} + +GTZC1_TZSC: + _strip: TZSC_ + +GTZC2_TZSC: {} + +HASH: {} + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +ICACHE: + _strip: ICACHE_ + +IWDG: + _include: patches/16bit.yaml + +LPDMA1: + _strip: LPDMA_ + _include: + - collect/dma/lpdma.yaml + +LPGPIO1: + _strip: LPGPIO_ + _include: + - collect/lpgpio/lp.yaml + +LPTIM[14]: {} + +LPUART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + # TODO: fields + +MDF1: + _strip: MDF_ + _include: + - collect/mdf/u5.yaml + +OCTOSPI[12]: + _include: + - patches/octospi/u5.yaml + - fields/octospi/u5.yaml + +OPAMP: {} + +OTFDEC1: {} + +OTG_FS: {} + +PKA: {} + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + _add: + CR4: + displayName: PWR control register 4 + addressOffset: 0xA8 + size: 0x20 + resetValue: 0x00000000 + access: read-write + fields: + SRAM1PDS4: + bitOffset: 0 + bitWidth: 1 + SRAM1PDS5: + bitOffset: 1 + bitWidth: 1 + SRAM1PDS6: + bitOffset: 2 + bitWidth: 1 + SRAM1PDS7: + bitOffset: 3 + bitWidth: 1 + SRAM1PDS8: + bitOffset: 4 + bitWidth: 1 + SRAM1PDS9: + bitOffset: 5 + bitWidth: 1 + SRAM1PDS10: + bitOffset: 6 + bitWidth: 1 + SRAM1PDS11: + bitOffset: 7 + bitWidth: 1 + SRAM1PDS12: + bitOffset: 8 + bitWidth: 1 + SRAM3PDS9: + bitOffset: 10 + bitWidth: 1 + SRAM3PDS10: + bitOffset: 11 + bitWidth: 1 + SRAM3PDS11: + bitOffset: 12 + bitWidth: 1 + SRAM3PDS12: + bitOffset: 13 + bitWidth: 1 + SRAM3PDS13: + bitOffset: 14 + bitWidth: 1 + _include: + - patches/pwr/add_cr5.yaml + - fields/pwr/pwr_u5.yaml + +RAMCFG: {} + +RCC: + _strip: RCC_ + _include: + - fields/rcc/rcc_u5.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAES: {} + +SAI1: + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/resp.yaml + - collect/sdio/fifo.yaml + +SPI1: + _strip: SPI_ + _include: + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + +SYSCFG: {} + +TAMP: + _strip: TAMP_ + _include: + - collect/rtc/tamp_bkpr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +TIM1: + _strip: TIM1_ + CCMR2_Output: + _modify: + CC3S_1_0: + name: CC3S + CC4S_1_0: + name: CC4S + OC3M_2_0: + name: OC3M + OC4M_3_0: + name: OC4M + OC4M_bit3: + name: OC4M_3 + _include: + - patches/tim/mms.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm1_bit3.yaml + - patches/tim/v2/oc5m.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - patches/tim/v2/arr_20bit.yaml + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - patches/tim/v3/add_dithen.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +UCPD1: + _strip: UCPD_ + _include: + - patches/ucpd/rxordseten_split.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/C.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u595.yaml b/devices/stm32u595.yaml new file mode 100644 index 000000000..d9c887abd --- /dev/null +++ b/devices/stm32u595.yaml @@ -0,0 +1,340 @@ +_svd: ../svd/stm32u595.svd + +_clear_fields: "*" + +_modify: + ICache: + name: ICACHE + +ADC12_Common: + _strip: ADC12_ + _include: + - fields/adc/adc_u5_common.yaml + - fields/adc/adc_u5_dual.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_12.yaml + - collect/adc/v3.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC4: + _strip: ADC_ + _include: + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - patches/adc/u5_vsensesel.yaml + - fields/adc/adc_u5_4.yaml + - fields/adc/adc_u5_common.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + PWR: + name: PWRR + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +ADF1: + _strip: ADF_ + +COMP: {} + +CORDIC: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/u5.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCACHE1: + _strip: DCACHE_ + +DCB: {} + +DCMI: + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DMA2D: + _include: + - fields/dma/dma2d_v2.yaml + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/exti_u5.yaml + +FDCAN1_RAM: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/u5.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - patches/dma/gpdma_u5_tr1.yaml + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABCHIJ]: + _strip: GPIO_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHIJ]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[1235]: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC2_MPCBB4: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC[12]_TZIC: {} + +GTZC1_TZSC: + _strip: TZSC_ + +GTZC2_TZSC: {} + +HASH: {} + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +ICACHE: + _strip: ICACHE_ + +IWDG: + _include: patches/16bit.yaml + +LPDMA1: + _strip: LPDMA_ + _include: + - collect/dma/lpdma.yaml + +LPGPIO1: + _strip: LPGPIO_ + _include: + - collect/lpgpio/lp.yaml + +LPTIM[14]: {} + +LPUART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + # TODO: fields + +MDF1: + _strip: MDF_ + _include: + - collect/mdf/u5.yaml + +OCTOSPI[12]: + _include: + - patches/octospi/u5.yaml + - fields/octospi/u5.yaml + +OPAMP: {} + +OTG_HS: {} + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + CR1: + _add: + FORCE_USBPWR: + bitOffset: 15 + bitWidth: 1 + CR2: + _remove: [GPRAMPDS, DSIRAMPDS, DC2RAMPDS] + VOSR: + _add: + VDD11USBDIS: + bitOffset: 21 + bitWidth: 1 + _include: + - patches/pwr/add_cr5.yaml + - fields/pwr/pwr_u5.yaml + +RAMCFG: {} + +RCC: + _strip: RCC_ + _include: + - fields/rcc/rcc_u5.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/resp.yaml + - collect/sdio/fifo.yaml + +SPI1: + _include: + - patches/spi/u5.yaml + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + CCMR2_Output: + _modify: + CC3S_1_0: + name: CC3S + CC4S_1_0: + name: CC4S + OC3M_2_0: + name: OC3M + OC4M_3_0: + name: OC4M + OC4M_bit3: + name: OC4M_3 + CCMR3_Output: + _modify: + OC6M: + name: OC6M_3 + OC6M1: + name: OC6M + OC5M1: + name: OC5M + OC5M2: + name: OC5M_3 + _include: + - patches/tim/mms.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm1_bit3.yaml + - patches/tim/icpsc.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - patches/tim/v3/add_dithen.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/C.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u599.yaml b/devices/stm32u599.yaml new file mode 100644 index 000000000..d202556a8 --- /dev/null +++ b/devices/stm32u599.yaml @@ -0,0 +1,355 @@ +_svd: ../svd/stm32u599.svd + +_clear_fields: "*" + +_modify: + ICache: + name: ICACHE + +ADC12_Common: + _strip: ADC12_ + _include: + - fields/adc/adc_u5_common.yaml + - fields/adc/adc_u5_dual.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_12.yaml + - collect/adc/v3.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC4: + _strip: ADC_ + _include: + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - patches/adc/u5_vsensesel.yaml + - fields/adc/adc_u5_4.yaml + - fields/adc/adc_u5_common.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + PWR: + name: PWRR + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +ADF1: + _strip: ADF_ + +COMP: {} + +CORDIC: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/u5.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCACHE1: + _strip: DCACHE_ + +DCB: {} + +DCMI: + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DMA2D: + _include: + - fields/dma/dma2d_v2.yaml + +DSI: + _strip: DSI_ + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/exti_u5.yaml + +FDCAN1_RAM: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/u5.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GFXMMU: + _strip: GFXMMU_ + _include: + - collect/gfxmmu/lut.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - patches/dma/gpdma_u5_tr1.yaml + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABCHIJ]: + _strip: GPIO_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHIJ]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[1235]: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC2_MPCBB4: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC[12]_TZIC: {} + +GTZC1_TZSC: + _strip: TZSC_ + +GTZC2_TZSC: {} + +HASH: {} + +HSPI1: + _strip: HSPI_ + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +ICACHE: + _strip: ICACHE_ + +IWDG: + _include: patches/16bit.yaml + +LPDMA1: + _strip: LPDMA_ + _include: + - collect/dma/lpdma.yaml + +LPGPIO1: + _strip: LPGPIO_ + _include: + - collect/lpgpio/lp.yaml + +LPTIM[14]: {} + +LPUART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + # TODO: fields + +LTDC: + _strip: LTDC_ + _include: + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDF1: + _strip: MDF_ + _include: + - collect/mdf/u5.yaml + +OCTOSPI[12]: + _include: + - patches/octospi/u5.yaml + - fields/octospi/u5.yaml + +OPAMP: {} + +OTG_HS: {} + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + CR1: + _add: + FORCE_USBPWR: + bitOffset: 15 + bitWidth: 1 + VOSR: + _add: + VDD11USBDIS: + bitOffset: 21 + bitWidth: 1 + _include: + - patches/pwr/add_cr5.yaml + - fields/pwr/pwr_u5.yaml + +RAMCFG: {} + +RCC: + _strip: RCC_ + _include: + - fields/rcc/rcc_u5.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAI1: + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/resp.yaml + - collect/sdio/fifo.yaml + +SPI1: + _include: + - patches/spi/u5.yaml + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + CCMR2_Output: + _modify: + CC3S_1_0: + name: CC3S + CC4S_1_0: + name: CC4S + OC3M_2_0: + name: OC3M + OC4M_3_0: + name: OC4M + OC4M_bit3: + name: OC4M_3 + CCMR3_Output: + _modify: + OC6M: + name: OC6M_3 + OC6M1: + name: OC6M + OC5M1: + name: OC5M + OC5M2: + name: OC5M_3 + _include: + - patches/tim/mms.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm1_bit3.yaml + - patches/tim/icpsc.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - patches/tim/v3/add_dithen.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/C.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u5a5.yaml b/devices/stm32u5a5.yaml new file mode 100644 index 000000000..6fa707d9e --- /dev/null +++ b/devices/stm32u5a5.yaml @@ -0,0 +1,354 @@ +_svd: ../svd/stm32u5a5.svd + +_clear_fields: "*" + +_modify: + ICache: + name: ICACHE + +ADC12_Common: + _strip: ADC12_ + _include: + - fields/adc/adc_u5_common.yaml + - fields/adc/adc_u5_dual.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_12.yaml + - collect/adc/v3.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC4: + _strip: ADC_ + _include: + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - patches/adc/u5_vsensesel.yaml + - fields/adc/adc_u5_4.yaml + - fields/adc/adc_u5_common.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + PWR: + name: PWRR + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +ADF1: + _strip: ADF_ + +AES: + SUSP?R: + _modify: + SUSP?: + name: SUSP + _include: + - fields/aes/v3.yaml + +COMP: {} + +CORDIC: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/u5.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCACHE1: + _strip: DCACHE_ + +DCB: {} + +DCMI: + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DMA2D: + _include: + - fields/dma/dma2d_v2.yaml + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/exti_u5.yaml + +FDCAN1_RAM: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/u5.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - patches/dma/gpdma_u5_tr1.yaml + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABCHIJ]: + _strip: GPIO_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHIJ]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[1235]: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC2_MPCBB4: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC[12]_TZIC: {} + +GTZC1_TZSC: + _strip: TZSC_ + +GTZC2_TZSC: {} + +HASH: {} + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +ICACHE: + _strip: ICACHE_ + +IWDG: + _include: patches/16bit.yaml + +LPDMA1: + _strip: LPDMA_ + _include: + - collect/dma/lpdma.yaml + +LPGPIO1: + _strip: LPGPIO_ + _include: + - collect/lpgpio/lp.yaml + +LPTIM[14]: {} + +LPUART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + # TODO: fields + +MDF1: + _strip: MDF_ + _include: + - collect/mdf/u5.yaml + +OCTOSPI[12]: + _include: + - patches/octospi/u5.yaml + - fields/octospi/u5.yaml + +OPAMP: {} + +OTFDEC1: {} + +OTG_HS: {} + +PKA: {} + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + CR1: + _add: + FORCE_USBPWR: + bitOffset: 15 + bitWidth: 1 + CR2: + _remove: [GPRAMPDS, DSIRAMPDS, DC2RAMPDS] + VOSR: + _add: + VDD11USBDIS: + bitOffset: 21 + bitWidth: 1 + _include: + - patches/pwr/add_cr5.yaml + - fields/pwr/pwr_u5.yaml + +RAMCFG: {} + +RCC: + _strip: RCC_ + _include: + - fields/rcc/rcc_u5.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAES: {} + +SAI1: + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/resp.yaml + - collect/sdio/fifo.yaml + +SPI1: + _include: + - patches/spi/u5.yaml + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + +SYSCFG: {} + +TAMP: + _include: + - collect/rtc/tamp_bkpr.yaml + +TIM1: + CCMR2_Output: + _modify: + CC3S_1_0: + name: CC3S + CC4S_1_0: + name: CC4S + OC3M_2_0: + name: OC3M + OC4M_3_0: + name: OC4M + OC4M_bit3: + name: OC4M_3 + CCMR3_Output: + _modify: + OC6M: + name: OC6M_3 + OC6M1: + name: OC6M + OC5M1: + name: OC5M + OC5M2: + name: OC5M_3 + _include: + - patches/tim/mms.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm1_bit3.yaml + - patches/tim/icpsc.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - patches/tim/v3/add_dithen.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/C.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32u5a9.yaml b/devices/stm32u5a9.yaml new file mode 100644 index 000000000..ae3404fd1 --- /dev/null +++ b/devices/stm32u5a9.yaml @@ -0,0 +1,367 @@ +_svd: ../svd/stm32u5a9.svd + +_clear_fields: "*" + +_modify: + ICache: + name: ICACHE + +ADC12_Common: + _strip: ADC12_ + _include: + - fields/adc/adc_u5_common.yaml + - fields/adc/adc_u5_dual.yaml + +ADC1: + _strip: ADC_ + _include: + - patches/adc/split.yaml + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - fields/adc/adc_u5_12.yaml + - collect/adc/v3.yaml + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC4: + _strip: ADC_ + _include: + - patches/adc/u5_access.yaml + - fields/adc/adc_u5.yaml + - patches/adc/u5_vsensesel.yaml + - fields/adc/adc_u5_4.yaml + - fields/adc/adc_u5_common.yaml + - collect/adc/c0_g0_wl.yaml + _modify: + PWR: + name: PWRR + CHSELRMOD0: + name: CHSELR0 + CHSELRMOD1: + name: CHSELR1 + alternateRegister: CHSELR0 + +ADF1: + _strip: ADF_ + +AES: + SUSP?R: + _modify: + SUSP?: + name: SUSP + _include: + - fields/aes/v3.yaml + +COMP: {} + +CORDIC: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DAC1: + _strip: DAC_ + _include: + - fields/dac/u5.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DCACHE1: + _strip: DCACHE_ + +DCB: {} + +DCMI: + _include: + - fields/dcmi/v2.yaml + - collect/dcmi/dcmi.yaml + +DLYBOS1: + _strip: DLYB_ + +DMA2D: + _include: + - fields/dma/dma2d_v2.yaml + +DSI: + _strip: DSI_ + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/exti_u5.yaml + +FDCAN1_RAM: + _strip: FDCAN_ + +FLASH: + _strip: FLASH_ + +FMAC: {} + +FMC: + _include: + - patches/fsmc/bcr_clean.yaml + - patches/fsmc/u5.yaml + - fields/fsmc/sram.yaml + - fields/fsmc/nand.yaml + - collect/fsmc/sram.yaml + +FM[C]: + _include: + - collect/fsmc/sram_derive.yaml + +GFXMMU: + _strip: GFXMMU_ + _include: + - collect/gfxmmu/lut.yaml + +GPDMA1: + _strip: GPDMA_ + _include: + - patches/dma/gpdma_u5_tr1.yaml + - collect/dma/gpdma/h7rs_u5.yaml + +GPIO[ABCHIJ]: + _strip: GPIO_ + _include: + - fields/gpio/gpio_l5_u5.yaml + - collect/gpio/v2r.yaml + +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCHIJ]: + _include: collect/gpio/v2r_derive.yaml + +GTZC1_MPCBB[1235]: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC2_MPCBB4: + _strip: MPCBB?_ + _include: + - collect/gtzc/h5_u5.yaml + +GTZC[12]_TZIC: {} + +GTZC1_TZSC: + _strip: TZSC_ + +GTZC2_TZSC: {} + +HASH: {} + +HSPI1: + _strip: HSPI + +I2C1: + _strip: I2C_ + _include: + - fields/i2c/v3.yaml + +ICACHE: + _strip: ICACHE_ + +IWDG: + _include: patches/16bit.yaml + +LPDMA1: + _strip: LPDMA_ + _include: + - collect/dma/lpdma.yaml + +LPGPIO1: + _strip: LPGPIO_ + _include: + - collect/lpgpio/lp.yaml + +LPTIM[14]: {} + +LPUART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + # TODO: fields + +LTDC: + _strip: LTDC_ + _include: + - fields/ltdc/ltdc.yaml + - collect/ltdc/layer.yaml + +MDF1: + _strip: MDF_ + _include: + - collect/mdf/u5.yaml + +OCTOSPI[12]: + _include: + - patches/octospi/u5.yaml + - fields/octospi/u5.yaml + +OPAMP: {} + +OTFDEC1: {} + +OTG_HS: {} + +PKA: {} + +PSSI: + _include: + - fields/pssi/pssi.yaml + +PWR: + _strip: PWR_ + CR1: + _add: + FORCE_USBPWR: + bitOffset: 15 + bitWidth: 1 + VOSR: + _add: + VDD11USBDIS: + bitOffset: 21 + bitWidth: 1 + _include: + - patches/pwr/add_cr5.yaml + - fields/pwr/pwr_u5.yaml + +RAMCFG: {} + +RCC: + _strip: RCC_ + _include: + - fields/rcc/rcc_u5.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - fields/rtc/v3/common.yaml + - collect/rtc/alarm.yaml + +SAES: {} + +SAI1: + _include: + - patches/sai/fsdef-rw.yaml + +SDMMC1: + _strip: SDMMC_ + _include: + - patches/sdio_sdmmc/cardstatus.yaml + - collect/sdio/resp.yaml + - collect/sdio/fifo.yaml + +SPI1: + _include: + - patches/spi/u5.yaml + - patches/spi/rxtxdr.yaml + - fields/spi/spi_v4.yaml + +SYSCFG: {} + +TAMP: {} + +TIM1: + CCMR2_Output: + _modify: + CC3S_1_0: + name: CC3S + CC4S_1_0: + name: CC4S + OC3M_2_0: + name: OC3M + OC4M_3_0: + name: OC4M + OC4M_bit3: + name: OC4M_3 + CCMR3_Output: + _modify: + OC6M: + name: OC6M_3 + OC6M1: + name: OC6M + OC5M1: + name: OC5M + OC5M2: + name: OC5M_3 + _include: + - patches/tim/mms.yaml + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/ccmr3.yaml + - patches/tim/v2/ocm1_bit3.yaml + - patches/tim/icpsc.yaml + - fields/tim/v3/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/sms.yaml + - patches/tim/ts.yaml + - patches/tim/v2/ocm_bit3.yaml + - patches/tim/tim2_common_32bit.yaml + - patches/tim/v2/add_uifcpy.yaml + - fields/tim/v3/tim2.yaml + - collect/tim/ccr.yaml + +TIM6: + _include: + - fields/tim/v3/tim6.yaml + +TIM15: + _include: + - patches/tim/ts.yaml + - patches/tim/v2/ocm1_bit3.yaml + - fields/tim/v3/tim15.yaml + - collect/tim/ccr.yaml + +TIM16: + CCMR1_Output: + _modify: + OC1M_2: + name: OC1M_3 + _include: + - patches/tim/v3/add_dithen.yaml + - fields/tim/v3/tim16.yaml + - fields/tim/v3/occe.yaml + - collect/tim/ccr.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +UCPD1: + _include: + - patches/ucpd/rxordseten_split.yaml + - patches/ucpd/tx_rx_missing_r.yaml + - fields/ucpd/ucpd_v1.yaml + +USART1: + _include: + - patches/usart/rename_CR1_ISR_enabled_disabled.yaml + - patches/usart/add_udr.yaml + - fields/usart/v4/C.yaml + +VREFBUF: + _strip: VREFBUF_ + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml diff --git a/devices/stm32wb55.yaml b/devices/stm32wb55.yaml new file mode 100644 index 000000000..75fe0300a --- /dev/null +++ b/devices/stm32wb55.yaml @@ -0,0 +1,322 @@ +_svd: ../svd/stm32wb55.svd + +_modify: + name: STM32WB55 + ADC: + # Consistent naming across families + name: ADC1 + SYSCFG_VREFBUF: + name: SYSCFG + groupName: SYSCFG + AES?: + groupName: AES + HSEM: + groupName: HSEM + +_derive: + DMA2: DMA1 + +# Rename the L3 field to L to match RM0434 +ADC1: + SQR1: + _modify: + L3: + name: L + description: Regular channel sequence length + _delete: + - CCR # this is part of the ADC_Common block. + _include: + - patches/adc/offset_en.yaml + - patches/adc/split.yaml + - patches/adc/l4+.yaml + - fields/adc/adc_v3.yaml + - fields/adc/adc_v3_l4.yaml + - fields/adc/awd0_18.yaml + - collect/adc/v3.yaml + DR: + _modify: + RDATA_0_6: + bitWidth: 7 + _merge: + RDATA: RDATA* + SQR?: + SQ*: [0, 18] + +ADC[1]: + _include: collect/adc/derive_sq.yaml + +ADC_Common: {} + +AES[12]: + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +CRS: + _include: + - fields/crs/crs.yaml + +DBGMCU: {} + +DMA1: + _include: + - fields/dma/v1.yaml + - collect/dma/v1.yaml + +DMAMUX1: + _include: + - fields/dma/dmamux_v1.yaml + - collect/dma/dmamux.yaml + +EXTI: + _modify: + C1IMR1: + name: IMR1 + C1EMR1: + name: EMR1 + C1IMR2: + name: IMR2 + C1EMR2: + name: EMR2 + + _interrupts: + EXTI10_15: + name: EXTI15_10 + EXTI5_9: + name: EXTI9_5 + + RTSR1: + _modify: + RT_31: + name: RT31 + _split: RT + + FTSR1: + _modify: + FT_31: + name: FT31 + _split: FT + + SWIER1: + _modify: + SWI_31: + name: SWI31 + _split: SWI + + PR1: + _modify: + PIF_31: + name: PIF31 + _split: PIF + + IMR1: + _split: IM + IMR2: + _split: IM + C2IMR1: + _split: IM + C2IMR2: + _split: IM + +Flash: {} + +GPIO[ABCEH]: + _include: + - fields/gpio/v2/common.yaml + +GPIO[A-E]: #H + _include: collect/gpio/v2.yaml +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[BCE]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _modify: + C1IER0: + name: C1IER + C2IER0: + name: C2IER + C[12]IER: + _split: + ISEm: + name: ISE%s + C[12]ICR: + _split: + ISCm: + name: ISC%s + C[12]ISR: + _split: + ISFm: + name: ISF%s + C[12]MISR: + _split: + MISFm: + name: MISF%s + _include: + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IPCC: + _modify: + C1TO2SR: + name: C1TOC2SR + +IWDG: + _include: patches/16bit.yaml + +LCD: + _delete: RAM_COM* + _include: + - patches/lcd/ram_segment_40.yaml + +LPTIM1: + _include: + - fields/lptim/v1.yaml + +PKA: {} + +PWR: {} + +QUADSPI: + _include: + - patches/quadspi/dr_multi_access.yaml + - fields/quadspi/quadspi_v1_single_flash.yaml + +RCC: + _include: + - fields/rcc/rcc_wb.yaml + - fields/rcc/rcc_wx_c2.yaml + +RNG: + _include: + - fields/rng/v1.yaml + +RTC: + _include: + - patches/rtc/alarm.yaml + - patches/rtc/rtc_cr.yaml + - fields/rtc/v2/common.yaml + - collect/rtc/alarm.yaml + - collect/rtc/bkpr.yaml + +SAI1: + _delete: + - GCR + _include: + - patches/sai/sai_v1.yaml + - fields/sai/sai.yaml + - collect/sai/ch.yaml + - collect/sai/pdm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - fields/spi/spi_common.yaml + - fields/spi/spi_FRF_FRE.yaml + - fields/spi/spi_v2_spi.yaml + +SYSCFG: + _strip: SYSCFG_ + _include: fields/syscfg/syscfg_wb55.yaml + _modify: + IMR1: + addressOffset: 0x100 + IMR2: + addressOffset: 0x104 + C2IMR1: + addressOffset: 0x108 + C2IMR2: + addressOffset: 0x10c + SIPCR: + addressOffset: 0x110 + +TIM1: + CCMR1_Input: + _modify: + C1F: + name: IC1F + _include: + - patches/tim/v2/oc5m_bit3.yaml + - patches/tim/dmab_32.yaml + - fields/tim/v2/tim1.yaml + - collect/tim/ccr.yaml + +TIM2: + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/basic.yaml + - fields/tim/tim_32bit.yaml + - fields/tim/tim_gp1.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr.yaml + - fields/tim/v2/ccm_extended.yaml + - collect/tim/ccr.yaml + CNT: + _add: + UIFREMAP_CNT: + description: Counter value when CR1.UIFREMAP=1 + bitOffset: 0 + bitWidth: 31 + _modify: + UIFCPY: + description: Copy of ISR.UIF when CR1.UIFREMAP=1 + CNT_H: + bitWidth: 16 + bitOffset: 16 + CNT_L: + bitOffset: 0 + +TIM1[67]: + _include: + - fields/tim/v2/tim16.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TSC: + _include: + - fields/tsc/tsc.yaml + - collect/tsc/iogcr.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR2_DATAINV_field.yaml + - fields/usart/v4/B.yaml + +USB: + _include: + - fields/usb/v2_with_LPM.yaml + - collect/usb/epxr.yaml + #_array: + # COUNT?_RX: {} + # COUNT?_TX: {} + # ADDR?_RX: {} + # ADDR?_TX: {} + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg_v2.yaml + +_include: + - patches/adc/wb_adc_common.yaml diff --git a/devices/stm32wl5x_cm0p.yaml b/devices/stm32wl5x_cm0p.yaml new file mode 100644 index 000000000..ad8246eb1 --- /dev/null +++ b/devices/stm32wl5x_cm0p.yaml @@ -0,0 +1,263 @@ +_svd: ../svd/stm32wl5x_cm0p.svd + +_clear_fields: "*" + +_delete: + - SYSCFG_continue + +_derive: + LPTIM3: LPTIM2 + +_modify: + name: STM32WL5X_CM0P + TIM*: + groupName: TIM + +ADC: + _strip: ADC_ + _include: + - patches/adc/wl.yaml + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + +AES: + CR: + _modify: + CHMOD10: + name: CHMOD + _include: + - patches/aes/fields.yaml + - fields/aes/v2.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + CR: + _merge: TSEL1* + _include: + - fields/dac/wl.yaml + - collect/dac/v3.yaml + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/dma_wl.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux_wl.yaml + - collect/dma/dmamux.yaml + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/common.yaml + +FLASH: + _include: + - fields/flash/flash_wl.yaml + - fields/flash/flash_wl_c2.yaml + +GPIO[ABCH]: + _include: fields/gpio/v2/common.yaml + +GPIO[AB]: #CH + _include: collect/gpio/v2.yaml +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _modify: + C2ICR: + access: read-write + _include: + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IPCC: + _strip: IPCC_ + _include: + - fields/ipcc/ipcc_wl.yaml + +IWDG: + _delete: + - WINR + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + - fields/iwdg/iwdg_sr.yaml + +LPTIM1: + _strip: LPTIM?_ + _include: + - fields/lptim/v2.yaml + - fields/lptim/lptim1_wl.yaml +LPTIM2: + _strip: LPTIM?_ + _include: + - fields/lptim/v2.yaml + - fields/lptim/lptim2_wl.yaml + OR: + _merge: OR* + +# Rename this so it has the same name as all other STM32 USARTs +LPUART,USART?: + ICR: + _modify: + NECF: + name: NCF + +# CR1 and ISR have 2 versions depending on whether FIFO is enabled or not +# The only difference is the addition of 2 bits at the top of the register +# and some names (e.g. TXEIE - TXFNFIE), but all functionality remains the same +# so we remove the "disabled" version and leave the "enabled" version as +# reference +LPUART: + _modify: + CR1_enabled: + name: CR1 + ISR_enabled: + name: ISR + _delete: + - CR1_disabled + - ISR_disabled + CR1: + _modify: + TXFNFIE: + name: TXEIE + _include: + - fields/usart/v4/lp_wl.yaml + +PKA: + _include: + - fields/pka/pka.yaml + +PWR: + _include: + - fields/pwr/pwr_wl.yaml + - fields/pwr/pwr_wl_c2.yaml + +RCC: + _include: + - fields/rcc/rcc_wl.yaml + - fields/rcc/rcc_wx_c2.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/rtc_register_descriptions.yaml + - patches/rtc/wl.yaml + - fields/rtc/v3/wl.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - fields/syscfg/syscfg_wl.yaml + +TAMP: + _include: + - patches/rtc/tamp_wl.yaml + - fields/tamp/tamp_wl.yaml + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _modify: + CCMR3OutputComparemode: + name: CCMR3_Output + _include: + - patches/tim/ts.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim1_wl.yaml + - fields/tim/tim_gp1.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr.yaml + - fields/tim/tim12_common_wl.yaml + - fields/tim/v2/ccm_extended.yaml + - collect/tim/ccr.yaml + +TIM2: + _strip: TIM2_ + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim2_wl.yaml + - fields/tim/tim_gp1.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr.yaml + - fields/tim/tim12_common_wl.yaml + - fields/tim/v2/ccm_extended.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _strip: TIM1?_ + DIER: + _delete: + - COMDE + BDTR: + _delete: + - BKF + _include: + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr1.yaml + - fields/tim/tim16_wl.yaml + - fields/tim/v2/ccm_common.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TZIC: {} + +TZSC: + _strip: TZSC_ + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/rename_CR1_M0_field.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR3_SCARCNT_field.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _include: + - fields/vrefbuf/vrefbuf_wl.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - fields/comp/comp_wl.yaml diff --git a/devices/stm32wl5x_cm4.yaml b/devices/stm32wl5x_cm4.yaml new file mode 100644 index 000000000..68e84bb67 --- /dev/null +++ b/devices/stm32wl5x_cm4.yaml @@ -0,0 +1,284 @@ +_svd: ../svd/stm32wl5x_cm4.svd + +_clear_fields: "*" + +_delete: + - SYSCFG_continue + +_derive: + LPTIM3: LPTIM2 + +_modify: + name: STM32WL5X_CM4 + TIM*: + groupName: TIM + +ADC: + _include: + - patches/adc/wl.yaml + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + +AES: + CR: + _modify: + CHMOD10: + name: CHMOD + DINR: + _modify: + AES_DINR: + name: DIN + DOUTR: + _modify: + AES_DOUTR: + name: DOUT + KEYR?: + _modify: + AES_KEYR?: + name: KEY + IVR?: + _modify: + AES_IVR?: + name: IVI + SUSP?R: + _modify: + AES_SUSP?R: + name: SUSP + _include: + - fields/aes/v2.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + CR: + _merge: TSEL1* + _include: + - fields/dac/wl.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/dma_wl.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux_wl.yaml + - collect/dma/dmamux.yaml + +EXTI: + _strip: EXTI_ + _include: + - fields/exti/common.yaml + +FLASH: + _include: + - fields/flash/flash_wl.yaml + - fields/flash/flash_wl_c2.yaml + +GPIO[ABCH]: + _include: + - fields/gpio/v2/common.yaml + +GPIO[AB]: #CH + _include: collect/gpio/v2.yaml +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _modify: + C2ICR: + access: read-write + _include: + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IPCC: + _include: + - fields/ipcc/ipcc_wl.yaml + +IWDG: + _delete: + - WINR + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + - fields/iwdg/iwdg_sr.yaml + +LPTIM1: + _strip: LPTIM?_ + _include: + - fields/lptim/v2.yaml + - fields/lptim/lptim1_wl.yaml +LPTIM2: + _strip: LPTIM?_ + _include: + - fields/lptim/v2.yaml + - fields/lptim/lptim2_wl.yaml + OR: + _merge: OR* + +# Rename this so it has the same name as all other STM32 USARTs +LPUART,USART?: + ICR: + _modify: + NECF: + name: NCF + +# CR1 and ISR have 2 versions depending on whether FIFO is enabled or not +# The only difference is the addition of 2 bits at the top of the register +# and some names (e.g. TXEIE - TXFNFIE), but all functionality remains the same +# so we remove the "disabled" version and leave the "enabled" version as +# reference +LPUART: + _modify: + CR1_enabled: + name: CR1 + ISR_enabled: + name: ISR + _delete: + - CR1_disabled + - ISR_disabled + CR1: + _modify: + TXFNFIE: + name: TXEIE + _include: + - fields/usart/v4/lp_wl.yaml + +PKA: + _include: + - fields/pka/pka.yaml + +PWR: + _include: + - fields/pwr/pwr_wl.yaml + - fields/pwr/pwr_wl_c2.yaml + +RCC: + _include: + - fields/rcc/rcc_wl.yaml + - fields/rcc/rcc_wx_c2.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/rtc_register_descriptions.yaml + - patches/rtc/wl.yaml + - fields/rtc/v3/wl.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - fields/syscfg/syscfg_wl.yaml + +TAMP: + _include: + - patches/rtc/tamp_wl.yaml + - fields/tamp/tamp_wl.yaml + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _modify: + CCMR3OutputComparemode: + name: CCMR3_Output + _include: + - patches/tim/ts.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim1_wl.yaml + - fields/tim/tim_gp1.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr.yaml + - fields/tim/tim12_common_wl.yaml + - fields/tim/v2/ccm_extended.yaml + - collect/tim/ccr.yaml + +TIM2: + _strip: TIM2_ + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim2_wl.yaml + - fields/tim/tim_gp1.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr.yaml + - fields/tim/tim12_common_wl.yaml + - fields/tim/v2/ccm_extended.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _strip: TIM1?_ + DIER: + _delete: + - COMDE + BDTR: + _delete: + - BKF + _include: + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr1.yaml + - fields/tim/tim16_wl.yaml + - fields/tim/v2/ccm_common.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +TZIC: {} + +TZSC: + _strip: TZSC_ + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/rename_CR1_M0_field.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR3_SCARCNT_field.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _include: + - fields/vrefbuf/vrefbuf_wl.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - fields/comp/comp_wl.yaml + - fields/dbg/dbg_wl.yaml diff --git a/devices/stm32wle5.yaml b/devices/stm32wle5.yaml new file mode 100644 index 000000000..1f0076ffe --- /dev/null +++ b/devices/stm32wle5.yaml @@ -0,0 +1,299 @@ +_svd: ../svd/stm32wle5.svd + +_clear_fields: "*" + +_delete: + - SYSCFG_continue + +_derive: + LPTIM3: LPTIM2 + +_modify: + name: STM32WLE5 + TIM*: + groupName: TIM + +ADC: + _include: + - patches/adc/wl.yaml + - fields/adc/c0_g0_wl.yaml + - collect/adc/c0_g0_wl.yaml + +AES: + CR: + _modify: + CHMOD10: + name: CHMOD + DINR: + _modify: + AES_DINR: + name: DIN + DOUTR: + _modify: + AES_DOUTR: + name: DOUT + KEYR?: + _modify: + AES_KEYR?: + name: KEY + IVR?: + _modify: + AES_IVR?: + name: IVI + SUSP?R: + _modify: + AES_SUSP?R: + name: SUSP + _include: + - fields/aes/v2.yaml + +COMP: {} + +CRC: + _include: + - patches/crc/crc_rename_init.yaml + - patches/crc/add_dr8.yaml + - fields/crc/v3_idr32.yaml + +DAC: + CR: + _merge: TSEL1* + _include: + - fields/dac/wl.yaml + - collect/dac/v3.yaml + +DBGMCU: {} + +DMA1: + IFCR: + _prefix: C + _include: + - fields/dma/dma_wl.yaml + - collect/dma/v1.yaml + +DMAMUX: + _include: + - fields/dma/dmamux_v1.yaml + - fields/dma/dmamux_wl.yaml + - collect/dma/dmamux.yaml + +EXTI: + _include: + - patches/exti/wl.yaml + - fields/exti/common.yaml + _modify: + IMR1: + name: C1IMR1 + IMR2: + name: C1IMR2 + C1IMR2: + _modify: + IM42: + bitWidth: 1 + _add: + IM43: + description: CPUm Wakeup with interrupt Mask on Event input + bitOffset: 11 + bitWidth: 1 + access: read-write + IM44: + description: CPUm Wakeup with interrupt Mask on Event input + bitOffset: 12 + bitWidth: 1 + access: read-write + IM45: + description: CPUm Wakeup with interrupt Mask on Event input + bitOffset: 13 + bitWidth: 1 + access: read-write + IM46: + description: CPUm Wakeup with interrupt Mask on Event input + bitOffset: 14 + bitWidth: 1 + access: read-write + +FLASH: + _include: + - fields/flash/flash_wl.yaml + +GPIO[ABCH]: + _include: + - fields/gpio/v2/common.yaml + +GPIO[AB]: #CH + _include: collect/gpio/v2.yaml +GPIO[A]: + _include: collect/gpio/gpioa_afr.yaml +GPIO[B]: + _include: collect/gpio/v2_derive.yaml + +HSEM: + _strip: HSEM_ + _include: + - fields/hsem/common.yaml + - collect/hsem/fields.yaml + - collect/hsem/r.yaml + +I2C1: + _include: + - fields/i2c/v2.yaml + +IWDG: + _delete: + - WINR + _include: + - patches/16bit.yaml + - fields/iwdg/iwdg.yaml + - fields/iwdg/iwdg_sr.yaml + +LPTIM1: + _strip: LPTIM?_ + _include: + - fields/lptim/v2.yaml + - fields/lptim/lptim1_wl.yaml +LPTIM2: + _strip: LPTIM?_ + _include: + - fields/lptim/v2.yaml + - fields/lptim/lptim2_wl.yaml + OR: + _merge: OR* + +# Rename this so it has the same name as all other STM32 USARTs +LPUART,USART?: + ICR: + _modify: + NECF: + name: NCF + +# CR1 and ISR have 2 versions depending on whether FIFO is enabled or not +# The only difference is the addition of 2 bits at the top of the register +# and some names (e.g. TXEIE - TXFNFIE), but all functionality remains the same +# so we remove the "disabled" version and leave the "enabled" version as +# reference +LPUART: + _modify: + CR1_enabled: + name: CR1 + ISR_enabled: + name: ISR + _delete: + - CR1_disabled + - ISR_disabled + CR1: + _modify: + TXFNFIE: + name: TXEIE + _include: + - fields/usart/v4/lp_wl.yaml + +PKA: + _include: + - fields/pka/pka.yaml + +PWR: + _include: + - fields/pwr/pwr_wl.yaml + +RCC: + _include: + - fields/rcc/rcc_wl.yaml + +RNG: + _include: + - fields/rng/v2.yaml + +RTC: + _include: + - patches/rtc/rtc_register_descriptions.yaml + - patches/rtc/wl.yaml + - fields/rtc/v3/wl.yaml + - collect/rtc/alarm.yaml + +SPI1: + _include: + - patches/16bit.yaml + - patches/spi/dr8.yaml + - patches/spi/rename_dff_tifrfe.yaml + - fields/spi/spi_v2.yaml + +SYSCFG: + _include: + - fields/syscfg/syscfg_wl.yaml + +TAMP: + _include: + - patches/rtc/tamp_wl.yaml + - fields/tamp/tamp_wl.yaml + - collect/rtc/tamp_bkpr.yaml + +TIM1: + _modify: + CCMR3OutputComparemode: + name: CCMR3_Output + _include: + - patches/tim/ts.yaml + - patches/tim/dmab_32.yaml + - fields/tim/tim1_wl.yaml + - fields/tim/tim_gp1.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr.yaml + - fields/tim/tim12_common_wl.yaml + - fields/tim/v2/ccm_extended.yaml + - collect/tim/ccr.yaml + +TIM2: + _strip: TIM2_ + _include: + - patches/tim/tim2_common_32bit.yaml + - fields/tim/tim2_wl.yaml + - fields/tim/tim_gp1.yaml + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr.yaml + - fields/tim/tim12_common_wl.yaml + - fields/tim/v2/ccm_extended.yaml + - collect/tim/ccr.yaml + +TIM1[67]: + _strip: TIM1?_ + DIER: + _delete: + - COMDE + BDTR: + _delete: + - BKF + _include: + - fields/tim/basic.yaml + - fields/tim/tim_ckd.yaml + - fields/tim/ccr1.yaml + - fields/tim/tim16_wl.yaml + - fields/tim/v2/ccm_common.yaml + - collect/tim/ccr.yaml + +TIM17: + _include: collect/tim/tim17_derive.yaml + +USART1: + _include: + - patches/usart/merge_CR1_DEDTx_fields.yaml + - patches/usart/merge_CR1_DEATx_fields.yaml + - patches/usart/rename_CR1_M0_field.yaml + - patches/usart/merge_CR2_ABRMODx_fields.yaml + - patches/usart/merge_CR2_ADDx_fields.yaml + - patches/usart/rename_CR3_SCARCNT_field.yaml + - fields/usart/v4/B.yaml + +VREFBUF: + _include: + - fields/vrefbuf/vrefbuf_wl.yaml + +WWDG: + _include: + - patches/16bit.yaml + - fields/wwdg/wwdg.yaml + +_include: + - fields/comp/comp_wl.yaml + - fields/dbg/dbg_wl.yaml diff --git a/peripherals/adc/adc_aditf4_v1_1.yaml b/peripherals/adc/adc_aditf4_v1_1.yaml deleted file mode 100644 index 0209f340f..000000000 --- a/peripherals/adc/adc_aditf4_v1_1.yaml +++ /dev/null @@ -1,169 +0,0 @@ -# ADC common as used on F0x0, F0x1, F0x2 and F0x8 - -ADC: - ISR: - AWD: - _read: - NoEvent: [0, "No analog watchdog event occurred"] - Event: [1, "Analog watchdog event occurred"] - _write: - Clear: [1, "Clear the analog watchdog event flag"] - OVR: - _read: - NoOverrun: [0, "No overrun occurred"] - Overrun: [1, "Overrun occurred"] - _write: - Clear: [1, "Clear the overrun flag"] - EOSEQ: - _read: - NotComplete: [0, "Conversion sequence is not complete"] - Complete: [1, "Conversion sequence complete"] - _write: - Clear: [1, "Clear the conversion sequence flag"] - EOC: - _read: - NotComplete: [0, "Channel conversion is not complete"] - Complete: [1, "Channel conversion complete"] - _write: - Clear: [1, "Clear the channel conversion flag"] - EOSMP: - _read: - NotAtEnd: [0, "Not at the end of the samplings phase"] - AtEnd: [1, "End of sampling phase reached"] - _write: - Clear: [1, "Clear the sampling phase flag"] - ADRDY: - _read: - NotReady: [0, "ADC not yet ready to start conversion"] - Ready: [1, "ADC ready to start conversion"] - _write: - Clear: [1, "Clear the ADC ready flag"] - IER: - AWDIE: - Disabled: [0, "Analog watchdog interrupt disabled"] - Enabled: [1, "Analog watchdog interrupt enabled"] - OVRIE: - Disabled: [0, "Overrun interrupt disabled"] - Enabled: [1, "Overrun interrupt enabled"] - EOSEQIE: - Disabled: [0, "End of conversion sequence interrupt disabled"] - Enabled: [1, "End of conversion sequence interrupt enabled"] - EOCIE: - Disabled: [0, "End of conversion interrupt disabled"] - Enabled: [1, "End of conversion interrupt enabled"] - EOSMPIE: - Disabled: [0, "End of sampling interrupt disabled"] - Enabled: [1, "End of sampling interrupt enabled"] - ADRDYIE: - Disabled: [0, "ADC ready interrupt disabled"] - Enabled: [1, "ADC ready interrupt enabled"] - CR: - ADCAL: - _read: - NotCalibrating: [0, "ADC calibration either not yet performed or completed"] - Calibrating: [1, "ADC calibration in progress"] - _write: - StartCalibration: [1, "Start the ADC calibration sequence"] - ADSTP: - _read: - NotStopping: [0, "No stop command active"] - Stopping: [1, "ADC stopping conversion"] - _write: - StopConversion: [1, "Stop the active conversion"] - ADSTART: - _read: - NotActive: [0, "No conversion ongoing"] - Active: [1, "ADC operating and may be converting"] - _write: - StartConversion: [1, "Start the ADC conversion (may be delayed for hardware triggers)"] - ADDIS: - _read: - NotDisabling: [0, "No disable command active"] - Disabling: [1, "ADC disabling"] - _write: - Disable: [1, "Disable the ADC"] - ADEN: - _read: - Disabled: [0, "ADC disabled"] - Enabled: [1, "ADC enabled"] - _write: - Enabled: [1, "Enable the ADC"] - CFGR1: - AWDCH: [0, 18] - AWDEN: - Disabled: [0, "Analog watchdog disabled on regular channels"] - Enabled: [1, "Analog watchdog enabled on regular channels"] - AWDSGL: - AllChannels: [0, "Analog watchdog enabled on all channels"] - SingleChannel: [1, "Analog watchdog enabled on a single channel"] - DISCEN: - Disabled: [0, "Discontinuous mode on regular channels disabled"] - Enabled: [1, "Discontinuous mode on regular channels enabled"] - AUTOFF: - Disabled: [0, "Auto-off mode disabled"] - Enabled: [1, "Auto-off mode enabled"] - WAIT: - Disabled: [0, "Wait conversion mode off"] - Enabled: [1, "Wait conversion mode on"] - CONT: - Single: [0, "Single conversion mode"] - Continuous: [1, "Continuous conversion mode"] - OVRMOD: - Preserved: [0, "ADC_DR register is preserved with the old data when an overrun is detected"] - Overwritten: [1, "ADC_DR register is overwritten with the last conversion result when an overrun is detected"] - EXTEN: - Disabled: [0, "Trigger detection disabled"] - RisingEdge: [1, "Trigger detection on the rising edge"] - FallingEdge: [2, "Trigger detection on the falling edge"] - BothEdges: [3, "Trigger detection on both the rising and falling edges"] - EXTSEL: - TIM1_TRGO: [0, "Timer 1 TRGO Event"] - TIM1_CC4: [1, "Timer 1 CC4 event"] - TIM3_TRGO: [3, "Timer 3 TRGO event"] - TIM15_TRGO: [4, "Timer 15 TRGO event"] - ALIGN: - Right: [0, "Right alignment"] - Left: [1, "Left alignment"] - RES: - TwelveBit: [0, "12-bit (14 ADCCLK cycles)"] - TenBit: [1, "10-bit (13 ADCCLK cycles)"] - EightBit: [2, "8-bit (11 ADCCLK cycles)"] - SixBit: [3, "6-bit (9 ADCCLK cycles)"] - SCANDIR: - Upward: [0, "Upward scan (from CHSEL0 to CHSEL18)"] - Backward: [1, "Backward scan (from CHSEL18 to CHSEL0)"] - DMACFG: - OneShot: [0, "DMA one shot mode"] - Circular: [1, "DMA circular mode"] - DMAEN: - Disabled: [0, "DMA mode disabled"] - Enabled: [1, "DMA mode enabled"] - CFGR2: - CKMODE: - ADCCLK: [0, "Asynchronous clock mode"] - PCLK_Div2: [1, "Synchronous clock mode (PCLK/2)"] - PCLK_Div4: [2, "Sychronous clock mode (PCLK/4)"] - SMPR: - SMP: - Cycles1_5: [0, "1.5 cycles"] - Cycles7_5: [1, "7.5 cycles"] - Cycles13_5: [2, "13.5 cycles"] - Cycles28_5: [3, "28.5 cycles"] - Cycles41_5: [4, "41.5 cycles"] - Cycles55_5: [5, "55.5 cycles"] - Cycles71_5: [6, "71.5 cycles"] - Cycles239_5: [7, "239.5 cycles"] - TR: - HT: [0, 4095] - LT: [0, 4095] - CHSELR: - "CHSEL*": - NotSelected: [0, "Input Channel is not selected for conversion"] - Selected: [1, "Input Channel is selected for conversion"] - CCR: - TSEN: - Disabled: [0, "Temperature sensor disabled"] - Enabled: [1, "Temperature sensor enabled"] - VREFEN: - Disabled: [0, "V_REFINT channel disabled"] - Enabled: [1, "V_REFINT channel enabled"] diff --git a/peripherals/adc/adc_aditf4_v1_1_RM0091.yaml b/peripherals/adc/adc_aditf4_v1_1_RM0091.yaml deleted file mode 100644 index 833cdade0..000000000 --- a/peripherals/adc/adc_aditf4_v1_1_RM0091.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# ADC as used on F0x1, F0x2 and F0x8 - -_include: - - "adc_aditf4_v1_1.yaml" - -ADC: - CFGR1: - EXTSEL: - TIM2_TRGO: [2, "Timer 2 TRGO event"] - CCR: - VBATEN: - Disabled: [0, "V_BAT channel disabled"] - Enabled: [1, "V_BAT channel enabled"] diff --git a/peripherals/adc/adc_array.yaml b/peripherals/adc/adc_array.yaml deleted file mode 100644 index 45747b6e5..000000000 --- a/peripherals/adc/adc_array.yaml +++ /dev/null @@ -1,8 +0,0 @@ -"ADC?": - _array: - "JOFR?": - JOFFSET: [0, 4095] - _modify: - JOFFSET1: - name: JOFFSET - "JDR?": {} diff --git a/peripherals/adc/adc_f1.yaml b/peripherals/adc/adc_f1.yaml deleted file mode 100644 index 915db8946..000000000 --- a/peripherals/adc/adc_f1.yaml +++ /dev/null @@ -1,37 +0,0 @@ -_include: - - ./adc_f1_common.yaml - -ADC1: - CR1: - DUALMOD: - Independent: [0, "Independent mode"] - RegularInjected: [1, "Combined regular simultaneous + injected simultaneous mode"] - RegularAlternateTrigger: [2, "Combined regular simultaneous + alternate trigger mode"] - InjectedFastInterleaved: [3, "Combined injected simultaneous + fast interleaved mode"] - InjectedSlowInterleaved: [4, "Combined injected simultaneous + slow interleaved mode"] - Injected: [5, "Injected simultaneous mode only"] - Regular: [6, "Regular simultaneous mode only"] - FastInterleaved: [7, "Fast interleaved mode only"] - SlowInterleaved: [8, "Slow interleaved mode only"] - AlternateTrigger: [9, "Alternate trigger mode only"] - -ADC3: - CR2: - EXTSEL: - Tim3Cc1: [0, "Timer 3 CC1 event"] - Tim2Cc3: [1, "Timer 2 CC3 event"] - Tim1Cc3: [2, "Timer 1 CC3 event"] - Tim8Cc1: [3, "Timer 8 CC1 event"] - Tim8Trgo: [4, "Timer 8 TRGO event"] - Tim5Cc1: [5, "Timer 5 CC1 event"] - Tim5Cc3: [6, "Timer 5 CC3 event"] - Swstart: [7, "SWSTART"] - JEXTSEL: - Tim1Trgo: [0, "Timer 1 TRGO event"] - Tim1Cc4: [1, "Timer 1 CC4 event"] - Tim4Cc3: [2, "Timer 4 CC3 event"] - Tim8Cc2: [3, "Timer 8 CC2 event"] - Tim8Cc4: [4, "Timer 8 CC4 event"] - Tim5Trgo: [5, "Timer 5 TRGO event"] - Tim5Cc4: [6, "Timer 5 CC4 event"] - Jswstart: [7, "JSWSTART"] diff --git a/peripherals/adc/adc_f1_common.yaml b/peripherals/adc/adc_f1_common.yaml deleted file mode 100644 index fab3a3346..000000000 --- a/peripherals/adc/adc_f1_common.yaml +++ /dev/null @@ -1,23 +0,0 @@ -_include: - - ./adc_f1_f37x.yaml - -"ADC[12]": - CR2: - EXTSEL: - Tim1Cc1: [0, "Timer 1 CC1 event"] - Tim1Cc2: [1, "Timer 1 CC2 event"] - Tim1Cc3: [2, "Timer 1 CC3 event"] - Tim2Cc2: [3, "Timer 2 CC2 event"] - Tim3Trgo: [4, "Timer 3 TRGO event"] - Tim4Cc4: [5, "Timer 4 CC4 event"] - Exti11: [6, "EXTI line 11/TIM8_TRGO event (TIM8_TRGO is available only in high-density and XL-density devices)"] - Swstart: [7, "SWSTART"] - JEXTSEL: - Tim1Trgo: [0, "Timer 1 TRGO event"] - Tim1Cc4: [1, "Timer 1 CC4 event"] - Tim2Trgo: [2, "Timer 2 TRGO event"] - Tim2Cc1: [3, "Timer 2 CC1 event"] - Tim3Cc4: [4, "Timer 3 CC4 event"] - Tim4Trgo: [5, "Timer 4 TRGO event"] - Exti15: [6, "EXTI line15/TIM8_CC4 event (TIM8_CC4 is available only in high-density and XL-density devices)"] - Jswstart: [7, "JSWSTART"] diff --git a/peripherals/adc/adc_f1_f37x.yaml b/peripherals/adc/adc_f1_f37x.yaml deleted file mode 100644 index 4f6cfb82f..000000000 --- a/peripherals/adc/adc_f1_f37x.yaml +++ /dev/null @@ -1,137 +0,0 @@ -"ADC?": - SR: - STRT: - _read: - NotStarted: [0, "No regular channel conversion started"] - Started: [1, "Regular channel conversion has started"] - _write: - Clear: [0, "Clear the Regular channel Start flag"] - JSTRT: - _read: - NotStarted: [0, "No injected group conversion started"] - Started: [1, "Injected group conversion has started"] - _write: - Clear: [0, "Clear Injected channel Start flag"] - JEOC: - _read: - NotComplete: [0, "Conversion is not complete"] - Complete: [1, "Conversion complete"] - _write: - Clear: [0, "Clear Injected channel end of conversion flag"] - EOC: - _read: - NotComplete: [0, "Conversion is not complete"] - Complete: [1, "Conversion complete"] - _write: - Clear: [0, "Clear End of conversion flag"] - AWD: - _read: - NoEvent: [0, "No analog watchdog event occurred"] - Event: [1, "Analog watchdog event occurred"] - _write: - Clear: [0, "Clear the analog watchdog event flag"] - - CR1: - AWDEN: - Disabled: [0, "Analog watchdog disabled on regular channels"] - Enabled: [1, "Analog watchdog enabled on regular channels"] - JAWDEN: - Disabled: [0, "Analog watchdog disabled on injected channels"] - Enabled: [1, "Analog watchdog enabled on injected channels"] - DISCNUM: [0, 7] - JDISCEN: - Disabled: [0, "Discontinuous mode on injected channels disabled"] - Enabled: [1, "Discontinuous mode on injected channels enabled"] - DISCEN: - Disabled: [0, "Discontinuous mode on regular channels disabled"] - Enabled: [1, "Discontinuous mode on regular channels enabled"] - JAUTO: - Disabled: [0, "Automatic injected group conversion disabled"] - Enabled: [1, "Automatic injected group conversion enabled"] - AWDSGL: - All: [0, "Analog watchdog enabled on all channels"] - Single: [1, "Analog watchdog enabled on a single channel"] - SCAN: - Disabled: [0, "Scan mode disabled"] - Enabled: [1, "Scan mode enabled"] - JEOCIE: - Disabled: [0, "JEOC interrupt disabled"] - Enabled: [1, "JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set"] - AWDIE: - Disabled: [0, "Analog watchdog interrupt disabled"] - Enabled: [1, "Analog watchdog interrupt enabled"] - EOCIE: - Disabled: [0, "EOC interrupt disabled"] - Enabled: [1, "EOC interrupt enabled. An interrupt is generated when the EOC bit is set"] - AWDCH: [0, 17] - - CR2: - TSVREFE: - Disabled: [0, "Temperature sensor and V_REFINT channel disabled"] - Enabled: [1, "Temperature sensor and V_REFINT channel enabled"] - SWSTART: - _read: - Started: [0, "Reset state"] - NotStarted: [1, "Starting conversion of regular channels"] - _write: - Start: [1, "Start conversion of regular channels"] - JSWSTART: - _read: - Started: [0, "Reset state"] - NotStarted: [1, "Starting conversion of injected channels"] - _write: - Start: [1, "Start conversion of injected channels"] - EXTTRIG: - Disabled: [0, "Conversion on external event disabled"] - Enabled: [1, "Conversion on external event enabled"] - JEXTTRIG: - Disabled: [0, "Conversion on external event disabled"] - Enabled: [1, "Conversion on external event enabled"] - ALIGN: - Right: [0, "Right Alignment"] - Left: [1, "Left Alignment"] - RSTCAL: - _read: - Initialized: [0, "Calibration register initialized"] - NotInitialized: [1, "Initializing calibration register"] - _write: - Initialize: [1, "Initialize calibration register"] - CAL: - _read: - Complete: [0, "Calibration completed"] - NotComplete: [1, "Calibrating"] - _write: - Start: [1, "Enable calibration"] - CONT: - Single: [0, "Single conversion mode"] - Continuous: [1, "Continuous conversion mode"] - ADON: - Disabled: [0, "Disable ADC conversion/calibration and go to power down mode"] - Enabled: [1, "Enable ADC and to start conversion"] - - "SMPR?": - "SMP*": - Cycles1_5: [0, "1.5 ADC clock cycles"] - Cycles7_5: [1, "7.5 ADC clock cycles"] - Cycles13_5: [2, "13.5 ADC clock cycles"] - Cycles28_5: [3, "28.5 ADC clock cycles"] - Cycles41_5: [4, "41.5 ADC clock cycles"] - Cycles55_5: [5, "55.5 ADC clock cycles"] - Cycles71_5: [6, "71.5 ADC clock cycles"] - Cycles239_5: [7, "239.5 ADC clock cycles"] - HTR: - HT: [0, 4095] - LTR: - LT: [0, 4095] - "*SQR*": - "*SQ*": [0, 17] - SQR1: - L: [0, 15] - JSQR: - JL: [0, 3] - -"ADC[13]": - CR2: - DMA: - Disabled: [0, "DMA mode disabled"] - Enabled: [1, "DMA mode enabled"] diff --git a/peripherals/adc/adc_f37x.yaml b/peripherals/adc/adc_f37x.yaml deleted file mode 100644 index 51a45c30e..000000000 --- a/peripherals/adc/adc_f37x.yaml +++ /dev/null @@ -1,23 +0,0 @@ -_include: - - ./adc_f1_f37x.yaml - -ADC1: - CR2: - EXTSEL: - Tim19Trgo: [0, "Timer 19 TRGO event"] - Tim19Cc3: [1, "Timer 19 CC3 event"] - Tim19Cc4: [2, "Timer 19 CC4 event"] - Tim2Cc2: [3, "Timer 2 CC2 event"] - Tim3Trgo: [4, "Timer 3 TRGO event"] - Tim4Cc4: [5, "Timer 4 CC4 event"] - Exti11: [6, "EXTI line 11"] - Swstart: [7, "SWSTART"] - JEXTSEL: - Tim19Cc1: [0, "Timer 19 CC1 event"] - Tim19Cc2: [1, "Timer 19 CC2 event"] - Tim2Trgo: [2, "Timer 2 TRGO event"] - Tim2Cc1: [3, "Timer 2 CC1 event"] - Tim3Cc4: [4, "Timer 3 CC4 event"] - Tim4Trgo: [5, "Timer 4 TRGO event"] - Exti15: [6, "EXTI line15"] - Jswstart: [7, "JSWSTART"] diff --git a/peripherals/adc/adc_h7_revision_v.yaml b/peripherals/adc/adc_h7_revision_v.yaml deleted file mode 100644 index 0b796e5b2..000000000 --- a/peripherals/adc/adc_h7_revision_v.yaml +++ /dev/null @@ -1,16 +0,0 @@ -# ADC features specific to H7 Rev V - -"ADC?": - CFGR: - RES: - SixteenBit: [0, "16-bit resolution"] - FourteenBit: [1, "14-bit resolution"] - TwelveBit: [2, "12-bit resolution"] - TenBit: [3, "10-bit resolution"] - EightBit: [7, "8-bit resolution"] - CR: - BOOST: - LT6_25: [0, "Boost mode used when ADC clock ≤ 6.25 MHz"] - LT12_5: [1, "Boost mode used when 6.25 MHz < ADC clock ≤ 12.5 MHz"] - LT25: [2, "Boost mode used when 12.5 MHz < ADC clock ≤ 25.0 MHz"] - LT50: [3, "Boost mode used when 25.0 MHz < ADC clock ≤ 50.0 MHz"] diff --git a/peripherals/adc/adc_h7_revision_y.yaml b/peripherals/adc/adc_h7_revision_y.yaml deleted file mode 100644 index 1d3ac6df8..000000000 --- a/peripherals/adc/adc_h7_revision_y.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# ADC features specific to H742/743/753/750 Rev Y - -"ADC?": - CFGR: - RES: - SixteenBit: [0, "16-bit resolution"] - FourteenBit: [1, "14-bit resolution"] - TwelveBit: [2, "12-bit resolution"] - TenBit: [3, "10-bit resolution"] - EightBit: [4, "8-bit resolution"] - CR: - BOOST: - "Off": [0, "Boost mode off. Used when ADC clock < 20MHz"] - "On": [1, "Boost mode on. Used when ADC clock > 20MHz"] diff --git a/peripherals/adc/adc_l0.yaml b/peripherals/adc/adc_l0.yaml deleted file mode 100644 index d4b75fdbc..000000000 --- a/peripherals/adc/adc_l0.yaml +++ /dev/null @@ -1,223 +0,0 @@ -# ADC as used on L0 - -ADC: - ISR: - EOCAL: - _read: - NotComplete: [0, "Calibration is not complete"] - Complete: [1, "Calibration complete"] - _write: - Clear: [1, "Clear the calibration flag"] - AWD: - _read: - NoEvent: [0, "No analog watchdog event occurred"] - Event: [1, "Analog watchdog event occurred"] - _write: - Clear: [1, "Clear the analog watchdog event flag"] - OVR: - _read: - NoOverrun: [0, "No overrun occurred"] - Overrun: [1, "Overrun occurred"] - _write: - Clear: [1, "Clear the overrun flag"] - EOS: - _read: - NotComplete: [0, "Conversion sequence is not complete"] - Complete: [1, "Conversion sequence complete"] - _write: - Clear: [1, "Clear the conversion sequence flag"] - EOC: - _read: - NotComplete: [0, "Channel conversion is not complete"] - Complete: [1, "Channel conversion complete"] - _write: - Clear: [1, "Clear the channel conversion flag"] - EOSMP: - _read: - NotAtEnd: [0, "Not at the end of the samplings phase"] - AtEnd: [1, "End of sampling phase reached"] - _write: - Clear: [1, "Clear the sampling phase flag"] - ADRDY: - _read: - NotReady: [0, "ADC not yet ready to start conversion"] - Ready: [1, "ADC ready to start conversion"] - _write: - Clear: [1, "Clear the ADC ready flag"] - IER: - EOCALIE: - Disabled: [0, "End of calibration interrupt disabled"] - Enabled: [1, "End of calibration interrupt enabled"] - AWDIE: - Disabled: [0, "Analog watchdog interrupt disabled"] - Enabled: [1, "Analog watchdog interrupt enabled"] - OVRIE: - Disabled: [0, "Overrun interrupt disabled"] - Enabled: [1, "Overrun interrupt enabled. An interrupt is generated when the OVR bit is set."] - EOSIE: - Disabled: [0, "EOS interrupt disabled"] - Enabled: [1, "EOS interrupt enabled. An interrupt is generated when the EOS bit is set."] - EOCIE: - Disabled: [0, "EOC interrupt disabled"] - Enabled: [1, "EOC interrupt enabled. An interrupt is generated when the EOC bit is set."] - EOSMPIE: - Disabled: [0, "EOSMP interrupt disabled"] - Enabled: [1, "EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set."] - ADRDYIE: - Disabled: [0, "ADRDY interrupt disabled"] - Enabled: [1, "ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set."] - CR: - ADCAL: - _read: - NotCalibrating: [0, "ADC calibration either not yet performed or completed"] - Calibrating: [1, "ADC calibration in progress"] - _write: - StartCalibration: [1, "Start the ADC calibration sequence"] - ADVREGEN: - Disabled: [0, "ADC voltage regulator disabled"] - Enabled: [1, "ADC voltage regulator enabled"] - ADSTP: - _read: - NotStopping: [0, "No stop command active"] - Stopping: [1, "ADC stopping conversion"] - _write: - StopConversion: [1, "Stop the active conversion"] - ADSTART: - _read: - NotActive: [0, "No conversion ongoing"] - Active: [1, "ADC operating and may be converting"] - _write: - StartConversion: [1, "Start the ADC conversion (may be delayed for hardware triggers)"] - ADDIS: - _read: - NotDisabling: [0, "No disable command active"] - Disabling: [1, "ADC disabling"] - _write: - Disable: [1, "Disable the ADC"] - ADEN: - _read: - Disabled: [0, "ADC disabled"] - Enabled: [1, "ADC enabled"] - _write: - Enabled: [1, "Enable the ADC"] - CFGR1: - AWDCH: [0, 18] - AWDEN: - Disabled: [0, "Analog watchdog disabled"] - Enabled: [1, "Analog watchdog enabled"] - AWDSGL: - AllChannels: [0, "Analog watchdog enabled on all channels"] - SingleChannel: [1, "Analog watchdog enabled on a single channel"] - DISCEN: - Disabled: [0, "Discontinuous mode disabled"] - Enabled: [1, "Discontinuous mode enabled"] - AUTOFF: - Disabled: [0, "Auto-off mode disabled"] - Enabled: [1, "Auto-off mode enabled"] - WAIT: - Disabled: [0, "Wait conversion mode off"] - Enabled: [1, "Wait conversion mode on"] - CONT: - Single: [0, "Single conversion mode"] - Continuous: [1, "Continuous conversion mode"] - OVRMOD: - Preserve: [0, "ADC_DR register is preserved with the old data when an overrun is detected"] - Overwrite: [1, "ADC_DR register is overwritten with the last conversion result when an overrun is detected"] - EXTEN: - Disabled: [0, "Hardware trigger detection disabled"] - RisingEdge: [1, "Hardware trigger detection on the rising edge"] - FallingEdge: [2, "Hardware trigger detection on the falling edge"] - BothEdges: [3, "Hardware trigger detection on both the rising and falling edges"] - EXTSEL: - TIM6_TRGO: [0, "Timer 6 TRGO event"] - TIM21_CH2: [1, "Timer 21 CH2 event"] - TIM2_TRGO: [2, "Timer 2 TRGO event"] - TIM2_CH4: [3, "Timer 2 CH4 event"] - TIM22_TRGO: [4, "Timer 22 TRGO, Timer 21 TRGO event"] - TIM2_CH3: [5, "Timer 2 CH3 event"] - TIM3_TRGO: [6, "Timer 3 TRGO event"] - EXTI_LINE11: [7, "EXTI line 11 event"] - ALIGN: - Right: [0, "Right alignment"] - Left: [1, "Left alignment"] - RES: - TwelveBit: [0, "12 bits"] - TenBit: [1, "10 bits"] - EightBit: [2, "8 bits"] - SixBit: [3, "6 bits"] - SCANDIR: - Upward: [0, "Upward scan (from CHSEL0 to CHSEL18)"] - Backward: [1, "Backward scan (from CHSEL18 to CHSEL0)"] - DMACFG: - OneShot: [0, "DMA one shot mode selected"] - Circular: [1, "DMA circular mode selected"] - DMAEN: - Disabled: [0, "DMA disabled"] - Enabled: [1, "DMA enabled"] - CFGR2: - CKMODE: - ADCLK: [0, "ADCCLK (Asynchronous clock mode)"] - PCLK_Div2: [1, "PCLK/2 (Synchronous clock mode)"] - PCLK_Div4: [2, "PCLK/4 (Synchronous clock mode)"] - PCLK: [3, "PCLK (Synchronous clock mode)"] - TOVS: - TriggerAll: [0, "All oversampled conversions for a channel are done consecutively after a trigger"] - TriggerEach: [1, "Each oversampled conversion for a channel needs a trigger"] - OVSS: [0, 8] - OVSR: - Mul2: [0, "2x"] - Mul4: [1, "4x"] - Mul8: [2, "8x"] - Mul16: [3, "16x"] - Mul32: [4, "32x"] - Mul64: [5, "64x"] - Mul128: [6, "128x"] - Mul256: [7, "256x"] - OVSE: - Disabled: [0, "Oversampler disabled"] - Enabled: [1, "Oversampler enabled"] - SMPR: - SMP: - Cycles1_5: [0, "1.5 ADC clock cycles"] - Cycles3_5: [1, "3.5 ADC clock cycles"] - Cycles7_5: [2, "7.5 ADC clock cycles"] - Cycles12_5: [3, "12.5 ADC clock cycles"] - Cycles19_5: [4, "19.5 ADC clock cycles"] - Cycles39_5: [5, "39.5 ADC clock cycles"] - Cycles79_5: [6, "79.5 ADC clock cycles"] - Cycles160_5: [7, "160.5 ADC clock cycles"] - TR: - HT: [0, 2047] - LT: [0, 2047] - CHSELR: - "CHSEL*": - NotSelected: [0, "Input Channel is not selected for conversion"] - Selected: [1, "Input Channel is selected for conversion"] - DR: - DATA: [0, 65535] - CALFACT: - CALFACT: [0, 127] - CCR: - LFMEN: - Disabled: [0, "Low Frequency Mode disabled"] - Enabled: [1, "Low Frequency Mode enabled"] - TSEN: - Disabled: [0, "Temperature sensor disabled"] - Enabled: [1, "Temperature sensor enabled"] - VREFEN: - Disabled: [0, "VREFINT disabled"] - Enabled: [1, "VREFINT enabled"] - PRESC: - Div1: [0, "Input ADC clock not divided"] - Div2: [1, "Input ADC clock divided by 2"] - Div4: [2, "Input ADC clock divided by 4"] - Div6: [3, "Input ADC clock divided by 6"] - Div8: [4, "Input ADC clock divided by 8"] - Div10: [5, "Input ADC clock divided by 10"] - Div12: [6, "Input ADC clock divided by 12"] - Div16: [7, "Input ADC clock divided by 16"] - Div32: [8, "Input ADC clock divided by 32"] - Div64: [9, "Input ADC clock divided by 64"] - Div128: [10, "Input ADC clock divided by 128"] - Div256: [11, "Input ADC clock divided by 256"] - diff --git a/peripherals/adc/adc_v2.yaml b/peripherals/adc/adc_v2.yaml deleted file mode 100644 index d193c54e6..000000000 --- a/peripherals/adc/adc_v2.yaml +++ /dev/null @@ -1,159 +0,0 @@ -# ADC as used on F2, F4 and F7 - -_include: - - "adc_array.yaml" - -"ADC?": - SR: - OVR: - NoOverrun: [0, "No overrun occurred"] - Overrun: [1, "Overrun occurred"] - STRT: - NotStarted: [0, "No regular channel conversion started"] - Started: [1, "Regular channel conversion has started"] - JSTRT: - NotStarted: [0, "No injected channel conversion started"] - Started: [1, "Injected channel conversion has started"] - JEOC: - NotComplete: [0, "Conversion is not complete"] - Complete: [1, "Conversion complete"] - EOC: - NotComplete: [0, "Conversion is not complete"] - Complete: [1, "Conversion complete"] - AWD: - NoEvent: [0, "No analog watchdog event occurred"] - Event: [1, "Analog watchdog event occurred"] - CR1: - OVRIE: - Disabled: [0, "Overrun interrupt disabled"] - Enabled: [1, "Overrun interrupt enabled"] - RES: - TwelveBit: [0, "12-bit (15 ADCCLK cycles)"] - TenBit: [1, "10-bit (13 ADCCLK cycles)"] - EightBit: [2, "8-bit (11 ADCCLK cycles)"] - SixBit: [3, "6-bit (9 ADCCLK cycles)"] - AWDEN: - Disabled: [0, "Analog watchdog disabled on regular channels"] - Enabled: [1, "Analog watchdog enabled on regular channels"] - JAWDEN: - Disabled: [0, "Analog watchdog disabled on injected channels"] - Enabled: [1, "Analog watchdog enabled on injected channels"] - DISCNUM: [0, 7] - JDISCEN: - Disabled: [0, "Discontinuous mode on injected channels disabled"] - Enabled: [1, "Discontinuous mode on injected channels enabled"] - DISCEN: - Disabled: [0, "Discontinuous mode on regular channels disabled"] - Enabled: [1, "Discontinuous mode on regular channels enabled"] - JAUTO: - Disabled: [0, "Automatic injected group conversion disabled"] - Enabled: [1, "Automatic injected group conversion enabled"] - AWDSGL: - AllChannels: [0, "Analog watchdog enabled on all channels"] - SingleChannel: [1, "Analog watchdog enabled on a single channel"] - SCAN: - Disabled: [0, "Scan mode disabled"] - Enabled: [1, "Scan mode enabled"] - JEOCIE: - Disabled: [0, "JEOC interrupt disabled"] - Enabled: [1, "JEOC interrupt enabled"] - AWDIE: - Disabled: [0, "Analogue watchdog interrupt disabled"] - Enabled: [1, "Analogue watchdog interrupt enabled"] - EOCIE: - Disabled: [0, "EOC interrupt disabled"] - Enabled: [1, "EOC interrupt enabled"] - AWDCH: [0, 18] - CR2: - SWSTART: - _write: - Start: [1, "Starts conversion of regular channels"] - EXTEN: - Disabled: [0, "Trigger detection disabled"] - RisingEdge: [1, "Trigger detection on the rising edge"] - FallingEdge: [2, "Trigger detection on the falling edge"] - BothEdges: [3, "Trigger detection on both the rising and falling edges"] - EXTSEL: - TIM1CC1: [0, "Timer 1 CC1 event"] - TIM1CC2: [1, "Timer 1 CC2 event"] - TIM1CC3: [2, "Timer 1 CC3 event"] - TIM2CC2: [3, "Timer 2 CC2 event"] - TIM2CC3: [4, "Timer 2 CC3 event"] - TIM2CC4: [5, "Timer 2 CC4 event"] - TIM2TRGO: [6, "Timer 2 TRGO event"] - JSWSTART: - _write: - Start: [1, "Starts conversion of injected channels"] - JEXTEN: - Disabled: [0, "Trigger detection disabled"] - RisingEdge: [1, "Trigger detection on the rising edge"] - FallingEdge: [2, "Trigger detection on the falling edge"] - BothEdges: [3, "Trigger detection on both the rising and falling edges"] - JEXTSEL: - TIM1TRGO: [0, "Timer 1 TRGO event"] - TIM1CC4: [1, "Timer 1 CC4 event"] - TIM2TRGO: [2, "Timer 2 TRGO event"] - TIM2CC1: [3, "Timer 2 CC1 event"] - TIM3CC4: [4, "Timer 3 CC4 event"] - TIM4TRGO: [5, "Timer 4 TRGO event"] - TIM8CC4: [7, "Timer 8 CC4 event"] - TIM1TRGO2: [8, "Timer 1 TRGO(2) event"] - TIM8TRGO: [9, "Timer 8 TRGO event"] - TIM8TRGO2: [10, "Timer 8 TRGO(2) event"] - TIM3CC3: [11, "Timer 3 CC3 event"] - TIM5TRGO: [12, "Timer 5 TRGO event"] - TIM3CC1: [13, "Timer 3 CC1 event"] - TIM6TRGO: [14, "Timer 6 TRGO event"] - ALIGN: - Right: [0, "Right alignment"] - Left: [1, "Left alignment"] - EOCS: - EachSequence: [0, "The EOC bit is set at the end of each sequence of regular conversions"] - EachConversion: [1, "The EOC bit is set at the end of each regular conversion"] - DDS: - Single: [0, "No new DMA request is issued after the last transfer"] - Continuous: [1, "DMA requests are issued as long as data are converted and DMA=1"] - DMA: - Disabled: [0, "DMA mode disabled"] - Enabled: [1, "DMA mode enabled"] - CONT: - Single: [0, "Single conversion mode"] - Continuous: [1, "Continuous conversion mode"] - ADON: - Disabled: [0, "Disable ADC conversion and go to power down mode"] - Enabled: [1, "Enable ADC"] - "SMPR?": - "SMP*": - Cycles3: [0, "3 cycles"] - Cycles15: [1, "15 cycles"] - Cycles28: [2, "28 cycles"] - Cycles56: [3, "56 cycles"] - Cycles84: [4, "84 cycles"] - Cycles112: [5, "112 cycles"] - Cycles144: [6, "144 cycles"] - Cycles480: [7, "480 cycles"] - HTR: - HT: [0, 4095] - LTR: - LT: [0, 4095] - SQR1: - L: [0, 15] - "SQR?": - "SQ*": [0, 18] - JSQR: - JL: [0, 3] - "JSQ?": [0, 18] - -ADC_Common: - CCR: - TSVREFE: - Disabled: [0, "Temperature sensor and V_REFINT channel disabled"] - Enabled: [1, "Temperature sensor and V_REFINT channel enabled"] - VBATE: - Disabled: [0, "V_BAT channel disabled"] - Enabled: [1, "V_BAT channel enabled"] - ADCPRE: - Div2: [0, "PCLK2 divided by 2"] - Div4: [1, "PCLK2 divided by 4"] - Div6: [2, "PCLK2 divided by 6"] - Div8: [3, "PCLK2 divided by 8"] diff --git a/peripherals/adc/adc_v2_multi.yaml b/peripherals/adc/adc_v2_multi.yaml deleted file mode 100644 index d161a1663..000000000 --- a/peripherals/adc/adc_v2_multi.yaml +++ /dev/null @@ -1,34 +0,0 @@ -# ADC_Common as used on F2, F4 and F7 with multiple ADCs - -_include: - - "adc_v2_single.yaml" - -ADC_Common: - CCR: - _modify: - # This appears to have the wrong name in every single SVD. - MULT: - name: MULTI - DMA: - Disabled: [0, "DMA mode disabled"] - Mode1: [1, "DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)"] - Mode2: [2, "DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)"] - Mode3: [3, "DMA mode 3 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)"] - DDS: - Single: [0, "No new DMA request is issued after the last transfer"] - Continuous: [1, "DMA requests are issued as long as data are converted and DMA=01, 10 or 11"] - DELAY: [0, 15] - MULTI: - Independent: [0, "All the ADCs independent: independent mode"] - DualRJ: [1, "Dual ADC1 and ADC2, combined regular and injected simultaneous mode"] - DualRA: [2, "Dual ADC1 and ADC2, combined regular and alternate trigger mode"] - DualJ: [5, "Dual ADC1 and ADC2, injected simultaneous mode only"] - DualR: [6, "Dual ADC1 and ADC2, regular simultaneous mode only"] - DualI: [7, "Dual ADC1 and ADC2, interleaved mode only"] - DualA: [9, "Dual ADC1 and ADC2, alternate trigger mode only"] - TripleRJ: [17, "Triple ADC, regular and injected simultaneous mode"] - TripleRA: [18, "Triple ADC, regular and alternate trigger mode"] - TripleJ: [21, "Triple ADC, injected simultaneous mode only"] - TripleR: [22, "Triple ADC, regular simultaneous mode only"] - TripleI: [23, "Triple ADC, interleaved mode only"] - TripleA: [24, "Triple ADC, alternate trigger mode only"] diff --git a/peripherals/adc/adc_v2_single.yaml b/peripherals/adc/adc_v2_single.yaml deleted file mode 100644 index 820e875d0..000000000 --- a/peripherals/adc/adc_v2_single.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# ADC_Common as used on F4 with single ADC and a CSR register - -_include: - - "adc_v2.yaml" - -ADC_Common: - CSR: - "OVR?": - NoOverrun: [0, "No overrun occurred"] - Overrun: [1, "Overrun occurred"] - "STRT?": - NotStarted: [0, "No regular channel conversion started"] - Started: [1, "Regular channel conversion has started"] - "JSTRT?": - NotStarted: [0, "No injected channel conversion started"] - Started: [1, "Injected channel conversion has started"] - "JEOC?": - NotComplete: [0, "Conversion is not complete"] - Complete: [1, "Conversion complete"] - "EOC?": - NotComplete: [0, "Conversion is not complete"] - Complete: [1, "Conversion complete"] - "AWD?": - NoEvent: [0, "No analog watchdog event occurred"] - Event: [1, "Analog watchdog event occurred"] diff --git a/peripherals/adc/adc_v2_smpr.yaml b/peripherals/adc/adc_v2_smpr.yaml deleted file mode 100644 index ded6d69bd..000000000 --- a/peripherals/adc/adc_v2_smpr.yaml +++ /dev/null @@ -1,87 +0,0 @@ -# Fix the poorly defined SMPR fields in ADCv2 - -"ADC?": - SMPR1: - _modify: - SMPx_x: - name: SMP18 - description: Channel 18 sampling time selection - bitWidth: 3 - bitOffset: 24 - _add: - SMP17: - description: Channel 17 sampling time selection - bitWidth: 3 - bitOffset: 21 - SMP16: - description: Channel 16 sampling time selection - bitWidth: 3 - bitOffset: 18 - SMP15: - description: Channel 15 sampling time selection - bitWidth: 3 - bitOffset: 15 - SMP14: - description: Channel 14 sampling time selection - bitWidth: 3 - bitOffset: 12 - SMP13: - description: Channel 13 sampling time selection - bitWidth: 3 - bitOffset: 9 - SMP12: - description: Channel 12 sampling time selection - bitWidth: 3 - bitOffset: 6 - SMP11: - description: Channel 11 sampling time selection - bitWidth: 3 - bitOffset: 3 - SMP10: - description: Channel 10 sampling time selection - bitWidth: 3 - bitOffset: 0 - SMPR2: - _modify: - SMPx_x: - name: SMP9 - description: Channel 9 sampling time selection - bitWidth: 3 - bitOffset: 27 - _add: - SMP8: - description: Channel 8 sampling time selection - bitWidth: 3 - bitOffset: 24 - SMP7: - description: Channel 7 sampling time selection - bitWidth: 3 - bitOffset: 21 - SMP6: - description: Channel 6 sampling time selection - bitWidth: 3 - bitOffset: 18 - SMP5: - description: Channel 5 sampling time selection - bitWidth: 3 - bitOffset: 15 - SMP4: - description: Channel 4 sampling time selection - bitWidth: 3 - bitOffset: 12 - SMP3: - description: Channel 3 sampling time selection - bitWidth: 3 - bitOffset: 9 - SMP2: - description: Channel 2 sampling time selection - bitWidth: 3 - bitOffset: 6 - SMP1: - description: Channel 1 sampling time selection - bitWidth: 3 - bitOffset: 3 - SMP0: - description: Channel 0 sampling time selection - bitWidth: 3 - bitOffset: 0 diff --git a/peripherals/adc/adc_v3.yaml b/peripherals/adc/adc_v3.yaml deleted file mode 100644 index 51f6b4adc..000000000 --- a/peripherals/adc/adc_v3.yaml +++ /dev/null @@ -1,193 +0,0 @@ -# ADC as used on H7 and F3 - -"ADC,ADC?": - ISR: - JQOVF: - _read: - NoOverflow: [0, "No injected context queue overflow has occurred"] - Overflow: [1, "Injected context queue overflow has occurred"] - _write: - Clear: [1, "Clear injected context queue overflow flag"] - "AWD?": - _read: - NoEvent: [0, "No analog watchdog event occurred"] - Event: [1, "Analog watchdog event occurred"] - _write: - Clear: [1, "Clear analog watchdog event occurred flag"] - OVR: - _read: - NoOverrun: [0, "No overrun occurred"] - Overrun: [1, "Overrun occurred"] - _write: - Clear: [1, "Clear overrun occurred flag"] - JEOS: - _read: - NotComplete: [0, "Injected sequence is not complete"] - Complete: [1, "Injected sequence complete"] - _write: - Clear: [1, "Clear Injected sequence complete flag"] - EOS: - _read: - NotComplete: [0, "Regular sequence is not complete"] - Complete: [1, "Regular sequence complete"] - _write: - Clear: [1, "Clear regular sequence complete flag"] - JEOC: - _read: - NotComplete: [0, "Injected conversion is not complete"] - Complete: [1, "Injected conversion complete"] - _write: - Clear: [1, "Clear injected conversion complete flag"] - EOC: - _read: - NotComplete: [0, "Regular conversion is not complete"] - Complete: [1, "Regular conversion complete"] - _write: - Clear: [1, "Clear regular conversion complete flag"] - EOSMP: - _read: - NotEnded: [0, "End of sampling phase no yet reached"] - Ended: [1, "End of sampling phase reached"] - _write: - Clear: [1, "Clear end of sampling phase reached flag"] - ADRDY: - _read: - NotReady: [0, "ADC is not ready to start conversion"] - Ready: [1, "ADC is ready to start conversion"] - _write: - Clear: [1, "Clear ADC is ready to start conversion flag"] - IER: - JQOVFIE: - Disabled: [0, "Injected context queue overflow interrupt disabled"] - Enabled: [1, "Injected context queue overflow interrupt enabled"] - "AWD?IE": - Disabled: [0, "Analog watchdog interrupt disabled"] - Enabled: [1, "Analog watchdog interrupt enabled"] - JEOSIE: - Disabled: [0, "End of injected sequence interrupt disabled"] - Enabled: [1, "End of injected sequence interrupt enabled"] - EOSIE: - Disabled: [0, "End of regular sequence interrupt disabled"] - Enabled: [1, "End of regular sequence interrupt enabled"] - JEOCIE: - Disabled: [0, "End of injected conversion interrupt disabled"] - Enabled: [1, "End of injected conversion interrupt enabled"] - EOCIE: - Disabled: [0, "End of regular conversion interrupt disabled"] - Enabled: [1, "End of regular conversion interrupt enabled"] - OVRIE: - Disabled: [0, "Overrun interrupt disabled"] - Enabled: [1, "Overrun interrupt enabled"] - EOSMPIE: - Disabled: [0, "End of regular conversion sampling phase interrupt disabled"] - Enabled: [1, "End of regular conversion sampling phase interrupt enabled"] - ADRDYIE: - Disabled: [0, "ADC ready interrupt disabled"] - Enabled: [1, "ADC ready interrupt enabled"] - CR: - ADCAL: - Complete: [0, "Calibration complete"] - Calibration: [1, "Start the calibration of the ADC"] - ADCALDIF: - SingleEnded: [0, "Calibration for single-ended mode"] - Differential: [1, "Calibration for differential mode"] - JADSTP,ADSTP: - Stop: [1, "Stop conversion of channel"] - JADSTART,ADSTART: - Start: [1, "Starts conversion of channel"] - ADDIS: - _write: - Disable: [0, "Disable ADC conversion and go to power down mode"] - ADEN: - _write: - Enable: [1, "Enable ADC"] - CFGR: - AWD1CH: [0, 19] - JAUTO: - Disabled: [0, "Automatic injected group conversion disabled"] - Enabled: [1, "Automatic injected group conversion enabled"] - JAWD1EN: - Disabled: [0, "Analog watchdog 1 disabled on injected channels"] - Enabled: [1, "Analog watchdog 1 enabled on injected channels"] - AWD1EN: - Disabled: [0, "Analog watchdog 1 disabled on regular channels"] - Enabled: [1, "Analog watchdog 1 enabled on regular channels"] - AWD1SGL: - All: [0, "Analog watchdog 1 enabled on all channels"] - Single: [1, "Analog watchdog 1 enabled on single channel selected in AWD1CH"] - JQM: - Mode0: [0, "JSQR Mode 0: Queue maintains the last written configuration into JSQR"] - Mode1: [1, "JSQR Mode 1: An empty queue disables software and hardware triggers of the injected sequence"] - JDISCEN: - Disabled: [0, "Discontinuous mode on injected channels disabled"] - Enabled: [1, "Discontinuous mode on injected channels enabled"] - DISCNUM: [0, 7] - DISCEN: - Disabled: [0, "Discontinuous mode on regular channels disabled"] - Enabled: [1, "Discontinuous mode on regular channels enabled"] - AUTDLY: - "Off": [0, "Auto delayed conversion mode off"] - "On": [1, "Auto delayed conversion mode on"] - CONT: - Single: [0, "Single conversion mode"] - Continuous: [1, "Continuous conversion mode"] - OVRMOD: - Preserve: [0, "Preserve DR register when an overrun is detected"] - Overwrite: [1, "Overwrite DR register when an overrun is detected"] - EXTSEL: - TIM1_CC1: [0, "Timer 1 CC1 event"] - TIM1_CC2: [1, "Timer 1 CC2 event"] - TIM1_CC3: [2, "Timer 1 CC3 event"] - TIM2_CC2: [3, "Timer 2 CC2 event"] - TIM3_TRGO: [4, "Timer 3 TRGO event"] - EXTI11: [6, "EXTI line 11"] - TIM1_TRGO: [9, "Timer 1 TRGO event"] - TIM1_TRGO2: [10, "Timer 1 TRGO2 event"] - TIM2_TRGO: [11, "Timer 2 TRGO event"] - TIM6_TRGO: [13, "Timer 6 TRGO event"] - TIM15_TRGO: [14, "Timer 15 TRGO event"] - TIM3_CC4: [15, "Timer 3 CC4 event"] - CFGR,JSQR: - EXTEN,JEXTEN: - Disabled: [0, "Trigger detection disabled"] - RisingEdge: [1, "Trigger detection on the rising edge"] - FallingEdge: [2, "Trigger detection on the falling edge"] - BothEdges: [3, "Trigger detection on both the rising and falling edges"] - JSQR: - JEXTSEL: - TIM1_TRGO: [0, "Timer 1 TRGO event"] - TIM1_CC4: [1, "Timer 1 CC4 event"] - TIM2_TRGO: [2, "Timer 2 TRGO event"] - TIM2_CC1: [3, "Timer 2 CC1 event"] - TIM3_CC4: [4, "Timer 3 CC4 event"] - EXTI15: [6, "EXTI line 15"] - TIM1_TRGO2: [8, "Timer 1 TRGO2 event"] - TIM3_CC3: [11, "Timer 3 CC3 event"] - TIM3_TRGO: [12, "Timer 3 TRGO event"] - TIM3_CC1: [13, "Timer 3 CC1 event"] - TIM6_TRGO: [14, "Timer 6 TRGO event"] - TIM15_TRGO: [15, "Timer 15 TRGO event"] - AWD2CR: - _split: [AWD2CH] - "AWD2CH*": - NotMonitored: [0, "Input channel not monitored by AWDx"] - Monitored: [1, "Input channel monitored by AWDx"] - AWD3CR: - _split: [AWD3CH] - "AWD3CH*": - NotMonitored: [0, "Input channel not monitored by AWDx"] - Monitored: [1, "Input channel monitored by AWDx"] - # Sequences - SQR1: - L: [0, 15] # Total number of conversions in regular sequence - SQR?: - "SQ*": [0, 19] # Channel number for Nth item in regular seqeunce - JSQR: - JL: [0, 3] # Total number of conversions in injected sequence - "JSQ?": [0, 19] # Channel number for Nth item in injected sequence - # Differential mode - DIFSEL: - _split: ["DIFSEL*"] - "DIFSEL*": - SingleEnded: [0, "Input channel is configured in single-ended mode"] - Differential: [1, "Input channel is configured in differential mode"] diff --git a/peripherals/adc/adc_v3_common.yaml b/peripherals/adc/adc_v3_common.yaml deleted file mode 100644 index 038e2955a..000000000 --- a/peripherals/adc/adc_v3_common.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# ADC_Common as used on H7 and F3 - -_include: - - "adc_v3_common_single.yaml" - -"ADC*_*": - CCR: - DELAY: [0, 15] - DUAL: - Independent: [0, "Independent mode"] - DualRJ: [1, "Dual, combined regular simultaneous + injected simultaneous mode"] - DualRA: [2, "Dual, combined regular simultaneous + alternate trigger mode"] - DualIJ: [3, "Dual, combined interleaved mode + injected simultaneous mode"] - DualJ: [5, "Dual, injected simultaneous mode only"] - DualR: [6, "Dual, regular simultaneous mode only"] - DualI: [7, "Dual, interleaved mode only"] - DualA: [9, "Dual, alternate trigger mode only"] diff --git a/peripherals/adc/adc_v3_common_f3.yaml b/peripherals/adc/adc_v3_common_f3.yaml deleted file mode 100644 index ff0eb3efa..000000000 --- a/peripherals/adc/adc_v3_common_f3.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# ADC_Common with F3 specific fields - -_include: - - "adc_v3_common_f3_single.yaml" - - "adc_v3_common.yaml" - -"ADC*_*": - CCR: - MDMA: - Disabled: [0, "MDMA mode disabled"] - Bits12_10: [2, "MDMA mode enabled for 12 and 10-bit resolution"] - Bits8_6: [3, "MDMA mode enabled for 8 and 6-bit resolution"] - DMACFG: - OneShot: [0, "DMA one shot mode selected"] - Circulator: [1, "DMA circular mode selected"] diff --git a/peripherals/adc/adc_v3_common_f3_single.yaml b/peripherals/adc/adc_v3_common_f3_single.yaml deleted file mode 100644 index 93c2df0d7..000000000 --- a/peripherals/adc/adc_v3_common_f3_single.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# ADC_Common with F3 specific fields -# limited to fields available even on parts with a single ADC - -"ADC*_*": - CCR: - VBATEN: - Disabled: [0, "V_BAT channel disabled"] - Enabled: [1, "V_BAT channel enabled"] - TSEN: - Disabled: [0, "Temperature sensor channel disabled"] - Enabled: [1, "Temperature sensor channel enabled"] diff --git a/peripherals/adc/adc_v3_common_g4.yaml b/peripherals/adc/adc_v3_common_g4.yaml deleted file mode 100644 index 8ac20ea0d..000000000 --- a/peripherals/adc/adc_v3_common_g4.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# ADC_Common with G4 specific fields - -_include: - - "adc_v3_common.yaml" - -"ADC*_*": - CCR: - VBATSEL: - Disabled: [0, "V_BAT channel disabled"] - Enabled: [1, "V_BAT channel enabled"] - VSENSESEL: - Disabled: [0, "Temperature sensor channel disabled"] - Enabled: [1, "Temperature sensor channel enabled"] diff --git a/peripherals/adc/adc_v3_common_h7.yaml b/peripherals/adc/adc_v3_common_h7.yaml deleted file mode 100644 index 26ab60e75..000000000 --- a/peripherals/adc/adc_v3_common_h7.yaml +++ /dev/null @@ -1,30 +0,0 @@ -# ADC_Common with H7 specific fields - -_include: - - "adc_v3_common.yaml" - -"ADC*_Common": - CCR: - VSENSEEN: - Disabled: [0, "Temperature sensor channel disabled"] - Enabled: [1, "Temperature sensor channel enabled"] - VBATEN: - Disabled: [0, "V_BAT channel disabled"] - Enabled: [1, "V_BAT channel enabled"] - PRESC: - Div1: [0, "adc_ker_ck_input not divided"] - Div2: [1, "adc_ker_ck_input divided by 2"] - Div4: [2, "adc_ker_ck_input divided by 4"] - Div6: [3, "adc_ker_ck_input divided by 6"] - Div8: [4, "adc_ker_ck_input divided by 8"] - Div10: [5, "adc_ker_ck_input divided by 10"] - Div12: [6, "adc_ker_ck_input divided by 12"] - Div16: [7, "adc_ker_ck_input divided by 16"] - Div32: [8, "adc_ker_ck_input divided by 32"] - Div64: [9, "adc_ker_ck_input divided by 64"] - Div128: [10, "adc_ker_ck_input divided by 128"] - Div256: [11, "adc_ker_ck_input divided by 256"] - DAMDF: - NoPack: [0, "Without data packing, CDR/CDR2 not used"] - Format32to10: [2, "CDR formatted for 32-bit down to 10-bit resolution"] - Format8: [3, "CDR formatted for 8-bit resolution"] diff --git a/peripherals/adc/adc_v3_common_single.yaml b/peripherals/adc/adc_v3_common_single.yaml deleted file mode 100644 index 8b0a9921a..000000000 --- a/peripherals/adc/adc_v3_common_single.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# ADC_Common as used on H7 and F3 -# limited to fields available even on parts with a single ADC - -"ADC*_*": - CSR: - JQOVF_MST,JQOVF_SLV: - NoOverflow: [0, "No injected context queue overflow has occurred"] - Overflow: [1, "Injected context queue overflow has occurred"] - "AWD?_MST,AWD?_SLV": - NoEvent: [0, "No analog watchdog event occurred"] - Event: [1, "Analog watchdog event occurred"] - OVR_MST,OVR_SLV: - NoOverrun: [0, "No overrun occurred"] - Overrun: [1, "Overrun occurred"] - JEOS_MST,JEOS_SLV: - NotComplete: [0, "Injected sequence is not complete"] - Complete: [1, "Injected sequence complete"] - EOS_MST,EOS_SLV: - NotComplete: [0, "Regular sequence is not complete"] - Complete: [1, "Regular sequence complete"] - JEOC_MST,JEOC_SLV: - NotComplete: [0, "Injected conversion is not complete"] - Complete: [1, "Injected conversion complete"] - EOC_MST,EOC_SLV: - NotComplete: [0, "Regular conversion is not complete"] - Complete: [1, "Regular conversion complete"] - EOSMP_MST,EOSMP_SLV: - NotEnded: [0, "End of sampling phase no yet reached"] - Ended: [1, "End of sampling phase reached"] - ADRDY_MST,ADRDY_SLV: - NotReady: [0, "ADC is not ready to start conversion"] - Ready: [1, "ADC is ready to start conversion"] - CCR: - VREFEN: - Disabled: [0, "V_REFINT channel disabled"] - Enabled: [1, "V_REFINT channel enabled"] - CKMODE: - Asynchronous: [0, "Use Kernel Clock adc_ker_ck_input divided by PRESC. Asynchronous to AHB clock"] - SyncDiv1: [1, "Use AHB clock rcc_hclk3. In this case rcc_hclk must equal sys_d1cpre_ck"] - SyncDiv2: [2, "Use AHB clock rcc_hclk3 divided by 2"] - SyncDiv4: [3, "Use AHB clock rcc_hclk3 divided by 4"] diff --git a/peripherals/adc/adc_v3_f3.yaml b/peripherals/adc/adc_v3_f3.yaml deleted file mode 100644 index dbf277fbf..000000000 --- a/peripherals/adc/adc_v3_f3.yaml +++ /dev/null @@ -1,53 +0,0 @@ -# ADC v3 with F3 specific fields -_include: - - "adc_v3.yaml" - -"ADC,ADC?": - CR: - ADVREGEN: - Intermediate: [0, "Intermediate state required when moving the ADC voltage regulator between states"] - Enabled: [1, "ADC voltage regulator enabled"] - Disabled: [2, "ADC voltage regulator disabled"] - CFGR: - EXTSEL: - HRTIM_ADCTRG1: [7, "HRTIM_ADCTRG1 event"] - HRTIM_ADCTRG3: [8, "HRTIM_ADCTRG3 event"] - ALIGN: - Right: [0, "Right alignment"] - Left: [1, "Left alignment"] - RES: - Bits12: [0, "12-bit"] - Bits10: [1, "10-bit"] - Bits8: [2, "8-bit"] - Bits6: [3, "6-bit"] - DMACFG: - OneShot: [0, "DMA One Shot Mode selected"] - Circular: [1, "DMA circular mode selected"] - DMAEN: - Disabled: [0, "DMA disabled"] - Enabled: [1, "DMA enabled"] - JSQR: - JEXTSEL: - HRTIM_ADCTRG2: [9, "HRTIM_ADCTRG2 event"] - HRTIM_ADCTRG4: [10, "HRTIM_ADCTRG4 event"] - "SMPR?": - "SMP*": - Cycles1_5: [0, "1.5 ADC clock cycles"] - Cycles2_5: [1, "2.5 ADC clock cycles"] - Cycles4_5: [2, "4.5 ADC clock cycles"] - Cycles7_5: [3, "7.5 ADC clock cycles"] - Cycles19_5: [4, "19.5 ADC clock cycles"] - Cycles61_5: [5, "61.5 ADC clock cycles"] - Cycles181_5: [6, "181.5 ADC clock cycles"] - Cycles601_5: [7, "601.5 ADC clock cycles"] - "TR?": - "HT?": [0, 0xFFF] - "LT?": [0, 0xFFF] - "OFR?": - "OFFSET?_EN": - Disabled: [0, "Offset disabled"] - Enabled: [1, "Offset enabled"] - "OFFSET?_CH": [0, 31] - "OFFSET?": [0, 0xFFF] - CALFACT: - "CALFACT_?": [0, 0x7F] diff --git a/peripherals/adc/adc_v3_g4.yaml b/peripherals/adc/adc_v3_g4.yaml deleted file mode 100644 index 9abb81a29..000000000 --- a/peripherals/adc/adc_v3_g4.yaml +++ /dev/null @@ -1,108 +0,0 @@ -# ADC v3 with G4 specific fields - -_include: - - "adc_v3.yaml" - -"ADC,ADC?": - DIFSEL: - _merge: - - "DIFSEL*" - CR: - ADVREGEN: - Disabled: [0, "ADC voltage regulator disabled"] - Enabled: [1, "ADC voltage regulator enabled"] - DEEPPWD: - Disabled: [0, ADC not in Deep-power down] - Enabled: [1, ADC in Deep-power-down (default reset state)] - - CFGR: - JQDIS: - Enabled: [0, Injected Queue enabled] - Disabled: [1, Injected Queue disabled] - AWD1CH: [0, 18] - EXTSEL: - HRTIM_ADCTRG1: [7, "HRTIM_ADCTRG1 event"] - HRTIM_ADCTRG3: [8, "HRTIM_ADCTRG3 event"] - ALIGN: - Right: [0, "Right alignment"] - Left: [1, "Left alignment"] - RES: - Bits12: [0, "12-bit"] - Bits10: [1, "10-bit"] - Bits8: [2, "8-bit"] - Bits6: [3, "6-bit"] - DMACFG: - OneShot: [0, "DMA One Shot Mode selected"] - Circular: [1, "DMA circular mode selected"] - DMAEN: - Disabled: [0, "DMA disabled"] - Enabled: [1, "DMA enabled"] - "CFGR2": - SMPTRIG: - Disabled: [0, Sampling time control trigger mode disabled] - Enabled: [1, Sampling time control trigger mode enabled] - BULB: - Disabled: [0, Bulb sampling mode disabled] - Enabled: [1, "Bulb sampling mode enabled. Immediately start sampling after last conversion finishes."] - SWTRIG: - Disabled: [0, End sampling period and start conversion] - Enabled: [1, Start sampling period] - GCOMP: - Disabled: [0, Regular ADC operating mode] - Enabled: [1, Gain compensation enabled and applies to all channels] - ROVSM: - Continued: [0, "Oversampling is temporary stopped and continued after injection sequence"] - Resumed: [1, "Oversampling is aborted and resumed from start after injection sequence"] - TROVS: - Automatic: [0, "All oversampled conversions for a channel are run following a trigger"] - Triggered: [1, "Each oversampled conversion for a channel needs a new trigger"] - OVSS: - NoShift: [0, "No right shift applied to oversampling result"] - Shift1: [1, "Shift oversampling result right by 1 bit"] - Shift2: [2, "Shift oversampling result right by 2 bits"] - Shift3: [3, "Shift oversampling result right by 3 bits"] - Shift4: [4, "Shift oversampling result right by 4 bits"] - Shift5: [5, "Shift oversampling result right by 5 bits"] - Shift6: [6, "Shift oversampling result right by 6 bits"] - Shift7: [7, "Shift oversampling result right by 7 bits"] - Shift8: [8, "Shift oversampling result right by 8 bits"] - OVSR: - OS2: [0, "Oversampling ratio of 2"] - OS4: [1, "Oversampling ratio of 4"] - OS8: [2, "Oversampling ratio of 8"] - OS16: [3, "Oversampling ratio of 16"] - OS32: [4, "Oversampling ratio of 32"] - OS64: [5, "Oversampling ratio of 64"] - OS128: [6, "Oversampling ratio of 128"] - OS256: [7, "Oversampling ratio of 256"] - JOVSE: - Disabled: [0, "Injected oversampling disabled"] - Enabled: [1, "Injected oversampling enabled"] - ROVSE: - Disabled: [0, "Regular oversampling disabled"] - Enabled: [1, "Regular oversampling enabled"] - "SMPR1": - "SMPPLUS": - Normal: [0, "2.5 in SMPR remains 2.5 cycles"] - Plus1: [1, "2.5 in SMPR becomes 3.5 cycles"] - "SMPR?": - "SMP?,SMP??": - Cycles2_5: [0, "2.5 ADC clock cycles"] - Cycles6_5: [1, "6.5 ADC clock cycles"] - Cycles12_5: [2, "12.5 ADC clock cycles"] - Cycles24_5: [3, "24.5 ADC clock cycles"] - Cycles47_5: [4, "47.5 ADC clock cycles"] - Cycles92_5: [5, "92.5 ADC clock cycles"] - Cycles247_5: [6, "247.5 ADC clock cycles"] - Cycles640_5: [7, "640.5 ADC clock cycles"] - "TR?": - "HT?": [0, 0xFFF] - "LT?": [0, 0xFFF] - "OFR?": - "OFFSET?_EN": - Disabled: [0, "Offset disabled"] - Enabled: [1, "Offset enabled"] - "OFFSET?_CH": [0, 31] - "OFFSET?": [0, 0xFFF] - CALFACT: - "CALFACT_?": [0, 0x7F] diff --git a/peripherals/adc/adc_v3_h7.yaml b/peripherals/adc/adc_v3_h7.yaml deleted file mode 100644 index b3cbf094c..000000000 --- a/peripherals/adc/adc_v3_h7.yaml +++ /dev/null @@ -1,96 +0,0 @@ -# ADC v3 with H7 specific fields - -_include: - - "adc_v3.yaml" - -"ADC,ADC?": - CR: - ADVREGEN: - Disabled: [0, "ADC voltage regulator disabled"] - Enabled: [1, "ADC voltage regulator enabled"] - DEEPPWD: - PowerUp: [0, "ADC not in deep power down"] - PowerDown: [1, "ADC in deep power down"] - "LINCALRDYW?": - Reset: [0, "LINCALFACT Word Read"] - Set: [1, "LINCALFACT Word Write"] - ADCALLIN: - NoLinearity: [0, "ADC calibration without linearaity calibration"] - Linearity: [1, "ADC calibration with linearaity calibration"] - CFGR: - EXTSEL: - TIM4_CC4: [5, "Timer 4 CC4 event"] - TIM8_TRGO: [7, "Timer 8 TRGO event"] - TIM8_TRGO2: [8, "Timer 8 TRGO2 event"] - TIM4_TRGO: [12, "Timer 4 TRGO event"] - HRTIM1_ADCTRG1: [16, "HRTIM1_ADCTRG1 event"] - HRTIM1_ADCTRG3: [17, "HRTIM1_ADCTRG3 event"] - LPTIM1_OUT: [18, "LPTIM1_OUT event"] - LPTIM2_OUT: [19, "LPTIM2_OUT event"] - LPTIM3_OUT: [20, "LPTIM3_OUT event"] - JQDIS: - Enabled: [0, "Injected Queue enabled"] - Disabled: [1, "Injected Queue disabled"] - DMNGT: - DR: [0, "Store output data in DR only"] - DMA_OneShot: [1, "DMA One Shot Mode selected"] - DFSDM: [2, "DFSDM mode selected"] - DMA_Circular: [3, "DMA Circular Mode selected"] - CFGR2: - LSHIFT: [0, 15] - OSVR: [0, 1023] - "RSHIFT?": - Disabled: [0, "Right-shifting disabled"] - Enabled: [1, "Data is right-shifted 1-bit"] - ROVSM: - Continued: [0, "Oversampling is temporary stopped and continued after injection sequence"] - Resumed: [1, "Oversampling is aborted and resumed from start after injection sequence"] - TROVS: - Automatic: [0, "All oversampled conversions for a channel are run following a trigger"] - Triggered: [1, "Each oversampled conversion for a channel needs a new trigger"] - OVSS: [0, 11] - JOVSE: - Disabled: [0, "Injected oversampling disabled"] - Enabled: [1, "Injected oversampling enabled"] - ROVSE: - Disabled: [0, "Regular oversampling disabled"] - Enabled: [1, "Regular oversampling enabled"] - "SMPR?": - "SMP*": - Cycles1_5: [0, "1.5 ADC clock cycles"] - Cycles2_5: [1, "2.5 ADC clock cycles"] - Cycles8_5: [2, "8.5 ADC clock cycles"] - Cycles16_5: [3, "16.5 ADC clock cycles"] - Cycles32_5: [4, "32.5 ADC clock cycles"] - Cycles64_5: [5, "64.5 ADC clock cycles"] - Cycles387_5: [6, "387.5 ADC clock cycles"] - Cycles810_5: [7, "810.5 ADC clock cycles"] - "HTR?": - "HTR?": [0, 0x03FF_FFFF] - "LTR?": - "LTR?": [0, 0x03FF_FFFF] - JSQR: - JEXTSEL: - TIM4_TRGO: [5, "Timer 4 TRGO event"] - TIM8_CC4: [7, "Timer 8 CC4 event"] - TIM8_TRGO: [9, "Timer 8 TRGO event"] - TIM8_TRGO2: [10, "Timer 8 TRGO2 event"] - HRTIM1_ADCTRG2: [16, "HRTIM1_ADCTRG2 event"] - HRTIM1_ADCTRG4: [17, "HRTIM1_ADCTRG4 event"] - LPTIM1_OUT: [18, "LPTIM1_OUT event"] - LPTIM2_OUT: [19, "LPTIM2_OUT event"] - LPTIM3_OUT: [20, "LPTIM3_OUT event"] - "OFR?": - SSATE: - Disabled: [0, "Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)"] - Enabled: [1, "Offset is subtracted and result is saturated to maintain result size"] - "OFFSET?_CH": [0, 31] - "OFFSET?": [0, 0x3FFFFFF] - PCSEL: - "PCSEL*": - NotPreselected: [0, "Input channel x is not pre-selected"] - Preselected: [1, "Pre-select input channel x"] - CALFACT: - CALFACT_?: [0, 2047] - CALFACT2: - LINCALFACT: [0, 0x3FFFFFFF] diff --git a/peripherals/aes/aes_l0.yaml b/peripherals/aes/aes_l0.yaml deleted file mode 100644 index 0f34f3969..000000000 --- a/peripherals/aes/aes_l0.yaml +++ /dev/null @@ -1,55 +0,0 @@ -AES: - CR: - DMAOUTEN: - Disabled: [0, "Disable DMA Output"] - Enabled: [1, "Enabled DMA Output"] - DMAINEN: - Disabled: [0, "Disable DMA Input"] - Enabled: [1, "Enable DMA Input"] - ERRIE: - Disabled: [0, "Disable (mask) error interrupt"] - Enabled: [1, "Enable error interrupt"] - CCFIE: - Disabled: [0, "Disable (mask) CCF interrupt"] - Enabled: [1, "Enable CCF interrupt"] - ERRC: - _write: - Clear: [1, "Clear RDERR and WRERR flags"] - CCFC: - _write: - Clear: [1, "Clear computation complete flag"] - CHMOD: - ECB: [0, "Electronic codebook (ECB)"] - CBC: [1, "Cipher-Block Chaining (CBC)"] - CTR: [2, "Counter Mode (CTR)"] - MODE: - Mode1: [0, "Mode 1: encryption"] - Mode2: [1, "Mode 2: key derivation (or key preparation for ECB/CBC decryption)"] - Mode3: [2, "Mode 3: decryption"] - Mode4: [3, "Mode 4: key derivation then single decryption"] - DATATYPE: - None: [0, "Word"] - HalfWord: [1, "Half-word (16-bit)"] - Byte: [2, "Byte (8-bit)"] - Bit: [3, "Bit"] - EN: - Disabled: [0, "Disable AES"] - Enabled: [1, "Enable AES"] - SR: - WRERR: - NoError: [0, "Write error not detected"] - Error: [1, "Write error detected"] - RDERR: - NoError: [0, "Read error not detected"] - Error: [1, "Read error detected"] - CCF: - Complete: [0, "Computation complete"] - NotComplete: [1, "Computation not complete"] - DINR: - DIN: [0, 0xFFFFFFFF] - DOUTR: - DOUT: [0, 0xFFFFFFFF] - "KEYR[0123]": - "KEY*": [0, 0xFFFFFFFF] - "IVR[0123]": - "IV*": [0, 0xFFFFFFFF] diff --git a/peripherals/axi/axi_v1.yaml b/peripherals/axi/axi_v1.yaml deleted file mode 100644 index c13398fd3..000000000 --- a/peripherals/axi/axi_v1.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# Advanced eXtensible Interface (AXI) management on H7 - -AXI: - INI?_FN_MOD: - WRITE_ISS_OVERRIDE: - Normal: [0, "Normal ASIB write issuing capability"] - Force1: [1, "Force ASIB write issuing capability to 1"] - READ_ISS_OVERRIDE: - Normal: [0, "Normal ASIB read issuing capability"] - Force1: [1, "Force ASIB read issuing capability to 1"] - INI?_READ_QOS: - AR_QOS: [0, 0xF] - INI?_WRITE_QOS: - AW_QOS: [0, 0xF] diff --git a/peripherals/bkp/bkp.yaml b/peripherals/bkp/bkp.yaml deleted file mode 100644 index cb9ac5fdb..000000000 --- a/peripherals/bkp/bkp.yaml +++ /dev/null @@ -1,27 +0,0 @@ -BKP: - RTCCR: - ASOS: - Alarm: [0, "RTC Alarm pulse output selected"] - Second: [1, "RTC Second pulse output selected"] - ASOE: - Disabled: [0, "Disabled"] - Enabled: [1, "Setting this bit outputs either the RTC Alarm pulse signal or the Second pulse signal on the TAMPER pin depending on the ASOS bit"] - CAL: [0, 121] - CR: - TPAL: - High: [0, "A high level on the TAMPER pin resets all data backup registers (if TPE bit is set)"] - Low: [1, "A low level on the TAMPER pin resets all data backup registers (if TPE bit is set)"] - TPE: - General: [0, "The TAMPER pin is free for general purpose I/O"] - Alternate: [1, "Tamper alternate I/O function is activated"] - CSR: - TPIE: - Disabled: [0, "Tamper interrupt disabled"] - Enabled: [1, "Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register"] - CTI: - _write: - Clear: [1, "Clear the Tamper interrupt and the TIF Tamper interrupt flag"] - CTE: - _write: - Reset: [1, "Reset the TEF Tamper event flag (and the Tamper detector)"] - diff --git a/peripherals/can/can.yaml b/peripherals/can/can.yaml deleted file mode 100644 index 65cbfb5e3..000000000 --- a/peripherals/can/can.yaml +++ /dev/null @@ -1,136 +0,0 @@ -"CAN,CAN?": - #MCR: - - #MSR: - - #TSR: - - RF?R: - RFOM?: - _write: - Release: [1, "Set by software to release the output mailbox of the FIFO"] - FOVR?: - _read: - NoOverrun: [0, "No FIFO x overrun"] - Overrun: [1, "FIFO x overrun"] - _write: - Clear: [1, "Clear flag"] - FULL?: - _read: - NotFull: [0, "FIFO x is not full"] - Full: [1, "FIFO x is full"] - _write: - Clear: [1, "Clear flag"] - #FMP?: - - IER: - SLKIE: - Disabled: [0, "No interrupt when SLAKI bit is set"] - Enabled: [1, "Interrupt generated when SLAKI bit is set"] - WKUIE: - Disabled: [0, "No interrupt when WKUI is set"] - Enabled: [1, "Interrupt generated when WKUI bit is set"] - ERRIE: - Disabled: [0, "No interrupt will be generated when an error condition is pending in the CAN_ESR"] - Enabled: [1, "An interrupt will be generation when an error condition is pending in the CAN_ESR"] - LECIE: - Disabled: [0, "ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error detection"] - Enabled: [1, "ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection"] - BOFIE: - Disabled: [0, "ERRI bit will not be set when BOFF is set"] - Enabled: [1, "ERRI bit will be set when BOFF is set"] - EPVIE: - Disabled: [0, "ERRI bit will not be set when EPVF is set"] - Enabled: [1, "ERRI bit will be set when EPVF is set"] - EWGIE: - Disabled: [0, "ERRI bit will not be set when EWGF is set"] - Enabled: [1, "ERRI bit will be set when EWGF is set"] - FOVIE1: - Disabled: [0, "No interrupt when FOVR is set"] - Enabled: [1, "Interrupt generation when FOVR is set"] - FFIE1: - Disabled: [0, "No interrupt when FULL bit is set"] - Enabled: [1, "Interrupt generated when FULL bit is set"] - FMPIE1: - Disabled: [0, "No interrupt generated when state of FMP[1:0] bits are not 00b"] - Enabled: [1, "Interrupt generated when state of FMP[1:0] bits are not 00b"] - FOVIE0: - Disabled: [0, "No interrupt when FOVR bit is set"] - Enabled: [1, "Interrupt generated when FOVR bit is set"] - FFIE0: - Disabled: [0, "No interrupt when FULL bit is set"] - Enabled: [1, "Interrupt generated when FULL bit is set"] - FMPIE0: - Disabled: [0, "No interrupt generated when state of FMP[1:0] bits are not 00"] - Enabled: [1, "Interrupt generated when state of FMP[1:0] bits are not 00b"] - TMEIE: - Disabled: [0, "No interrupt when RQCPx bit is set"] - Enabled: [1, "Interrupt generated when RQCPx bit is set"] - - ESR: - #REC: - #TEC: - LEC: - NoError: [0, "No Error"] - Stuff: [1, "Stuff Error"] - Form: [2, "Form Error"] - Ack: [3, "Acknowledgment Error"] - BitRecessive: [4, "Bit recessive Error"] - BitDominant: [5, "Bit dominant Error"] - Crc: [6, "CRC Error"] - Custom: [7, "Set by software"] - #BOFF: - #EPVF: - #EWGF: - - BTR: - SILM: - Normal: [0, "Normal operation"] - Silent: [1, "Silent Mode"] - LBKM: - Disabled: [0, "Loop Back Mode disabled"] - Enabled: [1, "Loop Back Mode enabled"] - #SJW: - #TS2: - #TS1: - #BRP: - - TI?R: - #STID: - #EXID: - IDE: - Standard: [0, "Standard identifier"] - Extended: [1, "Extended identifier"] - RTR: - Data: [0, "Data frame"] - Remote: [1, "Remote frame"] - #TXRQ: - - TDT?R: - #TIME: - #TGT: - DLC: [0, 8] - - #TDL?R: - - #TDH?R: - - RI?R: - #STID: - #EXID: - IDE: - Standard: [0, "Standard identifier"] - Extended: [1, "Extended identifier"] - RTR: - Data: [0, "Data frame"] - Remote: [1, "Remote frame"] - - RDT?R: - #TIME: - #FMI: - DLC: [0, 8] - - #RDL?R: - - #RDH?R: - diff --git a/peripherals/comp/comp_f0.yaml b/peripherals/comp/comp_f0.yaml deleted file mode 100644 index c5393e64d..000000000 --- a/peripherals/comp/comp_f0.yaml +++ /dev/null @@ -1,86 +0,0 @@ -COMP: - CSR: - COMP1EN: - Disabled: [0, "Comparator 1 disabled"] - Enabled: [1, "Comparator 1 enabled"] - COMP1SW1: - Open: [0, "Switch open"] - Closed: [1, "Switch closed"] - COMP1MODE: - HighSpeed: [0, "High speed / full power"] - MediumSpeed: [1, "Medium speed / medium power"] - LowSpeed: [2, "Low speed / low power"] - VeryLowSpeed: [3, "Very-low speed / ultra-low power"] - COMP1INSEL: - OneQuarterVRef: [0, "1/4 of VRefint"] - OneHalfVRef: [1, "1/2 of VRefint"] - ThreeQuarterVRef: [2, "3/4 of VRefint"] - VRef: [3, "VRefint"] - Comp1_INM4: [4, "COMP1_INM4 (PA4 with DAC_OUT1 if enabled)"] - Comp1_INM5: [5, "COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)"] - Comp1_INM6: [6, "COMP1_INM6 (PA0)"] - COMP1OUTSEL: - NoSelection: [0, "No selection"] - Timer1BreakInput: [1, "Timer 1 break input"] - Timer1InputCapture1: [2, "Timer 1 Input capture 1"] - Timer1OCRefClearInput: [3, "Timer 1 OCrefclear input"] - Timer2InputCapture4: [4, "Timer 2 input capture 4"] - Timer2OCRefClearInput: [5, "Timer 2 OCrefclear input"] - Timer3InputCapture1: [6, "Timer 3 input capture 1"] - Timer3OCRefClearInput: [7, "Timer 3 OCrefclear input"] - COMP1POL: - NotInverted: [0, "Output is not inverted"] - Inverted: [1, "Output is inverted"] - COMP1HYST: - NoHysteresis: [0, "No hysteresis"] - LowHysteresis: [1, "Low hysteresis"] - MediumHysteresis: [2, "Medium hysteresis"] - HighHysteresis: [3, "High hysteresis"] - COMP1OUT: - Low: [0, "Non-inverting input below inverting input"] - High: [1, "Non-inverting input above inverting input"] - COMP1LOCK: - Unlocked: [0, "Comparator 1 CSR bits (CSR[15:0]) are read-write"] - Locked: [1, "Comparator 1 CSR bits (CSR[15:0]) are read-only"] - COMP2EN: - Disabled: [0, "Comparator 2 disabled"] - Enabled: [1, "Comparator 2 enabled"] - COMP2MODE: - HighSpeed: [0, "High speed / full power"] - MediumSpeed: [1, "Medium speed / medium power"] - LowSpeed: [2, "Low speed / low power"] - VeryLowSpeed: [3, "Very-low speed / ultra-low power"] - COMP2INSEL: - OneQuarterVRef: [0, "1/4 of VRefint"] - OneHalfVRef: [1, "1/2 of VRefint"] - ThreeQuarterVRef: [2, "3/4 of VRefint"] - VRef: [3, "VRefint"] - Comp2_INM4: [4, "COMP1_INM4 (PA4 with DAC_OUT1 if enabled)"] - Comp2_INM5: [5, "COMP1_INM5 (PA5 with DAC_OUT2 if present and enabled)"] - Comp2_INM6: [6, "COMP1_INM6 (PA2)"] - WNDWEN: - Disabled: [0, "Window mode disabled"] - Enabled: [1, "Window mode enabled"] - COMP2OUTSEL: - NoSelection: [0, "No selection"] - Timer1BreakInput: [1, "Timer 1 break input"] - Timer1InputCapture1: [2, "Timer 1 Input capture 1"] - Timer1OCRefClearInput: [3, "Timer 1 OCrefclear input"] - Timer2InputCapture4: [4, "Timer 2 input capture 4"] - Timer2OCRefClearInput: [5, "Timer 2 OCrefclear input"] - Timer3InputCapture1: [6, "Timer 3 input capture 1"] - Timer3OCRefClearInput: [7, "Timer 3 OCrefclear input"] - COMP2POL: - NotInverted: [0, "Output is not inverted"] - Inverted: [1, "Output is inverted"] - COMP2HYST: - NoHysteresis: [0, "No hysteresis"] - LowHysteresis: [1, "Low hysteresis"] - MediumHysteresis: [2, "Medium hysteresis"] - HighHysteresis: [3, "High hysteresis"] - COMP2OUT: - Low: [0, "Non-inverting input below inverting input"] - High: [1, "Non-inverting input above inverting input"] - COMP2LOCK: - Unlocked: [0, "Comparator 2 CSR bits (CSR[31:16]) are read-write"] - Locked: [1, "Comparator 2 CSR bits (CSR[31:16]) are read-only"] diff --git a/peripherals/comp/comp_f3.yaml b/peripherals/comp/comp_f3.yaml deleted file mode 100644 index a64496ad9..000000000 --- a/peripherals/comp/comp_f3.yaml +++ /dev/null @@ -1,83 +0,0 @@ -COMP: - COMP[246]_CSR: - COMP[246]EN: - Disabled: [0, "Comparator disabled"] - Enabled: [1, "Comparator enabled"] - COMP[246]POL: - NotInverted: [0, "Output is not inverted"] - Inverted: [1, "Output is inverted"] - COMP[246]OUT: - Low: [0, "Non-inverting input below inverting input"] - High: [1, "Non-inverting input above inverting input"] - COMP[246]LOCK: - Unlocked: [0, "Comparator CSR bits are read-write"] - Locked: [1, "Comparator CSR bits are read-only"] - - COMP2_CSR: - COMP2INMSEL: - OneQuarterVRef: [0, "1/4 of VRefint"] - OneHalfVRef: [1, "1/2 of VRefint"] - ThreeQuarterVRef: [2, "3/4 of VRefint"] - VRef: [3, "VRefint"] - PA4_DAC1_CH1: [4, "PA4 or DAC1_CH1 output if enabled"] - DAC1_CH2: [5, "DAC1_CH2"] - PA2: [6, "PA2"] - COMP2OUTSEL: - NoSelection: [0, "No selection"] - Timer1BreakInput: [1, "Timer 1 break input"] - Timer1BreakInput2: [2, "Timer 1 break input 2"] - Timer1OCRefClearInput: [6, "Timer 1 OCREF_CLR input"] - Timer1InputCapture1: [7, "Timer 1 input capture 1"] - Timer2InputCapture4: [8, "Timer 2 input capture 4"] - Timer2OCRefClearInput: [9, "Timer 2 OCREF_CLR input"] - Timer3InputCapture1: [10, "Timer 3 input capture 1"] - Timer3OCRefClearInput: [11, "Timer 3 OCREF_CLR input"] - COMP2_BLANKING: - NoBlanking: [0, "No blanking"] - TIM1OC5: [1, "TIM1 OC5 selected as blanking source"] - TIM2OC3: [2, "TIM2 OC3 selected as blanking source"] - TIM3OC3: [3, "TIM3 OC3 selected as blanking source"] - - COMP4_CSR: - COMP4INMSEL: - OneQuarterVRef: [0, "1/4 of VRefint"] - OneHalfVRef: [1, "1/2 of VRefint"] - ThreeQuarterVRef: [2, "3/4 of VRefint"] - VRef: [3, "VRefint"] - PA4_DAC1_CH1: [4, "PA4 or DAC1_CH1 output if enabled"] - DAC1_CH2: [5, "DAC1_CH2"] - PB2: [7, "PB2"] - COMP4OUTSEL: - NoSelection: [0, "No selection"] - Timer1BreakInput: [1, "Timer 1 break input"] - Timer1BreakInput2: [2, "Timer 1 break input 2"] - Timer3InputCapture3: [6, "Timer 3 input capture 3"] - Timer15InputCapture2: [8, "Timer 15 input capture 2"] - Timer15OCRefClearInput: [10, "Timer 15 OCREF_CLR input"] - Timer3OCRefClearInput: [11, "Timer 3 OCREF_CLR input"] - COMP4_BLANKING: - NoBlanking: [0, "No blanking"] - TIM3OC4: [1, "TIM3 OC4 selected as blanking source"] - TIM15OC1: [3, "TIM15 OC1 selected as blanking source"] - - COMP6_CSR: - COMP6INMSEL: - OneQuarterVRef: [0, "1/4 of VRefint"] - OneHalfVRef: [1, "1/2 of VRefint"] - ThreeQuarterVRef: [2, "3/4 of VRefint"] - VRef: [3, "VRefint"] - PA4_DAC1_CH1: [4, "PA4 or DAC1_CH1 output if enabled"] - DAC1_CH2: [5, "DAC1_CH2"] - PB15: [7, "PB15"] - COMP6OUTSEL: - NoSelection: [0, "No selection"] - Timer1BreakInput: [1, "Timer 1 break input"] - Timer1BreakInput2: [2, "Timer 1 break input 2"] - Timer2InputCapture2: [6, "Timer 2 input capture 2"] - Timer2OCRefClearInput: [8, "Timer 2 OCREF_CLR input"] - Timer16OCRefClearInput: [9, "Timer 16 OCREF_CLR input"] - Timer16InputCapture1: [10, "Timer 16 input capture 1"] - COMP6_BLANKING: - NoBlanking: [0, "No blanking"] - TIM2OC4: [3, "TIM2 OC4 selected as blanking source"] - TIM15OC2: [4, "TIM15 OC2 selected as blanking source"] diff --git a/peripherals/crc/crc_advanced.yaml b/peripherals/crc/crc_advanced.yaml deleted file mode 100644 index 25813b06e..000000000 --- a/peripherals/crc/crc_advanced.yaml +++ /dev/null @@ -1,48 +0,0 @@ -# CRC peripheral with reversal features. -# Documented from STM32F0xx reference manual. - -_include: - - ./crc_basic.yaml - -CRC: - _add: - DR8: - description: Data register - byte sized - addressOffset: 0x0 - size: 0x8 - access: read-write - resetValue: 0xFF - alternateRegister: DR - fields: - DR8: - description: Data register bits - bitOffset: 0 - bitWidth: 8 - DR16: - description: Data register - half-word sized - addressOffset: 0x0 - size: 0x10 - access: read-write - resetValue: 0xFFFF - alternateRegister: DR - fields: - DR16: - description: Data register bits - bitOffset: 0 - bitWidth: 16 - - DR8: - DR8: [0, 255] - DR16: - DR16: [0, 65535] - CR: - REV_IN: - Normal: [0, "Bit order not affected"] - Byte: [1, "Bit reversal done by byte"] - HalfWord: [2, "Bit reversal done by half-word"] - Word: [3, "Bit reversal done by word"] - REV_OUT: - Normal: [0, "Bit order not affected"] - Reversed: [1, "Bit reversed output"] - INIT: - INIT: [0, 4294967295] diff --git a/peripherals/crc/crc_basic.yaml b/peripherals/crc/crc_basic.yaml deleted file mode 100644 index c92d53a14..000000000 --- a/peripherals/crc/crc_basic.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# CRC peripheral. Details specifically from RM0090 but widely applicable. -# This covers the basic features - DR, IDR, and CR. For the more sophisticated -# CRC available on some STM32s, use crc_advanced.yaml. - -CRC: - DR: - DR: [0, 4294967295] - IDR: - IDR: [0, 255] - CR: - RESET: - _write: - Reset: [1, "Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF"] diff --git a/peripherals/crc/crc_pol.yaml b/peripherals/crc/crc_pol.yaml deleted file mode 100644 index 6e4200266..000000000 --- a/peripherals/crc/crc_pol.yaml +++ /dev/null @@ -1,3 +0,0 @@ -CRC: - POL: - POL: [0, 0xFFFFFFFF] diff --git a/peripherals/crc/crc_with_polysize.yaml b/peripherals/crc/crc_with_polysize.yaml deleted file mode 100644 index b7bcacf10..000000000 --- a/peripherals/crc/crc_with_polysize.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# CRC peripheral with polysize feature - -CRC: - CR: - POLYSIZE: - Polysize32: [0, "32-bit polynomial"] - Polysize16: [1, "16-bit polynomial"] - Polysize8: [2, "8-bit polynomial"] - Polysize7: [3, "7-bit polynomial"] diff --git a/peripherals/dac/dac_common_1ch.yaml b/peripherals/dac/dac_common_1ch.yaml deleted file mode 100644 index 3f19782b7..000000000 --- a/peripherals/dac/dac_common_1ch.yaml +++ /dev/null @@ -1,35 +0,0 @@ -# The DAC is widely used. This is the common subset on all devices, -# for just a single channel. - -DAC,DAC?: - CR: - EN?: - Disabled: [0, "DAC channel X disabled"] - Enabled: [1, "DAC channel X enabled"] - BOFF?: - Enabled: [0, "DAC channel X output buffer enabled"] - Disabled: [1, "DAC channel X output buffer disabled"] - TEN?: - Disabled: [0, "DAC channel X trigger disabled"] - Enabled: [1, "DAC channel X trigger enabled"] - TSEL1: - TIM6_TRGO: [0, "Timer 6 TRGO event"] - TIM3_TRGO: [1, "Timer 3 TRGO event"] - TIM7_TRGO: [2, "Timer 7 TRGO event"] - TIM15_TRGO: [3, "Timer 15 TRGO event"] - TIM2_TRGO: [4, "Timer 2 TRGO event"] - EXTI9: [6, "EXTI line9"] - SOFTWARE: [7, "Software trigger"] - DMAEN?: - Disabled: [0, "DAC channel X DMA mode disabled"] - Enabled: [1, "DAC channel X DMA mode enabled"] - SWTRIGR: - SWTRIG?: - Disabled: [0, "DAC channel X software trigger disabled"] - Enabled: [1, "DAC channel X software trigger enabled"] - DHR12R?: - DACC?DHR: [0, 4095] - DHR12L?: - DACC?DHR: [0, 4095] - DHR8R?: - DACC?DHR: [0, 255] diff --git a/peripherals/dac/dac_common_2ch.yaml b/peripherals/dac/dac_common_2ch.yaml deleted file mode 100644 index f0a9b430b..000000000 --- a/peripherals/dac/dac_common_2ch.yaml +++ /dev/null @@ -1,16 +0,0 @@ -# The DAC is widely used. This is the common subset for two-channel devices. - -_include: - - "dac_common_1ch.yaml" - -DAC,DAC?: - CR: - TSEL2: - TIM6_TRGO: [0, "Timer 6 TRGO event"] - TIM8_TRGO: [1, "Timer 8 TRGO event"] - TIM7_TRGO: [2, "Timer 7 TRGO event"] - TIM5_TRGO: [3, "Timer 5 TRGO event"] - TIM2_TRGO: [4, "Timer 2 TRGO event"] - TIM4_TRGO: [5, "Timer 4 TRGO event"] - EXTI9: [6, "EXTI line9"] - SOFTWARE: [7, "Software trigger"] diff --git a/peripherals/dac/dac_dmaudr.yaml b/peripherals/dac/dac_dmaudr.yaml deleted file mode 100644 index fa6db6d55..000000000 --- a/peripherals/dac/dac_dmaudr.yaml +++ /dev/null @@ -1,10 +0,0 @@ - -DAC,DAC?: - CR: - DMAUDRIE?: - Disabled: [0, "DAC channel X DMA Underrun Interrupt disabled"] - Enabled: [1, "DAC channel X DMA Underrun Interrupt enabled"] - SR: - DMAUDR?: - NoUnderrun: [0, "No DMA underrun error condition occurred for DAC channel X"] - Underrun: [1, "DMA underrun error condition occurred for DAC channel X"] diff --git a/peripherals/dac/dac_wavegen.yaml b/peripherals/dac/dac_wavegen.yaml deleted file mode 100644 index 8cc291ce0..000000000 --- a/peripherals/dac/dac_wavegen.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# These are the extra DAC features on fancier devices. - -DAC,DAC?: - CR: - WAVE1: - Disabled: [0, "Wave generation disabled"] - Noise: [1, "Noise wave generation enabled"] - Triangle: [2, "Triangle wave generation enabled"] - MAMP1: [0, 15] - WAVE2: - Disabled: [0, "Wave generation disabled"] - Noise: [1, "Noise wave generation enabled"] - Triangle: [2, "Triangle wave generation enabled"] - MAMP2: [0, 15] diff --git a/peripherals/dbg/dbg_l0.yaml b/peripherals/dbg/dbg_l0.yaml deleted file mode 100644 index 91ba0080a..000000000 --- a/peripherals/dbg/dbg_l0.yaml +++ /dev/null @@ -1,41 +0,0 @@ -# Debug registers for L0 - -DBG: - IDCODE: - _read: - REV_ID: [0, 65535] - _read: - DEV_ID: [0, 4095] - CR: - DBG_STANDBY: - Disabled: [0, "Debug Standby Mode Disabled"] - Enabled: [1, "Debug Standby Mode Enabled"] - DBG_STOP: - Disabled: [0, "Debug Stop Mode Disabled"] - Enabled: [1, "Debug Stop Mode Enabled"] - DBG_SLEEP: - Disabled: [0, "Debug Sleep Mode Disabled"] - Enabled: [1, "Debug Sleep Mode Enabled"] - APB1_FZ: - DBG_LPTIMER_STOP: - Continue: [0, "LPTIM1 counter clock is fed even if the core is halted"] - Stop: [1, "LPTIM1 counter clock is stopped when the core is halted"] - "DBG_I2C*_STOP": - NormalMode: [0, "Same behavior as in normal mode"] - SMBusTimeoutFrozen: [1, "I2C3 SMBUS timeout is frozen"] - DBG_IWDG_STOP: - Continue: [0, "The independent watchdog counter clock continues even if the core is halted"] - Stop: [1, "The independent watchdog counter clock is stopped when the core is halted"] - DBG_WWDG_STOP: - Continue: [0, "The window watchdog counter clock continues even if the core is halted"] - Stop: [1, "The window watchdog counter clock is stopped when the core is halted"] - DBG_RTC_STOP: - Continue: [0, "The clock of the RTC counter is fed even if the core is halted"] - Stop: [1, "The clock of the RTC counter is stopped when the core is halted"] - "DBG_TIM*_STOP": - Continue: [0, "The counter clock of TIMx is fed even if the core is halted"] - Stop: [1, "The counter clock of TIMx is stopped when the core is halted"] - APB2_FZ: - "DBG_TIM*_STOP": - Continue: [0, "The counter clock of TIMx is fed even if the core is halted"] - Stop: [1, "The counter clock of TIMx is stopped when the core is halted"] \ No newline at end of file diff --git a/peripherals/dma/bdma.yaml b/peripherals/dma/bdma.yaml deleted file mode 100644 index 06bbea45c..000000000 --- a/peripherals/dma/bdma.yaml +++ /dev/null @@ -1,67 +0,0 @@ -# Basic DMA as found on H7, .. - -"BDMA*": - "ISR": - "TCIF?": - NotComplete: [0, "No transfer complete event on channel x"] - Complete: [1, "A transfer complete event occurred on channel x"] - "HTIF?": - NotHalf: [0, "No half transfer event on channel x"] - Half: [1, "A half transfer event occurred on channel x"] - "TEIF?": - NoError: [0, "No transfer error on channel x"] - Error: [1, "A transfer error occurred on channel x"] - "GIF?": - NoEvent: [0, "No TE, HT or TC event on channel x"] - Event: [1, "A TE, HT or TC event occurred on channel x"] - "IFCR": - "CTCIF?": - Clear: [1, "Clear the corresponding TCIFx flag"] - "CHTIF?": - Clear: [1, "Clear the corresponding HTIFx flag"] - "CTEIF?": - Clear: [1, "Clear the corresponding TEIFx flag"] - "CGIF?": - Clear: [1, "Clear the corresponding CGIFx flag"] - "CCR?": - CT: - Memory0: [0, "The current target memory is Memory 0"] - Memory1: [1, "The current target memory is Memory 1"] - DBM: - Disabled: [0, "No buffer switching at the end of transfer"] - Enabled: [1, "Memory target switched at the end of the DMA transfer"] - MEM2MEM: - Disabled: [0, "Memory-to-memory mode disabled"] - Enabled: [1, "Memory-to-memory mode enabled"] - PL: - Low: [0, "Low"] - Medium: [1, "Medium"] - High: [2, "High"] - VeryHigh: [3, "Very high"] - "[MP]SIZE": - Bits8: [0, "Byte (8-bit)"] - Bits16: [1, "Half-word (16-bit)"] - Bits32: [2, "Word (32-bit)"] - "[MP]INC": - Fixed: [0, "Address pointer is fixed"] - Incremented: [1, "Address pointer is incremented after each data transfer"] - CIRC: - Disabled: [0, "Circular mode disabled"] - Enabled: [1, "Circular mode enabled"] - DIR: - PeripheralToMemory: [0, "Peripheral-to-memory"] - MemoryToPeripheral: [1, "Memory-to-peripheral"] - TCIE: - Disabled: [0, "TC interrupt disabled"] - Enabled: [1, "TC interrupt enabled"] - HTIE: - Disabled: [0, "HT interrupt disabled"] - Enabled: [1, "HT interrupt enabled"] - TEIE: - Disabled: [0, "TE interrupt disabled"] - Enabled: [1, "TE interrupt enabled"] - EN: - Disabled: [0, "Channel disabled"] - Enabled: [1, "Channel enabled"] - "CNDTR?": - NDT: [0, 65535] diff --git a/peripherals/dma/dma2d_common.yaml b/peripherals/dma/dma2d_common.yaml deleted file mode 100644 index 7606c8004..000000000 --- a/peripherals/dma/dma2d_common.yaml +++ /dev/null @@ -1,79 +0,0 @@ -# "Chrom-Art Accelerator" 2D DMA engine -# Common fields - -"DMA2D*": - CR: - MODE: - MemoryToMemory: [0, "Memory-to-memory (FG fetch only)"] - MemoryToMemoryPFC: [1, "Memory-to-memory with PFC (FG fetch only with FG PFC active)"] - MemoryToMemoryPFCBlending: [2, "Memory-to-memory with blending (FG and BG fetch with PFC and blending)"] - RegisterToMemory: [3, "Register-to-memory"] - CEIE: - Disabled: [0, "CE interrupt disabled"] - Enabled: [1, "CE interrupt enabled"] - CTCIE: - Disabled: [0, "CTC interrupt disabled"] - Enabled: [1, "CTC interrupt enabled"] - CAEIE: - Disabled: [0, "CAE interrupt disabled"] - Enabled: [1, "CAE interrupt enabled"] - TWIE: - Disabled: [0, "TW interrupt disabled"] - Enabled: [1, "TW interrupt enabled"] - TCIE: - Disabled: [0, "TC interrupt disabled"] - Enabled: [1, "TC interrupt enabled"] - TEIE: - Disabled: [0, "TE interrupt disabled"] - Enabled: [1, "TE interrupt enabled"] - ABORT: - AbortRequest: [1, "Transfer abort requested"] - SUSP: - NotSuspended: [0, "Transfer not suspended"] - Suspended: [1, "Transfer suspended"] - START: - Start: [1, "Launch the DMA2D"] - IFCR: - CCEIF: - Clear: [1, "Clear the CEIF flag in the ISR register"] - CCTCIF: - Clear: [1, "Clear the CTCIF flag in the ISR register"] - CAECIF: - Clear: [1, "Clear the CAEIF flag in the ISR register"] - CTWIF: - Clear: [1, "Clear the TWIF flag in the ISR register"] - CTCIF: - Clear: [1, "Clear the TCIF flag in the ISR register"] - CTEIF: - Clear: [1, "Clear the TEIF flag in the ISR register"] - "[FB]GPFCCR": - ALPHA: [0, 255] - AM: - NoModify: [0, "No modification of alpha channel"] - Replace: [1, "Replace with value in ALPHA[7:0]"] - Multiply: [2, "Multiply with value in ALPHA[7:0]"] - CS: [0, 255] - START: - Start: [1, "Start the automatic loading of the CLUT"] - CCM: - ARGB8888: [0, "CLUT color format ARGB8888"] - RGB888: [1, "CLUT color format RGB888"] - "[FB]GCOLR": - RED: [0, 255] - GREEN: [0, 255] - BLUE: [0, 255] - OPFCCR: - CM: - ARGB8888: [0, "ARGB8888"] - RGB888: [1, "RGB888"] - RGB565: [2, "RGB565"] - ARGB1555: [3, "ARGB1555"] - ARGB4444: [4, "ARGB4444"] - NLR: - PL: [0, 16383] - NL: [0, 65535] - AMTCR: - DT: [0, 255] - EN: - Disabled: [0, "Disabled AHB/AXI dead-time functionality"] - Enabled: [1, "Enabled AHB/AXI dead-time functionality"] diff --git a/peripherals/dma/dma2d_v1.yaml b/peripherals/dma/dma2d_v1.yaml deleted file mode 100644 index fb75288d8..000000000 --- a/peripherals/dma/dma2d_v1.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# "Chrom-Art Accelerator" 2D DMA engine -# Version 1 found on F4 - -_include: - - dma2d_common.yaml - -"DMA2D*": - "[FB]GOR,OOR": - LO: [0, 16383] - "[FB]GPFCCR": - CM: - ARGB8888: [0, "Color mode ARGB8888"] - RGB888: [1, "Color mode RGB888"] - RGB565: [2, "Color mode RGB565"] - ARGB1555: [3, "Color mode ARGB1555"] - ARGB4444: [4, "Color mode ARGB4444"] - L8: [5, "Color mode L8"] - AL44: [6, "Color mode AL44"] - AL88: [7, "Color mode AL88"] - L4: [8, "Color mode L4"] - A8: [9, "Color mode A8"] - A4: [10, "Color mode A4"] diff --git a/peripherals/dma/dma2d_v2.yaml b/peripherals/dma/dma2d_v2.yaml deleted file mode 100644 index b0d6c09dd..000000000 --- a/peripherals/dma/dma2d_v2.yaml +++ /dev/null @@ -1,47 +0,0 @@ -# "Chrom-Art Accelerator" 2D DMA engine -# Version 2 found on H7 - -_include: - - dma2d_common.yaml - -"DMA2D*": - "[FB]GPFCCR,OPFCCR": - RBS: - Regular: [0, "No Red Blue Swap (RGB or ARGB)"] - Swap: [1, "Red Blue Swap (BGR or ABGR)"] - AI: - RegularAlpha: [0, "Regular alpha"] - InvertedAlpha: [1, "Inverted alpha"] - FGPFCCR: - CM: - ARGB8888: [0, "Color mode ARGB8888"] - RGB888: [1, "Color mode RGB888"] - RGB565: [2, "Color mode RGB565"] - ARGB1555: [3, "Color mode ARGB1555"] - ARGB4444: [4, "Color mode ARGB4444"] - L8: [5, "Color mode L8"] - AL44: [6, "Color mode AL44"] - AL88: [7, "Color mode AL88"] - L4: [8, "Color mode L4"] - A8: [9, "Color mode A8"] - A4: [10, "Color mode A4"] - YCbCr: [11, "Color mode YCbCr"] - BGPFCCR: - CM: - ARGB8888: [0, "Color mode ARGB8888"] - RGB888: [1, "Color mode RGB888"] - RGB565: [2, "Color mode RGB565"] - ARGB1555: [3, "Color mode ARGB1555"] - ARGB4444: [4, "Color mode ARGB4444"] - L8: [5, "Color mode L8"] - AL44: [6, "Color mode AL44"] - AL88: [7, "Color mode AL88"] - L4: [8, "Color mode L4"] - A8: [9, "Color mode A8"] - A4: [10, "Color mode A4"] - OPFCCR: - SB: - Regular: [0, "Regular byte order"] - SwapBytes: [1, "Bytes are swapped two by two"] - "[FB]GOR,OOR": - LO: [0, 65535] diff --git a/peripherals/dma/dma_v1.yaml b/peripherals/dma/dma_v1.yaml deleted file mode 100644 index 355261e74..000000000 --- a/peripherals/dma/dma_v1.yaml +++ /dev/null @@ -1,66 +0,0 @@ -# DMA as used on F0, F1, F3 family -# -# Please use `dma_v1_with_remapping.yaml` for devices that has DMA remapping -# functionality such as the L0 and L4 family. - -# DMA1 has 7 channels -# DMA2 has 5 channels -"DMA[12]": - ISR: - "TEIF*": - NoError: [0, "No transfer error"] - Error: [1, "A transfer error has occured"] - "HTIF*": - NotHalf: [0, "No half transfer event"] - Half: [1, "A half transfer event has occured"] - "TCIF*": - NotComplete: [0, "No transfer complete event"] - Complete: [1, "A transfer complete event has occured"] - "GIF*": - NoEvent: [0, "No transfer error, half event, complete event"] - Event: [1, "A transfer error, half event or complete event has occured"] - IFCR: - "CTEIF*": - Clear: [1, "Clears the TEIF flag in the ISR register"] - "CHTIF*": - Clear: [1, "Clears the HTIF flag in the ISR register"] - "CTCIF*": - Clear: [1, "Clears the TCIF flag in the ISR register"] - "CGIF*": - Clear: [1, "Clears the GIF, TEIF, HTIF, TCIF flags in the ISR register"] - "CCR*": - MEM2MEM: - Disabled: [0, "Memory to memory mode disabled"] - Enabled: [1, "Memory to memory mode enabled"] - PL: - Low: [0, "Low priority"] - Medium: [1, "Medium priority"] - High: [2, "High priority"] - VeryHigh: [3, "Very high priority"] - "[MP]SIZE": - Bits8: [0, "8-bit size"] # or Byte - Bits16: [1, "16-bit size"] # of HalfWord - Bits32: [2, "32-bit size"] # or Word - "[MP]INC": - Disabled: [0, "Increment mode disabled"] - Enabled: [1, "Increment mode enabled"] - CIRC: - Disabled: [0, "Circular buffer disabled"] - Enabled: [1, "Circular buffer enabled"] - DIR: - FromPeripheral: [0, "Read from peripheral"] - FromMemory: [1, "Read from memory"] - TEIE: - Disabled: [0, "Transfer Error interrupt disabled"] - Enabled: [1, "Transfer Error interrupt enabled"] - HTIE: - Disabled: [0, "Half Transfer interrupt disabled"] - Enabled: [1, "Half Transfer interrupt enabled"] - TCIE: - Disabled: [0, "Transfer Complete interrupt disabled"] - Enabled: [1, "Transfer Complete interrupt enabled"] - EN: - Disabled: [0, "Channel disabled"] - Enabled: [1, "Channel enabled"] - "CNDTR*": - NDT: [0, 65535] diff --git a/peripherals/dma/dma_v1_with_remapping.yaml b/peripherals/dma/dma_v1_with_remapping.yaml deleted file mode 100644 index 784232d78..000000000 --- a/peripherals/dma/dma_v1_with_remapping.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# DMA v1 with remapping functionnality -# Found on F0 and F4 family and on specific devices (stm32f09x). - -_include: - - ./dma_v1.yaml - -"DMA[12]": - CSELR: - "C*S": - NoMapping: [0, "Default mapping"] - Map1: [1, "Mapping 1"] - Map2: [2, "Mapping 2"] - Map3: [3, "Mapping 3"] - Map4: [4, "Mapping 4"] - Map5: [5, "Mapping 5"] - Map6: [6, "Mapping 6"] - Map7: [7, "Mapping 7"] - Map8: [8, "Mapping 8"] - Map9: [9, "Mapping 9"] - Map10: [10, "Mapping 10"] - Map11: [11, "Mapping 11"] - Map12: [12, "Mapping 12"] - Map13: [13, "Mapping 13"] - Map14: [14, "Mapping 14"] - Map15: [15, "Mapping 15"] diff --git a/peripherals/dma/dma_v2.yaml b/peripherals/dma/dma_v2.yaml deleted file mode 100644 index da9bb8753..000000000 --- a/peripherals/dma/dma_v2.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# DMA as used on F4 and F7 - -_include: - - dma_v3.yaml - -"DMA?": - "S?CR": - CHSEL: [0, 7] diff --git a/peripherals/dma/dma_v21.yaml b/peripherals/dma/dma_v21.yaml deleted file mode 100644 index 1ccab9467..000000000 --- a/peripherals/dma/dma_v21.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# DMA as used on F4 and F7 - -_include: - - dma_v3.yaml - -"DMA?": - "S?CR": - CHSEL: [0, 15] diff --git a/peripherals/dma/dma_v3.yaml b/peripherals/dma/dma_v3.yaml deleted file mode 100644 index 7fa5baa56..000000000 --- a/peripherals/dma/dma_v3.yaml +++ /dev/null @@ -1,103 +0,0 @@ -# DMA as used on H7 - -"DMA?": - "[LH]ISR": - "TCIF?": - NotComplete: [0, "No transfer complete event on stream x"] - Complete: [1, "A transfer complete event occurred on stream x"] - "HTIF?": - NotHalf: [0, "No half transfer event on stream x"] - Half: [1, "A half transfer event occurred on stream x"] - "TEIF?": - NoError: [0, "No transfer error on stream x"] - Error: [1, "A transfer error occurred on stream x"] - "DMEIF?": - NoError: [0, "No Direct Mode error on stream x"] - Error: [1, "A Direct Mode error occurred on stream x"] - "FEIF?": - NoError: [0, "No FIFO error event on stream x"] - Error: [1, "A FIFO error event occurred on stream x"] - "[LH]IFCR": - "CTCIF?": - Clear: [1, "Clear the corresponding TCIFx flag"] - "CHTIF?": - Clear: [1, "Clear the corresponding HTIFx flag"] - "CTEIF?": - Clear: [1, "Clear the corresponding TEIFx flag"] - "CDMEIF?": - Clear: [1, "Clear the corresponding DMEIFx flag"] - "CFEIF?": - Clear: [1, "Clear the corresponding CFEIFx flag"] - "S?CR": - "[MP]BURST": - Single: [0, "Single transfer"] - INCR4: [1, "Incremental burst of 4 beats"] - INCR8: [2, "Incremental burst of 8 beats"] - INCR16: [3, "Incremental burst of 16 beats"] - CT: - Memory0: [0, "The current target memory is Memory 0"] - Memory1: [1, "The current target memory is Memory 1"] - DBM: - Disabled: [0, "No buffer switching at the end of transfer"] - Enabled: [1, "Memory target switched at the end of the DMA transfer"] - PL: - Low: [0, "Low"] - Medium: [1, "Medium"] - High: [2, "High"] - VeryHigh: [3, "Very high"] - PINCOS: - PSIZE: [0, "The offset size for the peripheral address calculation is linked to the PSIZE"] - Fixed4: [1, "The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment)"] - "[MP]SIZE": - Bits8: [0, "Byte (8-bit)"] - Bits16: [1, "Half-word (16-bit)"] - Bits32: [2, "Word (32-bit)"] - "[MP]INC": - Fixed: [0, "Address pointer is fixed"] - Incremented: [1, "Address pointer is incremented after each data transfer"] - CIRC: - Disabled: [0, "Circular mode disabled"] - Enabled: [1, "Circular mode enabled"] - DIR: - PeripheralToMemory: [0, "Peripheral-to-memory"] - MemoryToPeripheral: [1, "Memory-to-peripheral"] - MemoryToMemory: [2, "Memory-to-memory"] - PFCTRL: - DMA: [0, "The DMA is the flow controller"] - Peripheral: [1, "The peripheral is the flow controller"] - TCIE: - Disabled: [0, "TC interrupt disabled"] - Enabled: [1, "TC interrupt enabled"] - HTIE: - Disabled: [0, "HT interrupt disabled"] - Enabled: [1, "HT interrupt enabled"] - TEIE: - Disabled: [0, "TE interrupt disabled"] - Enabled: [1, "TE interrupt enabled"] - DMEIE: - Disabled: [0, "DME interrupt disabled"] - Enabled: [1, "DME interrupt enabled"] - EN: - Disabled: [0, "Stream disabled"] - Enabled: [1, "Stream enabled"] - "S?NDTR": - NDT: [0, 65535] - "S?FCR": - FEIE: - Disabled: [0, "FE interrupt disabled"] - Enabled: [1, "FE interrupt enabled"] - FS: - Quarter1: [0, "0 < fifo_level < 1/4"] - Quarter2: [1, "1/4 <= fifo_level < 1/2"] - Quarter3: [2, "1/2 <= fifo_level < 3/4"] - Quarter4: [3, "3/4 <= fifo_level < full"] - Empty: [4, "FIFO is empty"] - Full: [5, "FIFO is full"] - DMDIS: - Enabled: [0, "Direct mode is enabled"] - Disabled: [1, "Direct mode is disabled"] - FTH: - Quarter: [0, "1/4 full FIFO"] - Half: [1, "1/2 full FIFO"] - ThreeQuarters: [2, "3/4 full FIFO"] - Full: [3, "Full FIFO"] diff --git a/peripherals/dma/dmamux_v1.yaml b/peripherals/dma/dmamux_v1.yaml deleted file mode 100644 index fe6fad617..000000000 --- a/peripherals/dma/dmamux_v1.yaml +++ /dev/null @@ -1,239 +0,0 @@ -"DMAMUX?": - CCR%s: - NBREQ: [0, 31] - SPOL: - NoEdge: [0, "No event, i.e. no synchronization nor detection"] - RisingEdge: [1, "Rising edge"] - FallingEdge: [2, "Falling edge"] - BothEdges: [3, "Rising and falling edges"] - SE: - Disabled: [0, "Synchronization disabled"] - Enabled: [1, "Synchronization enabled"] - EGE: - Disabled: [0, "Event generation disabled"] - Enabled: [1, "Event generation enabled"] - SOIE: - Disabled: [0, "Synchronization overrun interrupt disabled"] - Enabled: [1, "Synchronization overrun interrupt enabled"] - RGCR%s: - GNBREQ: [0, 31] - GPOL: - NoEdge: [0, "No event, i.e. no detection nor generation"] - RisingEdge: [1, "Rising edge"] - FallingEdge: [2, "Falling edge"] - BothEdges: [3, "Rising and falling edges"] - GE: - Disabled: [0, "DMA request generation disabled"] - Enabled: [1, "DMA request enabled"] - OIE: - Disabled: [0, "Trigger overrun interrupt disabled"] - Enabled: [1, "Trigger overrun interrupt enabled"] - -DMAMUX1: - CCR%s: - SYNC_ID: - dmamux1_evt0: [0, "Signal `dmamux1_evt0` selected as synchronization input"] - dmamux1_evt1: [1, "Signal `dmamux1_evt1` selected as synchronization input"] - dmamux1_evt2: [2, "Signal `dmamux1_evt2` selected as synchronization input"] - lptim1_out: [3, "Signal `lptim1_out` selected as synchronization input"] - lptim2_out: [4, "Signal `lptim2_out` selected as synchronization input"] - lptim3_out: [5, "Signal `lptim3_out` selected as synchronization input"] - extit0: [6, "Signal `extit0` selected as synchronization input"] - tim12_trgo: [7, "Signal `tim12_trgo` selected as synchronization input"] - DMAREQ_ID: - none: [0, "No signal selected as request input"] - dmamux1_req_gen0: [1, "Signal `dmamux1_req_gen0` selected as request input"] - dmamux1_req_gen1: [2, "Signal `dmamux1_req_gen1` selected as request input"] - dmamux1_req_gen2: [3, "Signal `dmamux1_req_gen2` selected as request input"] - dmamux1_req_gen3: [4, "Signal `dmamux1_req_gen3` selected as request input"] - dmamux1_req_gen4: [5, "Signal `dmamux1_req_gen4` selected as request input"] - dmamux1_req_gen5: [6, "Signal `dmamux1_req_gen5` selected as request input"] - dmamux1_req_gen6: [7, "Signal `dmamux1_req_gen6` selected as request input"] - dmamux1_req_gen7: [8, "Signal `dmamux1_req_gen7` selected as request input"] - adc1_dma: [9, "Signal `adc1_dma` selected as request input"] - adc2_dma: [10, "Signal `adc2_dma` selected as request input"] - tim1_ch1: [11, "Signal `tim1_ch1` selected as request input"] - tim1_ch2: [12, "Signal `tim1_ch2` selected as request input"] - tim1_ch3: [13, "Signal `tim1_ch3` selected as request input"] - tim1_ch4: [14, "Signal `tim1_ch4` selected as request input"] - tim1_up: [15, "Signal `tim1_up` selected as request input"] - tim1_trig: [16, "Signal `tim1_trig` selected as request input"] - tim1_com: [17, "Signal `tim1_com` selected as request input"] - tim2_ch1: [18, "Signal `tim2_ch1` selected as request input"] - tim2_ch2: [19, "Signal `tim2_ch2` selected as request input"] - tim2_ch3: [20, "Signal `tim2_ch3` selected as request input"] - tim2_ch4: [21, "Signal `tim2_ch4` selected as request input"] - tim2_up: [22, "Signal `tim2_up` selected as request input"] - tim3_ch1: [23, "Signal `tim3_ch1` selected as request input"] - tim3_ch2: [24, "Signal `tim3_ch2` selected as request input"] - tim3_ch3: [25, "Signal `tim3_ch3` selected as request input"] - tim3_ch4: [26, "Signal `tim3_ch4` selected as request input"] - tim3_up: [27, "Signal `tim3_up` selected as request input"] - tim3_trig: [28, "Signal `tim3_trig` selected as request input"] - tim4_ch1: [29, "Signal `tim4_ch1` selected as request input"] - tim4_ch2: [30, "Signal `tim4_ch2` selected as request input"] - tim4_ch3: [31, "Signal `tim4_ch3` selected as request input"] - tim4_up: [32, "Signal `tim4_up` selected as request input"] - i2c1_rx_dma: [33, "Signal `i2c1_rx_dma` selected as request input"] - i2c1_tx_dma: [34, "Signal `i2c1_tx_dma` selected as request input"] - i2c2_rx_dma: [35, "Signal `i2c2_rx_dma` selected as request input"] - i2c2_tx_dma: [36, "Signal `i2c2_tx_dma` selected as request input"] - spi1_rx_dma: [37, "Signal `spi1_rx_dma` selected as request input"] - spi1_tx_dma: [38, "Signal `spi1_tx_dma` selected as request input"] - spi2_rx_dma: [39, "Signal `spi2_rx_dma` selected as request input"] - spi2_tx_dma: [40, "Signal `spi2_tx_dma` selected as request input"] - usart1_rx_dma: [41, "Signal `usart1_rx_dma` selected as request input"] - usart1_tx_dma: [42, "Signal `usart1_tx_dma` selected as request input"] - usart2_rx_dma: [43, "Signal `usart2_rx_dma` selected as request input"] - usart2_tx_dma: [44, "Signal `usart2_tx_dma` selected as request input"] - usart3_rx_dma: [45, "Signal `usart3_rx_dma` selected as request input"] - usart3_tx_dma: [46, "Signal `usart3_tx_dma` selected as request input"] - tim8_ch1: [47, "Signal `tim8_ch1` selected as request input"] - tim8_ch2: [48, "Signal `tim8_ch2` selected as request input"] - tim8_ch3: [49, "Signal `tim8_ch3` selected as request input"] - tim8_ch4: [50, "Signal `tim8_ch4` selected as request input"] - tim8_up: [51, "Signal `tim8_up` selected as request input"] - tim8_trig: [52, "Signal `tim8_trig` selected as request input"] - tim8_com: [53, "Signal `tim8_com` selected as request input"] - tim5_ch1: [55, "Signal `tim5_ch1` selected as request input"] - tim5_ch2: [56, "Signal `tim5_ch2` selected as request input"] - tim5_ch3: [57, "Signal `tim5_ch3` selected as request input"] - tim5_ch4: [58, "Signal `tim5_ch4` selected as request input"] - tim5_up: [59, "Signal `tim5_up` selected as request input"] - tim5_trig: [60, "Signal `tim5_trig` selected as request input"] - spi3_rx_dma: [61, "Signal `spi3_rx_dma` selected as request input"] - spi3_tx_dma: [62, "Signal `spi3_tx_dma` selected as request input"] - uart4_rx_dma: [63, "Signal `uart4_rx_dma` selected as request input"] - uart4_tx_dma: [64, "Signal `uart4_tx_dma` selected as request input"] - uart5_rx_dma: [65, "Signal `uart5_rx_dma` selected as request input"] - uart5_tx_dma: [66, "Signal `uart5_tx_dma` selected as request input"] - dac_ch1_dma: [67, "Signal `dac_ch1_dma` selected as request input"] - dac_ch2_dma: [68, "Signal `dac_ch2_dma` selected as request input"] - tim6_up: [69, "Signal `tim6_up` selected as request input"] - tim7_up: [70, "Signal `tim7_up` selected as request input"] - usart6_rx_dma: [71, "Signal `usart6_rx_dma` selected as request input"] - usart6_tx_dma: [72, "Signal `usart6_tx_dma` selected as request input"] - i2c3_rx_dma: [73, "Signal `i2c3_rx_dma` selected as request input"] - i2c3_tx_dma: [74, "Signal `i2c3_tx_dma` selected as request input"] - dcmi_dma: [75, "Signal `dcmi_dma` selected as request input"] - cryp_in_dma: [76, "Signal `cryp_in_dma` selected as request input"] - cryp_out_dma: [77, "Signal `cryp_out_dma` selected as request input"] - hash_in_dma: [78, "Signal `hash_in_dma` selected as request input"] - uart7_rx_dma: [79, "Signal `uart7_rx_dma` selected as request input"] - uart7_tx_dma: [80, "Signal `uart7_tx_dma` selected as request input"] - uart8_rx_dma: [81, "Signal `uart8_rx_dma` selected as request input"] - uart8_tx_dma: [82, "Signal `uart8_tx_dma` selected as request input"] - spi4_rx_dma: [83, "Signal `spi4_rx_dma` selected as request input"] - spi4_tx_dma: [84, "Signal `spi4_tx_dma` selected as request input"] - spi5_rx_dma: [85, "Signal `spi5_rx_dma` selected as request input"] - spi5_tx_dma: [86, "Signal `spi5_tx_dma` selected as request input"] - sai1a_dma: [87, "Signal `sai1a_dma` selected as request input"] - sai1b_dma: [88, "Signal `sai1b_dma` selected as request input"] - sai2a_dma: [89, "Signal `sai2a_dma` selected as request input"] - sai2b_dma: [90, "Signal `sai2b_dma` selected as request input"] - swpmi_rx_dma: [91, "Signal `swpmi_rx_dma` selected as request input"] - swpmi_tx_dma: [92, "Signal `swpmi_tx_dma` selected as request input"] - spdifrx_dat_dma: [93, "Signal `spdifrx_dat_dma` selected as request input"] - spdifrx_ctrl_dma: [94, "Signal `spdifrx_ctrl_dma` selected as request input"] - hr_req1: [95, "Signal `hr_req(1)` selected as request input"] - hr_req2: [96, "Signal `hr_req(2)` selected as request input"] - hr_req3: [97, "Signal `hr_req(3)` selected as request input"] - hr_req4: [98, "Signal `hr_req(4)` selected as request input"] - hr_req5: [99, "Signal `hr_req(5)` selected as request input"] - hr_req6: [100, "Signal `hr_req(6)` selected as request input"] - dfsdm1_dma0: [101, "Signal `dfsdm1_dma0` selected as request input"] - dfsdm1_dma1: [102, "Signal `dfsdm1_dma1` selected as request input"] - dfsdm1_dma2: [103, "Signal `dfsdm1_dma2` selected as request input"] - dfsdm1_dma3: [104, "Signal `dfsdm1_dma3` selected as request input"] - tim15_ch1: [105, "Signal `tim15_ch1` selected as request input"] - tim15_up: [106, "Signal `tim15_up` selected as request input"] - tim15_trig: [107, "Signal `tim15_trig` selected as request input"] - tim15_com: [108, "Signal `tim15_com` selected as request input"] - tim16_ch1: [109, "Signal `tim16_ch1` selected as request input"] - tim16_up: [110, "Signal `tim16_up` selected as request input"] - tim17_ch1: [111, "Signal `tim17_ch1` selected as request input"] - tim17_up: [112, "Signal `tim17_up` selected as request input"] - sai3_a_dma: [113, "Signal `sai3_a_dma` selected as request input"] - sai3_b_dma: [114, "Signal `sai3_b_dma` selected as request input"] - adc3_dma: [115, "Signal `adc3_dma` selected as request input"] - RGCR%s: - SIG_ID: - dmamux1_evt0: [0, "Signal `dmamux1_evt0` selected as trigger input"] - dmamux1_evt1: [1, "Signal `dmamux1_evt1` selected as trigger input"] - dmamux1_evt2: [2, "Signal `dmamux1_evt2` selected as trigger input"] - lptim1_out: [3, "Signal `lptim1_out` selected as trigger input"] - lptim2_out: [4, "Signal `lptim2_out` selected as trigger input"] - lptim3_out: [5, "Signal `lptim3_out` selected as trigger input"] - extit0: [6, "Signal `extit0` selected as trigger input"] - tim12_trgo: [7, "Signal `tim12_trgo` selected as trigger input"] - -DMAMUX2: - CCR%s: - SYNC_ID: - dmamux2_evt0: [0, "Signal `dmamux2_evt0` selected as synchronization input"] - dmamux2_evt1: [1, "Signal `dmamux2_evt1` selected as synchronization input"] - dmamux2_evt2: [2, "Signal `dmamux2_evt2` selected as synchronization input"] - dmamux2_evt3: [3, "Signal `dmamux2_evt3` selected as synchronization input"] - dmamux2_evt4: [4, "Signal `dmamux2_evt4` selected as synchronization input"] - dmamux2_evt5: [5, "Signal `dmamux2_evt5` selected as synchronization input"] - lpuart1_rx_wkup: [6, "Signal `lpuart1_rx_wkup` selected as synchronization input"] - lpuart1_tx_wkup: [7, "Signal `lpuart1_tx_wkup` selected as synchronization input"] - lptim2_out: [8, "Signal `lptim2_out` selected as synchronization input"] - lptim3_out: [9, "Signal `lptim3_out` selected as synchronization input"] - i2c4_wkup: [10, "Signal `i2c4_wkup` selected as synchronization input"] - spi6_wkup: [11, "Signal `spi6_wkup` selected as synchronization input"] - comp1_out: [12, "Signal `comp1_out` selected as synchronization input"] - rtc_wkup: [13, "Signal `rtc_wkup` selected as synchronization input"] - syscfg_exti0_mux: [14, "Signal `syscfg_exti0_mux` selected as synchronization input"] - syscfg_exti2_mux: [15, "Signal `syscfg_exti2_mux` selected as synchronization input"] - DMAREQ_ID: - none: [0, "No signal selected as request input"] - dmamux2_req_gen0: [1, "Signal `dmamux2_req_gen0` selected as request input"] - dmamux2_req_gen1: [2, "Signal `dmamux2_req_gen1` selected as request input"] - dmamux2_req_gen2: [3, "Signal `dmamux2_req_gen2` selected as request input"] - dmamux2_req_gen3: [4, "Signal `dmamux2_req_gen3` selected as request input"] - dmamux2_req_gen4: [5, "Signal `dmamux2_req_gen4` selected as request input"] - dmamux2_req_gen5: [6, "Signal `dmamux2_req_gen5` selected as request input"] - dmamux2_req_gen6: [7, "Signal `dmamux2_req_gen6` selected as request input"] - dmamux2_req_gen7: [8, "Signal `dmamux2_req_gen7` selected as request input"] - lpuart1_rx_dma: [9, "Signal `lpuart1_rx_dma` selected as request input"] - lpuart1_tx_dma: [10, "Signal `lpuart1_tx_dma` selected as request input"] - spi6_rx_dma: [11, "Signal `spi6_rx_dma` selected as request input"] - spi6_tx_dma: [12, "Signal `spi6_tx_dma` selected as request input"] - i2c4_rx_dma: [13, "Signal `i2c4_rx_dma` selected as request input"] - i2c4_tx_dma: [14, "Signal `i2c4_tx_dma` selected as request input"] - sai4_a_dma: [15, "Signal `sai4_a_dma` selected as request input"] - sai4_b_dma: [16, "Signal `sai4_b_dma` selected as request input"] - adc3_dma: [17, "Signal `adc3_dma` selected as request input"] - RGCR%s: - SIG_ID: - dmamux2_evt0: [0, "Signal `dmamux2_evt0` selected as trigger input"] - dmamux2_evt1: [1, "Signal `dmamux2_evt1` selected as trigger input"] - dmamux2_evt2: [2, "Signal `dmamux2_evt2` selected as trigger input"] - dmamux2_evt3: [3, "Signal `dmamux2_evt3` selected as trigger input"] - dmamux2_evt4: [4, "Signal `dmamux2_evt4` selected as trigger input"] - dmamux2_evt5: [5, "Signal `dmamux2_evt5` selected as trigger input"] - dmamux2_evt6: [6, "Signal `dmamux2_evt6` selected as trigger input"] - lpuart_rx_wkup: [7, "Signal `lpuart_rx_wkup` selected as trigger input"] - lpuart_tx_wkup: [8, "Signal `lpuart_tx_wkup` selected as trigger input"] - lptim2_wkup: [9, "Signal `lptim2_wkup` selected as trigger input"] - lptim2_out: [10, "Signal `lptim2_out` selected as trigger input"] - lptim3_wkup: [11, "Signal `lptim3_wkup` selected as trigger input"] - lptim3_out: [12, "Signal `lptim3_out` selected as trigger input"] - lptim4_ait: [13, "Signal `lptim4_ait` selected as trigger input"] - lptim5_ait: [14, "Signal `lptim5_ait` selected as trigger input"] - i2c4_wkup: [15, "Signal `i2c4_wkup` selected as trigger input"] - spi6_wkup: [16, "Signal `spi6_wkup` selected as trigger input"] - comp1_out: [17, "Signal `comp1_out` selected as trigger input"] - comp2_out: [18, "Signal `comp2_out` selected as trigger input"] - rtc_wkup: [19, "Signal `rtc_wkup` selected as trigger input"] - syscfg_exti0_mux: [20, "Signal `syscfg_exti0_mux` selected as trigger input"] - syscfg_exti2_mux: [21, "Signal `syscfg_exti2_mux` selected as trigger input"] - i2c4_event_it: [22, "Signal `i2c4_event_it` selected as trigger input"] - spi6_it: [23, "Signal `spi6_it` selected as trigger input"] - lpuart1_it_t: [24, "Signal `lpuart1_it_t` selected as trigger input"] - lpuart1_it_r: [25, "Signal `lpuart1_it_r` selected as trigger input"] - adc3_it: [26, "Signal `adc3_it` selected as trigger input"] - adc3_awd1: [27, "Signal `adc3_awd1` selected as trigger input"] - bdma_ch0_it: [28, "Signal `bdma_ch0_it` selected as trigger input"] - bdma_ch1_it: [29, "Signal `bdma_ch1_it` selected as trigger input"] diff --git a/peripherals/eth/eth_dma_common.yaml b/peripherals/eth/eth_dma_common.yaml deleted file mode 100644 index c4335e9bb..000000000 --- a/peripherals/eth/eth_dma_common.yaml +++ /dev/null @@ -1,276 +0,0 @@ -"Ethernet_DMA": - DMABMR: - AAB: - Unaligned: [0, "Bursts are not aligned"] - Aligned: [1, "Align bursts to start address LS bits. First burst alignment depends on FB bit"] - FPM: - x1: [0, "PBL values used as-is"] - x4: [1, "PBL values multiplied by 4"] - USP: - Combined: [0, "PBL value used for both Rx and Tx DMA"] - Separate: [1, "RxDMA uses RDP value, TxDMA uses PBL value"] - RDP: - RDP1: [1, "1 beat per RxDMA transaction"] - RDP2: [2, "2 beats per RxDMA transaction"] - RDP4: [4, "4 beats per RxDMA transaction"] - RDP8: [8, "8 beats per RxDMA transaction"] - RDP16: [16, "16 beats per RxDMA transaction"] - RDP32: [32, "32 beats per RxDMA transaction"] - FB: - Variable: [0, "AHB uses SINGLE and INCR burst transfers"] - Fixed: [1, "AHB uses only fixed burst transfers"] - PM: - OneToOne: [0, "RxDMA priority over TxDMA is 1:1"] - TwoToOne: [1, "RxDMA priority over TxDMA is 2:1"] - ThreeToOne: [2, "RxDMA priority over TxDMA is 3:1"] - FourToOne: [3, "RxDMA priority over TxDMA is 4:1"] - PBL: - PBL1: [1, "Maximum of 1 beat per DMA transaction"] - PBL2: [2, "Maximum of 2 beats per DMA transaction"] - PBL4: [4, "Maximum of 4 beats per DMA transaction"] - PBL8: [8, "Maximum of 8 beats per DMA transaction"] - PBL16: [16, "Maximum of 16 beats per DMA transaction"] - PBL32: [32, "Maximum of 32 beats per DMA transaction"] - DSL: [0, 0x1F] - DA: - RoundRobin: [0, "Round-robin with Rx:Tx priority given by PM"] - RxPriority: [1, "Rx has priority over Tx"] - SR: - Reset: [1, "Reset all MAC subsystem internal registers and logic. Cleared automatically"] - _modify: - MB: - description: Mixed burst - AAB: - description: Address-aligned beats - FPM: - description: 4xPBL mode - USP: - description: Use separate PBL - RDP: - description: Rx DMA PBL - FB: - description: Fixed burst - PM: - description: Rx-Tx priority ratio - PBL: - description: Programmable burst length - EDFE: - description: Enhanced descriptor format enable - DSL: - description: Descriptor skip length - DA: - description: DMA arbitration - SR: - description: Software reset - - DMATPDR: - TPD: - Poll: [0, "Poll the transmit descriptor list"] - _modify: - TPD: - description: Transmit poll demand - - DMARPDR: - RPD: - Poll: [0, "Poll the receive descriptor list"] - _modify: - RPD: - description: Receive poll demand - - DMARDLAR: - _modify: - SRL: - description: Start of receive list - - DMATDLAR: - _modify: - STL: - description: Start of transmit list - - DMASR: - TPS: - Stopped: [0, "Stopped, Reset or Stop Transmit command issued"] - RunningFetching: [1, "Running, fetching transmit transfer descriptor"] - RunningWaiting: [2, "Running, waiting for status"] - RunningReading: [3, "Running, reading data from host memory buffer"] - Suspended: [6, "Suspended, transmit descriptor unavailable or transmit buffer underflow"] - Running: [7, "Running, closing transmit descriptor"] - RPS: - Stopped: [0, "Stopped, reset or Stop Receive command issued"] - RunningFetching: [1, "Running, fetching receive transfer descriptor"] - RunningWaiting: [3, "Running, waiting for receive packet"] - Suspended: [4, "Suspended, receive descriptor unavailable"] - RunningWriting: [7, "Running, writing data to host memory buffer"] - _modify: - TSTS: - description: Time stamp trigger status - PMTS: - description: PMT status - MMCS: - description: MMC status - EBS: - description: Error bits status - TPS: - description: Transmit process state - RPS: - description: Receive process state - NIS: - description: Normal interrupt summary - AIS: - description: Abnormal interrupt summary - ERS: - description: Early receive status - FBES: - description: Fatal bus error status - ETS: - description: Early transmit status - RWTS: - description: Receive watchdog timeout status - RPSS: - description: Receive process stopped status - RBUS: - description: Receive buffer unavailable status - RS: - description: Receive status - TUS: - description: Transmit underflow status - ROS: - description: Receive overflow status - TJTS: - description: Transmit jabber timeout status - TBUS: - description: Transmit buffer unavailable status - TPSS: - description: Transmit process stopped status - TS: - description: Transmit status - - DMAOMR: - DTCEFD: - Enabled: [0, "Drop frames with errors only in the receive checksum offload engine"] - Disabled: [1, "Do not drop frames that only have errors in the receive checksum offload engine"] - RSF: - CutThrough: [0, "Rx FIFO operates in cut-through mode, subject to RTC bits"] - StoreForward: [1, "Frames are read from Rx FIFO after complete frame has been written"] - DFRF: - TSF: - CutThrough: [0, "Transmission starts when the frame size in the Tx FIFO exceeds TTC threshold"] - StoreForward: [1, "Transmission starts when a full frame is in the Tx FIFO"] - FTF: - Flush: [1, "Transmit FIFO controller logic is reset to its default values. Cleared automatically"] - TTC: - TTC64: [0, "64 bytes"] - TTC128: [1, "128 bytes"] - TTC192: [2, "192 bytes"] - TTC256: [3, "256 bytes"] - TTC40: [4, "40 bytes"] - TTC32: [5, "32 bytes"] - TTC24: [6, "24 bytes"] - TTC16: [7, "16 bytes"] - ST: - Stopped: [0, "Transmission is placed in the Stopped state"] - Started: [1, "Transmission is placed in Running state"] - FEF: - Drop: [0, "Rx FIFO drops frames with error status"] - Forward: [1, "All frames except runt error frames are forwarded to the DMA"] - FUGF: - Drop: [0, "Rx FIFO drops all frames of less than 64 bytes"] - Forward: [1, "Rx FIFO forwards undersized frames"] - RTC: - RTC64: [0, "64 bytes"] - RTC32: [1, "32 bytes"] - RTC96: [2, "96 bytes"] - RTC128: [3, "128 bytes"] - OSF: - SR: - Stopped: [0, "Reception is stopped after transfer of the current frame"] - Started: [1, "Reception is placed in the Running state"] - _modify: - DTCEFD: - description: Dropping of TCP/IP checksum error frames disable - RSF: - description: Receive store and forward - DFRF: - description: Disable flushing of received frames - TSF: - description: Transmit store and forward - FTF: - description: Flush transmit FIFO - TTC: - description: Transmit threshold control - ST: - description: Start/stop transmission - FEF: - description: Forward error frames - FUGF: - description: Forward undersized good frames - RTC: - description: Receive threshold control - OSF: - description: Operate on second frame - SR: - description: Start/stop receive - - DMAIER: - _modify: - NISE: - description: Normal interrupt summary enable - AISE: - description: Abnormal interrupt summary enable - ERIE: - description: Early receive interrupt enable - FBEIE: - description: Fatal bus error interrupt enable - ETIE: - description: Early transmit interrupt enable - RWTIE: - description: Receive watchdog timeout interrupt enable - RPSIE: - description: Receive process stopped interrupt enable - RBUIE: - description: Receive buffer unavailable interrupt enable - RIE: - description: Receive interrupt enable - TUIE: - description: Transmit underflow interrupt enable - ROIE: - description: Receive overflow interrupt enable - TJTIE: - description: Transmit jabber timeout interrupt enable - TBUIE: - description: Transmit buffer unavailable interrupt enable - TPSIE: - description: Transmit process stopped interrupt enable - TIE: - description: Transmit interrupt enable - - DMAMFBOCR: - _modify: - OFOC: - description: Overflow bit for FIFO overflow counter - MFA: - description: Missed frames by the application - OMFC: - description: Overflow bit for missed frame counter - MFC: - description: Missed frames by the controller - - DMACHTDR: - _modify: - HTDAP: - description: Host transmit descriptor address pointer - - DMACHRDR: - _modify: - HRDAP: - description: Host receive descriptor address pointer - - DMACHTBAR: - _modify: - HTBAP: - description: Host transmit buffer address pointer - - DMACHRBAR: - _modify: - HRBAP: - description: Host receive buffer address pointer diff --git a/peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml b/peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml deleted file mode 100644 index e04dc4965..000000000 --- a/peripherals/eth/eth_dma_mb_edfe_dmarswtr.yaml +++ /dev/null @@ -1,14 +0,0 @@ -"Ethernet_DMA": - DMABMR: - MB: - Normal: [0, "Fixed burst transfers (INCRx and SINGLE) for burst lengths of 16 and below"] - Mixed: [1, "If FB is low, start all bursts greater than 16 with INCR (undefined burst)"] - EDFE: - Disabled: [0, "Normal descriptor format"] - Enabled: [1, "Enhanced 32-byte descriptor format, required for timestamping and IPv4 checksum offload"] - - DMARSWTR: - RSWTC: [0, 0xFF] - _modify: - RSWTC: - description: Receive status watchdog timer count diff --git a/peripherals/eth/eth_mac_common.yaml b/peripherals/eth/eth_mac_common.yaml deleted file mode 100644 index da7bbc75d..000000000 --- a/peripherals/eth/eth_mac_common.yaml +++ /dev/null @@ -1,314 +0,0 @@ -"Ethernet_MAC": - MACCR: - WD: - Enabled: [0, "Watchdog enabled, receive frames limited to 2048 bytes"] - Disabled: [1, "Watchdog disabled, receive frames may be up to to 16384 bytes"] - JD: - Enabled: [0, "Jabber enabled, transmit frames up to 2048 bytes"] - Disabled: [1, "Jabber disabled, transmit frames up to 16384 bytes"] - IFG: - IFG96: [0, "96 bit times"] - IFG88: [1, "88 bit times"] - IFG80: [2, "80 bit times"] - IFG80: [3, "72 bit times"] - IFG80: [4, "64 bit times"] - IFG80: [5, "56 bit times"] - IFG80: [6, "48 bit times"] - IFG40: [7, "40 bit times"] - CSD: - Enabled: [0, "Errors generated due to loss of carrier"] - Disabled: [1, "No error generated due to loss of carrier"] - FES: - FES10: [0, "10 Mbit/s"] - FES100: [1, "100 Mbit/s"] - ROD: - Enabled: [0, "MAC receives all packets from PHY while transmitting"] - Disabled: [1, "MAC disables reception of frames in half-duplex mode"] - LM: - Normal: [0, "Normal mode"] - Loopback: [1, "MAC operates in loopback mode at the MII"] - DM: - HalfDuplex: [0, "MAC operates in half-duplex mode"] - FullDuplex: [1, "MAC operates in full-duplex mode"] - IPCO: - Disabled: [0, "IPv4 checksum offload disabled"] - Offload: [1, "IPv4 checksums are checked in received frames"] - RD: - Enabled: [0, "MAC attempts retries based on the settings of BL"] - Disabled: [1, "MAC attempts only 1 transmission"] - APCS: - Disabled: [0, "MAC passes all incoming frames unmodified"] - Strip: [1, "MAC strips the Pad/FCS field on incoming frames only for lengths less than or equal to 1500 bytes"] - BL: - BL10: [0, "For retransmission n, wait up to 2^min(n, 10) time slots"] - BL8: [1, "For retransmission n, wait up to 2^min(n, 8) time slots"] - BL4: [2, "For retransmission n, wait up to 2^min(n, 4) time slots"] - BL1: [3, "For retransmission n, wait up to 2^min(n, 1) time slots"] - DC: - Disabled: [0, "MAC defers until CRS signal goes inactive"] - Enabled: [1, "Deferral check function enabled"] - TE: - Disabled: [0, "MAC transmit state machine is disabled after completion of the transmission of the current frame"] - Enabled: [1, "MAC transmit state machine is enabled"] - RE: - Disabled: [0, "MAC receive state machine is disabled after the completion of the reception of the current frame"] - Enabled: [1, "MAC receive state machine is enabled"] - _modify: - CSTF: - description: CRC stripping for type frames - WD: - description: Watchdog disable - JD: - description: Jabber disable - IFG: - description: Interframe gap - CSD: - description: Carrier sense disable - FES: - description: Fast Ethernet speed - ROD: - description: Receive own disable - LM: - description: Loopback mode - DM: - description: Duplex mode - IPCO: - description: IPv4 checksum offload - RD: - description: Retry disable - APCS: - description: Automatic pad/CRC stripping - BL: - description: Back-off limit - DC: - description: Deferral check - TE: - description: Transmitter enable - RE: - description: Receiver enable - - MACFFR: - RA: - Disabled: [0, "MAC receiver passes on to the application only those frames that have passed the SA/DA address file"] - Enabled: [1, "MAC receiver passes oll received frames on to the application"] - HPF: - HashOnly: [0, "If HM or HU is set, only frames that match the Hash filter are passed"] - HashOrPerfect: [1, "If HM or HU is set, frames that match either the perfect filter or the hash filter are passed"] - SAF: - Disabled: [0, "Source address ignored"] - Enabled: [1, "MAC drops frames that fail the source address filter"] - SAIF: - Normal: [0, "Source address filter operates normally"] - Invert: [1, "Source address filter operation inverted"] - PCF: - PreventAll: [0, "MAC prevents all control frames from reaching the application"] - ForwardAllExceptPause: [1, "MAC forwards all control frames to application except Pause"] - ForwardAll: [2, "MAC forwards all control frames to application even if they fail the address filter"] - ForwardAllFiltered: [3, "MAC forwards control frames that pass the address filter"] - BFD: - Enabled: [0, "Address filters pass all received broadcast frames"] - Disabled: [1, "Address filters filter all incoming broadcast frames"] - PAM: - Disabled: [0, "Filtering of multicast frames depends on HM"] - Enabled: [1, "All received frames with a multicast destination address are passed"] - DAIF: - Normal: [0, "Normal filtering of frames"] - Invert: [1, "Address check block operates in inverse filtering mode for the DA address comparison"] - HM: - Perfect: [0, "MAC performs a perfect destination address filtering for multicast frames"] - Hash: [1, "MAC performs destination address filtering of received multicast frames according to the hash table"] - HU: - Perfect: [0, "MAC performs a perfect destination address filtering for unicast frames"] - Hash: [1, "MAC performs destination address filtering of received unicast frames according to the hash table"] - PM: - Disabled: [0, "Normal address filtering"] - Enabled: [1, "Address filters pass all incoming frames regardless of their destination or source address"] - _modify: - RA: - description: Receive all - HPF: - description: Hash or perfect filter - SAF: - description: Source address filter - SAIF: - description: Source address inverse filtering - PCF: - description: Pass control frames - BFD: - description: Broadcast frames disable - RAM: - name: PAM - description: Pass all multicast - DAIF: - description: Destination address unique filtering - HM: - description: Hash multicast - HU: - description: Hash unicast - PM: - description: Promiscuous mode - - MACHTHR: - HTH: [0, 0xFFFFFFFF] - _modify: - HTH: - description: Upper 32 bits of hash table - - MACHTLR: - HTL: [0, 0xFFFFFFFF] - _modify: - HTL: - description: Lower 32 bits of hash table - - MACMIIAR: - PA: [0, 0x1F] - MR: [0, 0x1F] - CR: - CR_60_100: [0, "60-100MHz HCLK/42"] - CR_100_150: [1, "100-150 MHz HCLK/62"] - CR_20_35: [2, "20-35MHz HCLK/16"] - CR_35_60: [3, "35-60MHz HCLK/16"] - CR_150_168: [4, "150-168MHz HCLK/102"] - MW: - Read: [0, "Read operation"] - Write: [1, "Write operation"] - MB: - Busy: [1, "This bit is set to 1 by the application to indicate that a read or write access is in progress"] - _modify: - PA: - description: PHY address - select which of possible 32 PHYs is being accessed - MR: - description: MII register - select the desired MII register in the PHY device - CR: - description: Clock range - MW: - description: MII write - MB: - description: MII busy - - MACMIIDR: - MD: [0, 0xFFFF] - _modify: - MD: - description: MII data read from/written to the PHY - - MACFCR: - PT: [0, 0xFFFF] - ZQPD: - Enabled: [0, "Normal operation with automatic zero-quanta pause control frame generation"] - Disabled: [1, "Automatic generation of zero-quanta pause control frames is disabled"] - PLT: - PLT4: [0, "Pause time minus 4 slot times"] - PLT28: [1, "Pause time minus 28 slot times"] - PLT144: [2, "Pause time minus 144 slot times"] - PLT256: [3, "Pause time minus 256 slot times"] - UPFD: - Disabled: [0, "MAC detects only a Pause frame with the multicast address specified in the 802.3x standard"] - Enabled: [1, "MAC additionally detects Pause frames with the station's unicast address"] - RFCE: - Disabled: [0, "Pause frames are not decoded"] - Enabled: [1, "MAC decodes received Pause frames and disables its transmitted for a specified time"] - TFCE: - Disabled: [0, "In full duplex, flow control is disabled. In half duplex, back pressure is disabled"] - Enabled: [1, "In full duplex, flow control is enabled. In half duplex, back pressure is enabled"] - FCB: - PauseOrBackPressure: [1, "In full duplex, initiate a Pause control frame. In half duplex, assert back pressure"] - DisableBackPressure: [0, "In half duplex only, deasserts back pressure"] - _modify: - PT: - description: Pause time - ZQPD: - description: Zero-quanta pause disable - PLT: - description: Pause low threshold - UPFD: - description: Unicast pause frame detect - RFCE: - description: Receive flow control enable - TFCE: - description: Transmit flow control enable - FCB: - description: Flow control busy/back pressure activate - - MACVLANTR: - VLANTC: - VLANTC16: [0, "Full 16 bit VLAN identifiers are used for comparison and filtering"] - VLANTC12: [1, "12 bit VLAN identifies are used for comparison and filtering"] - VLANTI: [0, 0xFFFF] - _modify: - VLANTC: - description: 12-bit VLAN tag comparison - VLANTI: - description: VLAN tag identifier (for receive frames) - - MACPMTCSR: - WFFRPR: - Reset: [1, "Reset wakeup frame filter register point to 0b000. Automatically cleared"] - GU: - Disabled: [0, "Normal operation"] - Enabled: [1, "Any unicast packet filtered by the MAC address recognition may be a wakeup frame"] - WFE: - Disabled: [0, "No power management event generated due to wakeup frame reception"] - Enabled: [1, "Enable generation of a power management event due to wakeup frame reception"] - MPE: - Disabled: [0, "No power management event generated due to Magic Packet reception"] - Enabled: [1, "Enable generation of a power management event due to Magic Packet reception"] - PD: - Enabled: [1, "All received frames will be dropped. Cleared automatically when a magic packet or wakeup frame is received"] - _modify: - WFFRPR: - description: Wakeup frame filter register pointer reset - GU: - description: Global unicast - WFR: - description: Wakeup frame received - MPR: - description: Magic packet received - WFE: - description: Wakeup frame enable - MPE: - description: Magic packet enable - PD: - description: Power down - - MACSR: - _modify: - TSTS: - description: Time stamp trigger status - MMCTS: - description: MMC transmit status - MMCRS: - description: MMC receive status - MMCS: - description: MMC status - PMTS: - description: PMT status - - MACIMR: - TSTIM: - Unmasked: [0, "Time stamp interrupt generation enabled"] - Masked: [1, "Time stamp interrupt generation disabled"] - PMTIM: - Unmasked: [0, "PMT Status interrupt generation enabled"] - Masked: [1, "PMT Status interrupt generation disabled"] - _modify: - TSTIM: - description: Time stamp trigger interrupt mask - PMTIM: - description: PMT interrupt mask - - MACA0HR: - MACA0H: [0, 0xFFFF] - - "MACA?LR": - "MACA?L": [0, 0xFFFFFFFF] - - "MACA[123]HR": - AE: - Disabled: [0, "Address filters ignore this address"] - Enabled: [1, "Address filters use this address"] - SA: - Destination: [0, "This address is used for comparison with DA fields of the received frame"] - Source: [1, "This address is used for comparison with SA fields of received frames"] - MBC: [0, 0x3F] - "MACA?H": [0, 0xFFFF] diff --git a/peripherals/eth/eth_mac_cstf.yaml b/peripherals/eth/eth_mac_cstf.yaml deleted file mode 100644 index f55ad9079..000000000 --- a/peripherals/eth/eth_mac_cstf.yaml +++ /dev/null @@ -1,5 +0,0 @@ -"Ethernet_MAC": - MACCR: - CSTF: - Disabled: [0, "CRC not stripped"] - Enabled: [1, "CRC stripped"] diff --git a/peripherals/eth/eth_mmc_common.yaml b/peripherals/eth/eth_mmc_common.yaml deleted file mode 100644 index 4185f4cc0..000000000 --- a/peripherals/eth/eth_mmc_common.yaml +++ /dev/null @@ -1,85 +0,0 @@ -"Ethernet_MMC": - MMCCR: - MCF: - Unfrozen: [0, "All MMC counters update normally"] - Frozen: [1, "All MMC counters frozen to their current value"] - ROR: - Disabled: [0, "MMC counters do not reset on read"] - Enabled: [1, "MMC counters reset to zero after read"] - CSR: - Disabled: [0, "Counters roll over to zero after reaching the maximum value"] - Enabled: [1, "Counters do not roll over to zero after reaching the maximum value"] - CR: - Reset: [1, "Reset all counters. Cleared automatically"] - _modify: - MCFHP: - description: MMC counter Full-Half preset - MCP: - description: MMC counter preset - MCF: - description: MMC counter freeze - ROR: - description: Reset on read - CSR: - description: Counter stop rollover - CR: - description: Counter reset - - MMCRIR: - _modify: - RGUFS: - description: Received good Unicast frames status - RFAES: - description: Received frames alignment error status - RFCES: - description: Received frames CRC error status - - MMCTIR: - _modify: - TGFS: - description: Transmitted good frames status - TGFMSCS: - description: Transmitted good frames more than single collision status - TGFSCS: - description: Transmitted good frames single collision status - - MMCRIMR: - RGUFM: - Unmasked: [0, "Received-good-unicast counter half-full interrupt enabled"] - Masked: [1, "Received-good-unicast counter half-full interrupt disabled"] - RFAEM: - Unmasked: [0, "Received-alignment-error counter half-full interrupt enabled"] - Masked: [1, "Received-alignment-error counter half-full interrupt disabled"] - RFCEM: - Unmasked: [0, "Received-crc-error counter half-full interrupt enabled"] - Masked: [1, "Received-crc-error counter half-full interrupt disabled"] - _modify: - RGUFM: - description: Received good Unicast frames mask - RFAEM: - description: Received frames alignment error mask - RFCEM: - description: Received frame CRC error mask - - MMCTIMR: - TGFM: - Unmasked: [0, "Transmitted-good counter half-full interrupt enabled"] - Masked: [1, "Transmitted-good counter half-full interrupt disabled"] - TGFMSCM: - Unmasked: [0, "Transmitted-good-multiple-collision half-full interrupt enabled"] - Masked: [1, "Transmitted-good-multiple-collision half-full interrupt disabled"] - TGFSCM: - Unmasked: [0, "Transmitted-good-single-collision half-full interrupt enabled"] - Masked: [1, "Transmitted-good-single-collision half-full interrupt disabled"] - _modify: - TGFM: - description: Transmitted good frames mask - TGFMSCM: - description: Transmitted good frames more than single collision mask - TGFSCM: - description: Transmitted good frames single collision mask - - MMCTGFSCCR: - _modify: - TGFSCC: - description: Transmitted good frames single collision counter diff --git a/peripherals/eth/eth_mmc_mcfhp_mcp.yaml b/peripherals/eth/eth_mmc_mcfhp_mcp.yaml deleted file mode 100644 index 22b1cd1dc..000000000 --- a/peripherals/eth/eth_mmc_mcfhp_mcp.yaml +++ /dev/null @@ -1,7 +0,0 @@ -"Ethernet_MMC": - MMCCR: - MCFHP: - AlmostHalf: [0, "When MCP is set, MMC counters are preset to almost-half value 0x7FFF_FFF0"] - AlmostFull: [1, "When MCP is set, MMC counters are preset to almost-full value 0xFFFF_FFF0"] - MCP: - Preset: [1, "MMC counters will be preset to almost full or almost half. Cleared automatically"] diff --git a/peripherals/exti/exti.yaml b/peripherals/exti/exti.yaml deleted file mode 100644 index a06635be0..000000000 --- a/peripherals/exti/exti.yaml +++ /dev/null @@ -1,28 +0,0 @@ -EXTI: - IMR,IMR?,CPUIMR?,C?IMR?,D3PMR?: - "MR*,IM*": - Masked: [0, "Interrupt request line is masked"] - Unmasked: [1, "Interrupt request line is unmasked"] - EMR,EMR?,CPUEMR?,C?EMR?: - "MR*,EM*": - Masked: [0, "Interrupt request line is masked"] - Unmasked: [1, "Interrupt request line is unmasked"] - RTSR,RTSR?: - "TR*,RT*": - Disabled: [0, "Rising edge trigger is disabled"] - Enabled: [1, "Rising edge trigger is enabled"] - FTSR,FTSR?: - "TR*,FT*": - Disabled: [0, "Falling edge trigger is disabled"] - Enabled: [1, "Falling edge trigger is enabled"] - SWIER,SWIER?: - "SWIER*,SWI*": - _write: - Pend: [1, "Generates an interrupt request"] - PR,PR?,?PR?,CPUPR?,C?PR?: - "PR*,PIF*,?PIF*": - _write: - Clear: [1, "Clears pending bit"] - _read: - NotPending: [0, "No trigger request occurred"] - Pending: [1, "Selected trigger request occurred"] diff --git a/peripherals/exti/exti_g0.yaml b/peripherals/exti/exti_g0.yaml deleted file mode 100644 index 0188fec35..000000000 --- a/peripherals/exti/exti_g0.yaml +++ /dev/null @@ -1,16 +0,0 @@ -_include: - - exti.yaml - -EXTI: - EXTICR?: - "EXTI*": - PA: [0, "GPIO port A selected"] - PB: [1, "GPIO port B selected"] - PC: [2, "GPIO port C selected"] - PD: [3, "GPIO port D selected"] - PF: [5, "GPIO port F selected"] - - # fix bug: some svd files have the offset wrong for EMR1 - _modify: - EMR1: - addressOffset: "0x84" \ No newline at end of file diff --git a/peripherals/exti/exti_h7.yaml b/peripherals/exti/exti_h7.yaml deleted file mode 100644 index aacb7b9ed..000000000 --- a/peripherals/exti/exti_h7.yaml +++ /dev/null @@ -1,10 +0,0 @@ -_include: - - exti.yaml - -EXTI: - D3PCR??: - "PCS*": - DMA_CH6: [0, "DMA ch6 event selected as D3 domain pendclear source"] - DMA_CH7: [1, "DMA ch7 event selected as D3 domain pendclear source"] - LPTIM4: [2, "LPTIM4 out selected as D3 domain pendclear source"] - LPTIM5: [3, "LPTIM5 out selected as D3 domain pendclear source"] diff --git a/peripherals/flash/flash_f0.yaml b/peripherals/flash/flash_f0.yaml deleted file mode 100644 index cc3f3ef14..000000000 --- a/peripherals/flash/flash_f0.yaml +++ /dev/null @@ -1,100 +0,0 @@ -# Flash peripheral -# Applicable to STM32F0 -# OBR->BOOT_SEL and OBR->nBOOT0 available only on STM32F04x and STM32F09x - -"Flash": - ACR: - PRFTBS: - _read: - Disabled: [0, "Prefetch buffer is disabled"] - Enabled: [1, "Prefetch buffer is enabled"] - PRFTBE: - Disabled: [0, "Prefetch is disabled"] - Enabled: [1, "Prefetch is enabled"] - LATENCY: - WS0: [0, "0 wait states"] - WS1: [1, "1 wait state"] - - KEYR: - FKEYR: [0, 0xFFFFFFFF] - - OPTKEYR: - OPTKEYR: [0, 0xFFFFFFFF] - - SR: - EOP: - NoEvent: [0, "No EOP operation occurred"] - Event: [1, "An EOP event occurred"] - WRPRT: - NoError: [0, "No write protection error occurred"] - Error: [1, "A write protection error occurred"] - PGERR: - NoError: [0, "No programming error occurred"] - Error: [1, "A programming error occurred"] - BSY: - _read: - Inactive: [0, "No write/erase operation is in progress"] - Active: [1, "No write/erase operation is in progress"] - - CR: - FORCE_OPTLOAD: - Inactive: [0, "Force option byte loading inactive"] - Active: [1, "Force option byte loading active"] - EOPIE: - Disabled: [0, "End of operation interrupt disabled"] - Enabled: [1, "End of operation interrupt enabled"] - ERRIE: - Disabled: [0, "Error interrupt generation disabled"] - Enabled: [1, "Error interrupt generation enabled"] - OPTWRE: - Disabled: [0, "Option byte write enabled"] - Enabled: [1, "Option byte write disabled"] - LOCK: - Unlocked: [0, "FLASH_CR register is unlocked"] - Locked: [1, "FLASH_CR register is locked"] - STRT: - Start: [1, "Trigger an erase operation"] - OPTER: - OptionByteErase: [1, "Erase option byte activated"] - OPTPG: - OptionByteProgramming: [1, "Program option byte activated"] - MER: - MassErase: [1, "Erase activated for all user sectors"] - PER: - PageErase: [1, "Erase activated for selected page"] - PG: - Program: [1, "Flash programming activated"] - - AR: - FAR: [0, 0xFFFFFFFF] - - OBR: - Data1: [0, 0xFF] - Data0: [0, 0xFF] - RAM_PARITY_CHECK: - Disabled: [1, "RAM parity check disabled"] - Enabled: [0, "RAM parity check enabled"] - VDDA_MONITOR: - Disabled: [0, "VDDA power supply supervisor disabled"] - Enabled: [1, "VDDA power supply supervisor enabled"] - nBOOT1: - Disabled: [0, "Together with BOOT0, select the device boot mode"] - Enabled: [1, "Together with BOOT0, select the device boot mode"] - nRST_STDBY: - Reset: [0, "Reset generated when entering Standby mode"] - NoReset: [1, "No reset generated"] - nRST_STOP: - Reset: [0, "Reset generated when entering Stop mode"] - NoReset: [1, "No reset generated"] - WDG_SW: - Hardware: [0, "Hardware watchdog"] - Software: [1, "Software watchdog"] - RDPRT: - Level0: [0, "Level 0"] - Level1: [1, "Level 1"] - Level2: [3, "Level 2"] - OPTERR: - OptionByteError: [1, "The loaded option byte and its complement do not match"] - - WRPR: - WRP: [0, 0xFFFFFFFF] diff --git a/peripherals/flash/flash_f04x_f09x.yaml b/peripherals/flash/flash_f04x_f09x.yaml deleted file mode 100644 index d980906cc..000000000 --- a/peripherals/flash/flash_f04x_f09x.yaml +++ /dev/null @@ -1,11 +0,0 @@ -_include: - - ./flash_f0.yaml - -"Flash": - OBR: - BOOT_SEL: - nBOOT0: [0, "BOOT0 signal is defined by nBOOT0 option bit"] - BOOT0: [1, "BOOT0 signal is defined by BOOT0 pin value (legacy mode)"] - nBOOT0: - Disabled: [0, "When BOOT_SEL is cleared, select the device boot mode"] - Enabled: [1, "When BOOT_SEL is cleared, select the device boot mode"] diff --git a/peripherals/flash/flash_f1.yaml b/peripherals/flash/flash_f1.yaml deleted file mode 100644 index a89f32b5d..000000000 --- a/peripherals/flash/flash_f1.yaml +++ /dev/null @@ -1,6 +0,0 @@ -"FLASH": - ACR: - LATENCY: - WS0: [0, "Zero wait state, if 0 < SYSCLK≤ 24 MHz"] - WS1: [1, "One wait state, if 24 MHz < SYSCLK ≤ 48 MHz"] - WS2: [2, "Two wait states, if 48 MHz < SYSCLK ≤ 72 MHz"] diff --git a/peripherals/flash/flash_f3_acr_hlfcya.yaml b/peripherals/flash/flash_f3_acr_hlfcya.yaml deleted file mode 100644 index 8c98cbc2b..000000000 --- a/peripherals/flash/flash_f3_acr_hlfcya.yaml +++ /dev/null @@ -1,5 +0,0 @@ -FLASH: - ACR: - HLFCYA: - Disabled: [0, "Half cycle is disabled"] - Enabled: [1, "Half cycle is enabled"] diff --git a/peripherals/flash/flash_f3_common.yaml b/peripherals/flash/flash_f3_common.yaml deleted file mode 100644 index ac75121b5..000000000 --- a/peripherals/flash/flash_f3_common.yaml +++ /dev/null @@ -1,108 +0,0 @@ -# Flash peripheral -# Applicable to STM32F3 - -FLASH: - ACR: - PRFTBS: - Disabled: [0, "Prefetch buffer is disabled"] - Enabled: [1, "Prefetch buffer is enabled"] - PRFTBE: - Disabled: [0, "Prefetch is disabled"] - Enabled: [1, "Prefetch is enabled"] - LATENCY: - WS0: [0, "0 wait states, if 0 < HCLK <= 24 MHz"] - WS1: [1, "1 wait state, if 24 < HCLK <= 48 MHz"] - WS2: [2, "2 wait states, if 48 < HCLK <= 72 MHz"] - - KEYR: - FKEYR: [0, 0xFFFFFFFF] - - OPTKEYR: - OPTKEYR: [0, 0xFFFFFFFF] - - SR: - EOP: - _read: - NoEvent: [0, "No EOP event occurred"] - Event: [1, "An EOP event occurred"] - _write: - Reset: [1, "Reset EOP event"] - WRPRTERR: - _read: - NoError: [0, "No write protection error occurred"] - Error: [1, "A write protection error occurred"] - _write: - Reset: [1, "Reset write protection error"] - PGERR: - _read: - NoError: [0, "No programming error occurred"] - Error: [1, "A programming error occurred"] - _write: - Reset: [1, "Reset programming error"] - BSY: - _read: - Inactive: [0, "No write/erase operation is in progress"] - Active: [1, "No write/erase operation is in progress"] - - CR: - OBL_LAUNCH: - Inactive: [0, "Force option byte loading inactive"] - Active: [1, "Force option byte loading active"] - EOPIE: - Disabled: [0, "End of operation interrupt disabled"] - Enabled: [1, "End of operation interrupt enabled"] - ERRIE: - Disabled: [0, "Error interrupt generation disabled"] - Enabled: [1, "Error interrupt generation enabled"] - OPTWRE: - Disabled: [0, "Option byte write enabled"] - Enabled: [1, "Option byte write disabled"] - LOCK: - _read: - Unlocked: [0, "FLASH_CR register is unlocked"] - Locked: [1, "FLASH_CR register is locked"] - _write: - Lock: [1, "Lock the FLASH_CR register"] - STRT: - Start: [1, "Trigger an erase operation"] - OPTER: - OptionByteErase: [1, "Erase option byte activated"] - OPTPG: - OptionByteProgramming: [1, "Program option byte activated"] - MER: - MassErase: [1, "Erase activated for all user sectors"] - PER: - PageErase: [1, "Erase activated for selected page"] - PG: - Program: [1, "Flash programming activated"] - - AR: - FAR: [0, 0xFFFFFFFF] - - OBR: - Data1: [0, 0xFF] - Data0: [0, 0xFF] - VDDA_MONITOR: - Disabled: [0, "VDDA power supply supervisor disabled"] - Enabled: [1, "VDDA power supply supervisor enabled"] - nBOOT1: - Disabled: [0, "Together with BOOT0, select the device boot mode"] - Enabled: [1, "Together with BOOT0, select the device boot mode"] - nRST_STDBY: - Reset: [0, "Reset generated when entering Standby mode"] - NoReset: [1, "No reset generated"] - nRST_STOP: - Reset: [0, "Reset generated when entering Stop mode"] - NoReset: [1, "No reset generated"] - WDG_SW: - Hardware: [0, "Hardware watchdog"] - Software: [1, "Software watchdog"] - RDPRT: - Level0: [0, "Level 0"] - Level1: [1, "Level 1"] - Level2: [3, "Level 2"] - OPTERR: - OptionByteError: [1, "The loaded option byte and its complement do not match"] - - WRPR: - WRP: [0, 0xFFFFFFFF] diff --git a/peripherals/flash/flash_f3_obr_sram_parity_check.yaml b/peripherals/flash/flash_f3_obr_sram_parity_check.yaml deleted file mode 100644 index 622492dcd..000000000 --- a/peripherals/flash/flash_f3_obr_sram_parity_check.yaml +++ /dev/null @@ -1,6 +0,0 @@ -FLASH: - OBR: - # Only avaliable for f302, f303 and f37x - SRAM_PARITY_CHECK: - Disabled: [0, "RAM parity check disabled"] - Enabled: [1, "RAM parity check enabled"] diff --git a/peripherals/flash/flash_f3_obr_vdd_monitor.yaml b/peripherals/flash/flash_f3_obr_vdd_monitor.yaml deleted file mode 100644 index d5e1b16c6..000000000 --- a/peripherals/flash/flash_f3_obr_vdd_monitor.yaml +++ /dev/null @@ -1,6 +0,0 @@ -FLASH: - OBR: - # This flag does only exist for stm32f37x devices - SDADC12_VDD_MONITOR: - Disabled: [0, "VDDSD12 monitoring disabled"] - Enabled: [1, "VDDSD12 monitoring enabled"] diff --git a/peripherals/flash/flash_l0.yaml b/peripherals/flash/flash_l0.yaml deleted file mode 100644 index 447da0922..000000000 --- a/peripherals/flash/flash_l0.yaml +++ /dev/null @@ -1,144 +0,0 @@ -# This FLASH is used on the STM32L0 families. - -"FLASH": - ACR: - PRE_READ: - Disabled: [0, "The pre-read is disabled"] - Enabled: [1, "The pre-read is enabled"] - DISAB_BUF: - Enabled: [0, "The buffers are enabled"] - Disabled: [1, "The buffers are disabled"] - RUN_PD: - NVMIdleMode: [0, "When the device is in Run mode, the NVM is in Idle mode"] - NVMPwrDownMode: [1, "When the device is in Run mode, the NVM is in power-down mode"] - SLEEP_PD: - NVMIdleMode: [0, "When the device is in Sleep mode, the NVM is in Idle mode"] - NVMPwrDownMode: [1, "When the device is in Sleep mode, the NVM is in power-down mode"] - PRFTEN: - Disabled: [0, "Prefetch is disabled"] - Enabled: [1, "Prefetch is enabled"] - LATENCY: - WS0: [0, "Zero wait state is used to read a word in the NVM"] - WS1: [1, "One wait state is used to read a word in the NVM"] - PECR: - OBL_LAUNCH: - _read: - Complete: [0, "Option byte loaded"] - NotComplete: [1, "Option byte loading to be done"] - _write: - Reload: [1, "Reload option byte"] - ERRIE: - Disabled: [0, "Error interrupt disable"] - Enabled: [1, "Error interrupt enable"] - EOPIE: - Disabled: [0, "End of program interrupt disable"] - Enabled: [1, "End of program interrupt enable"] - PARALLELBANK: - Disabled: [0, "Parallel bank mode disabled"] - Enabled: [1, "Parallel bank mode enabled"] - FPRG: - Disabled: [0, "Half Page programming disabled"] - Enabled: [1, "Half Page programming enabled"] - ERASE: - NoErase: [0, "No erase operation requested"] - Erase: [1, "Erase operation requested"] - FIX: - AutoErase: [0, "An erase phase is automatically performed"] - PrelimErase: [1, "The program operation is always performed with a preliminary erase"] - DATA: - NotSelected: [0, "Data EEPROM not selected"] - Selected: [1, "Data memory selected"] - PROG: - NotSelected: [0, "The Flash program memory is not selected"] - Selected: [1, "The Flash program memory is selected"] - OPTLOCK: - Unlocked: [0, "The write and erase operations in the Option bytes area are disabled"] - Locked: [1, "The write and erase operations in the Option bytes area are enabled"] - PRGLOCK: - Unlocked: [0, "The write and erase operations in the Flash program memory are disabled"] - Locked: [1, "The write and erase operations in the Flash program memory are enabled"] - PELOCK: - Unlocked: [0, "The FLASH_PECR register is unlocked"] - Locked: [1, "The FLASH_PECR register is locked and no write/erase operation can start"] - PDKEYR: - PDKEYR: [0, 0xFFFFFFFF] - PEKEYR: - PEKEYR: [0, 0xFFFFFFFF] - PRGKEYR: - PRGKEYR: [0, 0xFFFFFFFF] - OPTKEYR: - OPTKEYR: [0, 0xFFFFFFFF] - SR: - FWWERR: - _read: - NoError: [0, "No write/erase operation aborted to perform a fetch"] - Error: [1, "A write/erase operation aborted to perform a fetch"] - _write: - Clear: [1, "Clear the flag"] - NOTZEROERR: - _read: - NoEvent: [0, "The write operation is done in an erased region or the memory interface can apply an erase before a write"] - Event: [1, "The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write"] - _write: - Clear: [1, "Clear the flag"] - RDERR: - _read: - NoError: [0, "No read protection error happened."] - Error: [1, "One read protection error happened"] - _write: - Clear: [1, "Clear the flag"] - OPTVERR: - _read: - NoError: [0, "No error happened during the Option bytes loading"] - Error: [1, "One or more errors happened during the Option bytes loading"] - _write: - Clear: [1, "Clear the flag"] - SIZERR: - _read: - NoError: [0, "No size error happened"] - Error: [1, "One size error happened"] - _write: - Clear: [1, "Clear the flag"] - PGAERR: - _read: - NoError: [0, "No alignment error happened"] - Error: [1, "One alignment error happened"] - _write: - Clear: [1, "Clear the flag"] - WRPERR: - _read: - NoError: [0, "No protection error happened"] - Error: [1, "One protection error happened"] - _write: - Clear: [1, "Clear the flag"] - READY: - NotReady: [0, "The NVM is not ready"] - Ready: [1, "The NVM is ready"] - ENDHV: - Active: [0, "High voltage is executing a write/erase operation in the NVM"] - Inactive: [1, "High voltage is off, no write/erase operation is ongoing"] - EOP: - NoEvent: [0, "No EOP operation occurred"] - Event: [1, "An EOP event occurred"] - BSY: - Inactive: [0, "No write/erase operation is in progress"] - Active: [1, "No write/erase operation is in progress"] - "OPTR": - BOR_LEV: - BOR_Off: [0, "This is the reset threshold level for the 1.45 V - 1.55 V voltage range (power-down only)"] - BOR_Level1: [1, "Reset threshold level for VBOR0 (around 1.8 V)"] - BOR_Level2: [2, "Reset threshold level for VBOR1 (around 2.0 V)"] - BOR_Level3: [3, "Reset threshold level for VBOR2 (around 2.5 V)"] - BOR_Level4: [4, "Reset threshold level for VBOR3 (around 2.7 V)"] - BOR_Level5: [5, "Reset threshold level for VBOR4 (around 3.0 V)"] - WPRMOD: - Disabled: [0, "PCROP disabled. The WRPROT bits are used as a write protection on a sector."] - Enabled: [1, "PCROP enabled. The WRPROT bits are used as a read protection on a sector."] - RDPROT: - Level0: [0xAA, "Level 0"] - Level1: [0, "Level 1"] - Level2: [0xCC, "Level 2"] - WRPROT1: - WRPROT1: [0, 0xFFFFFFFF] - WRPROT2: - WRPROT2: [0, 0xFFFF] \ No newline at end of file diff --git a/peripherals/flash/flash_v1.yaml b/peripherals/flash/flash_v1.yaml deleted file mode 100644 index 414e72c6b..000000000 --- a/peripherals/flash/flash_v1.yaml +++ /dev/null @@ -1,66 +0,0 @@ - -"FLASH": - ACR: - DCRST: - NotReset: [0, "Data cache is not reset"] - Reset: [1, "Data cache is reset"] - ICRST: - NotReset: [0, "Instruction cache is not reset"] - Reset: [1, "Instruction cache is reset"] - DCEN: - Disabled: [0, "Data cache is disabled"] - Enabled: [1, "Data cache is enabled"] - ICEN: - Disabled: [0, "Instruction cache is disabled"] - Enabled: [1, "Instruction cache is enabled"] - PRFTEN: - Disabled: [0, "Prefetch is disabled"] - Enabled: [1, "Prefetch is enabled"] - LATENCY: - WS0: [0, "0 wait states"] - WS1: [1, "1 wait states"] - WS2: [2, "2 wait states"] - WS3: [3, "3 wait states"] - WS4: [4, "4 wait states"] - WS5: [5, "5 wait states"] - WS6: [6, "6 wait states"] - WS7: [7, "7 wait states"] - WS8: [8, "8 wait states"] - WS9: [9, "9 wait states"] - WS10: [10, "10 wait states"] - WS11: [11, "11 wait states"] - WS12: [12, "12 wait states"] - WS13: [13, "13 wait states"] - WS14: [14, "14 wait states"] - WS15: [15, "15 wait states"] - - KEYR: - KEY: [0, 0xFFFFFFFF] - - OPTKEYR: - OPTKEY: [0, 0xFFFFFFFF] - - CR: - LOCK: - Unlocked: [0, "FLASH_CR register is unlocked"] - Locked: [1, "FLASH_CR register is locked"] - ERRIE: - Disabled: [0, "Error interrupt generation disabled"] - Enabled: [1, "Error interrupt generation enabled"] - EOPIE: - Disabled: [0, "End of operation interrupt disabled"] - Enabled: [1, "End of operation interrupt enabled"] - STRT: - Start: [1, "Trigger an erase operation"] - PSIZE: - PSIZE8: [0, "Program x8"] - PSIZE16: [1, "Program x16"] - PSIZE32: [2, "Program x32"] - PSIZE64: [3, "Program x64"] - SNB: [0, 11] # TODO: this depends on device - MER: - MassErase: [1, "Erase activated for all user sectors"] - SER: - SectorErase: [1, "Erase activated for selected sector"] - PG: - Program: [1, "Flash programming activated"] diff --git a/peripherals/flash/flash_v2.yaml b/peripherals/flash/flash_v2.yaml deleted file mode 100644 index 7edf5df19..000000000 --- a/peripherals/flash/flash_v2.yaml +++ /dev/null @@ -1,60 +0,0 @@ - -"FLASH": - ACR: - ARTRST: - NotReset: [0, "Accelerator is not reset"] - Reset: [1, "Accelerator is reset"] - ARTEN: - Disabled: [0, "ART Accelerator is disabled"] - Enabled: [1, "ART Accelerator is enabled"] - PRFTEN: - Disabled: [0, "Prefetch is disabled"] - Enabled: [1, "Prefetch is enabled"] - LATENCY: - WS0: [0, "0 wait states"] - WS1: [1, "1 wait states"] - WS2: [2, "2 wait states"] - WS3: [3, "3 wait states"] - WS4: [4, "4 wait states"] - WS5: [5, "5 wait states"] - WS6: [6, "6 wait states"] - WS7: [7, "7 wait states"] - WS8: [8, "8 wait states"] - WS9: [9, "9 wait states"] - WS10: [10, "10 wait states"] - WS11: [11, "11 wait states"] - WS12: [12, "12 wait states"] - WS13: [13, "13 wait states"] - WS14: [14, "14 wait states"] - WS15: [15, "15 wait states"] - - KEYR: - KEY: [0, 0xFFFFFFFF] - - OPTKEYR: - OPTKEYR: [0, 0xFFFFFFFF] - - CR: - LOCK: - Unlocked: [0, "FLASH_CR register is unlocked"] - Locked: [1, "FLASH_CR register is locked"] - ERRIE: - Disabled: [0, "Error interrupt generation disabled"] - Enabled: [1, "Error interrupt generation enabled"] - EOPIE: - Disabled: [0, "End of operation interrupt disabled"] - Enabled: [1, "End of operation interrupt enabled"] - STRT: - Start: [1, "Trigger an erase operation"] - PSIZE: - PSIZE8: [0, "Program x8"] - PSIZE16: [1, "Program x16"] - PSIZE32: [2, "Program x32"] - PSIZE64: [3, "Program x64"] - SNB: [0, 11] # TODO: this depends on device - MER: - MassErase: [1, "Erase activated for all user sectors"] - SER: - SectorErase: [1, "Erase activated for selected sector"] - PG: - Program: [1, "Flash programming activated"] diff --git a/peripherals/flash/flash_v2_dual_bank.yaml b/peripherals/flash/flash_v2_dual_bank.yaml deleted file mode 100644 index 1252d39a7..000000000 --- a/peripherals/flash/flash_v2_dual_bank.yaml +++ /dev/null @@ -1,62 +0,0 @@ - -"FLASH": - ACR: - ARTRST: - NotReset: [0, "Accelerator is not reset"] - Reset: [1, "Accelerator is reset"] - ARTEN: - Disabled: [0, "ART Accelerator is disabled"] - Enabled: [1, "ART Accelerator is enabled"] - PRFTEN: - Disabled: [0, "Prefetch is disabled"] - Enabled: [1, "Prefetch is enabled"] - LATENCY: - WS0: [0, "0 wait states"] - WS1: [1, "1 wait states"] - WS2: [2, "2 wait states"] - WS3: [3, "3 wait states"] - WS4: [4, "4 wait states"] - WS5: [5, "5 wait states"] - WS6: [6, "6 wait states"] - WS7: [7, "7 wait states"] - WS8: [8, "8 wait states"] - WS9: [9, "9 wait states"] - WS10: [10, "10 wait states"] - WS11: [11, "11 wait states"] - WS12: [12, "12 wait states"] - WS13: [13, "13 wait states"] - WS14: [14, "14 wait states"] - WS15: [15, "15 wait states"] - - KEYR: - KEY: [0, 0xFFFFFFFF] - - OPTKEYR: - OPTKEYR: [0, 0xFFFFFFFF] - - CR: - LOCK: - Unlocked: [0, "FLASH_CR register is unlocked"] - Locked: [1, "FLASH_CR register is locked"] - ERRIE: - Disabled: [0, "Error interrupt generation disabled"] - Enabled: [1, "Error interrupt generation enabled"] - EOPIE: - Disabled: [0, "End of operation interrupt disabled"] - Enabled: [1, "End of operation interrupt enabled"] - STRT: - Start: [1, "Trigger an erase operation"] - PSIZE: - PSIZE8: [0, "Program x8"] - PSIZE16: [1, "Program x16"] - PSIZE32: [2, "Program x32"] - PSIZE64: [3, "Program x64"] - SNB: [0, 11] # TODO: this depends on device - MER1: - MassErase: [1, "Erase activated for all user sectors or bank 1 in dual bank mode"] - MER2: - MassErase: [1, "Erase activated for bank 2 in dual bank mode"] - SER: - SectorErase: [1, "Erase activated for selected sector"] - PG: - Program: [1, "Flash programming activated"] diff --git a/peripherals/fsmc/fsmc_nand.yaml b/peripherals/fsmc/fsmc_nand.yaml deleted file mode 100644 index ab9d93a55..000000000 --- a/peripherals/fsmc/fsmc_nand.yaml +++ /dev/null @@ -1,63 +0,0 @@ -"FMC,FSMC": - "PCR,PCR?": - ECCPS: - Bytes256: [0, "ECC page size 256 bytes"] - Bytes512: [1, "ECC page size 512 bytes"] - Bytes1024: [2, "ECC page size 1024 bytes"] - Bytes2048: [3, "ECC page size 2048 bytes"] - Bytes4096: [4, "ECC page size 4096 bytes"] - Bytes8192: [5, "ECC page size 8192 bytes"] - TAR: [0, 15] - TCLR: [0, 15] - ECCEN: - Disabled: [0, "ECC logic is disabled and reset"] - Enabled: [1, "ECC logic is enabled"] - PWID: - Bits8: [0, "External memory device width 8 bits"] - Bits16: [1, "External memory device width 16 bits"] - PTYP: - NANDFlash: [1, "NAND Flash"] - PBKEN: - Disabled: [0, "Corresponding memory bank is disabled"] - Enabled: [1, "Corresponding memory bank is enabled"] - PWAITEN: - Disabled: [0, "Wait feature disabled"] - Enabled: [1, "Wait feature enabled"] - - "SR,SR?": - FEMPT: - NotEmpty: [0, "FIFO not empty"] - Empty: [1, "FIFO empty"] - IFEN: - Disabled: [0, "Interrupt falling edge detection request disabled"] - Enabled: [1, "Interrupt falling edge detection request enabled"] - ILEN: - Disabled: [0, "Interrupt high-level detection request disabled"] - Enabled: [1, "Interrupt high-level detection request enabled"] - IREN: - Disabled: [0, "Interrupt rising edge detection request disabled"] - Enabled: [1, "Interrupt rising edge detection request enabled"] - IFS: - DidNotOccur: [0, "Interrupt falling edge did not occur"] - Occurred: [1, "Interrupt falling edge occurred"] - ILS: - DidNotOccur: [0, "Interrupt high-level did not occur"] - Occurred: [1, "Interrupt high-level occurred"] - IRS: - DidNotOccur: [0, "Interrupt rising edge did not occur"] - Occurred: [1, "Interrupt rising edge occurred"] - - "PMEM,PMEM?": - MEMHIZ: [0, 254] - MEMHOLD: [1, 254] - MEMWAIT: [1, 254] - MEMSET: [0, 254] - - "PATT,PATT?": - ATTHIZ: [0, 254] - ATTHOLD: [1, 254] - ATTWAIT: [1, 254] - ATTSET: [0, 254] - - "ECCR,ECCR?": - ECC: [0, 0xFFFFFFFF] diff --git a/peripherals/fsmc/fsmc_sd.yaml b/peripherals/fsmc/fsmc_sd.yaml deleted file mode 100644 index ab2dcc54f..000000000 --- a/peripherals/fsmc/fsmc_sd.yaml +++ /dev/null @@ -1,82 +0,0 @@ -# FMC as used in STM32F7 - -"FMC,FSMC": - "SDCR?": - RPIPE: - NoDelay: [0, "No clock cycle delay"] - Clocks1: [1, "One clock cycle delay"] - Clocks2: [2, "Two clock cycles delay"] - RBURST: - Disabled: [0, "Single read requests are not managed as bursts"] - Enabled: [1, "Single read requests are always managed as bursts"] - SDCLK: - Disabled: [0, "SDCLK clock disabled"] - Div2: [2, "SDCLK period = 2 x HCLK period"] - Div3: [3, "SDCLK period = 3 x HCLK period"] - WP: - Disabled: [0, "Write accesses allowed"] - Enabled: [1, "Write accesses ignored"] - CAS: - Clocks1: [1, "1 cycle"] - Clocks2: [2, "2 cycles"] - Clocks3: [3, "3 cycles"] - NB: - NB2: [0, "Two internal Banks"] - NB4: [1, "Four internal Banks"] - MWID: - Bits8: [0, "Memory data bus width 8 bits"] - Bits16: [1, "Memory data bus width 16 bits"] - Bits32: [2, "Memory data bus width 32 bits"] - NR: - Bits11: [0, "11 bits"] - Bits12: [1, "12 bits"] - Bits13: [2, "13 bits"] - NC: - Bits8: [0, "8 bits"] - Bits9: [1, "9 bits"] - Bits10: [2, "10 bits"] - Bits11: [3, "11 bits"] - - "SDTR?": - TRCD: [0, 15] - TRP: [0, 15] - TWR: [0, 15] - TRC: [0, 15] - TRAS: [0, 15] - TXSR: [0, 15] - TMRD: [0, 15] - - SDCMR: - MRD: [0, 8191] - NRFS: [0, 15] - CTB?: - NotIssued: [0, "Command not issued to SDRAM Bank 1"] - Issued: [1, "Command issued to SDRAM Bank 1"] - MODE: - Normal: [0, "Normal Mode"] - ClockConfigurationEnable: [1, "Clock Configuration Enable"] - PALL: [2, "PALL (All Bank Precharge) command"] - AutoRefreshCommand: [3, "Auto-refresh command"] - LoadModeRegister: [4, "Load Mode Resgier"] - SelfRefreshCommand: [5, "Self-refresh command"] - PowerDownCommand: [6, "Power-down command"] - - SDRTR: - REIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is generated if RE = 1"] - COUNT: [0, 8191] - CRE: - Clear: [1, "Refresh Error Flag is cleared"] - - SDSR: - BUSY: - NotBusy: [0, "SDRAM Controller is ready to accept a new request"] - Busy: [1, "SDRAM Controller is not ready to accept a new request"] - "MODES?": - Normal: [0, "Normal Mode"] - SelfRefresh: [1, "Self-refresh mode"] - PowerDown: [2, "Power-down mode"] - RE: - NoError: [0, "No refresh error has been detected"] - Error: [1, "A refresh error has been detected"] diff --git a/peripherals/fsmc/fsmc_sram.yaml b/peripherals/fsmc/fsmc_sram.yaml deleted file mode 100644 index 1f6f25afe..000000000 --- a/peripherals/fsmc/fsmc_sram.yaml +++ /dev/null @@ -1,73 +0,0 @@ -"FMC,FSMC": - "BCR?": - CBURSTRW: - Enabled: [1, "Write operations are performed in synchronous mode"] - Disabled: [0, "Write operations are always performed in asynchronous mode"] - CPSIZE: - NoBurstSplit: [0, "No burst split when crossing page boundary"] - Bytes128: [1, "128 bytes CRAM page size"] - Bytes256: [2, "256 bytes CRAM page size"] - Bytes512: [3, "512 bytes CRAM page size"] - Bytes1024: [4, "1024 bytes CRAM page size"] - ASYNCWAIT: - Disabled: [0, "Wait signal not used in asynchronous mode"] - Enabled: [1, "Wait signal used even in asynchronous mode"] - EXTMOD: - Disabled: [0, "Values inside the FMC_BWTR are not taken into account"] - Enabled: [1, "Values inside the FMC_BWTR are taken into account"] - WAITEN: - Disabled: [0, "Values inside the FMC_BWTR are taken into account"] - Enabled: [1, "NWAIT signal enabled"] - WREN: - Disabled: [0, "Write operations disabled for the bank by the FMC"] - Enabled: [1, "Write operations enabled for the bank by the FMC"] - WAITCFG: - BeforeWaitState: [0, "NWAIT signal is active one data cycle before wait state"] - DuringWaitState: [1, "NWAIT signal is active during wait state"] - WAITPOL: - ActiveLow: [0, "NWAIT active low"] - ActiveHigh: [1, "NWAIT active high"] - BURSTEN: - Disabled: [0, "Burst mode disabled"] - Enabled: [1, "Burst mode enabled"] - FACCEN: - Disabled: [0, "Corresponding NOR Flash memory access is disabled"] - Enabled: [1, "Corresponding NOR Flash memory access is enabled"] - MWID: - Bits8: [0, "Memory data bus width 8 bits"] - Bits16: [1, "Memory data bus width 16 bits"] - Bits32: [2, "Memory data bus width 32 bits"] - MTYP: - SRAM: [0, "SRAM memory type"] - PSRAM: [1, "PSRAM (CRAM) memory type"] - Flash: [2, "NOR Flash/OneNAND Flash"] - MUXEN: - Disabled: [0, "Address/Data non-multiplexed"] - Enabled: [1, "Address/Data multiplexed on databus"] - MBKEN: - Disabled: [0, "Corresponding memory bank is disabled"] - Enabled: [1, "Corresponding memory bank is enabled"] - - "BTR?": - ACCMOD: - A: [0, "Access mode A"] - B: [1, "Access mode B"] - C: [2, "Access mode C"] - D: [3, "Access mode D"] - DATLAT: [0, 15] - CLKDIV: [1, 15] - BUSTURN: [0, 15] - DATAST: [1, 255] - ADDHLD: [1, 15] - ADDSET: [0, 15] - - "BWTR?": - ACCMOD: - A: [0, "Access mode A"] - B: [1, "Access mode B"] - C: [2, "Access mode C"] - D: [3, "Access mode D"] - BUSTURN: [0, 15] - DATAST: [1, 255] - ADDHLD: [1, 15] - ADDSET: [0, 15] diff --git a/peripherals/fsmc/fsmc_wfdis.yaml b/peripherals/fsmc/fsmc_wfdis.yaml deleted file mode 100644 index ec7f49615..000000000 --- a/peripherals/fsmc/fsmc_wfdis.yaml +++ /dev/null @@ -1,8 +0,0 @@ -"FMC,FSMC": - "BCR1": - WFDIS: - Enabled: [0, "Write FIFO enabled"] - Disabled: [1, "Write FIFO disabled"] - CCLKEN: - Enabled: [1, "The FMC_CLK is only generated during the synchronous memory access (read/write transaction)"] - Disabled: [0, "The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set"] diff --git a/peripherals/fw/fw_l0.yaml b/peripherals/fw/fw_l0.yaml deleted file mode 100644 index 007e41561..000000000 --- a/peripherals/fw/fw_l0.yaml +++ /dev/null @@ -1,32 +0,0 @@ -# This FW is used on the STM32L0 families. - -"FW": - CSSA: - ADD: [0, 0xFFFF] - CSL: - LENG: [0, 0x3FFF] - NVDSSA: - ADD: [0, 0xFFFF] - NVDSL: - LENG: [0, 0x3FFF] - VDSSA: - ADD: [0, 0x3FF] - VDSL: - LENG: [0, 0x3FF] - CR: - VDE: - _write: - Reset: [0, "Resets volatile data execution bit"] - _read: - NotExecutable: [0, "Volatile data segment cannot be executed if VDS = 0"] - Executable: [1, "Volatile data segment is declared executable whatever VDS bit value"] - VDS: - _write: - Reset: [0, "Resets volatile data shared bit"] - _read: - NotShared: [0, "Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed"] - Shared: [1, "Volatile data segment is shared with non protected application code"] - FPA: - _write: - PreArmReset: [0, "Any code executed outside the protected segment when the Firewall is opened will generate a system reset"] - PreArmSet: [1, "Any code executed outside the protected segment will close the Firewall"] diff --git a/peripherals/gpio/gpio_f1.yaml b/peripherals/gpio/gpio_f1.yaml deleted file mode 100644 index 2ff0a5560..000000000 --- a/peripherals/gpio/gpio_f1.yaml +++ /dev/null @@ -1,56 +0,0 @@ -# This GPIO is used on the STM32F1 family. - -"GPIO*": - IDR: - "IDR*": - High: [1, "Input is logic high"] - Low: [0, "Input is logic low"] - ODR: - "ODR*": - High: [1, "Set output to logic high"] - Low: [0, "Set output to logic low"] - BSRR: - "BR*": - _write: - Reset: [1, "Resets the corresponding ODRx bit"] - "BS*": - _write: - Set: [1, "Sets the corresponding ODRx bit"] - BRR: - "BR*": - _write: - NoAction: [0, "No action on the corresponding ODx bit"] - Reset: [1, "Reset the ODx bit"] - LCKR: - "LCK[0123456789]": - Unlocked: [0, "Port configuration not locked"] - Locked: [1, "Port configuration locked"] - "LCK1[012345]": - Unlocked: [0, "Port configuration not locked"] - Locked: [1, "Port configuration locked"] - "LCKK": - NotActive: [0, "Port configuration lock key not active"] - Active: [1, "Port configuration lock key active"] - CRH: - CNF*: - PushPull: [0, "Analog mode / Push-Pull mode"] - OpenDrain: [1, "Floating input (reset state) / Open Drain-Mode"] - AltPushPull: [2, "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] - AltOpenDrain: [3, "Alternate Function Open-Drain Mode"] - MODE*: - Input: [0, "Input mode (reset state)"] - Output: [1, "Output mode 10 MHz"] - Output2: [2, "Output mode 2 MHz"] - Output50: [3, "Output mode 50 MHz"] - CRL: - CNF*: - PushPull: [0, "Analog mode / Push-Pull mode"] - OpenDrain: [1, "Floating input (reset state) / Open Drain-Mode"] - AltPushPull: [2, "Input with pull-up/pull-down / Alternate Function Push-Pull Mode"] - AltOpenDrain: [3, "Alternate Function Open-Drain Mode"] - MODE*: - Input: [0, "Input mode (reset state)"] - Output: [1, "Output mode 10 MHz"] - Output2: [2, "Output mode 2 MHz"] - Output50: [3, "Output mode 50 MHz"] - diff --git a/peripherals/gpio/gpio_l0.yaml b/peripherals/gpio/gpio_l0.yaml deleted file mode 100644 index cb46c0041..000000000 --- a/peripherals/gpio/gpio_l0.yaml +++ /dev/null @@ -1,67 +0,0 @@ -# This GPIO is used on the STM32L0 families. - -"GPIO*": - MODER: - "MODE*": - Input: [0, "Input mode (reset state)"] - Output: [1, "General purpose output mode"] - Alternate: [2, "Alternate function mode"] - Analog: [3, "Analog mode"] - OTYPER: - "OT*": - PushPull: [0, "Output push-pull (reset state)"] - OpenDrain: [1, "Output open-drain"] - OSPEEDR: - "OSPEED*": - LowSpeed: [0, "Low speed"] - MediumSpeed: [1, "Medium speed"] - HighSpeed: [2, "High speed"] - VeryHighSpeed: [3, "Very high speed"] - PUPDR: - "PUPD*": - Floating: [0, "No pull-up, pull-down"] - PullUp: [1, "Pull-up"] - PullDown: [2, "Pull-down"] - IDR: - "ID*": - High: [1, "Input is logic high"] - Low: [0, "Input is logic low"] - ODR: - "OD*": - High: [1, "Set output to logic high"] - Low: [0, "Set output to logic low"] - BSRR: - "BR*": - _write: - Reset: [1, "Resets the corresponding ODx bit"] - "BS*": - _write: - Set: [1, "Sets the corresponding ODx bit"] - LCKR: - "LCK[0123456789]": - Unlocked: [0, "Port configuration not locked"] - Locked: [1, "Port configuration locked"] - "LCK1[012345]": - Unlocked: [0, "Port configuration not locked"] - Locked: [1, "Port configuration locked"] - "LCKK": - NotActive: [0, "Port configuration lock key not active"] - Active: [1, "Port configuration lock key active"] - "AFR[LH]": - "AFSEL*": - AF0: [0, "AF0"] - AF1: [1, "AF1"] - AF2: [2, "AF2"] - AF3: [3, "AF3"] - AF4: [4, "AF4"] - AF5: [5, "AF5"] - AF6: [6, "AF6"] - AF7: [7, "AF7"] - AF8: [8, "AF8"] - AF9: [9, "AF9"] - AF10: [10, "AF10"] - AF11: [11, "AF11"] - AF12: [12, "AF12"] - AF13: [13, "AF13"] - AF14: [14, "AF14"] - AF15: [15, "AF15"] diff --git a/peripherals/gpio/gpio_v2.yaml b/peripherals/gpio/gpio_v2.yaml deleted file mode 100644 index d649e93f0..000000000 --- a/peripherals/gpio/gpio_v2.yaml +++ /dev/null @@ -1,16 +0,0 @@ -# This GPIO is used on the STM32F0, F3, F4, and F7 families. - -_include: - - gpio_v2_common.yaml - -"GPIO*": - LCKR: - "LCK[0123456789]": - Unlocked: [0, "Port configuration not locked"] - Locked: [1, "Port configuration locked"] - "LCK1[012345]": - Unlocked: [0, "Port configuration not locked"] - Locked: [1, "Port configuration locked"] - "LCKK": - NotActive: [0, "Port configuration lock key not active"] - Active: [1, "Port configuration lock key active"] diff --git a/peripherals/gpio/gpio_v2_common.yaml b/peripherals/gpio/gpio_v2_common.yaml deleted file mode 100644 index c0608a1fb..000000000 --- a/peripherals/gpio/gpio_v2_common.yaml +++ /dev/null @@ -1,55 +0,0 @@ -"GPIO*": - MODER: - "MODER*": - Input: [0, "Input mode (reset state)"] - Output: [1, "General purpose output mode"] - Alternate: [2, "Alternate function mode"] - Analog: [3, "Analog mode"] - OTYPER: - "OT*": - PushPull: [0, "Output push-pull (reset state)"] - OpenDrain: [1, "Output open-drain"] - OSPEEDR: - "OSPEEDR*": - LowSpeed: [0, "Low speed"] - MediumSpeed: [1, "Medium speed"] - HighSpeed: [2, "High speed"] - VeryHighSpeed: [3, "Very high speed"] - PUPDR: - "PUPDR*": - Floating: [0, "No pull-up, pull-down"] - PullUp: [1, "Pull-up"] - PullDown: [2, "Pull-down"] - IDR: - "IDR*": - High: [1, "Input is logic high"] - Low: [0, "Input is logic low"] - ODR: - "ODR*": - High: [1, "Set output to logic high"] - Low: [0, "Set output to logic low"] - BSRR: - "BR*": - _write: - Reset: [1, "Resets the corresponding ODRx bit"] - "BS*": - _write: - Set: [1, "Sets the corresponding ODRx bit"] - "AFR[LH]": - "AFR*": - AF0: [0, "AF0"] - AF1: [1, "AF1"] - AF2: [2, "AF2"] - AF3: [3, "AF3"] - AF4: [4, "AF4"] - AF5: [5, "AF5"] - AF6: [6, "AF6"] - AF7: [7, "AF7"] - AF8: [8, "AF8"] - AF9: [9, "AF9"] - AF10: [10, "AF10"] - AF11: [11, "AF11"] - AF12: [12, "AF12"] - AF13: [13, "AF13"] - AF14: [14, "AF14"] - AF15: [15, "AF15"] diff --git a/peripherals/gpio/gpio_v2_f373.yaml b/peripherals/gpio/gpio_v2_f373.yaml deleted file mode 100644 index ef7872df7..000000000 --- a/peripherals/gpio/gpio_v2_f373.yaml +++ /dev/null @@ -1,16 +0,0 @@ -# This GPIO is used on the STM32F373 and STM32F3x8 families. - -_include: - - gpio_v2_common.yaml - -"GPIO[ABD]": - LCKR: - "LCK[0123456789]": - Unlocked: [0, "Port configuration not locked"] - Locked: [1, "Port configuration locked"] - "LCK1[012345]": - Unlocked: [0, "Port configuration not locked"] - Locked: [1, "Port configuration locked"] - "LCKK": - NotActive: [0, "Port configuration lock key not active"] - Active: [1, "Port configuration lock key active"] diff --git a/peripherals/gpio/gpio_with_brr.yaml b/peripherals/gpio/gpio_with_brr.yaml deleted file mode 100644 index a53acce6d..000000000 --- a/peripherals/gpio/gpio_with_brr.yaml +++ /dev/null @@ -1,12 +0,0 @@ -# Some GPIO appear to have BRR registers - -"GPIO*": - BRR: - "BR[0123456789]": - _write: - NoAction: [0, "No action on the corresponding ODx bit"] - Reset: [1, "Reset the ODx bit"] - "BR1[012345]": - _write: - NoAction: [0, "No action on the corresponding ODx bit"] - Reset: [1, "Reset the ODx bit"] diff --git a/peripherals/hrtim/hrtim.yaml b/peripherals/hrtim/hrtim.yaml deleted file mode 100644 index 635e11993..000000000 --- a/peripherals/hrtim/hrtim.yaml +++ /dev/null @@ -1,721 +0,0 @@ -# HRTIM as found on STM32F3x4 and STM32H7 - -HRTIM_Common: - CR1: - "AD?USRC": - Master: [0, "ADC trigger update from master timer"] - TimerA: [1, "ADC trigger update from timer A"] - TimerB: [2, "ADC trigger update from timer B"] - TimerC: [3, "ADC trigger update from timer C"] - TimerD: [4, "ADC trigger update from timer D"] - TimerE: [5, "ADC trigger update from timer E"] - "T?UDIS,MUDIS": - Enabled: [0, "Timer update enabled"] - Disabled: [1, "Timer update disabled"] - CR2: - "T?RST,MRST": - Reset: [1, "Reset timer"] - "T?SWU,MSWU": - Update: [1, "Force immediate update"] - ISR: - BMPER: - _read: - NoEvent: [0, "No burst mode period interrupt occurred"] - Event: [1, "Burst mode period interrupt occured"] - _write: - Clear: [1, "Clear burst mode period interrupt"] - DLLRDY: - _read: - NoEvent: [0, "No DLL calibration ready interrupt occurred"] - Event: [1, "DLL calibration ready interrupt occurred"] - _write: - Clear: [1, "Clear DLL calibration interrupt"] - "SYSFLT,FLT?": - _read: - NoEvent: [0, "No fault interrupt occurred"] - Event: [1, "Fault interrupt occurred"] - _write: - Clear: [1, "Clear fault interrupt"] - ICR: - BMPERC: - Clear: [1, "Clears BMPER flag"] - DLLRDYC: - Clear: [1, "Clears DLL ready flag"] - "FLT?C": - Clear: [1, "Clears FLTx flag"] - SYSFLTC: - Clear: [1, "Clears SYSFLT flag"] - IER: - BMPERIE: - Disabled: [0, "Burst mode period interrupt disabled"] - Enabled: [1, "Burst mode period interrupt enabled"] - DLLRDYIE: - Disabled: [0, "DLL ready interrupt disabled"] - Enabled: [1, "DLL Ready interrupt enabled"] - "SYSFLTIE,FLT?IE": - Disabled: [0, "Fault interrupt disabled"] - Enabled: [1, "Fault interrupt enabled"] - OENR: - "T[ABCDE][12]OEN": - _read: - Disabled: [0, "Output disabled"] - Enabled: [1, "Output enabled"] - _write: - Enable: [1, "Enable output"] - ODISR: - "T[ABCDE][12]ODIS": - Disable: [1, "Disable output"] - ODSR: - "T[ABCDE][12]ODS": - Idle: [0, "Output disabled in idle state"] - Fault: [1, "Output disabled in fault state"] - BMCR: - BMSTAT: - _read: - Normal: [0, "Normal operation"] - Burst: [1, "Burst operation ongoing"] - _write: - Cancel: [0, "Terminate burst mode"] - "T[ABCDE]BM,MTBM": - Normal: [0, "Counter clock is maintained and timer operates normally"] - Stopped: [1, "Counter clock is stopped and counter is reset"] - BMPREN: - Disabled: [0, "Preload disabled: the write access is directly done into active registers"] - Enabled: [1, "Preload enabled: the write access is done into preload registers"] - BMPRSC: - Div1: [0, "Clock not divided"] - Div2: [1, "Division by 2"] - Div4: [2, "Division by 4"] - Div8: [3, "Division by 8"] - Div16: [4, "Division by 16"] - Div32: [5, "Division by 32"] - Div64: [6, "Division by 64"] - Div128: [7, "Division by 128"] - Div256: [8, "Division by 256"] - Div512: [9, "Division by 512"] - Div1024: [10, "Division by 1024"] - Div2048: [11, "Division by 2048"] - Div4096: [12, "Division by 4096"] - Div8192: [13, "Division by 8192"] - Div16384: [14, "Division by 16384"] - Div32768: [15, "Division by 32768"] - BMCLK: - Master: [0, "Master timer reset/roll-over"] - TimerA: [1, "Timer A counter reset/roll-over"] - TimerB: [2, "Timer B counter reset/roll-over"] - TimerC: [3, "Timer C counter reset/roll-over"] - TimerD: [4, "Timer D counter reset/roll-over"] - TimerE: [5, "Timer E counter reset/roll-over"] - Event1: [6, "On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock"] - Event2: [7, "On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock"] - Event3: [8, "On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock"] - Event4: [9, "On-chip Event 4 (BMClk[4]), acting as a burst mode counter clock"] - Clock: [10, "Prescaled f_HRTIM clock (as per BMPRSC[3:0] setting"] - BMOM: - SingleShot: [0, "Single-shot mode"] - Continuous: [1, "Continuous operation"] - BME: - Disabled: [0, "Burst mode disabled"] - Enabled: [1, "Burst mode enabled"] - BMTRGR: - OCHPEV: - NoEffect: [0, "Rising edge on an on-chip event has no effect"] - Trigger: [1, "Rising edge on an on-chip event triggers a burst mode entry"] - "EEV[78]": - NoEffect: [0, "External event X has no effect"] - Trigger: [1, "External event X triggers a burst mode entry"] - "TDEEV8,TAEEV7": - NoEffect: [0, "Timer X period following external event Y has no effect"] - Trigger: [1, "Timer X period following external event Y triggers a burst mode entry"] - NoEffect: [0, "has no effect"] - Trigger: [1, "triggers a burst mode entry"] - "T[ABCDE]CMP[12]": - NoEffect: [0, "Timer X compare Y event has no effect"] - Trigger: [1, "Timer X compare Y event triggers a burst mode entry"] - "T[ABCDE]REP": - NoEffect: [0, "Timer X repetition event has no effect"] - Trigger: [1, "Timer X repetition event triggers a burst mode entry"] - "T[ABCDE]RST": - NoEffect: [0, "Timer X reset/roll-over event has no effect"] - Trigger: [1, "Timer X reset/roll-over event triggers a burst mode entry"] - "MSTCMP[1234]": - NoEffect: [0, "Master timer compare X event has no effect"] - Trigger: [1, "Master timer compare X event triggers a burst mode entry"] - "MSTREP": - NoEffect: [0, "Master timer repetition event has no effect"] - Trigger: [1, "Master timer repetition event triggers a burst mode entry"] - "MSTRST": - NoEffect: [0, "Master timer reset/roll-over event has no effect"] - Trigger: [1, "Master timer reset/roll-over event triggers a burst mode entry"] - "SW": - NoEffect: [0, "No effect"] - Trigger: [1, "Trigger immediate burst mode operation"] - BMCMPR: - BMCMP: [0, 0xFFFF] - BMPER: - BMPER: [0, 0xFFFF] - EECR1: - "EE*FAST": - Resynchronized: [0, "External event is re-synchronised by the HRTIM logic before acting on outputs"] - Asynchronous: [1, "External event is acting asynchronously on outputs (low-latency mode)"] - "EECR[12]": - "EE*SNS": - Active: [0, "On active level defined by EExPOL bit"] - Rising: [1, "Rising edge"] - Falling: [2, "Falling edge"] - Both: [3, "Both edges"] - "EE*POL": - ActiveHigh: [0, "External event is active high"] - ActiveLow: [1, "External event is active low"] - "EE*SRC": - Src1: [0, "Source 1"] - Src2: [1, "Source 2"] - Src3: [2, "Source 3"] - Src4: [3, "Source 4"] - EECR3: - EEVSD: - Div1: [0, "f_EEVS=f_HRTIM"] - Div2: [1, "f_EEVS=f_HRTIM/2"] - Div4: [2, "f_EEVS=f_HRTIM/4"] - Div8: [3, "f_EEVS=f_HRTIM/8"] - "EE*F": - Disabled: [0, "Filter disabled"] - Div1_N2: [1, "f_SAMPLING=f_HRTIM, N=2"] - Div1_N4: [2, "f_SAMPLING=f_HRTIM, N=4"] - Div1_N8: [3, "f_SAMPLING=f_HRTIM, N=8"] - Div2_N6: [4, "f_SAMPLING=f_HRTIM/2, N=6"] - Div2_N8: [5, "f_SAMPLING=f_HRTIM/2, N=8"] - Div4_N6: [6, "f_SAMPLING=f_HRTIM/4, N=6"] - Div4_N8: [7, "f_SAMPLING=f_HRTIM/4, N=8"] - Div8_N6: [8, "f_SAMPLING=f_HRTIM/8, N=6"] - Div8_N8: [9, "f_SAMPLING=f_HRTIM/8, N=8"] - Div16_N5: [10, "f_SAMPLING=f_HRTIM/16, N=5"] - Div16_N6: [11, "f_SAMPLING=f_HRTIM/16, N=6"] - Div16_N8: [12, "f_SAMPLING=f_HRTIM/16, N=8"] - Div32_N5: [13, "f_SAMPLING=f_HRTIM/32, N=5"] - Div32_N6: [14, "f_SAMPLING=f_HRTIM/32, N=6"] - Div32_N8: [15, "f_SAMPLING=f_HRTIM/32, N=8"] - "ADC[1234]R": - "AD*RST": - Disabled: [0, "No generation of ADC trigger on timer reset and roll-over"] - Enabled: [1, "Generation of ADC trigger on timer reset and roll-over"] - "AD*PER": - Disabled: [0, "No generation of ADC trigger on timer period event"] - Enabled: [1, "Generation of ADC trigger on timer period event"] - "AD*T*C[234]": - Disabled: [0, "No generation of ADC trigger on timer compare event"] - Enabled: [1, "Generation of ADC trigger on timer compare event"] - "AD*EV*": - Disabled: [0, "No generation of ADC trigger on external event"] - Enabled: [1, "Generation of ADC trigger on external event"] - "AD*MC*": - Disabled: [0, "No generation of ADC trigger on master compare event"] - Enabled: [1, "Generation of ADC trigger on master compare event"] - DLLCR: - CALRTE: - Millis7_3: [0, "1048576*t_HRTIM (7.3ms)"] - Micros910: [1, "131072*t_HRTIM (910µs)"] - Micros114: [2, "16384*t_HRTIM (114µs)"] - Micros14: [3, "2048*t_HRTIM (14µs)"] - CALEN: - Disabled: [0, "Periodic calibration disabled"] - Enabled: [1, "Calibration is performed periodically, as per CALRTE setting"] - CAL: - Start: [1, "Calibration start"] - "FLTINR[12]": - "FLT[12345]LCK": - _read: - Unlocked: [0, "Fault bits are read/write"] - Locked: [1, "Fault bits are read-only"] - _write: - Lock: [1, "Lock corresponding fault bits"] - "FLT[12345]F": - Disabled: [0, "No filter, FLTx acts asynchronously"] - Div1_N2: [1, "f_SAMPLING=f_HRTIM, N=2"] - Div1_N4: [2, "f_SAMPLING=f_HRTIM, N=4"] - Div1_N8: [3, "f_SAMPLING=f_HRTIM, N=8"] - Div2_N6: [4, "f_SAMPLING=f_HRTIM/2, N=6"] - Div2_N8: [5, "f_SAMPLING=f_HRTIM/2, N=8"] - Div4_N6: [6, "f_SAMPLING=f_HRTIM/4, N=6"] - Div4_N8: [7, "f_SAMPLING=f_HRTIM/4, N=8"] - Div8_N6: [8, "f_SAMPLING=f_HRTIM/8, N=6"] - Div8_N8: [9, "f_SAMPLING=f_HRTIM/8, N=8"] - Div16_N5: [10, "f_SAMPLING=f_HRTIM/16, N=5"] - Div16_N6: [11, "f_SAMPLING=f_HRTIM/16, N=6"] - Div16_N8: [12, "f_SAMPLING=f_HRTIM/16, N=8"] - Div32_N5: [13, "f_SAMPLING=f_HRTIM/32, N=5"] - Div32_N6: [14, "f_SAMPLING=f_HRTIM/32, N=6"] - Div32_N8: [15, "f_SAMPLING=f_HRTIM/32, N=8"] - "FLT[12345]SRC": - Input: [0, "Fault input is FLTx input pin"] - Internal: [1, "Fault input is FLTn_Int signal"] - "FLT[12345]P": - ActiveLow: [0, "Fault input is active low"] - ActiveHigh: [1, "Fault input is active high"] - "FLT[12345]E": - Disabled: [0, "Fault input disabled"] - Enabled: [1, "Fault input enabled"] - FLTINR2: - FLTSD: - Div1: [0, "f_FLTS=f_HRTIM"] - Div2: [1, "f_FLTS=f_HRTIM/2"] - Div4: [2, "f_FLTS=f_HRTIM/4"] - Div8: [3, "f_FLTS=f_HRTIM/8"] - BDMUPR: - "M*": - NotUpdated: [0, "Register not updated by burst DMA access"] - Updated: [1, "Register updated by burst DMA access"] - "BDT?UPR": - "TIM*": - NotUpdated: [0, "Register not updated by burst DMA access"] - Updated: [1, "Register updated by burst DMA access"] - BDMADR: - BDMADR: [0, 0xFFFFFFFF] - -HRTIM_Master: - MCR: - BRSTDMA: - Independent: [0, "Update done independently from the DMA burst transfer completion"] - Completion: [1, "Update done when the DMA burst transfer is completed"] - Rollover: [2, "Update done on master timer roll-over following a DMA burst transfer completion"] - MREPU: - Disabled: [0, "Update on repetition disabled"] - Enabled: [1, "Update on repetition enabled"] - PREEN: - Disabled: [0, "Preload disabled: the write access is directly done into the active register"] - Enabled: [1, "Preload enabled: the write access is done into the preload register"] - DACSYNC: - Disabled: [0, "No DAC trigger generated"] - DACSync1: [1, "Trigger generated on DACSync1"] - DACSync2: [2, "Trigger generated on DACSync2"] - DACSync3: [3, "Trigger generated on DACSync3"] - "T[ABCDE]CEN": - Disabled: [0, "Timer counter disabled"] - Enabled: [1, "Timer counter enabled"] - MCEN: - Disabled: [0, "Master timer counter disabled"] - Enabled: [1, "Master timer counter enabled"] - SYNCSRC: - MasterStart: [0, "Master timer Start"] - MasterCompare1: [1, "Master timer Compare 1 event"] - TimerAStart: [2, "Timer A start/reset"] - TimerACompare1: [3, "Timer A Compare 1 event"] - SYNCOUT: - Disabled: [0, "Disabled"] - PositivePulse: [2, "Positive pulse on SCOUT output (16x f_HRTIM clock cycles)"] - NegativePulse: [3, "Negative pulse on SCOUT output (16x f_HRTIM clock cycles)"] - SYNCSTRTM: - Disabled: [0, "No effect on the master timer"] - Enabled: [1, "A synchroniation input event starts the master timer"] - SYNCRSTM: - Disabled: [0, "No effect on the master timer"] - Enabled: [1, "A synchroniation input event resets the master timer"] - SYNCIN: - Disabled: [0, "Disabled. HRTIM is not synchronized and runs in standalone mode"] - Internal: [2, "Internal event: the HRTIM is synchronized with the on-chip timer"] - External: [3, "External event: a positive pulse on HRTIM_SCIN input triggers the HRTIM"] - HALF: - Disabled: [0, "Half mode disabled"] - Enabled: [1, "Half mode enabled"] - RETRIG: - Disabled: [0, "The timer is not re-triggerable: a counter reset can be done only if the counter is stopped"] - Enabled: [1, "The timer is retriggerable: a counter reset is done whatever the counter state"] - CONT: - SingleShot: [0, "The timer operates in single-shot mode and stops when it reaches the MPER value"] - Continuous: [1, "The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value"] - CKPSC: [0, 7] - MISR: - MUPD: - NoEvent: [0, "No master update interrupt occurred"] - Event: [1, "Master update interrupt occurred"] - SYNC: - NoEvent: [0, "No sync input interrupt occurred"] - Event: [1, "Sync input interrupt occurred"] - MREP: - NoEvent: [0, "No master repetition interrupt occurred"] - Event: [1, "Master repetition interrupt occurred"] - "MCMP[1234]": - NoEvent: [0, "No master compare interrupt occurred"] - Event: [1, "Master compare interrupt occurred"] - MICR: - "M*C,SYNCC": - Clear: [1, "Clears flag in MISR register"] - MDIER: - "M*DE,SYNCDE": - Disabled: [0, "DMA request disabled"] - Enabled: [1, "DMA request enabled"] - "M*IE,SYNCIE": - Disabled: [0, "Interrupt disabled"] - Enabled: [1, "Interrupt enabled"] - MCNTR: - MCNT: [0, 0xFFFF] - MPER: - MPER: [0, 0xFFFF] - MREP: - MREP: [0, 0xFF] - "MCMP[1234]R": - "MCMP[1234]": [0, 0xFFFF] - -"HRTIM_TIM[ABCDE]": - "TIM[ABCDE]CR": - UPDGAT: - Independent: [0, "Update occurs independently from the DMA burst transfer"] - DMABurst: [1, "Update occurs when the DMA burst transfer is completed"] - DMABurst_Update: [2, "Update occurs on the update event following DMA burst transfer completion"] - Input1: [3, "Update occurs on a rising edge of HRTIM update enable input 1"] - Input2: [4, "Update occurs on a rising edge of HRTIM update enable input 2"] - Input3: [5, "Update occurs on a rising edge of HRTIM update enable input 3"] - Input1_Update: [6, "Update occurs on the update event following a rising edge of HRTIM update enable input 1"] - Input2_Update: [7, "Update occurs on the update event following a rising edge of HRTIM update enable input 2"] - Input3_Update: [8, "Update occurs on the update event following a rising edge of HRTIM update enable input 3"] - PREEN: - Disabled: [0, "Preload disabled: the write access is directly done into the active register"] - Enabled: [1, "Preload enabled: the write access is done into the preload register"] - DACSYNC: - Disabled: [0, "No DAC trigger generated"] - DACSync1: [1, "Trigger generated on DACSync1"] - DACSync2: [2, "Trigger generated on DACSync2"] - DACSync3: [3, "Trigger generated on DACSync3"] - MSTU: - Disabled: [0, "Update by master timer disabled"] - Enabled: [1, "Update by master timer enabled"] - "T[ABCDE]U": - Disabled: [0, "Update by timer x disabled"] - Enabled: [1, "Update by timer x enabled"] - "T?RSTU": - Disabled: [0, "Update by timer x reset/roll-over disabled"] - Enabled: [1, "Update by timer x reset/roll-over enabled"] - "T?REPU": - Disabled: [0, "Update by timer x repetition disabled"] - Enabled: [1, "Update by timer x repetition enabled"] - DELCMP4: - Standard: [0, "CMP4 register is always active (standard compare mode)"] - Capture2: [1, "CMP4 is recomputed and is active following a capture 2 event"] - Capture2_Compare1: [2, "CMP4 is recomputed and is active following a capture 2 event or a Compare 1 match"] - Capture_Compare3: [3, "CMP4 is recomputed and is active following a capture event or a Compare 3 match"] - DELCMP2: - Standard: [0, "CMP2 register is always active (standard compare mode)"] - Capture1: [1, "CMP2 is recomputed and is active following a capture 1 event"] - Capture1_Compare1: [2, "CMP2 is recomputed and is active following a capture 1 event or a Compare 1 match"] - Capture1_Compare3: [3, "CMP2 is recomputed and is active following a capture 1 event or a Compare 3 match"] - SYNCSTRTx: - Disabled: [0, "Synchronization event has no effect on Timer x"] - Start: [1, "Synchronization event starts Timer x"] - SYNCRSTx: - Disabled: [0, "Synchronization event has no effect on Timer x"] - Reset: [1, "Synchronization event resets Timer x"] - PSHPLL: - Disabled: [0, "Push-pull mode disabled"] - Enabled: [1, "Push-pull mode enabled"] - HALF: - Disabled: [0, "Half mode disabled"] - Enabled: [1, "Half mode enabled"] - RETRIG: - Disabled: [0, "The timer is not re-triggerable: a counter reset can be done only if the counter is stopped"] - Enabled: [1, "The timer is retriggerable: a counter reset is done whatever the counter state"] - CONT: - SingleShot: [0, "The timer operates in single-shot mode and stops when it reaches the MPER value"] - Continuous: [1, "The timer operates in continuous (free-running) mode and rolls over to zero when it reaches the MPER value"] - CKPSCx: [0, 7] - "TIM[ABCDE]ISR": - "O[12]CPY": - Inactive: [0, "Output is inactive"] - Active: [1, "Output is active"] - "O[12]STAT": - Inactive: [0, "Output was inactive"] - Active: [1, "Output was active"] - IPPSTAT: - Output1Active: [0, "Protection occurred when the output 1 was active and output 2 forced inactive"] - Output2Active: [1, "Protection occurred when the output 2 was active and output 1 forced inactive"] - CPPSTAT: - Output1Active: [0, "Signal applied on output 1 and output 2 forced inactive"] - Output2Active: [1, "Signal applied on output 2 and output 1 forced inactive"] - DLYPRT: - Inactive: [0, "Not in delayed idle or balanced idle mode"] - Active: [1, "Delayed idle or balanced idle mode entry"] - "RST": - NoEvent: [0, "No TIMx counter reset/roll-over interrupt occurred"] - Event: [1, "TIMx counter reset/roll-over interrupt occurred"] - "RSTx[12]": - NoEvent: [0, "No Tx output reset interrupt occurred"] - Event: [1, "Tx output reset interrupt occurred"] - "SETx[12]": - NoEvent: [0, "No Tx output set interrupt occurred"] - Event: [1, "Tx output set interrupt occurred"] - "CPT[12]": - NoEvent: [0, "No timer x capture reset interrupt occurred"] - Event: [1, "Timer x capture reset interrupt occurred"] - UPD: - NoEvent: [0, "No timer update interrupt occurred"] - Event: [1, "Timer update interrupt occurred"] - REP: - NoEvent: [0, "No timer repetition interrupt occurred"] - Event: [1, "Timer repetition interrupt occurred"] - "CMP[1234]": - NoEvent: [0, "No compare interrupt occurred"] - Event: [1, "Compare interrupt occurred"] - "TIM[ABCDE]ICR": - "*C": - Clear: [1, "Clears associated flag in ISR register"] - "TIM[ABCDE]DIER": - DLYPRTDE: - Disabled: [0, "Delayed protection DMA request disabled"] - Enabled: [1, "Delayed protection DMA request enabled"] - RSTDE: - Disabled: [0, "Timer x counter reset/roll-over DMA request disabled"] - Enabled: [1, "Timer x counter reset/roll-over DMA request enabled"] - "RSTx[12]DE": - Disabled: [0, "Tx output reset DMA request disabled"] - Enabled: [1, "Tx output reset DMA request enabled"] - "SETx[12]DE": - Disabled: [0, "Tx output set DMA request disabled"] - Enabled: [1, "Tx output set DMA request enabled"] - "CPT[12]DE": - Disabled: [0, "Capture DMA request disabled"] - Enabled: [1, "Capture DMA request enabled"] - UPDDE: - Disabled: [0, "Update DMA request disabled"] - Enabled: [1, "Update DMA request enabled"] - REPDE: - Disabled: [0, "Repetition DMA request disabled"] - Enabled: [1, "Repetition DMA request enabled"] - "CMP[1234]DE": - Disabled: [0, "Compare DMA request disabled"] - Enabled: [1, "Compare DMA request enabled"] - DLYPRTIE: - Disabled: [0, "Delayed protection interrupt disabled"] - Enabled: [1, "Delayed protection interrupt enabled"] - RSTIE: - Disabled: [0, "Timer x counter/reset roll-over interrupt disabled"] - Enabled: [1, "Timer x counter/reset roll-over interrupt enabled"] - "RSTx[12]IE": - Disabled: [0, "Tx output reset interrupt disabled"] - Enabled: [1, "Tx output reset interrupt enabled"] - "SETx[12]IE": - Disabled: [0, "Tx output set interrupt disabled"] - Enabled: [1, "Tx output set interrupt enabled"] - "CPT[12]IE": - Disabled: [0, "Capture interrupt disabled"] - Enabled: [1, "Capture interrupt enabled"] - UPDIE: - Disabled: [0, "Update interrupt disabled"] - Enabled: [1, "Update interrupt enabled"] - REPIE: - Disabled: [0, "Repetition interrupt disabled"] - Enabled: [1, "Repetition interrupt enabled"] - "CMP[1234]IE": - Disabled: [0, "Compare interrupt disabled"] - Enabled: [1, "Compare interrupt enabled"] - "CNT[ABCDE]R": - CNTx: [0, 0xFFFF] - "PER[ABCDE]R": - PERx: [0, 0xFFFF] - "REP[ABCDE]R": - REPx: [0, 0xFF] - "CMP[1234][ABCDE]R": - "CMP[1234]x": [0, 0xFFFF] - "CMP1C[ABCDE]R": - CMP1x: [0, 0xFFFF] - REPx: [0, 0xFF] - "CPT[12][ABCDE]R": - "CPT[12]x": [0, 0xFFFF] - "DT[ABCDE]R": - DTFLKx: - Unlocked: [0, "Deadtime falling value and sign is writable"] - Locked: [1, "Deadtime falling value and sign is read-only"] - DTFSLKx: - Unlocked: [0, "Deadtime falling sign is writable"] - Locked: [1, "Deadtime falling sign is read-only"] - SDTFx: - Positive: [0, "Positive deadtime on falling edge"] - Negative: [1, "Negative deadtime on falling edge"] - DTFx: [0, 0x1FF] - DTRLKx: - Unlocked: [0, "Deadtime rising value and sign is writable"] - Locked: [1, "Deadtime rising value and sign is read-only"] - DTRSLKx: - Unlocked: [0, "Deadtime rising sign is writable"] - Locked: [1, "Deadtime rising sign is read-only"] - DTPRSC: [0, 7] - SDTRx: - Positive: [0, "Positive deadtime on rising edge"] - Negative: [1, "Negative deadtime on rising edge"] - DTRx: [0, 0x1FF] - "SET[ABCDE][12]R": - UPDATE: - NoEffect: [0, "Register update event has no effect"] - SetActive: [1, "Register update event forces the output to its active state"] - "EXTEVNT*": - NoEffect: [0, "External event has no effect"] - SetActive: [1, "External event forces the output to its active state"] - "TIMEVNT*": - NoEffect: [0, "Timer event has no effect"] - SetActive: [1, "Timer event forces the output to its active state"] - "MSTCMP[1234]": - NoEffect: [0, "Master timer compare event has no effect"] - SetActive: [1, "Master timer compare event forces the output to its active state"] - MSTPER: - NoEffect: [0, "Master timer counter roll-over/reset has no effect"] - SetActive: [1, "Master timer counter roll-over/reset forces the output to its active state"] - "CMP[1234]": - NoEffect: [0, "Timer compare event has no effect"] - SetActive: [1, "Timer compare event forces the output to its active state"] - PER: - NoEffect: [0, "Timer period event has no effect"] - SetActive: [1, "Timer period event forces the output to its active state"] - RESYNC: - NoEffect: [0, "Timer reset event coming solely from software or SYNC input event has no effect"] - SetActive: [1, "Timer reset event coming solely from software or SYNC input event forces the output to its active state"] - SST: - NoEffect: [0, "No effect"] - SetActive: [1, "Force output to its active state"] - "RST[ABCDE][12]R": - UPDATE: - NoEffect: [0, "Register update event has no effect"] - SetInactive: [1, "Register update event forces the output to its inactive state"] - "EXTEVNT*": - NoEffect: [0, "External event has no effect"] - SetInactive: [1, "External event forces the output to its inactive state"] - "TIMEVNT*": - NoEffect: [0, "Timer event has no effect"] - SetInactive: [1, "Timer event forces the output to its inactive state"] - "MSTCMP[1234]": - NoEffect: [0, "Master timer compare event has no effect"] - SetInactive: [1, "Master timer compare event forces the output to its inactive state"] - MSTPER: - NoEffect: [0, "Master timer counter roll-over/reset has no effect"] - SetInactive: [1, "Master timer counter roll-over/reset forces the output to its inactive state"] - "CMP[1234]": - NoEffect: [0, "Timer compare event has no effect"] - SetInactive: [1, "Timer compare event forces the output to its inactive state"] - PER: - NoEffect: [0, "Timer period event has no effect"] - SetInactive: [1, "Timer period event forces the output to its inactive state"] - RESYNC: - NoEffect: [0, "Timer reset event coming solely from software or SYNC input event has no effect"] - SetInactive: [1, "Timer reset event coming solely from software or SYNC input event forces the output to its inactive state"] - SRT: - NoEffect: [0, "No effect"] - SetInactive: [1, "Force output to its inactive state"] - "EEF[ABCDE]R[12]": - "EE*FLTR": - Disabled: [0, "No filtering"] - BlankResetToCompare1: [1, "Blanking from counter reset/roll-over to Compare 1"] - BlankResetToCompare2: [2, "Blanking from counter reset/roll-over to Compare 2"] - BlankResetToCompare3: [3, "Blanking from counter reset/roll-over to Compare 3"] - BlankResetToCompare4: [4, "Blanking from counter reset/roll-over to Compare 4"] - BlankTIMFLTR1: [5, "Blanking from another timing unit: TIMFLTR1 source"] - BlankTIMFLTR2: [6, "Blanking from another timing unit: TIMFLTR2 source"] - BlankTIMFLTR3: [7, "Blanking from another timing unit: TIMFLTR3 source"] - BlankTIMFLTR4: [8, "Blanking from another timing unit: TIMFLTR4 source"] - BlankTIMFLTR5: [9, "Blanking from another timing unit: TIMFLTR5 source"] - BlankTIMFLTR6: [10, "Blanking from another timing unit: TIMFLTR6 source"] - BlankTIMFLTR7: [11, "Blanking from another timing unit: TIMFLTR7 source"] - BlankTIMFLTR8: [12, "Blanking from another timing unit: TIMFLTR8 source"] - WindowResetToCompare2: [13, "Windowing from counter reset/roll-over to compare 2"] - WindowResetToCompare3: [14, "Windowing from counter reset/roll-over to compare 3"] - WindowTIMWIN: [15, "Windowing from another timing unit: TIMWIN source"] - "EE*LTCH": - Disabled: [0, "Event is ignored if it happens during a blank, or passed through during a window"] - Enabled: [1, "Event is latched and delayed till the end of the blanking or windowing period"] - "RST[ABCDE]R": - "TIM[ABCDE]CMP[1234]": - NoEffect: [0, "Timer Y compare Z event has no effect"] - ResetCounter: [1, "Timer X counter is reset upon timer Y compare Z event"] - "EXTEVNT*": - NoEffect: [0, "External event Z has no effect"] - ResetCounter: [1, "Timer X counter is reset upon external event Z"] - "MSTCMP[1234]": - NoEffect: [0, "Master timer compare Z event has no effect"] - ResetCounter: [1, "Timer X counter is reset upon master timer compare Z event"] - MSTPER: - NoEffect: [0, "Master timer period event has no effect"] - ResetCounter: [1, "Timer X counter is reset upon master timer period event"] - "CMP[24]": - NoEffect: [0, "Timer X compare Z event has no effect"] - ResetCounter: [1, "Timer X counter is reset upon timer X compare Z event"] - UPDT: - NoEffect: [0, "Update event has no effect"] - ResetCounter: [1, "Timer X counter is reset upon update event"] - "CHP[ABCDE]R": - STRTPW: [0, 0xF] - CARDTY: [0, 7] - CARFRQ: [0, 0xF] - "CPT[12][ABCDE]CR": - "T[ABCDE]CMP[12]": - NoEffect: [0, "Timer X compare Y has no effect"] - TriggerCapture: [1, "Timer X compare Y triggers capture Z"] - "T[ABCDE]1RST": - NoEffect: [0, "Timer X output Y active to inactive transition has no effect"] - TriggerCapture: [1, "Timer X output Y active to inactive transition triggers capture Z"] - "T[ABCDE]1SET": - NoEffect: [0, "Timer X output Y inactive to active transition has no effect"] - TriggerCapture: [1, "Timer X output Y inactive to active transition triggers capture Z"] - "EXEV*CPT": - NoEffect: [0, "External event Y has no effect"] - TriggerCapture: [1, "External event Y triggers capture Z"] - UPDCPT: - NoEffect: [0, "Update event has no effect"] - TriggerCapture: [1, "Update event triggers capture Z"] - SWCPT: - NoEffect: [0, "No effect"] - TriggerCapture: [1, "Force capture Z"] - "OUT[ABCDE]R": - "DIDL[12]": - Disabled: [0, "The programmed idle state is applied immediately to the output"] - Enabled: [1, "Deadtime (inactive level) is inserted on output before entering the idle mode"] - "CHP[12]": - Disabled: [0, "Output signal not altered"] - Enabled: [1, "Output signal is chopped by a carrier signal"] - "FAULT[12]": - Disabled: [0, "No action: the output is not affected by the fault input and stays in run mode"] - SetActive: [1, "Output goes to active state after a fault event"] - SetInactive: [2, "Output goes to inactive state after a fault event"] - SetHighZ: [3, "Output goes to high-z state after a fault event"] - "IDLES[12]": - Inactive: [0, "Output idle state is inactive"] - Active: [1, "Output idle state is active"] - "IDLEM[12]": - NoEffect: [0, "No action: the output is not affected by the burst mode operation"] - SetIdle: [1, "The output is in idle state when requested by the burst mode controller"] - "POL[12]": - ActiveHigh: [0, "Positive polarity (output active high)"] - ActiveLow: [1, "Negative polarity (output active low)"] - DLYPRTEN: - Disabled: [0, "No action"] - Enabled: [1, "Delayed protection is enabled, as per DLYPRT bits"] - DTEN: - Disabled: [0, "Output 1 and 2 signals are independent"] - Enabled: [1, "Deadtime is inserted between output 1 and output 2"] - "FLT[ABCDE]R": - FLTLCK: - Unlocked: [0, "FLT1EN..FLT5EN bits are read/write"] - Locked: [1, "FLT1EN..FLT5EN bits are read only"] - "FLT[12345]EN": - Ignored: [0, "Fault input ignored"] - Active: [1, "Fault input is active and can disable HRTIM outputs"] - - -"HRTIM_TIM[ABC]": - "OUT[ABC]R": - DLYPRT: - Output1_EE6: [0, "Output 1 delayed idle on external event 6"] - Output2_EE6: [1, "Output 2 delayed idle on external event 6"] - Output1_2_EE6: [2, "Output 1 and 2 delayed idle on external event 6"] - Balanced_EE6: [3, "Balanced idle on external event 6"] - Output1_EE7: [4, "Output 1 delayed idle on external event 7"] - Output2_EE7: [5, "Output 2 delayed idle on external event 7"] - Output1_2_EE7: [6, "Output 1 and 2 delayed idle on external event 7"] - Balanced_EE7: [7, "Balanced idle on external event 7"] - -"HRTIM_TIM[DE]": - "OUT[DE]R": - DLYPRT: - Output1_EE8: [0, "Output 1 delayed idle on external event 8"] - Output2_EE8: [1, "Output 2 delayed idle on external event 8"] - Output1_2_EE8: [2, "Output 1 and 2 delayed idle on external event 8"] - Balanced_EE8: [3, "Balanced idle on external event 8"] - Output1_EE9: [4, "Output 1 delayed idle on external event 9"] - Output2_EE9: [5, "Output 2 delayed idle on external event 9"] - Output1_2_EE9: [6, "Output 1 and 2 delayed idle on external event 9"] - Balanced_EE9: [7, "Balanced idle on external event 9"] diff --git a/peripherals/i2c/i2c_v1.yaml b/peripherals/i2c/i2c_v1.yaml deleted file mode 100644 index fc3592e4e..000000000 --- a/peripherals/i2c/i2c_v1.yaml +++ /dev/null @@ -1,131 +0,0 @@ -# I2C peripheral used in STM32F1, F4, and L1 platforms - -"I2C*": - CR1: - SWRST: - NotReset: [0, "I2C peripheral not under reset"] - Reset: [1, "I2C peripheral under reset"] - ALERT: - Release: [0, "SMBA pin released high"] - Drive: [1, "SMBA pin driven low"] - PEC: - Disabled: [0, "No PEC transfer"] - Enabled: [1, "PEC transfer"] - POS: - Current: [0, "ACK bit controls the (N)ACK of the current byte being received"] - Next: [1, "ACK bit controls the (N)ACK of the next byte to be received"] - ACK: - NAK: [0, "No acknowledge returned"] - ACK: [1, "Acknowledge returned after a byte is received"] - STOP: - NoStop: [0, "No Stop generation"] - Stop: [1, "In master mode: stop generation after current byte/start, in slave mode: release SCL and SDA after current byte"] - START: - NoStart: [0, "No Start generation"] - Start: [1, "In master mode: repeated start generation, in slave mode: start generation when bus is free"] - NOSTRETCH: - Enabled: [0, "Clock stretching enabled"] - Disabled: [1, "Clock stretching disabled"] - ENGC: - Disabled: [0, "General call disabled"] - Enabled: [1, "General call enabled"] - ENPEC: - Disabled: [0, "PEC calculation disabled"] - Enabled: [1, "PEC calculation enabled"] - ENARP: - Disabled: [0, "ARP disabled"] - Enabled: [1, "ARP enabled"] - SMBTYPE: - Device: [0, "SMBus Device"] - Host: [1, "SMBus Host"] - SMBUS: - I2C: [0, "I2C Mode"] - SMBus: [1, "SMBus"] - PE: - Disabled: [0, "Peripheral disabled"] - Enabled: [1, "Peripheral enabled"] - - CR2: - LAST: - NotLast: [0, "Next DMA EOT is not the last transfer"] - Last: [1, "Next DMA EOT is the last transfer"] - DMAEN: - Disabled: [0, "DMA requests disabled"] - Enabled: [1, "DMA request enabled when TxE=1 or RxNE=1"] - ITBUFEN: - Disabled: [0, "TxE=1 or RxNE=1 does not generate any interrupt"] - Enabled: [1, "TxE=1 or RxNE=1 generates Event interrupt"] - ITEVTEN: - Disabled: [0, "Event interrupt disabled"] - Enabled: [1, "Event interrupt enabled"] - ITERREN: - Disabled: [0, "Error interrupt disabled"] - Enabled: [1, "Error interrupt enabled"] - FREQ: [2, 50] - - OAR1: - ADDMODE: - ADD7: [0, "7-bit slave address"] - ADD10: [1, "10-bit slave address"] - ADD: [0, 1023] - - OAR2: - ADD2: [0, 0x7F] - ENDUAL: - Single: [0, "Single addressing mode"] - Dual: [1, "Dual addressing mode"] - - DR: - DR: [0, 0xFF] - - SR1: - SMBALERT: - NoAlert: [0, "No SMBALERT occured"] - Alert: [1, "SMBALERT occurred"] - TIMEOUT: - NoTimeout: [0, "No Timeout error"] - Timeout: [1, "SCL remained LOW for 25 ms"] - PECERR: - NoError: [0, "no PEC error: receiver returns ACK after PEC reception (if ACK=1)"] - Error: [1, "PEC error: receiver returns NACK after PEC reception (whatever ACK)"] - OVR: - NoOverrun: [0, "No overrun/underrun occured"] - Overrun: [1, "Overrun/underrun occured"] - AF: - NoFailure: [0, "No acknowledge failure"] - Failure: [1, "Acknowledge failure"] - ARLO: - NoLost: [0, "No Arbitration Lost detected"] - Lost: [1, "Arbitration Lost detected"] - BERR: - NoError: [0, "No misplaced Start or Stop condition"] - Error: [1, "Misplaced Start or Stop condition"] - TxE: - NotEmpty: [0, "Data register not empty"] - Empty: [1, "Data register empty"] - RxNE: - Empty: [0, "Data register empty"] - NotEmpty: [1, "Data register not empty"] - STOPF: - NoStop: [0, "No Stop condition detected"] - Stop: [1, "Stop condition detected"] - BTF: - NotFinished: [0, "Data byte transfer not done"] - Finished: [1, "Data byte transfer successful"] - ADDR: - NotMatch: [0, "Adress mismatched or not received"] - Match: [1, "Received slave address matched with one of the enabled slave addresses"] - SB: - NoStart: [0, "No Start condition"] - Start: [1, "Start condition generated"] - CCR: - F_S: - Standard: [0, "Standard mode I2C"] - Fast: [1, "Fast mode I2C"] - DUTY: - Duty2_1: [0, "Duty cycle t_low/t_high = 2/1"] - Duty16_9: [1, "Duty cycle t_low/t_high = 16/9"] - CCR: [1, 0xFFF] - - TRISE: - TRISE: [0, 0x3F] diff --git a/peripherals/i2c/i2c_v2.yaml b/peripherals/i2c/i2c_v2.yaml deleted file mode 100644 index 29a77f46e..000000000 --- a/peripherals/i2c/i2c_v2.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# I2C peripheral used in STM32F0, F3, F7, L0, and L4 platforms - -"I2C*": - _include: - - i2c_v2_base.yaml - CR1: - WUPEN: - Disabled: [0, "Wakeup from Stop mode disabled"] - Enabled: [1, "Wakeup from Stop mode enabled"] diff --git a/peripherals/i2c/i2c_v2_base.yaml b/peripherals/i2c/i2c_v2_base.yaml deleted file mode 100644 index a3b0862f7..000000000 --- a/peripherals/i2c/i2c_v2_base.yaml +++ /dev/null @@ -1,220 +0,0 @@ -# Base for `i2c_v2.yaml`. - - CR1: - PECEN: - Disabled: [0, "PEC calculation disabled"] - Enabled: [1, "PEC calculation enabled"] - ALERTEN: - Disabled: [0, "In device mode (SMBHEN=Disabled) Releases SMBA pin high and Alert Response Address Header disabled (0001100x) followed by NACK. In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) not supported"] - Enabled: [1, "In device mode (SMBHEN=Disabled) Drives SMBA pin low and Alert Response Address Header enabled (0001100x) followed by ACK.In host mode (SMBHEN=Enabled) SMBus Alert pin (SMBA) supported"] - SMBDEN: - Disabled: [0, "Device default address disabled. Address 0b1100001x is NACKed"] - Enabled: [1, "Device default address enabled. Address 0b1100001x is ACKed"] - SMBHEN: - Disabled: [0, "Host address disabled. Address 0b0001000x is NACKed"] - Enabled: [1, "Host address enabled. Address 0b0001000x is ACKed"] - GCEN: - Disabled: [0, "General call disabled. Address 0b00000000 is NACKed"] - Enabled: [1, "General call enabled. Address 0b00000000 is ACKed"] - NOSTRETCH: - Enabled: [0, "Clock stretching enabled"] - Disabled: [1, "Clock stretching disabled"] - SBC: - Disabled: [0, "Slave byte control disabled"] - Enabled: [1, "Slave byte control enabled"] - RXDMAEN: - Disabled: [0, "DMA mode disabled for reception"] - Enabled: [1, "DMA mode enabled for reception"] - TXDMAEN: - Disabled: [0, "DMA mode disabled for transmission"] - Enabled: [1, "DMA mode enabled for transmission"] - ANFOFF: - Enabled: [0, "Analog noise filter enabled"] - Disabled: [1, "Analog noise filter disabled"] - DNF: - NoFilter: [0, "Digital filter disabled"] - Filter1: [1, "Digital filter enabled and filtering capability up to 1 tI2CCLK"] - Filter2: [2, "Digital filter enabled and filtering capability up to 2 tI2CCLK"] - Filter3: [3, "Digital filter enabled and filtering capability up to 3 tI2CCLK"] - Filter4: [4, "Digital filter enabled and filtering capability up to 4 tI2CCLK"] - Filter5: [5, "Digital filter enabled and filtering capability up to 5 tI2CCLK"] - Filter6: [6, "Digital filter enabled and filtering capability up to 6 tI2CCLK"] - Filter7: [7, "Digital filter enabled and filtering capability up to 7 tI2CCLK"] - Filter8: [8, "Digital filter enabled and filtering capability up to 8 tI2CCLK"] - Filter9: [9, "Digital filter enabled and filtering capability up to 9 tI2CCLK"] - Filter10: [10, "Digital filter enabled and filtering capability up to 10 tI2CCLK"] - Filter11: [11, "Digital filter enabled and filtering capability up to 11 tI2CCLK"] - Filter12: [12, "Digital filter enabled and filtering capability up to 12 tI2CCLK"] - Filter13: [13, "Digital filter enabled and filtering capability up to 13 tI2CCLK"] - Filter14: [14, "Digital filter enabled and filtering capability up to 14 tI2CCLK"] - Filter15: [15, "Digital filter enabled and filtering capability up to 15 tI2CCLK"] - ERRIE: - Disabled: [0, "Error detection interrupts disabled"] - Enabled: [1, "Error detection interrupts enabled"] - TCIE: - Disabled: [0, "Transfer Complete interrupt disabled"] - Enabled: [1, "Transfer Complete interrupt enabled"] - STOPIE: - Disabled: [0, "Stop detection (STOPF) interrupt disabled"] - Enabled: [1, "Stop detection (STOPF) interrupt enabled"] - NACKIE: - Disabled: [0, "Not acknowledge (NACKF) received interrupts disabled"] - Enabled: [1, "Not acknowledge (NACKF) received interrupts enabled"] - ADDRIE: - Disabled: [0, "Address match (ADDR) interrupts disabled"] - Enabled: [1, "Address match (ADDR) interrupts enabled"] - RXIE: - Disabled: [0, "Receive (RXNE) interrupt disabled"] - Enabled: [1, "Receive (RXNE) interrupt enabled"] - TXIE: - Disabled: [0, "Transmit (TXIS) interrupt disabled"] - Enabled: [1, "Transmit (TXIS) interrupt enabled"] - PE: - Disabled: [0, "Peripheral disabled"] - Enabled: [1, "Peripheral enabled"] - CR2: - PECBYTE: - NoPec: [0, "No PEC transfer"] - Pec: [1, "PEC transmission/reception is requested"] - AUTOEND: - Software: [0, "Software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low"] - Automatic: [1, "Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred"] - RELOAD: - Completed: [0, "The transfer is completed after the NBYTES data transfer (STOP or RESTART will follow)"] - NotCompleted: [1, "The transfer is not completed after the NBYTES data transfer (NBYTES will be reloaded)"] - NACK: - Ack: [0, "an ACK is sent after current received byte"] - Nack: [1, "a NACK is sent after current received byte"] - STOP: - NoStop: [0, "No Stop generation"] - Stop: [1, "Stop generation after current byte transfer"] - START: - NoStart: [0, "No Start generation"] - Start: [1, "Restart/Start generation"] - HEAD10R: - Complete: [0, "The master sends the complete 10 bit slave address read sequence"] - Partial: [1, "The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction"] - ADD10: - Bit7: [0, "The master operates in 7-bit addressing mode"] - Bit10: [1, "The master operates in 10-bit addressing mode"] - RD_WRN: - Write: [0, "Master requests a write transfer"] - Read: [1, "Master requests a read transfer"] - NBYTES: [0, 255] - SADD: [0, 1023] - OAR1: - OA1EN: - Disabled: [0, "Own address 1 disabled. The received slave address OA1 is NACKed"] - Enabled: [1, "Own address 1 enabled. The received slave address OA1 is ACKed"] - OA1MODE: - Bit7: [0, "Own address 1 is a 7-bit address"] - Bit10: [1, "Own address 1 is a 10-bit address"] - OA1: [0, 1023] - OAR2: - OA2EN: - Disabled: [0, "Own address 2 disabled. The received slave address OA2 is NACKed"] - Enabled: [1, "Own address 2 enabled. The received slave address OA2 is ACKed"] - OA2MSK: - NoMask: [0, "No mask"] - Mask1: [1, "OA2[1] is masked and don’t care. Only OA2[7:2] are compared"] - Mask2: [2, "OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared"] - Mask3: [3, "OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared"] - Mask4: [4, "OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared"] - Mask5: [5, "OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared"] - Mask6: [6, "OA2[6:1] are masked and don’t care. Only OA2[7] is compared."] - Mask7: [7, "OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged"] - OA2: [0, 127] - TIMINGR: - PRESC: [0, 15] - SCLDEL: [0, 15] - SDADEL: [0, 15] - SCLH: [0, 255] - SCLL: [0, 255] - TIMEOUTR: - TEXTEN: - Disabled: [0, "Extended clock timeout detection is disabled"] - Enabled: [1, "Extended clock timeout detection is enabled"] - TIMEOUTB: [0, 4095] - TIMOUTEN: - Disabled: [0, "SCL timeout detection is disabled"] - Enabled: [1, "SCL timeout detection is enabled"] - TIDLE: - Disabled: [0, "TIMEOUTA is used to detect SCL low timeout"] - Enabled: [1, "TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)"] - TIMEOUTA: [0, 4095] - ISR: - ADDCODE: [0, 127] - DIR: - Write: [0, "Write transfer, slave enters receiver mode"] - Read: [1, "Read transfer, slave enters transmitter mode"] - BUSY: - NotBusy: [0, "No communication is in progress on the bus"] - Busy: [1, "A communication is in progress on the bus"] - ALERT: - NoAlert: [0, "SMBA alert is not detected"] - Alert: [1, "SMBA alert event is detected on SMBA pin"] - TIMEOUT: - NoTimeout: [0, "No timeout occured"] - Timeout: [1, "Timeout occured"] - PECERR: - Match: [0, "Received PEC does match with PEC register"] - NoMatch: [1, "Received PEC does not match with PEC register"] - OVR: - NoOverrun: [0, "No overrun/underrun error occurs"] - Overrun: [1, "slave mode with NOSTRETCH=1, when an overrun/underrun error occurs"] - ARLO: - NotLost: [0, "No arbitration lost"] - Lost: [1, "Arbitration lost"] - BERR: - NoError: [0, "No bus error"] - Error: [1, "Misplaced Start and Stop condition is detected"] - TCR: - NotComplete: [0, "Transfer is not complete"] - Complete: [1, "NBYTES has been transfered"] - TC: - NotComplete: [0, "Transfer is not complete"] - Complete: [1, "NBYTES has been transfered"] - STOPF: - NoStop: [0, "No Stop condition detected"] - Stop: [1, "Stop condition detected"] - NACKF: - NoNack: [0, "No NACK has been received"] - Nack: [1, "NACK has been received"] - ADDR: - NotMatch: [0, "Adress mismatched or not received"] - Match: [1, "Received slave address matched with one of the enabled slave addresses"] - RXNE: - Empty: [0, "The RXDR register is empty"] - NotEmpty: [1, "Received data is copied into the RXDR register, and is ready to be read"] - TXIS: - NotEmpty: [0, "The TXDR register is not empty"] - Empty: [1, "The TXDR register is empty and the data to be transmitted must be written in the TXDR register"] - TXE: - NotEmpty: [0, "TXDR register not empty"] - Empty: [1, "TXDR register empty"] - - ICR: - ALERTCF: - Clear: [1, "Clears the ALERT flag in ISR register"] - TIMOUTCF: - Clear: [1, "Clears the TIMOUT flag in ISR register"] - PECCF: - Clear: [1, "Clears the PEC flag in ISR register"] - OVRCF: - Clear: [1, "Clears the OVR flag in ISR register"] - ARLOCF: - Clear: [1, "Clears the ARLO flag in ISR register"] - BERRCF: - Clear: [1, "Clears the BERR flag in ISR register"] - STOPCF: - Clear: [1, "Clears the STOP flag in ISR register"] - NACKCF: - Clear: [1, "Clears the NACK flag in ISR register"] - ADDRCF: - Clear: [1, "Clears the ADDR flag in ISR register"] - PECR: - PEC: [0, 255] - RXDR: - RXDATA: [0, 255] - TXDR: - TXDATA: [0, 255] diff --git a/peripherals/i2c/i2c_v2_fmp.yaml b/peripherals/i2c/i2c_v2_fmp.yaml deleted file mode 100644 index f0cd1c480..000000000 --- a/peripherals/i2c/i2c_v2_fmp.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# I2C peripheral used for FMPI2C1 device in stm32f4 families - -"FMPI2C*": - _include: - - i2c_v2_base.yaml diff --git a/peripherals/i2c/i2c_v2_without_wakeup.yaml b/peripherals/i2c/i2c_v2_without_wakeup.yaml deleted file mode 100644 index 1b9966b22..000000000 --- a/peripherals/i2c/i2c_v2_without_wakeup.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# I2C peripheral without wakup used in stm32f7x{2,3} families -# It has no CR1 WUPEN field. - -"I2C*": - _include: - - i2c_v2_base.yaml diff --git a/peripherals/iwdg/iwdg.yaml b/peripherals/iwdg/iwdg.yaml deleted file mode 100644 index 3235d87aa..000000000 --- a/peripherals/iwdg/iwdg.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# IWDG peripheral -# Present on F1, F2, F4 and L1 families. -# Base for `iwdg_with_window.yaml`. - -"IWDG,IWDG?": - KR: - KEY: - Enable: [21845, "Enable access to PR, RLR and WINR registers (0x5555)"] - Reset: [43690, "Reset the watchdog value (0xAAAA)"] - Start: [52428, "Start the watchdog (0xCCCC)"] - PR: - PR: - DivideBy4: [0, "Divider /4"] - DivideBy8: [1, "Divider /8"] - DivideBy16: [2, "Divider /16"] - DivideBy32: [3, "Divider /32"] - DivideBy64: [4, "Divider /64"] - DivideBy128: [5, "Divider /128"] - DivideBy256: [6, "Divider /256"] - DivideBy256bis: [7, "Divider /256"] - RLR: - RL: [0, 4095] diff --git a/peripherals/iwdg/iwdg_with_WINR.yaml b/peripherals/iwdg/iwdg_with_WINR.yaml deleted file mode 100644 index af520fb40..000000000 --- a/peripherals/iwdg/iwdg_with_WINR.yaml +++ /dev/null @@ -1,10 +0,0 @@ -# IWDG peripheral with window register -# Present on F0, F3, F7, H7, L0 and L4 families. -# Extend `iwdg.yaml`. - -_include: - - ./iwdg.yaml - -"IWDG,IWDG?": - WINR: - WIN: [0, 4095] diff --git a/peripherals/lptim/lptim_v1.yaml b/peripherals/lptim/lptim_v1.yaml deleted file mode 100644 index eef21bce8..000000000 --- a/peripherals/lptim/lptim_v1.yaml +++ /dev/null @@ -1,145 +0,0 @@ -# Low Power Timers used on at least L0, H7 - -LPTIM,LPTIM?: - ISR: - DOWN: - _read: - Set: [1, "Counter direction change up to down"] - UP: - _read: - Set: [1, "Counter direction change down to up"] - ARROK: - _read: - Set: [1, "Autoreload register update OK"] - CMPOK: - _read: - Set: [1, "Compare register update OK"] - EXTTRIG: - _read: - Set: [1, "External trigger edge event"] - ARRM: - _read: - Set: [1, "Autoreload match"] - CMPM: - _read: - Set: [1, "Compare match"] - ICR: - DOWNCF: - _write: - Clear: [1, "Direction change to down Clear Flag"] - UPCF: - _write: - Clear: [1, "Direction change to up Clear Flag"] - ARROKCF: - _write: - Clear: [1, "Autoreload register update OK Clear Flag"] - CMPOKCF: - _write: - Clear: [1, "Compare register update OK Clear Flag"] - EXTTRIGCF: - _write: - Clear: [1, "External trigger valid edge Clear Flag"] - ARRMCF: - _write: - Clear: [1, "Autoreload match Clear Flag"] - CMPMCF: - _write: - Clear: [1, "Compare match Clear Flag"] - IER: - DOWNIE: - Disabled: [0, "DOWN interrupt disabled"] - Enabled: [1, "DOWN interrupt enabled"] - UPIE: - Disabled: [0, "UP interrupt disabled"] - Enabled: [1, "UP interrupt enabled"] - ARROKIE: - Disabled: [0, "ARROK interrupt disabled"] - Enabled: [1, "ARROK interrupt enabled"] - CMPOKIE: - Disabled: [0, "CMPOK interrupt disabled"] - Enabled: [1, "CMPOK interrupt enabled"] - EXTTRIGIE: - Disabled: [0, "EXTTRIG interrupt disabled"] - Enabled: [1, "EXTTRIG interrupt enabled"] - ARRMIE: - Disabled: [0, "ARRM interrupt disabled"] - Enabled: [1, "ARRM interrupt enabled"] - CMPMIE: - Disabled: [0, "CMPM interrupt disabled"] - Enabled: [1, "CMPM interrupt enabled"] - CFGR: - ENC: - Disabled: [0, "Encoder mode disabled"] - Enabled: [1, "Encoder mode enabled"] - COUNTMODE: - Internal: [0, "The counter is incremented following each internal clock pulse"] - External: [1, "The counter is incremented following each valid clock pulse on the LPTIM external Input1"] - PRELOAD: - Immediate: [0, "Registers are updated after each APB bus write access"] - EndOfPeriod: [1, "Registers are updated at the end of the current LPTIM period"] - WAVPOL: - Positive: [0, "The LPTIM output reflects the compare results between LPTIM_ARR and LPTIM_CMP registers"] - Negative: [1, "The LPTIM output reflects the inverse of the compare results between LPTIM_ARR and LPTIM_CMP registers"] - WAVE: - Inactive: [0, "Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit)"] - Active: [1, "Activate the Set-once mode"] - TIMOUT: - Disabled: [0, "A trigger event arriving when the timer is already started will be ignored"] - Enabled: [1, "A trigger event arriving when the timer is already started will reset and restart the counter"] - TRIGEN: - SW: [0, "Software trigger (counting start is initiated by software)"] - RisingEdge: [1, "Rising edge is the active edge"] - FallingEdge: [2, "Falling edge is the active edge"] - BothEdges: [3, "Both edges are active edges"] - TRIGSEL: - Trig0: [0, "lptim_ext_trig0"] - Trig1: [1, "lptim_ext_trig1"] - Trig2: [2, "lptim_ext_trig2"] - Trig3: [3, "lptim_ext_trig3"] - Trig4: [4, "lptim_ext_trig4"] - Trig5: [5, "lptim_ext_trig5"] - Trig6: [6, "lptim_ext_trig6"] - Trig7: [7, "lptim_ext_trig7"] - PRESC: - Div1: [0, "/1"] - Div2: [1, "/2"] - Div4: [2, "/4"] - Div8: [3, "/8"] - Div16: [4, "/16"] - Div32: [5, "/32"] - Div64: [6, "/64"] - Div128: [7, "/128"] - TRGFLT: - Immediate: [0, "Any trigger active level change is considered as a valid trigger"] - Clocks2: [1, "Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger"] - Clocks4: [2, "Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger"] - Clocks8: [3, "Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger"] - CKFLT: - Immediate: [0, "Any external clock signal level change is considered as a valid transition"] - Clocks2: [1, "External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition"] - Clocks4: [2, "External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition"] - Clocks8: [3, "External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition"] - CKPOL: - RisingEdge: [0, "The rising edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 1 is active."] - FallingEdge: [1, "The falling edge is the active edge used for counting. If LPTIM is in encoder mode: Encoder sub-mode 2 is active."] - BothEdges: [2, "Both edges are active edge. If LPTIM is in encoder mode: Encoder sub-mode 3 is active."] - CKSEL: - Internal: [0, "LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)"] - External: [1, "LPTIM is clocked by an external clock source through the LPTIM external Input1"] - CR: - CNTSTRT: - _write: - Start: [1, "Timer start in Continuous mode"] - SNGSTRT: - _write: - Start: [1, "LPTIM start in Single mode"] - ENABLE: - Disabled: [0, "LPTIM is disabled"] - Enabled: [1, "LPTIM is enabled"] - CMP: - CMP: [0, 0xFFFF] - ARR: - ARR: [0, 0xFFFF] - CNT: - _read: - CNT: [0, 0xFFFF] diff --git a/peripherals/mpu/mpu_v1.yaml b/peripherals/mpu/mpu_v1.yaml deleted file mode 100644 index d9f1ef563..000000000 --- a/peripherals/mpu/mpu_v1.yaml +++ /dev/null @@ -1,46 +0,0 @@ -# Memory Protection Unit - Programming Manual PM0214 - -MPU: - TYPER: - _read: - IREGION: [0, 0xFF] - DREGION: [0, 0xFF] - SEPARATE: - _read: - Unified: [0, "Unified"] - Separate: [1, "Separate"] - CTRL: - PRIVDEFENA: - Disabled: [0, "Disables use of the default memory map"] - Enabled: [1, "Enables use of the default memory map as a background region for privileged software accesses"] - HFNMIENA: - Disabled: [0, "Disabled during hard fault, NMI, and FAULTMASK handlers"] - Enabled: [1, "Enabled during hard fault, NMI, and FAULTMASK handlers"] - ENABLE: - Disabled: [0, "MPU disabled"] - Enabled: [1, "MPU enabled"] - RNR: - REGION: [0, 0xFF] - RBAR: - ADDR: [0x7FFFFFF] - VALID: - _write: - Update: [1, "Updates the base address for the region specified in the REGION field"] - REGION: [0, 0xF] - RASR: - XN: - Enabled: [0, "Instruction fetches enabled"] - Disabled: [1, "Instruction fetches disabled"] - AP: [0, 0x7] - TEX: [0, 0x7] - S: [0, 1] - C: [0, 1] - B: [0, 1] - SRD: - Enabled: [0, "Corresponding sub-region is enabled"] - Disabled: [1, "corresponding sub-region is disabled"] - SIZE: [0, 0x1F] - ENABLE: - Disabled: [0, "Disable region"] - Enabled: [1, "Enable region"] - diff --git a/peripherals/opamp/opamp_f3.yaml b/peripherals/opamp/opamp_f3.yaml deleted file mode 100644 index 277b937dd..000000000 --- a/peripherals/opamp/opamp_f3.yaml +++ /dev/null @@ -1,62 +0,0 @@ -OPAMP: - OPAMP2_CSR: - OPAMP2EN: - Disabled: [0, "OPAMP2 is disabled"] - Enabled: [1, "OPAMP2 is enabled"] - FORCE_VP: - Normal: [0, "Normal operating mode"] - Calibration: [1, "Calibration mode. Non-inverting input connected to calibration reference"] - VP_SEL: - PB14: [1, "PB14 used as OPAMP2 non-inverting input"] - PB0: [2, "PB0 used as OPAMP2 non-inverting input"] - PA7: [3, "PA7 used as OPAMP2 non-inverting input"] - VM_SEL: - PC5: [0, "PC5 (VM0) used as OPAMP2 inverting input"] - PA5: [1, "PA5 (VM1) used as OPAMP2 inverting input"] - PGA: [2, "Resistor feedback output (PGA mode)"] - Follower: [3, "Follower mode"] - TCM_EN: - Disabled: [0, "Timer controlled mux disabled"] - Enabled: [1, "Timer controlled mux enabled"] - VMS_SEL: - PC5: [0, "PC5 (VM0) used as OPAMP2 inverting input when TCM_EN=1"] - PA5: [1, "PA5 (VM1) used as OPAMP2 inverting input when TCM_EN=1"] - VPS_SEL: - PB14: [1, "PB14 used as OPAMP2 non-inverting input when TCM_EN=1"] - PB0: [2, "PB0 used as OPAMP2 non-inverting input when TCM_EN=1"] - PA7: [3, "PA7 used as OPAMP2 non-inverting input when TCM_EN=1"] - CALON: - Disabled: [0, "Calibration mode disabled"] - Enabled: [1, "Calibration mode enabled"] - CALSEL: - Percent3_3: [0, "VREFOPAMP=3.3% VDDA"] - Percent10: [1, "VREFOPAMP=10% VDDA"] - Percent50: [2, "VREFOPAMP=50% VDDA"] - Percent90: [3, "VREFOPAMP=90% VDDA"] - PGA_GAIN: - Gain2: [0, "Gain 2"] - Gain4: [1, "Gain 4"] - Gain8: [2, "Gain 8"] - Gain16: [4, "Gain 16"] - Gain2_VM0: [8, "Gain 2, feedback connected to VM0"] - Gain4_VM0: [9, "Gain 4, feedback connected to VM0"] - Gain8_VM0: [10, "Gain 8, feedback connected to VM0"] - Gain16_VM0: [11, "Gain 16, feedback connected to VM0"] - Gain2_VM1: [12, "Gain 2, feedback connected to VM1"] - Gain4_VM1: [13, "Gain 4, feedback connected to VM1"] - Gain8_VM1: [14, "Gain 8, feedback connected to VM1"] - Gain16_VM1: [15, "Gain 16, feedback connected to VM1"] - USER_TRIM: - Disabled: [0, "User trimming disabled"] - Enabled: [1, "User trimming enabled"] - TRIMOFFSETP: [0, 31] - TRIMOFFSETN: [0, 31] - TSTREF: - Output: [0, "VREFOPAMP2 is output"] - NotOutput: [1, "VREFOPAMP2 is not output"] - OUTCAL: - Low: [0, "Non-inverting < inverting"] - High: [1, "Non-inverting > inverting"] - LOCK: - Unlocked: [0, "Comparator CSR bits are read-write"] - Locked: [1, "Comparator CSR bits are read-only"] diff --git a/peripherals/pwr/pwr_f7.yaml b/peripherals/pwr/pwr_f7.yaml deleted file mode 100644 index 4439989bf..000000000 --- a/peripherals/pwr/pwr_f7.yaml +++ /dev/null @@ -1,6 +0,0 @@ -PWR: - CR1: - VOS: - SCALE1: [3, "Scale 1 mode (reset value)"] - SCALE2: [2, "Scale 2 mode"] - SCALE3: [1, "Scale 3 mode"] \ No newline at end of file diff --git a/peripherals/pwr/pwr_l0.yaml b/peripherals/pwr/pwr_l0.yaml deleted file mode 100644 index 56e43c9cf..000000000 --- a/peripherals/pwr/pwr_l0.yaml +++ /dev/null @@ -1,80 +0,0 @@ -# Power Controller for L0 Family -_include: - - pwr_v1.yaml - -PWR: - CR: - LPRUN: - MAIN_MODE: [0, "Voltage regulator in Main mode in Low-power run mode"] - LOW_POWER_MODE: [1, "Voltage regulator in low-power mode in Low-power run mode"] - DS_EE_KOFF: - NVMWakeUp: [0, "NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set"] - NVMSleep: [1, "NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set)"] - VOS: - V1_8: [1, "1.8 V (range 1)"] - V1_5: [2, "1.5 V (range 2)"] - V1_2: [3, "1.2 V (range 3)"] - FWU: - Disabled: [0, "Low-power modes exit occurs only when VREFINT is ready"] - Enabled: [1, "VREFINT start up time is ignored when exiting low-power modes"] - ULP: - Enabled: [0, "VREFINT is on in low-power mode"] - Disabled: [1, "VREFINT is off in low-power mode"] - DBP: - Disabled: [0, "Access to RTC, RTC Backup and RCC CSR registers disabled"] - Enabled: [1, "Access to RTC, RTC Backup and RCC CSR registers enabled"] - PLS: - V1_9: [0, "1.9 V"] - V2_1: [1, "2.1 V"] - V2_3: [2, "2.3 V"] - V2_5: [3, "2.5 V"] - V2_7: [4, "2.7 V"] - V2_9: [5, "2.9 V"] - V3_1: [6, "3.1 V"] - External: [7, "External input analog voltage (Compare internally to VREFINT)"] - PVDE: - Disabled: [0, "PVD Disabled"] - Enabled: [1, "PVD Enabled"] - CSBF: - _write: - Clear: [1, "Clear the SBF Standby flag"] - CWUF: - _write: - Clear: [1, "Clear the WUF Wakeup flag after 2 system clock cycles"] - LPSDSR: - MAIN_MODE: [0, "Voltage regulator on during Deepsleep/Sleep/Low-power run mode"] - LOW_POWER_MODE: [1, "Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode"] - CSR: - EWUP3: - Disabled: [0, "WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode"] - Enabled: [1, "WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode)"] - EWUP2: - Disabled: [0, "WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode"] - Enabled: [1, "WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode)"] - EWUP1: - Disabled: [0, "WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode"] - Enabled: [1, "WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode)"] - REGLPF: - _read: - Ready: [0, "Regulator is ready in Main mode"] - NotReady: [1, "Regulator voltage is in low-power mode"] - VOSF: - _read: - Ready: [0, "Regulator is ready in the selected voltage range"] - NotReady: [1, "Regulator voltage output is changing to the required VOS level"] - VREFINTRDYF: - _read: - NotReady: [0, "VREFINT is OFF"] - Ready: [1, "VREFINT is ready"] - PVDO: - _read: - AboveThreshold: [0, "VDD is higher than the PVD threshold selected with the PLS[2:0] bits"] - BelowThreshold: [1, "VDD is lower than the PVD threshold selected with the PLS[2:0] bits"] - SBF: - _read: - NoStandbyEvent: [0, "Device has not been in Standby mode"] - StandbyEvent: [1, "Device has been in Standby mode"] - WUF: - _read: - NoWakeupEvent: [0, "No wakeup event occurred"] - WakeupEvent: [1, "A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)"] diff --git a/peripherals/pwr/pwr_v1.yaml b/peripherals/pwr/pwr_v1.yaml deleted file mode 100644 index c58152b59..000000000 --- a/peripherals/pwr/pwr_v1.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Power controller - -PWR: - CR: - PDDS: - STOP_MODE: [0, "Enter Stop mode when the CPU enters deepsleep"] - STANDBY_MODE: [1, "Enter Standby mode when the CPU enters deepsleep"] diff --git a/peripherals/pwr/pwr_v2.yaml b/peripherals/pwr/pwr_v2.yaml deleted file mode 100644 index 6c5f784db..000000000 --- a/peripherals/pwr/pwr_v2.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Power controller - -PWR: - CR1: - PDDS: - STOP_MODE: [0, "Enter Stop mode when the CPU enters deepsleep"] - STANDBY_MODE: [1, "Enter Standby mode when the CPU enters deepsleep"] diff --git a/peripherals/rcc/rcc_cfgr2_f107.yaml b/peripherals/rcc/rcc_cfgr2_f107.yaml deleted file mode 100644 index 2f3fc2b33..000000000 --- a/peripherals/rcc/rcc_cfgr2_f107.yaml +++ /dev/null @@ -1,21 +0,0 @@ -_include: - - ./rcc_cfgr2_prediv.yaml - -RCC: - CFGR2: - PLL?MUL: - Mul8: [6, "PLL clock entry x8"] - Mul9: [7, "PLL clock entry x9"] - Mul10: [8, "PLL clock entry x10"] - Mul11: [9, "PLL clock entry x11"] - Mul12: [10, "PLL clock entry x12"] - Mul13: [11, "PLL clock entry x13"] - Mul14: [12, "PLL clock entry x14"] - Mul16: [14, "PLL clock entry x16"] - Mul20: [15, "PLL clock entry x20"] - PREDIV1SRC: - HSE: [0, "HSE oscillator clock selected as PREDIV1 clock entry"] - PLL2: [1, "PLL2 selected as PREDIV1 clock entry"] - I2S?SRC: - SYSCLK: [0, "System clock (SYSCLK) selected as I2S clock entry"] - PLL3: [1, "PLL3 VCO clock selected as I2S clock entry"] diff --git a/peripherals/rcc/rcc_cfgr2_prediv.yaml b/peripherals/rcc/rcc_cfgr2_prediv.yaml deleted file mode 100644 index 29621dcad..000000000 --- a/peripherals/rcc/rcc_cfgr2_prediv.yaml +++ /dev/null @@ -1,19 +0,0 @@ -RCC: - CFGR2: - PREDIV,PREDIV[12]: - Div1: [0, "PREDIV input clock not divided"] - Div2: [1, "PREDIV input clock divided by 2"] - Div3: [2, "PREDIV input clock divided by 3"] - Div4: [3, "PREDIV input clock divided by 4"] - Div5: [4, "PREDIV input clock divided by 5"] - Div6: [5, "PREDIV input clock divided by 6"] - Div7: [6, "PREDIV input clock divided by 7"] - Div8: [7, "PREDIV input clock divided by 8"] - Div9: [8, "PREDIV input clock divided by 9"] - Div10: [9, "PREDIV input clock divided by 10"] - Div11: [10, "PREDIV input clock divided by 11"] - Div12: [11, "PREDIV input clock divided by 12"] - Div13: [12, "PREDIV input clock divided by 13"] - Div14: [13, "PREDIV input clock divided by 14"] - Div15: [14, "PREDIV input clock divided by 15"] - Div16: [15, "PREDIV input clock divided by 16"] diff --git a/peripherals/rcc/rcc_cfgr3_cecsw.yaml b/peripherals/rcc/rcc_cfgr3_cecsw.yaml deleted file mode 100644 index 873523d5b..000000000 --- a/peripherals/rcc/rcc_cfgr3_cecsw.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CFGR3: - CECSW: - HSI_Div244: [0, "HSI clock divided by 244 selected as CEC clock source"] - LSE: [1, "LSE clock selected as CEC clock source"] diff --git a/peripherals/rcc/rcc_cfgr_mcopre.yaml b/peripherals/rcc/rcc_cfgr_mcopre.yaml deleted file mode 100644 index f0c6dc326..000000000 --- a/peripherals/rcc/rcc_cfgr_mcopre.yaml +++ /dev/null @@ -1,11 +0,0 @@ -RCC: - CFGR: - MCOPRE: - Div1: [0, "MCO is divided by 1"] - Div2: [1, "MCO is divided by 2"] - Div4: [2, "MCO is divided by 4"] - Div8: [3, "MCO is divided by 8"] - Div16: [4, "MCO is divided by 16"] - Div32: [5, "MCO is divided by 32"] - Div64: [6, "MCO is divided by 64"] - Div128: [7, "MCO is divided by 128"] diff --git a/peripherals/rcc/rcc_cfgr_pllnodiv.yaml b/peripherals/rcc/rcc_cfgr_pllnodiv.yaml deleted file mode 100644 index 04d5af41d..000000000 --- a/peripherals/rcc/rcc_cfgr_pllnodiv.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CFGR: - PLLNODIV: - Div2: [0, "PLL is divided by 2 for MCO"] - Div1: [1, "PLL is not divided for MCO"] diff --git a/peripherals/rcc/rcc_common.yaml b/peripherals/rcc/rcc_common.yaml deleted file mode 100644 index 4d0c5edf7..000000000 --- a/peripherals/rcc/rcc_common.yaml +++ /dev/null @@ -1,107 +0,0 @@ -# Common bits of RCC peripheral - -RCC: - CR: - CSSON: - "Off": [0, "Clock security system disabled (clock detector OFF)"] - "On": [1, "Clock security system enable (clock detector ON if the HSE is ready, OFF if not)"] - HSEBYP: - NotBypassed: [0, "HSE crystal oscillator not bypassed"] - Bypassed: [1, "HSE crystal oscillator bypassed with external clock"] - HSICAL: [0, 255] - HSITRIM: [0, 31] - "*RDY": - _read: - NotReady: [0, "Clock not ready"] - Ready: [1, "Clock ready"] - HSION,HSEON,PLLON,PLLI2SON,PLLSAION: - "Off": [0, "Clock Off"] - "On": [1, "Clock On"] - CFGR: - PPRE*: - Div1: [0, "HCLK not divided"] # Same for [0, 8] - Div2: [4, "HCLK divided by 2"] - Div4: [5, "HCLK divided by 4"] - Div8: [6, "HCLK divided by 8"] - Div16: [7, "HCLK divided by 16"] - HPRE: - Div1: [0, "SYSCLK not divided"] # Same for [0, 7] - Div2: [8, "SYSCLK divided by 2"] - Div4: [9, "SYSCLK divided by 4"] - Div8: [10, "SYSCLK divided by 8"] - Div16: [11, "SYSCLK divided by 16"] - Div64: [12, "SYSCLK divided by 64"] - Div128: [13, "SYSCLK divided by 128"] - Div256: [14, "SYSCLK divided by 256"] - Div512: [15, "SYSCLK divided by 512"] - SWS: - _read: - HSI: [0, "HSE oscillator used as system clock"] - HSE: [1, "HSI oscillator used as system clock"] - PLL: [2, "PLL used as system clock"] - SW: - HSI: [0, "HSI selected as system clock"] - HSE: [1, "HSE selected as system clock"] - PLL: [2, "PLL selected as system clock"] - CIR: - CSSC: - _write: - Clear: [1, "Clear CSSF flag"] - "*RDYC": - _write: - Clear: [1, "Clear interrupt flag"] - "*RDYIE": - Disabled: [0, "Interrupt disabled"] - Enabled: [1, "Interrupt enabled"] - CSSF: - _read: - NotInterrupted: [0, "No clock security interrupt caused by HSE clock failure"] - Interrupted: [1, "Clock security interrupt caused by HSE clock failure"] - "*RDYF": - _read: - NotInterrupted: [0, "No clock ready interrupt"] - Interrupted: [1, "Clock ready interrupt"] - "A?B?RSTR,A?BRSTR": - "*RST": - Reset: [1, "Reset the selected module"] - "A?B?ENR,A?BENR": - "*EN": - Disabled: [0, "The selected clock is disabled"] - Enabled: [1, "The selected clock is enabled"] - BDCR: - BDRST: - Disabled: [0, "Reset not activated"] - Enabled: [1, "Reset the entire RTC domain"] - RTCEN: - Disabled: [0, "RTC clock disabled"] - Enabled: [1, "RTC clock enabled"] - RTCSEL: - NoClock: [0, "No clock"] - LSE: [1, "LSE oscillator clock used as RTC clock"] - LSI: [2, "LSI oscillator clock used as RTC clock"] - HSE: [3, "HSE oscillator clock divided by a prescaler used as RTC clock"] - LSEBYP: - NotBypassed: [0, "LSE crystal oscillator not bypassed"] - Bypassed: [1, "LSE crystal oscillator bypassed with external clock"] - LSERDY: - _read: - NotReady: [0, "LSE oscillator not ready"] - Ready: [1, "LSE oscillator ready"] - LSEON: - "Off": [0, "LSE oscillator Off"] - "On": [1, "LSE oscillator On"] - CSR: - "*RSTF": - _read: - NoReset: [0, "No reset has occured"] - Reset: [1, "A reset has occured"] - RMVF: - _write: - Clear: [1, "Clears the reset flag"] - LSIRDY: - _read: - NotReady: [0, "LSI oscillator not ready"] - Ready: [1, "LSI oscillator ready"] - LSION: - "Off": [0, "LSI oscillator Off"] - "On": [1, "LSI oscillator On"] diff --git a/peripherals/rcc/rcc_f0.yaml b/peripherals/rcc/rcc_f0.yaml deleted file mode 100644 index 8ed6ce8e9..000000000 --- a/peripherals/rcc/rcc_f0.yaml +++ /dev/null @@ -1,56 +0,0 @@ -# RCC peripheral -# Applicable to STM32F0 -# PLLSRC[0] available only on STM32F04x, STM32F07x and STM32F09x - -_include: - - ./rcc_f0_f1_f3_common.yaml - - ./rcc_f0_f3_common.yaml - - ./rcc_cfgr_mcopre.yaml - - ./rcc_cfgr_pllnodiv.yaml - - ./rcc_v2_bdcr_lsedrv.yaml - - ./rcc_cfgr2_prediv.yaml - -RCC: - CFGR: - _modify: - PLLXTPRE: - description: "HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning" - ADCPRE: - description: "APCPRE is deprecated. See ADC field in CFGR2 register." - - MCO: - HSI14: [1, "Internal RC 14 MHz (HSI14) oscillator clock selected"] - HSI48: [8, "Internal RC 48 MHz (HSI48) oscillator clock selected"] - SWS: - _read: - HSI48: [3, "HSI48 used as system clock (when avaiable)"] - SW: - HSI48: [3, "HSI48 selected as system clock (when available)"] - CFGR3: - _modify: - ADCSW: - description: "ADCSW is deprecated. See ADC field in CFGR2 register." - - USBSW: - PLLCLK: [1, "PLL clock selected as USB clock source"] - CR2: - HSI48CAL: [0, 255] - HSI48RDY: - _read: - NotReady: [0, "HSI48 oscillator ready"] - Ready: [1, "HSI48 oscillator ready"] - HSI48ON: - "Off": [0, "HSI48 oscillator off"] - "On": [1, "HSI48 oscillator on"] - HSI14CAL: [0, 255] - HSI14TRIM: [0, 31] - HSI14DIS: - Allow: [0, "ADC can turn on the HSI14 oscillator"] - Disallow: [1, "ADC can not turn on the HSI14 oscillator"] - HSI14RDY: - _read: - NotReady: [0, "HSI14 oscillator not ready"] - Ready: [1, "HSI14 oscillator ready"] - HSI14ON: - "Off": [0, "HSI14 oscillator off"] - "On": [1, "HSI14 oscillator on"] diff --git a/peripherals/rcc/rcc_f0_f1_f3_common.yaml b/peripherals/rcc/rcc_f0_f1_f3_common.yaml deleted file mode 100644 index 2d2d23ab5..000000000 --- a/peripherals/rcc/rcc_f0_f1_f3_common.yaml +++ /dev/null @@ -1,25 +0,0 @@ -_include: - - ./rcc_common.yaml - -RCC: - CFGR: - PLLMUL: - Mul2: [0, "PLL input clock x2"] - Mul3: [1, "PLL input clock x3"] - Mul4: [2, "PLL input clock x4"] - Mul5: [3, "PLL input clock x5"] - Mul6: [4, "PLL input clock x6"] - Mul7: [5, "PLL input clock x7"] - Mul8: [6, "PLL input clock x8"] - Mul9: [7, "PLL input clock x9"] - Mul10: [8, "PLL input clock x10"] - Mul11: [9, "PLL input clock x11"] - Mul12: [10, "PLL input clock x12"] - Mul13: [11, "PLL input clock x13"] - Mul14: [12, "PLL input clock x14"] - Mul15: [13, "PLL input clock x15"] - Mul16: [14, "PLL input clock x16"] - Mul16x: [15, "PLL input clock x16"] - PLLXTPRE: - Div1: [0, "HSE clock not divided"] - Div2: [1, "HSE clock divided by 2"] diff --git a/peripherals/rcc/rcc_f0_f3_common.yaml b/peripherals/rcc/rcc_f0_f3_common.yaml deleted file mode 100644 index 7f0e152dc..000000000 --- a/peripherals/rcc/rcc_f0_f3_common.yaml +++ /dev/null @@ -1,19 +0,0 @@ -RCC: - CFGR: - MCO: - NoMCO: [0, "MCO output disabled, no clock on MCO"] - LSI: [2, "Internal low speed (LSI) oscillator clock selected"] - LSE: [3, "External low speed (LSE) oscillator clock selected"] - SYSCLK: [4, "System clock selected"] - HSI: [5, "Internal RC 8 MHz (HSI) oscillator clock selected"] - HSE: [6, "External 4-32 MHz (HSE) oscillator clock selected"] - PLL: [7, "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"] - CFGR3: - "U*ART*SW": - PCLK: [0, "PCLK selected as USART clock source"] - SYSCLK: [1, "SYSCLK selected as USART clock source"] - LSE: [2, "LSE selected as USART clock source"] - HSI: [3, "HSI selected as USART clock source"] - "I2C*SW": - HSI: [0, "HSI clock selected as I2C clock source"] - SYSCLK: [1, "SYSCLK clock selected as I2C clock source"] diff --git a/peripherals/rcc/rcc_f0x0.yaml b/peripherals/rcc/rcc_f0x0.yaml deleted file mode 100644 index 7ce7af837..000000000 --- a/peripherals/rcc/rcc_f0x0.yaml +++ /dev/null @@ -1,8 +0,0 @@ -_include: - - rcc_f0.yaml - - rcc_pllsrc_1bit.yaml - -RCC: - CFGR3: - USBSW: - Disabled: [0, "USB clock disabled"] diff --git a/peripherals/rcc/rcc_f0x128.yaml b/peripherals/rcc/rcc_f0x128.yaml deleted file mode 100644 index b11e33aac..000000000 --- a/peripherals/rcc/rcc_f0x128.yaml +++ /dev/null @@ -1,12 +0,0 @@ -_include: - - rcc_f0.yaml - - rcc_pllsrc_2bit.yaml - - rcc_cfgr3_cecsw.yaml - -RCC: - CFGR: - PLLSRC: - HSI48_Div_PREDIV: [3, "HSI48 divided by PREDIV selected as PLL input clock"] - CFGR3: - USBSW: - HSI48: [0, "HSI48 selected as USB clock source"] diff --git a/peripherals/rcc/rcc_f1.yaml b/peripherals/rcc/rcc_f1.yaml deleted file mode 100644 index d6fd8ec7e..000000000 --- a/peripherals/rcc/rcc_f1.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# RCC peripheral -# Applicable to STM32F1 - -_include: - - ./rcc_f0_f1_f3_common.yaml - - ./rcc_pllsrc_1bit.yaml - -RCC: - CFGR: - MCO: - NoMCO: [0, "MCO output disabled, no clock on MCO"] - SYSCLK: [4, "System clock selected"] - HSI: [5, "HSI oscillator clock selected"] - HSE: [6, "HSE oscillator clock selected"] - PLL: [7, "PLL clock selected (divided by 1 or 2, depending en PLLNODIV)"] - ADCPRE: - Div2: [0, "PCLK2 divided by 2"] - Div4: [1, "PCLK2 divided by 4"] - Div6: [2, "PCLK2 divided by 8"] - Div8: [3, "PCLK2 divided by 16"] diff --git a/peripherals/rcc/rcc_f107.yaml b/peripherals/rcc/rcc_f107.yaml deleted file mode 100644 index e8b4ea9bd..000000000 --- a/peripherals/rcc/rcc_f107.yaml +++ /dev/null @@ -1,36 +0,0 @@ -# RCC peripheral -# Applicable to STM32F107 - -_include: - - ./rcc_common.yaml - - ./rcc_pllsrc_1bit.yaml - -RCC: - CFGR: - PLLMUL: - Mul4: [2, "PLL input clock x4"] - Mul5: [3, "PLL input clock x5"] - Mul6: [4, "PLL input clock x6"] - Mul7: [5, "PLL input clock x7"] - Mul8: [6, "PLL input clock x8"] - Mul9: [7, "PLL input clock x9"] - Mul6_5: [13, "PLL input clock x6.5"] - PLLXTPRE: - Div1: [0, "HSE clock not divided"] - Div2: [1, "HSE clock divided by 2"] - MCO: - NoMCO: [0, "MCO output disabled, no clock on MCO"] - SYSCLK: [4, "System clock selected"] - HSI: [5, "HSI oscillator clock selected"] - HSE: [6, "HSE oscillator clock selected"] - PLL: [7, "PLL clock divided by 2 selected"] - PLL2: [8, "PLL2 clock selected"] - PLL3: [9, "PLL3 clock divided by 2 selected"] - XT1: [10, "XT1 external 3-25 MHz oscillator clock selected (for Ethernet)"] - PLL3Ethernet: [11, "PLL3 clock selected (for Ethernet)"] - ADCPRE: - Div2: [0, "PCLK2 divided by 2"] - Div4: [1, "PCLK2 divided by 4"] - Div6: [2, "PCLK2 divided by 8"] - Div8: [3, "PCLK2 divided by 16"] - diff --git a/peripherals/rcc/rcc_f1_f3_usb.yaml b/peripherals/rcc/rcc_f1_f3_usb.yaml deleted file mode 100644 index 3a549bae0..000000000 --- a/peripherals/rcc/rcc_f1_f3_usb.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# RCC peripheral -# Applicable to STM32F103 and STMF107 - -RCC: - CFGR: - USBPRE,OTGFSPRE: - DIV1_5: [0, "PLL clock is divided by 1.5"] - DIV1: [1, "PLL clock is not divided"] diff --git a/peripherals/rcc/rcc_f3.yaml b/peripherals/rcc/rcc_f3.yaml deleted file mode 100644 index 1bc7fe95e..000000000 --- a/peripherals/rcc/rcc_f3.yaml +++ /dev/null @@ -1,31 +0,0 @@ -# RCC peripheral -# Applicable to STM32F3 - -_include: - - rcc_f0_f1_f3_common.yaml - - rcc_f0_f3_common.yaml - - rcc_cfgr_mcopre.yaml - - rcc_cfgr_pllnodiv.yaml - - rcc_v2_bdcr_lsedrv.yaml - - rcc_cfgr2_prediv.yaml - -RCC: - CFGR2: - "ADC*PRES": - NoClock: [0, "No clock"] # Same for [0, 15] - Div1: [16, "PLL clock not divided"] - Div2: [17, "PLL clock divided by 2"] - Div4: [18, "PLL clock divided by 4"] - Div6: [19, "PLL clock divided by 6"] - Div8: [20, "PLL clock divided by 8"] - Div10: [21, "PLL clock divided by 10"] - Div12: [22, "PLL clock divided by 12"] - Div16: [23, "PLL clock divided by 16"] - Div32: [24, "PLL clock divided by 32"] - Div64: [25, "PLL clock divided by 64"] - Div128: [26, "PLL clock divided by 128"] - Div256: [27, "PLL clock divided by 256"] # Same for [27, 31] - CFGR3: - "TIM*SW,HRTIM*SW": - PCLK2: [0, "PCLK2 clock (doubled frequency when prescaled)"] - PLL: [1, "PLL vco output (running up to 144 MHz)"] diff --git a/peripherals/rcc/rcc_f373.yaml b/peripherals/rcc/rcc_f373.yaml deleted file mode 100644 index 81c17fc56..000000000 --- a/peripherals/rcc/rcc_f373.yaml +++ /dev/null @@ -1,34 +0,0 @@ -# RCC peripheral -# Applicable to STM32F373 - -_include: - - rcc_f0_f1_f3_common.yaml - - rcc_f0_f3_common.yaml - - rcc_v2_bdcr_lsedrv.yaml - - rcc_cfgr2_prediv.yaml - - rcc_cfgr3_cecsw.yaml - -RCC: - CFGR: - ADCPRE: - Div2: [0, "PCLK divided by 2"] - Div4: [1, "PCLK divided by 4"] - Div6: [2, "PCLK divided by 6"] - Div8: [3, "PCLK divided by 8"] - SDPRE: - Div2: [0, "SYSCLK divided by 2"] # Same for [0, 16] - Div4: [17, "SYSCLK divided by 4"] - Div6: [18, "SYSCLK divided by 6"] - Div8: [19, "SYSCLK divided by 8"] - Div10: [20, "SYSCLK divided by 10"] - Div12: [21, "SYSCLK divided by 12"] - Div14: [22, "SYSCLK divided by 14"] - Div16: [23, "SYSCLK divided by 16"] - Div20: [24, "SYSCLK divided by 20"] - Div24: [25, "SYSCLK divided by 24"] - Div28: [26, "SYSCLK divided by 28"] - Div32: [27, "SYSCLK divided by 32"] - Div36: [28, "SYSCLK divided by 36"] - Div40: [29, "SYSCLK divided by 40"] - Div44: [30, "SYSCLK divided by 44"] - Div48: [31, "SYSCLK divided by 48"] diff --git a/peripherals/rcc/rcc_f3_i2s.yaml b/peripherals/rcc/rcc_f3_i2s.yaml deleted file mode 100644 index fb7ad9872..000000000 --- a/peripherals/rcc/rcc_f3_i2s.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CFGR: - I2SSRC: - SYSCLK: [0, "System clock used as I2S clock source"] - CKIN: [1, "External clock mapped on the I2S_CKIN pin used as I2S clock source"] diff --git a/peripherals/rcc/rcc_f7.yaml b/peripherals/rcc/rcc_f7.yaml deleted file mode 100644 index e6a79c785..000000000 --- a/peripherals/rcc/rcc_f7.yaml +++ /dev/null @@ -1,13 +0,0 @@ -_include: - - ./rcc_v2.yaml - - ./rcc_v2_i2s.yaml - - ./rcc_v2_i2s_pll.yaml - - ./rcc_v2_i2s_pllq.yaml - - ./rcc_v2_sai_pllp.yaml - - ./rcc_v2_bdcr_lsedrv.yaml - - ./rcc_v2_dckcfgr_timpre.yaml - - ./rcc_v2_dckcfgr_i2s_sai_f7.yaml - - ./rcc_v2_dckcfgr2_48m_sd.yaml - - ./rcc_v2_dckcfgr2_lptimsel.yaml - - ./rcc_v2_dckcfgr2_i2csel.yaml - - ./rcc_v2_dckcfgr2_usartsel.yaml diff --git a/peripherals/rcc/rcc_h7.yaml b/peripherals/rcc/rcc_h7.yaml deleted file mode 100644 index 6ba9e4d53..000000000 --- a/peripherals/rcc/rcc_h7.yaml +++ /dev/null @@ -1,4 +0,0 @@ -_include: - - ./rcc_v3.yaml - - ./rcc_v3_pll.yaml - - ./rcc_v3_h7_ccip.yaml diff --git a/peripherals/rcc/rcc_h7_revision_v.yaml b/peripherals/rcc/rcc_h7_revision_v.yaml deleted file mode 100644 index a951537fd..000000000 --- a/peripherals/rcc/rcc_h7_revision_v.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Revision V of H7 has HSICFGR / CSICFGR instead of ICSCR. - -# Does not apply to Revsion Y of H7 - -RCC: - HSICFGR: - HSITRIM: [0, 0x7F] - _read: - HSICAL: [0, 0xFFF] - CSICFGR: - CSITRIM: [0, 0x3F] - _read: - CSICAL: [0, 0x3FF] diff --git a/peripherals/rcc/rcc_h7_revision_y.yaml b/peripherals/rcc/rcc_h7_revision_y.yaml deleted file mode 100644 index 3f33ee50d..000000000 --- a/peripherals/rcc/rcc_h7_revision_y.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# Revision Y of H7 has ICSCR. - -# Does not apply to Revsion V of H7 - -RCC: - ICSCR: - CSITRIM: [0, 0x1F] - HSITRIM: [0, 0x3F] - _read: - CSICAL: [0, 0xFF] - HSICAL: [0, 0xFFF] diff --git a/peripherals/rcc/rcc_l0.yaml b/peripherals/rcc/rcc_l0.yaml deleted file mode 100644 index 7404d9f85..000000000 --- a/peripherals/rcc/rcc_l0.yaml +++ /dev/null @@ -1,149 +0,0 @@ -# RCC peripheral -# Applicable to STM32L0xx - -RCC: - CR: - HSI16OUTEN: - Disabled: [0, "HSI output clock disabled"] - Enabled: [1, "HSI output clock enabled"] - HSI16DIVF: - _read: - NotDivided: [0, "16 MHz HSI clock not divided"] - Div4: [1, "16 MHz HSI clock divided by 4"] - HSI16DIVEN: - NotDivided: [0, "no 16 MHz HSI division requested"] - Div4: [1, "16 MHz HSI division by 4 requested"] - HSI16RDYF: - _read: - NotReady: [0, "HSI 16 MHz oscillator not ready"] - Ready: [1, "HSI 16 MHz oscillator ready"] - ICSCR: - MSITRIM: [0, 255] - MSICAL: [0, 255] - MSIRANGE: - Range0: [0, "range 0 around 65.536 kHz"] - Range1: [1, "range 1 around 131.072 kHz"] - Range2: [2, "range 2 around 262.144 kHz"] - Range3: [3, "range 3 around 524.288 kHz"] - Range4: [4, "range 4 around 1.048 MHz"] - Range5: [5, "range 5 around 2.097 MHz (reset value)"] - Range6: [6, "range 6 around 4.194 MHz"] - Range7: [7, "not allowed"] - HSI16TRIM: [0, 31] - HSI16CAL: [0, 255] - CFGR: - MCOSEL: - NoClock: [0, "No clock"] - SYSCLK: [1, "SYSCLK clock selected"] - HSI16: [2, "HSI oscillator clock selected"] - MSI: [3, "MSI oscillator clock selected"] - HSE: [4, "HSE oscillator clock selected"] - PLL: [5, "PLL clock selected"] - LSI: [6, "LSI oscillator clock selected"] - LSE: [7, "LSE oscillator clock selected"] - PLLSRC: - HSI16: [0, "HSI selected as PLL input clock"] - HSE: [1, "HSE selected as PLL input clock"] - STOPWUCK: - MSI: [0, "Internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock"] - HSI16: [1, "Internal 16 MHz (HSI) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1)"] - SWS: - MSI: [0, "MSI oscillator used as system clock"] - HSI16: [1, "HSI oscillator used as system clock"] - HSE: [2, "HSE oscillator used as system clock"] - PLL: [3, "PLL used as system clock"] - SW: - MSI: [0, "MSI oscillator used as system clock"] - HSI16: [1, "HSI oscillator used as system clock"] - HSE: [2, "HSE oscillator used as system clock"] - PLL: [3, "PLL used as system clock"] - CIER: - CSSLSE: - Disabled: [0, "LSE CSS interrupt disabled"] - Enabled: [1, "LSE CSS interrupt enabled"] - "*RDYIE": - Disabled: [0, "Ready interrupt disabled"] - Enabled: [1, "Ready interrupt enabled"] - CIFR: - CSSHSEF: - NoClock: [0, "No clock security interrupt caused by HSE clock failure"] - Clock: [1, "Clock security interrupt caused by HSE clock failure"] - CSSLSEF: - NoFailure: [0, "No failure detected on LSE clock failure"] - Failure: [1, "Failure detected on LSE clock failure"] - "*RDYF": - _read: - NotInterrupted: [0, "No clock ready interrupt"] - Interrupted: [1, "Clock ready interrupt"] - CICR: - "*SEC,*RDYC": - _write: - Clear: [1, "Clear interrupt flag"] - IOPRSTR: - "IOP*RST": - Reset: [1, "Reset I/O port"] - IOPENR: - "IOP*EN": - Disabled: [0, "Port clock disabled"] - Enabled: [1, "Port clock enabled"] - CCIPR: - "LPTIM1SEL": - APB: [0, "APB clock selected as Timer clock"] - LSI: [1, "LSI clock selected as Timer clock"] - HSI16: [2, "HSI16 clock selected as Timer clock"] - LSE: [3, "LSE clock selected as Timer clock"] - "I2C?SEL": - APB: [0, "APB clock selected as peripheral clock"] - SYSTEM: [1, "System clock selected as peripheral clock"] - HSI16: [2, "HSI16 clock selected as peripheral clock"] - "LPUART1SEL,USART?SEL": - APB: [0, "APB clock selected as peripheral clock"] - SYSTEM: [1, "System clock selected as peripheral clock"] - HSI16: [2, "HSI16 clock selected as peripheral clock"] - LSE: [3, "LSE clock selected as peripheral clock"] - CSR: - RTCEN: - Disabled: [0, "RTC clock disabled"] - Enabled: [1, "RTC clock enabled"] - RTCSEL: - NoClock: [0, "No clock"] - LSE: [1, "LSE oscillator clock used as RTC clock"] - LSI: [2, "LSI oscillator clock used as RTC clock"] - HSE: [3, "HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock"] - CSSLSED: - NoFailure: [0, "No failure detected on LSE (32 kHz oscillator)"] - Failure: [1, "Failure detected on LSE (32 kHz oscillator)"] - LSEDRV: - Low: [0, "Lowest drive"] - MediumLow: [1, "Medium low drive"] - MediumHigh: [2, "Medium high drive"] - High: [3, "Highest drive"] - LSEBYP: - NotBypassed: [0, "LSE oscillator not bypassed"] - Bypassed: [1, "LSE oscillator bypassed"] - "*ON": - "Off": [0, "Oscillator OFF"] - "On": [1, "Oscillator ON"] - "*RDY": - NotReady: [0, "Oscillator not ready"] - Ready: [1, "Oscillator ready"] - IOPSMEN: - "IOP?SMEN": - Disabled: [0, "Port x clock is disabled in Sleep mode"] - Enabled: [1, "Port x clock is enabled in Sleep mode (if enabled by IOPHEN)"] - AHBSMENR: - CRYPSMEN: - Disabled: [0, "Crypto clock disabled in Sleep mode"] - Enabled: [1, "Crypto clock enabled in Sleep mode"] - CRCSMEN: - Disabled: [0, "Test integration module clock disabled in Sleep mode"] - Enabled: [1, "Test integration module clock enabled in Sleep mode (if enabled by CRCEN)"] - SRAMSMEN: - Disabled: [0, "NVM interface clock disabled in Sleep mode"] - Enabled: [1, "NVM interface clock enabled in Sleep mode"] - MIFSMEN: - Disabled: [0, "NVM interface clock disabled in Sleep mode"] - Enabled: [1, "NVM interface clock enabled in Sleep mode"] - DMASMEN: - Disabled: [0, "DMA clock disabled in Sleep mode"] - Enabled: [1, "DMA clock enabled in Sleep mode"] diff --git a/peripherals/rcc/rcc_l0_l1_common.yaml b/peripherals/rcc/rcc_l0_l1_common.yaml deleted file mode 100644 index 17db55e84..000000000 --- a/peripherals/rcc/rcc_l0_l1_common.yaml +++ /dev/null @@ -1,85 +0,0 @@ -RCC: - CR: - RTCPRE: - Div2: [0, "HSE divided by 2"] - Div4: [1, "HSE divided by 4"] - Div8: [2, "HSE divided by 8"] - Div16: [3, "HSE divided by 16"] - "*ON": - Disabled: [0, "Clock disabled"] - Enabled: [1, "Clock enabled"] - PLLRDY: - _read: - Unlocked: [0, "PLL unlocked"] - Locked: [1, "PLL locked"] - HSEBYP: - NotBypassed: [0, "HSE oscillator not bypassed"] - Bypassed: [1, "HSE oscillator bypassed"] - "HSERDY,HSIRDY,MSIRDY": - _read: - NotReady: [0, "Oscillator is not stable"] - Ready: [1, "Oscillator is stable"] - CFGR: - MCOPRE: - Div1: [0, "No division"] - Div2: [1, "Division by 2"] - Div4: [2, "Division by 4"] - Div8: [3, "Division by 8"] - Div16: [4, "Division by 16"] - PLLDIV: - Div2: [1, "PLLVCO / 2"] - Div3: [2, "PLLVCO / 3"] - Div4: [3, "PLLVCO / 4"] - PLLMUL: - Mul3: [0, "PLL clock entry x 3"] - Mul4: [1, "PLL clock entry x 4"] - Mul6: [2, "PLL clock entry x 6"] - Mul8: [3, "PLL clock entry x 8"] - Mul12: [4, "PLL clock entry x 12"] - Mul16: [5, "PLL clock entry x 16"] - Mul24: [6, "PLL clock entry x 24"] - Mul32: [7, "PLL clock entry x 32"] - Mul48: [8, "PLL clock entry x 48"] - "PPRE[12]": - Div1: [0, "HCLK not divided"] - Div2: [4, "HCLK divided by 2"] - Div4: [5, "HCLK divided by 4"] - Div8: [6, "HCLK divided by 8"] - Div16: [7, "HCLK divided by 16"] - HPRE: - Div1: [0, "system clock not divided"] - Div2: [8, "system clock divided by 2"] - Div4: [9, "system clock divided by 4"] - Div8: [10, "system clock divided by 8"] - Div16: [11, "system clock divided by 16"] - Div64: [12, "system clock divided by 64"] - Div128: [13, "system clock divided by 128"] - Div256: [14, "system clock divided by 256"] - Div512: [15, "system clock divided by 512"] - AHBRSTR: - "*RST": - _write: - Reset: [1, "Reset the module"] - "APB[12]RSTR": - "*RST": - _write: - Reset: [1, "Reset the module"] - AHBENR: - "*EN": - Disabled: [0, "Clock disabled"] - Enabled: [1, "Clock enabled"] - "APB*ENR": - "*EN": - Disabled: [0, "Clock disabled"] - Enabled: [1, "Clock enabled"] - CSR: - "*RSTF": - _read: - NoReset: [0, "No reset has occured"] - Reset: [1, "A reset has occured"] - RMVF: - _write: - Clear: [1, "Clears the reset flag"] - RTCRST: - _write: - Reset: [1, "Resets the RTC peripheral"] diff --git a/peripherals/rcc/rcc_l1.yaml b/peripherals/rcc/rcc_l1.yaml deleted file mode 100644 index 778070d7e..000000000 --- a/peripherals/rcc/rcc_l1.yaml +++ /dev/null @@ -1,57 +0,0 @@ -# RCC peripheral -# Applicable to STM32L1xx - -RCC: - CFGR: - MCOSEL: - NoClock: [0, "No clock"] - SYSCLK: [1, "SYSCLK clock selected"] - HSI: [2, "HSI oscillator clock selected"] - MSI: [3, "MSI oscillator clock selected"] - HSE: [4, "HSE oscillator clock selected"] - PLL: [5, "PLL clock selected"] - LSI: [6, "LSI oscillator clock selected"] - LSE: [7, "LSE oscillator clock selected"] - PLLSRC: - HSI: [0, "HSI selected as PLL input clock"] - HSE: [1, "HSE selected as PLL input clock"] - SWS: - _read: - HSI: [0, "MSI oscillator used as system clock"] - MSI: [1, "HSI oscillator used as system clock"] - HSE: [2, "HSE oscillator used as system clock"] - PLL: [3, "PLL used as system clock"] - SW: - HSI: [0, "MSI oscillator used as system clock"] - MSI: [1, "HSI oscillator used as system clock"] - HSE: [2, "HSE oscillator used as system clock"] - PLL: [3, "PLL used as system clock"] - CIR: - "*CSSC": - _write: - Clear: [1, "Clear interrupt"] - "*RDYC": - _write: - Clear: [1, "Clear interrupt"] - LSECSSIE: - Disabled: [0, "LSE CSS interrupt disabled"] - Enabled: [1, "LSE CSS interrupt enabled"] - "*RDYIE": - Disabled: [0, "Interrupt disabled"] - Enabled: [1, "Interrupt enabled"] - CSSF: - _read: - NotInterupted: [0, "No clock security interrupt caused by HSE clock failure"] - Interupted: [1, "Clock security interrupt caused by HSE clock failure"] - LSECSSF: - _read: - NoFailure: [0, "No failure detected on the external 32 KHz oscillator"] - Failure: [1, "A failure is detected on the external 32 kHz oscillator"] - "*RDYF": - _read: - NotStable: [0, "Clock is not stable"] - Stable: [1, "Clock is stable"] - "AHBLPENR": - "*EN": - Disabled: [0, "Clock disabled"] - Enabled: [1, "Clock enabled"] diff --git a/peripherals/rcc/rcc_l4.yaml b/peripherals/rcc/rcc_l4.yaml deleted file mode 100644 index ee9c5d2ab..000000000 --- a/peripherals/rcc/rcc_l4.yaml +++ /dev/null @@ -1,15 +0,0 @@ -RCC: - CR: - MSIRANGE: - Range100K: [0b0000, "range 0 around 100 kHz"] - Range200K: [0b0001, "range 1 around 200 kHz"] - Range400K: [0b0010, "range 2 around 400 kHz"] - Range800K: [0b0011, "range 3 around 800 kHz"] - Range1M: [0b0100, "range 4 around 1 MHz"] - Range2M: [0b0101, "range 5 around 2 MHz"] - Range4M: [0b0110, "range 6 around 4 MHz"] - Range8M: [0b0111, "range 7 around 8 MHz"] - Range16M: [0b1000, "range 8 around 16 MHz"] - Range24M: [0b1001, "range 9 around 24 MHz"] - Range32M: [0b1010, "range 10 around 32 MHz"] - Range48M: [0b1011, "range 11 around 48 MHz"] diff --git a/peripherals/rcc/rcc_merge_rtcsel.yaml b/peripherals/rcc/rcc_merge_rtcsel.yaml deleted file mode 100644 index 4ef905bd5..000000000 --- a/peripherals/rcc/rcc_merge_rtcsel.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# Applicable at least to STM32F4 and STM32F7. - -RCC: - BDCR: - _merge: ["RTCSEL[01]"] diff --git a/peripherals/rcc/rcc_merge_sw_sws.yaml b/peripherals/rcc/rcc_merge_sw_sws.yaml deleted file mode 100644 index daaabaa84..000000000 --- a/peripherals/rcc/rcc_merge_sw_sws.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# Applicable at least to some STM32F4 and STM32F7. - -RCC: - CFGR: - _merge: ["SW[01]", "SWS[01]"] diff --git a/peripherals/rcc/rcc_pllsrc_1bit.yaml b/peripherals/rcc/rcc_pllsrc_1bit.yaml deleted file mode 100644 index 713b7799e..000000000 --- a/peripherals/rcc/rcc_pllsrc_1bit.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CFGR: - PLLSRC: - HSI_Div2: [0, "HSI divided by 2 selected as PLL input clock"] - HSE_Div_PREDIV: [1, "HSE divided by PREDIV selected as PLL input clock"] diff --git a/peripherals/rcc/rcc_pllsrc_2bit.yaml b/peripherals/rcc/rcc_pllsrc_2bit.yaml deleted file mode 100644 index 070d9acc2..000000000 --- a/peripherals/rcc/rcc_pllsrc_2bit.yaml +++ /dev/null @@ -1,6 +0,0 @@ -RCC: - CFGR: - PLLSRC: - HSI_Div2: [0, "HSI divided by 2 selected as PLL input clock"] - HSI_Div_PREDIV: [1, "HSI divided by PREDIV selected as PLL input clock"] - HSE_Div_PREDIV: [2, "HSE divided by PREDIV selected as PLL input clock"] diff --git a/peripherals/rcc/rcc_v2.yaml b/peripherals/rcc/rcc_v2.yaml deleted file mode 100644 index 3934f0ad6..000000000 --- a/peripherals/rcc/rcc_v2.yaml +++ /dev/null @@ -1,50 +0,0 @@ -# Applicable at least to STM32F4 and STM32F7. - -_include: - - ./rcc_common.yaml - -RCC: - PLLCFGR: - _merge: ["PLLM*", "PLLN*", "PLLP*", "PLLQ*"] - PLLSRC: - HSI: [0, "HSI clock selected as PLL and PLLI2S clock entry"] - HSE: [1, "HSE oscillator clock selected as PLL and PLLI2S clock entry"] - PLLQ: [2, 15] - PLLP: - Div2: [0, "PLLP=2"] - Div4: [1, "PLLP=4"] - Div6: [2, "PLLP=6"] - Div8: [3, "PLLP=8"] - PLLN: [50, 432] - PLLM: [2, 63] - CFGR: - MCO2: - SYSCLK: [0, "System clock (SYSCLK) selected"] - PLLI2S: [1, "PLLI2S clock selected"] - HSE: [2, "HSE oscillator clock selected"] - PLL: [3, "PLL clock selected"] - "MCO*PRE": - Div1: [0, "No division"] - Div2: [4, "Division by 2"] - Div3: [5, "Division by 3"] - Div4: [6, "Division by 4"] - Div5: [7, "Division by 5"] - MCO1: - HSI: [0, "HSI clock selected"] - LSE: [1, "LSE oscillator selected"] - HSE: [2, "HSE oscillator clock selected"] - PLL: [3, "PLL clock selected"] - RTCPRE: [0, 31] - "A?B?LPENR": - "*LPEN": - DisabledInSleep: [0, "Selected module is disabled during Sleep mode"] - EnabledInSleep: [1, "Selected module is enabled during Sleep mode"] - SSCGR: - SSCGEN: - Disabled: [0, "Spread spectrum modulation disabled"] - Enabled: [1, "Spread spectrum modulation enabled"] - SPREADSEL: - Center: [0, "Center spread"] - Down: [1, "Down spread"] - INCSTEP: [0, 32767] - MODPER: [0, 8191] diff --git a/peripherals/rcc/rcc_v2_bdcr_lsedrv.yaml b/peripherals/rcc/rcc_v2_bdcr_lsedrv.yaml deleted file mode 100644 index b032d0886..000000000 --- a/peripherals/rcc/rcc_v2_bdcr_lsedrv.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - BDCR: - LSEDRV: - Low: [0, "Low drive capacity"] - MediumHigh: [1, "Medium-high drive capacity"] - MediumLow: [2, "Medium-low drive capacity"] - High: [3, "High drive capacity"] diff --git a/peripherals/rcc/rcc_v2_bdcr_lsemod.yaml b/peripherals/rcc/rcc_v2_bdcr_lsemod.yaml deleted file mode 100644 index 422e909ba..000000000 --- a/peripherals/rcc/rcc_v2_bdcr_lsemod.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - BDCR: - LSEMOD: - Low: [0, "LSE oscillator low power mode selection"] - High: [1, "LSE oscillator high drive mode selection"] diff --git a/peripherals/rcc/rcc_v2_cfgr_mcoen.yaml b/peripherals/rcc/rcc_v2_cfgr_mcoen.yaml deleted file mode 100644 index f5f7a2c87..000000000 --- a/peripherals/rcc/rcc_v2_cfgr_mcoen.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CFGR: - MCO?EN: - Disabled: [0, "MCO output disabled"] - Enabled: [1, "MCO output enabled"] diff --git a/peripherals/rcc/rcc_v2_ckgatenr.yaml b/peripherals/rcc/rcc_v2_ckgatenr.yaml deleted file mode 100644 index 5ed88254a..000000000 --- a/peripherals/rcc/rcc_v2_ckgatenr.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - CKGATENR: - "*_CKEN": - Enabled: [0, "The clock gating is enabled"] - Disabled: [1, "The clock gating is disabled, the clock is always enabled"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr2_48m_sd.yaml b/peripherals/rcc/rcc_v2_dckcfgr2_48m_sd.yaml deleted file mode 100644 index a9d223350..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr2_48m_sd.yaml +++ /dev/null @@ -1,8 +0,0 @@ -RCC: - DCKCFGR2: - CK48MSEL: - PLL: [0, "48MHz clock from PLL is selected"] - PLLSAI: [1, "48MHz clock from PLLSAI is selected"] - SDMMC?SEL,SDIOSEL: - CK48M: [0, "48 MHz clock is selected as SD clock"] - SYSCLK: [1, "System clock is selected as SD clock"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml b/peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml deleted file mode 100644 index b89fea1cf..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr2_cecsel.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - DCKCFGR2: - CECSEL: - LSE: [0, "LSE clock is selected as HDMI-CEC clock"] - HSI_Div488: [1, "HSI divided by 488 clock is selected as HDMI-CEC clock"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr2_i2csel.yaml b/peripherals/rcc/rcc_v2_dckcfgr2_i2csel.yaml deleted file mode 100644 index b7840409d..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr2_i2csel.yaml +++ /dev/null @@ -1,6 +0,0 @@ -RCC: - DCKCFGR2: - "*I2C?SEL": - APB: [0, "APB clock selected as I2C clock"] - SYSCLK: [1, "System clock selected as I2C clock"] - HSI: [2, "HSI clock selected as I2C clock"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr2_lptimsel.yaml b/peripherals/rcc/rcc_v2_dckcfgr2_lptimsel.yaml deleted file mode 100644 index 9d90daa9d..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr2_lptimsel.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - DCKCFGR2: - LPTIM1SEL: - APB1: [0, "APB1 clock (PCLK1) selected as LPTILM1 clock"] - LSI: [1, "LSI clock is selected as LPTILM1 clock"] - HSI: [2, "HSI clock is selected as LPTILM1 clock"] - LSE: [3, "LSE clock is selected as LPTILM1 clock"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr2_spdifrxsel.yaml b/peripherals/rcc/rcc_v2_dckcfgr2_spdifrxsel.yaml deleted file mode 100644 index b17f8bbca..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr2_spdifrxsel.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - DCKCFGR2: - SPDIFRXSEL: - PLL: [0, "SPDIF-Rx clock from PLL is selected"] - PLLI2S: [1, "SPDIF-Rx clock from PLLI2S is selected"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr2_usartsel.yaml b/peripherals/rcc/rcc_v2_dckcfgr2_usartsel.yaml deleted file mode 100644 index 5ec95b9c3..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr2_usartsel.yaml +++ /dev/null @@ -1,12 +0,0 @@ -RCC: - DCKCFGR2: - USART2SEL,USART3SEL,UART4SEL,UART5SEL,UART7SEL,UART8SEL: - APB1: [0, "APB1 clock (PCLK1) is selected as USART clock"] - SYSCLK: [1, "System clock is selected as USART clock"] - HSI: [2, "HSI clock is selected as USART clock"] - LSE: [3, "LSE clock is selected as USART clock"] - USART1SEL,USART6SEL: - APB2: [0, "APB2 clock (PCLK2) is selected as USART clock"] - SYSCLK: [1, "System clock is selected as USART clock"] - HSI: [2, "HSI clock is selected as USART clock"] - LSE: [3, "LSE clock is selected as USART clock"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_48m_sd.yaml b/peripherals/rcc/rcc_v2_dckcfgr_48m_sd.yaml deleted file mode 100644 index 211455593..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_48m_sd.yaml +++ /dev/null @@ -1,8 +0,0 @@ -RCC: - DCKCFGR: - CK48MSEL: - PLL: [0, "48MHz clock from PLL is selected"] - PLLSAI: [1, "48MHz clock from PLLSAI is selected"] - SDIOSEL: - CK48M: [0, "48 MHz clock is selected as SD clock"] - SYSCLK: [1, "System clock is selected as SD clock"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f4.yaml b/peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f4.yaml deleted file mode 100644 index 95488d6ec..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f4.yaml +++ /dev/null @@ -1,8 +0,0 @@ -RCC: - DCKCFGR: - CKDFSDM?ASEL: - I2S1: [0, "CK_I2S_APB1 selected as audio clock"] - I2S2: [1, "CK_I2S_APB2 selected as audio clock"] - CKDFSDM1SEL: - APB2: [0, "APB2 clock used as Kernel clock"] - SYSCLK: [1, "System clock used as Kernel clock"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f7.yaml b/peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f7.yaml deleted file mode 100644 index e1c0caaf9..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_dfsdm_f7.yaml +++ /dev/null @@ -1,8 +0,0 @@ -RCC: - DCKCFGR1: - DFSDM1SEL: - APB2: [0, "APB2 clock (PCLK2) selected as DFSDM1 Kernel clock source"] - SYSCLK: [1, "System clock (SYSCLK) clock selected as DFSDM1 Kernel clock source"] - ADFSDM1SEL: - SAI1: [0, "SAI1 clock selected as DFSDM1 Audio clock source"] - SAI2: [1, "SAI2 clock selected as DFSDM1 Audio clock source"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_dsisel.yaml b/peripherals/rcc/rcc_v2_dckcfgr_dsisel.yaml deleted file mode 100644 index 68bf15cf9..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_dsisel.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - DCKCFGR,DCKCFGR2: - DSISEL: - DSI_PHY: [0, "DSI-PHY used as DSI byte lane clock source (usual case)"] - PLLR: [1, "PLLR used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode)"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_i2s12src.yaml b/peripherals/rcc/rcc_v2_dckcfgr_i2s12src.yaml deleted file mode 100644 index 8ed055eb5..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_i2s12src.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - DCKCFGR: - I2S?SRC: - PLLI2SR: [0, "I2Sx clock frequency = f(PLLI2S_R)"] - I2S_CKIN: [1, "I2Sx clock frequency = I2S_CKIN Alternate function input frequency"] - PLLR: [2, "I2Sx clock frequency = f(PLL_R)"] - HSI_HSE: [3, "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_common.yaml b/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_common.yaml deleted file mode 100644 index 7f815efb4..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_common.yaml +++ /dev/null @@ -1,68 +0,0 @@ -RCC: - DCKCFGR,DCKCFGR1: - PLLI2SDIVQ,PLLI2SDIVR: - Div1: [0, "PLLI2SDIVQ = /1"] - Div2: [1, "PLLI2SDIVQ = /2"] - Div3: [2, "PLLI2SDIVQ = /3"] - Div4: [3, "PLLI2SDIVQ = /4"] - Div5: [4, "PLLI2SDIVQ = /5"] - Div6: [5, "PLLI2SDIVQ = /6"] - Div7: [6, "PLLI2SDIVQ = /7"] - Div8: [7, "PLLI2SDIVQ = /8"] - Div9: [8, "PLLI2SDIVQ = /9"] - Div10: [9, "PLLI2SDIVQ = /10"] - Div11: [10, "PLLI2SDIVQ = /11"] - Div12: [11, "PLLI2SDIVQ = /12"] - Div13: [12, "PLLI2SDIVQ = /13"] - Div14: [13, "PLLI2SDIVQ = /14"] - Div15: [14, "PLLI2SDIVQ = /15"] - Div16: [15, "PLLI2SDIVQ = /16"] - Div17: [16, "PLLI2SDIVQ = /17"] - Div18: [17, "PLLI2SDIVQ = /18"] - Div19: [18, "PLLI2SDIVQ = /19"] - Div20: [19, "PLLI2SDIVQ = /20"] - Div21: [20, "PLLI2SDIVQ = /21"] - Div22: [21, "PLLI2SDIVQ = /22"] - Div23: [22, "PLLI2SDIVQ = /23"] - Div24: [23, "PLLI2SDIVQ = /24"] - Div25: [24, "PLLI2SDIVQ = /25"] - Div26: [25, "PLLI2SDIVQ = /26"] - Div27: [26, "PLLI2SDIVQ = /27"] - Div28: [27, "PLLI2SDIVQ = /28"] - Div29: [28, "PLLI2SDIVQ = /29"] - Div30: [29, "PLLI2SDIVQ = /30"] - Div31: [30, "PLLI2SDIVQ = /31"] - Div32: [31, "PLLI2SDIVQ = /32"] - PLLSAIDIVQ,PLLDIVR: - Div1: [0, "PLLSAIDIVQ = /1"] - Div2: [1, "PLLSAIDIVQ = /2"] - Div3: [2, "PLLSAIDIVQ = /3"] - Div4: [3, "PLLSAIDIVQ = /4"] - Div5: [4, "PLLSAIDIVQ = /5"] - Div6: [5, "PLLSAIDIVQ = /6"] - Div7: [6, "PLLSAIDIVQ = /7"] - Div8: [7, "PLLSAIDIVQ = /8"] - Div9: [8, "PLLSAIDIVQ = /9"] - Div10: [9, "PLLSAIDIVQ = /10"] - Div11: [10, "PLLSAIDIVQ = /11"] - Div12: [11, "PLLSAIDIVQ = /12"] - Div13: [12, "PLLSAIDIVQ = /13"] - Div14: [13, "PLLSAIDIVQ = /14"] - Div15: [14, "PLLSAIDIVQ = /15"] - Div16: [15, "PLLSAIDIVQ = /16"] - Div17: [16, "PLLSAIDIVQ = /17"] - Div18: [17, "PLLSAIDIVQ = /18"] - Div19: [18, "PLLSAIDIVQ = /19"] - Div20: [19, "PLLSAIDIVQ = /20"] - Div21: [20, "PLLSAIDIVQ = /21"] - Div22: [21, "PLLSAIDIVQ = /22"] - Div23: [22, "PLLSAIDIVQ = /23"] - Div24: [23, "PLLSAIDIVQ = /24"] - Div25: [24, "PLLSAIDIVQ = /25"] - Div26: [25, "PLLSAIDIVQ = /26"] - Div27: [26, "PLLSAIDIVQ = /27"] - Div28: [27, "PLLSAIDIVQ = /28"] - Div29: [28, "PLLSAIDIVQ = /29"] - Div30: [29, "PLLSAIDIVQ = /30"] - Div31: [30, "PLLSAIDIVQ = /31"] - Div32: [31, "PLLSAIDIVQ = /32"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f4.yaml b/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f4.yaml deleted file mode 100644 index 5f3d7b9cf..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f4.yaml +++ /dev/null @@ -1,13 +0,0 @@ -_include: - - ./rcc_v2_dckcfgr_i2s_sai_common.yaml - -RCC: - DCKCFGR: - SAI1ASRC: - PLLSAI: [0, "SAI1-A clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] - PLLI2S: [1, "SAI1-A clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] - I2S_CKIN: [2, "SAI1-A clock frequency = Alternate function input frequency"] - SAI1BSRC: - PLLSAI: [0, "SAI1-B clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] - PLLI2S: [1, "SAI1-B clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] - I2S_CKIN: [2, "SAI1-B clock frequency = Alternate function input frequency"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f446.yaml b/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f446.yaml deleted file mode 100644 index d29dc480a..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f446.yaml +++ /dev/null @@ -1,15 +0,0 @@ -_include: - - ./rcc_v2_dckcfgr_i2s_sai_common.yaml - -RCC: - DCKCFGR: - SAI1SRC: - PLLSAI: [0, "SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] - PLLI2S: [1, "SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] - PLLR: [2, "SAI1 clock frequency = f(PLL_R)"] - I2S_CKIN: [3, "I2S_CKIN Alternate function input frequency"] - SAI2SRC: - PLLSAI: [0, "SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] - PLLI2S: [1, "SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] - PLLR: [2, "SAI2 clock frequency = f(PLL_R)"] - HSI_HSE: [3, "SAI2 clock frequency = Alternate function input frequency"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f7.yaml b/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f7.yaml deleted file mode 100644 index ed5ef042e..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_i2s_sai_f7.yaml +++ /dev/null @@ -1,15 +0,0 @@ -_include: - - ./rcc_v2_dckcfgr_i2s_sai_common.yaml - -RCC: - DCKCFGR1: - SAI1SEL: - PLLSAI: [0, "SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] - PLLI2S: [1, "SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] - AFIF: [2, "SAI1 clock frequency = Alternate function input frequency"] - HSI_HSE: [3, "SAI1 clock frequency = HSI or HSE"] - SAI2SEL: - PLLSAI: [0, "SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ"] - PLLI2S: [1, "SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ"] - AFIF: [2, "SAI2 clock frequency = Alternate function input frequency"] - HSI_HSE: [3, "SAI2 clock frequency = HSI or HSE"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_i2ssrc.yaml b/peripherals/rcc/rcc_v2_dckcfgr_i2ssrc.yaml deleted file mode 100644 index ca9f3a363..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_i2ssrc.yaml +++ /dev/null @@ -1,6 +0,0 @@ -RCC: - DCKCFGR: - I2SSRC: - PLLCLKR: [0, "I2Sx clock frequency = f(PLLCLK_R)"] - I2S_CKIN: [1, "I2Sx clock frequency = I2S_CKIN Alternate function input frequency"] - HSI_HSE: [3, "I2Sx clock frequency = HSI/HSE depends on PLLSRC bit (PLLCFGR[22])"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml b/peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml deleted file mode 100644 index 1bab22101..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_saidivr.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - DCKCFGR,DCKCFGR1: - PLLSAIDIVR: - Div2: [0, "PLLSAIDIVR = /2"] - Div4: [1, "PLLSAIDIVR = /4"] - Div8: [2, "PLLSAIDIVR = /8"] - Div16: [3, "PLLSAIDIVR = /16"] diff --git a/peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml b/peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml deleted file mode 100644 index d4cc40adf..000000000 --- a/peripherals/rcc/rcc_v2_dckcfgr_timpre.yaml +++ /dev/null @@ -1,5 +0,0 @@ -RCC: - DCKCFGR,DCKCFGR1: - TIMPRE: - Mul2: [0, "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx"] - Mul4: [1, "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx"] diff --git a/peripherals/rcc/rcc_v2_i2s.yaml b/peripherals/rcc/rcc_v2_i2s.yaml deleted file mode 100644 index 786e308ff..000000000 --- a/peripherals/rcc/rcc_v2_i2s.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Applicable at least to some STM32F4 and STM32F7. - -RCC: - CFGR: - I2SSRC: - PLLI2S: [0, "PLLI2S clock used as I2S clock source"] - CKIN: [1, "External clock mapped on the I2S_CKIN pin used as I2S clock source"] diff --git a/peripherals/rcc/rcc_v2_i2s_pll.yaml b/peripherals/rcc/rcc_v2_i2s_pll.yaml deleted file mode 100644 index 09d679cae..000000000 --- a/peripherals/rcc/rcc_v2_i2s_pll.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Applicable at least to some STM32F4 and STM32F7. - -RCC: - PLLI2SCFGR: - "PLL*R": [2, 7] - PLLI2SCFGR,PLLSAICFGR: - "PLL*N": [50, 432] diff --git a/peripherals/rcc/rcc_v2_i2s_pllm.yaml b/peripherals/rcc/rcc_v2_i2s_pllm.yaml deleted file mode 100644 index 610e9b3d1..000000000 --- a/peripherals/rcc/rcc_v2_i2s_pllm.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# Applicable at least to some STM32F4 and STM32F7. - -RCC: - PLLI2SCFGR,PLLSAICFGR: - "PLL*M": [2, 63] diff --git a/peripherals/rcc/rcc_v2_i2s_pllp.yaml b/peripherals/rcc/rcc_v2_i2s_pllp.yaml deleted file mode 100644 index e6689f6d8..000000000 --- a/peripherals/rcc/rcc_v2_i2s_pllp.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - PLLI2SCFGR: - "PLL*P": - Div2: [0, "PLL*P=2"] - Div4: [1, "PLL*P=4"] - Div6: [2, "PLL*P=6"] - Div8: [3, "PLL*P=8"] diff --git a/peripherals/rcc/rcc_v2_i2s_pllq.yaml b/peripherals/rcc/rcc_v2_i2s_pllq.yaml deleted file mode 100644 index 453441114..000000000 --- a/peripherals/rcc/rcc_v2_i2s_pllq.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# Applicable at least to some STM32F4 and STM32F7. - -RCC: - PLLI2SCFGR,PLLSAICFGR: - "PLL*Q": [2, 15] diff --git a/peripherals/rcc/rcc_v2_i2s_pllsrc.yaml b/peripherals/rcc/rcc_v2_i2s_pllsrc.yaml deleted file mode 100644 index 406026c23..000000000 --- a/peripherals/rcc/rcc_v2_i2s_pllsrc.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Applicable at least to some STM32F4 - -RCC: - PLLI2SCFGR: - PLLI2SSRC: - HSE_HSI: [0, "HSE or HSI depending on PLLSRC of PLLCFGR"] - External: [1, "External AFI clock (CK_PLLI2S_EXT) selected as PLL clock entry"] diff --git a/peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml b/peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml deleted file mode 100644 index f99c76787..000000000 --- a/peripherals/rcc/rcc_v2_pllcfgr_pllr.yaml +++ /dev/null @@ -1,3 +0,0 @@ -RCC: - PLLCFGR: - PLLR: [2, 7] diff --git a/peripherals/rcc/rcc_v2_sai_pllp.yaml b/peripherals/rcc/rcc_v2_sai_pllp.yaml deleted file mode 100644 index 366b7c76e..000000000 --- a/peripherals/rcc/rcc_v2_sai_pllp.yaml +++ /dev/null @@ -1,7 +0,0 @@ -RCC: - PLLSAICFGR: - "PLL*P": - Div2: [0, "PLL*P=2"] - Div4: [1, "PLL*P=4"] - Div6: [2, "PLL*P=6"] - Div8: [3, "PLL*P=8"] diff --git a/peripherals/rcc/rcc_v2_sai_pllr.yaml b/peripherals/rcc/rcc_v2_sai_pllr.yaml deleted file mode 100644 index 9c8317f08..000000000 --- a/peripherals/rcc/rcc_v2_sai_pllr.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# Applicable at least to some STM32F4 and STM32F7. - -RCC: - PLLSAICFGR: - "PLL*R": [2, 7] diff --git a/peripherals/rcc/rcc_v3.yaml b/peripherals/rcc/rcc_v3.yaml deleted file mode 100644 index b08d19391..000000000 --- a/peripherals/rcc/rcc_v3.yaml +++ /dev/null @@ -1,139 +0,0 @@ -# Applicable at least to H7 - -# Fresh start - even fields from rcc_common are quite different - -RCC: - CR: - HSIDIVF: - _read: - NotPropagated: [0, "New HSIDIV ratio has not yet propagated to hsi_ck"] - Propagated: [1, "HSIDIV ratio has propagated to hsi_ck"] - HSEBYP: - NotBypassed: [0, "HSE crystal oscillator not bypassed"] - Bypassed: [1, "HSE crystal oscillator bypassed with external clock"] - HSIDIV: - Div1: [0, "No division"] - Div2: [1, "Division by 2"] - Div4: [2, "Division by 4"] - Div8: [3, "Division by 8"] - "*RDY": - _read: - NotReady: [0, "Clock not ready"] - Ready: [1, "Clock ready"] - "*ON": - "Off": [0, "Clock Off"] - "On": [1, "Clock On"] - CRRCR: - _read: - HSI48CAL: [0, 0x3FF] - CFGR: - MCO2: - SYSCLK: [0, "System clock selected for micro-controller clock output"] - PLL2_P: [1, "pll2_p selected for micro-controller clock output"] - HSE: [2, "HSE selected for micro-controller clock output"] - PLL1_P: [3, "pll1_p selected for micro-controller clock output"] - CSI: [4, "CSI selected for micro-controller clock output"] - LSI: [5, "LSI selected for micro-controller clock output"] - MCO1: - HSI: [0, "HSI selected for micro-controller clock output"] - LSE: [1, "LSE selected for micro-controller clock output"] - HSE: [2, "HSE selected for micro-controller clock output"] - PLL1_Q: [3, "pll1_q selected for micro-controller clock output"] - HSI48: [4, "HSI48 selected for micro-controller clock output"] - MCO?PRE: [0, 15] - TIMPRE: - DefaultX2: [0, "Timer kernel clock equal to 2x pclk by default"] - DefaultX4: [1, "Timer kernel clock equal to 4x pclk by default"] - HRTIMSEL: - TIMY_KER: [0, "The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)"] - C_CK: [1, "The HRTIM prescaler clock source is the CPU clock (c_ck)"] - RTCPRE: [0, 63] - STOPWUCK,STOPKERWUCK: - HSI: [0, "HSI selected as wake up clock from system Stop"] - CSI: [1, "CSI selected as wake up clock from system Stop"] - SWS: - _read: - HSI: [0, "HSI oscillator used as system clock"] - CSI: [1, "CSI oscillator used as system clock"] - HSE: [2, "HSE oscillator used as system clock"] - PLL1: [3, "PLL1 used as system clock"] - SW: - HSI: [0, "HSI selected as system clock"] - CSI: [1, "CSI selected as system clock"] - HSE: [2, "HSE selected as system clock"] - PLL1: [3, "PLL1 selected as system clock"] - CIER: - "*IE": - Disabled: [0, "Interrupt disabled"] - Enabled: [1, "Interrupt enabled"] - CICR: - "*C": - Clear: [1, "Clear interrupt flag"] - BDCR: - BDRST: - Reset: [1, "Resets the entire VSW domain"] - RTCEN: - Disabled: [0, "RTC clock disabled"] - Enabled: [1, "RTC clock enabled"] - RTCSEL: - NoClock: [0, "No clock"] - LSE: [1, "LSE oscillator clock used as RTC clock"] - LSI: [2, "LSI oscillator clock used as RTC clock"] - HSE: [3, "HSE oscillator clock divided by a prescaler used as RTC clock"] - LSECSSD: - _read: - NoFailure: [0, "No failure detected on 32 kHz oscillator"] - Failure: [1, "Failure detected on 32 kHz oscillator"] - LSECSSON: - SecurityOff: [0, "Clock security system on 32 kHz oscillator off"] - SecurityOn: [1, "Clock security system on 32 kHz oscillator on"] - LSEDRV: - Lowest: [0, "Lowest LSE oscillator driving capability"] - MediumLow: [1, "Medium low LSE oscillator driving capability"] - MediumHigh: [2, "Medium high LSE oscillator driving capability"] - Highest: [3, "Highest LSE oscillator driving capability"] - LSEBYP: - NotBypassed: [0, "LSE crystal oscillator not bypassed"] - Bypassed: [1, "LSE crystal oscillator bypassed with external clock"] - LSERDY: - _read: - NotReady: [0, "LSE oscillator not ready"] - Ready: [1, "LSE oscillator ready"] - LSEON: - "Off": [0, "LSE oscillator Off"] - "On": [1, "LSE oscillator On"] - CSR: - LSIRDY: - _read: - NotReady: [0, "LSI oscillator not ready"] - Ready: [1, "LSI oscillator ready"] - LSION: - "Off": [0, "LSI oscillator Off"] - "On": [1, "LSI oscillator On"] - "A?B?RSTR,A?B??RSTR": - "*RST": - Reset: [1, "Reset the selected module"] - GCR: - WW1RSC: - Clear: [0, "Clear WWDG1 scope control"] - Set: [1, "Set WWDG1 scope control"] - D3AMR: - "*AMEN": - Disabled: [0, "Clock disabled in autonomous mode"] - Enabled: [1, "Clock enabled in autonomous mode"] - RSR,C1_RSR: - "*RSTF": - _read: - NoResetOccoured: [0, "No reset occoured for block"] - ResetOccourred: [1, "Reset occoured for block"] - RMVF: - NotActive: [0, "Not clearing the the reset flags"] - Clear: [1, "Clear the reset flags"] - "A?B?ENR,A?B??ENR,C1_A?B?ENR,C1_A?B??ENR": - "*EN": - Disabled: [0, "The selected clock is disabled"] - Enabled: [1, "The selected clock is enabled"] - "A?B?LPENR,A?B??LPENR,C1_A?B?LPENR,C1_A?B??LPENR": - "*LPEN": - Disabled: [0, "The selected clock is disabled during csleep mode"] - Enabled: [1, "The selected clock is enabled during csleep mode"] diff --git a/peripherals/rcc/rcc_v3_h7_ccip.yaml b/peripherals/rcc/rcc_v3_h7_ccip.yaml deleted file mode 100644 index 612fe8fcb..000000000 --- a/peripherals/rcc/rcc_v3_h7_ccip.yaml +++ /dev/null @@ -1,149 +0,0 @@ -# Applicable at least to H7 - -# Domain kernel clock configuration registers (DxCCIPR) and Domain -# clock configuration registers (DxCFGR) - -RCC: - D1CFGR: - "D?CPRE,HPRE": - Div1: [0, "sys_ck not divided"] - Div2: [8, "sys_ck divided by 2"] - Div4: [9, "sys_ck divided by 4"] - Div8: [10, "sys_ck divided by 8"] - Div16: [11, "sys_ck divided by 16"] - Div64: [12, "sys_ck divided by 64"] - Div128: [13, "sys_ck divided by 128"] - Div256: [14, "sys_ck divided by 256"] - Div512: [15, "sys_ck divided by 512"] - D?CFGR: - D?PPR*: - Div1: [0, "rcc_hclk not divided"] - Div2: [4, "rcc_hclk divided by 2"] - Div4: [5, "rcc_hclk divided by 4"] - Div8: [6, "rcc_hclk divided by 8"] - Div16: [7, "rcc_hclk divided by 16"] - D1CCIPR,CDCCIPR: - CKPERSEL: - HSI: [0, "HSI selected as peripheral clock"] - CSI: [1, "CSI selected as peripheral clock"] - HSE: [2, "HSE selected as peripheral clock"] - SDMMCSEL: - PLL1_Q: [0, "pll1_q selected as peripheral clock"] - PLL2_R: [1, "pll2_r selected as peripheral clock"] - QSPISEL,FMCSEL,OCTOSPISEL: - RCC_HCLK3: [0, "rcc_hclk3 selected as peripheral clock"] - PLL1_Q: [1, "pll1_q selected as peripheral clock"] - PLL2_R: [2, "pll2_r selected as peripheral clock"] - PER: [3, "PER selected as peripheral clock"] - D2CCIP1R,CDCCIP1R: - SWPSEL: - PCLK: [0, "pclk selected as peripheral clock"] - HSI_KER: [1, "hsi_ker selected as peripheral clock"] - FDCANSEL: - HSE: [0, "HSE selected as peripheral clock"] - PLL1_Q: [1, "pll1_q selected as peripheral clock"] - PLL2_Q: [2, "pll2_q selected as peripheral clock"] - DFSDM1SEL: - RCC_PCLK2: [0, "rcc_pclk2 selected as peripheral clock"] - SYS: [1, "System clock selected as peripheral clock"] - SPDIFSEL,SPDIFRXSEL: - PLL1_Q: [0, "pll1_q selected as peripheral clock"] - PLL2_R: [1, "pll2_r selected as peripheral clock"] - PLL3_R: [2, "pll3_r selected as peripheral clock"] - HSI_KER: [3, "hsi_ker selected as peripheral clock"] - SPI45SEL: - APB: [0, "APB clock selected as peripheral clock"] - PLL2_Q: [1, "pll2_q selected as peripheral clock"] - PLL3_Q: [2, "pll3_q selected as peripheral clock"] - HSI_KER: [3, "hsi_ker selected as peripheral clock"] - CSI_KER: [4, "csi_ker selected as peripheral clock"] - HSE: [5, "HSE selected as peripheral clock"] - SPI123SEL,SAI23SEL,SAI1SEL: - PLL1_Q: [0, "pll1_q selected as peripheral clock"] - PLL2_P: [1, "pll2_p selected as peripheral clock"] - PLL3_P: [2, "pll3_p selected as peripheral clock"] - I2S_CKIN: [3, "I2S_CKIN selected as peripheral clock"] - PER: [4, "PER selected as peripheral clock"] - D2CCIP2R,CDCCIP2R: - LPTIM1SEL: - RCC_PCLK1: [0, "rcc_pclk1 selected as peripheral clock"] - PLL2_P: [1, "pll2_p selected as peripheral clock"] - PLL3_R: [2, "pll3_r selected as peripheral clock"] - LSE: [3, "LSE selected as peripheral clock"] - LSI: [4, "LSI selected as peripheral clock"] - PER: [5, "PER selected as peripheral clock"] - CECSEL: - LSE: [0, "LSE selected as peripheral clock"] - LSI: [1, "LSI selected as peripheral clock"] - CSI_KER: [2, "csi_ker selected as peripheral clock"] - USBSEL: - DISABLE: [0, "Disable the kernel clock"] - PLL1_Q: [1, "pll1_q selected as peripheral clock"] - PLL3_Q: [2, "pll3_q selected as peripheral clock"] - HSI48: [3, "HSI48 selected as peripheral clock"] - I2C123SEL: - RCC_PCLK1: [0, "rcc_pclk1 selected as peripheral clock"] - PLL3_R: [1, "pll3_r selected as peripheral clock"] - HSI_KER: [2, "hsi_ker selected as peripheral clock"] - CSI_KER: [3, "csi_ker selected as peripheral clock"] - RNGSEL: - HSI48: [0, "HSI48 selected as peripheral clock"] - PLL1_Q: [1, "pll1_q selected as peripheral clock"] - LSE: [2, "LSE selected as peripheral clock"] - LSI: [3, "LSI selected as peripheral clock"] - USART16SEL,USART16910SEL: - RCC_PCLK2: [0, "rcc_pclk2 selected as peripheral clock"] - PLL2_Q: [1, "pll2_q selected as peripheral clock"] - PLL3_Q: [2, "pll3_q selected as peripheral clock"] - HSI_KER: [3, "hsi_ker selected as peripheral clock"] - CSI_KER: [4, "csi_ker selected as peripheral clock"] - LSE: [5, "LSE selected as peripheral clock"] - USART234578SEL: - RCC_PCLK1: [0, "rcc_pclk1 selected as peripheral clock"] - PLL2_Q: [1, "pll2_q selected as peripheral clock"] - PLL3_Q: [2, "pll3_q selected as peripheral clock"] - HSI_KER: [3, "hsi_ker selected as peripheral clock"] - CSI_KER: [4, "csi_ker selected as peripheral clock"] - LSE: [5, "LSE selected as peripheral clock"] - - # D3 / SRD - D3CCIPR,SRDCCIPR: - SPI6SEL: - RCC_PCLK4: [0, "rcc_pclk4 selected as peripheral clock"] - PLL2_Q: [1, "pll2_q selected as peripheral clock"] - PLL3_Q: [2, "pll3_q selected as peripheral clock"] - HSI_KER: [3, "hsi_ker selected as peripheral clock"] - CSI_KER: [4, "csi_ker selected as peripheral clock"] - HSE: [5, "HSE selected as peripheral clock"] - ADCSEL: - PLL2_P: [0, "pll2_p selected as peripheral clock"] - PLL3_R: [1, "pll3_r selected as peripheral clock"] - PER: [2, "PER selected as peripheral clock"] - LPTIM345SEL,LPTIM2SEL: - RCC_PCLK4: [0, "rcc_pclk4 selected as peripheral clock"] - PLL2_P: [1, "pll2_p selected as peripheral clock"] - PLL3_R: [2, "pll3_r selected as peripheral clock"] - LSE: [3, "LSE selected as peripheral clock"] - LSI: [4, "LSI selected as peripheral clock"] - PER: [5, "PER selected as peripheral clock"] - I2C4SEL: - RCC_PCLK4: [0, "rcc_pclk4 selected as peripheral clock"] - PLL3_R: [1, "pll3_r selected as peripheral clock"] - HSI_KER: [2, "hsi_ker selected as peripheral clock"] - CSI_KER: [3, "csi_ker selected as peripheral clock"] - LPUART1SEL: - RCC_PCLK_D3: [0, "rcc_pclk_d3 selected as peripheral clock"] - PLL2_Q: [1, "pll2_q selected as peripheral clock"] - PLL3_Q: [2, "pll3_q selected as peripheral clock"] - HSI_KER: [3, "hsi_ker selected as peripheral clock"] - CSI_KER: [4, "csi_ker selected as peripheral clock"] - LSE: [5, "LSE selected as peripheral clock"] - - # Applies to SAI2 or SAI4 when split - D3CCIPR,CDCCIP1R: - SAI*[AB]SEL: - PLL1_Q: [0, "pll1_q selected as peripheral clock"] - PLL2_P: [1, "pll2_p selected as peripheral clock"] - PLL3_P: [2, "pll3_p selected as peripheral clock"] - I2S_CKIN: [3, "i2s_ckin selected as peripheral clock"] - PER: [4, "PER selected as peripheral clock"] diff --git a/peripherals/rcc/rcc_v3_pll.yaml b/peripherals/rcc/rcc_v3_pll.yaml deleted file mode 100644 index e18faf596..000000000 --- a/peripherals/rcc/rcc_v3_pll.yaml +++ /dev/null @@ -1,101 +0,0 @@ -# Applicable at least to H7 - -# PLL registers - -RCC: - PLLCKSELR: - DIVM?: [0, 63] - PLLSRC: - HSI: [0, "HSI selected as PLL clock"] - CSI: [1, "CSI selected as PLL clock"] - HSE: [2, "HSE selected as PLL clock"] - None: [3, "No clock sent to DIVMx dividers and PLLs"] - PLLCFGR: - DIV??EN: - Disabled: [0, "Clock ouput is disabled"] - Enabled: [1, "Clock output is enabled"] - PLL?RGE: - Range1: [0, "Frequency is between 1 and 2 MHz"] - Range2: [1, "Frequency is between 2 and 4 MHz"] - Range4: [2, "Frequency is between 4 and 8 MHz"] - Range8: [3, "Frequency is between 8 and 16 MHz"] - PLL?VCOSEL: - WideVCO: [0, "VCO frequency range 192 to 836 MHz"] - MediumVCO: [1, "VCO frequency range 150 to 420 MHz"] - PLL?FRACEN: - Reset: [0, "Reset latch to tranfer FRACN to the Sigma-Delta modulator"] - Set: [1, "Set latch to tranfer FRACN to the Sigma-Delta modulator"] - PLL1DIVR: - DIVP1: - Div1: [0, "pll_p_ck = vco_ck"] - Div2: [1, "pll_p_ck = vco_ck / 2"] - Div4: [3, "pll_p_ck = vco_ck / 4"] - Div6: [5, "pll_p_ck = vco_ck / 6"] - Div8: [7, "pll_p_ck = vco_ck / 8"] - Div10: [9, "pll_p_ck = vco_ck / 10"] - Div12: [11, "pll_p_ck = vco_ck / 12"] - Div14: [13, "pll_p_ck = vco_ck / 14"] - Div16: [15, "pll_p_ck = vco_ck / 16"] - Div18: [17, "pll_p_ck = vco_ck / 18"] - Div20: [19, "pll_p_ck = vco_ck / 20"] - Div22: [21, "pll_p_ck = vco_ck / 22"] - Div24: [23, "pll_p_ck = vco_ck / 24"] - Div26: [25, "pll_p_ck = vco_ck / 26"] - Div28: [27, "pll_p_ck = vco_ck / 28"] - Div30: [29, "pll_p_ck = vco_ck / 30"] - Div32: [31, "pll_p_ck = vco_ck / 32"] - Div34: [33, "pll_p_ck = vco_ck / 34"] - Div36: [35, "pll_p_ck = vco_ck / 36"] - Div38: [37, "pll_p_ck = vco_ck / 38"] - Div40: [39, "pll_p_ck = vco_ck / 40"] - Div42: [41, "pll_p_ck = vco_ck / 42"] - Div44: [43, "pll_p_ck = vco_ck / 44"] - Div46: [45, "pll_p_ck = vco_ck / 46"] - Div48: [47, "pll_p_ck = vco_ck / 48"] - Div50: [49, "pll_p_ck = vco_ck / 50"] - Div52: [51, "pll_p_ck = vco_ck / 52"] - Div54: [53, "pll_p_ck = vco_ck / 54"] - Div56: [55, "pll_p_ck = vco_ck / 56"] - Div58: [57, "pll_p_ck = vco_ck / 58"] - Div60: [59, "pll_p_ck = vco_ck / 60"] - Div62: [61, "pll_p_ck = vco_ck / 62"] - Div64: [63, "pll_p_ck = vco_ck / 64"] - Div66: [65, "pll_p_ck = vco_ck / 66"] - Div68: [67, "pll_p_ck = vco_ck / 68"] - Div70: [69, "pll_p_ck = vco_ck / 70"] - Div72: [71, "pll_p_ck = vco_ck / 72"] - Div74: [73, "pll_p_ck = vco_ck / 74"] - Div76: [75, "pll_p_ck = vco_ck / 76"] - Div78: [77, "pll_p_ck = vco_ck / 78"] - Div80: [79, "pll_p_ck = vco_ck / 80"] - Div82: [81, "pll_p_ck = vco_ck / 82"] - Div84: [83, "pll_p_ck = vco_ck / 84"] - Div86: [85, "pll_p_ck = vco_ck / 86"] - Div88: [87, "pll_p_ck = vco_ck / 88"] - Div90: [89, "pll_p_ck = vco_ck / 90"] - Div92: [91, "pll_p_ck = vco_ck / 92"] - Div94: [93, "pll_p_ck = vco_ck / 94"] - Div96: [95, "pll_p_ck = vco_ck / 96"] - Div98: [97, "pll_p_ck = vco_ck / 98"] - Div100: [99, "pll_p_ck = vco_ck / 100"] - Div102: [101, "pll_p_ck = vco_ck / 102"] - Div104: [103, "pll_p_ck = vco_ck / 104"] - Div106: [105, "pll_p_ck = vco_ck / 106"] - Div108: [107, "pll_p_ck = vco_ck / 108"] - Div110: [109, "pll_p_ck = vco_ck / 110"] - Div112: [111, "pll_p_ck = vco_ck / 112"] - Div114: [113, "pll_p_ck = vco_ck / 114"] - Div116: [115, "pll_p_ck = vco_ck / 116"] - Div118: [117, "pll_p_ck = vco_ck / 118"] - Div120: [119, "pll_p_ck = vco_ck / 120"] - Div122: [121, "pll_p_ck = vco_ck / 122"] - Div124: [123, "pll_p_ck = vco_ck / 124"] - Div126: [125, "pll_p_ck = vco_ck / 126"] - Div128: [127, "pll_p_ck = vco_ck / 128"] - PLL2DIVR,PLL3DIVR: - DIVP?: [0, 127] - PLL?DIVR: - DIVR?,DIVQ?: [0, 127] - DIVN?: [3, 511] - PLL?FRACR: - FRACN?: [0, 0x1FFF] diff --git a/peripherals/rng/rng_v1.yaml b/peripherals/rng/rng_v1.yaml deleted file mode 100644 index 2ed4bca90..000000000 --- a/peripherals/rng/rng_v1.yaml +++ /dev/null @@ -1,10 +0,0 @@ -# Applicable to at least H7 - -RNG: - CR: - RNGEN: - Disabled: [0, "Random number generator is disabled"] - Enabled: [1, "Random number generator is enabled"] - IE: - Disabled: [0, "RNG interrupt is disabled"] - Enabled: [1, "RNG interrupt is enabled"] diff --git a/peripherals/rng/rng_v1_ced.yaml b/peripherals/rng/rng_v1_ced.yaml deleted file mode 100644 index ec733a925..000000000 --- a/peripherals/rng/rng_v1_ced.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Applicable to at least F405, F407, F427, F429 - -RNG: - CR: - CED: - Enabled: [0, "Clock error detection is enabled"] - Disabled: [1, "Clock error detection is disabled"] diff --git a/peripherals/rtc/rtc_common.yaml b/peripherals/rtc/rtc_common.yaml deleted file mode 100644 index 22e0bebeb..000000000 --- a/peripherals/rtc/rtc_common.yaml +++ /dev/null @@ -1,218 +0,0 @@ -# Real Time Clock - -RTC: - TR: - PM: - AM: [0, "AM or 24-hour format"] - PM: [1, "PM"] - HT: [0, 3] - HU: [0, 15] - MNT: [0, 7] - MNU: [0, 15] - ST: [0, 7] - SU: [0, 15] - DR: - YT: [0, 15] - YU: [0, 15] - WDU: [1, 7] - MT: [0, 1] - MU: [0, 15] - DT: [0, 3] - DU: [0, 15] - CR: - COE: - Disabled: [0, "Calibration output disabled"] - Enabled: [1, "Calibration output enabled"] - OSEL: - Disabled: [0, "Output disabled"] - AlarmA: [1, "Alarm A output enabled"] - AlarmB: [2, "Alarm B output enabled"] - Wakeup: [3, "Wakeup output enabled"] - POL: - High: [0, "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"] - Low: [1, "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"] - COSEL: - CalFreq_512Hz: [0, "Calibration output is 512 Hz (with default prescaler setting)"] - CalFreq_1Hz: [1, "Calibration output is 1 Hz (with default prescaler setting)"] - BKP: - DST_Not_Changed: [0, "Daylight Saving Time change has not been performed"] - DST_Changed: [1, "Daylight Saving Time change has been performed"] - SUB1H: - _write: - Sub1: [1, "Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode"] - ADD1H: - _write: - Add1: [1, "Adds 1 hour to the current time. This can be used for summer time change outside initialization mode"] - TSIE: - Disabled: [0, "Time-stamp Interrupt disabled"] - Enabled: [1, "Time-stamp Interrupt enabled"] - WUTIE: - Disabled: [0, "Wakeup timer interrupt disabled"] - Enabled: [1, "Wakeup timer interrupt enabled"] - ALRBIE: - Disabled: [0, "Alarm B Interrupt disabled"] - Enabled: [1, "Alarm B Interrupt enabled"] - ALRAIE: - Disabled: [0, "Alarm A interrupt disabled"] - Enabled: [1, "Alarm A interrupt enabled"] - TSE: - Disabled: [0, "Timestamp disabled"] - Enabled: [1, "Timestamp enabled"] - WUTE: - Disabled: [0, "Wakeup timer disabled"] - Enabled: [1, "Wakeup timer enabled"] - ALRBE: - Disabled: [0, "Alarm B disabled"] - Enabled: [1, "Alarm B enabled"] - ALRAE: - Disabled: [0, "Alarm A disabled"] - Enabled: [1, "Alarm A enabled"] - FMT: - Twenty_Four_Hour: [0, "24 hour/day format"] - AM_PM: [1, "AM/PM hour format"] - BYPSHAD: - ShadowReg: [0, "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles"] - BypassShadowReg: [1, "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters"] - REFCKON: - Disabled: [0, "RTC_REFIN detection disabled"] - Enabled: [1, "RTC_REFIN detection enabled"] - TSEDGE: - RisingEdge: [0, "RTC_TS input rising edge generates a time-stamp event"] - FallingEdge: [1, "RTC_TS input falling edge generates a time-stamp event"] - WUCKSEL: - Div16: [0, "RTC/16 clock is selected"] - Div8: [1, "RTC/8 clock is selected"] - Div4: [2, "RTC/4 clock is selected"] - Div2: [3, "RTC/2 clock is selected"] - ClockSpare: [4, "ck_spre (usually 1 Hz) clock is selected"] - ClockSpareWithOffset: [6, "ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value"] - ISR: - RECALPF: - _read: - Pending: [1, "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0"] - "TAMP*F": - _read: - Tampered: [1, "This flag is set by hardware when a tamper detection event is detected on the RTC_TAMPx input"] - _write: - Clear: [0, "Flag cleared by software writing 0"] - TSOVF: - _read: - Overflow: [1, "This flag is set by hardware when a time-stamp event occurs while TSF is already set"] - _write: - Clear: [0, "This flag is cleared by software by writing 0"] - TSF: - _read: - TimestampEvent: [1, "This flag is set by hardware when a time-stamp event occurs"] - _write: - Clear: [0, "This flag is cleared by software by writing 0"] - WUTF: - _read: - Zero: [1, "This flag is set by hardware when the wakeup auto-reload counter reaches 0"] - _write: - Clear: [0, "This flag is cleared by software by writing 0"] - ALRBF: - _read: - Match: [1, "This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)"] - _write: - Clear: [0, "This flag is cleared by software by writing 0"] - ALRAF: - _read: - Match: [1, "This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)"] - _write: - Clear: [0, "This flag is cleared by software by writing 0"] - INIT: - FreeRunningMode: [0, "Free running mode"] - InitMode: [1, "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."] - INITF: - _read: - NotAllowed: [0, "Calendar registers update is not allowed"] - Allowed: [1, "Calendar registers update is allowed"] - RSF: - _read: - NotSynced: [0, "Calendar shadow registers not yet synchronized"] - Synced: [1, "Calendar shadow registers synchronized"] - _write: - Clear: [0, "This flag is cleared by software by writing 0"] - INITS: - _read: - NotInitalized: [0, "Calendar has not been initialized"] - Initalized: [1, "Calendar has been initialized"] - SHPF: - _read: - NoShiftPending: [0, "No shift operation is pending"] - ShiftPending: [1, "A shift operation is pending"] - WUTWF: - _read: - UpdateNotAllowed: [0, "Wakeup timer configuration update not allowed"] - UpdateAllowed: [1, "Wakeup timer configuration update allowed"] - "ALR?WF": - _read: - UpdateNotAllowed: [0, "Alarm update not allowed"] - UpdateAllowed: [1, "Alarm update allowed"] - PRER: - PREDIV_A: [0, 0x7F] - PREDIV_S: [0, 0x7FFF] - WUTR: - WUT: [0, 0xFFFF] - "ALRM?R": - "MSK*": - Mask: [0, "Alarm set if the date/day match"] - NotMask: [1, "Date/day don’t care in Alarm comparison"] - WDSEL: - DateUnits: [0, "DU[3:0] represents the date units"] - WeekDay: [1, "DU[3:0] represents the week day. DT[1:0] is don’t care."] - DT: [0, 3] - DU: [0, 15] - PM: - AM: [0, "AM or 24-hour format"] - PM: [1, "PM"] - HT: [0, 3] - HU: [0, 15] - MNT: [0, 7] - MNU: [0, 15] - ST: [0, 7] - SU: [0, 15] - WPR: - KEY: [0, 255] - SSR: - SS: [0, 65535] - SHIFTR: - ADD1S: - _write: - Add1: [1, "Add one second to the clock/calendar"] - SUBFS: [0, 32767] - TSTR: - _read: - PM: - AM: [0, "AM or 24-hour format"] - PM: [1, "PM"] - HT: [0, 3] - HU: [0, 15] - MNT: [0, 7] - MNU: [0, 15] - ST: [0, 7] - SU: [0, 15] - TSDR: - _read: - WDU: [0, 3] - MT: [0, 1] - MU: [0, 7] - DT: [0, 3] - DU: [0, 15] - TSSSR: - _read: - SS: [0, 65535] - CALR: - CALP: - NoChange: [0, "No RTCCLK pulses are added"] - IncreaseFreq: [1, "One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)"] - CALW8: - Eight_Second: [1, "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"] - CALW16: - Sixteen_Second: [1, "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1"] - CALM: [0, 511] - "ALRM?SSR": - MASKSS: [0, 15] - SS: [0, 32767] - "BKP?R": - BKP: [0, 0xFFFFFFFF] diff --git a/peripherals/rtc/rtc_f1.yaml b/peripherals/rtc/rtc_f1.yaml deleted file mode 100644 index 0ac51e492..000000000 --- a/peripherals/rtc/rtc_f1.yaml +++ /dev/null @@ -1,58 +0,0 @@ -RTC: - CRH: - OWIE: - Disabled: [0, "Overflow interrupt is masked"] - Enabled: [1, "Overflow interrupt is enabled"] - ALRIE: - Disabled: [0, "Alarm interrupt is masked"] - Enabled: [1, "Alarm interrupt is enabled"] - SECIE: - Disabled: [0, "Second interrupt is masked"] - Enabled: [1, "Second interrupt is enabled"] - CRL: - RTOFF: - Enabled: [0, "Last write operation on RTC registers is still ongoing"] - Disabled: [1, "Last write operation on RTC registers terminated"] - CNF: - Exit: [0, "Exit configuration mode (start update of RTC registers)"] - Enter: [1, "Enter configuration mode"] - RSF: - _read: - NotSynchronized: [0, "Registers not yet synchronized"] - Synchronized: [1, "Registers synchronized"] - _write: - Clear: [0, "Clear flag"] - OWF: - _read: - NoOverflow: [0, "Overflow not detected"] - Overflow: [1, "32-bit programmable counter overflow occurred"] - _write: - Clear: [0, "Clear flag"] - ALRF: - _read: - NoAlarm: [0, "Alarm not detected"] - Alarm: [1, "Alarm detected"] - _write: - Clear: [0, "Clear flag"] - SECF: - _read: - NoPrescalerOverflow: [0, "Second flag condition not met"] - PrescalerOverflow: [1, "Second flag condition met"] - _write: - Clear: [0, "Clear flag"] - PRLH: - PRLH: [0, 0xF] - PRLL: - PRLL: [0, 0xFFFF] - DIVH: - DIVH: [0, 0xF] - DIVL: - DIVL: [0, 0xFFFF] - CNTH: - CNTH: [0, 0xFFFF] - CNTL: - CNTL: [0, 0xFFFF] - ALRH: - ALRH: [0, 0xFFFF] - ALRL: - ALRL: [0, 0xFFFF] diff --git a/peripherals/rtc/rtc_f3.yaml b/peripherals/rtc/rtc_f3.yaml deleted file mode 100644 index ee022fe35..000000000 --- a/peripherals/rtc/rtc_f3.yaml +++ /dev/null @@ -1,44 +0,0 @@ -# Real Time Clock for F3 Family - -RTC: - TAFCR: - "PC*MODE": - Floating: [0, "PCx is controlled by the GPIO configuration Register. Consequently PC15 is floating in Standby mode"] - PushPull: [1, "PCx is forced to push-pull output if LSE is disabled"] - "PC*VALUE": - High: [1, "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic high"] - Low: [0, "If the LSE is disabled and PCxMODE = 1, set PCxVALUE to logic low"] - TAMPPUDIS: - Enabled: [0, "Precharge RTC_TAMPx pins before sampling (enable internal pull-up)"] - Disabled: [1, "Disable precharge of RTC_TAMPx pins"] - TAMPPRCH: - Cycles1: [0, "1 RTCCLK cycle"] - Cycles2: [1, "2 RTCCLK cycles"] - Cycles4: [2, "4 RTCCLK cycles"] - Cycles8: [3, "8 RTCCLK cycles"] - TAMPFLT: - Immediate: [0, "Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input)"] - Samples2: [1, "Tamper event is activated after 2 consecutive samples at the active level"] - Samples4: [2, "Tamper event is activated after 4 consecutive samples at the active level"] - Samples8: [3, "Tamper event is activated after 8 consecutive samples at the active level"] - TAMPFREQ: - Div32768: [0, "RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)"] - Div16384: [1, "RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)"] - Div8192: [2, "RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)"] - Div4096: [3, "RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)"] - Div2048: [4, "RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)"] - Div1024: [5, "RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)"] - Div512: [6, "RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)"] - Div256: [7, "RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"] - TAMPTS: - NoSave: [0, "Tamper detection event does not cause a timestamp to be saved"] - Save: [1, "Save timestamp on tamper detection event"] - "TAMP*TRG": - RisingEdge: [0, "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event."] - FallingEdge: [1, "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event"] - "TAMP[123]E": - Disabled: [0, "RTC_TAMPx input detection disabled"] - Enabled: [1, "RTC_TAMPx input detection enabled"] - TAMPIE: - Disabled: [0, "Tamper interrupt disabled"] - Enabled: [1, "Tamper interrupt enabled"] diff --git a/peripherals/rtc/rtc_l0.yaml b/peripherals/rtc/rtc_l0.yaml deleted file mode 100644 index 8c5ffdf82..000000000 --- a/peripherals/rtc/rtc_l0.yaml +++ /dev/null @@ -1,50 +0,0 @@ -# Real Time Clock for L0 Family - -RTC: - TAMPCR: - "TAMP*MF": - NotMasked: [0, "Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection"] - Masked: [1, "Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased."] - "TAMP*NOERASE": - Erase: [0, "Tamper x event erases the backup registers"] - NoErase: [1, "Tamper x event does not erase the backup registers"] - "TAMP[123]IE": - Disabled: [0, "Tamper x interrupt is disabled if TAMPIE = 0"] - Enabled: [1, "Tamper x interrupt enabled"] - TAMPPUDIS: - Enabled: [0, "Precharge RTC_TAMPx pins before sampling (enable internal pull-up)"] - Disabled: [1, "Disable precharge of RTC_TAMPx pins"] - TAMPPRCH: - Cycles1: [0, "1 RTCCLK cycle"] - Cycles2: [1, "2 RTCCLK cycles"] - Cycles4: [2, "4 RTCCLK cycles"] - Cycles8: [3, "8 RTCCLK cycles"] - TAMPFLT: - Immediate: [0, "Tamper event is activated on edge of RTC_TAMPx input transitions to the active level (no internal pull-up on RTC_TAMPx input)"] - Samples2: [1, "Tamper event is activated after 2 consecutive samples at the active level"] - Samples4: [2, "Tamper event is activated after 4 consecutive samples at the active level"] - Samples8: [3, "Tamper event is activated after 8 consecutive samples at the active level"] - TAMPFREQ: - Div32768: [0, "RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)"] - Div16384: [1, "RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)"] - Div8192: [2, "RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)"] - Div4096: [3, "RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)"] - Div2048: [4, "RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)"] - Div1024: [5, "RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)"] - Div512: [6, "RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)"] - Div256: [7, "RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"] - TAMPTS: - NoSave: [0, "Tamper detection event does not cause a timestamp to be saved"] - Save: [1, "Save timestamp on tamper detection event"] - "TAMP*TRG": - RisingEdge: [0, "If TAMPFLT = 00: RTC_TAMPx input rising edge triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input staying low triggers a tamper detection event."] - FallingEdge: [1, "If TAMPFLT = 00: RTC_TAMPx input staying high triggers a tamper detection event. If TAMPFLT ≠ 00: RTC_TAMPx input falling edge triggers a tamper detection event"] - "TAMP[123]E": - Disabled: [0, "RTC_TAMPx input detection disabled"] - Enabled: [1, "RTC_TAMPx input detection enabled"] - TAMPIE: - Disabled: [0, "Tamper interrupt disabled"] - Enabled: [1, "Tamper interrupt enabled"] - OR: - RTC_OUT_RMP: [0, 1] - RTC_ALARM_TYPE: [0, 1] diff --git a/peripherals/sai/sai.yaml b/peripherals/sai/sai.yaml deleted file mode 100644 index 1c4afe2ca..000000000 --- a/peripherals/sai/sai.yaml +++ /dev/null @@ -1,173 +0,0 @@ -"SAI,SAI?": - "*CR1": - #MCKDIV: - NODIV: - MasterClock: [0, "Master clock generator is enabled"] - NoDiv: [1, "No divider used in the clock generator (in this case Master Clock Divider bit has no effect)"] - DMAEN: - Disabled: [0, "DMA disabled"] - Enabled: [1, "DMA enabled"] - SAIEN: - Disabled: [0, "SAI audio block disabled"] - Enabled: [1, "SAI audio block enabled"] - OUTDRIV: - OnStart: [0, "Audio block output driven when SAIEN is set"] - Immediately: [1, "Audio block output driven immediately after the setting of this bit"] - MONO: - Stereo: [0, "Stereo mode"] - Mono: [1, "Mono mode"] - SYNCEN: - Asynchronous: [0, "audio sub-block in asynchronous mode"] - Internal: [1, "audio sub-block is synchronous with the other internal audio sub-block. In this case, the audio sub-block must be configured in slave mode"] - External: [2, "audio sub-block is synchronous with an external SAI embedded peripheral. In this case the audio sub-block should be configured in Slave mode"] - CKSTR: - FallingEdge: [0, "Data strobing edge is falling edge of SCK"] - RisingEdge: [1, "Data strobing edge is rising edge of SCK"] - LSBFIRST: - MsbFirst: [0, "Data are transferred with MSB first"] - LsbFirst: [1, "Data are transferred with LSB first"] - DS: - Bit8: [2, "8 bits"] - Bit10: [3, "10 bits"] - Bit16: [4, "16 bits"] - Bit20: [5, "20 bits"] - Bit24: [6, "24 bits"] - Bit32: [7, "32 bits"] - PRTCFG: - Free: [0, "Free protocol. Free protocol allows to use the powerful configuration of the audio block to address a specific audio protocol"] - Spdif: [1, "SPDIF protocol"] - Ac97: [2, "AC’97 protocol"] - MODE: - MasterTx: [0, "Master transmitter"] - MasterRx: [1, "Master receiver"] - SlaveTx: [2, "Slave transmitter"] - SlaveRx: [3, "Slave receiver"] - - "*CR2": - COMP: - NoCompanding: [0, "No companding algorithm"] - MuLaw: [2, "μ-Law algorithm"] - ALaw: [3, "A-Law algorithm"] - CPL: - OnesComplement: [0, "1’s complement representation"] - TwosComplement: [1, "2’s complement representation"] - #MUTECNT: - MUTEVAL: - SendZero: [0, "Bit value 0 is sent during the mute mode"] - SendLast: [1, "Last values are sent during the mute mode"] - MUTE: - Disabled: [0, "No mute mode"] - Enabled: [1, "Mute mode enabled"] - #TRIS: - FFLUSH: - NoFlush: [0, "No FIFO flush"] - Flush: [1, "FIFO flush. Programming this bit to 1 triggers the FIFO Flush. All the internal FIFO pointers (read and write) are cleared"] - FTH: - Empty: [0, "FIFO empty"] - Quarter1: [1, "1⁄4 FIFO"] - Quarter2: [2, "1⁄2 FIFO"] - Quarter3: [3, "3⁄4 FIFO"] - Full: [4, "FIFO full"] - - "*FRCR": - FSOFF: - OnFirst: [0, "FS is asserted on the first bit of the slot 0"] - BeforeFirst: [1, "FS is asserted one bit before the first bit of the slot 0"] - FSPOL: - FallingEdge: [0, "FS is active low (falling edge)"] - RisingEdge: [1, "FS is active high (rising edge)"] - #FSDEF: - #FSALL: - #FRL: - - "*SLOTR": - SLOTEN: - Inactive: [0, "Inactive slot"] - Active: [1, "Active slot"] - #NBSLOT: - SLOTSZ: - DataSize: [0, "The slot size is equivalent to the data size (specified in DS[3:0] in the SAI_xCR1 register)"] - Bit16: [1, "16-bit"] - Bit32: [2, "32-bit"] - #FBOFF: - - "*IM": - LFSDETIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is enabled"] - AFSDETIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is enabled"] - CNRDYIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is enabled"] - FREQIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is enabled"] - WCKCFGIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is enabled"] - MUTEDETIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is enabled"] - OVRUDRIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is enabled"] - - "*SR": - FLVL: - _read: - Empty: [0, "FIFO empty"] - Quarter1: [1, "FIFO <= 1⁄4 but not empty"] - Quarter2: [2, "1⁄4 < FIFO <= 1⁄2"] - Quarter3: [3, "1⁄2 < FIFO <= 3⁄4"] - Quarter4: [4, "3⁄4 < FIFO but not full"] - Full: [5, "FIFO full"] - LFSDET: - _read: - NoError: [0, "No error"] - NoSync: [1, "Frame synchronization signal is not present at the right time"] - AFSDET: - _read: - NoError: [0, "No error"] - EarlySync: [1, "Frame synchronization signal is detected earlier than expected"] - CNRDY: - _read: - Ready: [0, "External AC’97 Codec is ready"] - NotReady: [1, "External AC’97 Codec is not ready"] - FREQ: - _read: - NoRequest: [0, "No FIFO request"] - Request: [1, "FIFO request to read or to write the SAI_xDR"] - WCKCFG: - _read: - Correct: [0, "Clock configuration is correct"] - Wrong: [1, "Clock configuration does not respect the rule concerning the frame length specification"] - MUTEDET: - _read: - NoMute: [0, "No MUTE detection on the SD input line"] - Mute: [1, "MUTE value detected on the SD input line (0 value) for a specified number of consecutive audio frame"] - OVRUDR: - _read: - NoError: [0, "No overrun/underrun error"] - Overrun: [1, "Overrun/underrun error detection"] - - "*CLRFR": - CLFSDET: - _write: - Clear: [1, "Clears the LFSDET flag"] - CAFSDET: - _write: - Clear: [1, "Clears the AFSDET flag"] - CCNRDY: - _write: - Clear: [1, "Clears the CNRDY flag"] - CWCKCFG: - _write: - Clear: [1, "Clears the WCKCFG flag"] - CMUTEDET: - _write: - Clear: [1, "Clears the MUTEDET flag"] - COVRUDR: - _write: - Clear: [1, "Clears the OVRUDR flag"] diff --git a/peripherals/sdio/sdio.yaml b/peripherals/sdio/sdio.yaml deleted file mode 100644 index 098c71a25..000000000 --- a/peripherals/sdio/sdio.yaml +++ /dev/null @@ -1,6 +0,0 @@ -SDIO: - _array: - "RESP?": - _modify: - CARDSTATUS1: - name: CARDSTATUS diff --git a/peripherals/sdio/sdio_f4.yaml b/peripherals/sdio/sdio_f4.yaml deleted file mode 100644 index 276b79e2a..000000000 --- a/peripherals/sdio/sdio_f4.yaml +++ /dev/null @@ -1,25 +0,0 @@ -_include: - - sdio_f4_common.yaml - -SDIO: - CMD: - CE_ATACMD: - Disabled: [0, "CE-ATA command disabled"] - Enabled: [1, "CE-ATA command enabled"] - nIEN: - Disabled: [0, "Interrupts to the CE-ATA not disabled"] - Enabled: [1, "Interrupt to the CE-ATA are disabled"] - ENCMDcompl: - Disabled: [0, "Command complete signal disabled"] - Enabled: [1, "Command complete signal enabled"] - - STA: - CEATAEND: - NotReceived: [0, "Completion signal not received"] - Received: [1, "CE-ATA command completion signal received for CMD61"] - STBITERR: - Detected: [0, "No start bit detected error"] - NotDetected: [1, "Start bit not detected error"] - - DCTRL: - DBLOCKSIZE: [0, 0xF] \ No newline at end of file diff --git a/peripherals/sdio/sdio_f4_common.yaml b/peripherals/sdio/sdio_f4_common.yaml deleted file mode 100644 index cc713264f..000000000 --- a/peripherals/sdio/sdio_f4_common.yaml +++ /dev/null @@ -1,181 +0,0 @@ -SDIO: - POWER: - PWRCTRL: - PowerOff: [0, "Power off"] - PowerOn: [3, "Power on"] - - CLKCR: - HWFC_EN: - Disabled: [0, "HW Flow Control is disabled"] - Enabled: [1, "HW Flow Control is enabled"] - NEGEDGE: - Rising: [0, "SDIO_CK generated on the rising edge"] - Falling: [1, "SDIO_CK generated on the falling edge"] - WIDBUS: - BusWidth1: [0, "1 lane wide bus"] - BusWidth4: [1, "4 lane wide bus"] - BusWidth8: [2, "8 lane wide bus"] - BYPASS: - Disabled: [0, "SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal."] - Enabled: [1, "SDIOCLK directly drives the SDIO_CK output signal"] - PWRSAV: - Disabled: [1, "SDIO_CK is only enabled when the bus is active"] - Enabled: [0, "SDIO_CK clock is always enabled"] - CLKEN: - Disabled: [0, "Disable clock"] - Enabled: [1, "Enable clock"] - CLKDIV: [0, 0xFF] - - ARG: - CMDARG: [0, 0xFFFFFFFF] - - CMD: - SDIOSuspend: - Disabled: [0, "Next command is not a SDIO suspend command"] - Enabled: [1, "Next command send is a SDIO suspend command"] - CPSMEN: - Disabled: [0, "Command path state machine disabled"] - Enabled: [1, "Command path state machine enabled"] - WAITPEND: - Disabled: [0, "Don't wait for data end"] - Enabled: [1, "Wait for end of data transfer signal before sending command"] - WAITINT: - Disabled: [0, "Don't wait for interrupt request"] - Enabled: [1, "Wait for interrupt request"] - WAITRESP: - NoResponse: [0, "No response"] - ShortResponse: [1, "Short response"] - NoResponse2: [2, "No reponse"] - LongResponse: [3, "Long reponse"] - CMDINDEX: [0, 0x3F] - - RESPCMD: - RESPCMD: [0, 0x3F] - - RESP1: - CARDSTATUS1: [0, 0xFFFFFFFF] - RESP2: - CARDSTATUS2: [0, 0xFFFFFFFF] - RESP3: - CARDSTATUS3: [0, 0xFFFFFFFF] - RESP4: - CARDSTATUS4: [0, 0xFFFFFFFF] - - DTIMER: - DATATIME: [0, 0xFFFFFFFF] - - DLEN: - DATALENGTH: [0, 0x01FFFFFF] - - DCTRL: - SDIOEN: - Disabled: [0, "SDIO operations disabled"] - Enabled: [1, "SDIO operations enabled"] - RWMOD: - D2: [0, "Read wait control stopping using SDIO_D2"] - Ck: [1, "Read wait control using SDIO_CK"] - RWSTOP: - Disabled: [0, "Read wait in progress if RWSTART is enabled"] - Enabled: [1, "Enable for read wait stop if RWSTART is enabled"] - RWSTART: - Disabled: [0, "Don't start read wait operation"] - Enabled: [1, "Read wait operation starts"] - DMAEN: - Disabled: [0, "Dma disabled"] - Enabled: [1, "Dma enabled"] - DTMODE: - BlockMode: [0, "Bloack data transfer"] - StreamMode: [1, "Stream or SDIO multibyte data transfer"] - DTDIR: - ControllerToCard: [0, "From controller to card"] - CardToController: [1, "From card to controller"] - DTEN: - Disabled: [0, "Disabled"] - Enabled: [1, "Start transfer"] - - DCOUNT: - DATACOUNT: [0, 0x01FFFFFF] - - STA: - SDIOIT: - NotReceived: [0, "SDIO interrupt not receieved"] - Received: [1, "SDIO interrupt received"] - RXDAVL: - NotAvailable: [0, "Data not available in receive FIFO"] - Available: [1, "Data available in receive FIFO"] - TXDAVL: - NotAvailable: [0, "Data not available in transmit FIFO"] - Available: [1, "Data available in transmit FIFO"] - RXFIFOE: - NotEmpty: [0, "Receive FIFO not empty"] - Empty: [1, "Receive FIFO empty"] - TXFIFOE: - NotEmpty: [0, "Transmit FIFO not empty"] - Empty: [1, "Transmit FIFO empty. When HW Flow Control is enabled, TXFIFOE signals becomes activated when the FIFO contains 2 words."] - RXFIFOF: - NotFull: [0, "Transmit FIFO not full"] - Full: [1, "Receive FIFO full. When HW Flow Control is enabled, RXFIFOF signals becomes activated 2 words before the FIFO is full."] - TXFIFOF: - NotFull: [0, "Transmit FIFO not full"] - Full: [1, "Transmit FIFO full"] - RXFIFOHF: - NotHalfFull: [0, "Receive FIFO not half full"] - HalfFull: [1, "Receive FIFO half full. At least 8 words in the FIFO"] - TXFIFOHE: - NotHalfEmpty: [0, "Transmit FIFO not half empty"] - HalfEmpty: [1, "Transmit FIFO half empty. At least 8 words can be written into the FIFO"] - RXACT: - NotInProgress: [0, "Data receive not in progress"] - InProgress: [1, "Data receive in progress"] - TXACT: - NotInProgress: [0, "Data transmit is not in progress"] - InProgress: [1, "Data transmit in progress"] - CMDACT: - NotInProgress: [0, "Command transfer not in progress"] - InProgress: [1, "Command tranfer in progress"] - DBCKEND: - NotTransferred: [0, "Data block not sent/received (CRC check failed)"] - Transferred: [1, "Data block sent/received (CRC check passed)"] - DATAEND: - Done: [1, "Data end (DCOUNT, is zero)"] - NotDone: [0, "Not done"] - CMDSENT: - NotSent: [0, "Command not sent"] - Sent: [1, "Command sent (no response required)"] - CMDREND: - NotDone: [0, "Command not done"] - Done: [1, "Command response received (CRC check passed)"] - RXOVERR: - NoOverrun: [0, "No FIFO overrun error"] - Overrun: [1, "Receive FIFO overrun error"] - TXUNDERR: - NoUnderrun: [0, "No transmit FIFO underrun error"] - Underrun: [1, "Transmit FIFO underrun error"] - DTIMEOUT: - NoTimeout: [0, "No data timeout"] - Timeout: [1, "Data timeout"] - CTIMEOUT: - NoTimeout: [0, "No Command timeout"] - Timeout: [1, "Command timeout"] - DCRCFAIL: - NotFailed: [0, "No Data block sent/received crc check fail"] - Failed: [1, "Data block sent/received crc failed"] - CCRCFAIL: - NotFailed: [0, "Command response received, crc check passed"] - Failed: [1, "Command response received, crc check failed"] - - ICR: - "*C": - _write: - Clear: [1, "Clear flag"] - - MASK: - "*IE": - Disabled: [0, "Interrupt disabled"] - Enabled: [1, "Interrupt enabled"] - - FIFOCNT: - FIFOCOUNT: [0, 0x00FFFFFF] - - FIFO: - FIFOData: [0, 0xFFFFFFFF] diff --git a/peripherals/spi/spi_FRF_FRE.yaml b/peripherals/spi/spi_FRF_FRE.yaml deleted file mode 100644 index d5cf30f05..000000000 --- a/peripherals/spi/spi_FRF_FRE.yaml +++ /dev/null @@ -1,10 +0,0 @@ -"SPI*,I2S*": - CR2: - FRF: - Motorola: [0, "SPI Motorola mode"] - TI: [1, "SPI TI mode"] - SR: - FRE,TIFRFE: - _read: - NoError: [0, "No frame format error"] - Error: [1, "A frame format error occurred"] diff --git a/peripherals/spi/spi_I2S.yaml b/peripherals/spi/spi_I2S.yaml deleted file mode 100644 index 1b07fd758..000000000 --- a/peripherals/spi/spi_I2S.yaml +++ /dev/null @@ -1,39 +0,0 @@ -"SPI*,I2S*": - I2SCFGR: - I2SMOD: - SPIMode: [0, "SPI mode is selected"] - I2SMode: [1, "I2S mode is selected"] - I2SE: - Disabled: [0, "I2S peripheral is disabled"] - Enabled: [1, "I2S peripheral is enabled"] - I2SCFG: - SlaveTx: [0, "Slave - transmit"] - SlaveRx: [1, "Slave - receive"] - MasterTx: [2, "Master - transmit"] - MasterRx: [3, "Master - receive"] - PCMSYNC: - Short: [0, "Short frame synchronisation"] - Long: [1, "Long frame synchronisation"] - I2SSTD: - Philips: [0, "I2S Philips standard"] - MSB: [1, "MSB justified standard"] - LSB: [2, "LSB justified standard"] - PCM: [3, "PCM standard"] - CKPOL: - IdleLow: [0, "I2S clock inactive state is low level"] - IdleHigh: [1, "I2S clock inactive state is high level"] - DATLEN: - SixteenBit: [0, "16-bit data length"] - TwentyFourBit: [1, "24-bit data length"] - ThirtyTwoBit: [2, "32-bit data length"] - CHLEN: - SixteenBit: [0, "16-bit wide"] - ThirtyTwoBit: [1, "32-bit wide"] - I2SPR: - MCKOE: - Disabled: [0, "Master clock output is disabled"] - Enabled: [1, "Master clock output is enabled"] - ODD: - Even: [0, "Real divider value is I2SDIV * 2"] - Odd: [1, "Real divider value is (I2SDIV * 2) + 1"] - I2SDIV: [2, 255] diff --git a/peripherals/spi/spi_SR_UDR_CHSIDE.yaml b/peripherals/spi/spi_SR_UDR_CHSIDE.yaml deleted file mode 100644 index 251a26987..000000000 --- a/peripherals/spi/spi_SR_UDR_CHSIDE.yaml +++ /dev/null @@ -1,9 +0,0 @@ -"SPI*,I2S*": - SR: - UDR: - _read: - NoUnderrun: [0, "No underrun occurred"] - Underrun: [1, "Underrun occurred"] - CHSIDE: - Left: [0, "Channel left has to be transmitted or has been received"] - Right: [1, "Channel right has to be transmitted or has been received"] diff --git a/peripherals/spi/spi_common.yaml b/peripherals/spi/spi_common.yaml deleted file mode 100644 index ddca9d678..000000000 --- a/peripherals/spi/spi_common.yaml +++ /dev/null @@ -1,100 +0,0 @@ -# Common fields between SPIv1 and SPIv2 (most of them) -# Note that frustratingly the peripheral everything else derives from -# is occasionally I2S2ext instead of SPI1 in the SVD. - -"SPI*,I2S*": - CR1: - BIDIMODE: - Unidirectional: [0, "2-line unidirectional data mode selected"] - Bidirectional: [1, "1-line bidirectional data mode selected"] - BIDIOE: - OutputDisabled: [0, "Output disabled (receive-only mode)"] - OutputEnabled: [1, "Output enabled (transmit-only mode)"] - CRCEN: - Disabled: [0, "CRC calculation disabled"] - Enabled: [1, "CRC calculation enabled"] - CRCNEXT: - TxBuffer: [0, "Next transmit value is from Tx buffer"] - CRC: [1, "Next transmit value is from Tx CRC register"] - RXONLY: - FullDuplex: [0, "Full duplex (Transmit and receive)"] - OutputDisabled: [1, "Output disabled (Receive-only mode)"] - SSM: - Disabled: [0, "Software slave management disabled"] - Enabled: [1, "Software slave management enabled"] - SSI: - SlaveSelected: [0, "0 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] - SlaveNotSelected: [1, "1 is forced onto the NSS pin and the I/O value of the NSS pin is ignored"] - LSBFIRST: - MSBFirst: [0, "Data is transmitted/received with the MSB first"] - LSBFirst: [1, "Data is transmitted/received with the LSB first"] - SPE: - Disabled: [0, "Peripheral disabled"] - Enabled: [1, "Peripheral enabled"] - BR: - Div2: [0, "f_PCLK / 2"] - Div4: [1, "f_PCLK / 4"] - Div8: [2, "f_PCLK / 8"] - Div16: [3, "f_PCLK / 16"] - Div32: [4, "f_PCLK / 32"] - Div64: [5, "f_PCLK / 64"] - Div128: [6, "f_PCLK / 128"] - Div256: [7, "f_PCLK / 256"] - MSTR: - Slave: [0, "Slave configuration"] - Master: [1, "Master configuration"] - CPOL: - IdleLow: [0, "CK to 0 when idle"] - IdleHigh: [1, "CK to 1 when idle"] - CPHA: - FirstEdge: [0, "The first clock transition is the first data capture edge"] - SecondEdge: [1, "The second clock transition is the first data capture edge"] - CR2: - TXEIE: - Masked: [0, "TXE interrupt masked"] - NotMasked: [1, "TXE interrupt not masked"] - RXNEIE: - Masked: [0, "RXE interrupt masked"] - NotMasked: [1, "RXE interrupt not masked"] - ERRIE: - Masked: [0, "Error interrupt masked"] - NotMasked: [1, "Error interrupt not masked"] - SSOE: - Disabled: [0, "SS output is disabled in master mode"] - Enabled: [1, "SS output is enabled in master mode"] - TXDMAEN: - Disabled: [0, "Tx buffer DMA disabled"] - Enabled: [1, "Tx buffer DMA enabled"] - RXDMAEN: - Disabled: [0, "Rx buffer DMA disabled"] - Enabled: [1, "Rx buffer DMA enabled"] - SR: - BSY: - _read: - NotBusy: [0, "SPI not busy"] - Busy: [1, "SPI busy"] - OVR: - _read: - NoOverrun: [0, "No overrun occurred"] - Overrun: [1, "Overrun occurred"] - MODF: - _read: - NoFault: [0, "No mode fault occurred"] - Fault: [1, "Mode fault occurred"] - CRCERR: - Match: [0, "CRC value received matches the SPIx_RXCRCR value"] - NoMatch: [1, "CRC value received does not match the SPIx_RXCRCR value"] - TXE: - NotEmpty: [0, "Tx buffer not empty"] - Empty: [1, "Tx buffer empty"] - RXNE: - Empty: [0, "Rx buffer empty"] - NotEmpty: [1, "Rx buffer not empty"] - DR: - DR: [0, 65535] - CRCPR: - CRCPOLY: [0, 65535] - RXCRCR: - RxCRC: [0, 65535] - TXCRCR: - TxCRC: [0, 65535] diff --git a/peripherals/spi/spi_l0.yaml b/peripherals/spi/spi_l0.yaml deleted file mode 100644 index d50c5b7cd..000000000 --- a/peripherals/spi/spi_l0.yaml +++ /dev/null @@ -1,10 +0,0 @@ -# SPI for L0 - -_include: - - "spi_common.yaml" - -"SPI*,I2S*": - CR1: - DFF: - EightBit: [0, "8-bit data frame format is selected for transmission/reception"] - SixteenBit: [1, "16-bit data frame format is selected for transmission/reception"] diff --git a/peripherals/spi/spi_v1.yaml b/peripherals/spi/spi_v1.yaml deleted file mode 100644 index 115aac3e3..000000000 --- a/peripherals/spi/spi_v1.yaml +++ /dev/null @@ -1,5 +0,0 @@ -# SPIv1 is used on F1 and F4 - -_include: - - "spi_v1_without_FRF_FRE.yaml" - - "spi_FRF_FRE.yaml" diff --git a/peripherals/spi/spi_v1_without_FRF_FRE.yaml b/peripherals/spi/spi_v1_without_FRF_FRE.yaml deleted file mode 100644 index 6d78624b7..000000000 --- a/peripherals/spi/spi_v1_without_FRF_FRE.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# SPIv1 is used on F1 and F4 - -_include: - - "spi_v1_without_FRF_FRE_UDR_CHSIDE.yaml" - - "spi_SR_UDR_CHSIDE.yaml" - - "spi_I2S.yaml" diff --git a/peripherals/spi/spi_v1_without_FRF_FRE_UDR_CHSIDE.yaml b/peripherals/spi/spi_v1_without_FRF_FRE_UDR_CHSIDE.yaml deleted file mode 100644 index dd3d2de60..000000000 --- a/peripherals/spi/spi_v1_without_FRF_FRE_UDR_CHSIDE.yaml +++ /dev/null @@ -1,10 +0,0 @@ -# SPIv1 is used on F1 and F4 - -_include: - - "spi_common.yaml" - -"SPI*,I2S*": - CR1: - DFF: - EightBit: [0, "8-bit data frame format is selected for transmission/reception"] - SixteenBit: [1, "16-bit data frame format is selected for transmission/reception"] diff --git a/peripherals/spi/spi_v2.yaml b/peripherals/spi/spi_v2.yaml deleted file mode 100644 index 0dac1c8cc..000000000 --- a/peripherals/spi/spi_v2.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# SPI for F0x1, F0x2, F0x8, F3, F7 -# it includes all that the F0x0 has plus SR has UDR and CHSIDE - -_include: - - "spi_v2_without_UDR_CHSIDE.yaml" - - "spi_SR_UDR_CHSIDE.yaml" diff --git a/peripherals/spi/spi_v2_without_UDR_CHSIDE.yaml b/peripherals/spi/spi_v2_without_UDR_CHSIDE.yaml deleted file mode 100644 index 0533daf50..000000000 --- a/peripherals/spi/spi_v2_without_UDR_CHSIDE.yaml +++ /dev/null @@ -1,52 +0,0 @@ -# SPI for F0x0 - -_include: - - "spi_common.yaml" - - "spi_FRF_FRE.yaml" - - "spi_I2S.yaml" - -"SPI*": - CR1: - CRCL: - EightBit: [0, "8-bit CRC length"] - SixteenBit: [1, "16-bit CRC length"] - CR2: - LDMA_TX: - Even: [0, "Number of data to transfer for transmit is even"] - Odd: [1, "Number of data to transfer for transmit is odd"] - LDMA_RX: - Even: [0, "Number of data to transfer for receive is even"] - Odd: [1, "Number of data to transfer for receive is odd"] - FRXTH: - Half: [0, "RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)"] - Quarter: [1, "RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)"] - DS: - FourBit: [3, "4-bit"] - FiveBit: [4, "5-bit"] - SixBit: [5, "6-bit"] - SevenBit: [6, "7-bit"] - EightBit: [7, "8-bit"] - NineBit: [8, "9-bit"] - TenBit: [9, "10-bit"] - ElevenBit: [10, "11-bit"] - TwelveBit: [11, "12-bit"] - ThirteenBit: [12, "13-bit"] - FourteenBit: [13, "14-bit"] - FifteenBit: [14, "15-bit"] - SixteenBit: [15, "16-bit"] - NSSP: - NoPulse: [0, "No NSS pulse"] - PulseGenerated: [1, "NSS pulse generated"] - SR: - FTLVL: - _read: - Empty: [0, "Tx FIFO Empty"] - Quarter: [1, "Tx 1/4 FIFO"] - Half: [2, "Tx 1/2 FIFO"] - Full: [3, "Tx FIFO full"] - FRLVL: - _read: - Empty: [0, "Rx FIFO Empty"] - Quarter: [1, "Rx 1/4 FIFO"] - Half: [2, "Rx 1/2 FIFO"] - Full: [3, "Rx FIFO full"] diff --git a/peripherals/spi/spi_v3.yaml b/peripherals/spi/spi_v3.yaml deleted file mode 100644 index d51d06cab..000000000 --- a/peripherals/spi/spi_v3.yaml +++ /dev/null @@ -1,283 +0,0 @@ -"SPI*": - CR1: - IOLOCK: - Unlocked: [0, "IO configuration unlocked"] - Locked: [1, "IO configuration locked"] - TCRCINI: - AllZeros: [0, "All zeros TX CRC initialization pattern"] - AllOnes: [1, "All ones TX CRC initialization pattern"] - RCRCINI: - AllZeros: [0, "All zeros RX CRC initialization pattern"] - AllOnes: [1, "All ones RX CRC initialization pattern"] - CRC33_17: - Disabled: [0, "Full size (33/17 bit) CRC polynomial is not used"] - Enabled: [1, "Full size (33/17 bit) CRC polynomial is used"] - SSI: - SlaveSelected: [0, "0 is forced onto the SS signal and the I/O value of the SS pin is ignored"] - SlaveNotSelected: [1, "1 is forced onto the SS signal and the I/O value of the SS pin is ignored"] - HDDIR: - Receiver: [0, "Receiver in half duplex mode"] - Transmitter: [1, "Transmitter in half duplex mode"] - CSUSP: - _write: - NotRequested: [0, "Do not request master suspend"] - Requested: [1, "Request master suspend"] - CSTART: - NotStarted: [0, "Do not start master transfer"] - Started: [1, "Start master transfer"] - MASRX: - Disabled: [0, "Automatic suspend in master receive-only mode disabled"] - Enabled: [1, "Automatic suspend in master receive-only mode enabled"] - SPE: - Disabled: [0, "Peripheral disabled"] - Enabled: [1, "Peripheral enabled"] - - CR2: - TSER: [0, 65535] - TSIZE: [0, 65535] - - CFG1: - MBR: - Div2: [0, "f_spi_ker_ck / 2"] - Div4: [1, "f_spi_ker_ck / 4"] - Div8: [2, "f_spi_ker_ck / 8"] - Div16: [3, "f_spi_ker_ck / 16"] - Div32: [4, "f_spi_ker_ck / 32"] - Div64: [5, "f_spi_ker_ck / 64"] - Div128: [6, "f_spi_ker_ck / 128"] - Div256: [7, "f_spi_ker_ck / 256"] - CRCEN: - Disabled: [0, "CRC calculation disabled"] - Enabled: [1, "CRC calculation enabled"] - CRCSIZE: [0, 31] - TXDMAEN: - Disabled: [0, "Tx buffer DMA disabled"] - Enabled: [1, "Tx buffer DMA enabled"] - RXDMAEN: - Disabled: [0, "Rx buffer DMA disabled"] - Enabled: [1, "Rx buffer DMA enabled"] - UDRDET: - StartOfFrame: [0, "Underrun is detected at begin of data frame"] - EndOfFrame: [1, "Underrun is detected at end of last data frame"] - StartOfSlaveSelect: [2, "Underrun is detected at begin of active SS signal"] - UDRCFG: - Constant: [0, "Slave sends a constant underrun pattern"] - RepeatReceived: [1, "Slave repeats last received data frame from master"] - RepeatTransmitted: [2, "Slave repeats last transmitted data frame"] - FTHLV: - OneFrame: [0, "1 frame"] - TwoFrames: [1, "2 frames"] - ThreeFrames: [2, "3 frames"] - FourFrames: [3, "4 frames"] - FiveFrames: [4, "5 frames"] - SixFrames: [5, "6 frames"] - SevenFrames: [6, "7 frames"] - EightFrames: [7, "8 frames"] - NineFrames: [8, "9 frames"] - TenFrames: [9, "10 frames"] - ElevenFrames: [10, "11 frames"] - TwelveFrames: [11, "12 frames"] - ThirteenFrames: [12, "13 frames"] - FourteenFrames: [13, "14 frames"] - FifteenFrames: [14, "15 frames"] - SixteenFrames: [15, "16 frames"] - DSIZE: [0, 31] - - CFG2: - AFCNTR: - NotControlled: [0, "Peripheral takes no control of GPIOs while disabled"] - Controlled: [1, "Peripheral controls GPIOs while disabled"] - SSOM: - Asserted: [0, "SS is asserted until data transfer complete"] - NotAsserted: [1, "Data frames interleaved with SS not asserted during MIDI"] - SSOE: - Disabled: [0, "SS output is disabled in master mode"] - Enabled: [1, "SS output is enabled in master mode"] - SSIOP: - ActiveLow: [0, "Low level is active for SS signal"] - ActiveHigh: [1, "High level is active for SS signal"] - SSM: - Disabled: [0, "Software slave management disabled"] - Enabled: [1, "Software slave management enabled"] - CPOL: - IdleLow: [0, "CK to 0 when idle"] - IdleHigh: [1, "CK to 1 when idle"] - CPHA: - FirstEdge: [0, "The first clock transition is the first data capture edge"] - SecondEdge: [1, "The second clock transition is the first data capture edge"] - LSBFRST: - MSBFirst: [0, "Data is transmitted/received with the MSB first"] - LSBFirst: [1, "Data is transmitted/received with the LSB first"] - MASTER: - Slave: [0, "Slave configuration"] - Master: [1, "Master configuration"] - SP: - Motorola: [0, "Motorola SPI protocol"] - TI: [1, "TI SPI protocol"] - COMM: - FullDuplex: [0, "Full duplex"] - Transmitter: [1, "Simplex transmitter only"] - Receiver: [2, "Simplex receiver only"] - HalfDuplex: [3, "Half duplex"] - IOSWP: - Disabled: [0, "MISO and MOSI not swapped"] - Enabled: [1, "MISO and MOSI swapped"] - MIDI: [0, 15] - MSSI: [0, 15] - - IER: - TSERFIE: - Masked: [0, "TSER loaded interrupt masked"] - NotMasked: [1, "TSER loaded interrupt not masked"] - MODFIE: - Masked: [0, "Mode fault interrupt masked"] - NotMasked: [1, "Mode fault interrupt not masked"] - TIFREIE: - Masked: [0, "TI frame format error interrupt masked"] - NotMasked: [1, "TI frame format error interrupt not masked"] - CRCEIE: - Masked: [0, "CRC error interrupt masked"] - NotMasked: [1, "CRC error interrupt not masked"] - OVRIE: - Masked: [0, "Overrun interrupt masked"] - NotMasked: [1, "Overrun interrupt not masked"] - UDRIE: - Masked: [0, "Underrun interrupt masked"] - NotMasked: [1, "Underrun interrupt not masked"] - TXTFIE: - Masked: [0, "Transmission transfer filled interrupt masked"] - NotMasked: [1, "Transmission transfer filled interrupt not masked"] - EOTIE: - Masked: [0, "End-of-transfer interrupt masked"] - NotMasked: [1, "End-of-transfer interrupt not masked"] - DXPIE: - Masked: [0, "Duplex transfer complete interrupt masked"] - NotMasked: [1, "Duplex transfer complete interrupt not masked"] - TXPIE: - Masked: [0, "TX space available interrupt masked"] - NotMasked: [1, "TX space available interrupt not masked"] - RXPIE: - Masked: [0, "RX data available interrupt masked"] - NotMasked: [1, "RX data available interrupt not masked"] - - SR: - CTSIZE: [0, 65535] - RXWNE: - LessThan32: [0, "Less than 32-bit data frame received"] - AtLeast32: [1, "At least 32-bit data frame received"] - RXPLVL: - ZeroFrames: [0, "Zero frames beyond packing ratio available"] - OneFrame: [1, "One frame beyond packing ratio available"] - TwoFrames: [2, "Two frame beyond packing ratio available"] - ThreeFrames: [3, "Three frame beyond packing ratio available"] - TXC: - Ongoing: [0, "Transmission ongoing"] - Completed: [1, "Transmission completed"] - SUSP: - NotSuspended: [0, "Master not suspended"] - Suspended: [1, "Master suspended"] - TSERF: - NotLoaded: [0, "Additional number of SPI data to be transacted not yet loaded"] - Loaded: [1, "Additional number of SPI data to be transacted was reloaded"] - MODF: - NoFault: [0, "No mode fault detected"] - Fault: [1, "Mode fault detected"] - TIFRE: - NoError: [0, "TI frame format error detected"] - Error: [1, "TI frame format error detected"] - CRCE: - NoError: [0, "No CRC error detected"] - Error: [1, "CRC error detected"] - OVR: - NoOverrun: [0, "No overrun occurred"] - Overrun: [1, "Overrun occurred"] - UDR: - NoUnderrun: [0, "No underrun occurred"] - Underrun: [1, "Underrun occurred"] - TXTF: - NotCompleted: [0, "Transmission buffer incomplete"] - Completed: [1, "Transmission buffer filled with at least one transfer"] - EOT: - NotCompleted: [0, "Transfer ongoing or not started"] - Completed: [1, "Transfer complete"] - DXP: - Unavailable: [0, "Duplex packet unavailable: no space for transmission and/or no data received"] - Available: [1, "Duplex packet available: space for transmission and data received"] - TXP: - Full: [0, "Tx buffer full"] - NotFull: [1, "Tx buffer not full"] - RXP: - Empty: [0, "Rx buffer empty"] - NotEmpty: [1, "Rx buffer not empty"] - - IFCR: - "*C": - _write: - Clear: [1, "Clear interrupt flag"] - - TXDR: - TXDR: [0, 0xFFFFFFFF] - - RXDR: - _read: - RXDR: - - CRCPOLY: - CRCPOLY: [0, 0xFFFFFFFF] - - TXCRC: - _read: - TXCRC: - - RXCRC: - _read: - RXCRC: - - UDRDR: - UDRDR: [0, 0xFFFFFFFF] - - I2SCFGR: - MCKOE: - Disabled: [0, "Master clock output disabled"] - Enabled: [1, "Master clock output enabled"] - ODD: - Even: [0, "Real divider value is I2SDIV*2"] - Odd: [1, "Real divider value is I2SDIV*2 + 1"] - I2SDIV: [0, 255] - DATFMT: - RightAligned: [0, "The data inside RXDR and TXDR are right aligned"] - LeftAligned: [1, "The data inside RXDR and TXDR are left aligned"] - WSINV: - Disabled: [0, "Word select inversion disabled"] - Enabled: [1, "Word select inversion enabled"] - FIXCH: - NotFixed: [0, "The channel length in slave mode is different from 16 or 32 bits (CHLEN not taken into account)"] - Fixed: [1, "The channel length in slave mode is supposed to be 16 or 32 bits (according to CHLEN)"] - CKPOL: - SampleOnRising: [0, "Signals are sampled on rising and changed on falling clock edges"] - SampleOnFalling: [1, "Signals are sampled on falling and changed on rising clock edges"] - CHLEN: - Bits16: [0, "16 bit per channel"] - Bits32: [1, "32 bit per channel"] - DATLEN: - Bits16: [0, "16 bit data length"] - Bits24: [1, "24 bit data length"] - Bits32: [2, "32 bit data length"] - PCMSYNC: - Short: [0, "Short PCM frame synchronization"] - Long: [1, "Long PCM frame synchronization"] - I2SSTD: - Philips: [0, "I2S Philips standard"] - LeftAligned: [1, "MSB/left justified standard"] - RightAligned: [2, "LSB/right justified standard"] - PCM: [3, "PCM standard"] - I2SCFG: - SlaveTransmit: [0, "Slave, transmit"] - SlaveReceive: [1, "Slave, recteive"] - MasterTransmit: [2, "Master, transmit"] - MasterReceive: [3, "Master, receive"] - SlaveFullDuplex: [4, "Slave, full duplex"] - MasterFullDuplex: [5, "Master, full duplex"] - I2SMOD: - SPI: [0, "SPI mode selected"] - I2S: [1, "I2S/PCM mode selected"] diff --git a/peripherals/syscfg/syscfg_f0.yaml b/peripherals/syscfg/syscfg_f0.yaml deleted file mode 100644 index b3fa24659..000000000 --- a/peripherals/syscfg/syscfg_f0.yaml +++ /dev/null @@ -1,162 +0,0 @@ -SYSCFG: - CFGR1: - MEM_MODE: - MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] - SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] - MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] - SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] - PA11_PA12_RMP: - NotRemapped: [0, "Pin pair PA9/PA10 mapped on the pins"] - Remapped: [1, "Pin pair PA11/PA12 mapped instead of PA9/PA10"] - ADC_DMA_RMP: - NotRemapped: [0, "ADC DMA request mapped on DMA channel 1"] - Remapped: [1, "ADC DMA request mapped on DMA channel 2"] - USART1_TX_DMA_RMP: - NotRemapped: [0, "USART1_TX DMA request mapped on DMA channel 2"] - Remapped: [1, "USART1_TX DMA request mapped on DMA channel 4"] - USART1_RX_DMA_RMP: - NotRemapped: [0, "USART1_RX DMA request mapped on DMA channel 3"] - Remapped: [1, "USART1_RX DMA request mapped on DMA channel 5"] - TIM16_DMA_RMP: - NotRemapped: [0, "TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 3"] - Remapped: [1, "TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 4"] - TIM17_DMA_RMP: - NotRemapped: [0, "TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 1"] - Remapped: [1, "TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 2"] - I2C_PB6_FMP: - Standard: [0, "PB6 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] - I2C_PB7_FMP: - Standard: [0, "PB7 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] - I2C_PB8_FMP: - Standard: [0, "PB8 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] - I2C_PB9_FMP: - Standard: [0, "PB9 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] - I2C1_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers"] - I2C_PA9_FMP: - Standard: [0, "PA9 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PA9 and the Speed control is bypassed"] - I2C_PA10_FMP: - Standard: [0, "PA10 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PA10 and the Speed control is bypassed"] - USART3_DMA_RMP: - NotRemapped: [0, "USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively (or simply disabled on STM32F0x0)"] - Remapped: [1, "USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively"] - CFGR2: - LOCKUP_LOCK: - Disconnected: [0, "Cortex-M0 LOCKUP output disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "Cortex-M0 LOCKUP output connected to TIM1/15/16/17 Break input"] - SRAM_PARITY_LOCK: - Disconnected: [0, "SRAM parity error disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "SRAM parity error connected to TIM1/15/16/17 Break input"] - SRAM_PEF: - _read: - NoParityError: [0, "No SRAM parity error detected"] - ParityErrorDetected: [1, "SRAM parity error detected"] - _write: - Clear: [1, "Clear SRAM parity error flag"] - EXTICR1: - EXTI0: - PA0: [0, "Select PA0 as the source input for the EXTI0 external interrupt"] - PB0: [1, "Select PB0 as the source input for the EXTI0 external interrupt"] - PC0: [2, "Select PC0 as the source input for the EXTI0 external interrupt"] - PD0: [3, "Select PD0 as the source input for the EXTI0 external interrupt"] - PF0: [5, "Select PF0 as the source input for the EXTI0 external interrupt"] - EXTI1: - PA1: [0, "Select PA1 as the source input for the EXTI1 external interrupt"] - PB1: [1, "Select PB1 as the source input for the EXTI1 external interrupt"] - PC1: [2, "Select PC1 as the source input for the EXTI1 external interrupt"] - PD1: [3, "Select PD1 as the source input for the EXTI1 external interrupt"] - PF1: [5, "Select PF1 as the source input for the EXTI1 external interrupt"] - EXTI2: - PA2: [0, "Select PA2 as the source input for the EXTI2 external interrupt"] - PB2: [1, "Select PB2 as the source input for the EXTI2 external interrupt"] - PC2: [2, "Select PC2 as the source input for the EXTI2 external interrupt"] - PD2: [3, "Select PD2 as the source input for the EXTI2 external interrupt"] - PF2: [5, "Select PF2 as the source input for the EXTI2 external interrupt"] - EXTI3: - PA3: [0, "Select PA3 as the source input for the EXTI3 external interrupt"] - PB3: [1, "Select PB3 as the source input for the EXTI3 external interrupt"] - PC3: [2, "Select PC3 as the source input for the EXTI3 external interrupt"] - PD3: [3, "Select PD3 as the source input for the EXTI3 external interrupt"] - PF3: [5, "Select PF3 as the source input for the EXTI3 external interrupt"] - EXTICR2: - EXTI4: - PA4: [0, "Select PA4 as the source input for the EXTI4 external interrupt"] - PB4: [1, "Select PB4 as the source input for the EXTI4 external interrupt"] - PC4: [2, "Select PC4 as the source input for the EXTI4 external interrupt"] - PD4: [3, "Select PD4 as the source input for the EXTI4 external interrupt"] - PF4: [5, "Select PF4 as the source input for the EXTI4 external interrupt"] - EXTI5: - PA5: [0, "Select PA5 as the source input for the EXTI5 external interrupt"] - PB5: [1, "Select PB5 as the source input for the EXTI5 external interrupt"] - PC5: [2, "Select PC5 as the source input for the EXTI5 external interrupt"] - PD5: [3, "Select PD5 as the source input for the EXTI5 external interrupt"] - PF5: [5, "Select PF5 as the source input for the EXTI5 external interrupt"] - EXTI6: - PA6: [0, "Select PA6 as the source input for the EXTI6 external interrupt"] - PB6: [1, "Select PB6 as the source input for the EXTI6 external interrupt"] - PC6: [2, "Select PC6 as the source input for the EXTI6 external interrupt"] - PD6: [3, "Select PD6 as the source input for the EXTI6 external interrupt"] - PF6: [5, "Select PF6 as the source input for the EXTI6 external interrupt"] - EXTI7: - PA7: [0, "Select PA7 as the source input for the EXTI7 external interrupt"] - PB7: [1, "Select PB7 as the source input for the EXTI7 external interrupt"] - PC7: [2, "Select PC7 as the source input for the EXTI7 external interrupt"] - PD7: [3, "Select PD7 as the source input for the EXTI7 external interrupt"] - PF7: [5, "Select PF7 as the source input for the EXTI7 external interrupt"] - EXTICR3: - EXTI8: - PA8: [0, "Select PA8 as the source input for the EXTI8 external interrupt"] - PB8: [1, "Select PB8 as the source input for the EXTI8 external interrupt"] - PC8: [2, "Select PC8 as the source input for the EXTI8 external interrupt"] - PD8: [3, "Select PD8 as the source input for the EXTI8 external interrupt"] - PF8: [5, "Select PF8 as the source input for the EXTI8 external interrupt"] - EXTI9: - PA9: [0, "Select PA9 as the source input for the EXTI9 external interrupt"] - PB9: [1, "Select PB9 as the source input for the EXTI9 external interrupt"] - PC9: [2, "Select PC9 as the source input for the EXTI9 external interrupt"] - PD9: [3, "Select PD9 as the source input for the EXTI9 external interrupt"] - PF9: [5, "Select PF9 as the source input for the EXTI9 external interrupt"] - EXTI10: - PA10: [0, "Select PA10 as the source input for the EXTI10 external interrupt"] - PB10: [1, "Select PB10 as the source input for the EXTI10 external interrupt"] - PC10: [2, "Select PC10 as the source input for the EXTI10 external interrupt"] - PD10: [3, "Select PD10 as the source input for the EXTI10 external interrupt"] - PF10: [5, "Select PF10 as the source input for the EXTI10 external interrupt"] - EXTI11: - PA11: [0, "Select PA11 as the source input for the EXTI11 external interrupt"] - PB11: [1, "Select PB11 as the source input for the EXTI11 external interrupt"] - PC11: [2, "Select PC11 as the source input for the EXTI11 external interrupt"] - PD11: [3, "Select PD11 as the source input for the EXTI11 external interrupt"] - PF11: [5, "Select PF11 as the source input for the EXTI11 external interrupt"] - EXTICR4: - EXTI12: - PA12: [0, "Select PA12 as the source input for the EXTI12 external interrupt"] - PB12: [1, "Select PB12 as the source input for the EXTI12 external interrupt"] - PC12: [2, "Select PC12 as the source input for the EXTI12 external interrupt"] - PD12: [3, "Select PD12 as the source input for the EXTI12 external interrupt"] - PF12: [5, "Select PF12 as the source input for the EXTI12 external interrupt"] - EXTI13: - PA13: [0, "Select PA13 as the source input for the EXTI13 external interrupt"] - PB13: [1, "Select PB13 as the source input for the EXTI13 external interrupt"] - PC13: [2, "Select PC13 as the source input for the EXTI13 external interrupt"] - PD13: [3, "Select PD13 as the source input for the EXTI13 external interrupt"] - PF13: [5, "Select PF13 as the source input for the EXTI13 external interrupt"] - EXTI14: - PA14: [0, "Select PA14 as the source input for the EXTI14 external interrupt"] - PB14: [1, "Select PB14 as the source input for the EXTI14 external interrupt"] - PC14: [2, "Select PC14 as the source input for the EXTI14 external interrupt"] - PD14: [3, "Select PD14 as the source input for the EXTI14 external interrupt"] - PF14: [5, "Select PF14 as the source input for the EXTI14 external interrupt"] - EXTI15: - PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] - PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] - PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] - PD15: [3, "Select PD15 as the source input for the EXTI15 external interrupt"] - PF15: [5, "Select PF15 as the source input for the EXTI15 external interrupt"] diff --git a/peripherals/syscfg/syscfg_f0x128.yaml b/peripherals/syscfg/syscfg_f0x128.yaml deleted file mode 100644 index e577df05a..000000000 --- a/peripherals/syscfg/syscfg_f0x128.yaml +++ /dev/null @@ -1,76 +0,0 @@ -_include: - - ./syscfg_f0.yaml - -SYSCFG: - CFGR1: - IR_MOD: - TIM16: [0, "TIM16 selected"] - USART1: [1, "USART1 selected"] - USART4: [2, "USART4 selected"] - TIM16_DMA_RMP2: - NotAlternateRemapped: [0, "TIM16 DMA request mapped according to TIM16_DMA_RMP bit"] - AlternateRemapped: [1, "TIM16_CH1 and TIM16_UP DMA request mapped on DMA channel 6"] - TIM17_DMA_RMP2: - NotAlternateRemapped: [0, "TIM17 DMA request mapped according to TIM16_DMA_RMP bit"] - AlternateRemapped: [1, "TIM17_CH1 and TIM17_UP DMA request mapped on DMA channel 7"] - I2C2_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers"] - SPI2_DMA_RMP: - NotRemapped: [0, "SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively"] - Remapped: [1, "SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively"] - USART2_DMA_RMP: - NotRemapped: [0, "USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively"] - Remapped: [1, "USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively"] - I2C1_DMA_RMP: - NotRemapped: [0, "I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively"] - Remapped: [1, "I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively"] - TIM1_DMA_RMP: - NotRemapped: [0, "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively"] - Remapped: [1, "TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6"] - TIM2_DMA_RMP: - NotRemapped: [0, "TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively"] - Remapped: [1, "TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7"] - TIM3_DMA_RMP: - NotRemapped: [0, "TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4"] - Remapped: [1, "TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6"] - CFGR2: - PVD_LOCK: - Disconnected: [0, "PVD interrupt disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "PVD interrupt connected to TIM1/15/16/17 Break input"] - EXTICR1: - EXTI0: - PE0: [4, "Select PE0 as the source input for the EXTI0 external interrupt"] - EXTI1: - PE1: [4, "Select PE1 as the source input for the EXTI1 external interrupt"] - EXTI2: - PE2: [4, "Select PE2 as the source input for the EXTI2 external interrupt"] - EXTI3: - PE3: [4, "Select PE3 as the source input for the EXTI3 external interrupt"] - EXTICR2: - EXTI4: - PE4: [4, "Select PE4 as the source input for the EXTI4 external interrupt"] - EXTI5: - PE5: [4, "Select PE5 as the source input for the EXTI5 external interrupt"] - EXTI6: - PE6: [4, "Select PE6 as the source input for the EXTI6 external interrupt"] - EXTI7: - PE7: [4, "Select PE7 as the source input for the EXTI7 external interrupt"] - EXTICR3: - EXTI8: - PE8: [4, "Select PE8 as the source input for the EXTI8 external interrupt"] - EXTI9: - PE9: [4, "Select PE9 as the source input for the EXTI9 external interrupt"] - EXTI10: - PE10: [4, "Select PE10 as the source input for the EXTI10 external interrupt"] - EXTI11: - PE11: [4, "Select PE11 as the source input for the EXTI11 external interrupt"] - EXTICR4: - EXTI12: - PE12: [4, "Select PE12 as the source input for the EXTI12 external interrupt"] - EXTI13: - PE13: [4, "Select PE13 as the source input for the EXTI13 external interrupt"] - EXTI14: - PE14: [4, "Select PE14 as the source input for the EXTI14 external interrupt"] - EXTI15: - PE15: [4, "Select PE15 as the source input for the EXTI15 external interrupt"] diff --git a/peripherals/syscfg/syscfg_f3.yaml b/peripherals/syscfg/syscfg_f3.yaml deleted file mode 100644 index 3fbe00e35..000000000 --- a/peripherals/syscfg/syscfg_f3.yaml +++ /dev/null @@ -1,44 +0,0 @@ -SYSCFG: - CFGR1: - FPU_IE5: - Disabled: [0, "Inexact interrupt disable"] - Enabled: [1, "Inexact interrupt enable"] - FPU_IE4: - Disabled: [0, "Input denormal interrupt disable"] - Enabled: [1, "Input denormal interrupt enable"] - FPU_IE3: - Disabled: [0, "Overflow interrupt disable"] - Enabled: [1, "Overflow interrupt enable"] - FPU_IE2: - Disabled: [0, "Underflow interrupt disable"] - Enabled: [1, "Underflow interrupt enable"] - FPU_IE1: - Disabled: [0, "Devide-by-zero interrupt disable"] - Enabled: [1, "Devide-by-zero interrupt enable"] - FPU_IE0: - Disabled: [0, "Invalid operation interrupt disable"] - Enabled: [1, "Invalid operation interrupt enable"] - I2C2_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C2 pins selected through selection through IOPORT control registers AF selection bits"] - I2C1_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection through IOPORT control registers AF selection bits"] - I2C_PB9_FMP: - Standard: [0, "PB9 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] - I2C_PB8_FMP: - Standard: [0, "PB8 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] - I2C_PB7_FMP: - Standard: [0, "PB7 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] - I2C_PB6_FMP: - Standard: [0, "PB6 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] - TIM17_DMA_RMP: - NotRemapped: [0, "TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1"] - Remapped: [1, "TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2"] - TIM16_DMA_RMP: - NotRemapped: [0, "TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3"] - Remapped: [1, "TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4"] diff --git a/peripherals/syscfg/syscfg_f301.yaml b/peripherals/syscfg/syscfg_f301.yaml deleted file mode 100644 index e72dd7d12..000000000 --- a/peripherals/syscfg/syscfg_f301.yaml +++ /dev/null @@ -1,90 +0,0 @@ -SYSCFG: - CFGR1: - I2C3_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits"] - ENCODER_MODE: - NoRedirection: [0, "No redirection"] - MapTim2Tim15: [1, "TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively"] - TIM6_DAC1_DMA_RMP: - NotRemapped: [0, "TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3"] - Remapped: [1, "TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3"] - TIM1_ITR3_RMP: - NotRemapped: [0, "Not remapped"] - Remapped: [1, "TIM1_ITR3 = TIM17_OC"] - MEM_MODE: - MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] - SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] - MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] - SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] - EXTICR1: - EXTI0: - PA0: [0, "Select PA0 as the source input for the EXTI0 external interrupt"] - PB0: [1, "Select PB0 as the source input for the EXTI0 external interrupt"] - PC0: [2, "Select PC0 as the source input for the EXTI0 external interrupt"] - PF0: [5, "Select PF0 as the source input for the EXTI0 external interrupt"] - EXTI1: - PA1: [0, "Select PA1 as the source input for the EXTI1 external interrupt"] - PB1: [1, "Select PB1 as the source input for the EXTI1 external interrupt"] - PC1: [2, "Select PC1 as the source input for the EXTI1 external interrupt"] - PF1: [5, "Select PF1 as the source input for the EXTI1 external interrupt"] - EXTI2: - PA2: [0, "Select PA2 as the source input for the EXTI2 external interrupt"] - PB2: [1, "Select PB2 as the source input for the EXTI2 external interrupt"] - PC2: [2, "Select PC2 as the source input for the EXTI2 external interrupt"] - PD2: [3, "Select PD2 as the source input for the EXTI2 external interrupt"] - EXTI3: - PA3: [0, "Select PA3 as the source input for the EXTI3 external interrupt"] - PB3: [1, "Select PB3 as the source input for the EXTI3 external interrupt"] - PC3: [2, "Select PC3 as the source input for the EXTI3 external interrupt"] - EXTICR2: - EXTI4: - PA4: [0, "Select PA4 as the source input for the EXTI4 external interrupt"] - PB4: [1, "Select PB4 as the source input for the EXTI4 external interrupt"] - PC4: [2, "Select PC4 as the source input for the EXTI4 external interrupt"] - EXTI5: - PA5: [0, "Select PA5 as the source input for the EXTI5 external interrupt"] - PB5: [1, "Select PB5 as the source input for the EXTI5 external interrupt"] - PC5: [2, "Select PC5 as the source input for the EXTI5 external interrupt"] - EXTI6: - PA6: [0, "Select PA6 as the source input for the EXTI6 external interrupt"] - PB6: [1, "Select PB6 as the source input for the EXTI6 external interrupt"] - PC6: [2, "Select PC6 as the source input for the EXTI6 external interrupt"] - EXTI7: - PA7: [0, "Select PA7 as the source input for the EXTI7 external interrupt"] - PB7: [1, "Select PB7 as the source input for the EXTI7 external interrupt"] - PC7: [2, "Select PC7 as the source input for the EXTI7 external interrupt"] - EXTICR3: - EXTI8: - PA8: [0, "Select PA8 as the source input for the EXTI8 external interrupt"] - PB8: [1, "Select PB8 as the source input for the EXTI8 external interrupt"] - PC8: [2, "Select PC8 as the source input for the EXTI8 external interrupt"] - EXTI9: - PA9: [0, "Select PA9 as the source input for the EXTI9 external interrupt"] - PB9: [1, "Select PB9 as the source input for the EXTI9 external interrupt"] - PC9: [2, "Select PC9 as the source input for the EXTI9 external interrupt"] - EXTI10: - PA10: [0, "Select PA10 as the source input for the EXTI10 external interrupt"] - PB10: [1, "Select PB10 as the source input for the EXTI10 external interrupt"] - PC10: [2, "Select PC10 as the source input for the EXTI10 external interrupt"] - EXTI11: - PA11: [0, "Select PA11 as the source input for the EXTI11 external interrupt"] - PB11: [1, "Select PB11 as the source input for the EXTI11 external interrupt"] - PC11: [2, "Select PC11 as the source input for the EXTI11 external interrupt"] - EXTICR4: - EXTI12: - PA12: [0, "Select PA12 as the source input for the EXTI12 external interrupt"] - PB12: [1, "Select PB12 as the source input for the EXTI12 external interrupt"] - PC12: [2, "Select PC12 as the source input for the EXTI12 external interrupt"] - EXTI13: - PA13: [0, "Select PA13 as the source input for the EXTI13 external interrupt"] - PB13: [1, "Select PB13 as the source input for the EXTI13 external interrupt"] - PC13: [2, "Select PC13 as the source input for the EXTI13 external interrupt"] - EXTI14: - PA14: [0, "Select PA14 as the source input for the EXTI14 external interrupt"] - PB14: [1, "Select PB14 as the source input for the EXTI14 external interrupt"] - PC14: [2, "Select PC14 as the source input for the EXTI14 external interrupt"] - EXTI15: - PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] - PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] - PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] diff --git a/peripherals/syscfg/syscfg_f302.yaml b/peripherals/syscfg/syscfg_f302.yaml deleted file mode 100644 index 1bb02f324..000000000 --- a/peripherals/syscfg/syscfg_f302.yaml +++ /dev/null @@ -1,155 +0,0 @@ -SYSCFG: - CFGR1: - I2C3_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C3 pins selected through selection trhough IOPORT control registers AF selection bits"] - ENCODER_MODE: - NoRedirection: [0, "No redirection"] - MapTim2Tim15: [1, "TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively"] - MapTim3Tim15: [2, "TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively"] - MapTim4Tim15: [3, "TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively (STM32F302xB/C devices only)"] - TIM6_DAC1_DMA_RMP: - NotRemapped: [0, "TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3"] - Remapped: [1, "TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3"] - ADC2_DMA_RMP: - NotRemapped: [0, "ADC24 DMA requests mapped on DMA2 channels 1 and 2"] - Remapped: [1, "ADC24 DMA requests mapped on DMA2 channels 3 and 4"] - DAC1_TRIG_RMP: - NotRemapped: [0, "DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices"] - Remapped: [1, "DAC trigger is TIM3_TRGO"] - TIM1_ITR3_RMP: - NotRemapped: [0, "TIM1_ITR3 = TIM4_TRGO in STM32F303xB/C and STM32F358xC devices"] - Remapped: [1, "TIM1_ITR3 = TIM17_OC"] - # Is documented as reserverd but appears in register table (RM0365 p.172) and register map - USB_IT_RMP: - NotRemapped: [0, "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively"] - Remapped: [1, "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively"] - MEM_MODE: - MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] - SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] - SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] - FMC: [4, "FMC Bank (Only the first two banks) (Available on STM32F302xD/E only)"] - EXTICR1: - EXTI0: - PA0: [0, "Select PA0 as the source input for the EXTI0 external interrupt"] - PB0: [1, "Select PB0 as the source input for the EXTI0 external interrupt"] - PC0: [2, "Select PC0 as the source input for the EXTI0 external interrupt"] - PD0: [3, "Select PD0 as the source input for the EXTI0 external interrupt"] - PE0: [4, "Select PE0 as the source input for the EXTI0 external interrupt"] - PF0: [5, "Select PF0 as the source input for the EXTI0 external interrupt"] - EXTI1: - PA1: [0, "Select PA1 as the source input for the EXTI1 external interrupt"] - PB1: [1, "Select PB1 as the source input for the EXTI1 external interrupt"] - PC1: [2, "Select PC1 as the source input for the EXTI1 external interrupt"] - PD1: [3, "Select PD1 as the source input for the EXTI1 external interrupt"] - PE1: [4, "Select PE1 as the source input for the EXTI1 external interrupt"] - PF1: [5, "Select PF1 as the source input for the EXTI1 external interrupt"] - EXTI2: - PA2: [0, "Select PA2 as the source input for the EXTI2 external interrupt"] - PB2: [1, "Select PB2 as the source input for the EXTI2 external interrupt"] - PC2: [2, "Select PC2 as the source input for the EXTI2 external interrupt"] - PD2: [3, "Select PD2 as the source input for the EXTI2 external interrupt"] - PE2: [4, "Select PE2 as the source input for the EXTI2 external interrupt"] - PF2: [5, "Select PF2 as the source input for the EXTI2 external interrupt"] - EXTI3: - PA3: [0, "Select PA3 as the source input for the EXTI3 external interrupt"] - PB3: [1, "Select PB3 as the source input for the EXTI3 external interrupt"] - PC3: [2, "Select PC3 as the source input for the EXTI3 external interrupt"] - PD3: [3, "Select PD3 as the source input for the EXTI3 external interrupt"] - PE3: [4, "Select PE3 as the source input for the EXTI3 external interrupt"] - EXTICR2: - EXTI4: - PA4: [0, "Select PA4 as the source input for the EXTI4 external interrupt"] - PB4: [1, "Select PB4 as the source input for the EXTI4 external interrupt"] - PC4: [2, "Select PC4 as the source input for the EXTI4 external interrupt"] - PD4: [3, "Select PD4 as the source input for the EXTI4 external interrupt"] - PE4: [4, "Select PE4 as the source input for the EXTI4 external interrupt"] - PF4: [5, "Select PF4 as the source input for the EXTI4 external interrupt"] - EXTI5: - PA5: [0, "Select PA5 as the source input for the EXTI5 external interrupt"] - PB5: [1, "Select PB5 as the source input for the EXTI5 external interrupt"] - PC5: [2, "Select PC5 as the source input for the EXTI5 external interrupt"] - PD5: [3, "Select PD5 as the source input for the EXTI5 external interrupt"] - PE5: [4, "Select PE5 as the source input for the EXTI5 external interrupt"] - PF5: [5, "Select PF5 as the source input for the EXTI5 external interrupt"] - EXTI6: - PA6: [0, "Select PA6 as the source input for the EXTI6 external interrupt"] - PB6: [1, "Select PB6 as the source input for the EXTI6 external interrupt"] - PC6: [2, "Select PC6 as the source input for the EXTI6 external interrupt"] - PD6: [3, "Select PD6 as the source input for the EXTI6 external interrupt"] - PE6: [4, "Select PE6 as the source input for the EXTI6 external interrupt"] - PF6: [5, "Select PF6 as the source input for the EXTI6 external interrupt"] - EXTI7: - PA7: [0, "Select PA7 as the source input for the EXTI7 external interrupt"] - PB7: [1, "Select PB7 as the source input for the EXTI7 external interrupt"] - PC7: [2, "Select PC7 as the source input for the EXTI7 external interrupt"] - PD7: [3, "Select PD7 as the source input for the EXTI7 external interrupt"] - PE7: [4, "Select PE7 as the source input for the EXTI7 external interrupt"] - EXTICR3: - EXTI8: - PA8: [0, "Select PA8 as the source input for the EXTI8 external interrupt"] - PB8: [1, "Select PB8 as the source input for the EXTI8 external interrupt"] - PC8: [2, "Select PC8 as the source input for the EXTI8 external interrupt"] - PD8: [3, "Select PD8 as the source input for the EXTI8 external interrupt"] - PE8: [4, "Select PE8 as the source input for the EXTI8 external interrupt"] - EXTI9: - PA9: [0, "Select PA9 as the source input for the EXTI9 external interrupt"] - PB9: [1, "Select PB9 as the source input for the EXTI9 external interrupt"] - PC9: [2, "Select PC9 as the source input for the EXTI9 external interrupt"] - PD9: [3, "Select PD9 as the source input for the EXTI9 external interrupt"] - PE9: [4, "Select PE9 as the source input for the EXTI9 external interrupt"] - PF9: [5, "Select PF9 as the source input for the EXTI9 external interrupt"] - EXTI10: - PA10: [0, "Select PA10 as the source input for the EXTI10 external interrupt"] - PB10: [1, "Select PB10 as the source input for the EXTI10 external interrupt"] - PC10: [2, "Select PC10 as the source input for the EXTI10 external interrupt"] - PD10: [3, "Select PD10 as the source input for the EXTI10 external interrupt"] - PE10: [4, "Select PE10 as the source input for the EXTI10 external interrupt"] - PF10: [5, "Select PF10 as the source input for the EXTI10 external interrupt"] - EXTI11: - PA11: [0, "Select PA11 as the source input for the EXTI11 external interrupt"] - PB11: [1, "Select PB11 as the source input for the EXTI11 external interrupt"] - PC11: [2, "Select PC11 as the source input for the EXTI11 external interrupt"] - PD11: [3, "Select PD11 as the source input for the EXTI11 external interrupt"] - PE11: [4, "Select PE11 as the source input for the EXTI11 external interrupt"] - EXTICR4: - EXTI12: - PA12: [0, "Select PA12 as the source input for the EXTI12 external interrupt"] - PB12: [1, "Select PB12 as the source input for the EXTI12 external interrupt"] - PC12: [2, "Select PC12 as the source input for the EXTI12 external interrupt"] - PD12: [3, "Select PD12 as the source input for the EXTI12 external interrupt"] - PE12: [4, "Select PE12 as the source input for the EXTI12 external interrupt"] - EXTI13: - PA13: [0, "Select PA13 as the source input for the EXTI13 external interrupt"] - PB13: [1, "Select PB13 as the source input for the EXTI13 external interrupt"] - PC13: [2, "Select PC13 as the source input for the EXTI13 external interrupt"] - PD13: [3, "Select PD13 as the source input for the EXTI13 external interrupt"] - PE13: [4, "Select PE13 as the source input for the EXTI13 external interrupt"] - EXTI14: - PA14: [0, "Select PA14 as the source input for the EXTI14 external interrupt"] - PB14: [1, "Select PB14 as the source input for the EXTI14 external interrupt"] - PC14: [2, "Select PC14 as the source input for the EXTI14 external interrupt"] - PD14: [3, "Select PD14 as the source input for the EXTI14 external interrupt"] - PE14: [4, "Select PE14 as the source input for the EXTI14 external interrupt"] - EXTI15: - PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] - PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] - PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] - PD15: [3, "Select PD15 as the source input for the EXTI15 external interrupt"] - PE15: [4, "Select PE15 as the source input for the EXTI15 external interrupt"] - CFGR2: - SRAM_PEF: - _read: - NoParityError: [0, "No SRAM parity error detected"] - ParityErrorDetected: [1, "SRAM parity error detected"] - _write: - Clear: [1, "Clear SRAM parity error flag"] - BYP_ADDR_PAR: - NoBypass: [0, "The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated"] - Bypass: [1, "The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated"] - SRAM_PARITY_LOCK: - Disconnected: [0, "SRAM parity error disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "SRAM parity error connected to TIM1/15/16/17 Break input"] - LOCKUP_LOCK: - Disconnected: [0, "Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "Cortex-M4 LOCKUP output connected to TIM1/15/16/17 Break input"] diff --git a/peripherals/syscfg/syscfg_f303_3x8.yaml b/peripherals/syscfg/syscfg_f303_3x8.yaml deleted file mode 100644 index 11a607532..000000000 --- a/peripherals/syscfg/syscfg_f303_3x8.yaml +++ /dev/null @@ -1,257 +0,0 @@ -SYSCFG: - CFGR1: - I2C3_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C3 pins selected through selection through IOPORT control registers AF selection bits"] - ENCODER_MODE: - NoRedirection: [0, "No redirection"] - MapTim2Tim15: [1, "TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively"] - MapTim3Tim15: [2, "TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively"] - MapTim4Tim15: [3, "TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively (STM32F303xB/C and STM32F358xC devices only)"] - DAC2_CH1_DMA_RMP: - NotRemapped: [0, "Not remapped"] - Remapped: [1, "DAC2_CH1 DMA requests mapped on DMA1 channel 5"] - TIM7_DAC1_CH2_DMA_RMP: - NotRemapped: [0, "TIM7_UP and DAC_CH2 DMA requests mapped on DMA2 channel 4 in STM32F303xB/C and STM32F358xC devices"] - Remapped: [1, "TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4"] - TIM6_DAC1_CH1_DMA_RMP: - NotRemapped: [0, "TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3 in STM32F303xB/C and STM32F358xC"] - Remapped: [1, "TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3"] - # TODO: Is named ADC2_... in register description (RM0316 p.247) but ADC24_... in register map (RM0316 p.261) - ADC2_DMA_RMP: - NotRemapped: [0, "ADC24 DMA requests mapped on DMA2 channels 1 and 2"] - Remapped: [1, "ADC24 DMA requests mapped on DMA2 channels 3 and 4"] - # TODO: Is named DAC1_... in register description (RM0316 p.247) but DAC_... in register map (RM0316 p.261) - DAC1_TRIG_RMP: - NotRemapped: [0, "DAC trigger is TIM8_TRGO in STM32F303xB/C and STM32F358xC devices"] - Remapped: [1, "DAC trigger is TIM3_TRGO"] - TIM1_ITR3_RMP: - NotRemapped: [0, "TIM1_ITR3 = TIM4_TRGO in STM32F303xB/C and STM32F358xC devices"] - Remapped: [1, "TIM1_ITR3 = TIM17_OC"] - USB_IT_RMP: - NotRemapped: [0, "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 19, 20 and 42 respectively"] - Remapped: [1, "USB_HP, USB_LP and USB_WAKEUP interrupts are mapped on interrupt lines 74, 75 and 76 respectively"] - MEM_MODE: - MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] - SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] - SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] - FMC: [4, "FMC Bank (Only the first two banks) (Available on STM32F303xD/E only)"] - RCR: - PAGE*_WP: - Disabled: [0, "Write protection of pagex is disabled"] - Enabled: [1, "Write protection of pagex is enabled"] - EXTICR1: - EXTI0: - PA0: [0, "Select PA0 as the source input for the EXTI0 external interrupt"] - PB0: [1, "Select PB0 as the source input for the EXTI0 external interrupt"] - PC0: [2, "Select PC0 as the source input for the EXTI0 external interrupt"] - PD0: [3, "Select PD0 as the source input for the EXTI0 external interrupt"] - PE0: [4, "Select PE0 as the source input for the EXTI0 external interrupt"] - PF0: [5, "Select PF0 as the source input for the EXTI0 external interrupt"] - PG0: [6, "Select PG0 as the source input for the EXTI0 external interrupt"] - PH0: [7, "Select PH0 as the source input for the EXTI0 external interrupt"] - EXTI1: - PA1: [0, "Select PA1 as the source input for the EXTI1 external interrupt"] - PB1: [1, "Select PB1 as the source input for the EXTI1 external interrupt"] - PC1: [2, "Select PC1 as the source input for the EXTI1 external interrupt"] - PD1: [3, "Select PD1 as the source input for the EXTI1 external interrupt"] - PE1: [4, "Select PE1 as the source input for the EXTI1 external interrupt"] - PF1: [5, "Select PF1 as the source input for the EXTI1 external interrupt"] - PG1: [6, "Select PG1 as the source input for the EXTI1 external interrupt"] - PH1: [7, "Select PH1 as the source input for the EXTI1 external interrupt"] - EXTI2: - PA2: [0, "Select PA2 as the source input for the EXTI2 external interrupt"] - PB2: [1, "Select PB2 as the source input for the EXTI2 external interrupt"] - PC2: [2, "Select PC2 as the source input for the EXTI2 external interrupt"] - PD2: [3, "Select PD2 as the source input for the EXTI2 external interrupt"] - PE2: [4, "Select PE2 as the source input for the EXTI2 external interrupt"] - PF2: [5, "Select PF2 as the source input for the EXTI2 external interrupt"] - PG2: [6, "Select PG2 as the source input for the EXTI2 external interrupt"] - PH2: [7, "Select PH2 as the source input for the EXTI2 external interrupt"] - EXTI3: - PA3: [0, "Select PA3 as the source input for the EXTI3 external interrupt"] - PB3: [1, "Select PB3 as the source input for the EXTI3 external interrupt"] - PC3: [2, "Select PC3 as the source input for the EXTI3 external interrupt"] - PD3: [3, "Select PD3 as the source input for the EXTI3 external interrupt"] - PE3: [4, "Select PE3 as the source input for the EXTI3 external interrupt"] - PF3: [5, "Select PF3 as the source input for the EXTI3 external interrupt"] - PG3: [6, "Select PG3 as the source input for the EXTI3 external interrupt"] - EXTICR2: - EXTI4: - PA4: [0, "Select PA4 as the source input for the EXTI4 external interrupt"] - PB4: [1, "Select PB4 as the source input for the EXTI4 external interrupt"] - PC4: [2, "Select PC4 as the source input for the EXTI4 external interrupt"] - PD4: [3, "Select PD4 as the source input for the EXTI4 external interrupt"] - PE4: [4, "Select PE4 as the source input for the EXTI4 external interrupt"] - PF4: [5, "Select PF4 as the source input for the EXTI4 external interrupt"] - PG4: [6, "Select PG4 as the source input for the EXTI4 external interrupt"] - EXTI5: - PA5: [0, "Select PA5 as the source input for the EXTI5 external interrupt"] - PB5: [1, "Select PB5 as the source input for the EXTI5 external interrupt"] - PC5: [2, "Select PC5 as the source input for the EXTI5 external interrupt"] - PD5: [3, "Select PD5 as the source input for the EXTI5 external interrupt"] - PE5: [4, "Select PE5 as the source input for the EXTI5 external interrupt"] - PF5: [5, "Select PF5 as the source input for the EXTI5 external interrupt"] - PG5: [6, "Select PG5 as the source input for the EXTI5 external interrupt"] - EXTI6: - PA6: [0, "Select PA6 as the source input for the EXTI6 external interrupt"] - PB6: [1, "Select PB6 as the source input for the EXTI6 external interrupt"] - PC6: [2, "Select PC6 as the source input for the EXTI6 external interrupt"] - PD6: [3, "Select PD6 as the source input for the EXTI6 external interrupt"] - PE6: [4, "Select PE6 as the source input for the EXTI6 external interrupt"] - PF6: [5, "Select PF6 as the source input for the EXTI6 external interrupt"] - PG6: [6, "Select PG6 as the source input for the EXTI6 external interrupt"] - EXTI7: - PA7: [0, "Select PA7 as the source input for the EXTI7 external interrupt"] - PB7: [1, "Select PB7 as the source input for the EXTI7 external interrupt"] - PC7: [2, "Select PC7 as the source input for the EXTI7 external interrupt"] - PD7: [3, "Select PD7 as the source input for the EXTI7 external interrupt"] - PE7: [4, "Select PE7 as the source input for the EXTI7 external interrupt"] - PF7: [5, "Select PF7 as the source input for the EXTI7 external interrupt"] - PG7: [6, "Select PG7 as the source input for the EXTI7 external interrupt"] - EXTICR3: - EXTI8: - PA8: [0, "Select PA8 as the source input for the EXTI8 external interrupt"] - PB8: [1, "Select PB8 as the source input for the EXTI8 external interrupt"] - PC8: [2, "Select PC8 as the source input for the EXTI8 external interrupt"] - PD8: [3, "Select PD8 as the source input for the EXTI8 external interrupt"] - PE8: [4, "Select PE8 as the source input for the EXTI8 external interrupt"] - PF8: [5, "Select PF8 as the source input for the EXTI8 external interrupt"] - PG8: [6, "Select PG8 as the source input for the EXTI8 external interrupt"] - EXTI9: - PA9: [0, "Select PA9 as the source input for the EXTI9 external interrupt"] - PB9: [1, "Select PB9 as the source input for the EXTI9 external interrupt"] - PC9: [2, "Select PC9 as the source input for the EXTI9 external interrupt"] - PD9: [3, "Select PD9 as the source input for the EXTI9 external interrupt"] - PE9: [4, "Select PE9 as the source input for the EXTI9 external interrupt"] - PF9: [5, "Select PF9 as the source input for the EXTI9 external interrupt"] - PG9: [6, "Select PG9 as the source input for the EXTI9 external interrupt"] - EXTI10: - PA10: [0, "Select PA10 as the source input for the EXTI10 external interrupt"] - PB10: [1, "Select PB10 as the source input for the EXTI10 external interrupt"] - PC10: [2, "Select PC10 as the source input for the EXTI10 external interrupt"] - PD10: [3, "Select PD10 as the source input for the EXTI10 external interrupt"] - PE10: [4, "Select PE10 as the source input for the EXTI10 external interrupt"] - PF10: [5, "Select PF10 as the source input for the EXTI10 external interrupt"] - PG10: [6, "Select PG10 as the source input for the EXTI10 external interrupt"] - EXTI11: - PA11: [0, "Select PA11 as the source input for the EXTI11 external interrupt"] - PB11: [1, "Select PB11 as the source input for the EXTI11 external interrupt"] - PC11: [2, "Select PC11 as the source input for the EXTI11 external interrupt"] - PD11: [3, "Select PD11 as the source input for the EXTI11 external interrupt"] - PE11: [4, "Select PE11 as the source input for the EXTI11 external interrupt"] - PF11: [5, "Select PF11 as the source input for the EXTI11 external interrupt"] - PG11: [6, "Select PG11 as the source input for the EXTI11 external interrupt"] - EXTICR4: - EXTI12: - PA12: [0, "Select PA12 as the source input for the EXTI12 external interrupt"] - PB12: [1, "Select PB12 as the source input for the EXTI12 external interrupt"] - PC12: [2, "Select PC12 as the source input for the EXTI12 external interrupt"] - PD12: [3, "Select PD12 as the source input for the EXTI12 external interrupt"] - PE12: [4, "Select PE12 as the source input for the EXTI12 external interrupt"] - PF12: [5, "Select PF12 as the source input for the EXTI12 external interrupt"] - PG12: [6, "Select PG12 as the source input for the EXTI12 external interrupt"] - EXTI13: - PA13: [0, "Select PA13 as the source input for the EXTI13 external interrupt"] - PB13: [1, "Select PB13 as the source input for the EXTI13 external interrupt"] - PC13: [2, "Select PC13 as the source input for the EXTI13 external interrupt"] - PD13: [3, "Select PD13 as the source input for the EXTI13 external interrupt"] - PE13: [4, "Select PE13 as the source input for the EXTI13 external interrupt"] - PF13: [5, "Select PF13 as the source input for the EXTI13 external interrupt"] - PG13: [6, "Select PG13 as the source input for the EXTI13 external interrupt"] - EXTI14: - PA14: [0, "Select PA14 as the source input for the EXTI14 external interrupt"] - PB14: [1, "Select PB14 as the source input for the EXTI14 external interrupt"] - PC14: [2, "Select PC14 as the source input for the EXTI14 external interrupt"] - PD14: [3, "Select PD14 as the source input for the EXTI14 external interrupt"] - PE14: [4, "Select PE14 as the source input for the EXTI14 external interrupt"] - PF14: [5, "Select PF14 as the source input for the EXTI14 external interrupt"] - PG14: [6, "Select PG14 as the source input for the EXTI14 external interrupt"] - EXTI15: - PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] - PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] - PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] - PD15: [3, "Select PD15 as the source input for the EXTI15 external interrupt"] - PE15: [4, "Select PE15 as the source input for the EXTI15 external interrupt"] - PF15: [5, "Select PF15 as the source input for the EXTI15 external interrupt"] - PG15: [6, "Select PG15 as the source input for the EXTI15 external interrupt"] - CFGR2: - SRAM_PEF: - _read: - NoParityError: [0, "No SRAM parity error detected"] - ParityErrorDetected: [1, "SRAM parity error detected"] - _write: - Clear: [1, "Clear SRAM parity error flag"] - BYP_ADDR_PAR: - NoBypass: [0, "The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated"] - Bypass: [1, "The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated"] - SRAM_PARITY_LOCK: - Disconnected: [0, "SRAM parity error disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "SRAM parity error connected to TIM1/15/16/17 Break input"] - LOCKUP_LOCK: - Disconnected: [0, "Cortex-M4F LOCKUP output disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "Cortex-M4F LOCKUP output connected to TIM1/15/16/17 Break input"] - CFGR3: - ADC2_DMA_RMP: - MapDma2: [0, "ADC2 mapped on DMA2"] - MapDma1Ch2: [3, "ADC2 mapped on DMA1 channel 2"] - MapDma1Ch4: [4, "DC2 mapped on DMA1 channel 4"] - I2C1_TX_DMA_RMP: - MapDma1Ch6: [0, "I2C1_TX mapped on DMA1 CH6"] - MapDma1Ch2: [1, "I2C1_TX mapped on DMA1 CH2"] - MapDma1Ch4: [2, "I2C1_TX mapped on DMA1 CH4"] - I2C1_RX_DMA_RMP: - MapDma1Ch7: [0, "I2C1_RX mapped on DMA1 CH7"] - MapDma1Ch3: [1, "I2C1_RX mapped on DMA1 CH3"] - MapDma1Ch5: [2, "I2C1_RX mapped on DMA1 CH5"] - SPI1_TX_DMA_RMP: - MapDma1Ch3: [0, "SPI1_TX mapped on DMA1 CH3"] - MapDma1Ch5: [1, "SPI1_TX mapped on DMA1 CH5"] - MapDma1Ch7: [2, "SPI1_TX mapped on DMA1 CH7"] - SPI1_RX_DMA_RMP: - MapDma1Ch3: [0, "SPI1_RX mapped on DMA1 CH2"] - MapDma1Ch5: [1, "SPI1_RX mapped on DMA1 CH4"] - MapDma1Ch7: [2, "SPI1_RX mapped on DMA1 CH6"] - CFGR4: - ADC34_JEXT14_RMP: - Tim7: [0, "Trigger source is TIM7_TRGO"] - Tim20: [1, "Trigger source is TIM20_CC2"] - ADC34_JEXT11_RMP: - Tim1: [0, "Trigger source is TIM1_CC3"] - Tim20: [1, "Trigger source is TIM20_TRGO2"] - ADC34_JEXT5_RMP: - Tim4: [0, "Trigger source is TIM4_CC3"] - Tim20: [1, "Trigger source is TIM20_TRGO"] - ADC34_EXT15_RMP: - Tim2: [0, "Trigger source is TIM2_CC1"] - Tim20: [1, "Trigger source is TIM20_CC1"] - ADC34_EXT6_RMP: - Tim4: [0, "Trigger source is TIM4_CC1"] - Tim20: [1, "Trigger source is TIM20_TRGO2"] - ADC34_EXT5_RMP: - Exti2: [0, "Trigger source is EXTI line 2 when reset at 0"] - Tim20: [1, "Trigger source is TIM20_TRGO"] - ADC12_JEXT13_RMP: - Tim3: [0, "Trigger source is TIM3_CC1"] - Tim20: [1, "Trigger source is TIM20_CC4"] - ADC12_JEXT6_RMP: - Exti15: [0, "Trigger source is EXTI line 15"] - Tim20: [1, "Trigger source is TIM20_TRGO2"] - ADC12_JEXT3_RMP: - Tim2: [0, "Trigger source is TIM2_CC1"] - Tim20: [1, "Trigger source is TIM20_TRGO"] - ADC12_EXT15_RMP: - Tim3: [0, "Trigger source is TIM3_CC4"] - Tim20: [1, "Trigger source is TIM20_CC3"] - ADC12_EXT13_RMP: - Tim6: [0, "Trigger source is TIM6_TRGO"] - Tim20: [1, "Trigger source is TIM20_CC2"] - ADC12_EXT5_RMP: - Tim4: [0, "Trigger source is TIM4_CC4"] - Tim20: [1, "Trigger source is TIM20_CC1"] - ADC12_EXT3_RMP: - Tim2: [0, "Trigger source is TIM2_CC2"] - Tim20: [1, "rigger source is TIM20_TRGO2"] - ADC12_EXT2_RMP: - Tim1: [0, "Trigger source is TIM3_CC3"] - Tim20: [1, "rigger source is TIM20_TRGO"] diff --git a/peripherals/syscfg/syscfg_f37x.yaml b/peripherals/syscfg/syscfg_f37x.yaml deleted file mode 100644 index 8f5f318de..000000000 --- a/peripherals/syscfg/syscfg_f37x.yaml +++ /dev/null @@ -1,137 +0,0 @@ -SYSCFG: - CFGR1: - VBAT_MON: - Disable: [0, "Disable the power switch to not deliver VBAT voltage on ADC channel 18 input"] - Enable: [1, "Enable the power switch to deliver VBAT voltage on ADC channel 18 input"] - TIM18_DAC2_OUT1_DMA_RMP: - NotRemapped: [0, "TIM18 and DAC2_OUT1 DMA requests mapped on DMA2 channel 5"] - Remapped: [1, "TIM18 and DAC2_OUT1 DMA requests mapped on DMA1 channel 5"] - TIM7_DAC1_OUT2_DMA_RMP: - NotRemapped: [0, "TIM7 and DAC1_OUT2 DMA requests mapped on DMA2 channel 4"] - Remapped: [1, "TIM7 and DAC1_OUT2 DMA requests mapped on DMA1 channel 4"] - TIM6_DAC1_OUT1_DMA_RMP: - NotRemapped: [0, "TIM7 and DAC1_OUT1 DMA requests mapped on DMA2 channel 3"] - Remapped: [1, "TIM7 and DAC1_OUT1 DMA requests mapped on DMA1 channel 3"] - MEM_MODE: - MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] - SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] - MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] - SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] - EXTICR1: - EXTI0: - PA0: [0, "Select PA0 as the source input for the EXTI0 external interrupt"] - PB0: [1, "Select PB0 as the source input for the EXTI0 external interrupt"] - PC0: [2, "Select PC0 as the source input for the EXTI0 external interrupt"] - PD0: [3, "Select PD0 as the source input for the EXTI0 external interrupt"] - PE0: [4, "Select PE0 as the source input for the EXTI0 external interrupt"] - PF0: [5, "Select PF0 as the source input for the EXTI0 external interrupt"] - EXTI1: - PA1: [0, "Select PA1 as the source input for the EXTI1 external interrupt"] - PB1: [1, "Select PB1 as the source input for the EXTI1 external interrupt"] - PC1: [2, "Select PC1 as the source input for the EXTI1 external interrupt"] - PD1: [3, "Select PD1 as the source input for the EXTI1 external interrupt"] - PE1: [4, "Select PE1 as the source input for the EXTI1 external interrupt"] - PF1: [5, "Select PF1 as the source input for the EXTI1 external interrupt"] - EXTI2: - PA2: [0, "Select PA2 as the source input for the EXTI2 external interrupt"] - PB2: [1, "Select PB2 as the source input for the EXTI2 external interrupt"] - PC2: [2, "Select PC2 as the source input for the EXTI2 external interrupt"] - PD2: [3, "Select PD2 as the source input for the EXTI2 external interrupt"] - PE2: [4, "Select PE2 as the source input for the EXTI2 external interrupt"] - PF2: [5, "Select PF2 as the source input for the EXTI2 external interrupt"] - EXTI3: - PA3: [0, "Select PA3 as the source input for the EXTI3 external interrupt"] - PB3: [1, "Select PB3 as the source input for the EXTI3 external interrupt"] - PC3: [2, "Select PC3 as the source input for the EXTI3 external interrupt"] - PD3: [3, "Select PD3 as the source input for the EXTI3 external interrupt"] - PE3: [4, "Select PE3 as the source input for the EXTI3 external interrupt"] - EXTICR2: - EXTI4: - PA4: [0, "Select PA4 as the source input for the EXTI4 external interrupt"] - PB4: [1, "Select PB4 as the source input for the EXTI4 external interrupt"] - PC4: [2, "Select PC4 as the source input for the EXTI4 external interrupt"] - PD4: [3, "Select PD4 as the source input for the EXTI4 external interrupt"] - PE4: [4, "Select PE4 as the source input for the EXTI4 external interrupt"] - PF4: [5, "Select PF4 as the source input for the EXTI4 external interrupt"] - EXTI5: - PA5: [0, "Select PA5 as the source input for the EXTI5 external interrupt"] - PB5: [1, "Select PB5 as the source input for the EXTI5 external interrupt"] - PC5: [2, "Select PC5 as the source input for the EXTI5 external interrupt"] - PD5: [3, "Select PD5 as the source input for the EXTI5 external interrupt"] - PE5: [4, "Select PE5 as the source input for the EXTI5 external interrupt"] - EXTI6: - PA6: [0, "Select PA6 as the source input for the EXTI6 external interrupt"] - PB6: [1, "Select PB6 as the source input for the EXTI6 external interrupt"] - PC6: [2, "Select PC6 as the source input for the EXTI6 external interrupt"] - PD6: [3, "Select PD6 as the source input for the EXTI6 external interrupt"] - PE6: [4, "Select PE6 as the source input for the EXTI6 external interrupt"] - PF6: [5, "Select PF6 as the source input for the EXTI6 external interrupt"] - EXTI7: - PA7: [0, "Select PA7 as the source input for the EXTI7 external interrupt"] - PB7: [1, "Select PB7 as the source input for the EXTI7 external interrupt"] - PC7: [2, "Select PC7 as the source input for the EXTI7 external interrupt"] - PD7: [3, "Select PD7 as the source input for the EXTI7 external interrupt"] - PE7: [4, "Select PE7 as the source input for the EXTI7 external interrupt"] - PF7: [5, "Select PF7 as the source input for the EXTI7 external interrupt"] - EXTICR3: - EXTI8: - PA8: [0, "Select PA8 as the source input for the EXTI8 external interrupt"] - PB8: [1, "Select PB8 as the source input for the EXTI8 external interrupt"] - PC8: [2, "Select PC8 as the source input for the EXTI8 external interrupt"] - PD8: [3, "Select PD8 as the source input for the EXTI8 external interrupt"] - PE8: [4, "Select PE8 as the source input for the EXTI8 external interrupt"] - EXTI9: - PA9: [0, "Select PA9 as the source input for the EXTI9 external interrupt"] - PB9: [1, "Select PB9 as the source input for the EXTI9 external interrupt"] - PC9: [2, "Select PC9 as the source input for the EXTI9 external interrupt"] - PD9: [3, "Select PD9 as the source input for the EXTI9 external interrupt"] - PE9: [4, "Select PE9 as the source input for the EXTI9 external interrupt"] - PF9: [5, "Select PF9 as the source input for the EXTI9 external interrupt"] - EXTI10: - PA10: [0, "Select PA10 as the source input for the EXTI10 external interrupt"] - PB10: [1, "Select PB10 as the source input for the EXTI10 external interrupt"] - PC10: [2, "Select PC10 as the source input for the EXTI10 external interrupt"] - PD10: [3, "Select PD10 as the source input for the EXTI10 external interrupt"] - PE10: [4, "Select PE10 as the source input for the EXTI10 external interrupt"] - PF10: [5, "Select PF10 as the source input for the EXTI10 external interrupt"] - EXTI11: - PA11: [0, "Select PA11 as the source input for the EXTI11 external interrupt"] - PC11: [2, "Select PC11 as the source input for the EXTI11 external interrupt"] - PD11: [3, "Select PD11 as the source input for the EXTI11 external interrupt"] - PE11: [4, "Select PE11 as the source input for the EXTI11 external interrupt"] - EXTICR4: - EXTI12: - PA12: [0, "Select PA12 as the source input for the EXTI12 external interrupt"] - PC12: [2, "Select PC12 as the source input for the EXTI12 external interrupt"] - PD12: [3, "Select PD12 as the source input for the EXTI12 external interrupt"] - PE12: [4, "Select PE12 as the source input for the EXTI12 external interrupt"] - EXTI13: - PA13: [0, "Select PA13 as the source input for the EXTI13 external interrupt"] - PC13: [2, "Select PC13 as the source input for the EXTI13 external interrupt"] - PD13: [3, "Select PD13 as the source input for the EXTI13 external interrupt"] - PE13: [4, "Select PE13 as the source input for the EXTI13 external interrupt"] - EXTI14: - PA14: [0, "Select PA14 as the source input for the EXTI14 external interrupt"] - PB14: [1, "Select PB14 as the source input for the EXTI14 external interrupt"] - PC14: [2, "Select PC14 as the source input for the EXTI14 external interrupt"] - PD14: [3, "Select PD14 as the source input for the EXTI14 external interrupt"] - PE14: [4, "Select PE14 as the source input for the EXTI14 external interrupt"] - EXTI15: - PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] - PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] - PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] - PD15: [3, "Select PD15 as the source input for the EXTI15 external interrupt"] - PE15: [4, "Select PE15 as the source input for the EXTI15 external interrupt"] - CFGR2: - SRAM_PEF: - _read: - NoParityError: [0, "No SRAM parity error detected"] - ParityErrorDetected: [1, "SRAM parity error detected"] - _write: - Clear: [1, "Clear SRAM parity error flag"] - SRAM_PARITY_LOCK: - Disconnected: [0, "SRAM parity error disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "SRAM parity error connected to TIM1/15/16/17 Break input"] - LOCKUP_LOCK: - Disconnected: [0, "Cortex-M4F LOCKUP output disconnected from TIM1/15/16/17 Break input"] - Connected: [1, "Cortex-M4F LOCKUP output connected to TIM1/15/16/17 Break input"] diff --git a/peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml b/peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml deleted file mode 100644 index bb5009045..000000000 --- a/peripherals/syscfg/syscfg_f3_cfgr2_pvd_lock.yaml +++ /dev/null @@ -1,5 +0,0 @@ -SYSCFG: - CFGR2: - PVD_LOCK: - Disconnected: [0, "PVD interrupt disconnected from TIM15/16/17 Break input"] - Connected: [1, "PVD interrupt connected to TIM15/16/17 Break input"] diff --git a/peripherals/syscfg/syscfg_f3x4.yaml b/peripherals/syscfg/syscfg_f3x4.yaml deleted file mode 100644 index df11452d4..000000000 --- a/peripherals/syscfg/syscfg_f3x4.yaml +++ /dev/null @@ -1,181 +0,0 @@ -SYSCFG: - CFGR1: - ENCODER_MODE: - NoRedirection: [0, "No redirection"] - MapTim2Tim15: [1, "TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively"] - MapTim3Tim15: [2, "TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively"] - DAC2_CH1_DMA_RMP: - NotRemapped: [0, "Not remapped"] - Remapped: [1, "DAC2_CH1 DMA requests mapped on DMA1 channel 5"] - TIM7_DAC1_CH2_DMA_RMP: - NotRemapped: [0, "Not remapped"] - Remapped: [1, "TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4"] - TIM6_DAC1_CH1_DMA_RMP: - NotRemapped: [0, "TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3"] - Remapped: [1, "TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3"] - DAC_TRIG_RMP: - NotRemapped: [0, "Not remapped"] - Remapped: [1, "DAC trigger is TIM3_TRGO"] - TIM1_ITR3_RMP: - NotRemapped: [0, "Not remapped"] - Remapped: [1, "TIM1_ITR3 = TIM17_OC"] - MEM_MODE: - MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] - SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] - MainFlash2: [2, "Main Flash memory mapped at 0x0000_0000"] - SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] - RCR: - PAGE*_WP: - Disabled: [0, "Write protection of pagex is disabled"] - Enabled: [1, "Write protection of pagex is enabled"] - EXTICR1: - EXTI0: - PA0: [0, "Select PA0 as the source input for the EXTI0 external interrupt"] - PB0: [1, "Select PB0 as the source input for the EXTI0 external interrupt"] - PC0: [2, "Select PC0 as the source input for the EXTI0 external interrupt"] - PD0: [3, "Select PD0 as the source input for the EXTI0 external interrupt"] - PE0: [4, "Select PE0 as the source input for the EXTI0 external interrupt"] - PF0: [5, "Select PF0 as the source input for the EXTI0 external interrupt"] - EXTI1: - PA1: [0, "Select PA1 as the source input for the EXTI1 external interrupt"] - PB1: [1, "Select PB1 as the source input for the EXTI1 external interrupt"] - PC1: [2, "Select PC1 as the source input for the EXTI1 external interrupt"] - PD1: [3, "Select PD1 as the source input for the EXTI1 external interrupt"] - PE1: [4, "Select PE1 as the source input for the EXTI1 external interrupt"] - PF1: [5, "Select PF1 as the source input for the EXTI1 external interrupt"] - EXTI2: - PA2: [0, "Select PA2 as the source input for the EXTI2 external interrupt"] - PB2: [1, "Select PB2 as the source input for the EXTI2 external interrupt"] - PC2: [2, "Select PC2 as the source input for the EXTI2 external interrupt"] - PD2: [3, "Select PD2 as the source input for the EXTI2 external interrupt"] - PE2: [4, "Select PE2 as the source input for the EXTI2 external interrupt"] - PF2: [5, "Select PF2 as the source input for the EXTI2 external interrupt"] - EXTI3: - PA3: [0, "Select PA3 as the source input for the EXTI3 external interrupt"] - PB3: [1, "Select PB3 as the source input for the EXTI3 external interrupt"] - PC3: [2, "Select PC3 as the source input for the EXTI3 external interrupt"] - PD3: [3, "Select PD3 as the source input for the EXTI3 external interrupt"] - PE3: [4, "Select PE3 as the source input for the EXTI3 external interrupt"] - EXTICR2: - EXTI4: - PA4: [0, "Select PA4 as the source input for the EXTI4 external interrupt"] - PB4: [1, "Select PB4 as the source input for the EXTI4 external interrupt"] - PC4: [2, "Select PC4 as the source input for the EXTI4 external interrupt"] - PD4: [3, "Select PD4 as the source input for the EXTI4 external interrupt"] - PE4: [4, "Select PE4 as the source input for the EXTI4 external interrupt"] - PF4: [5, "Select PF4 as the source input for the EXTI4 external interrupt"] - EXTI5: - PA5: [0, "Select PA5 as the source input for the EXTI5 external interrupt"] - PB5: [1, "Select PB5 as the source input for the EXTI5 external interrupt"] - PC5: [2, "Select PC5 as the source input for the EXTI5 external interrupt"] - PD5: [3, "Select PD5 as the source input for the EXTI5 external interrupt"] - PE5: [4, "Select PE5 as the source input for the EXTI5 external interrupt"] - PF5: [5, "Select PF5 as the source input for the EXTI5 external interrupt"] - EXTI6: - PA6: [0, "Select PA6 as the source input for the EXTI6 external interrupt"] - PB6: [1, "Select PB6 as the source input for the EXTI6 external interrupt"] - PC6: [2, "Select PC6 as the source input for the EXTI6 external interrupt"] - PD6: [3, "Select PD6 as the source input for the EXTI6 external interrupt"] - PE6: [4, "Select PE6 as the source input for the EXTI6 external interrupt"] - PF6: [5, "Select PF6 as the source input for the EXTI6 external interrupt"] - EXTI7: - PA7: [0, "Select PA7 as the source input for the EXTI7 external interrupt"] - PB7: [1, "Select PB7 as the source input for the EXTI7 external interrupt"] - PC7: [2, "Select PC7 as the source input for the EXTI7 external interrupt"] - PD7: [3, "Select PD7 as the source input for the EXTI7 external interrupt"] - PE7: [4, "Select PE7 as the source input for the EXTI7 external interrupt"] - EXTICR3: - EXTI8: - PA8: [0, "Select PA8 as the source input for the EXTI8 external interrupt"] - PB8: [1, "Select PB8 as the source input for the EXTI8 external interrupt"] - PC8: [2, "Select PC8 as the source input for the EXTI8 external interrupt"] - PD8: [3, "Select PD8 as the source input for the EXTI8 external interrupt"] - PE8: [4, "Select PE8 as the source input for the EXTI8 external interrupt"] - EXTI9: - PA9: [0, "Select PA9 as the source input for the EXTI9 external interrupt"] - PB9: [1, "Select PB9 as the source input for the EXTI9 external interrupt"] - PC9: [2, "Select PC9 as the source input for the EXTI9 external interrupt"] - PD9: [3, "Select PD9 as the source input for the EXTI9 external interrupt"] - PE9: [4, "Select PE9 as the source input for the EXTI9 external interrupt"] - PF9: [5, "Select PF9 as the source input for the EXTI9 external interrupt"] - EXTI10: - PA10: [0, "Select PA10 as the source input for the EXTI10 external interrupt"] - PB10: [1, "Select PB10 as the source input for the EXTI10 external interrupt"] - PC10: [2, "Select PC10 as the source input for the EXTI10 external interrupt"] - PD10: [3, "Select PD10 as the source input for the EXTI10 external interrupt"] - PE10: [4, "Select PE10 as the source input for the EXTI10 external interrupt"] - PF10: [5, "Select PF10 as the source input for the EXTI10 external interrupt"] - EXTI11: - PA11: [0, "Select PA11 as the source input for the EXTI11 external interrupt"] - PB11: [1, "Select PB11 as the source input for the EXTI11 external interrupt"] - PC11: [2, "Select PC11 as the source input for the EXTI11 external interrupt"] - PD11: [3, "Select PD11 as the source input for the EXTI11 external interrupt"] - PE11: [4, "Select PE11 as the source input for the EXTI11 external interrupt"] - EXTICR4: - EXTI12: - PA12: [0, "Select PA12 as the source input for the EXTI12 external interrupt"] - PB12: [1, "Select PB12 as the source input for the EXTI12 external interrupt"] - PC12: [2, "Select PC12 as the source input for the EXTI12 external interrupt"] - PD12: [3, "Select PD12 as the source input for the EXTI12 external interrupt"] - PE12: [4, "Select PE12 as the source input for the EXTI12 external interrupt"] - EXTI13: - PA13: [0, "Select PA13 as the source input for the EXTI13 external interrupt"] - PB13: [1, "Select PB13 as the source input for the EXTI13 external interrupt"] - PC13: [2, "Select PC13 as the source input for the EXTI13 external interrupt"] - PD13: [3, "Select PD13 as the source input for the EXTI13 external interrupt"] - PE13: [4, "Select PE13 as the source input for the EXTI13 external interrupt"] - EXTI14: - PA14: [0, "Select PA14 as the source input for the EXTI14 external interrupt"] - PB14: [1, "Select PB14 as the source input for the EXTI14 external interrupt"] - PC14: [2, "Select PC14 as the source input for the EXTI14 external interrupt"] - PD14: [3, "Select PD14 as the source input for the EXTI14 external interrupt"] - PE14: [4, "Select PE14 as the source input for the EXTI14 external interrupt"] - EXTI15: - PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] - PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] - PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] - PD15: [3, "Select PD15 as the source input for the EXTI15 external interrupt"] - PE15: [4, "Select PE15 as the source input for the EXTI15 external interrupt"] - CFGR2: - SRAM_PEF: - _read: - NoParityError: [0, "No SRAM parity error detected"] - ParityErrorDetected: [1, "SRAM parity error detected"] - _write: - Clear: [1, "Clear SRAM parity error flag"] - BYP_ADDR_PAR: - NoBypass: [0, "The ramload operation is performed taking into consideration bit 29 of the address when the parity is calculated"] - Bypass: [1, "The ramload operation is performed without taking into consideration bit 29 of the address when the parity is calculated"] - SRAM_PARITY_LOCK: - Disconnected: [0, "SRAM parity error signal disconnected from TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs"] - Connected: [1, "SRAM parity error signal connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs"] - LOCKUP_LOCK: - Disconnected: [0, "Cortex-M4 LOCKUP output disconnected from TIM1/15/16/17 Break inputs and HRTIM1 SYSFLT."] - Connected: [1, "Cortex-M4 LOCKUP output connected to TIM1/15/16/17 and HRTIM1 SYSFLT Break inputs"] - CFGR3: - DAC1_TRIG5_RMP: - NotRemapped: [0, "Not remapped"] - Remapped: [1, "DAC trigger is HRTIM1_DAC1_TRIG2"] - DAC1_TRIG3_RMP: - Tim15: [0, "DAC trigger is TIM15_TRGO"] - HrTim1: [1, "DAC trigger is HRTIM1_DAC1_TRIG1"] - ADC2_DMA_RMP: - MapDma2: [0, "ADC2 mapped on DMA2"] - MapDma1Ch2: [3, "ADC2 mapped on DMA1 channel 2"] - MapDma1Ch4: [4, "DC2 mapped on DMA1 channel 4"] - I2C1_TX_DMA_RMP: - MapDma1Ch6: [0, "I2C1_TX mapped on DMA1 CH6"] - MapDma1Ch2: [1, "I2C1_TX mapped on DMA1 CH2"] - MapDma1Ch4: [2, "I2C1_TX mapped on DMA1 CH4"] - I2C1_RX_DMA_RMP: - MapDma1Ch7: [0, "I2C1_RX mapped on DMA1 CH7"] - MapDma1Ch3: [1, "I2C1_RX mapped on DMA1 CH3"] - MapDma1Ch5: [2, "I2C1_RX mapped on DMA1 CH5"] - SPI1_TX_DMA_RMP: - MapDma1Ch3: [0, "SPI1_TX mapped on DMA1 CH3"] - MapDma1Ch5: [1, "SPI1_TX mapped on DMA1 CH5"] - MapDma1Ch7: [2, "SPI1_TX mapped on DMA1 CH7"] - SPI1_RX_DMA_RMP: - MapDma1Ch3: [0, "SPI1_RX mapped on DMA1 CH2"] - MapDma1Ch5: [1, "SPI1_RX mapped on DMA1 CH4"] - MapDma1Ch7: [2, "SPI1_RX mapped on DMA1 CH6"] diff --git a/peripherals/syscfg/syscfg_h747.yaml b/peripherals/syscfg/syscfg_h747.yaml deleted file mode 100644 index 202a2b2f0..000000000 --- a/peripherals/syscfg/syscfg_h747.yaml +++ /dev/null @@ -1,5 +0,0 @@ -SYSCFG: - PWRCR: - ODEN: - Disabled: [0, "Overdrive mode disabled"] - Enabled: [1, "Overdrive mode enabled (the LDO generates VOS0 for VCORE)"] diff --git a/peripherals/syscfg/syscfg_l0.yaml b/peripherals/syscfg/syscfg_l0.yaml deleted file mode 100644 index 833df6594..000000000 --- a/peripherals/syscfg/syscfg_l0.yaml +++ /dev/null @@ -1,235 +0,0 @@ -# System configuration controller and COMP registers for L0 family -SYSCFG: - CFGR1: - BOOT_MODE: - MainFlash: [0, "Main Flash memory boot mode"] - SystemFlash: [1, "System Flash memory boot mode"] - SRAM: [3, "Embedded SRAM boot mode"] - UFB: - Bank1: [0, "Flash Program memory Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if MEM_MODE=00) and Data EEPROM Bank 1 at 0x0808 0000 (aliased at 0x0008 0000 if MEM_MODE=00)"] - Bank2: [1, "Flash Program memory Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if MEM_MODE=00) and Data EEPROM Bank 2 at 0x0808 0000 (and aliased at 0x0008 0000 if MEM_MODE=00)"] - MEM_MODE: - MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] - SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] - SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] - CFGR2: - I2C3_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers"] - I2C2_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers"] - I2C1_FMP: - Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] - FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers"] - I2C_PB9_FMP: - Standard: [0, "PB9 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] - I2C_PB8_FMP: - Standard: [0, "PB8 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] - I2C_PB7_FMP: - Standard: [0, "PB7 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] - I2C_PB6_FMP: - Standard: [0, "PB6 pin operate in standard mode"] - FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] - FWDIS: - Enabled: [0, "Firewall access enabled"] - Disabled: [1, "Firewall access disabled"] - CFGR3: - REF_LOCK: - ReadWrite: [0, "SYSCFG_CFGR3[31:0] bits are read/write"] - ReadOnly: [1, "SYSCFG_CFGR3[31:0] bits are read-only"] - VREFINT_RDYF: - NotReady: [0, "VREFINT OFF"] - Ready: [1, "VREFINT ready"] - ENBUF_VREFINT_COMP2: - Disabled: [0, "Disables the buffer used to generate VREFINT references for COMP2"] - Enabled: [1, "Enables the buffer used to generate VREFINT references for COMP2"] - ENBUF_SENSOR_ADC: - Disabled: [0, "Disables the buffer used to generate VREFINT reference for the temperature sensor"] - Enabled: [1, "Enables the buffer used to generate VREFINT reference for the temperature sensor"] - ENBUF_VREFINT_ADC: - Disabled: [0, "Disables the buffer used to generate VREFINT reference for the ADC"] - Enabled: [1, "Enables the buffer used to generate VREFINT reference for the ADC"] - SEL_VREF_OUT: - NoConnection: [0, "no pad connected"] - PB0: [1, "PB0 connected"] - PB1: [2, "PB1 connected"] - Both: [3, "PB0 and PB1 connected"] - EN_VREFINT: - Disabled: [0, "VREFINT voltage disabled in low-power mode (if ULP=1) and scaler for COMP2 disabled"] - Enabled: [1, "VREFINT voltage enabled in low-power mode and scaler for COMP2 enabled"] - EXTICR1: - EXTI0: - PA0: [0, "Select PA0 as the source input for the EXTI0 external interrupt"] - PB0: [1, "Select PB0 as the source input for the EXTI0 external interrupt"] - PC0: [2, "Select PC0 as the source input for the EXTI0 external interrupt"] - PD0: [3, "Select PD0 as the source input for the EXTI0 external interrupt"] - PE0: [4, "Select PE0 as the source input for the EXTI0 external interrupt"] - PH0: [5, "Select PH0 as the source input for the EXTI0 external interrupt"] - EXTI1: - PA1: [0, "Select PA1 as the source input for the EXTI1 external interrupt"] - PB1: [1, "Select PB1 as the source input for the EXTI1 external interrupt"] - PC1: [2, "Select PC1 as the source input for the EXTI1 external interrupt"] - PD1: [3, "Select PD1 as the source input for the EXTI1 external interrupt"] - PE1: [4, "Select PE1 as the source input for the EXTI1 external interrupt"] - PH1: [5, "Select PH1 as the source input for the EXTI1 external interrupt"] - EXTI2: - PA2: [0, "Select PA2 as the source input for the EXTI2 external interrupt"] - PB2: [1, "Select PB2 as the source input for the EXTI2 external interrupt"] - PC2: [2, "Select PC2 as the source input for the EXTI2 external interrupt"] - PD2: [3, "Select PD2 as the source input for the EXTI2 external interrupt"] - PE2: [4, "Select PE2 as the source input for the EXTI2 external interrupt"] - PH2: [5, "Select PH2 as the source input for the EXTI2 external interrupt"] - EXTI3: - PA3: [0, "Select PA3 as the source input for the EXTI3 external interrupt"] - PB3: [1, "Select PB3 as the source input for the EXTI3 external interrupt"] - PC3: [2, "Select PC3 as the source input for the EXTI3 external interrupt"] - PD3: [3, "Select PD3 as the source input for the EXTI3 external interrupt"] - PE3: [4, "Select PE3 as the source input for the EXTI3 external interrupt"] - PH3: [5, "Select PH3 as the source input for the EXTI3 external interrupt"] - EXTICR2: - EXTI4: - PA4: [0, "Select PA4 as the source input for the EXTI4 external interrupt"] - PB4: [1, "Select PB4 as the source input for the EXTI4 external interrupt"] - PC4: [2, "Select PC4 as the source input for the EXTI4 external interrupt"] - PD4: [3, "Select PD4 as the source input for the EXTI4 external interrupt"] - PE4: [4, "Select PE4 as the source input for the EXTI4 external interrupt"] - EXTI5: - PA5: [0, "Select PA5 as the source input for the EXTI5 external interrupt"] - PB5: [1, "Select PB5 as the source input for the EXTI5 external interrupt"] - PC5: [2, "Select PC5 as the source input for the EXTI5 external interrupt"] - PD5: [3, "Select PD5 as the source input for the EXTI5 external interrupt"] - PE5: [4, "Select PE5 as the source input for the EXTI5 external interrupt"] - EXTI6: - PA6: [0, "Select PA6 as the source input for the EXTI6 external interrupt"] - PB6: [1, "Select PB6 as the source input for the EXTI6 external interrupt"] - PC6: [2, "Select PC6 as the source input for the EXTI6 external interrupt"] - PD6: [3, "Select PD6 as the source input for the EXTI6 external interrupt"] - PE6: [4, "Select PE6 as the source input for the EXTI6 external interrupt"] - EXTI7: - PA7: [0, "Select PA7 as the source input for the EXTI7 external interrupt"] - PB7: [1, "Select PB7 as the source input for the EXTI7 external interrupt"] - PC7: [2, "Select PC7 as the source input for the EXTI7 external interrupt"] - PD7: [3, "Select PD7 as the source input for the EXTI7 external interrupt"] - PE7: [4, "Select PE7 as the source input for the EXTI7 external interrupt"] - EXTICR3: - EXTI8: - PA8: [0, "Select PA8 as the source input for the EXTI8 external interrupt"] - PB8: [1, "Select PB8 as the source input for the EXTI8 external interrupt"] - PC8: [2, "Select PC8 as the source input for the EXTI8 external interrupt"] - PD8: [3, "Select PD8 as the source input for the EXTI8 external interrupt"] - PE8: [4, "Select PE8 as the source input for the EXTI8 external interrupt"] - PH8: [5, "Select PH8 as the source input for the EXTI8 external interrupt"] - EXTI9: - PA9: [0, "Select PA9 as the source input for the EXTI9 external interrupt"] - PB9: [1, "Select PB9 as the source input for the EXTI9 external interrupt"] - PC9: [2, "Select PC9 as the source input for the EXTI9 external interrupt"] - PD9: [3, "Select PD9 as the source input for the EXTI9 external interrupt"] - PE9: [4, "Select PE9 as the source input for the EXTI9 external interrupt"] - PH9: [5, "Select PH9 as the source input for the EXTI9 external interrupt"] - EXTI10: - PA10: [0, "Select PA10 as the source input for the EXTI10 external interrupt"] - PB10: [1, "Select PB10 as the source input for the EXTI10 external interrupt"] - PC10: [2, "Select PC10 as the source input for the EXTI10 external interrupt"] - PD10: [3, "Select PD10 as the source input for the EXTI10 external interrupt"] - PE10: [4, "Select PE10 as the source input for the EXTI10 external interrupt"] - PH10: [5, "Select PH10 as the source input for the EXTI10 external interrupt"] - EXTI11: - PA11: [0, "Select PA11 as the source input for the EXTI11 external interrupt"] - PB11: [1, "Select PB11 as the source input for the EXTI11 external interrupt"] - PC11: [2, "Select PC11 as the source input for the EXTI11 external interrupt"] - PD11: [3, "Select PD11 as the source input for the EXTI11 external interrupt"] - PE11: [4, "Select PE11 as the source input for the EXTI11 external interrupt"] - PH11: [5, "Select PH11 as the source input for the EXTI11 external interrupt"] - EXTICR4: - EXTI12: - PA12: [0, "Select PA12 as the source input for the EXTI12 external interrupt"] - PB12: [1, "Select PB12 as the source input for the EXTI12 external interrupt"] - PC12: [2, "Select PC12 as the source input for the EXTI12 external interrupt"] - PD12: [3, "Select PD12 as the source input for the EXTI12 external interrupt"] - PE12: [4, "Select PE12 as the source input for the EXTI12 external interrupt"] - EXTI13: - PA13: [0, "Select PA13 as the source input for the EXTI13 external interrupt"] - PB13: [1, "Select PB13 as the source input for the EXTI13 external interrupt"] - PC13: [2, "Select PC13 as the source input for the EXTI13 external interrupt"] - PD13: [3, "Select PD13 as the source input for the EXTI13 external interrupt"] - PE13: [4, "Select PE13 as the source input for the EXTI13 external interrupt"] - EXTI14: - PA14: [0, "Select PA14 as the source input for the EXTI14 external interrupt"] - PB14: [1, "Select PB14 as the source input for the EXTI14 external interrupt"] - PC14: [2, "Select PC14 as the source input for the EXTI14 external interrupt"] - PD14: [3, "Select PD14 as the source input for the EXTI14 external interrupt"] - PE14: [4, "Select PE14 as the source input for the EXTI14 external interrupt"] - EXTI15: - PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] - PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] - PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] - PD15: [3, "Select PD15 as the source input for the EXTI15 external interrupt"] - PE15: [4, "Select PE15 as the source input for the EXTI15 external interrupt"] - COMP1_CSR: - COMP1LOCK: - ReadWrite: [0, "COMP1_CSR[31:0] for comparator 1 are read/write"] - ReadOnly: [1, "COMP1_CSR[31:0] for comparator 1 are read-only"] - COMP1VALUE: - _read: - NotEqual: [0, "Comparator values are not equal"] - Equal: [1, "Comparator values are equal"] - COMP1POLARITY: - NotInverted: [0, "Comparator 1 output value not inverted"] - Inverted: [1, "Comparator 1 output value inverted"] - COMP1LPTIMIN1: - Gated: [0, "Comparator 1 output gated"] - NotGated: [1, "Comparator 1 output sent to LPTIM input 1"] - COMP1WM: - PA1: [0, "Plus input of comparator 1 connected to PA1"] - Comp2Plus: [1, "Plus input of comparator 1 shorted with Plus input of comparator 2 (see COMP1_CSR)"] - COMP1INNSEL: - VREFINT: [0, "VREFINT"] - PA0: [1, "PA0"] - PA4: [2, "PA4"] - PA5: [3, "PA5"] - COMP1EN: - Disabled: [0, "Comparator 1 switched OFF"] - Enabled: [1, "Comparator 1 switched ON"] - COMP2_CSR: - COMP2LOCK: - ReadWrite: [0, "COMP2_CSR[31:0] for comparator 2 are read/write"] - ReadOnly: [1, "COMP2_CSR[31:0] for comparator 2 are read-only"] - COMP2VALUE: - _read: - NotEqual: [0, "Comparator values are not equal"] - Equal: [1, "Comparator values are equal"] - COMP2POLARITY: - NotInverted: [0, "Comparator 2 output value not inverted"] - Inverted: [1, "Comparator 2 output value inverted"] - COMP2LPTIMIN1: - Gated: [0, "Comparator 2 output gated"] - NotGated: [1, "Comparator 2 output sent to LPTIM input 1"] - COMP2LPTIMIN2: - Gated: [0, "Comparator 2 output gated"] - NotGated: [1, "Comparator 2 output sent to LPTIM input 2"] - COMP2INPSEL: - PA3: [0, "PA3"] - PB4: [1, "PB4"] - PB5: [2, "PB5"] - PB6: [3, "PB6"] - PB7: [4, "PB7"] - PA7: [5, "PA7"] - COMP2INNSEL: - VREFINT: [0, "VREFINT"] - PA2: [1, "PA2"] - PA4: [2, "PA4"] - PA5: [3, "PA5"] - VREFINT_Div4: [4, "1/4 VREFINT"] - VREFINT_Div2: [5, "1/2 VREFINT"] - VREFINT_Div3_4: [6, "3/4 VREFINT"] - PB3: [7, "PB3"] - COMP2SPEED: - Slow: [0, "Slow speed"] - Fast: [1, "Fast speed"] - COMP2EN: - Disabled: [0, "Comparator 2 switched OFF"] - Enabled: [1, "Comparator 2 switched ON"] diff --git a/peripherals/tim/tim1234_1567_ccm_v2.yaml b/peripherals/tim/tim1234_1567_ccm_v2.yaml deleted file mode 100644 index de4d5d022..000000000 --- a/peripherals/tim/tim1234_1567_ccm_v2.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Applies to TIM12 through TIM17 inclusive - -"TIM1[2-7]": - CCMR[12]_Output: - OC[1234]M: - Frozen: [0, "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] - ActiveOnMatch: [1, "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] - InactiveOnMatch: [2, "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] - Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] - ForceInactive: [4, "OCyREF is forced low"] - ForceActive: [5, "OCyREF is forced high"] - PwmMode1: [6, "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] - PwmMode2: [7, "Inversely to PwmMode1"] - OpmMode1: [8, "Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"] - OpmMode2: [9, "Inversely to OpmMode1"] - CombinedPwmMode1: [12, "OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"] - CombinedPwmMode2: [13, "OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"] - AsymmetricPwmMode1: [14, "OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] - AsymmetricPwmMode2: [15, "OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] diff --git a/peripherals/tim/tim14_16bit.yaml b/peripherals/tim/tim14_16bit.yaml deleted file mode 100644 index 1d13c227b..000000000 --- a/peripherals/tim/tim14_16bit.yaml +++ /dev/null @@ -1,4 +0,0 @@ -# TIM14 is 16-bit with one channel -TIM14: - _include: - - ./tim_1ch_16bit.yaml diff --git a/peripherals/tim/tim15_16bit.yaml b/peripherals/tim/tim15_16bit.yaml deleted file mode 100644 index 817f977f2..000000000 --- a/peripherals/tim/tim15_16bit.yaml +++ /dev/null @@ -1,4 +0,0 @@ -# TIM15 is 16-bit with 2 channels -TIM15: - _include: - - ./tim_2ch_16bit.yaml diff --git a/peripherals/tim/tim16.yaml b/peripherals/tim/tim16.yaml deleted file mode 100644 index f23fa8213..000000000 --- a/peripherals/tim/tim16.yaml +++ /dev/null @@ -1,39 +0,0 @@ -# TIM16 and TIM17 peripherals -# All devices that has TIM16 has TIM17 except stm32l4x{1,2,3} where only TIM16 -# exists. -# - -"TIM16": - CR1: - OPM: - NotStopped: [0, "Not stopped at update event"] - Stopped: [1, "Counter stops counting at next update event"] - CR2: - CCPC: - NotPreloaded: [0, "CCxE, CCxNE and OCxM bits are not preloaded"] - Preloaded: [1, "CCxE, CCxNE and OCxM bits are preloaded"] - CCUS: - Default: [0, "Capture/compare are updated only by setting the COMG bit"] - WithRisingEdge: [1, "Capture/compare are updated by setting the COMG bit or when an rising edge occurs on TRGI"] - CCDS: - OnCompare: [0, "CCx DMA request sent when CCx event occurs"] - OnUpdate: [1, "CCx DMA request sent when update event occurs"] - OIS1N: - Low: [0, "OC1N=0 after a dead-time when MOE=0"] - High: [1, "OC1N=1 after a dead-time when MOE=0"] - OIS1: - Low: [0, "OC1=0 (after a dead-time if OC1N is implemented) when MOE=0"] - High: [1, "OC1=1 (after a dead-time if OC1N is implemented) when MOE=0"] - DIER: - CC1IE: - Disabled: [0, "CC1 interrupt disabled"] - Enabled: [1, "CC1 interrupt enabled"] - COMIE: - Disabled: [0, "COM interrupt disabled"] - Enabled: [1, "COM interrupt enabled"] - BIE: - Disabled: [0, "Break interrupt disabled"] - Enabled: [1, "Break interrupt enabled"] - CC1DE: - Disabled: [0, "CC1 DMA request disabled"] - Enabled: [1, "CC1 DMA request enabled"] diff --git a/peripherals/tim/tim16_16bit.yaml b/peripherals/tim/tim16_16bit.yaml deleted file mode 100644 index 76826b517..000000000 --- a/peripherals/tim/tim16_16bit.yaml +++ /dev/null @@ -1,4 +0,0 @@ -# TIM16 is 16-bit with one channel -TIM16: - _include: - - ./tim_1ch_16bit.yaml diff --git a/peripherals/tim/tim1_16bit.yaml b/peripherals/tim/tim1_16bit.yaml deleted file mode 100644 index 11756f8af..000000000 --- a/peripherals/tim/tim1_16bit.yaml +++ /dev/null @@ -1,4 +0,0 @@ -# TIM1 is 16-bit -TIM1: - _include: - - ./tim2_common_16bit.yaml diff --git a/peripherals/tim/tim21.yaml b/peripherals/tim/tim21.yaml deleted file mode 100644 index d26cf4509..000000000 --- a/peripherals/tim/tim21.yaml +++ /dev/null @@ -1,173 +0,0 @@ -# TIM21 and TIM22 peripherals - -"TIM2?": - CR1: - CKD: - Div1: [0, "t_DTS = t_CK_INT"] - Div2: [1, "t_DTS = 2 × t_CK_INT"] - Div4: [2, "t_DTS = 4 × t_CK_INT"] - CMS: - EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] - CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] - CenterAligned2: [2, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] - CenterAligned3: [3, "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] - DIR: - Up: [0, "Counter used as upcounter"] - Down: [1, "Counter used as downcounter"] - OPM: - NotStopped: [0, "Counter is not stopped on the update event"] - Stopped: [1, "Counter stops counting on the next update event (clearing the CEN bit)"] - CR2: - MMS: - Reset: [0, "Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO)"] - Enable: [1, "Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO)"] - Update: [2, "Update - The update event is selected as trigger output (TRGO)"] - ComparePulse: [3, "Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred"] - OC1REF: [4, "OC1REF signal is used as trigger output (TRGO)"] - OC2REF: [5, "OC2REF signal is used as trigger output (TRGO)"] - SMCR: - ETP: - RisingEdge: [0, "ETR is non-inverted, active at high level or rising edge"] - FallingEdge: [1, "ETR is inverted, active at low level or falling edge"] - ECE: - Disabled: [0, "External clock mode 2 disabled"] - Enabled: [1, "External clock mode 2 enabled"] - ETPS: - Div1: [0, "Prescaler OFF"] - Div2: [1, "ETRP frequency divided by 2"] - Div4: [2, "ETRP frequency divided by 4"] - Div8: [3, "ETRP frequency divided by 8"] - ETF: - NoFilter: [0, "No filter, sampling is done at fDTS"] - FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] - FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] - FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] - FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] - FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] - FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] - FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] - FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] - FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] - FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] - FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] - FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] - FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] - FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] - FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] - MSM: - NoSync: [0, "No action"] - Sync: [1, "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] - TS: - ITR0: [0, "Internal Trigger 0 (ITR0)"] - ITR1: [1, "Internal Trigger 1 (ITR1)"] - ITR2: [2, "Internal Trigger 2 (ITR2)"] - TI1F_ED: [4, "TI1 Edge Detector (TI1F_ED)"] - TI1FP1: [5, "Filtered Timer Input 1 (TI1FP1)"] - TI2FP2: [6, "Filtered Timer Input 2 (TI2FP2)"] - ETRF: [7, "External Trigger input (ETRF)"] - SMS: - Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] - Encoder_Mode_1: [1, "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] - Encoder_Mode_2: [2, "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] - Encoder_Mode_3: [3, "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] - Reset_Mode: [4, "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] - Gated_Mode: [5, "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] - Trigger_Mode: [6, "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] - Ext_Clock_Mode: [7, "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] - DIER: - TIE: - Disabled: [0, "Trigger interrupt disabled"] - Enabled: [1, "Trigger interrupt enabled"] - "CC?IE": - Disabled: [0, "CCx interrupt disabled"] - Enabled: [1, "CCx interrupt enabled"] - SR: - "CC?OF": - _read: - Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set"] - _write: - Clear: [0, "Clear flag"] - TIF: - _read: - NoTrigger: [0, "No trigger event occurred"] - Trigger: [1, "Trigger interrupt pending"] - _write: - Clear: [0, "Clear flag"] - "CC?IF": - _read: - Match: [1, "If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register."] - _write: - Clear: [0, "Clear flag"] - EGR: - TG: - _write: - Trigger: [1, "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."] - "CC?G": - _write: - Trigger: [1, "If CCx is an output: CCxIF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CCx is an input: The current value of the counter is captured in TIMx_CCR1 register."] - CCMR?_Input: - IC?F: - NoFilter: [0, "No filter, sampling is done at fDTS"] - FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] - FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] - FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] - FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] - FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] - FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] - FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] - FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] - FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] - FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] - FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] - FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] - FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] - FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] - FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] - IC?PSC: [0, 3] - CC?S: - Output: [0, "CCx channel is configured as output"] - TI1: [1, "CCx channel is configured as input, ICx is mapped on TI1"] - TI2: [2, "CCx channel is configured as input, ICx is mapped on TI2"] - TRC: [3, "CCx channel is configured as input, ICx is mapped on TRC"] - CCMR?_Output: - OC?PE: - Disabled: [0, "Preload register on CCRx disabled. New values written to CCRx are taken into account immediately"] - Enabled: [1, "Preload register on CCRx enabled. Preload value is loaded into active register on each update event"] - CC?S: - Output: [0, "CCx channel is configured as output"] - OC?M: - Frozen: [0, "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] - ActiveOnMatch: [1, "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] - InactiveOnMatch: [2, "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] - Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] - ForceInactive: [4, "OCyREF is forced low"] - ForceActive: [5, "OCyREF is forced high"] - PwmMode1: [6, "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] - PwmMode2: [7, "Inversely to PwmMode1"] - CCER: - "CC?NP": - Negative: [0, "Negative polarity"] - Positive: [1, "Positive polarity"] - "CC?P": - RisingEdge: [0, "Noninverted/rising edge"] - FallingEdge: [1, "Inverted/falling edge"] - "CC?E": - Disabled: [0, "Capture disabled"] - Enabled: [1, "Capture enabled"] - CNT: - CNT: [0, 65535] - ARR: - ARR: [0, 65535] - "CCR?": - "CCR?": [0, 65535] - OR: - TI1_RMP: - GPIO: [0, "TIM2x TI1 input connected to GPIO"] - COMP2_OUT: [1, "TIM2x TI1 input connected to COMP2_OUT"] - COMP1_OUT: [2, "TIM2x TI1 input connected to COMP1_OUT"] - ETR_RMP: - GPIO: [0, "TIM2x ETR input connected to GPIO"] - COMP2_OUT: [1, "TIM2x ETR input connected to COMP2_OUT"] - COMP1_OUT: [2, "TIM2x ETR input connected to COMP1_OUT"] - LSE: [3, "TIM2x ETR input connected to LSE clock"] - diff --git a/peripherals/tim/tim2345_16bit.yaml b/peripherals/tim/tim2345_16bit.yaml deleted file mode 100644 index 55dc6f95b..000000000 --- a/peripherals/tim/tim2345_16bit.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# General-purpose timers on F1, L0 (at least) -# TIM2/TIM3/TIM4/TIM5 are 16 bit - -_include: - - ./tim2_common.yaml - -"TIM[2345]": - _include: - - ./tim2_common_16bit.yaml diff --git a/peripherals/tim/tim2345_mixed.yaml b/peripherals/tim/tim2345_mixed.yaml deleted file mode 100644 index 16400d182..000000000 --- a/peripherals/tim/tim2345_mixed.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# General-purpose timers on F0, F3, F4, F7, H7 (at least) -# TIM2/TIM5 are 32 bit, TIM3/TIM4 are 16 bit - -_include: - - ./tim2_common.yaml - -"TIM[34]": - _include: - - ./tim2_common_16bit.yaml - -"TIM[25]": - _include: - - ./tim2_common_32bit.yaml diff --git a/peripherals/tim/tim2_32bit.yaml b/peripherals/tim/tim2_32bit.yaml deleted file mode 100644 index 7144c53f5..000000000 --- a/peripherals/tim/tim2_32bit.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# General-purpose timer where there is only a single 32-bit timer in -# the TIM[2-5] set. -# -# See tim2345* for when there are other timers - -_include: - - ./tim2_common.yaml - -"TIM2": - _include: - - ./tim2_common_32bit.yaml diff --git a/peripherals/tim/tim2_common.yaml b/peripherals/tim/tim2_common.yaml deleted file mode 100644 index 6257d6fc3..000000000 --- a/peripherals/tim/tim2_common.yaml +++ /dev/null @@ -1,173 +0,0 @@ -# Common base for 16bit and 32bit TIM2 peripheral - -"TIM[1-58]": - CR2: - TI1S: - Normal: [0, "The TIMx_CH1 pin is connected to TI1 input"] - XOR: [1, "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] - MMS: - Reset: [0, "The UG bit from the TIMx_EGR register is used as trigger output"] - Enable: [1, "The counter enable signal, CNT_EN, is used as trigger output"] - Update: [2, "The update event is selected as trigger output"] - ComparePulse: [3, "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] - CompareOC1: [4, "OC1REF signal is used as trigger output"] - CompareOC2: [5, "OC2REF signal is used as trigger output"] - CompareOC3: [6, "OC3REF signal is used as trigger output"] - CompareOC4: [7, "OC4REF signal is used as trigger output"] - CCDS: - OnCompare: [0, "CCx DMA request sent when CCx event occurs"] - OnUpdate: [1, "CCx DMA request sent when update event occurs"] - SMCR: - ETP: - NotInverted: [0, "ETR is noninverted, active at high level or rising edge"] - Inverted: [1, "ETR is inverted, active at low level or falling edge"] - ECE: - Disabled: [0, "External clock mode 2 disabled"] - Enabled: [1, "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] - ETPS: - Div1: [0, "Prescaler OFF"] - Div2: [1, "ETRP frequency divided by 2"] - Div4: [2, "ETRP frequency divided by 4"] - Div8: [3, "ETRP frequency divided by 8"] - ETF: - NoFilter: [0, "No filter, sampling is done at fDTS"] - FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] - FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] - FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] - FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] - FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] - FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] - FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] - FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] - FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] - FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] - FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] - FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] - FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] - FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] - FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] - MSM: - NoSync: [0, "No action"] - Sync: [1, "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] - TS: - ITR0: [0, "Internal Trigger 0 (ITR0)"] - ITR1: [1, "Internal Trigger 1 (ITR1)"] - ITR2: [2, "Internal Trigger 2 (ITR2)"] - TI1F_ED: [4, "TI1 Edge Detector (TI1F_ED)"] - TI1FP1: [5, "Filtered Timer Input 1 (TI1FP1)"] - TI2FP2: [6, "Filtered Timer Input 2 (TI2FP2)"] - ETRF: [7, "External Trigger input (ETRF)"] - SMS: - Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] - Encoder_Mode_1: [1, "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] - Encoder_Mode_2: [2, "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] - Encoder_Mode_3: [3, "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] - Reset_Mode: [4, "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] - Gated_Mode: [5, "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] - Trigger_Mode: [6, "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] - Ext_Clock_Mode: [7, "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] - DIER: - TDE: - Disabled: [0, "Trigger DMA request disabled"] - Enabled: [1, "Trigger DMA request enabled"] - "CC?DE": - Disabled: [0, "CCx DMA request disabled"] - Enabled: [1, "CCx DMA request enabled"] - UDE: - Disabled: [0, "Update DMA request disabled"] - Enabled: [1, "Update DMA request enabled"] - TIE: - Disabled: [0, "Trigger interrupt disabled"] - Enabled: [1, "Trigger interrupt enabled"] - "CC?IE": - Disabled: [0, "CCx interrupt disabled"] - Enabled: [1, "CCx interrupt enabled"] - SR: - "CC?OF": - _read: - Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set"] - _write: - Clear: [0, "Clear flag"] - TIF: - _read: - NoTrigger: [0, "No trigger event occurred"] - Trigger: [1, "Trigger interrupt pending"] - _write: - Clear: [0, "Clear flag"] - "CC?IF": - _read: - Match: [1, "If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register."] - _write: - Clear: [0, "Clear flag"] - EGR: - TG: - _write: - Trigger: [1, "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."] - "CC?G": - _write: - Trigger: [1, "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register."] - CCMR1_Input: - IC2F: [0, 15] - CC2S: - TI2: [1, "CC2 channel is configured as input, IC2 is mapped on TI2"] - TI1: [2, "CC2 channel is configured as input, IC2 is mapped on TI1"] - TRC: [3, "CC2 channel is configured as input, IC2 is mapped on TRC"] - IC1F: - NoFilter: [0, "No filter, sampling is done at fDTS"] - FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] - FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] - FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] - FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] - FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] - FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] - FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] - FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] - FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] - FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] - FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] - FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] - FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] - FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] - FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] - CC1S: - TI1: [1, "CC1 channel is configured as input, IC1 is mapped on TI1"] - TI2: [2, "CC1 channel is configured as input, IC1 is mapped on TI2"] - TRC: [3, "CC1 channel is configured as input, IC1 is mapped on TRC"] - CCMR2_Input: - IC4F: [0, 15] - IC4PSC: [0, 3] - CC4S: - TI4: [1, "CC4 channel is configured as input, IC4 is mapped on TI4"] - TI3: [2, "CC4 channel is configured as input, IC4 is mapped on TI3"] - TRC: [3, "CC4 channel is configured as input, IC4 is mapped on TRC"] - IC3F: [0, 15] - IC3PSC: [0, 3] - CC3S: - TI3: [1, "CC3 channel is configured as input, IC3 is mapped on TI3"] - TI4: [2, "CC3 channel is configured as input, IC3 is mapped on TI4"] - TRC: [3, "CC3 channel is configured as input, IC3 is mapped on TRC"] - DCR: - DBL: [0, 18] - DBA: [0, 31] - CCMR1_Output: - OC2PE: - Disabled: [0, "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] - Enabled: [1, "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] - CC2S: - Output: [0, "CC2 channel is configured as output"] - OC1PE: - Disabled: [0, "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] - Enabled: [1, "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] - CC1S: - Output: [0, "CC1 channel is configured as output"] - CCMR2_Output: - OC4PE: - Disabled: [0, "Preload register on CCR4 disabled. New values written to CCR4 are taken into account immediately"] - Enabled: [1, "Preload register on CCR4 enabled. Preload value is loaded into active register on each update event"] - CC4S: - Output: [0, "CC4 channel is configured as output"] - OC3PE: - Disabled: [0, "Preload register on CCR3 disabled. New values written to CCR3 are taken into account immediately"] - Enabled: [1, "Preload register on CCR3 enabled. Preload value is loaded into active register on each update event"] - CC3S: - Output: [0, "CC3 channel is configured as output"] diff --git a/peripherals/tim/tim2_common_16bit.yaml b/peripherals/tim/tim2_common_16bit.yaml deleted file mode 100644 index 2cc79fc0d..000000000 --- a/peripherals/tim/tim2_common_16bit.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# 16bit TIM2 peripheral -# Applies to Advanced-control (ac) and General-purpose (gp) timers - -CNT: - CNT: [0, 65535] -ARR: - ARR: [0, 65535] -CCR1: - CCR1: [0, 65535] -CCR2: - CCR2: [0, 65535] -CCR3: - CCR3: [0, 65535] -CCR4: - CCR4: [0, 65535] diff --git a/peripherals/tim/tim2_common_32bit.yaml b/peripherals/tim/tim2_common_32bit.yaml deleted file mode 100644 index 79ac8753e..000000000 --- a/peripherals/tim/tim2_common_32bit.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# 32bit TIM2 peripheral -# Applies to Advanced-control (ac) and General-purpose (gp) timers - -# TIM2 is present on all devices except stm32f410 and stm32f0x0. -# TIM2 is 16bit on STM32F1 family. -# TIM3 is present on all devices with TIM2 except STML4x3 family. -# TIM3 is present on stm32f0x0. - -CNT: - CNT: [0, 4294967295] -ARR: - ARR: [0, 4294967295] -CCR1: - CCR1: [0, 4294967295] -CCR2: - CCR2: [0, 4294967295] -CCR3: - CCR3: [0, 4294967295] -CCR4: - CCR4: [0, 4294967295] diff --git a/peripherals/tim/tim6.yaml b/peripherals/tim/tim6.yaml deleted file mode 100644 index 3c70474e9..000000000 --- a/peripherals/tim/tim6.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# TIM6 and TIM7 -# Present accross all STM32 except STM32F401, STM32F413 and STM32F411 devices. -# STM32F410 has only TIM6 - -"TIM6": - CR2: - MMS: - Reset: [0, "Use UG bit from TIMx_EGR register"] - Enable: [1, "Use CNT bit from TIMx_CEN register"] - Update: [2, "Use the update event"] - CNT: - CNT: [0, 65535] - ARR: - ARR: [0, 65535] - DIER: - UDE: - Disabled: [0, "Update DMA request disabled"] - Enabled: [1, "Update DMA request enabled"] diff --git a/peripherals/tim/tim_1ch_16bit.yaml b/peripherals/tim/tim_1ch_16bit.yaml deleted file mode 100644 index 7ef944187..000000000 --- a/peripherals/tim/tim_1ch_16bit.yaml +++ /dev/null @@ -1,9 +0,0 @@ -# 16bit timer peripheral with 1 channel -# Applies to Advanced-control (ac) and General-purpose (gp) timers - -CNT: - CNT: [0, 65535] -ARR: - ARR: [0, 65535] -CCR1: - CCR1: [0, 65535] diff --git a/peripherals/tim/tim_2ch_16bit.yaml b/peripherals/tim/tim_2ch_16bit.yaml deleted file mode 100644 index bac2c6f2a..000000000 --- a/peripherals/tim/tim_2ch_16bit.yaml +++ /dev/null @@ -1,11 +0,0 @@ -# 16bit timer peripheral with 1 channel -# Applies to Advanced-control (ac) and General-purpose (gp) timers - -CNT: - CNT: [0, 65535] -ARR: - ARR: [0, 65535] -CCR1: - CCR1: [0, 65535] -CCR2: - CCR2: [0, 65535] diff --git a/peripherals/tim/tim_advanced.yaml b/peripherals/tim/tim_advanced.yaml deleted file mode 100644 index fda1487ce..000000000 --- a/peripherals/tim/tim_advanced.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# Advanced-control timers TIM1,TIM8. - - -"TIM[18]": - # Common features with 16-bit General-purpose timers - _include: - - ./tim2_common_16bit.yaml - # Various features not present in other timers - BDTR: - MOE: - DisabledIdle: [0, "OC/OCN are disabled or forced idle depending on OSSI"] - Enabled: [1, "OC/OCN are enabled if CCxE/CCxNE are set"] - OSSR: - Disabled: [0, "When inactive, OC/OCN outputs are disabled"] - IdleLevel: [1, "When inactive, OC/OCN outputs are enabled with their inactive level"] - OSSI: - Disabled: [0, "When inactive, OC/OCN outputs are disabled"] - IdleLevel: [1, "When inactive, OC/OCN outputs are forced to idle level"] diff --git a/peripherals/tim/tim_basic.yaml b/peripherals/tim/tim_basic.yaml deleted file mode 100644 index 281f39211..000000000 --- a/peripherals/tim/tim_basic.yaml +++ /dev/null @@ -1,59 +0,0 @@ -# The most common features, found on Basic timers TIM6 and TIM7, -# and found on all more advanced timers. - -_include: - - tim_gp1.yaml - -"TIM*": - CR1: - _modify: - OMP: - name: OPM - ARPE: - Disabled: [0, "TIMx_APRR register is not buffered"] - Enabled: [1, "TIMx_APRR register is buffered"] - URS: - AnyEvent: [0, "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] - CounterOnly: [1, "Only counter overflow/underflow generates an update interrupt or DMA request"] - UDIS: - Enabled: [0, "Update event enabled"] - Disabled: [1, "Update event disabled"] - CEN: - Disabled: [0, "Counter disabled"] - Enabled: [1, "Counter enabled"] - DIER: - UIE: - Disabled: [0, "Update interrupt disabled"] - Enabled: [1, "Update interrupt enabled"] - SR: - UIF: - Clear: [0, "No update occurred"] - UpdatePending: [1, "Update interrupt pending."] - EGR: - UG: - Update: [1, "Re-initializes the timer counter and generates an update of the registers."] - PSC: - PSC: [0, 65535] - -# OPM is often missing on TIM10, TIM11, TIM13, TIM14. -# Annoyingly it is not always missing - include tim_opm.yaml for those devices. -"TIM?,TIM12": - CR1: - OPM: - Disabled: [0, "Counter is not stopped at update event"] - Enabled: [1, "Counter stops counting at the next update event (clearing the CEN bit)"] - -"TIM[1-58-9],TIM1?": - CCMR1_Input: - _modify: - ICPCS: - name: IC1PSC - IC1PCS: - name: IC1PSC - IC2PCS: - name: IC2PSC - CR1: - CKD: - Div1: [0, "t_DTS = t_CK_INT"] - Div2: [1, "t_DTS = 2 × t_CK_INT"] - Div4: [2, "t_DTS = 4 × t_CK_INT"] diff --git a/peripherals/tim/tim_ccm_v1.yaml b/peripherals/tim/tim_ccm_v1.yaml deleted file mode 100644 index 44f2565a5..000000000 --- a/peripherals/tim/tim_ccm_v1.yaml +++ /dev/null @@ -1,11 +0,0 @@ -"TIM[1-58]": - CCMR[12]_Output: - OC[1234]M: - Frozen: [0, "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] - ActiveOnMatch: [1, "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] - InactiveOnMatch: [2, "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] - Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] - ForceInactive: [4, "OCyREF is forced low"] - ForceActive: [5, "OCyREF is forced high"] - PwmMode1: [6, "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] - PwmMode2: [7, "Inversely to PwmMode1"] diff --git a/peripherals/tim/tim_ccm_v2.yaml b/peripherals/tim/tim_ccm_v2.yaml deleted file mode 100644 index 177ed281d..000000000 --- a/peripherals/tim/tim_ccm_v2.yaml +++ /dev/null @@ -1,17 +0,0 @@ -"TIM[1-58]": - CCMR[12]_Output: - OC[1234]M: - Frozen: [0, "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] - ActiveOnMatch: [1, "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] - InactiveOnMatch: [2, "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] - Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] - ForceInactive: [4, "OCyREF is forced low"] - ForceActive: [5, "OCyREF is forced high"] - PwmMode1: [6, "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] - PwmMode2: [7, "Inversely to PwmMode1"] - OpmMode1: [8, "Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"] - OpmMode2: [9, "Inversely to OpmMode1"] - CombinedPwmMode1: [12, "OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"] - CombinedPwmMode2: [13, "OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"] - AsymmetricPwmMode1: [14, "OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] - AsymmetricPwmMode2: [15, "OCyREF has the same behavior as in PWM mode 2. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] diff --git a/peripherals/tim/tim_gp1.yaml b/peripherals/tim/tim_gp1.yaml deleted file mode 100644 index 1d9acfdd0..000000000 --- a/peripherals/tim/tim_gp1.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# General purpose timers, TIM2-TIM5, plus advanced timers TIM1,TIM8. -# Various features not present in other GP timers TIM9-14 - -"TIM[1-58]": - CR1: - CMS: - EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] - CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] - CenterAligned2: [2, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] - CenterAligned3: [3, "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] - DIR: - Up: [0, "Counter used as upcounter"] - Down: [1, "Counter used as downcounter"] diff --git a/peripherals/tim/tim_h7.yaml b/peripherals/tim/tim_h7.yaml deleted file mode 100644 index 35bc3615b..000000000 --- a/peripherals/tim/tim_h7.yaml +++ /dev/null @@ -1,94 +0,0 @@ -# Additonal general-purpose timers on H7 (at least) -# TIM12/TIM13/TIM14/TIM15/TIM16/TIM17 are 16 bit - -# These have fewer capture/compare registers - -"TIM1[2-4]": - CNT: - CNT: [0, 65535] - ARR: - ARR: [0, 65535] - CCR1: - CCR: [0, 65535] - -"TIM1[5-7]": - CNT: - CNT: [0, 65535] - ARR: - ARR: [0, 65535] - CCR1: - CCR: [0, 65535] - -# Dual channel timers -"TIM1[25]": - CCR2: - CCR: [0, 65535] - CCMR1_Input: - IC2F: [0, 15] - CC2S: - TI2: [1, "CC2 channel is configured as input, IC2 is mapped on TI2"] - TI1: [2, "CC2 channel is configured as input, IC2 is mapped on TI1"] - TRC: [3, "CC2 channel is configured as input, IC2 is mapped on TRC"] - IC1F: - NoFilter: [0, "No filter, sampling is done at fDTS"] - FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] - FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] - FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] - FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] - FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] - FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] - FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] - FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] - FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] - FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] - FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] - FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] - FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] - FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] - FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] - CC1S: - TI1: [1, "CC1 channel is configured as input, IC1 is mapped on TI1"] - TI2: [2, "CC1 channel is configured as input, IC1 is mapped on TI2"] - TRC: [3, "CC1 channel is configured as input, IC1 is mapped on TRC"] - CCMR1_Output: - OC2PE: - Disabled: [0, "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"] - Enabled: [1, "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"] - CC2S: - Output: [0, "CC2 channel is configured as output"] - OC1PE: - Disabled: [0, "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] - Enabled: [1, "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] - CC1S: - Output: [0, "CC1 channel is configured as output"] - -# Single channel timers -"TIM1[3467]": - CCMR1_Input: - IC1F: - NoFilter: [0, "No filter, sampling is done at fDTS"] - FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] - FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] - FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] - FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] - FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] - FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] - FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] - FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] - FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] - FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] - FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] - FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] - FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] - FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] - FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] - CC1S: - TI1: [1, "CC1 channel is configured as input, IC1 is mapped on TI1"] - TI2: [2, "CC1 channel is configured as input, IC1 is mapped on TI2"] - TRC: [3, "CC1 channel is configured as input, IC1 is mapped on TRC"] - CCMR1_Output: - OC1PE: - Disabled: [0, "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] - Enabled: [1, "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] - CC1S: - Output: [0, "CC1 channel is configured as output"] diff --git a/peripherals/tim/tim_l0.yaml b/peripherals/tim/tim_l0.yaml deleted file mode 100644 index e73808e51..000000000 --- a/peripherals/tim/tim_l0.yaml +++ /dev/null @@ -1,37 +0,0 @@ -# TIM2, TIM3, TIM21 registers specific to the L0 Family (and possibly others) - -"TIM[23]": - CCMR1_Input: - IC2PSC: [0, 3] - IC1PSC: - NoPrescaler: [0, "no prescaler, capture is done each time an edge is detected on the capture input"] - Two_Events: [1, "Capture is done once every 2 events"] - Four_Events: [2, "Capture is done once every 4 events"] - Eight_Events: [3, "Capture is done once every 8 events"] - CCER: - "CC?NP": - Negative: [0, "Negative polarity"] - Positive: [1, "Positive polarity"] - "CC?P": - RisingEdge: [0, "Noninverted/rising edge"] - FallingEdge: [1, "Inverted/falling edge"] - "CC?E": - Disabled: [0, "Capture disabled"] - Enabled: [1, "Capture enabled"] - DMAR: - DMAB: [0, 65535] - OR: - TI4_RMP: - COMP2_OUT: [1, "TIM2 TI4 input connected to COMP2_OUT"] - COMP1_OUT: [2, "TIM2 TI4 input connected to COMP1_OUT"] - ETR_RMP: - COMP1_OUT: [7, "TIM2 ETR input is connected to COMP1_OUT"] - COMP2_OUT: [6, "TIM2 ETR input is connected to COMP2_OUT"] - LSE: [5, "TIM2 ETR input is connected to LSE"] - HSI: [3, "TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set"] - -"TIM21": - OR: - TI2_RMP: - GPIO: [0, "TIM2x TI2 input connected to GPIO"] - COMP2_OUT: [1, "TIM2x TI2 input connected to COMP2_OUT"] \ No newline at end of file diff --git a/peripherals/tim/tim_opm.yaml b/peripherals/tim/tim_opm.yaml deleted file mode 100644 index 18c036167..000000000 --- a/peripherals/tim/tim_opm.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# Describes OPM for all timers, where tim_basic.yaml omits it for -# TIM10,11,13,14. -"TIM10,TIM11,TIM13,TIM14": - CR1: - OPM: - Disabled: [0, "Counter is not stopped at update event"] - Enabled: [1, "Counter stops counting at the next update event (clearing the CEN bit)"] diff --git a/peripherals/usart/_v2_ABC_common.yaml b/peripherals/usart/_v2_ABC_common.yaml deleted file mode 100644 index 360e568c3..000000000 --- a/peripherals/usart/_v2_ABC_common.yaml +++ /dev/null @@ -1,149 +0,0 @@ -# Common fields between v2 A, B and C peripherals - -CR1: - DEAT: [0, 0b11111] - DEDT: [0, 0b11111] - CMIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is generated when the CMF bit is set in the ISR register"] - MME: - Disabled: [0, "Receiver in active mode permanently"] - Enabled: [1, "Receiver can switch between mute mode and active mode"] - WAKE: - Idle: [0, "Idle line"] - Address: [1, "Address mask"] - PCE: - Disabled: [0, "Parity control disabled"] - Enabled: [1, "Parity control enabled"] - PS: - Even: [0, "Even parity"] - Odd: [1, "Odd parity"] - PEIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is generated whenever PE=1 in the ISR register"] - TXEIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is generated whenever TXE=1 in the ISR register"] - TCIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is generated whenever TC=1 in the ISR register"] - RXNEIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register"] - IDLEIE: - Disabled: [0, "Interrupt is disabled"] - Enabled: [1, "Interrupt is generated whenever IDLE=1 in the ISR register"] - TE: - Disabled: [0, "Transmitter is disabled"] - Enabled: [1, "Transmitter is enabled"] - RE: - Disabled: [0, "Receiver is disabled"] - Enabled: [1, "Receiver is enabled"] - UE: - Disabled: [0, "UART is disabled"] - Enabled: [1, "UART is enabled"] -CR2: - ADD: [0, 0xFF] - MSBFIRST: - LSB: [0, "data is transmitted/received with data bit 0 first, following the start bit"] - MSB: [1, "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"] - TXINV: - Standard: [0, "TX pin signal works using the standard logic levels"] - Inverted: [1, "TX pin signal values are inverted"] - RXINV: - Standard: [0, "RX pin signal works using the standard logic levels"] - Inverted: [1, "RX pin signal values are inverted"] - DATAINV: - Positive: [0, "Logical data from the data register are send/received in positive/direct logic"] - Negative: [1, "Logical data from the data register are send/received in negative/inverse logic"] - SWAP: - Standard: [0, "TX/RX pins are used as defined in standard pinout"] - Swapped: [1, "The TX and RX pins functions are swapped"] - STOP: - Stop1: [0, "1 stop bit"] - Stop0p5: [1, "0.5 stop bit"] - Stop2: [2, "2 stop bit"] - Stop1p5: [3, "1.5 stop bit"] - CLKEN: - Disabled: [0, "CK pin disabled"] - Enabled: [1, "CK pin enabled"] - ADDM7: - Bit4: [0, "4-bit address detection"] - Bit7: [1, "7-bit address detection"] -CR3: - DEP: - High: [0, "DE signal is active high"] - Low: [1, "DE signal is active low"] - DEM: - Disabled: [0, "DE function is disabled"] - Enabled: [1, "The DE signal is output on the RTS pin"] - DDRE: - NotDisabled: [0, "DMA is not disabled in case of reception error"] - Disabled: [1, "DMA is disabled following a reception error"] - OVRDIS: - Enabled: [0, "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"] - Disabled: [1, "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"] - CTSIE: - Disabled: [0, "Interrupt is inhibited"] - Enabled: [1, "An interrupt is generated whenever CTSIF=1 in the ISR register"] - CTSE: - Disabled: [0, "CTS hardware flow control disabled"] - Enabled: [1, "CTS mode enabled, data is only transmitted when the CTS input is asserted"] - RTSE: - Disabled: [0, "RTS hardware flow control disabled"] - Enabled: [1, "RTS output enabled, data is only requested when there is space in the receive buffer"] - DMAT: - Disabled: [0, "DMA mode is disabled for transmission"] - Enabled: [1, "DMA mode is enabled for transmission"] - DMAR: - Disabled: [0, "DMA mode is disabled for reception"] - Enabled: [1, "DMA mode is enabled for reception"] - HDSEL: - NotSelected: [0, "Half duplex mode is not selected"] - Selected: [1, "Half duplex mode is selected"] - EIE: - Disabled: [0, "Interrupt is inhibited"] - Enabled: [1, "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"] -RQR: - RXFRQ: - Discard: [1, "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"] - MMRQ: - Mute: [1, "Puts the USART in mute mode and sets the RWU flag"] - SBKRQ: - Break: [1, "sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"] -ISR: - TEACK: - SBKF: - CMF: - BUSY: - CTS: - CTSIF: - TXE: - TC: - RXNE: - IDLE: - ORE: - NF: - FE: - PE: -ICR: - CMCF: - Clear: [1, "Clears the CMF flag in the ISR register"] - CTSCF: - Clear: [1, "Clears the CTSIF flag in the ISR register"] - TCCF: - Clear: [1, "Clears the TC flag in the ISR register"] - IDLECF: - Clear: [1, "Clears the IDLE flag in the ISR register"] - ORECF: - Clear: [1, "Clears the ORE flag in the ISR register"] - NCF: - Clear: [1, "Clears the NF flag in the ISR register"] - FECF: - Clear: [1, "Clears the FE flag in the ISR register"] - PECF: - Clear: [1, "Clears the PE flag in the ISR register"] -RDR: - RDR: [0, 0xFF] -TDR: - TDR: [0, 0xFF] diff --git a/peripherals/usart/_v2_AB_common.yaml b/peripherals/usart/_v2_AB_common.yaml deleted file mode 100644 index 18b814ea9..000000000 --- a/peripherals/usart/_v2_AB_common.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# Common fields between v2 A and B peripherals - -CR1: - UESM: - Disabled: [0, "USART not able to wake up the MCU from Stop mode"] - Enabled: [1, "USART able to wake up the MCU from Stop mode"] -CR3: - WUFIE: - Disabled: [0, "Interrupt is inhibited"] - Enabled: [1, "An USART interrupt is generated whenever WUF=1 in the ISR register"] - WUS: - Address: [0, "WUF active on address match"] - Start: [2, "WuF active on Start bit detection"] - RXNE: [3, "WUF active on RXNE"] -ISR: - REAK: - WUF: - RWU: -ICR: - WUCF: - Clear: [1, "Clears the WUF flag in the ISR register"] diff --git a/peripherals/usart/_v2_BC_common.yaml b/peripherals/usart/_v2_BC_common.yaml deleted file mode 100644 index bcf55e6f8..000000000 --- a/peripherals/usart/_v2_BC_common.yaml +++ /dev/null @@ -1,85 +0,0 @@ -# Common fields between v2 B and C peripherals - -CR1: - OVER8: - Oversampling16: [0, "Oversampling by 16"] - Oversampling8: [1, "Oversampling by 8"] - EOBIE: - Disabled: [0, "Interrupt is inhibited"] - Enabled: [1, "A USART interrupt is generated when the EOBF flag is set in the ISR register"] - RTOIE: - Disabled: [0, "Interrupt is inhibited"] - Enabled: [1, "An USART interrupt is generated when the RTOF bit is set in the ISR register"] -CR2: - RTOEN: - Disabled: [0, "Receiver timeout feature disabled"] - Enabled: [1, "Receiver timeout feature enabled"] - ABRMOD: - Start: [0, "Measurement of the start bit is used to detect the baud rate"] - Edge: [1, "Falling edge to falling edge measurement"] - Frame7F: [2, "0x7F frame detection"] - Frame55: [3, "0x55 frame detection"] - ABREN: - Disabled: [0, "Auto baud rate detection is disabled"] - Enabled: [1, "Auto baud rate detection is enabled"] - LINEN: - Disabled: [0, "LIN mode disabled"] - Enabled: [1, "LIN mode enabled"] - CPOL: - Low: [0, "Steady low value on CK pin outside transmission window"] - High: [1, "Steady high value on CK pin outside transmission window"] - CPHA: - First: [0, "The first clock transition is the first data capture edge"] - Second: [1, "The second clock transition is the first data capture edge"] - LBCL: - NotOutput: [0, "The clock pulse of the last data bit is not output to the CK pin"] - Output: [1, "The clock pulse of the last data bit is output to the CK pin"] - LBDIE: - Disabled: [0, "Interrupt is inhibited"] - Enabled: [1, "An interrupt is generated whenever LBDF=1 in the ISR register"] - LBDL: - Bit10: [0, "10-bit break detection"] - Bit11: [1, "11-bit break detection"] -CR3: - SCARCNT: [0, 7] - ONEBIT: - Sample3: [0, "Three sample bit method"] - Sample1: [1, "One sample bit method"] - SCEN: - Disabled: [0, "Smartcard Mode disabled"] - Enabled: [1, "Smartcard Mode enabled"] - NACK: - Disabled: [0, "NACK transmission in case of parity error is disabled"] - Enabled: [1, "NACK transmission during parity error is enabled"] - IRLP: - Normal: [0, "Normal mode"] - LowPower: [1, "Low-power mode"] - IREN: - Disabled: [0, "IrDA disabled"] - Enabled: [1, "IrDA enabled"] -BRR: - BRR: [0, 0xFFFF] -GTPR: - GT: [0, 0xFF] - PSC: [0, 0xFF] -RTOR: - BLEN: [0, 0xFF] - RTO: [0, 0xFFFFFF] -RQR: - TXFRQ: - Discard: [1, "Set the TXE flags. This allows to discard the transmit data"] - ABRRQ: - Request: [1, "resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame"] -ISR: - ABRF: - ABRE: - EOBF: - RTOF: - LBDF: -ICR: - EOBCF: - Clear: [1, "Clears the EOBF flag in the ISR register"] - LBDCF: - Clear: [1, "Clears the LBDF flag in the ISR register"] - RTOCF: - Clear: [1, "Clears the RTOF flag in the ISR register"] diff --git a/peripherals/usart/_v2_with_7bit_data.yaml b/peripherals/usart/_v2_with_7bit_data.yaml deleted file mode 100644 index a306ff8fd..000000000 --- a/peripherals/usart/_v2_with_7bit_data.yaml +++ /dev/null @@ -1,10 +0,0 @@ -# USART v2 with 7bit data - -# FIXME workaround separated M0 and M1 fields -CR1: - M0: - Bit8: [0, "1 start bit, 8 data bits, n stop bits"] - Bit9: [1, "1 start bit, 9 data bits, n stop bits"] - M1: - M0: [0, "Use M0 to set the data bits"] - Bit7: [1, "1 start bit, 7 data bits, n stop bits"] diff --git a/peripherals/usart/_v2_without_7bit_data.yaml b/peripherals/usart/_v2_without_7bit_data.yaml deleted file mode 100644 index aed10b91f..000000000 --- a/peripherals/usart/_v2_without_7bit_data.yaml +++ /dev/null @@ -1,6 +0,0 @@ -# USART v2 without 7bit data - -CR1: - M: - Bit8: [0, "1 start bit, 8 data bits, n stop bits"] - Bit9: [1, "1 start bit, 9 data bits, n stop bits"] diff --git a/peripherals/usart/lpuart_v2A.yaml b/peripherals/usart/lpuart_v2A.yaml deleted file mode 100644 index 143304c13..000000000 --- a/peripherals/usart/lpuart_v2A.yaml +++ /dev/null @@ -1,12 +0,0 @@ -# LPUART1 found on L0 and L4 families - -LPUART1: - _include: - - _v2_ABC_common.yaml - - _v2_AB_common.yaml - - _v2_with_7bit_data.yaml - - ISR: - CMCF: - BRR: - BRR: [0, 0xFFFFF] diff --git a/peripherals/usart/uart_common.yaml b/peripherals/usart/uart_common.yaml deleted file mode 100644 index 4a2b2e178..000000000 --- a/peripherals/usart/uart_common.yaml +++ /dev/null @@ -1,84 +0,0 @@ - -"UART*,USART*": - DR: - DR: [0, 0x1FF] - - BRR: - DIV_Mantissa: [0, 0xFFF] - DIV_Fraction: [0, 0xF] - - CR1: - UE: - Disabled: [0, "USART prescaler and outputs disabled"] - Enabled: [1, "USART enabled"] - M: - M8: [0, "8 data bits"] - M9: [1, "9 data bits"] - WAKE: - IdleLine: [0, "USART wakeup on idle line"] - AddressMark: [1, "USART wakeup on address mark"] - PCE: - Disabled: [0, "Parity control disabled"] - Enabled: [1, "Parity control enabled"] - PS: - Even: [0, "Even parity"] - Odd: [1, "Odd parity"] - PEIE: - Disabled: [0, "PE interrupt disabled"] - Enabled: [1, "PE interrupt enabled"] - TXEIE: - Disabled: [0, "TXE interrupt disabled"] - Enabled: [1, "TXE interrupt enabled"] - TCIE: - Disabled: [0, "TC interrupt disabled"] - Enabled: [1, "TC interrupt enabled"] - RXNEIE: - Disabled: [0, "RXNE interrupt disabled"] - Enabled: [1, "RXNE interrupt enabled"] - IDLEIE: - Disabled: [0, "IDLE interrupt disabled"] - Enabled: [1, "IDLE interrupt enabled"] - TE: - Disabled: [0, "Transmitter disabled"] - Enabled: [1, "Transmitter enabled"] - RE: - Disabled: [0, "Receiver disabled"] - Enabled: [1, "Receiver enabled"] - RWU: - Active: [0, "Receiver in active mode"] - Mute: [1, "Receiver in mute mode"] - SBK: - NoBreak: [0, "No break character is transmitted"] - Break: [1, "Break character transmitted"] - - CR2: - LINEN: - Disabled: [0, "LIN mode disabled"] - Enabled: [1, "LIN mode enabled"] - LBDIE: - Disabled: [0, "LIN break detection interrupt disabled"] - Enabled: [1, "LIN break detection interrupt enabled"] - LBDL: - LBDL10: [0, "10-bit break detection"] - LBDL11: [1, "11-bit break detection"] - ADD: [0, 0xF] - - CR3: - DMAT: - Disabled: [0, "DMA mode is disabled for transmission"] - Enabled: [1, "DMA mode is enabled for transmission"] - DMAR: - Disabled: [0, "DMA mode is disabled for reception"] - Enabled: [1, "DMA mode is enabled for reception"] - HDSEL: - FullDuplex: [0, "Half duplex mode is not selected"] - HalfDuplex: [1, "Half duplex mode is selected"] - IRLP: - Normal: [0, "Normal mode"] - LowPower: [1, "Low-power mode"] - IREN: - Disabled: [0, "IrDA disabled"] - Enabled: [1, "IrDA enabled"] - EIE: - Disabled: [0, "Error interrupt disabled"] - Enabled: [1, "Error interrupt enabled"] diff --git a/peripherals/usart/uart_sample.yaml b/peripherals/usart/uart_sample.yaml deleted file mode 100644 index 3a7733c7f..000000000 --- a/peripherals/usart/uart_sample.yaml +++ /dev/null @@ -1,9 +0,0 @@ -"UART*,USART*": - CR1: - OVER8: - Oversample16: [0, "Oversampling by 16"] - Oversample8: [1, "Oversampling by 8"] - CR3: - ONEBIT: - Sample3: [0, "Three sample bit method"] - Sample1: [1, "One sample bit method"] diff --git a/peripherals/usart/uart_uart.yaml b/peripherals/usart/uart_uart.yaml deleted file mode 100644 index 9b6fa33c9..000000000 --- a/peripherals/usart/uart_uart.yaml +++ /dev/null @@ -1,6 +0,0 @@ - -"UART*": - CR2: - STOP: - Stop1: [0, "1 stop bit"] - Stop2: [2, "2 stop bits"] diff --git a/peripherals/usart/uart_usart.yaml b/peripherals/usart/uart_usart.yaml deleted file mode 100644 index ca1e9733b..000000000 --- a/peripherals/usart/uart_usart.yaml +++ /dev/null @@ -1,34 +0,0 @@ - -"USART*": - CR2: - STOP: - Stop1: [0, "1 stop bit"] - Stop0p5: [1, "0.5 stop bits"] - Stop2: [2, "2 stop bits"] - Stop1p5: [3, "1.5 stop bits"] - CLKEN: - Disabled: [0, "CK pin disabled"] - Enabled: [1, "CK pin enabled"] - CPOL: - Low: [0, "Steady low value on CK pin outside transmission window"] - High: [1, "Steady high value on CK pin outside transmission window"] - CPHA: - First: [0, "The first clock transition is the first data capture edge"] - Second: [1, "The second clock transition is the first data capture edge"] - - CR3: - CTSIE: - Disabled: [0, "CTS interrupt disabled"] - Enabled: [1, "CTS interrupt enabled"] - CTSE: - Disabled: [0, "CTS hardware flow control disabled"] - Enabled: [1, "CTS hardware flow control enabled"] - RTSE: - Disabled: [0, "RTS hardware flow control disabled"] - Enabled: [1, "RTS hardware flow control enabled"] - SCEN: - Disabled: [0, "Smartcard mode disabled"] - Enabled: [1, "Smartcard mode enabled"] - NACK: - Disabled: [0, "NACK transmission in case of parity error is disabled"] - Enabled: [1, "NACK transmission during parity error is enabled"] diff --git a/peripherals/usart/usart_v2B.yaml b/peripherals/usart/usart_v2B.yaml deleted file mode 100644 index 85bd4bd7a..000000000 --- a/peripherals/usart/usart_v2B.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# USART v2B found on F3 family - -"USART*": - _include: - - _v2_ABC_common.yaml - - _v2_AB_common.yaml - - _v2_BC_common.yaml - - _v2_without_7bit_data.yaml diff --git a/peripherals/usart/usart_v2B1.yaml b/peripherals/usart/usart_v2B1.yaml deleted file mode 100644 index 2029dfc53..000000000 --- a/peripherals/usart/usart_v2B1.yaml +++ /dev/null @@ -1,10 +0,0 @@ -# USART v2B1 found on F0, F7, L0 and L4 family -# Same as USART v2B with 7bit data functionality - -"USART*": - _include: - - _v2_ABC_common.yaml - - _v2_AB_common.yaml - - _v2_BC_common.yaml - - _v2_with_7bit_data.yaml - diff --git a/peripherals/usart/usart_v2B2.yaml b/peripherals/usart/usart_v2B2.yaml deleted file mode 100644 index 2650f44df..000000000 --- a/peripherals/usart/usart_v2B2.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# USART v2B2 found on some L4 devices -# Same as USART v2B1 with more fields - -# Handle USART1 and USART3 common field -_include: - - usart_v2B1.yaml - -# USART3 specific fields -"USART3": - CR3: - TCBGTIE: - Disabled: [0, "Interrupt is inhibited"] - Enabled: [1, "An USART interrupt is generated whenever TCBGT=1 in the ISR register"] - UCESM: - Disabled: [0, "USART clock is disabled in STOP mode"] - Enabled: [1, "USART clock is enabled in STOP mode"] - ISR: - TCBGT: - NotCompleted: [0, "Transmission not completed"] - Completed: [1, "Transmission has completed"] diff --git a/peripherals/usart/usart_v2C.yaml b/peripherals/usart/usart_v2C.yaml deleted file mode 100644 index 4325b2938..000000000 --- a/peripherals/usart/usart_v2C.yaml +++ /dev/null @@ -1,7 +0,0 @@ -# USART v2C found on some F7 devices - -"USART*": - _include: - - _v2_ABC_common.yaml - - _v2_BC_common.yaml - - _v2_with_7bit_data.yaml diff --git a/peripherals/usb/usb.yaml b/peripherals/usb/usb.yaml deleted file mode 100644 index b7b607d1b..000000000 --- a/peripherals/usb/usb.yaml +++ /dev/null @@ -1,104 +0,0 @@ -# USB peripheral and associated SRAM - -USB: - CNTR: - CTRM: - Disabled: [0, "Correct Transfer (CTR) Interrupt disabled"] - Enabled: [1, "CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - PMAOVRM: - Disabled: [0, "PMAOVR Interrupt disabled"] - Enabled: [1, "PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - ERRM: - Disabled: [0, "ERR Interrupt disabled"] - Enabled: [1, "ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - WKUPM: - Disabled: [0, "WKUP Interrupt disabled"] - Enabled: [1, "WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - SUSPM: - Disabled: [0, "Suspend Mode Request SUSP Interrupt disabled"] - Enabled: [1, "SUSP Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - RESETM: - Disabled: [0, "RESET Interrupt disabled"] - Enabled: [1, "RESET Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - SOFM: - Disabled: [0, "SOF Interrupt disabled"] - Enabled: [1, "SOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - ESOFM: - Disabled: [0, "ESOF Interrupt disabled"] - Enabled: [1, "ESOF Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - RESUME: - Requested: [1, "Resume requested"] - FSUSP: - NoEffect: [0, "No effect"] - Suspend: [1, "Enter suspend mode. Clocks and static power dissipation in the analog transceiver are left unaffected"] - LPMODE: - Disabled: [0, "No low-power mode"] - Enabled: [1, "Enter low-power mode"] - PDWN: - Disabled: [0, "No power down"] - Enabled: [1, "Enter power down mode"] - FRES: - NoReset: [0, "Clear USB reset"] - Reset: [1, "Force a reset of the USB peripheral, exactly like a RESET signaling on the USB"] - ISTR: - CTR: - Completed: [1, "endpoint has successfully completed a transaction"] - PMAOVR: - Overrun: [1, "microcontroller has not been able to respond in time to an USB memory request"] - ERR: - Error: [1, "One of No ANSwer, Cyclic Redundancy Check, Bit Stuffing or Framing format Violation error occurred"] - WKUP: - Wakeup: [1, "activity is detected that wakes up the USB peripheral"] - SUSP: - Suspend: [1, "no traffic has been received for 3 ms, indicating a suspend mode request from the USB bus"] - RESET: - Reset: [1, "peripheral detects an active USB RESET signal at its inputs"] - SOF: - StartOfFrame: [1, "beginning of a new USB frame and it is set when a SOF packet arrives through the USB bus"] - ESOF: - ExpectedStartOfFrame: [1, "an SOF packet is expected but not received"] - DIR: - To: [0, "data transmitted by the USB peripheral to the host PC"] - From: [1, "data received by the USB peripheral from the host PC"] - EP_ID: [0, 0b1111] - FNR: - RXDP: - Received: [1, "received data plus upstream port data line"] - RXDM: - Received: [1, "received data minus upstream port data line"] - LCK: - Locked: [1, "the frame timer remains in this state until an USB reset or USB suspend event occurs"] - LSOF: [0, 0b11] - FN: [0, 0b11111111111] - DADDR: - EF: - Disabled: [0, "USB device disabled"] - Enabled: [1, "USB device enabled"] - ADD: [0, 0b1111111] - BTABLE: - BTABLE: [0, 0b1111111111111] - "EP*R": - CTR_RX: - DTOG_RX: - STAT_RX: - Disabled: [0, "all reception requests addressed to this endpoint are ignored"] - Stall: [1, "the endpoint is stalled and all reception requests result in a STALL handshake"] - Nak: [2, "the endpoint is naked and all reception requests result in a NAK handshake"] - Valid: [3, "this endpoint is enabled for reception"] - SETUP: - #"the last completed transaction is a SETUP"] - EP_TYPE: - Bulk: [0, "Bulk endpoint"] - Control: [1, "Control endpoint"] - Iso: [2, "Iso endpoint"] - Interrupt: [3, "Interrupt endpoint"] - EP_KIND: - #"DBL_BUF if EP_TYPE=Bulk or STATUS_OUT if EP_TYPE=Control"] - CTR_TX: - DTOG_TX: - STAT_TX: - Disabled: [0, "all transmission requests addressed to this endpoint are ignored"] - Stall: [1, "the endpoint is stalled and all transmission requests result in a STALL handshake"] - Nak: [2, "the endpoint is naked and all transmission requests result in a NAK handshake"] - Valid: [3, "this endpoint is enabled for transmission"] - EA: [0, 0b1111] diff --git a/peripherals/usb/usb_array.yaml b/peripherals/usb/usb_array.yaml deleted file mode 100644 index c342bad51..000000000 --- a/peripherals/usb/usb_array.yaml +++ /dev/null @@ -1,3 +0,0 @@ -USB: - _array: - "EP?R": {} diff --git a/peripherals/usb/usb_with_LPM.yaml b/peripherals/usb/usb_with_LPM.yaml deleted file mode 100644 index 44aaf8acf..000000000 --- a/peripherals/usb/usb_with_LPM.yaml +++ /dev/null @@ -1,52 +0,0 @@ -# Extends USB peripheral with Low-Power Mode - -_include: - - usb.yaml - -USB: - CNTR: - L1REQM: - Disabled: [0, "L1REQ Interrupt disabled"] - Enabled: [1, "L1REQ Interrupt enabled, an interrupt request is generated when the corresponding bit in the USB_ISTR register is set"] - L1RESUME: - Requested: [1, "LPM L1 request requested"] - ISTR: - L1REQ: - Received: [1, "LPM command to enter the L1 state is successfully received and acknowledged"] - LPMCSR: - BESL: [0, 0b1111] - REMWAKE: - LPMACK: - Nyet: [0, "the valid LPM Token will be NYET"] - Ack: [1, "the valid LPM Token will be ACK"] - LPMEN: - Disabled: [0, "enable the LPM support within the USB device"] - Enabled: [1, "no LPM transactions are handled"] - BCDR: - DPPU: - Disabled: [0, "signalize disconnect to the host when needed by the user software"] - Enabled: [1, "enable the embedded pull-up on the DP line"] - PS2DET: - Normal: [0, "Normal port detected"] - PS2: [1, "PS2 port or proprietary charger detected"] - SDET: - CDP: [0, "CDP detected"] - DCP: [1, "DCP detected"] - PDET: - NoBCD: [0, "no BCD support detected"] - BCD: [1, "BCD support detected"] - DCDET: - NotDetected: [0, "data lines contact not detected"] - Detected: [1, "data lines contact detected"] - SDEN: - Disabled: [0, "Secondary detection (SD) mode disabled"] - Enabled: [1, "Secondary detection (SD) mode enabled"] - PDEN: - Disabled: [0, "Primary detection (PD) mode disabled"] - Enabled: [1, "Primary detection (PD) mode enabled"] - DCDEN: - Disabled: [0, "Data contact detection (DCD) mode disabled"] - Enabled: [1, "Data contact detection (DCD) mode enabled"] - BCDEN: - Disabled: [0, "disable the BCD support"] - Enabled: [1, "enable the BCD support within the USB device"] diff --git a/peripherals/wwdg/wwdg.yaml b/peripherals/wwdg/wwdg.yaml deleted file mode 100644 index e0c7440e9..000000000 --- a/peripherals/wwdg/wwdg.yaml +++ /dev/null @@ -1,27 +0,0 @@ -# Window watchdog - -"WWDG,WWDG?": - CR: - WDGA: - Disabled: [0, "Watchdog disabled"] - Enabled: [1, "Watchdog enabled"] - T: [0, 127] - CFR: - _merge: - - "WDGTB*" - WDGTB: - Div1: [0, "Counter clock (PCLK1 div 4096) div 1"] - Div2: [1, "Counter clock (PCLK1 div 4096) div 2"] - Div4: [2, "Counter clock (PCLK1 div 4096) div 4"] - Div8: [3, "Counter clock (PCLK1 div 4096) div 8"] - W: [0, 127] - EWI: - _write: - Enable: [1, "interrupt occurs whenever the counter reaches the value 0x40"] - SR: - EWIF: - _read: - Pending: [1, "The EWI Interrupt Service Routine has been triggered"] - Finished: [0, "The EWI Interrupt Service Routine has been serviced"] - _write: - Finished: [0, "The EWI Interrupt Service Routine has been serviced"] diff --git a/requirements.txt b/requirements.txt deleted file mode 100644 index 5e761b0ed..000000000 --- a/requirements.txt +++ /dev/null @@ -1 +0,0 @@ -svdtools~=0.1.0 diff --git a/rustfmt.toml b/rustfmt.toml deleted file mode 100644 index e8bb3d9a0..000000000 --- a/rustfmt.toml +++ /dev/null @@ -1 +0,0 @@ -normalize_doc_attributes = true diff --git a/scripts/comparesvd.py b/scripts/comparesvd.py index eddda3944..9b1168a55 100644 --- a/scripts/comparesvd.py +++ b/scripts/comparesvd.py @@ -9,11 +9,11 @@ def getregs(s): regs = {} for peripheral in s.iter('peripheral'): pname = peripheral.find('name').text - base = int(peripheral.find('baseAddress').text, 16) + base = int(peripheral.find('baseAddress').text, 0) for register in peripheral.iter('register'): rname = register.find('name').text name = pname + "_" + rname - offset = int(register.find('addressOffset').text, 16) + offset = int(register.find('addressOffset').text, 0) regs[name] = hex(base+offset) return regs diff --git a/scripts/htmlcomparesvd.py b/scripts/htmlcomparesvd.py index a1fbc2524..d070f4aad 100644 --- a/scripts/htmlcomparesvd.py +++ b/scripts/htmlcomparesvd.py @@ -1,4 +1,4 @@ -import sys +import argparse import os.path import xml.etree.ElementTree as ET @@ -24,15 +24,15 @@ def parse(svdfile): for ptag in iter_peripherals(tree): registers = {} pname = ptag.find('name').text - pbase = int(ptag.find('baseAddress').text, 16) + pbase = int(ptag.find('baseAddress').text, 0) for rtag in iter_registers(ptag): fields = {} rname = rtag.find('name').text - roffset = int(rtag.find('addressOffset').text, 16) + roffset = int(rtag.find('addressOffset').text, 0) for ftag in iter_fields(rtag): fname = ftag.find('name').text - foffset = int(ftag.find('bitOffset').text) - fwidth = int(ftag.find('bitWidth').text) + foffset = int(ftag.find('bitOffset').text, 0) + fwidth = int(ftag.find('bitWidth').text, 0) fields[fname] = {"name": fname, "offset": foffset, "width": fwidth} registers[rname] = {"name": rname, "offset": roffset, @@ -208,10 +208,15 @@ def html_tables(parts): def main(): - parts = [parse(svdfile) for svdfile in sys.argv[1:]] + parser = argparse.ArgumentParser() + parser.add_argument("htmldir", help="Path to write HTML files to") + parser.add_argument("svdfiles", help="Path to patched SVD files", nargs="*") + args = parser.parse_args() + + parts = [parse(svdfile) for svdfile in args.svdfiles] files = html_tables(parts) for fn in files: - with open(os.path.join("html", fn), "w") as f: + with open(os.path.join(args.htmldir, fn), "w") as f: f.write(files[fn]) if __name__ == "__main__": diff --git a/scripts/htmlcomparesvdall.sh b/scripts/htmlcomparesvdall.sh old mode 100644 new mode 100755 index 93f782b30..4329502e6 --- a/scripts/htmlcomparesvdall.sh +++ b/scripts/htmlcomparesvdall.sh @@ -1,79 +1,70 @@ #!/usr/bin/env bash set -euxo pipefail -mkdir html +svdtools htmlcompare html/stm32f svd/stm32f{0x8,103,107,217,303,3x4,469,779}.svd.patched +sed -i 's##

Only a representative member of each family included; click to view entire family

#' html/stm32f/index.html +sed -i 's#STM32F0x8#STM32F0x8#' html/stm32f/index.html +sed -i 's#STM32F103#STM32F103#' html/stm32f/index.html +sed -i 's#STM32F107#STM32F107#' html/stm32f/index.html +sed -i 's#STM32F217#STM32F217#' html/stm32f/index.html +sed -i 's#STM32F303#STM32F303#' html/stm32f/index.html +sed -i 's#STM32F3x4#STM32F3x4#' html/stm32f/index.html +sed -i 's#STM32F469#STM32F469#' html/stm32f/index.html +sed -i 's#STM32F7x9#STM32F7x9#' html/stm32f/index.html -mkdir html/stm32f -python3 scripts/htmlcomparesvd.py svd/stm32f{0x8,103,107,217,303,3x8,469,7x2,7x9}.svd.patched -sed -i 's#
#

Only a representative member of each family included; click to view entire family

#' html/index.html -sed -i 's#stm32f0x8#STM32F0x8#' html/index.html -sed -i 's#stm32f103#STM32F103#' html/index.html -sed -i 's#stm32f107#STM32F107#' html/index.html -sed -i 's#stm32f217#STM32F217#' html/index.html -sed -i 's#stm32f303#STM32F303#' html/index.html -sed -i 's#stm32f3x8#STM32F3x8#' html/index.html -sed -i 's#stm32f469#STM32F469#' html/index.html -sed -i 's#stm32f7x2#STM32F7x2#' html/index.html -sed -i 's#stm32f7x9#STM32F7x9#' html/index.html -mv html/*.html html/stm32f +svdtools htmlcompare html/stm32f/stm32f0 svd/stm32f0*.svd.patched +svdtools htmlcompare html/stm32f/stm32f1 svd/stm32f1*.svd.patched +svdtools htmlcompare html/stm32f/stm32f2 svd/stm32f2*.svd.patched +svdtools htmlcompare html/stm32f/stm32f3 svd/stm32f3*.svd.patched +svdtools htmlcompare html/stm32f/stm32f4 svd/stm32f4*.svd.patched +svdtools htmlcompare html/stm32f/stm32f7 svd/stm32f7{32,33,30,45,50,56,65,77,79}.svd.patched -mkdir html/stm32f/stm32f0 -python3 scripts/htmlcomparesvd.py svd/stm32f0*.svd.patched -mv html/*.html html/stm32f/stm32f0 +svdtools htmlcompare html/stm32l svd/stm32l{0x3,162,4x6}.svd.patched +sed -i 's#
#

Only a representative member of each family included; click to view entire family<\/p>

#' html/stm32l/index.html +sed -i 's#STM32L0x3#STM32L0x3#' html/stm32l/index.html +sed -i 's#STM32L162#STM32L162#' html/stm32l/index.html +sed -i 's#STM32L4x6#STM32L4x6#' html/stm32l/index.html -mkdir html/stm32f/stm32f1 -python3 scripts/htmlcomparesvd.py svd/stm32f1*.svd.patched -mv html/*.html html/stm32f/stm32f1 +svdtools htmlcompare html/stm32l/stm32l0 svd/stm32l0*.svd.patched +svdtools htmlcompare html/stm32l/stm32l1 svd/stm32l1*.svd.patched +svdtools htmlcompare html/stm32l/stm32l4 svd/stm32l4*.svd.patched -mkdir html/stm32f/stm32f2 -python3 scripts/htmlcomparesvd.py svd/stm32f2*.svd.patched -mv html/*.html html/stm32f/stm32f2 +svdtools htmlcompare html/stm32h svd/stm32h753.svd.patched +sed -i 's#
#

Only a representative member of each family included; click to view entire family

#' html/stm32h/index.html +sed -i 's#STM32H753#STM32H753#' html/stm32h/index.html -mkdir html/stm32f/stm32f3 -python3 scripts/htmlcomparesvd.py svd/stm32f3*.svd.patched -mv html/*.html html/stm32f/stm32f3 +svdtools htmlcompare html/stm32h/stm32h7 svd/stm32h7*.svd.patched -mkdir html/stm32f/stm32f4 -python3 scripts/htmlcomparesvd.py svd/stm32f4*.svd.patched -mv html/*.html html/stm32f/stm32f4 - -mkdir html/stm32f/stm32f7 -python3 scripts/htmlcomparesvd.py svd/stm32f7*.svd.patched -mv html/*.html html/stm32f/stm32f7 - -mkdir html/stm32l -python3 scripts/htmlcomparesvd.py svd/stm32l{0x3,162,4x6}.svd.patched -sed -i 's#
#

Only a representative member of each family included; click to view entire family<\/p>

#' html/index.html -sed -i 's#stm32l0x3#STM32L0x3#' html/index.html -sed -i 's#stm32l162#STM32L162#' html/index.html -sed -i 's#stm32l4x6#STM32L4x6#' html/index.html -mv html/*.html html/stm32l - -mkdir html/stm32l/stm32l0 -python3 scripts/htmlcomparesvd.py svd/stm32l0*.svd.patched -mv html/*.html html/stm32l/stm32l0 - -mkdir html/stm32l/stm32l1 -python3 scripts/htmlcomparesvd.py svd/stm32l1*.svd.patched -mv html/*.html html/stm32l/stm32l1 - -mkdir html/stm32l/stm32l4 -python3 scripts/htmlcomparesvd.py svd/stm32l4*.svd.patched -mv html/*.html html/stm32l/stm32l4 - -mkdir html/stm32h -python3 scripts/htmlcomparesvd.py svd/stm32h7x3.svd.patched -sed -i 's#
#

Only a representative member of each family included; click to view entire family

#' html/index.html -sed -i 's#stm32h7x3#STM32H7x3#' html/index.html -mv html/*.html html/stm32h +cat > html/comparisons.html < + + + +stm32-rs Peripheral Comparisons + + + -mkdir html/stm32h/stm32h7 -python3 scripts/htmlcomparesvd.py svd/stm32h7x3.svd.patched -mv html/*.html html/stm32h/stm32h7 + + -cat > html/index.html < -STM32F
-STM32L
-STM32H
+

Device families

+ + + EOF diff --git a/scripts/makecrates.py b/scripts/makecrates.py index 74c082403..1f8566c07 100644 --- a/scripts/makecrates.py +++ b/scripts/makecrates.py @@ -16,34 +16,44 @@ import re import yaml -VERSION = "0.12.0" -SVD2RUST_VERSION = "0.17.0" +VERSION = { + "default": "0.16.0", +} +SVD2RUST_VERSION = "0.36.1" CRATE_DOC_FEATURES = { - "stm32f0": ["rt", "stm32f0x0", "stm32f0x1", "stm32f0x2", "stm32f0x8"], - "stm32f1": ["rt", "stm32f100", "stm32f101", "stm32f102", "stm32f103", - "stm32f107"], - "stm32f2": ["rt", "stm32f215", "stm32f217"], - "stm32f3": ["rt", "stm32f303", "stm32f373", "stm32f3x8"], - "stm32f4": ["rt", "stm32f401", "stm32f407", "stm32f413", "stm32f469"], - "stm32f7": ["rt", "stm32f7x3", "stm32f7x9"], - "stm32h7": ["rt", "stm32h743", "stm32h743v", "stm32h747cm7"], - "stm32l0": ["rt", "stm32l0x1", "stm32l0x2", "stm32l0x3"], - "stm32l1": ["rt", "stm32l100", "stm32l151", "stm32l162"], - "stm32l4": ["rt", "stm32l4x1", "stm32l4x5"], - "stm32l5": ["rt", "stm32l562"], - "stm32g0": ["rt", "stm32g07x", "stm32g030", "stm32g031", "stm32g041", "stm32g081"], - "stm32g4": ["rt", "stm32g431", "stm32g441", "stm32g474", "stm32g484"], - "stm32mp1": ["rt", "stm32mp157"] + "stm32c0": ["atomics", "critical-section", "defmt", "rt", "stm32c011", "stm32c031", "stm32c071"], + "stm32f0": ["atomics", "critical-section", "defmt", "rt", "stm32f0x0", "stm32f0x1", "stm32f0x2", "stm32f0x8"], + "stm32f1": ["atomics", "critical-section", "defmt", "rt", "stm32f100", "stm32f101", "stm32f102", "stm32f103", "stm32f107"], + "stm32f2": ["atomics", "critical-section", "defmt", "rt", "stm32f215", "stm32f217"], + "stm32f3": ["atomics", "critical-section", "defmt", "rt", "stm32f302", "stm32f303", "stm32f373"], + "stm32f4": ["atomics", "critical-section", "defmt", "rt", "stm32f401", "stm32f407", "stm32f413", "stm32f469"], + "stm32f7": ["atomics", "critical-section", "defmt", "rt", "stm32f733", "stm32f779"], + "stm32h5": ["atomics", "critical-section", "defmt", "rt", "stm32h503", "stm32h533", "stm32h562", "stm32h573"], + "stm32h7": ["atomics", "critical-section", "defmt", "rt", "stm32h735", "stm32h750", "stm32h753", "stm32h753v", "stm32h757cm7", "stm32h7b3"], + "stm32l0": ["atomics", "critical-section", "defmt", "rt", "stm32l0x0", "stm32l0x1", "stm32l0x2", "stm32l0x3"], + "stm32l1": ["atomics", "critical-section", "defmt", "rt", "stm32l100", "stm32l151", "stm32l162"], + "stm32l4": ["atomics", "critical-section", "defmt", "rt", "stm32l4x1", "stm32l4x5"], + "stm32l5": ["atomics", "critical-section", "defmt", "rt", "stm32l562"], + "stm32g0": ["atomics", "critical-section", "defmt", "rt", "stm32g030", "stm32g070", "stm32g0b0", "stm32g041", "stm32g081", "stm32g0c1"], + "stm32g4": ["atomics", "critical-section", "defmt", "rt", "stm32g431", "stm32g441", "stm32g474", "stm32g484"], + "stm32mp1": ["atomics", "critical-section", "defmt", "rt", "stm32mp157"], + "stm32n6": ["atomics", "critical-section", "defmt", "rt", "stm32n645", "stm32n655", "stm32n647", "stm32n657"], + "stm32u0": ["atomics", "critical-section", "defmt", "rt", "stm32u031", "stm32u083"], + "stm32u5": ["atomics", "critical-section", "defmt", "rt", "stm32u535", "stm32u545", "stm32u575", "stm32u585", "stm32u595", "stm32u5a5", "stm32u599", "stm32u5a9"], + "stm32wl": ["atomics", "critical-section", "defmt", "rt", "stm32wle5", "stm32wl5x_cm4"], + "stm32wb": ["atomics", "critical-section", "defmt", "rt", "stm32wb55"] } CRATE_DOC_TARGETS = { + "stm32c0": "thumbv6m-none-eabi", "stm32f0": "thumbv6m-none-eabi", "stm32f1": "thumbv7m-none-eabi", "stm32f2": "thumbv7m-none-eabi", "stm32f3": "thumbv7em-none-eabihf", "stm32f4": "thumbv7em-none-eabihf", "stm32f7": "thumbv7em-none-eabihf", + "stm32h5": "thumbv8m.main-none-eabihf", "stm32h7": "thumbv7em-none-eabihf", "stm32l0": "thumbv6m-none-eabi", "stm32l1": "thumbv7m-none-eabi", @@ -52,11 +62,16 @@ "stm32g0": "thumbv6m-none-eabi", "stm32g4": "thumbv7em-none-eabihf", "stm32mp1": "thumbv7em-none-eabihf", + "stm32n6": "thumbv8m.main-none-eabi", + "stm32u0": "thumbv6m-none-eabi", + "stm32u5": "thumbv8m.main-none-eabi", + "stm32wl": "thumbv7em-none-eabi", + "stm32wb": "thumbv7em-none-eabihf" } CARGO_TOML_TPL = """\ [package] -edition = "2018" +edition = "2021" name = "{crate}" version = "{version}" authors = ["Adam Greig ", "stm32-rs Contributors"] @@ -66,15 +81,15 @@ keywords = ["stm32", "svd2rust", "no_std", "embedded"] categories = ["embedded", "no-std"] license = "MIT/Apache-2.0" +rust-version = "1.65" [dependencies] -bare-metal = "0.2.4" -vcell = "0.1.0" -cortex-m = ">=0.5.8,<0.7" - -[dependencies.cortex-m-rt] -optional = true -version = "0.6.10" +critical-section = {{ version = "1.0", optional = true }} +cortex-m = "0.7.7" +cortex-m-rt = {{ version = "0.7.5", optional = true }} +defmt = {{ version = "1", optional = true }} +vcell = "0.1.3" +portable-atomic = {{ version = "1", default-features = false, optional = true }} [package.metadata.docs.rs] features = {docs_features} @@ -82,8 +97,9 @@ targets = [] [features] -default = [] +default = ["critical-section", "rt"] rt = ["cortex-m-rt/device"] +atomics = ["dep:portable-atomic"] {features} """ @@ -100,13 +116,14 @@ //! //! This crate supports all {family} devices; for the complete list please //! see: -//! [{crate}](https://github.com/stm32-rs/stm32-rs/tree/master/{crate}) +//! [{crate}](https://crates.io/crates/{crate}) //! //! Due to doc build limitations, not all devices may be shown on docs.rs; //! a representative few have been selected instead. For a complete list of -//! available registers and fields see: [stm32-rs Device Coverage](https://stm32.agg.io/rs) +//! available registers and fields see: [stm32-rs Device Coverage](https://stm32-rs.github.io/stm32-rs/) #![allow(non_camel_case_types)] +#![allow(non_snake_case)] #![no_std] mod generic; @@ -123,7 +140,7 @@ Refer to the [documentation] for full details. -[svd2rust]: https://github.com/japaric/svd2rust +[svd2rust]: https://github.com/rust-embedded/svd2rust [main repo]: https://github.com/stm32-rs/stm32-rs [documentation]: https://docs.rs/{crate}/latest/{crate}/ @@ -134,10 +151,11 @@ ```toml [dependencies.{crate}] version = "{version}" -features = ["{device}", "rt"] +features = ["{device}"] ``` -The `rt` feature is optional and brings in support for `cortex-m-rt`. +The `rt` feature is enabled by default and brings in support for `cortex-m-rt`. +To disable, specify `default-features = false` in `Cargo.toml`. In your code: @@ -168,9 +186,20 @@ if env::var_os("CARGO_FEATURE_RT").is_some() {{ let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); println!("cargo:rustc-link-search={{}}", out.display()); - let device_file = {device_clauses}; - fs::copy(device_file, out.join("device.x")).unwrap(); - println!("cargo:rerun-if-changed={{}}", device_file); + let devices = [{devices}]; + let mut device_file = None; + for &d in &devices {{ + if env::var_os(&format!("CARGO_FEATURE_{{}}", d.to_uppercase())).is_some() {{ + device_file = Some(format!("src/{{d}}/device.x")); + break; + }} + }} + if let Some(device_file) = device_file {{ + fs::copy(&device_file, out.join("device.x")).unwrap(); + println!("cargo:rerun-if-changed={{device_file}}"); + }} else {{ + panic!("No device features selected. Avaliable device features are: {{devices:?}}"); + }} }} println!("cargo:rerun-if-changed=build.rs"); }} @@ -189,8 +218,11 @@ def read_device_table(): def make_device_rows(table, family): rows = [] for device, dt in table[family].items(): - links = "[{}]({}), [st.com]({})".format( - dt['rm'], dt['rm_url'], dt['url']) + if 'rm' in dt: + links = "[{}]({}), [st.com]({})".format( + dt['rm'], dt['rm_url'], dt['url']) + else: + links = "[st.com]({})".format(dt['url']) members = ", ".join(m for m in dt['members']) rows.append("| {} | {} | {} |".format(device, members, links)) return "\n".join(sorted(rows)) @@ -200,25 +232,25 @@ def make_features(devices): return "\n".join("{} = []".format(d) for d in sorted(devices)) +def make_feature_list(devices): + return ", ".join("\"{}\"".format(d) for d in sorted(devices)) + + def make_mods(devices): return "\n".join('#[cfg(feature = "{0}")]\npub mod {0};\n'.format(d) for d in sorted(devices)) -def make_device_clauses(devices): - return " else ".join("""\ - if env::var_os("CARGO_FEATURE_{}").is_some() {{ - "src/{}/device.x" - }}""".strip().format(d.upper(), d) for d in sorted(devices)) + \ - " else { panic!(\"No device features selected\"); }" - - def main(devices_path, yes, families): devices = {} for path in glob.glob(os.path.join(devices_path, "*.yaml")): yamlfile = os.path.basename(path) family = re.match(r'stm32[a-z]+[0-9]', yamlfile)[0] + if family.startswith('stm32wl'): + family = 'stm32wl' + if family.startswith('stm32wb'): + family = 'stm32wb' device = os.path.splitext(yamlfile)[0].lower() if len(families) == 0 or family in families: if family not in devices: @@ -236,21 +268,26 @@ def main(devices_path, yes, families): for family in devices: devices[family] = sorted(devices[family]) crate = family.lower() + crate_name = crate; features = make_features(devices[family]) - clauses = make_device_clauses(devices[family]) + feature_list = make_feature_list(devices[family]) mods = make_mods(devices[family]) ufamily = family.upper() + if crate in VERSION: + version = VERSION[crate] + else: + version = VERSION["default"] cargo_toml = CARGO_TOML_TPL.format( - family=ufamily, crate=crate, version=VERSION, features=features, + family=ufamily, crate=crate_name, version=version, features=features, docs_features=str(CRATE_DOC_FEATURES[crate]), doc_target=CRATE_DOC_TARGETS[crate]) readme = README_TPL.format( - family=ufamily, crate=crate, device=devices[family][0], - version=VERSION, svd2rust_version=SVD2RUST_VERSION, + family=ufamily, crate=crate_name, device=devices[family][0], + version=version, svd2rust_version=SVD2RUST_VERSION, devices=make_device_rows(table, family)) - lib_rs = SRC_LIB_RS_TPL.format(family=ufamily, mods=mods, crate=crate, + lib_rs = SRC_LIB_RS_TPL.format(family=ufamily, mods=mods, crate=crate_name, svd2rust_version=SVD2RUST_VERSION) - build_rs = BUILD_TPL.format(device_clauses=clauses) + build_rs = BUILD_TPL.format(devices=feature_list) os.makedirs(os.path.join(crate, "src"), exist_ok=True) with open(os.path.join(crate, "Cargo.toml"), "w") as f: diff --git a/scripts/makehtml.index.template.html b/scripts/makehtml.index.template.html index b1be0ba1d..d712b9df5 100644 --- a/scripts/makehtml.index.template.html +++ b/scripts/makehtml.index.template.html @@ -13,7 +13,12 @@ diff --git a/scripts/makehtml.py b/scripts/makehtml.py index cf92d6c5e..4cc5d7106 100644 --- a/scripts/makehtml.py +++ b/scripts/makehtml.py @@ -8,6 +8,7 @@ """ import shutil +import copy import sys import os.path import argparse @@ -38,6 +39,218 @@ def short_access(accs): }.get(accs, "N/A") +def iter_clusters(ptag): + registers = ptag.find("registers") + if registers is None: + return [] + else: + return registers.findall("cluster") + + +def iter_registers(ptag): + registers = ptag.find("registers") + if registers is None: + return [] + else: + return registers.findall("register") + + +def iter_fields(rtag): + fields = rtag.find("fields") + if fields is None: + return [] + else: + return fields.findall("field") + + +def get_string(node, tag, default=None): + text = node.findtext(tag, default=default) + if text == default: + return text + return " ".join(text.split()) + + +def get_int(node, tag, default=None): + text = get_string(node, tag, default=default) + if text == default: + return text + text = text.lower().strip() + if text == "true": + return 1 + elif text == "false": + return 0 + elif text[:2] == "0x": + return int(text[2:], 16) + elif text[:2] == "0b": + return int(text[2:], 2) + else: + return int(text, 10) + + +def expand_dim(node, field=False): + """ + Given a node (a cluster, a register or a field) which may have a `dim` child, + returns an expanded list of all such nodes with '%s' in the name replaced + by the appropriate index. If there is no `dim` child, a list containing + just the original node is returned. + """ + dim = node.findtext("dim") + if dim is None: + return [node] + inc = get_int(node, "dimIncrement") + idxs = get_string(node, "dimIndex") + if idxs is None: + idxs = list(range(int(dim, 0))) + else: + if len(idxs) == 1: + pass + elif "," in idxs: + idxs = idxs.split(",") + elif "-" in idxs: + li, ri = idxs.split("-") + idxs = list(range(int(li), int(ri) + 1)) + else: + raise ValueError(f"Unknown dimIndex: '{idxs}'") + nodes = [] + for cnt, idx in enumerate(idxs): + name = get_string(node, "name").replace("%s", f"[{idx}]") + description = get_string(node, "description").replace("%s", str(idx)) + dim_node = copy.deepcopy(node) + dim_node.find("name").text = name + dim_node.find("description").text = description + if field: + offset = get_int(dim_node, "bitOffset") + cnt * inc + dim_node.find("bitOffset").text = f"{offset}" + else: + addr = get_int(dim_node, "addressOffset") + cnt * inc + dim_node.find("addressOffset").text = f"0x{addr:08x}" + dim_node.attrib["dim_index"] = str(idx) + nodes.append(dim_node) + return nodes + + +def expand_cluster(node): + """ + Given a cluster, returns a list of all registers inside the cluster, + with their names updated to include the cluster index and their address + offsets updated to include the cluster address offset. + The returned register nodes are as though they were never in a cluster. + """ + if node.attrib.get("dim_index") is None: + raise ValueError("Can't process cluster '{}' without dim_index".format( + get_string(node, "name") + )) + cluster_idx = node.attrib["dim_index"] + cluster_addr = get_int(node, "addressOffset") + nodes = [] + for rtag in node.findall("register"): + addr = cluster_addr + get_int(rtag, "addressOffset") + name = f"{get_string(rtag, 'name')} [{cluster_idx}]" + new_rtag = copy.deepcopy(rtag) + new_rtag.find("addressOffset").text = f"0x{addr:08x}" + new_rtag.find("name").text = name + nodes.append(new_rtag) + return nodes + + +def parse_register(rtag): + fields = {} + register_fields_total = 0 + register_fields_documented = 0 + rname = get_string(rtag, 'name') + rdesc = get_string(rtag, 'description') + rrstv = get_string(rtag, 'resetValue') + raccs = get_string(rtag, 'access') or "Unspecified" + roffset = get_int(rtag, 'addressOffset') + for ftag in iter_fields(rtag): + register_fields_total += 1 + fname = get_string(ftag, 'name') + fdesc = get_string(ftag, 'description') + # Some svd files will specify a bitRange rather than + # bitOffset and bitWidth + frange = get_string(ftag, 'bitRange') + if frange: + parts = frange[1:-1].split(':') + end = int(parts[0], 0) + start = int(parts[1], 0) + foffset = start + fwidth = end - start + 1 + else: + foffset = get_int(ftag, 'bitOffset') + fwidth = get_int(ftag, 'bitWidth') + faccs = get_string(ftag, 'access') or raccs + enum = ftag.find('enumeratedValues') + wc = ftag.find('writeConstraint') + doc = False + if enum is not None or wc is not None or faccs == "read-only": + register_fields_documented += 1 + if enum is not None: + doc = "Allowed values:
" + if 'derivedFrom' in enum.attrib: + dfname = enum.attrib['derivedFrom'] + dffrom = rtag.findall( + ".//enumeratedValues/[name='" + dfname + "']") + if dffrom: + enum = dffrom[0] + for value in enum.iter('enumeratedValue'): + doc += "" + doc += get_string(value, 'value') + doc += ": " + doc += get_string(value, 'name') + doc += ": " + doc += get_string(value, 'description') + doc += "
" + elif wc is not None: + wcrange = wc.find('range') + if wcrange is not None: + mn = hex(get_int(wcrange, 'minimum')) + mx = hex(get_int(wcrange, 'maximum')) + doc = "Allowed values: {}-{}".format(mn, mx) + fields[foffset] = {"name": fname, "offset": foffset, + "width": fwidth, "description": fdesc, + "doc": doc, "access": faccs} + table = [[{"name": "", "width": 1, "doc": False} + for _ in range(16)] for _ in range(2)] + for foffset in reversed(sorted(fields.keys())): + fwidth = fields[foffset]['width'] + fname = fields[foffset]['name'] + fdoc = bool(fields[foffset]['doc']) + faccs = fields[foffset]['access'] + for idx in range(foffset, foffset + fwidth): + trowidx = (31 - idx)//16 + tcolidx = 15 - (idx % 16) + tcell = table[trowidx][tcolidx] + tcell['name'] = fname + tcell['doc'] = fdoc + tcell['access'] = short_access(faccs) + tcell['separated'] = foffset < 16 and foffset + fwidth > 16 + for trow in table: + idx = 0 + while idx < len(trow)-1: + if trow[idx]['name'] == trow[idx+1]['name']: + trow[idx]['width'] += 1 + del trow[idx+1] + continue + idx += 1 + table = [ + {"headers": reversed(list(range(16, 32))), "fields": table[0]}, + {"headers": reversed(list(range(0, 16))), "fields": table[1]}] + # Bodge to prevent /0 when there are no fields in a register + if register_fields_total == 0: + register_fields_total = 1 + return (roffset, rname), { + "name": rname, + "offset": hex(roffset), + "description": rdesc, + "resetValue": rrstv, + "access": raccs, + "fields": fields, + "table": table, + "fields_total": register_fields_total, + "fields_documented": register_fields_documented + } + + def parse_device(svdfile): tree = ET.parse(svdfile) temp = os.stat(svdfile).st_mtime @@ -49,8 +262,8 @@ def parse_device(svdfile): registers = {} peripheral_fields_total = 0 peripheral_fields_documented = 0 - pname = ptag.findtext('name') - pbase = ptag.findtext('baseAddress') + pname = get_string(ptag, 'name') + pbase = hex(get_int(ptag, 'baseAddress')) if 'derivedFrom' in ptag.attrib: dfname = ptag.attrib['derivedFrom'] dffrom = tree.findall(".//peripheral/[name='" + dfname + "']") @@ -60,102 +273,20 @@ def parse_device(svdfile): print("Can't find derivedFrom={} for {}" .format(dfname, pname)) continue - pdesc = ptag.findtext('description') - for rtag in ptag.iter('register'): - fields = {} - register_fields_total = 0 - register_fields_documented = 0 - rname = rtag.findtext('name') - rdesc = rtag.findtext('description') - rrstv = rtag.findtext('resetValue') - raccs = rtag.findtext('access') or "Unspecified" - roffset = int(rtag.findtext('addressOffset'), 16) - for ftag in rtag.iter('field'): - register_fields_total += 1 - fname = ftag.findtext('name') - fdesc = ftag.findtext('description') - # Some svd files will specify a bitRange rather than - # bitOffset and bitWidth - frange = ftag.findtext('bitRange') - if frange: - parts = frange[1:-1].split(':') - end = int(parts[0]) - start = int(parts[1]) - foffset = start - fwidth = end - start + 1 - else: - foffset = int(ftag.findtext('bitOffset')) - fwidth = int(ftag.findtext('bitWidth')) - faccs = ftag.findtext('access') or raccs - enum = ftag.find('enumeratedValues') - wc = ftag.find('writeConstraint') - doc = False - if enum is not None or wc is not None or faccs == "read-only": - register_fields_documented += 1 - if enum is not None: - doc = "Allowed values:
" - if 'derivedFrom' in enum.attrib: - dfname = enum.attrib['derivedFrom'] - dffrom = rtag.findall( - ".//enumeratedValues/[name='" + dfname + "']") - if dffrom: - enum = dffrom[0] - for value in enum.iter('enumeratedValue'): - doc += "" - doc += value.findtext('value') - doc += ": " - doc += value.findtext('name') - doc += ": " - doc += value.findtext('description') - doc += "
" - elif wc is not None: - wcrange = wc.find('range') - if wcrange is not None: - mn = wcrange.findtext('minimum') - mx = wcrange.findtext('maximum') - doc = "Allowed values: {}-{}".format(mn, mx) - fields[foffset] = {"name": fname, "offset": foffset, - "width": fwidth, "description": fdesc, - "doc": doc, "access": faccs} - table = [[{"name": "", "width": 1, "doc": False} - for _ in range(16)] for _ in range(2)] - for foffset in reversed(sorted(fields.keys())): - fwidth = fields[foffset]['width'] - fname = fields[foffset]['name'] - fdoc = bool(fields[foffset]['doc']) - faccs = fields[foffset]['access'] - for idx in range(foffset, foffset + fwidth): - trowidx = (31 - idx)//16 - tcolidx = 15 - (idx % 16) - tcell = table[trowidx][tcolidx] - tcell['name'] = fname - tcell['doc'] = fdoc - tcell['access'] = short_access(faccs) - tcell['separated'] = foffset < 16 and foffset + fwidth > 16 - for trow in table: - idx = 0 - while idx < len(trow)-1: - if trow[idx]['name'] == trow[idx+1]['name']: - trow[idx]['width'] += 1 - del trow[idx+1] - continue - idx += 1 - table = [ - {"headers": reversed(list(range(16, 32))), "fields": table[0]}, - {"headers": reversed(list(range(0, 16))), "fields": table[1]}] - # Bodge to prevent /0 when there are no fields in a register - if register_fields_total == 0: - register_fields_total = 1 - registers[roffset] = {"name": rname, - "offset": "0x{:X}".format(roffset), - "description": rdesc, "resetValue": rrstv, - "access": raccs, "fields": fields, - "table": table, - "fields_total": register_fields_total, - "fields_documented": - register_fields_documented} - peripheral_fields_total += register_fields_total - peripheral_fields_documented += register_fields_documented + pdesc = get_string(ptag, 'description') + for ctag in iter_clusters(ptag): + for ctag in expand_dim(ctag): + for rtag in expand_cluster(ctag): + key, register = parse_register(rtag) + registers[key] = register + peripheral_fields_total += register['fields_total'] + peripheral_fields_documented += register['fields_documented'] + for rtag in iter_registers(ptag): + for rtag in expand_dim(rtag): + key, register = parse_register(rtag) + registers[key] = register + peripheral_fields_total += register['fields_total'] + peripheral_fields_documented += register['fields_documented'] peripherals[pname] = {"name": pname, "base": pbase, "description": pdesc, "registers": registers, "fields_total": peripheral_fields_total, @@ -175,16 +306,17 @@ def process_svd(svdfile): return device -def generate_if_newer(device): +def generate_if_newer(arg): + device, htmldir = arg pagename = "{}.html".format(device["name"]) - filename = os.path.join(args.htmldir, pagename) + filename = os.path.join(htmldir, pagename) isfile = os.path.isfile(filename) if not isfile or os.stat(filename).st_mtime < device['last-modified']: page = generate_device_page(device) print("Generating", pagename) with open(filename, "w", encoding='utf-8') as f: f.write(page) - shutil.copy(device["svdfile"], args.htmldir) + shutil.copy(device["svdfile"], htmldir) if __name__ == "__main__": @@ -193,10 +325,9 @@ def generate_if_newer(device): parser.add_argument("svdfiles", help="Path to patched SVD files", nargs="*") args = parser.parse_args() devices = {} - with multiprocessing.pool.ThreadPool() if sys.platform == 'win32' else multiprocessing.Pool() as p: devices = p.map(process_svd, args.svdfiles) - p.map(generate_if_newer, devices) + p.map(generate_if_newer, [(device, args.htmldir) for device in devices]) devices = {d['name']: d for d in devices} index_page = generate_index_page(devices) with open(os.path.join(args.htmldir, "index.html"), "w", encoding='utf-8') as f: diff --git a/scripts/makehtml.template.html b/scripts/makehtml.template.html index 3d1d1e1b4..13211b044 100644 --- a/scripts/makehtml.template.html +++ b/scripts/makehtml.template.html @@ -22,12 +22,22 @@ border: solid 1px #eee; margin-bottom: 3px; } -.registers { +.registers, +.register-map { display: none; } .bitfield td, .bitfield th { text-align: center; } +.vertical { + padding: 5px 0 !important; + vertical-align: middle !important; + text-align: center; + text-align: -webkit-center; +} +.vertical div { + writing-mode: vertical-lr; +} .doccol { color: rgb(92, 184, 92); } @@ -57,9 +67,12 @@
+ + + + {% for i in range(31, -1, -1) %} + + {% endfor %} + + {% for _, register in peripheral.registers|dictsort %} + + + + {% for row in register.table %} + {% for field in row.fields %} + {% if not field.name %} + {% for _ in range(field.width) %} + + {% endfor %} + {% endif %} + {% if field.name %} + + {% endif %} + {% endfor %} + {% endfor %} + + {% endfor %} +
OffsetName
{{ i }}
{{ register.offset }}{{ register.name }} + +
+
- {% for roffset, register in peripheral.registers|dictsort %} + {% for _, register in peripheral.registers|dictsort %}

@@ -166,7 +211,7 @@

{% endfor %} - Toggle Fields. + Toggle Fields

@@ -213,6 +258,10 @@

$(this).parent().siblings(".registers").toggle(); e.preventDefault(); }); + $('.toggle-register-map').click(function(e) { + $(this).parent().siblings(".register-map").toggle(); + e.preventDefault(); + }); $('#show-all-registers').click(function(e) { $('.registers').show(); e.preventDefault(); @@ -235,7 +284,6 @@

var register = parts[1]; $('#' + peripheral + '-registers').show(0, function() { if(parts.length == 3) { - console.log("parts.length == 3"); $('#' + peripheral + '-' + register + '-fields').show(0, function() { window.location.hash = hash; }); diff --git a/scripts/makejson.py b/scripts/makejson.py index 64f0e6123..477fb7fbf 100644 --- a/scripts/makejson.py +++ b/scripts/makejson.py @@ -50,13 +50,13 @@ def parse_device(svdfile): raccs = raccs.text else: raccs = "Unspecified" - roffset = int(rtag.find('addressOffset').text, 16) + roffset = int(rtag.find('addressOffset').text, 0) for ftag in rtag.iter('field'): register_fields_total += 1 fname = ftag.find('name').text fdesc = ftag.find('description').text - foffset = int(ftag.find('bitOffset').text) - fwidth = int(ftag.find('bitWidth').text) + foffset = int(ftag.find('bitOffset').text, 0) + fwidth = int(ftag.find('bitWidth').text, 0) enum = ftag.find('enumeratedValues') if enum is not None: register_fields_documented += 1 diff --git a/scripts/makesettings.sh b/scripts/makesettings.sh new file mode 100755 index 000000000..aeb48ea00 --- /dev/null +++ b/scripts/makesettings.sh @@ -0,0 +1,6 @@ +set -euxo pipefail + +NAME=$(svdtools info $1 device-name --input-format xml) +CRATE_PATH=$(echo $(basename $1) | sed -E 's|(\w*)\.svd\.patched|\1|g') +echo "html_url: https://stm32-rs.github.io/stm32-rs/${NAME}.html" > $2 +echo "crate_path: crate::${CRATE_PATH}" >> $2 diff --git a/scripts/matchperipherals.py b/scripts/matchperipherals.py index 8b0034211..1aa306fdd 100644 --- a/scripts/matchperipherals.py +++ b/scripts/matchperipherals.py @@ -5,7 +5,7 @@ Finds all peripherals that match the specified device. -Usage: python3 scripts/makeyaml.py peripherals/ devices/stm32f0x0.yaml +Usage: python3 scripts/matchperipherals.py devices/fields/ devices/stm32f0x0.yaml """ import sys diff --git a/scripts/periphtemplate.py b/scripts/periphtemplate.py index 85d74389e..debea4285 100644 --- a/scripts/periphtemplate.py +++ b/scripts/periphtemplate.py @@ -29,11 +29,11 @@ def parse_periph(svdfile, pname): for rtag in ptag.iter('register'): fields = {} rname = rtag.find('name').text - roffset = int(rtag.find('addressOffset').text, 16) + roffset = int(rtag.find('addressOffset').text, 0) for ftag in rtag.iter('field'): fname = ftag.find('name').text - foffset = int(ftag.find('bitOffset').text) - fwidth = int(ftag.find('bitWidth').text) + foffset = int(ftag.find('bitOffset').text, 0) + fwidth = int(ftag.find('bitWidth').text, 0) fields[foffset] = {"name": fname, "width": fwidth} registers[roffset] = {"name": rname, "fields": fields} return registers diff --git a/scripts/svd2rust_install.sh b/scripts/svd2rust_install.sh deleted file mode 100755 index 6dcaf1380..000000000 --- a/scripts/svd2rust_install.sh +++ /dev/null @@ -1,15 +0,0 @@ -#!/usr/bin/env bash - -which svd2rust >/dev/null -if [ $? -ne 0 ] -then - cargo install --version $1 svd2rust -else - ver=$(svd2rust -V | cut -d' ' -f2) - if [ "$ver" != "$1" ] - then - cargo install --force --version $1 svd2rust - fi -fi - - diff --git a/scripts/svdmmap.py b/scripts/svdmmap.py deleted file mode 100644 index e273d0a69..000000000 --- a/scripts/svdmmap.py +++ /dev/null @@ -1,239 +0,0 @@ -""" -svdmmap.py - -Copyright 2019 Adam Greig. -Licensed under the MIT and Apache 2.0 licenses. See LICENSE files for details. -""" - -import sys -import copy -import xml.etree.ElementTree as ET - - -def iter_clusters(ptag): - registers = ptag.find('registers') - if registers is None: - return [] - else: - return registers.findall('cluster') - - -def iter_registers(ptag): - registers = ptag.find('registers') - if registers is None: - return [] - else: - return registers.findall('register') - - -def iter_fields(rtag): - fields = rtag.find('fields') - if fields is None: - return [] - else: - return fields.findall('field') - - -ACCESS = { - "read-only": "ro", - "read-write": "rw", - "write-only": "wo", -} - - -def get_access(tag): - """ - Reads and formats the access attribute of the tag. - If possible it is shortened to ro/rw/wo, and then - returned inside brackets with a leading space. - """ - access = get_string(tag, 'access') - if access is not None: - return " (" + ACCESS.get(access, access) + ")" - else: - return "" - - -def get_string(node, tag, default=None): - text = node.findtext(tag, default=default) - if text == default: - return text - return " ".join(text.split()) - - -def get_int(node, tag, default=None): - text = get_string(node, tag, default=default) - if text == default: - return text - text = text.lower().strip() - if text == "true": - return 1 - elif text == "false": - return 0 - elif text[:2] == "0x": - return int(text[2:], 16) - elif text[:2] == "0b": - return int(text[2:], 2) - else: - return int(text, 10) - - -def expand_dim(node): - """ - Given a node (a cluster or a register) which may have a `dim` child, - returns an expanded list of all such nodes with '%s' in the name replaced - by the appropriate index. If there is no `dim` child, a list containing - just the original node is returned. - """ - dim = node.findtext('dim') - if dim is None: - return [node] - inc = get_int(node, 'dimIncrement') - idxs = get_string(node, 'dimIndex') - if idxs is None: - idxs = list(range(dim)) - else: - if "," in idxs: - idxs = idxs.split(",") - elif "-" in idxs: - li, ri = idxs.split("-") - idxs = list(range(int(li), int(ri)+1)) - else: - raise ValueError(f"Unknown dimIndex: '{idxs}'") - nodes = [] - for cnt, idx in enumerate(idxs): - name = get_string(node, 'name').replace("%s", str(idx)) - dim_node = copy.deepcopy(node) - dim_node.find('name').text = name - addr = get_int(dim_node, 'addressOffset') + cnt * inc - dim_node.find('addressOffset').text = f"0x{addr:08x}" - dim_node.attrib['dim_index'] = idx - nodes.append(dim_node) - return nodes - - -def expand_cluster(node): - """ - Given a cluster, returns a list of all registers inside the cluster, - with their names updated to include the cluster index and their address - offsets updated to include the cluster address offset. - The returned register nodes are as though they were never in a cluster. - """ - if node.attrib.get('dim_index') is None: - raise ValueError("Can't process cluster without dim_index") - cluster_idx = node.attrib['dim_index'] - cluster_addr = get_int(node, 'addressOffset') - nodes = [] - for rtag in node.findall('register'): - addr = cluster_addr + get_int(rtag, 'addressOffset') - name = get_string(rtag, 'name') + str(cluster_idx) - new_rtag = copy.deepcopy(rtag) - new_rtag.find('addressOffset').text = f"0x{addr:08x}" - new_rtag.find('name').text = name - nodes.append(new_rtag) - return nodes - - -def parse_register(rtag): - """ - Extract register and field information from a register node into a dict. - """ - fields = {} - rname = get_string(rtag, 'name') - rdesc = get_string(rtag, 'description') - raccess = get_access(rtag) - roffset = get_int(rtag, 'addressOffset') - for ftag in iter_fields(rtag): - fname = get_string(ftag, 'name') - foffset = get_int(ftag, 'bitOffset') - fwidth = get_int(ftag, 'bitWidth') - fdesc = get_string(ftag, 'description') - faccess = get_access(ftag) - fields[fname] = {"name": fname, "offset": foffset, - "width": fwidth, "description": fdesc, - "access": faccess} - return {"name": rname, "offset": roffset, "description": rdesc, - "access": raccess, "fields": fields} - - -def parse(svdfile): - """ - Parse SVD file into dict of peripherals, registers, and fields. - """ - tree = ET.parse(svdfile) - peripherals = {} - device_interrupts = {} - for ptag in tree.find('peripherals').findall('peripheral'): - interrupts = {} - registers = {} - clusters = {} - pname = get_string(ptag, 'name') - pbase = get_int(ptag, 'baseAddress') - for itag in ptag.findall('interrupt'): - iname = get_string(itag, 'name') - idesc = get_string(itag, 'description') - ival = get_int(itag, 'value') - interrupt = {"name": iname, "description": idesc, "value": ival, - "pname": pname} - interrupts[iname] = device_interrupts[ival] = interrupt - for ctag in iter_clusters(ptag): - for ctag in expand_dim(ctag): - cname = get_string(ctag, 'name') - cdesc = get_string(ctag, 'description') - coff = get_int(ctag, 'addressOffset') - for rtag in expand_cluster(ctag): - register = parse_register(rtag) - registers[register['name']] = register - clusters[cname] = {"name": cname, "description": cdesc, - "offset": coff} - for rtag in iter_registers(ptag): - for rtag in expand_dim(rtag): - register = parse_register(rtag) - registers[register['name']] = register - peripherals[pname] = {"name": pname, "base": pbase, - "interrupts": interrupts, "registers": registers, - "clusters": clusters} - if 'derivedFrom' in ptag.attrib: - peripherals[pname]["derives"] = ptag.attrib["derivedFrom"] - for pname, periph in list(peripherals.items()): - if 'derives' in periph: - peripherals[pname]['registers'] = \ - peripherals[periph['derives']]['registers'] - return {"name": svdfile.split(".")[0], "peripherals": peripherals, - "interrupts": device_interrupts} - - -def to_text(device): - """ - Output sorted text of every peripheral, register, field, and interrupt - in the device, such that automated diffing is possible. - """ - mmap = [] - for i in device['interrupts'].values(): - mmap.append(f"INTERRUPT {i['value']:03d}: " - + f"{i['name']} ({i['pname']}): {i['description']}") - for p in device['peripherals'].values(): - mmap.append(f"0x{p['base']:08X} A PERIPHERAL {p['name']}") - for c in p['clusters'].values(): - addr = p['base'] + c['offset'] - mmap.append(f"0x{addr:08X} B CLUSTER {c['name']}: " - + f"{c['description']}") - for r in p['registers'].values(): - addr = p['base'] + r['offset'] - mmap.append(f"0x{addr:08X} B REGISTER {r['name']}{r['access']}: " - + f"{r['description']}") - for f in r['fields'].values(): - offset, width = f['offset'], f['width'] - mmap.append(f"0x{addr:08X} C FIELD {offset:02d}w{width:02d} " - + f"{f['name']}{f['access']}: " - + f"{f['description']}") - return "\n".join(sorted(mmap)) - - -def main(): - device = parse(sys.argv[1]) - print(to_text(device)) - - -if __name__ == "__main__": - main() diff --git a/scripts/tool_install.sh b/scripts/tool_install.sh new file mode 100755 index 000000000..e8387bb90 --- /dev/null +++ b/scripts/tool_install.sh @@ -0,0 +1,56 @@ +#!/usr/bin/env bash + +set -euo pipefail + +CARGO_HOME="${CARGO_HOME:-$HOME/.cargo/}" + +FORM_VERSION="${FORM_VERSION:-v0.13.0}" +SVDTOOLS_VERSION="${SVDTOOLS_VERSION:-v0.4.6}" +SVD2RUST_VERSION="${SVD2RUST_VERSION:-v0.36.1}" +SVDCONV_VERSION="${SVDCONV_VERSION:-3.3.46}" + +case "${1:-}" in + form) + form="${2:-$FORM_VERSION}" + ;; + svdtools) + svdtools="${2:-$SVDTOOLS_VERSION}" + ;; + svd2rust) + svd2rust="${2:-$SVD2RUST_VERSION}" + ;; + svdconv) + svdconv="${2:-$SVDCONV_VERSION}" + ;; + *) + form=$FORM_VERSION + svdtools=$SVDTOOLS_VERSION + svd2rust=$SVD2RUST_VERSION + svdconv=$SVDCONV_VERSION + echo "Install default versions" + ;; +esac + +if [ "${form:-}" ]; then + echo "form = ${form}" + curl -sSfL https://github.com/djmcgill/form/releases/download/$form/form-x86_64-unknown-linux-gnu.gz | gzip -d - > $CARGO_HOME/bin/form + chmod +x $CARGO_HOME/bin/form +fi + +if [ "${svdtools:-}" ]; then + echo "svdtools = ${svdtools}" + curl -sSfL https://github.com/stm32-rs/svdtools/releases/download/$svdtools/svdtools-x86_64-unknown-linux-gnu.gz | gzip -d - > $CARGO_HOME/bin/svdtools + chmod +x $CARGO_HOME/bin/svdtools +fi + +if [ "${svd2rust:-}" ]; then + echo "svd2rust = ${svd2rust}" + curl -sSfL https://github.com/rust-embedded/svd2rust/releases/download/$svd2rust/svd2rust-x86_64-unknown-linux-gnu.gz | gzip -d - > $CARGO_HOME/bin/svd2rust + chmod +x $CARGO_HOME/bin/svd2rust +fi + +if [ "${svdconv:-}" ]; then + echo "svdconv = ${svdconv}" + curl -sSfL https://github.com/Open-CMSIS-Pack/devtools/releases/download/tools/svdconv/$svdconv/svdconv-$svdconv-linux-amd64.tbz2 | tar -xj -C $CARGO_HOME/bin/ + chmod +x $CARGO_HOME/bin/svdconv +fi diff --git a/stm32_part_table.yaml b/stm32_part_table.yaml index c44bb2f10..7ded89b16 100644 --- a/stm32_part_table.yaml +++ b/stm32_part_table.yaml @@ -10,6 +10,16 @@ # # This data is used to generate more informative crate READMEs. +stm32c0: + stm32c0x1: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32c0x1.html + rm: RM0490 + rm_title: STM32C0x1 + rm_url: https://www.st.com/resource/en/reference_manual/rm0490-stm32c0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32C011 + - STM32C031 + - STM32C071 stm32f0: stm32f0x0: @@ -53,7 +63,6 @@ stm32f0: - STM32F078 - STM32F098 - stm32f1: stm32f100: url: https://www.st.com/en/microcontrollers-microprocessors/stm32f100-value-line.html @@ -96,7 +105,6 @@ stm32f1: - STM32F105 - STM32F107 - stm32f2: stm32f215: url: https://www.st.com/en/microcontrollers-microprocessors/stm32f2x5.html @@ -116,7 +124,6 @@ stm32f2: - STM32F207 - STM32F217 - stm32f3: stm32f301: url: https://www.st.com/en/microcontrollers-microprocessors/stm32f301.html @@ -142,6 +149,9 @@ stm32f3: rm_url: https://www.st.com/resource/en/reference_manual/dm00043574.pdf members: - STM32F303 + - STM32F328 + - STM32F358 + - STM32F398 stm32f373: url: https://www.st.com/en/microcontrollers-microprocessors/stm32f373.html @@ -160,17 +170,6 @@ stm32f3: members: - STM32F334 - stm32f3x8: - url: https://www.st.com/en/microcontrollers-microprocessors/stm32f3x8.html - rm: RM0316 - rm_title: STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8, STM32F358xC, STM32F398xE - rm_url: https://www.st.com/resource/en/reference_manual/dm00043574.pdf - members: - - STM32F328 - - STM32F358 - - STM32F398 - - stm32f4: stm32f401: url: https://www.st.com/en/microcontrollers-microprocessors/stm32f401.html @@ -266,7 +265,6 @@ stm32f4: - STM32F469 - STM32F479 - stm32f7: stm32f730: url: https://www.st.com/en/microcontrollers-microprocessors/stm32f7x0-value-line.html @@ -276,6 +274,14 @@ stm32f7: members: - STM32F730 + stm32f750: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32f7x0-value-line.html + rm: RM0385 + rm_title: STM32F75xxx and STM32F74xxx + rm_url: https://www.st.com/resource/en/reference_manual/dm00124865.pdf + members: + - STM32F750 + stm32f7x2: url: https://www.st.com/en/microcontrollers-microprocessors/stm32f7x2.html rm: RM0431 @@ -338,6 +344,38 @@ stm32f7: - STM32F778 - STM32F779 +stm32h5: + stm32h503: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32h503.html + rm: RM0492 + rm_title: STM32H503 line Arm®-based 32-bit MCUs + rm_url: https://www.st.com/resource/en/reference_manual/rm0492-stm32h503-line-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32H503 + + stm32h562: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32h562.html + rm: RM0481 + rm_title: STM32H563/H573 and STM32H562 Arm®-based 32-bit MCUs + rm_url: https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32H562 + + stm32h563: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32h563-573.html + rm: RM0481 + rm_title: STM32H563/H573 and STM32H562 Arm®-based 32-bit MCUs + rm_url: https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32H563 + + stm32h573: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32h563-573.html + rm: RM0481 + rm_title: STM32H563/H573 and STM32H562 Arm®-based 32-bit MCUs + rm_url: https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32H573 stm32h7: stm32h743: @@ -372,6 +410,18 @@ stm32h7: members: - STM32H753V + stm32h735: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32h730-value-line.html + rm: RM0468 + rm_title: STM32H723/733, STM32H725/735 and STM32H730 + rm_url: https://www.st.com/resource/en/reference_manual/dm00603761.pdf + members: + - STM32H723 + - STM32H725 + - STM32H730 + - STM32H733 + - STM32H735 + stm32h7b3: url: https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3-7b3.html rm: RM0455 @@ -404,7 +454,33 @@ stm32h7: - STM32H755 (CM4) - STM32H757 (CM4) + stm32h7r: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32h7r7-7s7.html + rm: RM0477 + rm_title: STM32H7Rx/7Sx + rm_url: https://www.st.com/resource/en/reference_manual/dm00686107.pdf + members: + - STM32H7R3 + - STM32H7R7 + + stm32h7s: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32h7r7-7s7.html + rm: RM0477 + rm_title: STM32H7Rx/7Sx + rm_url: https://www.st.com/resource/en/reference_manual/dm00686107.pdf + members: + - STM32H7S3 + - STM32H7S7 + stm32l0: + stm32l0x0: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32l0x0-value-line.html + rm: RM0451 + rm_title: STM32L0x0 + rm_url: https://www.st.com/resource/en/reference_manual/dm00443854-ultralowpower-stm32l0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32L010 + stm32l0x1: url: https://www.st.com/en/microcontrollers-microprocessors/stm32l0x1.html rm: RM0377 @@ -441,7 +517,6 @@ stm32l0: - STM32L073 - STM32L083 - stm32l1: stm32l100: url: https://www.st.com/en/microcontrollers-microprocessors/stm32l100-value-line.html @@ -468,7 +543,6 @@ stm32l1: members: - STM32L162 - stm32l4: stm32l4x1: url: https://www.st.com/en/microcontrollers-microprocessors/stm32l4x1.html @@ -491,6 +565,15 @@ stm32l4: - STM32L452 - STM32L462 + stm32l412: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32l4x2.html + rm: RM0394 + rm_title: STM32L43xxx STM32L44xxx STM32L45xxx STM32L46xxx + rm_url: https://www.st.com/resource/en/reference_manual/dm00151940.pdf + members: + - STM32L412 + - STM32L422 + stm32l4x3: url: https://www.st.com/en/microcontrollers-microprocessors/stm32l4x3.html rm: RM0394 @@ -519,6 +602,24 @@ stm32l4: - STM32L496 - STM32L4A6 + stm32l4r5: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32l4r5-s5.html + rm: RM0432 + rm_title: STM32L4+ Series + rm_url: https://www.st.com/resource/en/reference_manual/dm00310109.pdf + members: + - STM32L4R5 + - STM32L4S5 + + stm32l4r9: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32l4r9-s9.html + rm: RM0432 + rm_title: STM32L4+ Series + rm_url: https://www.st.com/resource/en/reference_manual/dm00310109.pdf + members: + - STM32L4R9 + - STM32L4S9 + stm32l5: stm32l552: url: https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-ultra-low-power-mcus/stm32l5-series/stm32l5x2.html @@ -536,26 +637,101 @@ stm32l5: - STM32L562 stm32g0: - stm32g0x0: + stm32g030: url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x0-value-line.html rm: RM0454 - rm_title: STM32G070xx - rm_url: https://www.st.com/resource/en/reference_manual/dm00463896.pdf + rm_title: STM32G0x0 + rm_url: https://www.st.com/resource/en/reference_manual/dm00463896-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf members: - - STM32G070 - STM32G030 - stm32g0x1: + stm32g050: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x0-value-line.html + rm: RM0454 + rm_title: STM32G0x0 + rm_url: https://www.st.com/resource/en/reference_manual/dm00463896-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32G050 + + stm32g070: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x0-value-line.html + rm: RM0454 + rm_title: STM32G0x0 + rm_url: https://www.st.com/resource/en/reference_manual/dm00463896-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32G070 + + stm32g0b0: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x0-value-line.html + rm: RM0454 + rm_title: STM32G0x0 + rm_url: https://www.st.com/resource/en/reference_manual/dm00463896-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32G0b0 + + stm32g031: url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x1.html rm: RM0444 - rm_title: STM32G071xx, STM32G081xx - rm_url: https://www.st.com/resource/en/reference_manual/dm00371828.pdf + rm_title: STM32G0x1 + rm_url: https://www.st.com/resource/en/reference_manual/dm00371828-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf members: - STM32G031 + + stm32g041: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x1.html + rm: RM0444 + rm_title: STM32G0x1 + rm_url: https://www.st.com/resource/en/reference_manual/dm00371828-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: - STM32G041 + + stm32g051: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x1.html + rm: RM0444 + rm_title: STM32G0x1 + rm_url: https://www.st.com/resource/en/reference_manual/dm00371828-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32G051 + + stm32g061: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x1.html + rm: RM0444 + rm_title: STM32G0x1 + rm_url: https://www.st.com/resource/en/reference_manual/dm00371828-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32G061 + + stm32g071: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x1.html + rm: RM0444 + rm_title: STM32G0x1 + rm_url: https://www.st.com/resource/en/reference_manual/dm00371828-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: - STM32G071 + + stm32g081: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x1.html + rm: RM0444 + rm_title: STM32G0x1 + rm_url: https://www.st.com/resource/en/reference_manual/dm00371828-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: - STM32G081 + stm32g0b1: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x1.html + rm: RM0444 + rm_title: STM32G0x1 + rm_url: https://www.st.com/resource/en/reference_manual/dm00371828-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32G0b1 + + stm32g0c1: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32g0x1.html + rm: RM0444 + rm_title: STM32G0x1 + rm_url: https://www.st.com/resource/en/reference_manual/dm00371828-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32G0c1 stm32g4: stm32g4x1: @@ -591,4 +767,128 @@ stm32mp1: rm_title: STM32MP157 rm_url: https://www.st.com/resource/en/reference_manual/dm00366355-stm32mp157-advanced-armbased-32bit-mpus-stmicroelectronics.pdf members: - - STM32MP157 \ No newline at end of file + - STM32MP157 + stm32mp153: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32mp153.html + rm: RM0442 + rm_title: STM32MP153 + rm_url: https://www.st.com/resource/en/reference_manual/rm0442-stm32mp153-advanced-armbased-32bit-mpus-stmicroelectronics.pdf + members: + - STM32MP153 + +stm32n6: + stm32n6x5: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32n6x5.html + members: + - STM32N645 + - STM32N655 + stm32n6x7: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32n6x7.html + members: + - STM32N647 + - STM32N657 + rm: RM0486 + rm_title: STM32N647/657xx Arm® -based 32-bit MCUs + rm_url: https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf + +stm32u0: + stm32u0xx: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u0-series.html + rm: RM0503 + rm_title: STM32U0 + rm_url: https://www.st.com/resource/en/reference_manual/rm0503-stm32u0-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U031 + - STM32U073 + - STM32U083 + +stm32wl: + stm32wle5: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32wlex.html + rm: RM0461 + rm_title: STM32WLEx + rm_url: https://www.st.com/resource/en/reference_manual/dm00530369-stm32wlex-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf + members: + - STM32WLE5 + + stm32wl5x_cm4: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32wl5x.html + rm: RM0453 + rm_title: STM32WL5x + rm_url: https://www.st.com/resource/en/reference_manual/dm00451556-stm32wl5x-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf + members: + - STM32WL5X (CM4) + + stm32wl5x_cm0p: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32wl5x.html + rm: RM0453 + rm_title: STM32WL5x + rm_url: https://www.st.com/resource/en/reference_manual/dm00451556-stm32wl5x-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf + members: + - STM32WL5X (CM0+) + +stm32wb: + stm32wb55: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32wbx5.html + rm: RM0434 + rm_title: STM32WBx5 + rm_url: https://www.st.com/resource/en/reference_manual/dm00318631-multiprotocol-wireless-32bit-mcu-armbased-cortexm4-with-fpu-bluetooth-lowenergy-and-802154-radio-solution-stmicroelectronics.pdf + members: + - STM32WB55 +stm32u5: + stm32u535: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u535-545.html + rm: RM0456 + rm_title: STM32U535 + rm_url: https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U535 + stm32u545: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u535-545.html + rm: RM0456 + rm_title: STM32U545 + rm_url: https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U545 + stm32u575: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html + rm: RM0456 + rm_title: STM32U575 + rm_url: https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U575 + stm32u585: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html + rm: RM0456 + rm_title: STM32U585 + rm_url: https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U585 + stm32u595: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u595-5a5.html + rm: RM0456 + rm_title: STM32U595 + rm_url: https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U595 + stm32u5a5: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u595-5a5.html + rm: RM0456 + rm_title: STM32U5A5 + rm_url: https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U5a5 + stm32u599: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u599-5a9.html + rm: RM0456 + rm_title: STM32U599 with enhanced graphics capability) + rm_url: https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U599 + stm32u5a9: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32u599-5a9.html + rm: RM0456 + rm_title: STM32U5A9 with enhanced graphics capability) + rm_url: https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + members: + - STM32U5a9 diff --git a/svd/README.md b/svd/README.md index b4db1ec61..f56c7eeea 100644 --- a/svd/README.md +++ b/svd/README.md @@ -1,10 +1,10 @@ # SVD Files -SVD files from zips in `vendor/` are extracted to this directory before -processing. They are also renamed to lower-case so that the SVD name, the YAML +SVD files from zips in `vendor/` are extracted to this directory before +processing. They are also renamed to lower-case so that the SVD name, the YAML name, and the Rust source file name all match. Run `extract.sh` to extract all zips in `vendor/` and rename to lowercase. -Don't commit any SVDs from this directory to git; only the zips in `vendor/` +Don't commit any SVDs from this directory to git; only the zips in `vendor/` should be committed. diff --git a/svd/cmsis-svd.xsd b/svd/cmsis-svd.xsd index 2460a3bf4..ea3771560 100644 --- a/svd/cmsis-svd.xsd +++ b/svd/cmsis-svd.xsd @@ -26,6 +26,7 @@ stm32-rs changes: - enumerationType now has enumeratedValue minOccurs=0, as otherwise a derivedFrom enumerationType does not validate + - add derivePathType that allows using full path for derivedFrom Version 1.3.6: - add ARMV81MML as enumeration value for cpuNameType. @@ -99,6 +100,7 @@ + @@ -154,6 +156,13 @@ + + + + + + + @@ -464,7 +473,7 @@ - + @@ -510,7 +519,7 @@ - + @@ -537,7 +546,7 @@ - + diff --git a/svd/download.sh b/svd/download.sh new file mode 100755 index 000000000..490b73724 --- /dev/null +++ b/svd/download.sh @@ -0,0 +1,31 @@ +#!/usr/bin/env bash +declare -a arr=( + "stm32c0-svd" + "stm32f0_svd" + "stm32f1_svd" + "stm32f2_svd" + "stm32f3-svd" + "stm32f4-svd" + "stm32f7-svd" + "stm32g0-svd" + "stm32g4_svd" + "stm32h5-svd" + "stm32h7-svd" + "stm32h7rs-svd" + "stm32l0-svd" + "stm32l1_svd" + "stm32l4_svd" + "stm32l4plus-svd" + "stm32l5-svd" + "stm32mp1-svd" + "stm32u0-svd" + "stm32u5_svd" + "stm32wb_svd" + "stm32wl-svd" + "stm32wl3-svd" +) + +for f in "${arr[@]}" +do + wget -U "Mozilla/4.0 (compatible; MSIE 6.0; Windows NT 5.1; SV1)" https://www.st.com/resource/en/svd/$f.zip -O vendor/en.$f.zip +done diff --git a/svd/extract.ds b/svd/extract.ds new file mode 100644 index 000000000..ef577aeb4 --- /dev/null +++ b/svd/extract.ds @@ -0,0 +1,41 @@ + +cd svd + +handle = glob_array vendor/*.zip +for path in ${handle} + echo ${path} + mkdir tmp + unzip ${path} tmp + svd_handle = glob_array tmp/**/*.svd . + for svd in ${svd_handle} + svd_name = basename ${svd} + svd_name = lowercase ${svd_name} + cp ${svd} ${svd_name} + end + rm -r tmp +end + +# Copy and rename H7 files to remove trailing 'x' +# and provide a second copy of the SVDs to modify +# for the revision-V hardware. +mv stm32h745_cm4.svd stm32h745cm4.svd +mv stm32h745_cm7.svd stm32h745cm7.svd +mv stm32h747_cm4.svd stm32h747cm4.svd +mv stm32h747_cm7.svd stm32h747cm7.svd +mv stm32h755_cm4.svd stm32h755cm4.svd +mv stm32h755_cm7.svd stm32h755cm7.svd +mv stm32h757_cm4.svd stm32h757cm4.svd +mv stm32h757_cm7.svd stm32h757cm7.svd +cp stm32h743.svd stm32h743v.svd +cp stm32h753.svd stm32h753v.svd + +# Rename MP1 svd files to remove trailing 'x' +mv stm32mp157x.svd stm32mp157.svd +mv stm32mp153x.svd stm32mp153.svd + +# Rename WLE5 file to remove _cm4, since it only has one core. +mv stm32wle5_cm4.svd stm32wle5.svd + +mv stm32wb55_cm4.svd stm32wb55.svd + +touch .extracted diff --git a/svd/extract.sh b/svd/extract.sh index 2b2d2a9ad..bea9a216e 100755 --- a/svd/extract.sh +++ b/svd/extract.sh @@ -3,11 +3,25 @@ for f in vendor/*.zip; do unzip -juLL $f '**.svd' done -cp stm32h743x.svd stm32h743.svd -cp stm32h743x.svd stm32h743v.svd -cp stm32h753x.svd stm32h753.svd -cp stm32h753x.svd stm32h753v.svd -cp stm32h7x5_cm4.svd stm32h747cm4.svd -cp stm32h7x5_cm7.svd stm32h747cm7.svd -cp stm32h7b3x.svd stm32h7b3.svd -cp stm32mp157x.svd stm32mp157.svd +# Copy and rename H7 files to remove trailing 'x' +# and provide a second copy of the SVDs to modify +# for the revision-V hardware. +mv stm32h745_cm4.svd stm32h745cm4.svd +mv stm32h745_cm7.svd stm32h745cm7.svd +mv stm32h747_cm4.svd stm32h747cm4.svd +mv stm32h747_cm7.svd stm32h747cm7.svd +mv stm32h755_cm4.svd stm32h755cm4.svd +mv stm32h755_cm7.svd stm32h755cm7.svd +mv stm32h757_cm4.svd stm32h757cm4.svd +mv stm32h757_cm7.svd stm32h757cm7.svd +cp stm32h743.svd stm32h743v.svd +cp stm32h753.svd stm32h753v.svd + +# Rename MP1 svd files to remove trailing 'x' +mv stm32mp157x.svd stm32mp157.svd +mv stm32mp153x.svd stm32mp153.svd + +# Rename WLE5 file to remove _cm4, since it only has one core. +mv stm32wle5_cm4.svd stm32wle5.svd + +mv stm32wb55_cm4.svd stm32wb55.svd diff --git a/svd/vendor/README.md b/svd/vendor/README.md index c6e55596b..18d914826 100644 --- a/svd/vendor/README.md +++ b/svd/vendor/README.md @@ -1,6 +1,6 @@ # STM32 SVD files from ST -Original files fetched from [st.com]. Redistributed according to the terms of +Original files fetched from [st.com]. Redistributed according to the terms of ST Software license agreement, included as [ST_SLA.pdf](ST_SLA.pdf). [st.com]:http://www.st.com/content/st_com/en/support/resources/resource-selector.html?querycriteria=productId=SC1169$$resourceCategory=cad_models_and_symbols$$resourceType=svd diff --git a/svd/vendor/STM32MP157x_v1r6.zip b/svd/vendor/STM32MP157x_v1r6.zip deleted file mode 100644 index 8368b9524..000000000 Binary files a/svd/vendor/STM32MP157x_v1r6.zip and /dev/null differ diff --git a/svd/vendor/en.stm32c0-svd.zip b/svd/vendor/en.stm32c0-svd.zip new file mode 100644 index 000000000..b1f3e8f1a Binary files /dev/null and b/svd/vendor/en.stm32c0-svd.zip differ diff --git a/svd/vendor/en.stm32f3-svd.zip b/svd/vendor/en.stm32f3-svd.zip new file mode 100644 index 000000000..48a4bb2d8 Binary files /dev/null and b/svd/vendor/en.stm32f3-svd.zip differ diff --git a/svd/vendor/en.stm32f3_svd.zip b/svd/vendor/en.stm32f3_svd.zip deleted file mode 100644 index 64e7d02d6..000000000 Binary files a/svd/vendor/en.stm32f3_svd.zip and /dev/null differ diff --git a/svd/vendor/en.stm32f4-svd.zip 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a/svd/vendor/stm32n6-svd.zip b/svd/vendor/stm32n6-svd.zip new file mode 100644 index 000000000..afd871498 Binary files /dev/null and b/svd/vendor/stm32n6-svd.zip differ diff --git a/svd2rust.toml b/svd2rust.toml new file mode 100644 index 000000000..0e408f683 --- /dev/null +++ b/svd2rust.toml @@ -0,0 +1,27 @@ +make_mod = true +generic_mod = true +strict = true +max_cluster_size = true +atomics = true +atomics_feature = "atomics" +impl_debug = true +impl_defmt = "defmt" +reexport_core_peripherals = true +reexport_interrupt = true +ident_formats_theme = "legacy" + +[ident_formats.register_spec] +case = "constant" +suffix = "rs" + +[ident_formats.enum_name] +case = "constant" + +[ident_formats.enum_read_name] +case = "constant" + +[ident_formats.enum_write_name] +case = "constant" + +[ident_formats.enum_value] +case = "pascal"