From 8b03042c926b6379daef8fb46f2e0fbb0e0a7b1f Mon Sep 17 00:00:00 2001
From: Matt Ickstadt <mattico8@gmail.com>
Date: Sat, 13 Feb 2021 16:22:36 -0600
Subject: [PATCH 1/2] H7B3: Split DAC1/2 REC, remove LPTIM45

---
 devices/stm32h7b3.yaml | 63 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)

diff --git a/devices/stm32h7b3.yaml b/devices/stm32h7b3.yaml
index f9644e9d5..a305fee7f 100644
--- a/devices/stm32h7b3.yaml
+++ b/devices/stm32h7b3.yaml
@@ -18,6 +18,69 @@ _modify:
   OctoSPII_O_Manager:
     groupName: OctoSPII_O_Manager
 
+# Remove LPTIM4/5 from RCC TODO: remove from EXTI  
+# split DAC1/2 REC
+RCC:
+  APB1LRSTR:
+    _modify:
+      DAC12RST:
+        name: DAC1RST
+        description: DAC1 (containing two converters) reset
+  APB1LENR:
+    _modify:
+      DAC12EN:
+        name: DAC1EN
+        description: DAC1 (containing two converters) peripheral clock enable
+  APB1LLPENR:
+    _modify:
+      ResetValue: 0xE8FFC3FF
+      DAC12LPEN:
+        name: DAC1LPEN
+        description: DAC1 (containing two converters) peripheral clock enable during CSleep mode
+  APB4RSTR:
+    _delete:
+      - LPTIM4RST
+      - LPTIM5RST
+    _add:
+      DAC2RST:
+        description: DAC2 (containing one converter) reset
+        bitOffset: 13
+        bitWidth: 1
+        access: read-write
+  APB4ENR:
+    _delete:
+      - LPTIM4EN
+      - LPTIM5EN
+    _modify:
+      ResetValue: 0x00010000
+    _add:
+      DAC2EN:
+        description: DAC2 (containing one converter) peripheral clock enable
+        bitOffset: 13
+        bitWidth: 1
+        access: read-write
+  APB4LPENR:
+    _delete:
+      - LPTIM4LPEN
+      - LPTIM5LPEN
+    _modify:
+      ResetValue: 0x0C01E6AA
+    _add:
+      DAC2LPEN:
+        description: DAC2 (containing one converter) peripheral clock enable during CSleep mode
+        bitOffset: 13
+        bitWidth: 1
+        access: read-write
+  D3AMR:
+    _delete:
+      - LPTIM4AMEN
+      - LPTIM5AMEN
+DBGMCU:
+  APB4FZ1:
+    _delete:
+      - LPTIM4
+      - LPTIM5
+
 _include:
  - common_patches/h7_common_highmemory.yaml
  - common_patches/dma_fcr_wo.yaml

From 57c5bd29c383949bff1c04ac634f60752caa489f Mon Sep 17 00:00:00 2001
From: Adam Greig <adam@adamgreig.com>
Date: Mon, 15 Feb 2021 02:49:17 +0000
Subject: [PATCH 2/2] Fix changes to resetValues in h7b3

---
 devices/stm32h7b3.yaml | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/devices/stm32h7b3.yaml b/devices/stm32h7b3.yaml
index a305fee7f..1c3a8c214 100644
--- a/devices/stm32h7b3.yaml
+++ b/devices/stm32h7b3.yaml
@@ -18,9 +18,21 @@ _modify:
   OctoSPII_O_Manager:
     groupName: OctoSPII_O_Manager
 
-# Remove LPTIM4/5 from RCC TODO: remove from EXTI  
-# split DAC1/2 REC
+# Remove LPTIM4/5 from RCC
+# Split DAC1/2 REC
+# TODO: remove LPTIM4/LPTIM5 from EXTI enumerated values
 RCC:
+  _modify:
+    # Fix reset values for these registers.
+    # Note that the rename operation to remove C1 happens alongside this
+    # modification, so we have to use the original names.
+    C1_APB1LLPENR:
+      resetValue: "0xE8FFC3FF"
+    C1_APB4ENR:
+      resetValue: "0x00010000"
+    C1_APB4LPENR:
+      resetValue: "0x0C01E6AA"
+
   APB1LRSTR:
     _modify:
       DAC12RST:
@@ -33,7 +45,6 @@ RCC:
         description: DAC1 (containing two converters) peripheral clock enable
   APB1LLPENR:
     _modify:
-      ResetValue: 0xE8FFC3FF
       DAC12LPEN:
         name: DAC1LPEN
         description: DAC1 (containing two converters) peripheral clock enable during CSleep mode
@@ -51,8 +62,6 @@ RCC:
     _delete:
       - LPTIM4EN
       - LPTIM5EN
-    _modify:
-      ResetValue: 0x00010000
     _add:
       DAC2EN:
         description: DAC2 (containing one converter) peripheral clock enable
@@ -63,8 +72,6 @@ RCC:
     _delete:
       - LPTIM4LPEN
       - LPTIM5LPEN
-    _modify:
-      ResetValue: 0x0C01E6AA
     _add:
       DAC2LPEN:
         description: DAC2 (containing one converter) peripheral clock enable during CSleep mode