From e3106c8a65d3b2b73920f06e17b714fbea14d319 Mon Sep 17 00:00:00 2001
From: Cyrus Metcalf <cyrus.metcalf@gmail.com>
Date: Wed, 17 Mar 2021 16:23:15 -0700
Subject: [PATCH 1/3] Fix bit shift in AHB1 register for CRC
 enable/reset/sleep-mode bits

Discovered when attempting to enable CRC hardware module.
```rust
    let crc_guy = dp.CRC.constrain(&mut rcc.ahb1);
```
CRC output would be 0. Found with debugger that the enable bit was not
being set in rcc.ahb1 power enable register. Other peripherals in the
register (DMA1/2) could be enabled and the remaining bits in the
register are not writable.

Tested against the following code provided by STM32CubeMX, in which the
CRC module is functional.

Source: CMSIS/Device/ST/STM32L4xx/Include/stm32l433xx.h
```

```
 - STM32L43xxx... Reference Manual RM0394 Rev 4. Sections 6.4.9, 6.4.15, 6.4.21

 - Bug Verified/Fixed/Tested on STM32L433 (Nucleo-L433RC-P)
---
 devices/stm32l4x3.yaml | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/devices/stm32l4x3.yaml b/devices/stm32l4x3.yaml
index c36f06f73..9674d344b 100644
--- a/devices/stm32l4x3.yaml
+++ b/devices/stm32l4x3.yaml
@@ -11,6 +11,21 @@ RCC:
       USBF:
         name: USBFSEN
         description: USB FS clock enable
+        
+# SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN  11 bits instead of 12
+RCC:
+    AHB1ENR:
+        _modify:
+            CRCEN:
+                bitOffset: 12
+    AHB1RSTR:
+        _modify:
+            CRCRST:
+                bitOffset: 12
+    AHB1SMENR:
+        _modify:
+            CRCSMEN:
+                bitOffset: 12
 
 _modify:
   # The SVD calls ADC1 ADC.

From 3aca3ef434541de0f888e205e9f99a30b420742a Mon Sep 17 00:00:00 2001
From: Cyrus Metcalf <cyrus.metcalf@gmail.com>
Date: Tue, 23 Mar 2021 20:17:19 -0700
Subject: [PATCH 2/3] Update devices/stm32l4x3.yaml

Co-authored-by: Adam Greig <adam@adamgreig.com>
---
 devices/stm32l4x3.yaml | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/devices/stm32l4x3.yaml b/devices/stm32l4x3.yaml
index 9674d344b..3889b3720 100644
--- a/devices/stm32l4x3.yaml
+++ b/devices/stm32l4x3.yaml
@@ -12,8 +12,7 @@ RCC:
         name: USBFSEN
         description: USB FS clock enable
         
-# SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN  11 bits instead of 12
-RCC:
+    # SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN  11 bits instead of 12
     AHB1ENR:
         _modify:
             CRCEN:

From 2f5b0e5faef6d7d735d30dd319ca7f9aa8eed11d Mon Sep 17 00:00:00 2001
From: Cyrus Metcalf <cyrus.metcalf@gmail.com>
Date: Sat, 27 Mar 2021 22:02:39 -0700
Subject: [PATCH 3/3] Update devices/stm32l4x3.yaml

Co-authored-by: Adam Greig <adam@adamgreig.com>
---
 devices/stm32l4x3.yaml | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/devices/stm32l4x3.yaml b/devices/stm32l4x3.yaml
index 3889b3720..642eb6551 100644
--- a/devices/stm32l4x3.yaml
+++ b/devices/stm32l4x3.yaml
@@ -12,19 +12,19 @@ RCC:
         name: USBFSEN
         description: USB FS clock enable
         
-    # SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN  11 bits instead of 12
-    AHB1ENR:
-        _modify:
-            CRCEN:
-                bitOffset: 12
-    AHB1RSTR:
-        _modify:
-            CRCRST:
-                bitOffset: 12
-    AHB1SMENR:
-        _modify:
-            CRCSMEN:
-                bitOffset: 12
+  # SVD incorrectly shifts CRCEN/CRCRST/CRCSMEN  11 bits instead of 12
+  AHB1ENR:
+    _modify:
+      CRCEN:
+        bitOffset: 12
+  AHB1RSTR:
+    _modify:
+      CRCRST:
+        bitOffset: 12
+  AHB1SMENR:
+    _modify:
+      CRCSMEN:
+        bitOffset: 12
 
 _modify:
   # The SVD calls ADC1 ADC.