diff --git a/devices/common_patches/dma/bdma_v2_new.yaml b/devices/common_patches/dma/bdma_v2_new.yaml new file mode 100644 index 000000000..f08a86040 --- /dev/null +++ b/devices/common_patches/dma/bdma_v2_new.yaml @@ -0,0 +1,1101 @@ +# Creates all the registers for a BDMA v2 peripheral from scratch + +"BDMA*": + _add: + ISR: + description: Interrupt status register + addressOffset: 0x00 + access: read-only + resetValue: 0x00000000 + fields: + TEIF7: + description: Transfer error (TE) flag for channel x + bitOffset: 31 + bitWidth: 1 + HTIF7: + description: Half transfer (HT) flag for channel x + bitOffset: 30 + bitWidth: 1 + TCIF7: + description: Transfer complete (TC) flag for channel x + bitOffset: 29 + bitWidth: 1 + GIF7: + description: Global interrupt flag for channel x + bitOffset: 28 + bitWidth: 1 + TEIF6: + description: Transfer error (TE) flag for channel x + bitOffset: 27 + bitWidth: 1 + HTIF6: + description: Half transfer (HT) flag for channel x + bitOffset: 26 + bitWidth: 1 + TCIF6: + description: Transfer complete (TC) flag for channel x + bitOffset: 25 + bitWidth: 1 + GIF6: + description: Global interrupt flag for channel x + bitOffset: 24 + bitWidth: 1 + TEIF5: + description: Transfer error (TE) flag for channel x + bitOffset: 23 + bitWidth: 1 + HTIF5: + description: Half transfer (HT) flag for channel x + bitOffset: 22 + bitWidth: 1 + TCIF5: + description: Transfer complete (TC) flag for channel x + bitOffset: 21 + bitWidth: 1 + GIF5: + description: Global interrupt flag for channel x + bitOffset: 20 + bitWidth: 1 + TEIF4: + description: Transfer error (TE) flag for channel x + bitOffset: 19 + bitWidth: 1 + HTIF4: + description: Half transfer (HT) flag for channel x + bitOffset: 18 + bitWidth: 1 + TCIF4: + description: Transfer complete (TC) flag for channel x + bitOffset: 17 + bitWidth: 1 + GIF4: + description: Global interrupt flag for channel x + bitOffset: 16 + bitWidth: 1 + TEIF3: + description: Transfer error (TE) flag for channel x + bitOffset: 15 + bitWidth: 1 + HTIF3: + description: Half transfer (HT) flag for channel x + bitOffset: 14 + bitWidth: 1 + TCIF3: + description: Transfer complete (TC) flag for channel x + bitOffset: 13 + bitWidth: 1 + GIF3: + description: Global interrupt flag for channel x + bitOffset: 12 + bitWidth: 1 + TEIF2: + description: Transfer error (TE) flag for channel x + bitOffset: 11 + bitWidth: 1 + HTIF2: + description: Half transfer (HT) flag for channel x + bitOffset: 10 + bitWidth: 1 + TCIF2: + description: Transfer complete (TC) flag for channel x + bitOffset: 9 + bitWidth: 1 + GIF2: + description: Global interrupt flag for channel x + bitOffset: 8 + bitWidth: 1 + TEIF1: + description: Transfer error (TE) flag for channel x + bitOffset: 7 + bitWidth: 1 + HTIF1: + description: Half transfer (HT) flag for channel x + bitOffset: 6 + bitWidth: 1 + TCIF1: + description: Transfer complete (TC) flag for channel x + bitOffset: 5 + bitWidth: 1 + GIF1: + description: Global interrupt flag for channel x + bitOffset: 4 + bitWidth: 1 + TEIF0: + description: Transfer error (TE) flag for channel x + bitOffset: 3 + bitWidth: 1 + HTIF0: + description: Half transfer (HT) flag for channel x + bitOffset: 2 + bitWidth: 1 + TCIF0: + description: Transfer complete (TC) flag for channel x + bitOffset: 1 + bitWidth: 1 + GIF0: + description: Global interrupt flag for channel x + bitOffset: 0 + bitWidth: 1 + IFCR: + description: Interrupt flag clear register + addressOffset: 0x04 + access: write-only + resetValue: 0x00000000 + fields: + CTEIF7: + description: Transfer error (TE) flag clear for channel x + bitOffset: 31 + bitWidth: 1 + CHTIF7: + description: Half transfer (HT) flag clear for channel x + bitOffset: 30 + bitWidth: 1 + CTCIF7: + description: Transfer complete (TC) flag clear for channel x + bitOffset: 29 + bitWidth: 1 + CGIF7: + description: Global interrupt flag clear for channel x + bitOffset: 28 + bitWidth: 1 + CTEIF6: + description: Transfer error (TE) flag clear for channel x + bitOffset: 27 + bitWidth: 1 + CHTIF6: + description: Half transfer (HT) flag clear for channel x + bitOffset: 26 + bitWidth: 1 + CTCIF6: + description: Transfer complete (TC) flag clear for channel x + bitOffset: 25 + bitWidth: 1 + CGIF6: + description: Global interrupt flag clear for channel x + bitOffset: 24 + bitWidth: 1 + CTEIF5: + description: Transfer error (TE) flag clear for channel x + bitOffset: 23 + bitWidth: 1 + CHTIF5: + description: Half transfer (HT) flag clear for channel x + bitOffset: 22 + bitWidth: 1 + CTCIF5: + description: Transfer complete (TC) flag clear for channel x + bitOffset: 21 + bitWidth: 1 + CGIF5: + description: Global interrupt flag clear for channel x + bitOffset: 20 + bitWidth: 1 + CTEIF4: + description: Transfer error (TE) flag clear for channel x + bitOffset: 19 + bitWidth: 1 + CHTIF4: + description: Half transfer (HT) flag clear for channel x + bitOffset: 18 + bitWidth: 1 + CTCIF4: + description: Transfer complete (TC) flag clear for channel x + bitOffset: 17 + bitWidth: 1 + CGIF4: + description: Global interrupt flag clear for channel x + bitOffset: 16 + bitWidth: 1 + CTEIF3: + description: Transfer error (TE) flag clear for channel x + bitOffset: 15 + bitWidth: 1 + CHTIF3: + description: Half transfer (HT) flag clear for channel x + bitOffset: 14 + bitWidth: 1 + CTCIF3: + description: Transfer complete (TC) flag clear for channel x + bitOffset: 13 + bitWidth: 1 + CGIF3: + description: Global interrupt flag clear for channel x + bitOffset: 12 + bitWidth: 1 + CTEIF2: + description: Transfer error (TE) flag clear for channel x + bitOffset: 11 + bitWidth: 1 + CHTIF2: + description: Half transfer (HT) flag clear for channel x + bitOffset: 10 + bitWidth: 1 + CTCIF2: + description: Transfer complete (TC) flag clear for channel x + bitOffset: 9 + bitWidth: 1 + CGIF2: + description: Global interrupt flag clear for channel x + bitOffset: 8 + bitWidth: 1 + CTEIF1: + description: Transfer error (TE) flag clear for channel x + bitOffset: 7 + bitWidth: 1 + CHTIF1: + description: Half transfer (HT) flag clear for channel x + bitOffset: 6 + bitWidth: 1 + CTCIF1: + description: Transfer complete (TC) flag clear for channel x + bitOffset: 5 + bitWidth: 1 + CGIF1: + description: Global interrupt flag clear for channel x + bitOffset: 4 + bitWidth: 1 + CTEIF0: + description: Transfer error (TE) flag clear for channel x + bitOffset: 3 + bitWidth: 1 + CHTIF0: + description: Half transfer (HT) flag clear for channel x + bitOffset: 2 + bitWidth: 1 + CTCIF0: + description: Transfer complete (TC) flag clear for channel x + bitOffset: 1 + bitWidth: 1 + CGIF0: + description: Global interrupt flag clear for channel x + bitOffset: 0 + bitWidth: 1 + CCR0: + description: Channel x configuration register + addressOffset: 0x08 + access: read-write + resetValue: 0x00000000 + fields: + CT: + description: Current target memory of DMA transfer in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + MEM2MEM: + description: Memory-to-memory mode + bitOffset: 14 + bitWidth: 1 + PL: + description: Priority level + bitOffset: 12 + bitWidth: 2 + MSIZE: + description: Memory size + bitOffset: 10 + bitWidth: 2 + PSIZE: + description: Peripheral size + bitOffset: 8 + bitWidth: 2 + MINC: + description: Memory increment mode + bitOffset: 7 + bitWidth: 1 + PINC: + description: Peripheral increment mode + bitOffset: 6 + bitWidth: 1 + CIRC: + description: Circular mode + bitOffset: 5 + bitWidth: 1 + DIR: + description: Data transfer direction + bitOffset: 4 + bitWidth: 1 + TEIE: + description: Transfer error interrupt enable + bitOffset: 3 + bitWidth: 1 + HTIE: + description: Half transfer error interrupt enable + bitOffset: 2 + bitWidth: 1 + TCIE: + description: Transfer complete interrupt enable + bitOffset: 1 + bitWidth: 1 + EN: + description: Channel enable + bitOffset: 1 + bitWidth: 1 + CCR1: + description: Channel x configuration register + addressOffset: 0x1C + access: read-write + resetValue: 0x00000000 + fields: + CT: + description: Current target memory of DMA transfer in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + MEM2MEM: + description: Memory-to-memory mode + bitOffset: 14 + bitWidth: 1 + PL: + description: Priority level + bitOffset: 12 + bitWidth: 2 + MSIZE: + description: Memory size + bitOffset: 10 + bitWidth: 2 + PSIZE: + description: Peripheral size + bitOffset: 8 + bitWidth: 2 + MINC: + description: Memory increment mode + bitOffset: 7 + bitWidth: 1 + PINC: + description: Peripheral increment mode + bitOffset: 6 + bitWidth: 1 + CIRC: + description: Circular mode + bitOffset: 5 + bitWidth: 1 + DIR: + description: Data transfer direction + bitOffset: 4 + bitWidth: 1 + TEIE: + description: Transfer error interrupt enable + bitOffset: 3 + bitWidth: 1 + HTIE: + description: Half transfer error interrupt enable + bitOffset: 2 + bitWidth: 1 + TCIE: + description: Transfer complete interrupt enable + bitOffset: 1 + bitWidth: 1 + EN: + description: Channel enable + bitOffset: 1 + bitWidth: 1 + CCR2: + description: Channel x configuration register + addressOffset: 0x30 + access: read-write + resetValue: 0x00000000 + fields: + CT: + description: Current target memory of DMA transfer in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + MEM2MEM: + description: Memory-to-memory mode + bitOffset: 14 + bitWidth: 1 + PL: + description: Priority level + bitOffset: 12 + bitWidth: 2 + MSIZE: + description: Memory size + bitOffset: 10 + bitWidth: 2 + PSIZE: + description: Peripheral size + bitOffset: 8 + bitWidth: 2 + MINC: + description: Memory increment mode + bitOffset: 7 + bitWidth: 1 + PINC: + description: Peripheral increment mode + bitOffset: 6 + bitWidth: 1 + CIRC: + description: Circular mode + bitOffset: 5 + bitWidth: 1 + DIR: + description: Data transfer direction + bitOffset: 4 + bitWidth: 1 + TEIE: + description: Transfer error interrupt enable + bitOffset: 3 + bitWidth: 1 + HTIE: + description: Half transfer error interrupt enable + bitOffset: 2 + bitWidth: 1 + TCIE: + description: Transfer complete interrupt enable + bitOffset: 1 + bitWidth: 1 + EN: + description: Channel enable + bitOffset: 1 + bitWidth: 1 + CCR3: + description: Channel x configuration register + addressOffset: 0x44 + access: read-write + resetValue: 0x00000000 + fields: + CT: + description: Current target memory of DMA transfer in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + MEM2MEM: + description: Memory-to-memory mode + bitOffset: 14 + bitWidth: 1 + PL: + description: Priority level + bitOffset: 12 + bitWidth: 2 + MSIZE: + description: Memory size + bitOffset: 10 + bitWidth: 2 + PSIZE: + description: Peripheral size + bitOffset: 8 + bitWidth: 2 + MINC: + description: Memory increment mode + bitOffset: 7 + bitWidth: 1 + PINC: + description: Peripheral increment mode + bitOffset: 6 + bitWidth: 1 + CIRC: + description: Circular mode + bitOffset: 5 + bitWidth: 1 + DIR: + description: Data transfer direction + bitOffset: 4 + bitWidth: 1 + TEIE: + description: Transfer error interrupt enable + bitOffset: 3 + bitWidth: 1 + HTIE: + description: Half transfer error interrupt enable + bitOffset: 2 + bitWidth: 1 + TCIE: + description: Transfer complete interrupt enable + bitOffset: 1 + bitWidth: 1 + EN: + description: Channel enable + bitOffset: 1 + bitWidth: 1 + CCR4: + description: Channel x configuration register + addressOffset: 0x58 + access: read-write + resetValue: 0x00000000 + fields: + CT: + description: Current target memory of DMA transfer in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + MEM2MEM: + description: Memory-to-memory mode + bitOffset: 14 + bitWidth: 1 + PL: + description: Priority level + bitOffset: 12 + bitWidth: 2 + MSIZE: + description: Memory size + bitOffset: 10 + bitWidth: 2 + PSIZE: + description: Peripheral size + bitOffset: 8 + bitWidth: 2 + MINC: + description: Memory increment mode + bitOffset: 7 + bitWidth: 1 + PINC: + description: Peripheral increment mode + bitOffset: 6 + bitWidth: 1 + CIRC: + description: Circular mode + bitOffset: 5 + bitWidth: 1 + DIR: + description: Data transfer direction + bitOffset: 4 + bitWidth: 1 + TEIE: + description: Transfer error interrupt enable + bitOffset: 3 + bitWidth: 1 + HTIE: + description: Half transfer error interrupt enable + bitOffset: 2 + bitWidth: 1 + TCIE: + description: Transfer complete interrupt enable + bitOffset: 1 + bitWidth: 1 + EN: + description: Channel enable + bitOffset: 1 + bitWidth: 1 + CCR5: + description: Channel x configuration register + addressOffset: 0x6C + access: read-write + resetValue: 0x00000000 + fields: + CT: + description: Current target memory of DMA transfer in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + MEM2MEM: + description: Memory-to-memory mode + bitOffset: 14 + bitWidth: 1 + PL: + description: Priority level + bitOffset: 12 + bitWidth: 2 + MSIZE: + description: Memory size + bitOffset: 10 + bitWidth: 2 + PSIZE: + description: Peripheral size + bitOffset: 8 + bitWidth: 2 + MINC: + description: Memory increment mode + bitOffset: 7 + bitWidth: 1 + PINC: + description: Peripheral increment mode + bitOffset: 6 + bitWidth: 1 + CIRC: + description: Circular mode + bitOffset: 5 + bitWidth: 1 + DIR: + description: Data transfer direction + bitOffset: 4 + bitWidth: 1 + TEIE: + description: Transfer error interrupt enable + bitOffset: 3 + bitWidth: 1 + HTIE: + description: Half transfer error interrupt enable + bitOffset: 2 + bitWidth: 1 + TCIE: + description: Transfer complete interrupt enable + bitOffset: 1 + bitWidth: 1 + EN: + description: Channel enable + bitOffset: 1 + bitWidth: 1 + CCR6: + description: Channel x configuration register + addressOffset: 0x80 + access: read-write + resetValue: 0x00000000 + fields: + CT: + description: Current target memory of DMA transfer in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + MEM2MEM: + description: Memory-to-memory mode + bitOffset: 14 + bitWidth: 1 + PL: + description: Priority level + bitOffset: 12 + bitWidth: 2 + MSIZE: + description: Memory size + bitOffset: 10 + bitWidth: 2 + PSIZE: + description: Peripheral size + bitOffset: 8 + bitWidth: 2 + MINC: + description: Memory increment mode + bitOffset: 7 + bitWidth: 1 + PINC: + description: Peripheral increment mode + bitOffset: 6 + bitWidth: 1 + CIRC: + description: Circular mode + bitOffset: 5 + bitWidth: 1 + DIR: + description: Data transfer direction + bitOffset: 4 + bitWidth: 1 + TEIE: + description: Transfer error interrupt enable + bitOffset: 3 + bitWidth: 1 + HTIE: + description: Half transfer error interrupt enable + bitOffset: 2 + bitWidth: 1 + TCIE: + description: Transfer complete interrupt enable + bitOffset: 1 + bitWidth: 1 + EN: + description: Channel enable + bitOffset: 1 + bitWidth: 1 + CCR7: + description: Channel x configuration register + addressOffset: 0x94 + access: read-write + resetValue: 0x00000000 + fields: + CT: + description: Current target memory of DMA transfer in double-buffer mode + bitOffset: 16 + bitWidth: 1 + DBM: + description: Double-buffer mode + bitOffset: 15 + bitWidth: 1 + MEM2MEM: + description: Memory-to-memory mode + bitOffset: 14 + bitWidth: 1 + PL: + description: Priority level + bitOffset: 12 + bitWidth: 2 + MSIZE: + description: Memory size + bitOffset: 10 + bitWidth: 2 + PSIZE: + description: Peripheral size + bitOffset: 8 + bitWidth: 2 + MINC: + description: Memory increment mode + bitOffset: 7 + bitWidth: 1 + PINC: + description: Peripheral increment mode + bitOffset: 6 + bitWidth: 1 + CIRC: + description: Circular mode + bitOffset: 5 + bitWidth: 1 + DIR: + description: Data transfer direction + bitOffset: 4 + bitWidth: 1 + TEIE: + description: Transfer error interrupt enable + bitOffset: 3 + bitWidth: 1 + HTIE: + description: Half transfer error interrupt enable + bitOffset: 2 + bitWidth: 1 + TCIE: + description: Transfer complete interrupt enable + bitOffset: 1 + bitWidth: 1 + EN: + description: Channel enable + bitOffset: 1 + bitWidth: 1 + CNDTR0: + description: Channel x number of data to transfer register + addressOffset: 0x0C + access: read-write + resetValue: 0x00000000 + fields: + NDT: + description: Number of data to transfer + bitOffset: 0 + bitWidth: 16 + CNDTR1: + description: Channel x number of data to transfer register + addressOffset: 0x20 + access: read-write + resetValue: 0x00000000 + fields: + NDT: + description: Number of data to transfer + bitOffset: 0 + bitWidth: 16 + CNDTR2: + description: Channel x number of data to transfer register + addressOffset: 0x34 + access: read-write + resetValue: 0x00000000 + fields: + NDT: + description: Number of data to transfer + bitOffset: 0 + bitWidth: 16 + CNDTR3: + description: Channel x number of data to transfer register + addressOffset: 0x48 + access: read-write + resetValue: 0x00000000 + fields: + NDT: + description: Number of data to transfer + bitOffset: 0 + bitWidth: 16 + CNDTR4: + description: Channel x number of data to transfer register + addressOffset: 0x5C + access: read-write + resetValue: 0x00000000 + fields: + NDT: + description: Number of data to transfer + bitOffset: 0 + bitWidth: 16 + CNDTR5: + description: Channel x number of data to transfer register + addressOffset: 0x70 + access: read-write + resetValue: 0x00000000 + fields: + NDT: + description: Number of data to transfer + bitOffset: 0 + bitWidth: 16 + CNDTR6: + description: Channel x number of data to transfer register + addressOffset: 0x84 + access: read-write + resetValue: 0x00000000 + fields: + NDT: + description: Number of data to transfer + bitOffset: 0 + bitWidth: 16 + CNDTR7: + description: Channel x number of data to transfer register + addressOffset: 0x98 + access: read-write + resetValue: 0x00000000 + fields: + NDT: + description: Number of data to transfer + bitOffset: 0 + bitWidth: 16 + CPAR0: + description: Channel x peripheral address register + addressOffset: 0x10 + access: read-write + resetValue: 0x00000000 + fields: + PA: + description: Peripheral address + bitOffset: 0 + bitWidth: 32 + CPAR1: + description: Channel x peripheral address register + addressOffset: 0x24 + access: read-write + resetValue: 0x00000000 + fields: + PA: + description: Peripheral address + bitOffset: 0 + bitWidth: 32 + CPAR2: + description: Channel x peripheral address register + addressOffset: 0x38 + access: read-write + resetValue: 0x00000000 + fields: + PA: + description: Peripheral address + bitOffset: 0 + bitWidth: 32 + CPAR3: + description: Channel x peripheral address register + addressOffset: 0x4C + access: read-write + resetValue: 0x00000000 + fields: + PA: + description: Peripheral address + bitOffset: 0 + bitWidth: 32 + CPAR4: + description: Channel x peripheral address register + addressOffset: 0x60 + access: read-write + resetValue: 0x00000000 + fields: + PA: + description: Peripheral address + bitOffset: 0 + bitWidth: 32 + CPAR5: + description: Channel x peripheral address register + addressOffset: 0x74 + access: read-write + resetValue: 0x00000000 + fields: + PA: + description: Peripheral address + bitOffset: 0 + bitWidth: 32 + CPAR6: + description: Channel x peripheral address register + addressOffset: 0x88 + access: read-write + resetValue: 0x00000000 + fields: + PA: + description: Peripheral address + bitOffset: 0 + bitWidth: 32 + CPAR7: + description: Channel x peripheral address register + addressOffset: 0x9C + access: read-write + resetValue: 0x00000000 + fields: + PA: + description: Peripheral address + bitOffset: 0 + bitWidth: 32 + CM0AR0: + description: Channel x memory 0 address register + addressOffset: 0x14 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM0AR1: + description: Channel x memory 0 address register + addressOffset: 0x28 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM0AR2: + description: Channel x memory 0 address register + addressOffset: 0x3C + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM0AR3: + description: Channel x memory 0 address register + addressOffset: 0x50 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM0AR4: + description: Channel x memory 0 address register + addressOffset: 0x64 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM0AR5: + description: Channel x memory 0 address register + addressOffset: 0x78 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM0AR6: + description: Channel x memory 0 address register + addressOffset: 0x8C + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM0AR7: + description: Channel x memory 0 address register + addressOffset: 0xA0 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR0: + description: Channel x memory 1 address register + addressOffset: 0x18 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR1: + description: Channel x memory 1 address register + addressOffset: 0x2C + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR2: + description: Channel x memory 1 address register + addressOffset: 0x40 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR3: + description: Channel x memory 1 address register + addressOffset: 0x54 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR4: + description: Channel x memory 1 address register + addressOffset: 0x68 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR5: + description: Channel x memory 1 address register + addressOffset: 0x7C + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR6: + description: Channel x memory 1 address register + addressOffset: 0x90 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + CM1AR7: + description: Channel x memory 1 address register + addressOffset: 0xA4 + access: read-write + resetValue: 0x00000000 + fields: + MA: + description: Memory address + bitOffset: 0 + bitWidth: 32 + _cluster: + "CH%s": + description: "Channel cluster: CCR?, CNDTR?, CPAR?, CM0AR? and CM1AR registers?" + "CCR?": + name: CR + "CNDTR?": + name: NDTR + "CPAR?": + name: PAR + "CM0AR?": + name: M0AR + "CM1AR?": + name: M1AR diff --git a/devices/common_patches/h7_common_dualcore.yaml b/devices/common_patches/h7_common_dualcore.yaml index 2d8be4e14..383ec77e4 100644 --- a/devices/common_patches/h7_common_dualcore.yaml +++ b/devices/common_patches/h7_common_dualcore.yaml @@ -748,16 +748,3 @@ _copy: from: TIM2 TIM14: from: TIM2 - -SYSCFG: - _add: - PWRCR: - description: SYSCFG Power Control Register - addressOffset: 0x2C - access: read-write - resetValue: 0x00000000 - fields: - ODEN: - description: Overdrive enable, this bit allows to activate the LDO regulator overdrive mode. This bit must be written only in VOS1 voltage scaling mode - bitOffset: 0 - bitWidth: 1 diff --git a/devices/common_patches/h7_common_highmemory.yaml b/devices/common_patches/h7_common_highmemory.yaml index e16b6351a..707a6d740 100644 --- a/devices/common_patches/h7_common_highmemory.yaml +++ b/devices/common_patches/h7_common_highmemory.yaml @@ -12,6 +12,8 @@ _modify: name: FDCAN2 DAC: name: DAC1 + OCTOSPI1_CONTROL_REGISTER: + name: OCTOSPI1 # The SVD is just quite different to the RM for all these registers. # We'll go with the RM convention even though it is inconsistent too. @@ -314,6 +316,10 @@ AXI: _delete: - DMA2 + - UART4 + - UART5 + - UART7 + - UART8 - USART9 - USART10 @@ -346,16 +352,38 @@ _add: DMA2_STR7: value: 70 description: DMA2 Stream7 - UART9: + UART4: derivedFrom: USART1 - baseAddress: 0x40018000 + baseAddress: 0x40004C00 + interrupts: + UART4: + description: UART4 global interrupt + value: 52 + UART5: + derivedFrom: USART1 + baseAddress: 0x40005000 + interrupts: + UART5: + description: UART5 global interrupt + value: 53 + UART7: + derivedFrom: USART1 + baseAddress: 0x40007800 interrupts: UART7: description: UART7 global interrupt value: 82 + UART8: + derivedFrom: USART1 + baseAddress: 0x40007C00 + interrupts: UART8: description: UART8 global interrupt value: 83 + UART9: + derivedFrom: USART1 + baseAddress: 0x40018000 + interrupts: UART9: description: UART9 global interrupt value: 140 @@ -466,96 +494,9 @@ RCC: bitOffset: 0 bitWidth: 1 - CDCCIPR: - _delete: - - "QSPI*" - _add: - OCTOSPISEL: - description: "OCTOSPI kernel clock source selection" - bitOffset: 4 - bitWidth: 2 - _modify: - CKPERSRC: - name: CKPERSEL - SDMMCSRC: - name: SDMMCSEL - FMCSRC: - name: FMCSEL - CDCCIP1R: - _delete: - - "SAI23*" - _add: - SAI2ASEL: - description: "SAI2 kernel clock source A source selection" - bitOffset: 6 - bitWidth: 3 - SAI2BSEL: - description: "SAI2 kernel clock source B source selection" - bitOffset: 9 - bitWidth: 3 - _modify: - SWPSRC: - name: SWPSEL - FDCANSRC: - name: FDCANSEL - DFSDM1SRC: - name: DFSDM1SEL - SPDIFSRC: - name: SPDIFRXSEL - SPI45SRC: - name: SPI45SEL - SPI123SRC: - name: SPI123SEL - SAI1SRC: - name: SAI1SEL - CDCCIP2R: - _modify: - LPTIM1SRC: - name: LPTIM1SEL - CECSRC: - name: CECSEL - USBSRC: - name: USBSEL - I2C123SRC: - name: I2C123SEL - RNGSRC: - name: RNGSEL - USART16SRC: - name: USART16910SEL - description: "USART1, 6, 9 and 10 kernel clock source selection" - USART234578SRC: - name: USART234578SEL - SRDCCIPR: - _delete: - - "SAI4*" - _add: - DFSDM2SEL: - description: "DFSDM2 kernel clock source selection" - bitOffset: 27 - bitWidth: 1 - _modify: - SPI6SRC: - name: SPI6SEL - ADCSRC: - name: ADCSEL - LPTIM345SRC: - name: LPTIM3SEL # LPTIM3 only - LPTIM2SRC: - name: LPTIM2SEL - I2C4SRC: - name: I2C4SEL - LPUART1SRC: - name: LPUART1SEL - - D3CFGR: - _delete: "*" - _add: - D3PPRE: - description: D3 domain APB4 prescaler - bitOffset: 4 - bitWidth: 3 - CR: + _clear: + "*" _modify: RC48ON: name: HSI48ON @@ -566,12 +507,16 @@ RCC: RC48CAL: name: HSI48CAL CFGR: + _clear: + "*" _modify: MCO1SEL: name: MCO1 MCO2SEL: name: MCO2 CIER: + _clear: + "*" _modify: RC48RDYIE: name: HSI48RDYIE @@ -580,16 +525,23 @@ RCC: RC48RDYF: name: HSI48RDYF CICR: + _clear: + "*" _modify: RC48RDYC: name: HSI48RDYC BDCR: + _clear: + "*" _modify: - VSWRST: - name: BDRST RTCSRC: name: RTCSEL + CSR: + _clear: + "*" PLL2DIVR: + _clear: + "*" _modify: DIVR1: name: DIVR2 @@ -599,6 +551,15 @@ RCC: name: DIVP2 DIVN1: name: DIVN2 + "A?B?RSTR,A?B??RSTR": + _clear: + "*RST" + "A?B?ENR,A?B??ENR,C1_A?B?ENR,C1_A?B??ENR": + _clear: + "*EN" + "A?B?LPENR,A?B??LPENR,C1_A?B?LPENR,C1_A?B??LPENR": + _clear: + "*LPEN" APB1LRSTR: _modify: USART7RST: @@ -670,6 +631,27 @@ RCC: FLITFLPEN: name: FLASHPREN description: "Flash interface clock enable during csleep mode" + RSR: + _clear: + "*RSTF" + PLLCKSELR,PLLCFGR,PLL1DIVR,CDCFGR?,CDCCIPR,CDCCIP?R: + _clear: + "*" + SRDAMR,SRDCCIPR: + _clear: + "*" + + +SYSCFG: + _modify: + SYSCFG_BRK_LOCKUPR: + name: CFGR + addressOffset: 0x18 + PMCR: + _delete: # Functionality not available on these parts + - BOOSTE + - EPIS + TIM1,TIM8: DMAR: @@ -752,22 +734,6 @@ PWR: - PWR_ _delete: _interrupts: WWDG1_RST # Doesn't exist at all on these parts - CR3: - # Annoyingly RM0455 names these fields differently to RM0399 whilst - # they have the same function - _add: - SMPSEXTRDY: - description: SMPS step-down converter external supply ready - bitOffset: 16 - bitWidth: 1 - SMPSLEVEL: - description: Step-down converter voltage output level selection - bitOffset: 4 - bitWidth: 2 - SMPSEXTHP: - description: Step-down converter forced ON and in High Power MR mode - bitOffset: 3 - bitWidth: 1 RAMECC: _add: @@ -827,7 +793,26 @@ IWDG: _strip: - IWDG_ -"USART*": +USART2: + _add: + _interrupts: + USART2: + description: USART2 global interrupt + value: 38 +USART3: + _add: + _interrupts: + USART3: + description: USART3 global interrupt + value: 39 +USART6: + _add: + _interrupts: + USART6: + description: USART6 global interrupt + value: 71 + +"USART*,UART*": BRR: _modify: BRR_4_15: @@ -835,6 +820,26 @@ IWDG: BRR_0_3: name: BRR0 _merge: ["BRR*"] + CR1: + _merge: + - "DEAT*" + - "DEDT*" + CR2: + _modify: + TAINV: + name: DATAINV + _merge: + - "ABRMOD*" + +"UART*": + CR2: + _modify: + ADD0_3: + name: ADD0R + ADD4_7: + name: ADD4R + _merge: + - "ADD*R" # TIM3, TIM4, TIM12, TIM13, TIM14 are 16-bit, whilst TIM2 is 32-bit _copy: diff --git a/devices/common_patches/h7_common_singlecore.yaml b/devices/common_patches/h7_common_singlecore.yaml index 788a5cace..a058e0f23 100644 --- a/devices/common_patches/h7_common_singlecore.yaml +++ b/devices/common_patches/h7_common_singlecore.yaml @@ -351,24 +351,6 @@ DMA1: description: DMA1 Stream6 # DMA1_STR7 is correct -Ethernet_DMA: - DMAMR: - _modify: - INTM: - bitWidth: 2 - PR: - access: read-write - TXPR: - access: read-write - DA: - access: read-write - DMASBMR: - _modify: - RB: - access: read-write - MB: - access: read-write - RCC: _modify: CIFR: diff --git a/devices/common_patches/h7_dbgmcu.yaml b/devices/common_patches/h7_dbgmcu.yaml index 6f5cf93cd..cc443ed41 100644 --- a/devices/common_patches/h7_dbgmcu.yaml +++ b/devices/common_patches/h7_dbgmcu.yaml @@ -1,192 +1,11 @@ -# Add H7 DBGMCU peripheral. From RM0433 rev 7 +# Patches for H7 DBGMCU periperal -_add: - DBGMCU: - description: Debug support - groupName: DBG - baseAddress: 0x5C001000 - addressBlock: - offset: 0x000 - size: 0x100 - usage: registers - registers: - IDC: - description: Identity code - addressOffset: 0x0 - access: read-only - resetValue: 0x10006480 - fields: - REV_ID: - description: Revision ID - bitOffset: 16 - bitWidth: 16 - DEV_ID: - description: Device ID - bitOffset: 0 - bitWidth: 12 - CR: - description: Configuration register - addressOffset: 0x004 - access: read-write - resetValue: 0x00000000 - fields: - TRGOEN: - description: External trigger output enable - bitOffset: 28 - bitWidth: 1 - D3DBGCKEN: - description: D3 debug clock enable enable - bitOffset: 22 - bitWidth: 1 - D1DBGCKEN: - description: D1 debug clock enable enable - bitOffset: 21 - bitWidth: 1 - TRACECLKEN: - description: Trace clock enable enable - bitOffset: 20 - bitWidth: 1 - DBGSTBY_D1: - description: Allow debug in D1 Standby mode - bitOffset: 2 - bitWidth: 1 - DBGSTOP_D1: - description: Allow debug in D1 Stop mode - bitOffset: 1 - bitWidth: 1 - DBGSLEEP_D1: - description: Allow debug in D1 Sleep mode - bitOffset: 0 - bitWidth: 1 - APB3FZ1: - description: APB3 peripheral freeze register - addressOffset: 0x034 - access: read-write - resetValue: 0x00000000 - fields: - WWDG1: - description: WWDG1 stop in debug mode - bitOffset: 6 - bitWidth: 1 - APB1LFZ1: - description: APB1L peripheral freeze register - addressOffset: 0x03C - access: read-write - resetValue: 0x00000000 - fields: - I2C3: - description: I2C3 SMBUS timeout stop in debug mode - bitOffset: 23 - bitWidth: 1 - I2C2: - description: I2C2 SMBUS timeout stop in debug mode - bitOffset: 22 - bitWidth: 1 - I2C1: - description: I2C1 SMBUS timeout stop in debug mode - bitOffset: 21 - bitWidth: 1 - LPTIM1: - description: LPTIM1 stop in debug mode - bitOffset: 9 - bitWidth: 1 - TIM14: - description: TIM14 stop in debug mode - bitOffset: 8 - bitWidth: 1 - TIM13: - description: TIM13 stop in debug mode - bitOffset: 7 - bitWidth: 1 - TIM12: - description: TIM12 stop in debug mode - bitOffset: 6 - bitWidth: 1 - TIM7: - description: TIM7 stop in debug mode - bitOffset: 5 - bitWidth: 1 - TIM6: - description: TIM6 stop in debug mode - bitOffset: 4 - bitWidth: 1 - TIM5: - description: TIM5 stop in debug mode - bitOffset: 3 - bitWidth: 1 - TIM4: - description: TIM4 stop in debug mode - bitOffset: 2 - bitWidth: 1 - TIM3: - description: TIM3 stop in debug mode - bitOffset: 1 - bitWidth: 1 - TIM2: - description: TIM2 stop in debug mode - bitOffset: 0 - bitWidth: 1 - APB2FZ1: - description: APB2 peripheral freeze register - addressOffset: 0x04C - access: read-write - resetValue: 0x00000000 - fields: - HRTIM: - description: HRTIM stop in debug mode - bitOffset: 29 - bitWidth: 1 - TIM17: - description: TIM17 stop in debug mode - bitOffset: 18 - bitWidth: 1 - TIM16: - description: TIM16 stop in debug mode - bitOffset: 17 - bitWidth: 1 - TIM15: - description: TIM15 stop in debug mode - bitOffset: 16 - bitWidth: 1 - TIM8: - description: TIM8 stop in debug mode - bitOffset: 1 - bitWidth: 1 - TIM1: - description: TIM1 stop in debug mode - bitOffset: 0 - bitWidth: 1 - APB4FZ1: - description: APB4 peripheral freeze register - addressOffset: 0x054 - access: read-write - resetValue: 0x00000000 - fields: - IWDG1: - description: Independent watchdog for D1 stop in debug mode - bitOffset: 18 - bitWidth: 1 - RTC: - description: RTC stop in debug mode - bitOffset: 16 - bitWidth: 1 - LPTIM5: - description: LPTIM5 stop in debug mode - bitOffset: 12 - bitWidth: 1 - LPTIM4: - description: LPTIM4 stop in debug mode - bitOffset: 11 - bitWidth: 1 - LPTIM3: - description: LPTIM3 stop in debug mode - bitOffset: 10 - bitWidth: 1 - LPTIM2: - description: LPTIM2 stop in debug mode - bitOffset: 9 - bitWidth: 1 - I2C4: - description: I2C4 SMBUS timeout stop in debug mode - bitOffset: 7 - bitWidth: 1 +# Remove registers not present in RM0433 Rev 7 +DBGMCU: + CR: + _delete: + - DBGSTBY_D2 + - DBGSTOP_D2 + - DBGSLEEP_D2 + - DBGSTOP_D3 + - DBGSTBY_D3 diff --git a/devices/common_patches/h7_dbgmcu_dualcore.yaml b/devices/common_patches/h7_dbgmcu_dualcore.yaml index faf19ba22..4f752c5d3 100644 --- a/devices/common_patches/h7_dbgmcu_dualcore.yaml +++ b/devices/common_patches/h7_dbgmcu_dualcore.yaml @@ -1,170 +1,8 @@ -# Add dualcore parts of DBGMCU periperal. From RM0399 rev 2 +# Patches for H7 DBGMCU periperal +# Remove registers not present in RM0399 Rev 3 DBGMCU: CR: - _add: - DBGSTBY_D2: - description: Allow debug in D2 Standby mode - bitOffset: 5 - bitWidth: 1 - DBGSTOP_D2: - description: Allow debug in D2 Stop mode - bitOffset: 4 - bitWidth: 1 - DBGSLEEP_D2: - description: Allow debug in D2 Sleep mode - bitOffset: 3 - bitWidth: 1 - APB4FZ1: - _add: - IWDG2: - description: Independent watchdog for D2 stop when Cortex-M7 in debug mode - bitOffset: 19 - bitWidth: 1 - APB1LFZ1: - _add: - WWDG2: - description: WWDG2 stop when Cortex-M7 in debug mode - bitOffset: 11 - bitWidth: 1 - _add: - APB3FZ2: - description: APB3 peripheral freeze register CPU2 - addressOffset: 0x038 - access: read-write - resetValue: 0x00000000 - fields: - WWDG1: - description: WWDG1 stop when Cortex-M4 in debug mode - bitOffset: 6 - bitWidth: 1 - APB1LFZ2: - description: APB1L peripheral freeze register CPU2 - addressOffset: 0x040 - access: read-write - resetValue: 0x00000000 - fields: - I2C3: - description: I2C3 SMBUS timeout stop when Cortex-M4 in debug mode - bitOffset: 23 - bitWidth: 1 - I2C2: - description: I2C2 SMBUS timeout stop when Cortex-M4 in debug mode - bitOffset: 22 - bitWidth: 1 - I2C1: - description: I2C1 SMBUS timeout stop when Cortex-M4 in debug mode - bitOffset: 21 - bitWidth: 1 - WWDG2: - description: WWDG2 stop in when Cortex-M4 when Cortex-M4 in debug mode - bitOffset: 11 - bitWidth: 1 - LPTIM1: - description: LPTIM1 stop when Cortex-M4 in debug mode - bitOffset: 9 - bitWidth: 1 - TIM14: - description: TIM14 stop when Cortex-M4 in debug mode - bitOffset: 8 - bitWidth: 1 - TIM13: - description: TIM13 stop when Cortex-M4 in debug mode - bitOffset: 7 - bitWidth: 1 - TIM12: - description: TIM12 stop when Cortex-M4 in debug mode - bitOffset: 6 - bitWidth: 1 - TIM7: - description: TIM7 stop when Cortex-M4 in debug mode - bitOffset: 5 - bitWidth: 1 - TIM6: - description: TIM6 stop when Cortex-M4 in debug mode - bitOffset: 4 - bitWidth: 1 - TIM5: - description: TIM5 stop when Cortex-M4 in debug mode - bitOffset: 3 - bitWidth: 1 - TIM4: - description: TIM4 stop when Cortex-M4 in debug mode - bitOffset: 2 - bitWidth: 1 - TIM3: - description: TIM3 stop when Cortex-M4 in debug mode - bitOffset: 1 - bitWidth: 1 - TIM2: - description: TIM2 stop when Cortex-M4 in debug mode - bitOffset: 0 - bitWidth: 1 - APB2FZ2: - description: APB2 peripheral freeze register CPU2 - addressOffset: 0x048 - access: read-write - resetValue: 0x00000000 - fields: - HRTIM: - description: HRTIM stop when Cortex-M4 in debug mode - bitOffset: 29 - bitWidth: 1 - TIM17: - description: TIM17 stop when Cortex-M4 in debug mode - bitOffset: 18 - bitWidth: 1 - TIM16: - description: TIM16 stop when Cortex-M4 in debug mode - bitOffset: 17 - bitWidth: 1 - TIM15: - description: TIM15 stop when Cortex-M4 in debug mode - bitOffset: 16 - bitWidth: 1 - TIM8: - description: TIM8 stop when Cortex-M4 in debug mode - bitOffset: 1 - bitWidth: 1 - TIM1: - description: TIM1 stop when Cortex-M4 in debug mode - bitOffset: 0 - bitWidth: 1 - APB4FZ2: - description: APB4 peripheral freeze register CPU2 - addressOffset: 0x058 - access: read-write - resetValue: 0x00000000 - fields: - WDGLSD2: - description: LS watchdog for D2 stop when Cortex-M4 in debug mode - bitOffset: 19 - bitWidth: 1 - WDGLSD1: - description: LS watchdog for D1 stop when Cortex-M4 in debug mode - bitOffset: 18 - bitWidth: 1 - RTC: - description: RTC stop when Cortex-M4 in debug mode - bitOffset: 16 - bitWidth: 1 - LPTIM5: - description: LPTIM5 stop when Cortex-M4 in debug mode - bitOffset: 12 - bitWidth: 1 - LPTIM4: - description: LPTIM4 stop when Cortex-M4 in debug mode - bitOffset: 11 - bitWidth: 1 - LPTIM3: - description: LPTIM3 stop when Cortex-M4 in debug mode - bitOffset: 10 - bitWidth: 1 - LPTIM2: - description: LPTIM2 stop when Cortex-M4 in debug mode - bitOffset: 9 - bitWidth: 1 - I2C4: - description: I2C4 SMBUS timeout stop when Cortex-M4 in debug mode - bitOffset: 7 - bitWidth: 1 + _delete: + - DBGSTOP_D3 + - DBGSTBY_D3 diff --git a/devices/common_patches/h7_dsi.yaml b/devices/common_patches/h7_dsi.yaml index ec5e01f87..b62a6f73f 100644 --- a/devices/common_patches/h7_dsi.yaml +++ b/devices/common_patches/h7_dsi.yaml @@ -1,5 +1,8 @@ # H7 MIPI DSI Host Peripheral +_delete: + - DSIHOST + _add: DSIHOST: description: MIPI DSI Host diff --git a/devices/common_patches/h7_ethernet_dma_mr.yaml b/devices/common_patches/h7_ethernet_dma_mr.yaml new file mode 100644 index 000000000..2ea9ea8ec --- /dev/null +++ b/devices/common_patches/h7_ethernet_dma_mr.yaml @@ -0,0 +1,17 @@ +Ethernet_DMA: + DMAMR: + _modify: + INTM: + bitWidth: 2 + PR: + access: read-write + TXPR: + access: read-write + DA: + access: read-write + DMASBMR: + _modify: + RB: + access: read-write + MB: + access: read-write \ No newline at end of file diff --git a/devices/common_patches/h7_octospi.yaml b/devices/common_patches/h7_octospi.yaml new file mode 100644 index 000000000..a7e06c136 --- /dev/null +++ b/devices/common_patches/h7_octospi.yaml @@ -0,0 +1,34 @@ +# OCTOSPI v1 peripheral on at least H7 + +"OCTOSPI*": + DCR1: + _add: + DLYBYP: + description: Delay block bypass + bitWidth: 1 + bitOffset: 3 + _modify: + MTYP: + bitWidth: 3 + DCR4: + _modify: + REFRESH: + bitWidth: 32 + SR: + _modify: + CTEF: + name: TEF + description: Transfer error flag + CTCF: + name: TCF + description: Transfer complete flag + CSMF: + name: SMF + description: Status match flag + CTOF: + name: TOF + description: Timeout flag + AR: + _modify: + ADRESS: + name: ADDRESS diff --git a/devices/common_patches/h7_rcc_src_sel.yaml b/devices/common_patches/h7_rcc_src_sel.yaml index 6a364d612..b328ea39d 100644 --- a/devices/common_patches/h7_rcc_src_sel.yaml +++ b/devices/common_patches/h7_rcc_src_sel.yaml @@ -1,6 +1,6 @@ # Rename *SRC to *SEL in H7 domain kernel clock configuration registers (DxCCIPR) -# Applies only to RM0433 and RM0399 parts +# Applies only to RM0433, RM0399 and RM0468 parts RCC: D1CCIPR: diff --git a/devices/stm32h735.yaml b/devices/stm32h735.yaml new file mode 100644 index 000000000..4456f541d --- /dev/null +++ b/devices/stm32h735.yaml @@ -0,0 +1,570 @@ +_svd: ../svd/stm32h735.svd + +# Merge the hundreds of individual bit fields into single fields for the +# crypt key/iv registers. +CRYP: + "K[0123][LR]R": + _merge: + - "k*" + "IV[01][LR]R": + _merge: + - "IV*" + +# Fix invalid groupName +_modify: + Flash: + name: FLASH + groupName: FLASH + OctoSPII_O_Manager: + groupName: OctoSPII_O_Manager + DMAMUX3: + name: DMAMUX2 + description: DMAMUX2 + ADC1: + addressBlock: + offset: 0x0 + size: 0x100 + usage: registers + +_add: + # ADC2 + # Slave ADC, shares an interrupt with ADC2 + ADC2: + description: Analog to Digital Converter + derivedFrom: ADC1 + baseAddress: 0x40022100 + addressBlock: + offset: 0x0 + size: 0x100 + usage: registers + + # BDMA block + BDMA: + description: Basic Direct Memory Access + groupName: BDMA + baseAddress: 0x58025400 + addressBlock: + offset: 0x000 + size: 0x400 + usage: registers + registers: + [] + interrupts: + BDMA_CH0: + description: BDMA Channel 0 interrupt + value: 129 + BDMA_CH1: + description: BDMA Channel 1 interrupt + value: 130 + BDMA_CH2: + description: BDMA Channel 2 interrupt + value: 131 + BDMA_CH3: + description: BDMA Channel 3 interrupt + value: 132 + BDMA_CH4: + description: BDMA Channel 4 interrupt + value: 133 + BDMA_CH5: + description: BDMA Channel 5 interrupt + value: 134 + BDMA_CH6: + description: BDMA Channel 6 interrupt + value: 135 + BDMA_CH7: + description: BDMA Channel 7 interrupt + value: 136 + +# PWR block +PWR: + CR3: + _add: + SDEXTHP: + description: SMPS step-down converter forced ON and in High Power MR mode + bitWidth: 1 + bitOffset: 3 + SDLEVEL: + description: SMPS step-down converter voltage output level selection + bitWidth: 2 + bitOffset: 4 + SDEXTRDY: + description: SMPS step-down converter external supply ready + bitWidth: 1 + bitOffset: 16 + WKUPCR: + _delete: + - WKUPC + _add: + WKUPC1: + description: Clear Wakeup pin flag for WKUPC1 + bitWidth: 1 + bitOffset: 0 + WKUPC2: + description: Clear Wakeup pin flag for WKUPC2 + bitWidth: 1 + bitOffset: 1 + WKUPC4: + description: Clear Wakeup pin flag for WKUPC4 + bitWidth: 1 + bitOffset: 3 + WKUPC6: + description: Clear Wakeup pin flag for WKUPC6 + bitWidth: 1 + bitOffset: 5 + WKUPFR: + _delete: + - WKUPF3 + - WKUPF5 + +# SYSCFG block +SYSCFG: + _add: + CFGR: + description: Timer break lockup register + addressOffset: 0x18 + resetValue: 0x00000000 + fields: + PVDL: + description: Programmable voltage detector lockup bit + bitOffset: 2 + bitWidth: 1 + FLASHL: + description: FLASH double error lockup bit + bitOffset: 3 + bitWidth: 1 + CM7L: + description: CPU lockup bit + bitOffset: 6 + bitWidth: 1 + BKRAML: + description: Backup RAM Double error lockup bit + bitOffset: 7 + bitWidth: 1 + SRAM4L: + description: SRAM4 Double error lockup bit + bitOffset: 9 + bitWidth: 1 + SRAM2L: + description: SRAM2 Double error lockup bit + bitOffset: 11 + bitWidth: 1 + SRAM1L: + description: SRAM1 Double error lockup bit + bitOffset: 12 + bitWidth: 1 + DTCML: + description: DTCM-RAM Double error lockup bit + bitOffset: 13 + bitWidth: 1 + ITCML: + description: ITCM-RAM Double error lockup bit + bitOffset: 14 + bitWidth: 1 + AXIRAML: + description: AXISRAM Double error lockup bit + bitOffset: 15 + bitWidth: 1 + ADC2ALT: + description: ADC2 internal input alternate connection + addressOffset: 0x30 + resetValue: 0x00000000 + fields: + ADC2_ROUT1: + description: ADC2 V_INP17 alternate connection + bitOffset: 1 + bitWidth: 1 + ADC2_ROUT0: + description: ADC2 V_INP16 alternate connection + bitOffset: 0 + bitWidth: 1 + UR18: + description: SYSCFG user register 18 + addressOffset: 0x348 + access: read-only + fields: + CPU_FREQ_BOOST: + description: CPU maximum frequency boost + bitOffset: 0 + bitWidth: 1 + _delete: + - UR8 # Only one flash bank + - UR9 + - UR10 + PMCR: + _add: + BOOSTVDDSEL: + description: Analog switch supply voltage selection + bitWidth: 1 + bitOffset: 9 + I2C5FMP: + description: I2C5 Fm+ + bitWidth: 1 + bitOffset: 10 + UR0: + _delete: + - BKS + UR11: + _delete: + - SA_END_2 + UR17: + _add: + TCM_AXI_SHARED_CFG: + description: ITCM-RAM/AXI-SRAM size + bitOffset: 16 + bitWidth: 2 + + +# RCC block +RCC: + _modify: + # Fix reset values for these registers. + # Note that the rename operation to remove C1 happens alongside this + # modification, so we have to use the original names. + C1_APB1LLPENR: + resetValue: "0xE8FFCBFF" + C1_APB4ENR: + resetValue: "0x00010000" + C1_APB4LPENR: + resetValue: "0x0421DEAA" + _delete: + - ICSCR + CSICFGR: + _modify: + CSICAL: + bitWidth: 10 + D1CCIPR: + _modify: + QSPISRC: + name: OCTOSPISEL + D2CCIP1R: + _delete: + - SAI23SRC + _modify: + SWPSRC: + name: SWPMISEL + D2CCIP2R: + _modify: + USART16SRC: + name: USART16910SEL + I2C123SRC: + name: I2C1235SEL + AHB3RSTR: + _delete: + - JPGDECRST + - QSPIRST + _add: + OCTOSPI1RST: + description: OCTOSPI1 and OCTOSPI1 delay block reset + bitWidth: 1 + bitOffset: 14 + OCTOSPI2RST: + description: OCTOSPI2 and OCTOSPI2 delay block reset + bitWidth: 1 + bitOffset: 19 + IOMNGRRST: + description: OCTOSPI IO manager reset + bitWidth: 1 + bitOffset: 21 + OTFD1RST: + description: OTFDEC1 reset + bitWidth: 1 + bitOffset: 22 + OTFD2RST: + description: OTFDEC2 reset + bitWidth: 1 + bitOffset: 23 + AHB3ENR: + _delete: + - JPGDECEN + - QSPIEN + _add: + OCTOSPI1EN: + description: OCTOSPI1 and OCTOSPI1 delay block enable + bitWidth: 1 + bitOffset: 14 + OCTOSPI2EN: + description: OCTOSPI2 and OCTOSPI2 delay block enable + bitWidth: 1 + bitOffset: 19 + IOMNGREN: + description: OCTOSPI IO manager enable + bitWidth: 1 + bitOffset: 21 + OTFD1EN: + description: OTFDEC1 enable + bitWidth: 1 + bitOffset: 22 + OTFD2EN: + description: OTFDEC2 enable + bitWidth: 1 + bitOffset: 23 + AHB3LPENR,C1_AHB3LPENR: + _delete: + - JPGDECLPEN + - QSPILPEN + _add: + OCTOSPI1LPEN: + description: OCTOSPI1 and OCTOSPI1 delay block enable during CSleep Mode + bitWidth: 1 + bitOffset: 14 + OCTOSPI2LPEN: + description: OCTOSPI2 and OCTOSPI2 delay block enable during CSleep Mode + bitWidth: 1 + bitOffset: 19 + IOMNGRLPEN: + description: OCTOSPI IO manager enable during CSleep Mode + bitWidth: 1 + bitOffset: 21 + OTFD1LPEN: + description: OTFDEC1 enable during CSleep Mode + bitWidth: 1 + bitOffset: 22 + OTFD2LPEN: + description: OTFDEC2 enable during CSleep Mode + bitWidth: 1 + bitOffset: 23 + AHB1RSTR: + _delete: + - USB2OTGRST + AHB1ENR: + _delete: + - USB2OTGEN + - USB2ULPIEN + AHB1LPENR,C1_AHB1LPENR: + _delete: + - USB2OTGLPEN + - USB2ULPILPEN + AHB2RSTR: + _add: + FMACRST: + description: FMAC reset + bitWidth: 1 + bitOffset: 16 + CORDICRST: + description: CORDIC reset + bitWidth: 1 + bitOffset: 17 + AHB2ENR: + _delete: + - SRAM3EN + _add: + FMACEN: + description: FMAC enable + bitWidth: 1 + bitOffset: 16 + CORDICEN: + description: CORDIC enable + bitWidth: 1 + bitOffset: 17 + AHB2LPENR,C1_AHB2LPENR: + _delete: + - SRAM3LPEN + _add: + FMACLPEN: + description: FMAC enable during CSleep Mode + bitWidth: 1 + bitOffset: 16 + CORDICLPEN: + description: CORDIC enable during CSleep Mode + bitWidth: 1 + bitOffset: 17 + APB1LRSTR: + _add: + I2C5RST: + description: I2C5 block reset + bitWidth: 1 + bitOffset: 25 + _modify: + HDMICECRST: + name: CECRST + APB1LENR: + _add: + I2C5EN: + description: I2C5 block enable + bitWidth: 1 + bitOffset: 25 + _modify: + HDMICECEN: + name: CECEN + APB1LLPENR,C1_APB1LLPENR: + _add: + I2C5LPEN: + description: I2C5 block enable during CSleep Mode + bitWidth: 1 + bitOffset: 25 + _modify: + HDMICECLPEN: + name: CECLPEN + APB1HRSTR: + _modify: + SWPRST: + name: SWPMIRST + _add: + TIM23RST: + description: TIM23 block reset + bitWidth: 1 + bitOffset: 24 + TIM24RST: + description: TIM24 block reset + bitWidth: 1 + bitOffset: 25 + APB1HENR: + _modify: + SWPEN: + name: SWPMIEN + _add: + TIM23EN: + description: TIM23 block enable + bitWidth: 1 + bitOffset: 24 + TIM24EN: + description: TIM24 block enable + bitWidth: 1 + bitOffset: 25 + APB1HLPENR,C1_APB1HLPENR: + _modify: + SWPLPEN: + name: SWPMILPEN + _add: + TIM23LPEN: + description: TIM23 block enable during CSleep Mode + bitWidth: 1 + bitOffset: 24 + TIM24LPEN: + description: TIM24 block enable during CSleep Mode + bitWidth: 1 + bitOffset: 25 + APB2RSTR: + _delete: + - HRTIMRST + APB2ENR: + _delete: + - HRTIMEN + APB2LPENR,C1_APB2LPENR: + _delete: + - HRTIMLPEN + APB4RSTR: + _add: + DTSRST: + description: Digital temperature sensor block reset + bitWidth: 1 + bitOffset: 26 + APB4ENR: + _add: + DTSEN: + description: Digital temperature sensor block enable + bitWidth: 1 + bitOffset: 26 + APB4LPENR,C1_APB4LPENR: + _add: + DTSLPEN: + description: Digital temperature sensor block enable during CSleep Mode + bitWidth: 1 + bitOffset: 26 + D3AMR: + _add: + DTSAMEN: + description: Digital temperature sensor Autonomous mode enable + bitWidth: 1 + bitOffset: 26 + +# OCTOSPI blocks +OCTOSPI?: + DCR1: + _modify: # Wider than in RM0455, where is it 3 bits + CSHT: + bitWidth: 6 + +_delete: + - HRTIM # RM0468 devices do not have an HRTIM + +FDCAN?: + _strip: + - FDCAN_ + +SAI?: + _strip: + - SAI_ + +SDMMC?: + _strip: + - SDMMC_ + +_include: + - common_patches/h7_common_singlecore.yaml + - common_patches/dma_fcr_wo.yaml + - common_patches/dma/bdma_v2_new.yaml + - common_patches/dma/dma_v3.yaml + - common_patches/dma/mdma.yaml + - common_patches/fdcan/fdcan_h7.yaml + - common_patches/fsmc/fsmc_sdram_cluster.yaml + - common_patches/h7_rcc_src_sel.yaml + - common_patches/h7_ethernet_combined_desc.yaml + - common_patches/h7_exti_singlecore.yaml + - common_patches/h7_dmacr.yaml + - common_patches/h7_dmamux.yaml + - common_patches/dma/dma2d_v2.yaml + - common_patches/h7_adc.yaml + - common_patches/h7_dsi.yaml + - common_patches/h7_adc_boost_rev_v.yaml + - common_patches/h7_octospi.yaml + - common_patches/h7_sai.yaml + - common_patches/h7_spdifrx.yaml + - common_patches/h7_otg.yaml + - common_patches/flash/flash_dual_bank.yaml + - common_patches/h7_hsicfgr_csicfgr_rev_v.yaml + - common_patches/ltdc/ltdc.yaml + - common_patches/merge_I2C_CR2_SADDx_fields.yaml + - common_patches/merge_USART_CR1_DEATx_fields.yaml + - common_patches/merge_USART_CR1_DEDTx_fields.yaml + - common_patches/merge_USART_CR2_ABRMODx_fields.yaml + - common_patches/merge_USART_CR2_ADDx_fields.yaml + - common_patches/rename_USART_CR2_DATAINV_field.yaml + - common_patches/merge_USART_BRR_fields.yaml + - common_patches/sai/sai_v1.yaml + - common_patches/tim/tim_o24ce.yaml + - ../peripherals/adc/adc_v3_h7.yaml + - ../peripherals/adc/adc_v3_common_h7.yaml + - ../peripherals/adc/adc_h7_revision_v.yaml + - ../peripherals/axi/axi_v1.yaml + - common_patches/crc/crc_rename_init.yaml + - ../peripherals/crc/crc_advanced.yaml + - ../peripherals/crc/crc_idr_32bit.yaml + - ../peripherals/crc/crc_with_polysize.yaml + - ../peripherals/crc/crc_pol.yaml + - ../peripherals/dma/bdma.yaml + - ../peripherals/dma/dma_v3.yaml + - ../peripherals/dma/dmamux_v1.yaml + - ../peripherals/dma/dma2d_v2.yaml + - ../peripherals/gpio/gpio_v2.yaml + - ../peripherals/lptim/lptim_v1.yaml + - ../peripherals/ltdc/ltdc.yaml + - ../peripherals/rcc/rcc_h7.yaml + - ../peripherals/rcc/rcc_h7_revision_v.yaml + - ../peripherals/rng/rng_v1.yaml + - ../peripherals/rng/rng_v1_ced.yaml + - ../peripherals/spi/spi_v3.yaml + - ../peripherals/tim/tim_basic.yaml + - ../peripherals/tim/tim_gp1.yaml + - ../peripherals/tim/tim16.yaml + - ../peripherals/tim/tim6.yaml + - ../peripherals/tim/tim2345_mixed.yaml + - common_patches/tim/tim2345_mixed_l.yaml + - ../peripherals/tim/tim_advanced.yaml + - common_patches/tim/tim_h7.yaml + - ../peripherals/tim/tim_h7.yaml + - ../peripherals/iwdg/iwdg_with_WINR.yaml + - ../peripherals/exti/exti_h7.yaml + - ../peripherals/i2c/i2c_v2.yaml + - ../peripherals/wwdg/wwdg_v2.yaml + - ../peripherals/usart/usart_v2B1.yaml + - common_patches/tim/tim_ccr.yaml + - ../peripherals/tim/tim_ccm_v2.yaml + - ../peripherals/tim/tim1234_1567_ccm_v2.yaml + - ../peripherals/sai/sai.yaml + - common_patches/rtc/rtc_bkpr.yaml + - common_patches/rtc/rtc_cr.yaml + - ../peripherals/rtc/rtc_common.yaml + - ../peripherals/rtc/rtc_h7.yaml + - common_patches/h7_crc_addr_fix.yaml + - common_patches/h7_wwdg.yaml diff --git a/devices/stm32h743.yaml b/devices/stm32h743.yaml index 4956a50d8..3e38e69e3 100644 --- a/devices/stm32h743.yaml +++ b/devices/stm32h743.yaml @@ -2,6 +2,7 @@ _svd: ../svd/stm32h743.svd _include: - common_patches/h7_common_singlecore.yaml + - common_patches/h7_ethernet_dma_mr.yaml - common_patches/dma_fcr_wo.yaml - common_patches/dma/bdma.yaml - common_patches/dma/dma_v3.yaml @@ -48,6 +49,7 @@ _include: - ../peripherals/lptim/lptim_v1.yaml - ../peripherals/ltdc/ltdc.yaml - ../peripherals/rcc/rcc_h7.yaml + - ../peripherals/rcc/rcc_v3_hrtim.yaml - ../peripherals/rcc/rcc_h7_revision_y.yaml - ../peripherals/rng/rng_v1.yaml - ../peripherals/rng/rng_v1_ced.yaml diff --git a/devices/stm32h743v.yaml b/devices/stm32h743v.yaml index c71b589e3..588a59387 100644 --- a/devices/stm32h743v.yaml +++ b/devices/stm32h743v.yaml @@ -2,6 +2,7 @@ _svd: ../svd/stm32h743v.svd _include: - common_patches/h7_common_singlecore.yaml + - common_patches/h7_ethernet_dma_mr.yaml - common_patches/dma_fcr_wo.yaml - common_patches/dma/bdma.yaml - common_patches/dma/dma_v3.yaml @@ -50,6 +51,7 @@ _include: - ../peripherals/lptim/lptim_v1.yaml - ../peripherals/ltdc/ltdc.yaml - ../peripherals/rcc/rcc_h7.yaml + - ../peripherals/rcc/rcc_v3_hrtim.yaml - ../peripherals/rcc/rcc_h7_revision_v.yaml - ../peripherals/rng/rng_v1.yaml - ../peripherals/rng/rng_v1_ced.yaml diff --git a/devices/stm32h747cm4.yaml b/devices/stm32h747cm4.yaml index 8a15de44d..9e3b9b697 100644 --- a/devices/stm32h747cm4.yaml +++ b/devices/stm32h747cm4.yaml @@ -25,7 +25,6 @@ _include: - common_patches/h7_rcc_src_sel.yaml - common_patches/h7_ethernet_combined_desc.yaml - common_patches/h7_exti_dualcore.yaml - - common_patches/h7_dbgmcu.yaml - common_patches/h7_dbgmcu_dualcore.yaml - common_patches/h7_dmamux.yaml - common_patches/dma/dma2d_v2.yaml @@ -65,6 +64,7 @@ _include: - ../peripherals/lptim/lptim_v1.yaml - ../peripherals/ltdc/ltdc.yaml - ../peripherals/rcc/rcc_h7.yaml + - ../peripherals/rcc/rcc_v3_hrtim.yaml - ../peripherals/rcc/rcc_h7_revision_v.yaml - ../peripherals/rng/rng_v1.yaml - ../peripherals/rng/rng_v1_ced.yaml diff --git a/devices/stm32h747cm7.yaml b/devices/stm32h747cm7.yaml index a47476ac4..5871904de 100644 --- a/devices/stm32h747cm7.yaml +++ b/devices/stm32h747cm7.yaml @@ -24,7 +24,6 @@ _include: - common_patches/h7_rcc_src_sel.yaml - common_patches/h7_ethernet_combined_desc.yaml - common_patches/h7_exti_dualcore.yaml - - common_patches/h7_dbgmcu.yaml - common_patches/h7_dbgmcu_dualcore.yaml - common_patches/h7_dmacr.yaml - common_patches/h7_dmamux.yaml @@ -66,6 +65,7 @@ _include: - ../peripherals/lptim/lptim_v1.yaml - ../peripherals/ltdc/ltdc.yaml - ../peripherals/rcc/rcc_h7.yaml + - ../peripherals/rcc/rcc_v3_hrtim.yaml - ../peripherals/rcc/rcc_h7_revision_v.yaml - ../peripherals/rng/rng_v1.yaml - ../peripherals/rng/rng_v1_ced.yaml diff --git a/devices/stm32h753.yaml b/devices/stm32h753.yaml index 2dbe16147..9956dcb75 100644 --- a/devices/stm32h753.yaml +++ b/devices/stm32h753.yaml @@ -12,6 +12,7 @@ CRYP: _include: - common_patches/h7_common_singlecore.yaml + - common_patches/h7_ethernet_dma_mr.yaml - common_patches/dma_fcr_wo.yaml - common_patches/dma/bdma.yaml - common_patches/dma/dma_v3.yaml @@ -58,6 +59,7 @@ _include: - ../peripherals/lptim/lptim_v1.yaml - ../peripherals/ltdc/ltdc.yaml - ../peripherals/rcc/rcc_h7.yaml + - ../peripherals/rcc/rcc_v3_hrtim.yaml - ../peripherals/rcc/rcc_h7_revision_y.yaml - ../peripherals/rng/rng_v1.yaml - ../peripherals/rng/rng_v1_ced.yaml diff --git a/devices/stm32h753v.yaml b/devices/stm32h753v.yaml index 25da11ba3..982788dad 100644 --- a/devices/stm32h753v.yaml +++ b/devices/stm32h753v.yaml @@ -12,6 +12,7 @@ CRYP: _include: - common_patches/h7_common_singlecore.yaml + - common_patches/h7_ethernet_dma_mr.yaml - common_patches/dma_fcr_wo.yaml - common_patches/dma/bdma.yaml - common_patches/dma/dma_v3.yaml @@ -60,6 +61,7 @@ _include: - ../peripherals/lptim/lptim_v1.yaml - ../peripherals/ltdc/ltdc.yaml - ../peripherals/rcc/rcc_h7.yaml + - ../peripherals/rcc/rcc_v3_hrtim.yaml - ../peripherals/rcc/rcc_h7_revision_v.yaml - ../peripherals/rng/rng_v1.yaml - ../peripherals/rng/rng_v1_ced.yaml diff --git a/devices/stm32h7b3.yaml b/devices/stm32h7b3.yaml index 44da1990b..6e6b23ed4 100644 --- a/devices/stm32h7b3.yaml +++ b/devices/stm32h7b3.yaml @@ -33,6 +33,9 @@ RCC: C1_APB4LPENR: resetValue: "0x0C01E6AA" + _strip: + - RCC_ + APB1LRSTR: _modify: DAC12RST: @@ -52,42 +55,15 @@ RCC: _delete: - LPTIM4RST - LPTIM5RST - _add: - DAC2RST: - description: DAC2 (containing one converter) reset - bitOffset: 13 - bitWidth: 1 - access: read-write APB4ENR: _delete: - LPTIM4EN - LPTIM5EN - _add: - DAC2EN: - description: DAC2 (containing one converter) peripheral clock enable - bitOffset: 13 - bitWidth: 1 - access: read-write APB4LPENR: _delete: - LPTIM4LPEN - LPTIM5LPEN - _add: - DAC2LPEN: - description: DAC2 (containing one converter) peripheral clock enable during CSleep mode - bitOffset: 13 - bitWidth: 1 - access: read-write - D3AMR: - _delete: - - LPTIM4AMEN - - LPTIM5AMEN - _add: - DAC2AMEN: - description: DAC2 (containing one converter) Autonomous mode enable - bitOffset: 13 - bitWidth: 1 - access: read-write + DBGMCU: APB4FZ1: _delete: @@ -110,7 +86,7 @@ _include: - common_patches/h7_adc.yaml - common_patches/h7_dsi.yaml - common_patches/h7_adc_boost_rev_v.yaml - - common_patches/h7_hsicfgr_csicfgr_rev_v.yaml + - common_patches/h7_octospi.yaml - common_patches/h7_sai.yaml - common_patches/h7_spdifrx.yaml - common_patches/h7_otg.yaml diff --git a/peripherals/rcc/rcc_v3.yaml b/peripherals/rcc/rcc_v3.yaml index b08d19391..72df06244 100644 --- a/peripherals/rcc/rcc_v3.yaml +++ b/peripherals/rcc/rcc_v3.yaml @@ -44,9 +44,6 @@ RCC: TIMPRE: DefaultX2: [0, "Timer kernel clock equal to 2x pclk by default"] DefaultX4: [1, "Timer kernel clock equal to 4x pclk by default"] - HRTIMSEL: - TIMY_KER: [0, "The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)"] - C_CK: [1, "The HRTIM prescaler clock source is the CPU clock (c_ck)"] RTCPRE: [0, 63] STOPWUCK,STOPKERWUCK: HSI: [0, "HSI selected as wake up clock from system Stop"] @@ -70,7 +67,7 @@ RCC: "*C": Clear: [1, "Clear interrupt flag"] BDCR: - BDRST: + BDRST,VSWRST: Reset: [1, "Resets the entire VSW domain"] RTCEN: Disabled: [0, "RTC clock disabled"] @@ -117,7 +114,7 @@ RCC: WW1RSC: Clear: [0, "Clear WWDG1 scope control"] Set: [1, "Set WWDG1 scope control"] - D3AMR: + D3AMR,SRDAMR: "*AMEN": Disabled: [0, "Clock disabled in autonomous mode"] Enabled: [1, "Clock enabled in autonomous mode"] diff --git a/peripherals/rcc/rcc_v3_h7_ccip.yaml b/peripherals/rcc/rcc_v3_h7_ccip.yaml index 612fe8fcb..84fb56501 100644 --- a/peripherals/rcc/rcc_v3_h7_ccip.yaml +++ b/peripherals/rcc/rcc_v3_h7_ccip.yaml @@ -4,8 +4,8 @@ # clock configuration registers (DxCFGR) RCC: - D1CFGR: - "D?CPRE,HPRE": + D1CFGR,CDCFGR1: + "D?CPRE,HPRE,CDCPRE": Div1: [0, "sys_ck not divided"] Div2: [8, "sys_ck divided by 2"] Div4: [9, "sys_ck divided by 4"] @@ -15,8 +15,8 @@ RCC: Div128: [13, "sys_ck divided by 128"] Div256: [14, "sys_ck divided by 256"] Div512: [15, "sys_ck divided by 512"] - D?CFGR: - D?PPR*: + D?CFGR,CDCFGR?: + D?PPR*,CDPPRE*: Div1: [0, "rcc_hclk not divided"] Div2: [4, "rcc_hclk divided by 2"] Div4: [5, "rcc_hclk divided by 4"] @@ -36,7 +36,7 @@ RCC: PLL2_R: [2, "pll2_r selected as peripheral clock"] PER: [3, "PER selected as peripheral clock"] D2CCIP1R,CDCCIP1R: - SWPSEL: + SWPSEL,SWPMISEL: PCLK: [0, "pclk selected as peripheral clock"] HSI_KER: [1, "hsi_ker selected as peripheral clock"] FDCANSEL: @@ -81,7 +81,7 @@ RCC: PLL1_Q: [1, "pll1_q selected as peripheral clock"] PLL3_Q: [2, "pll3_q selected as peripheral clock"] HSI48: [3, "HSI48 selected as peripheral clock"] - I2C123SEL: + I2C123SEL,I2C1235SEL: RCC_PCLK1: [0, "rcc_pclk1 selected as peripheral clock"] PLL3_R: [1, "pll3_r selected as peripheral clock"] HSI_KER: [2, "hsi_ker selected as peripheral clock"] diff --git a/peripherals/rcc/rcc_v3_hrtim.yaml b/peripherals/rcc/rcc_v3_hrtim.yaml new file mode 100644 index 000000000..9da73ead1 --- /dev/null +++ b/peripherals/rcc/rcc_v3_hrtim.yaml @@ -0,0 +1,7 @@ +# Applicable at least to H7, except RM0455 parts with no HRTIM + +RCC: + CFGR: + HRTIMSEL: + TIMY_KER: [0, "The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)"] + C_CK: [1, "The HRTIM prescaler clock source is the CPU clock (c_ck)"] diff --git a/stm32_part_table.yaml b/stm32_part_table.yaml index 3f6073e5c..6f0a102b7 100644 --- a/stm32_part_table.yaml +++ b/stm32_part_table.yaml @@ -373,6 +373,18 @@ stm32h7: members: - STM32H753V + stm32h735: + url: https://www.st.com/en/microcontrollers-microprocessors/stm32h730-value-line.html + rm: RM0468 + rm_title: STM32H723/733, STM32H725/735 and STM32H730 + rm_url: https://www.st.com/resource/en/reference_manual/dm00603761.pdf + members: + - STM32H723 + - STM32H725 + - STM32H730 + - STM32H733 + - STM32H735 + stm32h7b3: url: https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3-7b3.html rm: RM0455 diff --git a/svd/extract.sh b/svd/extract.sh index 69743f01b..dd0756939 100755 --- a/svd/extract.sh +++ b/svd/extract.sh @@ -6,13 +6,24 @@ done # Copy and rename H7 files to remove trailing 'x' # and provide a second copy of the SVDs to modify # for the revision-V hardware. -cp stm32h743x.svd stm32h743.svd -mv stm32h743x.svd stm32h743v.svd -cp stm32h753x.svd stm32h753.svd -mv stm32h753x.svd stm32h753v.svd -mv stm32h7x5_cm4.svd stm32h747cm4.svd -mv stm32h7x5_cm7.svd stm32h747cm7.svd +mv stm32h7a3x.svd stm32h7a3.svd +mv stm32h7b0x.svd stm32h7b0.svd mv stm32h7b3x.svd stm32h7b3.svd +mv stm32h73x.svd stm32h735.svd +mv stm32h742x.svd stm32h742.svd +# mv stm32h745_cm4.svd stm32h745cm4.svd +# mv stm32h745_cm7.svd stm32h745cm7.svd +# mv stm32h747_cm4.svd stm32h747cm4.svd +# mv stm32h747_cm7.svd stm32h747cm7.svd +mv stm32h750x.svd stm32h750.svd +# mv stm32h755_cm4.svd stm32h755cm4.svd +# mv stm32h755_cm7.svd stm32h755cm7.svd +# mv stm32h757_cm4.svd stm32h757cm4.svd +# mv stm32h757_cm7.svd stm32h757cm7.svd +mv stm32h757_cm4.svd stm32h747cm4.svd +mv stm32h757_cm7.svd stm32h747cm7.svd +cp stm32h743.svd stm32h743v.svd +cp stm32h753.svd stm32h753v.svd # Rename MP1 svd files to remove trailing 'x' mv stm32mp157x.svd stm32mp157.svd diff --git a/svd/vendor/en.stm32h7_svd.zip b/svd/vendor/en.stm32h7_svd.zip new file mode 100644 index 000000000..5ec820e06 Binary files /dev/null and b/svd/vendor/en.stm32h7_svd.zip differ diff --git a/svd/vendor/stm32h7_svd.zip b/svd/vendor/stm32h7_svd.zip deleted file mode 100644 index ff2f32bf7..000000000 Binary files a/svd/vendor/stm32h7_svd.zip and /dev/null differ