diff --git a/devices/common_patches/merge_USART_CR2_ADDx_fields_inverted.yaml b/devices/common_patches/merge_USART_CR2_ADDx_fields_inverted.yaml new file mode 100644 index 000000000..b1866dcb2 --- /dev/null +++ b/devices/common_patches/merge_USART_CR2_ADDx_fields_inverted.yaml @@ -0,0 +1,11 @@ +# Merge USART CR2 ADDx fields + +"USART*": + CR2: + _modify: + "ADD3_0": + name: ADD0 + "ADD7_4": + name: ADD4 + _merge: + - "ADD[04]" diff --git a/devices/common_patches/rename_USART_CR3_SCARCNT_field.yaml b/devices/common_patches/rename_USART_CR3_SCARCNT_field.yaml new file mode 100644 index 000000000..0731ebbb1 --- /dev/null +++ b/devices/common_patches/rename_USART_CR3_SCARCNT_field.yaml @@ -0,0 +1,7 @@ +# Rename USART CR3 SCARNT2_0 to SCARCNT + +"USART*": + CR3: + _modify: + SCARCNT2_0: + name: SCARCNT diff --git a/devices/common_patches/rtc/rtc_register_descriptions.yaml b/devices/common_patches/rtc/rtc_register_descriptions.yaml new file mode 100644 index 000000000..e6e6b2861 --- /dev/null +++ b/devices/common_patches/rtc/rtc_register_descriptions.yaml @@ -0,0 +1,42 @@ +RTC: + _modify: + TR: + description: Time register + DR: + description: Date register + SSR: + description: Sub second register + ICSR: + description: Initialization control and status register + PRER: + description: Pre-scaler register + WUTR: + description: Wakeup timer register + CR: + description: Control register + WPR: + description: Write protection register + CALR: + description: Calibration register + SHIFTR: + description: Shift control register + TSTR: + description: Timestamp time register + TSDR: + description: Timestamp date register + TSSSR: + description: Timestamp sub second register + ALRMAR: + description: Alarm A register + ALRMASSR: + description: Alarm A sub second register + ALRMBR: + description: Alarm B register + ALRMBSSR: + description: Alarm B sub second register + SR: + description: Status register (interrupts) + MISR: + description: Masked interrupt status register + SCR: + description: Status clear register (interrupts) diff --git a/devices/common_patches/wl_adc.yaml b/devices/common_patches/wl_adc.yaml new file mode 100644 index 000000000..70ba9c3de --- /dev/null +++ b/devices/common_patches/wl_adc.yaml @@ -0,0 +1,11 @@ +ADC: + CCR: + _merge: + - "PRESC*" + CFGR2: + _merge: + - "OVSS*" + - "OVSR*" + SMPR: + _split: + - "SMPSEL" diff --git a/devices/common_patches/wl_exti.yaml b/devices/common_patches/wl_exti.yaml new file mode 100644 index 000000000..e0b53710a --- /dev/null +++ b/devices/common_patches/wl_exti.yaml @@ -0,0 +1,47 @@ +EXTI: + RTSR1: + _add: + RT22: + description: Rising trigger event configuration bit of Configurable Event input + bitOffset: 22 + bitWidth: 1 + access: read-write + _modify: + RT21: + bitWidth: 1 + _split: [RT] + FTSR1: + _add: + FT22: + description: Falling trigger event configuration bit of Configurable Event input + bitOffset: 22 + bitWidth: 1 + access: read-write + _modify: + FT21: + bitWidth: 1 + _split: [FT] + SWIER1: + _add: + SWI22: + description: Software interrupt on event + bitOffset: 22 + bitWidth: 1 + access: read-write + _modify: + SWI21: + bitWidth: 1 + _split: [SWI] + PR1: + _add: + PIF22: + description: Configurable event inputs Pending bit + bitOffset: 22 + bitWidth: 1 + access: read-write + _modify: + PIF21: + bitWidth: 1 + _split: [PIF] + C1IMR1,IMR1: + _split: [IM] diff --git a/devices/stm32wl5x_cm0p.yaml b/devices/stm32wl5x_cm0p.yaml index 6fd8314f4..f954249af 100644 --- a/devices/stm32wl5x_cm0p.yaml +++ b/devices/stm32wl5x_cm0p.yaml @@ -2,3 +2,152 @@ _svd: ../svd/stm32wl5x_cm0p.svd _modify: name: STM32WL5X_CM0P + +AES: + CR: + _modify: + CHMOD10: + name: CHMOD + DINR: + _modify: + AES_DINR: + name: DIN + DOUTR: + _modify: + AES_DOUTR: + name: DOUT + "KEYR?": + _modify: + "AES_KEYR?": + name: KEY + "IVR?": + _modify: + "AES_IVR?": + name: IVI + "SUSP?R": + _modify: + "AES_SUSP?R": + name: SUSP + +DAC: + CR: + _merge: + - "TSEL1*" + +HSEM: + _strip: + - HSEM_ + _modify: + HSEM_C2ICR: + access: read-write + +TIM1: + _modify: + CCMR3OutputComparemode: + name: CCMR3_Output + +TIM2: + _strip: + - TIM2_ + +TIM1?: + _strip: + - TIM1?_ + DIER: + _delete: + - COMDE + BDTR: + _delete: + - BKF + +LPTIM,LPTIM?: + _strip: + - LPTIM_ + - LPTIM?_ + +LPTIM[23]: + OR: + _merge: + - "OR*" + +IWDG: + _delete: + - WINR + +# Rename this so it has the same name as all other STM32 USARTs +LPUART,USART?: + ICR: + _modify: + NECF: + name: NCF + +# CR1 and ISR have 2 versions depending on whether FIFO is enabled or not +# The only difference is the addition of 2 bits at the top of the register +# and some names (e.g. TXEIE - TXFNFIE), but all functionality remains the same +# so we remove the "disabled" version and leave the "enabled" version as +# reference +LPUART: + _modify: + CR1_enabled: + name: CR1 + ISR_enabled: + name: ISR + _delete: + - CR1_disabled + - ISR_disabled + CR1: + _modify: + TXFNFIE: + name: TXEIE +_delete: + - SYSCFG_continue + +_include: + - ../devices/common_patches/l4_spi.yaml + - ../devices/common_patches/crc/crc_rename_init.yaml + - ../devices/common_patches/rtc/rtc_register_descriptions.yaml + - ../devices/common_patches/wl_exti.yaml + - ../devices/common_patches/merge_USART_CR1_DEATx_fields.yaml + - ../devices/common_patches/merge_USART_CR1_DEDTx_fields.yaml + - ../devices/common_patches/merge_USART_CR2_ADDx_fields_inverted.yaml + - ../devices/common_patches/merge_USART_CR2_ABRMODx_fields.yaml + - ../devices/common_patches/rename_USART_CR1_M0_field.yaml + - ../devices/common_patches/rename_USART_CR3_SCARCNT_field.yaml + - ../peripherals/aes/aes_wl.yaml + - ../peripherals/comp/comp_wl.yaml + - ../peripherals/crc/crc_advanced.yaml + - ../peripherals/crc/crc_pol.yaml + - ../peripherals/crc/crc_with_polysize.yaml + - ../peripherals/dac/dac_wl.yaml + - ../peripherals/dac/dac_wl_12bit.yaml + - ../peripherals/dac/dac_wl_8bit.yaml + - ../peripherals/dma/dma_wl.yaml + - ../peripherals/dma/dmamux_wl.yaml + - ../peripherals/exti/exti.yaml + - ../peripherals/flash/flash_wl.yaml + - ../peripherals/gpio/gpio_v2_common.yaml + - ../peripherals/gpio/gpio_wl_with_brr.yaml + - ../peripherals/hsem/hsem_wl.yaml + - ../peripherals/i2c/i2c_v2.yaml + - ../peripherals/iwdg/iwdg.yaml + - ../peripherals/iwdg/iwdg_sr.yaml + - ../peripherals/lptim/lptim_v1.yaml + - ../peripherals/lptim/lptim_wl.yaml + - ../peripherals/usart/lpuart_wl.yaml + - ../peripherals/pka/pka.yaml + - ../peripherals/pwr/pwr_wl.yaml + - ../peripherals/rcc/rcc_wl.yaml + - ../peripherals/rtc/rtc_wl.yaml + - ../peripherals/rng/rng_wl.yaml + - ../peripherals/spi/spi_v2.yaml + - ../peripherals/syscfg/syscfg_wl.yaml + - ../peripherals/tamp/tamp_wl.yaml + - ../peripherals/tim/tim_basic.yaml + - ../peripherals/tim/tim12_common_wl.yaml + - ../peripherals/tim/tim1_wl.yaml + - ../peripherals/tim/tim2_wl.yaml + - ../peripherals/tim/tim16_wl.yaml + - ../peripherals/usart/usart_v2C.yaml + - ../peripherals/usart/usart_wl.yaml + - ../peripherals/vrefbuf/vrefbuf_wl.yaml + - ../peripherals/wwdg/wwdg.yaml diff --git a/devices/stm32wl5x_cm4.yaml b/devices/stm32wl5x_cm4.yaml index 00efcf8eb..d22f4b87f 100644 --- a/devices/stm32wl5x_cm4.yaml +++ b/devices/stm32wl5x_cm4.yaml @@ -2,3 +2,161 @@ _svd: ../svd/stm32wl5x_cm4.svd _modify: name: STM32WL5X_CM4 + +ADC: + CFGR2: + _merge: + - "OVSS*" + - "OVSR*" + +AES: + CR: + _modify: + CHMOD10: + name: CHMOD + DINR: + _modify: + AES_DINR: + name: DIN + DOUTR: + _modify: + AES_DOUTR: + name: DOUT + "KEYR?": + _modify: + "AES_KEYR?": + name: KEY + "IVR?": + _modify: + "AES_IVR?": + name: IVI + "SUSP?R": + _modify: + "AES_SUSP?R": + name: SUSP + +DAC: + CR: + _merge: + - "TSEL1*" + +HSEM: + _strip: + - HSEM_ + _modify: + HSEM_C2ICR: + access: read-write + +TIM1: + _modify: + CCMR3OutputComparemode: + name: CCMR3_Output + +TIM2: + _strip: + - TIM2_ + +TIM1?: + _strip: + - TIM1?_ + DIER: + _delete: + - COMDE + BDTR: + _delete: + - BKF + +LPTIM,LPTIM?: + _strip: + - LPTIM_ + - LPTIM?_ + +LPTIM[23]: + OR: + _merge: + - "OR*" + +IWDG: + _delete: + - WINR + +# Rename this so it has the same name as all other STM32 USARTs +LPUART,USART?: + ICR: + _modify: + NECF: + name: NCF + +# CR1 and ISR have 2 versions depending on whether FIFO is enabled or not +# The only difference is the addition of 2 bits at the top of the register +# and some names (e.g. TXEIE - TXFNFIE), but all functionality remains the same +# so we remove the "disabled" version and leave the "enabled" version as +# reference +LPUART: + _modify: + CR1_enabled: + name: CR1 + ISR_enabled: + name: ISR + _delete: + - CR1_disabled + - ISR_disabled + CR1: + _modify: + TXFNFIE: + name: TXEIE +_delete: + - SYSCFG_continue + +_include: + - ../devices/common_patches/l4_spi.yaml + - ../devices/common_patches/wl_adc.yaml + - ../devices/common_patches/crc/crc_rename_init.yaml + - ../devices/common_patches/rtc/rtc_register_descriptions.yaml + - ../devices/common_patches/wl_exti.yaml + - ../devices/common_patches/merge_USART_CR1_DEATx_fields.yaml + - ../devices/common_patches/merge_USART_CR1_DEDTx_fields.yaml + - ../devices/common_patches/merge_USART_CR2_ADDx_fields_inverted.yaml + - ../devices/common_patches/merge_USART_CR2_ABRMODx_fields.yaml + - ../devices/common_patches/rename_USART_CR1_M0_field.yaml + - ../devices/common_patches/rename_USART_CR3_SCARCNT_field.yaml + - ../peripherals/adc/adc_wl.yaml + - ../peripherals/aes/aes_wl.yaml + - ../peripherals/comp/comp_wl.yaml + - ../peripherals/crc/crc_advanced.yaml + - ../peripherals/crc/crc_pol.yaml + - ../peripherals/crc/crc_with_polysize.yaml + - ../peripherals/dac/dac_wl.yaml + - ../peripherals/dac/dac_wl_12bit.yaml + - ../peripherals/dac/dac_wl_8bit.yaml + - ../peripherals/dma/dma_wl.yaml + - ../peripherals/dma/dmamux_wl.yaml + - ../peripherals/dbg/dbg_wl.yaml + - ../peripherals/exti/exti.yaml + - ../peripherals/flash/flash_wl.yaml + - ../peripherals/gpio/gpio_v2_common.yaml + - ../peripherals/gpio/gpio_wl_with_brr.yaml + - ../peripherals/hsem/hsem_wl.yaml + - ../peripherals/i2c/i2c_v2.yaml + - ../peripherals/iwdg/iwdg.yaml + - ../peripherals/iwdg/iwdg_sr.yaml + - ../peripherals/lptim/lptim_v1.yaml + - ../peripherals/lptim/lptim_wl.yaml + - ../peripherals/usart/lpuart_wl.yaml + - ../peripherals/pka/pka.yaml + - ../peripherals/pwr/pwr_wl.yaml + - ../peripherals/rcc/rcc_wl.yaml + - ../peripherals/rtc/rtc_wl.yaml + - ../peripherals/rng/rng_wl.yaml + - ../peripherals/spi/spi_v2.yaml + - ../peripherals/syscfg/syscfg_wl.yaml + - ../peripherals/tamp/tamp_wl.yaml + - ../peripherals/tim/tim_basic.yaml + - ../peripherals/tim/tim12_common_wl.yaml + - ../peripherals/tim/tim1_wl.yaml + - ../peripherals/tim/tim2_wl.yaml + - ../peripherals/tim/tim16_wl.yaml + - ../peripherals/usart/usart_v2C.yaml + - ../peripherals/usart/usart_wl.yaml + - ../peripherals/vrefbuf/vrefbuf_wl.yaml + - ../peripherals/wwdg/wwdg.yaml diff --git a/devices/stm32wle5.yaml b/devices/stm32wle5.yaml index 515290bf4..ee8bb091a 100644 --- a/devices/stm32wle5.yaml +++ b/devices/stm32wle5.yaml @@ -2,3 +2,212 @@ _svd: ../svd/stm32wle5.svd _modify: name: STM32WLE5 + +AES: + CR: + _modify: + CHMOD10: + name: CHMOD + DINR: + _modify: + AES_DINR: + name: DIN + DOUTR: + _modify: + AES_DOUTR: + name: DOUT + "KEYR?": + _modify: + "AES_KEYR?": + name: KEY + "IVR?": + _modify: + "AES_IVR?": + name: IVI + "SUSP?R": + _modify: + "AES_SUSP?R": + name: SUSP + +DAC: + CR: + _merge: + - "TSEL1*" + +EXTI: + IMR2: + _modify: + IM42: + bitWidth: 1 + _add: + IM43: + description: CPUm Wakeup with interrupt Mask on Event input + bitOffset: 11 + bitWidth: 1 + access: read-write + IM44: + description: CPUm Wakeup with interrupt Mask on Event input + bitOffset: 12 + bitWidth: 1 + access: read-write + IM45: + description: CPUm Wakeup with interrupt Mask on Event input + bitOffset: 13 + bitWidth: 1 + access: read-write + IM46: + description: CPUm Wakeup with interrupt Mask on Event input + bitOffset: 14 + bitWidth: 1 + access: read-write + +HSEM: + _strip: + - HSEM_ + _modify: + HSEM_IER: + name: + C1IER + HSEM_ICR: + name: + C1ICR + HSEM_ISR: + name: + C1ISR + HSEM_MISR: + name: + C1MISR + "R[0123456789]": + _modify: + MASTERID: + name: COREID + "R1[012345]": + _modify: + MASTERID: + name: COREID + "RLR[0123456789]": + _modify: + MASTERID: + name: COREID + "RLR1[012345]": + _modify: + MASTERID: + name: COREID + CR: + _modify: + MASTERID: + name: COREID + +TIM1: + _modify: + CCMR3OutputComparemode: + name: CCMR3_Output + +TIM2: + _strip: + - TIM2_ + +TIM1?: + _strip: + - TIM1?_ + DIER: + _delete: + - COMDE + BDTR: + _delete: + - BKF + +LPTIM,LPTIM?: + _strip: + - LPTIM_ + - LPTIM?_ + +LPTIM[23]: + OR: + _merge: + - "OR*" + +IWDG: + _delete: + - WINR + +# Rename this so it has the same name as all other STM32 USARTs +LPUART,USART?: + ICR: + _modify: + NECF: + name: NCF + +# CR1 and ISR have 2 versions depending on whether FIFO is enabled or not +# The only difference is the addition of 2 bits at the top of the register +# and some names (e.g. TXEIE - TXFNFIE), but all functionality remains the same +# so we remove the "disabled" version and leave the "enabled" version as +# reference +LPUART: + _modify: + CR1_enabled: + name: CR1 + ISR_enabled: + name: ISR + _delete: + - CR1_disabled + - ISR_disabled + CR1: + _modify: + TXFNFIE: + name: TXEIE +_delete: + - SYSCFG_continue + +_include: + - ../devices/common_patches/l4_spi.yaml + - ../devices/common_patches/wl_adc.yaml + - ../devices/common_patches/crc/crc_rename_init.yaml + - ../devices/common_patches/rtc/rtc_register_descriptions.yaml + - ../devices/common_patches/wl_exti.yaml + - ../devices/common_patches/merge_USART_CR1_DEATx_fields.yaml + - ../devices/common_patches/merge_USART_CR1_DEDTx_fields.yaml + - ../devices/common_patches/merge_USART_CR2_ADDx_fields_inverted.yaml + - ../devices/common_patches/merge_USART_CR2_ABRMODx_fields.yaml + - ../devices/common_patches/rename_USART_CR1_M0_field.yaml + - ../devices/common_patches/rename_USART_CR3_SCARCNT_field.yaml + - ../peripherals/adc/adc_wl.yaml + - ../peripherals/aes/aes_wl.yaml + - ../peripherals/comp/comp_wl.yaml + - ../peripherals/crc/crc_advanced.yaml + - ../peripherals/crc/crc_pol.yaml + - ../peripherals/crc/crc_with_polysize.yaml + - ../peripherals/dac/dac_wl.yaml + - ../peripherals/dac/dac_wl_12bit.yaml + - ../peripherals/dac/dac_wl_8bit.yaml + - ../peripherals/dma/dma_wl.yaml + - ../peripherals/dma/dmamux_wl.yaml + - ../peripherals/dbg/dbg_wl.yaml + - ../peripherals/exti/exti.yaml + - ../peripherals/flash/flash_wl.yaml + - ../peripherals/gpio/gpio_v2_common.yaml + - ../peripherals/gpio/gpio_wl_with_brr.yaml + - ../peripherals/hsem/hsem_wl.yaml + - ../peripherals/i2c/i2c_v2.yaml + - ../peripherals/iwdg/iwdg.yaml + - ../peripherals/iwdg/iwdg_sr.yaml + - ../peripherals/lptim/lptim_v1.yaml + - ../peripherals/lptim/lptim_wl.yaml + - ../peripherals/usart/lpuart_wl.yaml + - ../peripherals/pka/pka.yaml + - ../peripherals/pwr/pwr_wl.yaml + - ../peripherals/rcc/rcc_wl.yaml + - ../peripherals/rtc/rtc_wl.yaml + - ../peripherals/rng/rng_wl.yaml + - ../peripherals/spi/spi_v2.yaml + - ../peripherals/syscfg/syscfg_wl.yaml + - ../peripherals/tamp/tamp_wl.yaml + - ../peripherals/tim/tim_basic.yaml + - ../peripherals/tim/tim12_common_wl.yaml + - ../peripherals/tim/tim1_wl.yaml + - ../peripherals/tim/tim2_wl.yaml + - ../peripherals/tim/tim16_wl.yaml + - ../peripherals/usart/usart_v2C.yaml + - ../peripherals/usart/usart_wl.yaml + - ../peripherals/vrefbuf/vrefbuf_wl.yaml + - ../peripherals/wwdg/wwdg.yaml diff --git a/peripherals/adc/adc_wl.yaml b/peripherals/adc/adc_wl.yaml new file mode 100644 index 000000000..7c8fccf97 --- /dev/null +++ b/peripherals/adc/adc_wl.yaml @@ -0,0 +1,269 @@ +# ADC as used on the WL family + +ADC: + ISR: + CCRDY: + _read: + NotComplete: [0, "Channel configuration update not applied"] + Complete: [1, "Channel configuration update is applied"] + _write: + Clear: [1, "Clear the channel configuration flag"] + EOCAL: + _read: + NotComplete: [0, "Calibration is not complete"] + Complete: [1, "Calibration complete"] + _write: + Clear: [1, "Clear the calibration flag"] + "AWD[123]": + _read: + NoEvent: [0, "No analog watchdog event occurred"] + Event: [1, "Analog watchdog event occurred"] + _write: + Clear: [1, "Clear the analog watchdog event flag"] + OVR: + _read: + NoOverrun: [0, "No overrun occurred"] + Overrun: [1, "Overrun occurred"] + _write: + Clear: [1, "Clear the overrun flag"] + EOS: + _read: + NotComplete: [0, "Conversion sequence is not complete"] + Complete: [1, "Conversion sequence complete"] + _write: + Clear: [1, "Clear the conversion sequence flag"] + EOC: + _read: + NotComplete: [0, "Channel conversion is not complete"] + Complete: [1, "Channel conversion complete"] + _write: + Clear: [1, "Clear the channel conversion flag"] + EOSMP: + _read: + NotAtEnd: [0, "Not at the end of the samplings phase"] + AtEnd: [1, "End of sampling phase reached"] + _write: + Clear: [1, "Clear the sampling phase flag"] + ADRDY: + _read: + NotReady: [0, "ADC not yet ready to start conversion"] + Ready: [1, "ADC ready to start conversion"] + _write: + Clear: [1, "Clear the ADC ready flag"] + IER: + CCRDYIE: + Disabled: [0, "Channel configuration ready interrupt disabled"] + Enabled: [1, "Channel configuration ready interrupt enabled"] + EOCALIE: + Disabled: [0, "End of calibration interrupt disabled"] + Enabled: [1, "End of calibration interrupt enabled"] + "AWD[123]IE": + Disabled: [0, "Analog watchdog interrupt disabled"] + Enabled: [1, "Analog watchdog interrupt enabled"] + OVRIE: + Disabled: [0, "Overrun interrupt disabled"] + Enabled: [1, "Overrun interrupt enabled. An interrupt is generated when the OVR bit is set."] + EOSIE: + Disabled: [0, "EOS interrupt disabled"] + Enabled: [1, "EOS interrupt enabled. An interrupt is generated when the EOS bit is set."] + EOCIE: + Disabled: [0, "EOC interrupt disabled"] + Enabled: [1, "EOC interrupt enabled. An interrupt is generated when the EOC bit is set."] + EOSMPIE: + Disabled: [0, "EOSMP interrupt disabled"] + Enabled: [1, "EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set."] + ADRDYIE: + Disabled: [0, "ADRDY interrupt disabled"] + Enabled: [1, "ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set."] + CR: + ADCAL: + _read: + NotCalibrating: [0, "ADC calibration either not yet performed or completed"] + Calibrating: [1, "ADC calibration in progress"] + _write: + StartCalibration: [1, "Start the ADC calibration sequence"] + ADVREGEN: + Disabled: [0, "ADC voltage regulator disabled"] + Enabled: [1, "ADC voltage regulator enabled"] + ADSTP: + _read: + NotStopping: [0, "No stop command active"] + Stopping: [1, "ADC stopping conversion"] + _write: + StopConversion: [1, "Stop the active conversion"] + ADSTART: + _read: + NotActive: [0, "No conversion ongoing"] + Active: [1, "ADC operating and may be converting"] + _write: + StartConversion: [1, "Start the ADC conversion (may be delayed for hardware triggers)"] + ADDIS: + _read: + NotDisabling: [0, "No disable command active"] + Disabling: [1, "ADC disabling"] + _write: + Disable: [1, "Disable the ADC"] + ADEN: + _read: + Disabled: [0, "ADC disabled"] + Enabled: [1, "ADC enabled"] + _write: + Enabled: [1, "Enable the ADC"] + CFGR1: + AWD1CH: [0, 17] + AWD1EN: + Disabled: [0, "Analog watchdog 1 disabled"] + Enabled: [1, "Analog watchdog 1 enabled"] + AWD1SGL: + AllChannels: [0, "Analog watchdog 1 enabled on all channels"] + SingleChannel: [1, "Analog watchdog 1 enabled on a single channel"] + CHSELRMOD: + BitPerInput: [0, "Each bit of the ADC_CHSELR register enables an input"] + Sequence: [1, "ADC_CHSELR register is able to sequence up to 8 channels"] + DISCEN: + Disabled: [0, "Discontinuous mode disabled"] + Enabled: [1, "Discontinuous mode enabled"] + AUTOFF: + Disabled: [0, "Auto-off mode disabled"] + Enabled: [1, "Auto-off mode enabled"] + WAIT: + Disabled: [0, "Wait conversion mode off"] + Enabled: [1, "Wait conversion mode on"] + CONT: + Single: [0, "Single conversion mode"] + Continuous: [1, "Continuous conversion mode"] + OVRMOD: + Preserve: [0, "ADC_DR register is preserved with the old data when an overrun is detected"] + Overwrite: [1, "ADC_DR register is overwritten with the last conversion result when an overrun is detected"] + EXTEN: + Disabled: [0, "Hardware trigger detection disabled"] + RisingEdge: [1, "Hardware trigger detection on the rising edge"] + FallingEdge: [2, "Hardware trigger detection on the falling edge"] + BothEdges: [3, "Hardware trigger detection on both the rising and falling edges"] + EXTSEL: + TIM1_TRGO: [0, "Timer 1 TRGO event"] + TIM1_CC4: [1, "Timer 1 CC4 event"] + TIM2_TRGO: [2, "Timer 2 TRGO event"] + TIM2_CH4: [3, "Timer 2 CH4 event"] + #Reserved1: [4, "Reserved - not forbidden but it has no effect"] + TIM2_CH3: [5, "Timer 2 CH3 event"] + #Reserved2: [6, "Reserved - not forbidden but it has no effect"] + EXTI_LINE11: [7, "EXTI line 11 event"] + ALIGN: + Right: [0, "Right alignment"] + Left: [1, "Left alignment"] + RES: + Bits12: [0, "12 bits"] + Bits10: [1, "10 bits"] + Bits8: [2, "8 bits"] + Bits6: [3, "6 bits"] + SCANDIR: + Upward: [0, "Upward scan (from CHSEL0 to CHSEL17)"] + Backward: [1, "Backward scan (from CHSEL17 to CHSEL0)"] + DMACFG: + OneShot: [0, "DMA one shot mode selected"] + Circular: [1, "DMA circular mode selected"] + DMAEN: + Disabled: [0, "DMA disabled"] + Enabled: [1, "DMA enabled"] + CFGR2: + CKMODE: + ADCLK: [0, "ADCCLK (Asynchronous clock mode)"] + PCLK_Div2: [1, "PCLK/2 (Synchronous clock mode)"] + PCLK_Div4: [2, "PCLK/4 (Synchronous clock mode)"] + PCLK: [3, "PCLK (Synchronous clock mode)"] + LFTRIG: + Disabled: [0, "Low Frequency Trigger Mode disabled"] + Enabled: [1, "Low Frequency Trigger Mode enabled"] + TOVS: + TriggerAll: [0, "All oversampled conversions for a channel are done consecutively after a trigger"] + TriggerEach: [1, "Each oversampled conversion for a channel needs a trigger"] + OVSS: + NoShift: [0, "No shift"] + Shift1: [1, "Shift 1-bit"] + Shift2: [2, "Shift 2-bits"] + Shift3: [3, "Shift 3-bits"] + Shift4: [4, "Shift 4-bits"] + Shift5: [5, "Shift 5-bits"] + Shift6: [6, "Shift 6-bits"] + Shift7: [7, "Shift 7-bits"] + Shift8: [8, "Shift 8-bits"] + OVSR: + Mul2: [0, "2x"] + Mul4: [1, "4x"] + Mul8: [2, "8x"] + Mul16: [3, "16x"] + Mul32: [4, "32x"] + Mul64: [5, "64x"] + Mul128: [6, "128x"] + Mul256: [7, "256x"] + OVSE: + Disabled: [0, "Oversampler disabled"] + Enabled: [1, "Oversampler enabled"] + SMPR: + "SMPSEL*": + Smp1: [0, "Sampling time of CHANNELx use the setting of SMP1 register"] + Smp2: [1, "Sampling time of CHANNELx use the setting of SMP2 register"] + "SMP?": + Cycles1_5: [0, "1.5 ADC clock cycles"] + Cycles3_5: [1, "3.5 ADC clock cycles"] + Cycles7_5: [2, "7.5 ADC clock cycles"] + Cycles12_5: [3, "12.5 ADC clock cycles"] + Cycles19_5: [4, "19.5 ADC clock cycles"] + Cycles39_5: [5, "39.5 ADC clock cycles"] + Cycles79_5: [6, "79.5 ADC clock cycles"] + Cycles160_5: [7, "160.5 ADC clock cycles"] + "AWD?TR": + "HT?": [0, 4095] + "LT?": [0, 4095] + CHSELR0: + "CHSEL*": + NotSelected: [0, "Input Channel is not selected for conversion"] + Selected: [1, "Input Channel is selected for conversion"] + CHSELR1: + "SQ*": + Ch0: [0, "Channel 0 selected for the Nth conversion"] + Ch1: [1, "Channel 1 selected for the Nth conversion"] + Ch2: [2, "Channel 2 selected for the Nth conversion"] + Ch3: [3, "Channel 3 selected for the Nth conversion"] + Ch4: [4, "Channel 4 selected for the Nth conversion"] + Ch5: [5, "Channel 5 selected for the Nth conversion"] + Ch6: [6, "Channel 6 selected for the Nth conversion"] + Ch7: [7, "Channel 7 selected for the Nth conversion"] + Ch8: [8, "Channel 8 selected for the Nth conversion"] + Ch9: [9, "Channel 9 selected for the Nth conversion"] + Ch10: [10, "Channel 10 selected for the Nth conversion"] + Ch11: [11, "Channel 11 selected for the Nth conversion"] + Ch12: [12, "Channel 12 selected for the Nth conversion"] + Ch13: [13, "Channel 13 selected for the Nth conversion"] + Ch14: [14, "Channel 14 selected for the Nth conversion"] + EOS: [15, "End of sequence"] + + DR: + DATA: [0, 65535] + CALFACT: + CALFACT: [0, 127] + CCR: + VBATEN: + Disabled: [0, "VBAT channel disabled"] + Enabled: [1, "VBAT channel enabled"] + TSEN: + Disabled: [0, "Temperature sensor disabled"] + Enabled: [1, "Temperature sensor enabled"] + VREFEN: + Disabled: [0, "VREFINT disabled"] + Enabled: [1, "VREFINT enabled"] + PRESC: + Div1: [0, "Input ADC clock not divided"] + Div2: [1, "Input ADC clock divided by 2"] + Div4: [2, "Input ADC clock divided by 4"] + Div6: [3, "Input ADC clock divided by 6"] + Div8: [4, "Input ADC clock divided by 8"] + Div10: [5, "Input ADC clock divided by 10"] + Div12: [6, "Input ADC clock divided by 12"] + Div16: [7, "Input ADC clock divided by 16"] + Div32: [8, "Input ADC clock divided by 32"] + Div64: [9, "Input ADC clock divided by 64"] + Div128: [10, "Input ADC clock divided by 128"] + Div256: [11, "Input ADC clock divided by 256"] + diff --git a/peripherals/aes/aes_wl.yaml b/peripherals/aes/aes_wl.yaml new file mode 100644 index 000000000..b144777cb --- /dev/null +++ b/peripherals/aes/aes_wl.yaml @@ -0,0 +1,73 @@ +AES: + CR: + NPBLB: [0, 15] + KEYSIZE: + Bits128: [0, "128 bits"] + Bits256: [1, "256 bits"] + GCMPH: + Init: [0, "Init phase"] + Header: [1, "Header phase"] + Payload: [2, "Payload phase"] + Final: [3, "Final phase"] + DMAOUTEN: + Disabled: [0, "Disable DMA Output"] + Enabled: [1, "Enabled DMA Output"] + DMAINEN: + Disabled: [0, "Disable DMA Input"] + Enabled: [1, "Enable DMA Input"] + ERRIE: + Disabled: [0, "Disable (mask) error interrupt"] + Enabled: [1, "Enable error interrupt"] + CCFIE: + Disabled: [0, "Disable (mask) CCF interrupt"] + Enabled: [1, "Enable CCF interrupt"] + ERRC: + _write: + Clear: [1, "Clear RDERR and WRERR flags"] + CCFC: + _write: + Clear: [1, "Clear computation complete flag"] + DATATYPE: + None: [0, "Word"] + HalfWord: [1, "Half-word (16-bit)"] + Byte: [2, "Byte (8-bit)"] + Bit: [3, "Bit"] + EN: + Disabled: [0, "Disable AES"] + Enabled: [1, "Enable AES"] + CHMOD: + ECB: [0, "Electronic codebook (ECB) / Counter with CBC-MAC (CCM) if CHMOD2 is 1"] + CBC: [1, "Cipher-block chaining (CBC)"] + CTR: [2, "Counter mode (CTR)"] + GCM: [3, "Galois counter mode (GCM) and Galois message authentication code (GMAC)"] + CHMOD2: + CHMOD: [0, "Mode as per CHMOD (ECB, CBC, CTR, GCM)"] + CCM: [1, "Counter with CBC-MAC (CCM) - CHMOD must be 0 (ECB)"] + MODE: + Mode1: [0, "Mode 1: encryption"] + Mode2: [1, "Mode 2: key derivation (or key preparation for ECB/CBC decryption)"] + Mode3: [2, "Mode 3: decryption"] + Mode4: [3, "Mode 4: key derivation & decrypt (UNDOCUMENTED in ref. manual, exists in CubeMX code)"] + SR: + BUSY: + Idle: [0, "Idle"] + Busy: [1, "Busy"] + WRERR: + NoError: [0, "Write error not detected"] + Error: [1, "Write error detected"] + RDERR: + NoError: [0, "Read error not detected"] + Error: [1, "Read error detected"] + CCF: + Complete: [0, "Computation complete"] + NotComplete: [1, "Computation not complete"] + "KEYR[01234567]": + "KEY": [0, 0xFFFFFFFF] + "IVR[0123]": + "IVI": [0, 0xFFFFFFFF] + "SUSP?R": + SUSP: [0, 0xFFFFFFFF] + DINR: + DIN: [0, 0xFFFFFFFF] + DOUTR: + DOUT: [0, 0xFFFFFFFF] diff --git a/peripherals/comp/comp_wl.yaml b/peripherals/comp/comp_wl.yaml new file mode 100644 index 000000000..bd237d603 --- /dev/null +++ b/peripherals/comp/comp_wl.yaml @@ -0,0 +1,64 @@ +COMP: + COMP?_CSR: + LOCK: + Unlocked: [0, "Comparator CSR bits are read-write"] + Locked: [1, "Comparator CSR bits are read-only"] + VALUE: + Low: [0, "Comparator output is low"] + High: [1, "Comparator output is high"] + SCALEN: + Disabled: [0, "Voltage scaler disabled"] + Enabled: [1, "Voltage scaler enabled"] + BRGEN: + Disabled: [0, "Scaler resistor bridge disabled"] + Enabled: [1, "Scaler resistor bridge enabled"] + BLANKING: + NoBlanking: [0, "No blanking"] + TIM1OC5: [1, "TIM1 OC5 selected as blanking source"] + TIM2OC3: [2, "TIM2 OC3 selected as blanking source"] + HYST: + NoHysteresis: [0, "No hysteresis"] + LowHysteresis: [1, "Low hysteresis"] + MediumHysteresis: [2, "Medium hysteresis"] + HighHysteresis: [3, "High hysteresis"] + POLARITY: + NotInverted: [0, "Output is not inverted"] + Inverted: [1, "Output is inverted"] + INMSEL: + OneQuarterVRef: [0, "1/4 of VRefint"] + OneHalfVRef: [1, "1/2 of VRefint"] + ThreeQuarterVRef: [2, "3/4 of VRefint"] + VRef: [3, "VRefint"] + DAC_CH1: [4, "DAC Channel 1"] + PB3: [6, "PB3"] + GPIO: [7, "GPIO pin selected by INMESEL"] + PWRMODE: + HighSpeed: [0, "High speed / full power"] + MediumSpeed: [1, "Medium speed / medium power"] + LowSpeed: [2, "Low speed / low power"] + VeryLowSpeed: [3, "Very-low speed / ultra-low power"] + EN: + Disabled: [0, "Comparator 1 disabled"] + Enabled: [1, "Comparator 1 enabled"] + + COMP1_CSR: + INMESEL: + PA10: [0, "PA10 connected to input minus"] + PA11: [1, "PA11 connected to input minus"] + PA15: [2, "PA15 connected to input minus"] + INPSEL: + PB4: [0, "PB4 connected to input plus"] + PB2: [1, "PB2 connected to input plus"] + + COMP2_CSR: + INMESEL: + PB2: [0, "PB2 connected to input minus"] + PA10: [1, "PA10 connected to input minus"] + PA11: [2, "PA11 connected to input minus"] + WINMODE: + Disabled: [0, "COMP2 input plus is not connected to COMP1"] + Enabled: [1, "COMP2 input plus is connected to COMP1"] + INPSEL: + PB4: [0, "PB4 connected to input plus"] + PB1: [1, "PB1 connected to input plus"] + PA15: [2, "PA15 connected to input plus"] diff --git a/peripherals/dac/dac_wl.yaml b/peripherals/dac/dac_wl.yaml new file mode 100644 index 000000000..bd0eb261f --- /dev/null +++ b/peripherals/dac/dac_wl.yaml @@ -0,0 +1,93 @@ +DAC: + "CR,CR?": + "CEN?": + Normal: [0, 'DAC Channel X Normal operating mode'] + Calibration: [1, 'DAC Channel X calibration mode'] + "DMAUDRIE?": + Disabled: [0, "DAC Channel X DMA Underrun Interrupt disabled"] + Enabled: [1, "DAC Channel X DMA Underrun Interrupt enabled"] + "DMAEN?": + Disabled: [0, "DAC Channel X DMA mode disabled"] + Enabled: [1, "DAC Channel X DMA mode enabled"] + "MAMP?": + Amp1: [0b0000, 'Unmask bit0 of LFSR/ triangle amplitude equal to 1'] + Amp3: [0b0001, 'Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3'] + Amp7: [0b0010, 'Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7'] + Amp15: [0b0011, 'Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15'] + Amp31: [0b0100, 'Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31'] + Amp63: [0b0101, 'Unmask bits[5:0] of LFSR/ triangle amplitude equal 63'] + Amp127: [0b0110, 'Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127'] + Amp255: [0b0111, 'Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255'] + Amp511: [0b1000, 'Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511'] + Amp1023: [0b1001, 'Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023'] + Amp2047: [0b1010, 'Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047'] + Amp4095: [0b1011, 'Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095'] + "WAVE?": + Disabled: [0, 'Wave generation disabled'] + Noise: [1, 'Noise wave generation enabled'] + Triangle: [2, 'Triangle wave generation enabled'] + "TSEL?": + SWTRIG: [0, 'SWTRIG1'] + TIM1_TRGO: [1, 'dac_chx_trg1'] + TIM2_TRGO: [2, 'dac_chx_trg2'] + TRG3: [3, 'dac_chx_trg3'] + TRG4: [4, 'dac_chx_trg4'] + TRG5: [5, 'dac_chx_trg5'] + TRG6: [6, 'dac_chx_trg6'] + TRG7: [7, 'dac_chx_trg7'] + TRG8: [8, 'dac_chx_trg8'] + TRG9: [9, 'dac_chx_trg9'] + TRG10: [10, 'dac_chx_trg10'] + LPTIM1_OUT: [11, 'dac_chx_trg11'] + LPTIM2_OUT: [12, 'dac_chx_trg12'] + LPTIM3_OUT: [13, 'dac_chx_trg13'] + EXTI9: [14, 'dac_chx_trg14'] + TRG15: [15, 'dac_chx_trg15'] + "TEN?": + Disabled: [0, "DAC Channel X trigger disabled"] + Enabled: [1, "DAC Channel X trigger enabled"] + "EN?": + Disabled: [0, "DAC Channel X disabled"] + Enabled: [1, "DAC Channel X enabled"] + + SWTRGR: + "SWTRIG?": + NoTrigger: [0, 'No trigger'] + Trigger: [1, 'Trigger'] + + "DOR?": + "DACC?DOR": [0, 4095] + + SR: + "BWST?": + Idle: [0, 'There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written'] + Busy: [1, 'There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written'] + "CAL_FLAG?": + Lower: [0, 'Calibration trimming value is lower than the offset correction value'] + Equal_Higher: [1, 'Calibration trimming value is equal or greater than the offset correction value'] + "DMAUDR?": + NoError: [0, 'No DMA underrun error condition occurred for DAC channel x'] + Error: [1, 'DMA underrun error condition occurred for DAC channel x (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)'] + + CCR: + "OTRIM?": [0, 63] + + MCR: + "MODE?": + NormalPinBuffer: [0b000, 'Normal mode - DAC channelx is connected to external pin with Buffer enabled'] + NormalPinChipBuffer: [0b001, 'Normal mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled'] + NormalPinNoBuffer: [0b010, 'Normal mode - DAC channelx is connected to external pin with Buffer disabled'] + NormalChipNoBuffer: [0b011, 'Normal mode - DAC channelx is connected to on chip peripherals with Buffer disabled'] + SHPinBuffer: [0b100, 'S&H mode - DAC channelx is connected to external pin with Buffer enabled'] + SHPinChipBuffer: [0b101, 'S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer enabled'] + SHPinNoBuffer: [0b110, 'S&H mode - DAC channelx is connected to external pin and to on chip peripherals with Buffer disabled'] + SHChipNoBuffer: [0b111, 'S&H mode - DAC channelx is connected to on chip peripherals with Buffer disabled'] + + "SHSR?": + "TSAMPLE?": [0, 1023] + + SHHR: + "THOLD?": [0, 1023] + + SHRR: + "TREFRESH?": [0, 255] diff --git a/peripherals/dac/dac_wl_12bit.yaml b/peripherals/dac/dac_wl_12bit.yaml new file mode 100644 index 000000000..7819a7d27 --- /dev/null +++ b/peripherals/dac/dac_wl_12bit.yaml @@ -0,0 +1,6 @@ +DAC: + "DHR12R?": + "DACC?DHR": [0, 4095] + + "DHR12L?": + "DACC?DHR": [0, 4095] diff --git a/peripherals/dac/dac_wl_8bit.yaml b/peripherals/dac/dac_wl_8bit.yaml new file mode 100644 index 000000000..d902f6f32 --- /dev/null +++ b/peripherals/dac/dac_wl_8bit.yaml @@ -0,0 +1,3 @@ +DAC: + "DHR8R?": + "DACC?DHR": [0, 255] diff --git a/peripherals/dbg/dbg_wl.yaml b/peripherals/dbg/dbg_wl.yaml new file mode 100644 index 000000000..a950758a0 --- /dev/null +++ b/peripherals/dbg/dbg_wl.yaml @@ -0,0 +1,46 @@ +# Debug registers for WL + +DBGMCU: + IDCODER: + _read: + REV_ID: [0, 65535] + _read: + DEV_ID: [0, 4095] + CR: + DBG_STANDBY: + Disabled: [0, "Debug Standby Mode Disabled"] + Enabled: [1, "Debug Standby Mode Enabled"] + DBG_STOP: + Disabled: [0, "Debug Stop Mode Disabled"] + Enabled: [1, "Debug Stop Mode Enabled"] + DBG_SLEEP: + Disabled: [0, "Debug Sleep Mode Disabled"] + Enabled: [1, "Debug Sleep Mode Enabled"] + APB1FZR1: + DBG_LPTIM1_STOP: + Continue: [0, "LPTIM1 counter clock is fed even if the core is halted"] + Stop: [1, "LPTIM1 counter clock is stopped when the core is halted"] + "DBG_I2C*_STOP": + NormalMode: [0, "Same behavior as in normal mode"] + SMBusTimeoutFrozen: [1, "I2C3 SMBUS timeout is frozen"] + DBG_IWDG_STOP: + Continue: [0, "The independent watchdog counter clock continues even if the core is halted"] + Stop: [1, "The independent watchdog counter clock is stopped when the core is halted"] + DBG_WWDG_STOP: + Continue: [0, "The window watchdog counter clock continues even if the core is halted"] + Stop: [1, "The window watchdog counter clock is stopped when the core is halted"] + DBG_RTC_STOP: + Continue: [0, "The clock of the RTC counter is fed even if the core is halted"] + Stop: [1, "The clock of the RTC counter is stopped when the core is halted"] + "DBG_TIM*_STOP": + Continue: [0, "The counter clock of TIMx is fed even if the core is halted"] + Stop: [1, "The counter clock of TIMx is stopped when the core is halted"] + APB1FZR2: + DBG_LPTIM?_STOP: + Continue: [0, "LPTIM1 counter clock is fed even if the core is halted"] + Stop: [1, "LPTIM1 counter clock is stopped when the core is halted"] + + APB2FZR: + "DBG_TIM*_STOP": + Continue: [0, "The counter clock of TIMx is fed even if the core is halted"] + Stop: [1, "The counter clock of TIMx is stopped when the core is halted"] diff --git a/peripherals/dma/dma_wl.yaml b/peripherals/dma/dma_wl.yaml new file mode 100644 index 000000000..98fa63576 --- /dev/null +++ b/peripherals/dma/dma_wl.yaml @@ -0,0 +1,76 @@ +"DMA[12]": + ISR: + "TCIF?": + NotComplete: [0, "No transfer complete event on channel x"] + Complete: [1, "A transfer complete event occurred on channel x"] + "HTIF?": + NotHalf: [0, "No half transfer event on channel x"] + Half: [1, "A half transfer event occurred on channel x"] + "TEIF?": + NoError: [0, "No transfer error on channel x"] + Error: [1, "A transfer error occurred on channel x"] + "GIF?": + NoEvent: [0, "No TE, HT or TC event on channel x"] + Event: [1, "A TE, HT or TC event occurred on channel x"] + IFCR: + "TCIF?": + Clear: [1, "Clear the corresponding TCIFx flag"] + "HTIF?": + Clear: [1, "Clear the corresponding HTIFx flag"] + "TEIF?": + Clear: [1, "Clear the corresponding TEIFx flag"] + "GIF?": + Clear: [1, "Clear the corresponding CGIFx flag"] + "CCR?": + PRIV: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + MEM2MEM: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + PL: + Low: [0, "Low"] + Medium: [1, "Medium"] + High: [2, "High"] + VeryHigh: [3, "Very high"] + MSIZE: + Bits8: [0, "8 bits"] + Bits16: [1, "16 bits"] + Bits32: [2, "32 bits"] + PSIZE: + Bits8: [0, "8 bits"] + Bits16: [1, "16 bits"] + Bits32: [2, "32 bits"] + MINC: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + PINC: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + CIRC: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + DIR: + Peripheral: [0, "Read from peripheral"] + Memory: [1, "Read from memory"] + TEIE: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + HTIE: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + TCIE: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + EN: + Disabled: [0, "Disabled"] + Enabled: [1, "Enabled"] + + "CNDTR?": + NDT: [0, 0x3FFFF] + + "CPAR?": + PA: [0, 0xFFFFFFFF] + + "CMAR?": + MA: [0, 0xFFFFFFFF] diff --git a/peripherals/dma/dmamux_wl.yaml b/peripherals/dma/dmamux_wl.yaml new file mode 100644 index 000000000..7f8e688b3 --- /dev/null +++ b/peripherals/dma/dmamux_wl.yaml @@ -0,0 +1,137 @@ +DMAMUX: + "C?CR": + SYNC_ID: + exti0: [0, "Signal `EXTIx` selected as synchronization input"] + exti1: [1, "Signal `EXTIx` selected as synchronization input"] + exti2: [2, "Signal `EXTIx` selected as synchronization input"] + exti3: [3, "Signal `EXTIx` selected as synchronization input"] + exti4: [4, "Signal `EXTIx` selected as synchronization input"] + exti5: [5, "Signal `EXTIx` selected as synchronization input"] + exti6: [6, "Signal `EXTIx` selected as synchronization input"] + exti7: [7, "Signal `EXTIx` selected as synchronization input"] + exti8: [8, "Signal `EXTIx` selected as synchronization input"] + exti9: [9, "Signal `EXTIx` selected as synchronization input"] + exti10: [10, "Signal `EXTIx` selected as synchronization input"] + exti11: [11, "Signal `EXTIx` selected as synchronization input"] + exti12: [12, "Signal `EXTIx` selected as synchronization input"] + exti13: [13, "Signal `EXTIx` selected as synchronization input"] + exti14: [14, "Signal `EXTIx` selected as synchronization input"] + exti15: [15, "Signal `EXTIx` selected as synchronization input"] + dmamux1_evt0: [16, "Signal `dmamux1_evt0` selected as synchronization input"] + dmamux1_evt1: [17, "Signal `dmamux1_evt1` selected as synchronization input"] + lptim1_out: [18, "Signal `lptim1_out` selected as synchronization input"] + lptim2_out: [19, "Signal `lptim2_out` selected as synchronization input"] + lptim3_out: [20, "Signal `lptim3_out` selected as synchronization input"] + NBREQ: [0, 31] + SPOL: + NoEdge: [0, "No event, i.e. no synchronization nor detection"] + RisingEdge: [1, "Rising edge"] + FallingEdge: [2, "Falling edge"] + BothEdges: [3, "Rising and falling edges"] + SE: + Disabled: [0, "Synchronization disabled"] + Enabled: [1, "Synchronization enabled"] + EGE: + Disabled: [0, "Event generation disabled"] + Enabled: [1, "Event generation enabled"] + SOIE: + Disabled: [0, "Synchronization overrun interrupt disabled"] + Enabled: [1, "Synchronization overrun interrupt enabled"] + DMAREQ_ID: + none: [0, "No signal selected as request input"] + dmamux1_req_gen0: [1, "Signal `dmamux1_req_gen0` selected as request input"] + dmamux1_req_gen1: [2, "Signal `dmamux1_req_gen1` selected as request input"] + dmamux1_req_gen2: [3, "Signal `dmamux1_req_gen2` selected as request input"] + dmamux1_req_gen3: [4, "Signal `dmamux1_req_gen3` selected as request input"] + adc: [5, "Signal `adc1_dma` selected as request input"] + dat_out1: [6, "Signal `dac_out1_dma` selected as request input"] + spi1_rx_dma: [7, "Signal `spi1_rx_dma` selected as request input"] + spi1_tx_dma: [8, "Signal `spi1_tx_dma` selected as request input"] + spi2_rx_dma: [9, "Signal `spi2_rx_dma` selected as request input"] + spi2_tx_dma: [10, "Signal `spi2_tx_dma` selected as request input"] + i2c1_rx_dma: [11, "Signal `i2c1_rx_dma` selected as request input"] + i2c1_tx_dma: [12, "Signal `i2c1_tx_dma` selected as request input"] + i2c2_rx_dma: [13, "Signal `i2c2_rx_dma` selected as request input"] + i2c2_tx_dma: [14, "Signal `i2c2_tx_dma` selected as request input"] + i2c3_rx_dma: [15, "Signal `i2c3_rx_dma` selected as request input"] + i2c3_tx_dma: [16, "Signal `i2c3_tx_dma` selected as request input"] + usart1_rx_dma: [17, "Signal `usart1_rx_dma` selected as request input"] + usart1_tx_dma: [18, "Signal `usart1_tx_dma` selected as request input"] + usart2_rx_dma: [19, "Signal `usart2_rx_dma` selected as request input"] + usart2_tx_dma: [20, "Signal `usart2_tx_dma` selected as request input"] + lpuart1_rx_dma: [21, "Signal `lpuart1_rx_dma` selected as request input"] + lpuart1_tx_dma: [22, "Signal `lpuart1_tx_dma` selected as request input"] + tim1_ch1: [23, "Signal `tim1_ch1` selected as request input"] + tim1_ch2: [24, "Signal `tim1_ch2` selected as request input"] + tim1_ch3: [25, "Signal `tim1_ch3` selected as request input"] + tim1_ch4: [26, "Signal `tim1_ch4` selected as request input"] + tim1_up: [27, "Signal `tim1_up` selected as request input"] + tim1_trig: [28, "Signal `tim1_trig` selected as request input"] + tim1_com: [29, "Signal `tim1_com` selected as request input"] + tim2_ch1: [30, "Signal `tim2_ch1` selected as request input"] + tim2_ch2: [31, "Signal `tim2_ch2` selected as request input"] + tim2_ch3: [32, "Signal `tim2_ch3` selected as request input"] + tim2_ch4: [33, "Signal `tim2_ch4` selected as request input"] + tim2_up: [34, "Signal `tim2_up` selected as request input"] + tim16_ch1: [35, "Signal `tim16_ch1` selected as request input"] + tim16_up: [36, "Signal `tim16_up` selected as request input"] + tim17_ch1: [37, "Signal `tim17_ch1` selected as request input"] + tim17_up: [38, "Signal `tim17_up` selected as request input"] + aes_in: [39, "Signal `aes_in` selected as request input"] + aes_out: [40, "Signal `aes_out` selected as request input"] + subghzspi_rx: [41, "Signal `subghzspi_rx` selected as request input"] + subghzspi_tx: [42, "Signal `subghzspi_tx` selected as request input"] + "RG?CR": + GNBREQ: [0, 31] + GPOL: + NoEdge: [0, "No event, i.e. no detection nor generation"] + RisingEdge: [1, "Rising edge"] + FallingEdge: [2, "Falling edge"] + BothEdges: [3, "Rising and falling edges"] + GE: + Disabled: [0, "DMA request generation disabled"] + Enabled: [1, "DMA request enabled"] + OIE: + Disabled: [0, "Trigger overrun interrupt disabled"] + Enabled: [1, "Trigger overrun interrupt enabled"] + SIG_ID: + exti0: [0, "Signal `EXTIx` selected as synchronization input"] + exti1: [1, "Signal `EXTIx` selected as synchronization input"] + exti2: [2, "Signal `EXTIx` selected as synchronization input"] + exti3: [3, "Signal `EXTIx` selected as synchronization input"] + exti4: [4, "Signal `EXTIx` selected as synchronization input"] + exti5: [5, "Signal `EXTIx` selected as synchronization input"] + exti6: [6, "Signal `EXTIx` selected as synchronization input"] + exti7: [7, "Signal `EXTIx` selected as synchronization input"] + exti8: [8, "Signal `EXTIx` selected as synchronization input"] + exti9: [9, "Signal `EXTIx` selected as synchronization input"] + exti10: [10, "Signal `EXTIx` selected as synchronization input"] + exti11: [11, "Signal `EXTIx` selected as synchronization input"] + exti12: [12, "Signal `EXTIx` selected as synchronization input"] + exti13: [13, "Signal `EXTIx` selected as synchronization input"] + exti14: [14, "Signal `EXTIx` selected as synchronization input"] + exti15: [15, "Signal `EXTIx` selected as synchronization input"] + dmamux1_evt0: [16, "Signal `dmamux1_evt0` selected as synchronization input"] + dmamux1_evt1: [17, "Signal `dmamux1_evt1` selected as synchronization input"] + lptim1_out: [18, "Signal `lptim1_out` selected as synchronization input"] + lptim2_out: [19, "Signal `lptim2_out` selected as synchronization input"] + lptim3_out: [20, "Signal `lptim3_out` selected as synchronization input"] + CSR: + "SOF[0123456789]": + NoSyncEvent: [0, "No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ"] + SyncEvent: [1, "Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ"] + "SOF1[0123]": + NoSyncEvent: [0, "No synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ"] + SyncEvent: [1, "Synchronization event occured on a DMA request line multiplexer channel x, while the DMA request counter value is lower than NBREQ"] + CCFR: + "CSOF[0123456789]": + Clear: [1, "Clear synchronization flag"] + "CSOF1[0123]": + Clear: [1, "Clear synchronization flag"] + RGSR: + "OF[0123]": + NoTrigger: [0, "No new trigger event occured on DMA request generator channel x, before the request counter underrun"] + Trigger: [1, "New trigger event occured on DMA request generator channel x, before the request counter underrun"] + RGCFR: + "COF[0123]": + Clear: [1, "Clear overrun flag"] diff --git a/peripherals/flash/flash_wl.yaml b/peripherals/flash/flash_wl.yaml new file mode 100644 index 000000000..774bd2980 --- /dev/null +++ b/peripherals/flash/flash_wl.yaml @@ -0,0 +1,256 @@ +FLASH: + ACR: + EMPTY: + Programmed: [0, "User Flash programmend"] + Empty: [1, "User Flash empty"] + PES: + Granted: [0, "Flash program and erase operations granted"] + Suspended: [1, "Any new Flash program and erase operation is suspended until this bit is cleared. The PESD bit in FLASH_SR is set when PES bit in FLASH_ACRis set"] + DCRST: + NotReset: [0, "Data cache is not reset"] + Reset: [1, "Data cache is reset"] + ICRST: + NotReset: [0, "Instruction cache is not reset"] + Reset: [1, "Instruction cache is reset"] + DCEN: + Disabled: [0, "Data cache is disabled"] + Enabled: [1, "Data cache is enabled"] + ICEN: + Disabled: [0, "Instruction cache is disabled"] + Enabled: [1, "Instruction cache is enabled"] + PRFTEN: + Disabled: [0, "Prefetch is disabled"] + Enabled: [1, "Prefetch is enabled"] + LATENCY: + WS0: [0, "0 wait states"] + WS1: [1, "1 wait states"] + WS2: [2, "2 wait states"] + + KEYR: + KEY: [0, 0xFFFFFFFF] + + OPTKEYR: + OPTKEY: [0, 0xFFFFFFFF] + + + SR: + _modify: + OPTVN: + name: OPTNV + MISERR: + name: MISSERR + PESD: + Granted: [0, "Flash program and erase operations granted"] + Suspended: [1, "Any new Flash program and erase operation is suspended until this bit is cleared. This bit is set when the PES bit in FLASH_ACR is set"] + CFGBSY: + Free: [0, "PG, PNB, PER, MER bits available for writing"] + Busy: [1, "PG, PNB, PER, MER bits not available for writing (operation ongoing)"] + BSY: + Inactive: [0, "No write/erase operation is in progress"] + Active: [1, "No write/erase operation is in progress"] + OPTVERR: + _read: + NoError: [0, "No error in option and engineering bits"] + Error: [1, "Error in option and engineering bits"] + _write: + Clear: [1, "Clear the flag"] + RDERR: + _read: + NoError: [0, "No read-only error happened"] + Error: [1, "Read-only error happened"] + _write: + Clear: [1, "Clear the flag"] + OPTNV: + Valid: [0, "The OBL user option OPTVAL indicates \"valid\""] + Invalid: [1, "The OBL user option OPTVAL indicates \"invalid\""] + FASTERR: + _read: + NoError: [0, "No fast programming error happened"] + Error: [1, "Fast programming error happened"] + _write: + Clear: [1, "Clear the flag"] + MISSERR: + _read: + NoError: [0, "No fast programming data miss error happened"] + Error: [1, "Fast programming data miss error happened"] + _write: + Clear: [1, "Clear the flag"] + PGSERR: + _read: + NoError: [0, "No fast programming sequence error happened"] + Error: [1, "Fast programming sequence error happened"] + _write: + Clear: [1, "Clear the flag"] + SIZERR: + _read: + NoError: [0, "No size error happened"] + Error: [1, "Size error happened"] + _write: + Clear: [1, "Clear the flag"] + PGAERR: + _read: + NoError: [0, "No programming alignment error happened"] + Error: [1, "Programming alignment error happened"] + _write: + Clear: [1, "Clear the flag"] + WRPERR: + _read: + NoError: [0, "No write protection error happened"] + Error: [1, "Write protection error happened"] + _write: + Clear: [1, "Clear the flag"] + PROGERR: + _read: + NoError: [0, "No size programming error happened"] + Error: [1, "Programming error happened"] + _write: + Clear: [1, "Clear the flag"] + OPERR: + _read: + NoError: [0, "No memory opreation error happened"] + Error: [1, "Memory operation error happened"] + _write: + Clear: [1, "Clear the flag"] + EOP: + _read: + NoEvent: [0, "No EOP operation occurred"] + Event: [1, "An EOP event occurred"] + _write: + Clear: [1, "Clear the flag"] + CR: + LOCK: + _read: + Unlocked: [0, "FLASH_CR is unlocked"] + _write: + Locked: [1, "FLASH_CR is locked"] + OPTLOCK: + _read: + Unlocked: [0, "FLASH_CR options are unlocked"] + _write: + Locked: [1, "FLASH_CR options are locked"] + OBL_LAUNCH: + _read: + Complete: [0, "Option byte loaded"] + NotComplete: [1, "Option byte loading to be done"] + _write: + Reload: [1, "Reload option byte"] + RDERRIE: + Disabled: [0, "PCROP read error interrupt disable"] + Enabled: [1, "PCROP read error interrupt enable"] + ERRIE: + Disabled: [0, "OPERR Error interrupt disable"] + Enabled: [1, "OPERR Error interrupt enable"] + EOPIE: + Disabled: [0, "End of program interrupt disable"] + Enabled: [1, "End of program interrupt enable"] + FSTPG: + Disabled: [0, "Fast programming disabled"] + Enabled: [1, "Fast programming enabled"] + OPTSTRT: + _read: + Done: [0, "Options modification completed or idle"] + _write: + Start: [1, "Trigger options programming operation"] + STRT: + _read: + Done: [0, "Options modification completed or idle"] + _write: + Start: [1, "Trigger options programming operation"] + PNB: [0, 0x63] + MER: + NoErase: [0, "No mass erase"] + MassErase: [1, "Trigger mass erase"] + PER: + Disabled: [0, "Page erase disabled"] + Enabled: [1, "Page erase enabled"] + PG: + Disabled: [0, "Flash programming disabled"] + Enabled: [1, "Flash programming enabled"] + + ECCR: + ECCD: + _read: + NoEvent: [0, "Two ECC errors detected"] + Event: [1, "No two ECC errors detected"] + _write: + Clear: [1, "Clear the flag"] + ECCC: + _read: + NoEvent: [0, "ECC error corrected"] + Event: [1, "No ECC error corrected"] + _write: + Clear: [1, "Clear the flag"] + ECCCIE: + Disabled: [0, "ECCC interrupt disabled"] + Enabled: [1, "ECCC interrupt enabled"] + SYSF_ECC: + NotInFlash: [0, "No System Flash memory ECC fail"] + InFlash: [1, "System Flash memory ECC fail"] + ADDR_ECC: [0, 0x1FFFF] + OPTR: + _modify: + SRAM2_RST: + name: SRAM_RST + BOOT_LOCK: + Disabled: [0, "Boot lock is disabled"] + Enabled: [1, "Boot lock is enabled"] + nBOOT0: + Clear: [0, "When nSWBOOT0 is cleared, select boot mode together with nBOOT1"] + Set: [1, "When nSWBOOT0 is cleared, select boot mode together with nBOOT1"] + nSWBOOT0: + Bit: [0, "BOOT0 taken from nBOOT0 in this register"] + Pin: [1, "BOOT0 taken from GPIO PH3/BOOT0"] + SRAM_RST: + Reset: [0, "SRAM1 and SRAM2 erased when a system reset occurs"] + NotReset: [1, "SRAM1 and SRAM2 not erased when a system reset occurs"] + SRAM2_PE: + Enabled: [0, "SRAM2 Parity check enabled"] + Disabled: [1, "SRAM2 Parity check disabled"] + nBOOT1: + Clear: [0, "When nSWBOOT0 is cleared, select boot mode together with nBOOT0"] + Set: [1, "When nSWBOOT0 is cleared, select boot mode together with nBOOT0"] + WWDG_SW: + Hardware: [0, "Hardware window watchdog"] + Software: [1, "Software window watchdog"] + IWDG_STDBY: + Frozen: [0, "Independent watchdog counter frozen in Standby mode"] + Running: [1, "Independent watchdog counter running in Standby mode"] + IWDG_STOP: + Frozen: [0, "Independent watchdog counter frozen in Stop mode"] + Running: [1, "Independent watchdog counter running in Stop mode"] + IWDG_SW: + Hardware: [0, "Hardware independent watchdog"] + Software: [1, "Software independent watchdog"] + nRST_SHDW: + Enabled: [0, "Reset generated when entering the Shutdown mode"] + Disabled: [1, "No reset generated when entering the Shutdown mode"] + nRST_STDBY: + Enabled: [0, "Reset generated when entering the Standby mode"] + Disabled: [1, "No reset generated when entering the Standby mode"] + nRST_STOP: + Enabled: [0, "Reset generated when entering the Standby mode"] + Disabled: [1, "No reset generated when entering the Standby mode"] + BOR_LEV: + Level0: [0, "BOR level 0. Reset level threshold is around 1.7 V"] + Level1: [1, "BOR level 1. Reset level threshold is around 2.0 V"] + Level2: [2, "BOR level 2. Reset level threshold is around 2.2 V"] + Level3: [3, "BOR level 3. Reset level threshold is around 2.5 V"] + Level4: [4, "BOR level 4. Reset level threshold is around 2.8 V"] + ESE: + Disabled: [0, "Security disabled"] + Enabled: [1, "Security enabled"] + RDP: + Level0: [0xAA, "Level 0, readout protection not active"] + Level2: [0xCC, "Level 2, chip readout protection active"] + # The manual specifies "Others" for Level 1, 0x88 is arbitrary + # Since the reset value is AA, the value for Level 1 needs to be written + # so there is no conflict reading other values (unless unsafe is used) + Level1: [0x88, "Level 1, memories readout protection active (writes 0x88)"] + + "PCROP1?SR": + "PCROP1?_STRT": [0, 0xFF] + "PCROP1?ER": + "PCROP1?_END": [0, 0xFF] + "WRP1?R": + "WRP1?_END": [0, 0x7F] + "WRP1?_STRT": [0, 0x7F] diff --git a/peripherals/gpio/gpio_wl_with_brr.yaml b/peripherals/gpio/gpio_wl_with_brr.yaml new file mode 100644 index 000000000..104ce3412 --- /dev/null +++ b/peripherals/gpio/gpio_wl_with_brr.yaml @@ -0,0 +1,28 @@ +# Some GPIO appear to have BRR registers + +"GPIO[AB]": + BRR: + "BR[0123456789]": + _write: + NoAction: [0, "No action on the corresponding ODx bit"] + Reset: [1, "Reset the ODx bit"] + "BR1[012345]": + _write: + NoAction: [0, "No action on the corresponding ODx bit"] + Reset: [1, "Reset the ODx bit"] +"GPIOC": + BRR: + "BR[0123456]": + _write: + NoAction: [0, "No action on the corresponding ODx bit"] + Reset: [1, "Reset the ODx bit"] + "BR1[345]": + _write: + NoAction: [0, "No action on the corresponding ODx bit"] + Reset: [1, "Reset the ODx bit"] +"GPIOH": + BRR: + "BR3": + _write: + NoAction: [0, "No action on the corresponding ODx bit"] + Reset: [1, "Reset the ODx bit"] diff --git a/peripherals/hsem/hsem_wl.yaml b/peripherals/hsem/hsem_wl.yaml new file mode 100644 index 000000000..cea2df1f6 --- /dev/null +++ b/peripherals/hsem/hsem_wl.yaml @@ -0,0 +1,80 @@ +"HSEM": + "R[0123456789]": + LOCK: + _read: + Free: [0, "Semaphore is free"] + Locked: [1, "Semaphore is locked"] + _write: + Free: [0, "Free semaphore"] + TryLock: [1, "Try to lock semaphore"] + COREID: [0, 0xF] + PROCID: [0, 0xFF] + "R1[012345]": + LOCK: + _read: + Free: [0, "Semaphore is free"] + Locked: [1, "Semaphore is locked"] + _write: + Free: [0, "Free semaphore"] + TryLock: [1, "Try to lock semaphore"] + COREID: [0, 0xF] + PROCID: [0, 0xFF] + "RLR[0123456789]": + LOCK: + _read: + Free: [0, "Semaphore is free"] + Locked: [1, "Semaphore is locked"] + _write: + Free: [0, "Free semaphore"] + TryLock: [1, "Try to lock semaphore"] + COREID: [0, 0xF] + PROCID: [0, 0xFF] + "RLR1[012345]": + LOCK: + _read: + Free: [0, "Semaphore is free"] + Locked: [1, "Semaphore is locked"] + _write: + Free: [0, "Free semaphore"] + TryLock: [1, "Try to lock semaphore"] + COREID: [0, 0xF] + PROCID: [0, 0xFF] + C?IER: + "ISE[0123456789]": + Disabled: [0, "Interrupt generation disabled"] + Enabled: [1, "Interrupt generation enabled"] + "ISE1[012345]": + Disabled: [0, "Interrupt generation disabled"] + Enabled: [1, "Interrupt generation enabled"] + C?ICR: + "ISC[0123456789]": + _read: + NoEffect: [0, "Always reads 0"] + _write: + NoEffect: [0, "Interrupt semaphore x status ISFx and masked status MISFx not affected"] + Clear : [1, "Interrupt semaphore x status ISFx and masked status MISFx cleared"] + "ISC1[012345]": + _read: + NoEffect: [0, "Always reads 0"] + _write: + NoEffect: [0, "Interrupt semaphore x status ISFx and masked status MISFx not affected"] + Clear : [1, "Interrupt semaphore x status ISFx and masked status MISFx cleared"] + C?ISR: + "ISF[0123456789]": + NotPending: [0, "No interrupt pending"] + Pending: [1, "Interrupt pending"] + "ISF1[012345]": + NotPending: [0, "No interrupt pending"] + Pending: [1, "Interrupt pending"] + C?MISR: + "MISF[0123456789]": + NotPending: [0, "No interrupt pending after masking"] + Pending: [1, "Interrupt pending after masking"] + "MISF1[012345]": + NotPending: [0, "No interrupt pending after masking"] + Pending: [1, "Interrupt pending after masking"] + CR: + KEY: [0, 0xFFFF] + COREID: [0, 0xF] + KEYR: + KEY: [0, 0xFFFF] diff --git a/peripherals/iwdg/iwdg_sr.yaml b/peripherals/iwdg/iwdg_sr.yaml new file mode 100644 index 000000000..018a09f93 --- /dev/null +++ b/peripherals/iwdg/iwdg_sr.yaml @@ -0,0 +1,11 @@ +"IWDG,IWDG?": + SR: + WVU: + Idle: [0, "No update on-going"] + Busy: [1, "Update on-going"] + RVU: + Idle: [0, "No update on-going"] + Busy: [1, "Update on-going"] + PVU: + Idle: [0, "No update on-going"] + Busy: [1, "Update on-going"] diff --git a/peripherals/lptim/lptim_wl.yaml b/peripherals/lptim/lptim_wl.yaml new file mode 100644 index 000000000..38cd7502f --- /dev/null +++ b/peripherals/lptim/lptim_wl.yaml @@ -0,0 +1,52 @@ +LPTIM,LPTIM?: + ISR: + REPOK: + _read: + Set: [1, "Repetition register update OK"] + UE: + _read: + Set: [1, "LPTIM update event occurred"] + ICR: + REPOKCF: + _write: + Clear: [1, "Clear REPOK flag"] + UECF: + _write: + Clear: [1, "Clear update event flag"] + IER: + REPOKIE: + Disabled: [0, "Repetition register update OK interrupt disabled"] + Enabled: [1, "Repetition register update OK interrupt enabled"] + UEIE: + Disabled: [0, "Update event interrupt disabled"] + Enabled: [1, "Update event interrupt enabled"] + + CR: + RSTARE: + Disabled: [0, "CNT Register reads do not trigger reset"] + Enabled: [1, "CNT Register reads trigger reset of LPTIM"] + COUNTRST: + _write: + Reset: [1, "Trigger synchronous reset of CNT (3 LPTimer core clock cycles)"] + _read: + Idle: [0, "Triggering of reset is possible"] + Busy: [1, "Reset in progress, do not write 1 to this field"] + RCR: + REP: [0, 0xFF] + +LPTIM1: + OR: + OR_1: + IO: [0, "LPTIM1 input 2 is connected to I/O"] + COMP2_OUT: [1, "LPTIM1 input 2 is connected to COMP2_OUT"] + OR_0: + IO: [0, "LPTIM1 input 1 is connected to I/O"] + COMP1_OUT: [1, "LPTIM1 input 1 is connected to COMP1_OUT"] + +LPTIM[23]: + OR: + OR_: + IO: [0, "Input 1 is connected to I/O"] + COMP1_OUT: [1, "Input 1 is connected to COMP1_OUT"] + COMP2_OUT: [2, "Input 1 is connected to COMP2_OUT"] + OR_COMP1_COMP2: [3, "Input 1 is connected to COMP1_OUT OR COMP2_OUT"] diff --git a/peripherals/pka/pka.yaml b/peripherals/pka/pka.yaml new file mode 100644 index 000000000..01bbbcafb --- /dev/null +++ b/peripherals/pka/pka.yaml @@ -0,0 +1,59 @@ +PKA: + CR: + ADDRERRIE: + Disabled: [0, 'No interrupt is generated when ADDRERRF flag is set in PKA_SR'] + Enabled: [1, 'An interrupt is generated when ADDRERRF flag is set in PKA_SR'] + RAMERRIE: + Disabled: [0, 'No interrupt is generated when RAMERRF flag is set in PKA_SR'] + Enabled: [1, 'An interrupt is generated when RAMERRF flag is set in PKA_SR'] + PROCENDIE: + Disabled: [0, 'No interrupt is generated when PROCENDF flag is set in PKA_SR'] + Enabled: [1, 'An interrupt is generated when PROCENDF flag is set in PKA_SR'] + MODE: + MontgomeryCompExp: [0b000000, 'Montgomery parameter computation then modular exponentiation'] + MontgomeryComp: [0b000001, 'Montgomery parameter computation only'] + MontgomeryExp: [0b000010, 'Modular exponentiation only (Montgomery parameter must be loaded first)'] + MontgomeryCompScalar: [0b100000, 'Montgomery parameter computation then ECC scalar multiplication'] + MontgomeryScalar: [0b100010, 'ECC scalar multiplication only (Montgomery parameter must be loaded first)'] + ECDSASign: [0b100100, 'ECDSA sign'] + ECDSAVerif: [0b100110, 'ECDSA verification'] + Elliptic: [0b101000, 'Point on elliptic curve Fp check'] + RSA: [0b000111, 'RSA CRT exponentiation'] + ModularInv: [0b001000, 'Modular inversion'] + ArithmeticAdd: [0b001001, 'Arithmetic addition'] + ArithmeticSub: [0b001010, 'Arithmetic subtraction'] + ArithmeticMul: [0b001011, 'Arithmetic multiplication'] + ArithmeticComp: [0b001100, 'Arithmetic comparison'] + ModularRed: [0b001101, 'Modular reduction'] + ModularAdd: [0b001110, 'Modular addition'] + ModularSub: [0b001111, 'Modular subtraction'] + ModularMul: [0b010000, 'Montgomery multiplication'] + START: + _write: + Start: [1, 'Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands +and data already written to the PKA RAM - This bit is always read as 0'] + EN: + Disabled: [0, 'Disable PKA'] + Enabled: [1, 'Enable PKA'] + + SR: + ADDRERRF: + NoError: [0, 'No error'] + Error: [1, 'Address access is out of range (unmapped address)'] + RAMERRF: + NoError: [0, 'No error'] + Error: [1, 'An AHB access to the PKA RAM occurred while the PKA core was computing and using its internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress)'] + PROCENDF: + InProgress: [0, 'Operation in progress'] + Completed: [1, 'PKA operation is completed - set when BUSY is deasserted'] + BUSY: + Idle: [0, 'No operation in pgoress'] + Busy: [1, 'Operation in progress'] + + CLRFR: + ADDRERRFC: + Clear: [1, 'Clear ADDRERRF flag'] + RAMERRFC: + Clear: [1, 'Clear RAMERRF flag'] + PROCENDFC: + Clear: [1, 'Clear PROCENDF flag'] diff --git a/peripherals/pwr/pwr_wl.yaml b/peripherals/pwr/pwr_wl.yaml new file mode 100644 index 000000000..91180c129 --- /dev/null +++ b/peripherals/pwr/pwr_wl.yaml @@ -0,0 +1,241 @@ +PWR: + CR1: + LPR: + MainMode: [0, "Voltage regulator in Main mode in Low-power run mode"] + LowPowerMode: [1, "Voltage regulator in low-power mode in Low-power run mode"] + VOS: + V1_2: [1, "1.2 V (range 1)"] + V1_0: [2, "1.0 V (range 2)"] + DBP: + Disabled: [0, "Access to RTC and backup registers disabled"] + Enabled: [1, "Access to RTC and backup registers enabled"] + FPDS: + Idle: [0, "Flash memory in Idle mode when system is in LPSleep mode"] + PowerDown: [1, "Flash memory in Power-down mode when system is in LPSleep mode"] + FPDR: + Idle: [0, "Flash memory in Idle mode when system is in LPRun mode"] + PowerDown: [1, "Flash memory in Power-down mode when system is in LPRun mode"] + SUBGHZSPINSSSEL: + SUBGHZSPICR: [0, "sub-GHz SPI NSS signal driven from PWR_SUBGHZSPICR.NSS (RFBUSYMS functionality enabled)"] + LPTIM3: [1, "sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled)"] + LPMS: + Stop0: [0, "Stop 0 mode"] + Stop1: [1, "Stop 1 mode"] + Stop2: [2, "Stop 2 mode"] + Standby: [3, "Standby mode"] + Shutdown: [4, "Shutdown mode"] + CR2: + PVME3: + Disabled: [0, "PVM3 (VDDA monitoring versus 1.62 V threshold) disable"] + Enabled: [1, "PVM3 (VDDA monitoring versus 1.62 V threshold) enable"] + PLS: + V2_0: [0, "2.0V"] + V2_2: [1, "2.2V"] + V2_4: [2, "2.4V"] + V2_5: [3, "2.5V"] + V2_6: [4, "2.6V"] + V2_8: [5, "2.8V"] + V2_9: [6, "2.9V"] + External: [7, "External input analog voltage PVD_IN (compared internally to VREFINT)"] + PVDE: + Disabled: [0, "PVD Disabled"] + Enabled: [1, "PVD Enabled"] + CR3: + EIWUL: + Disabled: [0, "Internal wakeup line interrupt to CPU disabled"] + Enabled: [1, "Internal wakeup line interrupt to CPU enabled"] + EWRFIRQ: + Disabled: [0, "Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU."] + Enabled: [1, "Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU."] + EWRFBUSY: + Disabled: [0, "Radio Busy is disabled and does not trigger a wakeup from Standby event to CPUwhen a rising or a falling edge occurs"] + Enabled: [1, "Radio Busy is enabled and triggers a wakeup from Standby event to CPUwhen a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4"] + APC: + Disabled: [0, "I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied"] + Enabled: [1, "PWR_PUCRx and PWR_PDCRx registers are NOT applied to the I/Os"] + RRS: + PowerOff: [0, "SRAM2 powered off in Standby mode (SRAM2 content lost)"] + OnLPR: [1, "SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)"] + EWPVD: + Disabled: [0, "PVD not enabled by the sub-GHz radio active state"] + Enabled: [1, "PVD enabled while the sub-GHz radio is active"] + EULPEN: + Disabled: [0, "Disable (the supply voltage is monitored continuously)"] + Enabled: [1, "Enable, when set, the supply voltage is sampled for PDR/BOR reset condition only periodically"] + EWUP3: + Disabled: [0, "WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode"] + Enabled: [1, "WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode)"] + EWUP2: + Disabled: [0, "WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode"] + Enabled: [1, "WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode)"] + EWUP1: + Disabled: [0, "WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode"] + Enabled: [1, "WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode)"] + CR4: + WRFBUSYP: + RisingEdge: [0, "Detection on high level (rising edge)"] + FallingEdge: [1, "Detection on low level (falling edge)"] + VBRS: + R5k: [0, "VBAT charging through a 5 kΩ resistor"] + R1_5k: [1, "VBAT charging through a 1.5 kΩ resistor"] + VBE: + Disabled: [0, "VBAT battery charging disabled"] + Enabled: [1, "VBAT battery charging enabled"] + WP3: + RisingEdge: [0, "Detection on high level (rising edge)"] + FallingEdge: [1, "Detection on low level (falling edge)"] + WP2: + RisingEdge: [0, "Detection on high level (rising edge)"] + FallingEdge: [1, "Detection on low level (falling edge)"] + WP1: + RisingEdge: [0, "Detection on high level (rising edge)"] + FallingEdge: [1, "Detection on low level (falling edge)"] + SR1: + WUFI: + Clear: [0, "All internal wakeup sources are cleared"] + Wakeup: [1, "wakeup is detected on the internal wakeup line"] + WRFBUSYF: + Clear: [0, "No wakeup event detected on radio busy"] + Wakeup: [1, "Wakeup event detected on radio busy"] + WPVDF: + Clear: [0, "No wakeup event detected on PVD"] + Wakeup: [1, "Wakeup event detected on PVD"] + WUF3: + Clear: [0, "No wakeup event detected on WKUP3"] + Wakeup: [1, "Wakeup event detected on WKUP3"] + WUF2: + Clear: [0, "No wakeup event detected on WKUP2"] + Wakeup: [1, "Wakeup event detected on WKUP2"] + WUF1: + Clear: [0, "No wakeup event detected on WKUP1"] + Wakeup: [1, "Wakeup event detected on WKUP1"] + SR2: + PVMO3: + Above: [0, "VDDA voltage above PVM3 threshold (around 1.62 V)"] + Below: [1, "VDDA voltage below PVM3 threshold (around 1.62 V)"] + PVDO: + Above: [0, "VDD or voltage level on PVD_IN above the selected PVD threshold"] + Below: [1, "VDD or voltage level on PVD_IN below the selected PVD threshold"] + VOSF: + Ready: [0, "Regulator ready in the selected voltage range"] + Change: [1, "Regulator output voltage changed to the required voltage level"] + REGLPF: + Main: [0, "Main regulator (MR) ready and used"] + LowPower: [1, "Low-power regulator (LPR) used"] + REGLPS: + NotReady: [0, "LPR not ready"] + Ready: [1, "LPR ready"] + FLASHRDY: + NotReady: [0, "Flash memory not ready to be accessed"] + Ready: [1, "Flash memory ready to be accessed"] + REGMRS: + V_DD: [0, "Main regulator supplied directly from VDD"] + LDO_SMPS: [1, "Main regulator supplied through LDO or SMPS"] + RFEOLF: + Above: [0, "Supply voltage above radio end-of-life operating low level"] + Below: [1, "Supply voltage below radio end-of-life operating low level"] + LDORDY: + NotReady: [0, "LDO not ready or off"] + Ready: [1, "LDO ready"] + SMPSRDY: + NotReady: [0, "SMPS step-down converter not ready or off"] + Ready: [1, "SMPS step-down converter ready"] + RFBUSYMS: + NotBusy: [0, "radio busy masked signal low (not busy)"] + Busy: [1, "radio busy masked signal high (busy)"] + RFBUSYS: + NotBusy: [0, "radio busy signal low (not busy)"] + Busy: [1, "radio busy signal high (busy)"] + SCR: + CWRFBUSYF: + _write: + Clear: [1, "Setting this bit clears the WRFBUSYF flag in the PWR_SR1. This bit is always read 0."] + CWPVDF: + _write: + Clear: [1, "Setting this bit clears the WPVDF flag in the PWR_SR1. This bit is always read as 0."] + CWUF3: + _write: + Clear: [1, "Setting this bit clears the WUF3 flag in the PWR_SR1 register. This bit is always read as 0."] + CWUF2: + _write: + Clear: [1, "Setting this bit clears the WUF2 flag in the PWR_SR1 register. This bit is always read as 0."] + CWUF1: + _write: + Clear: [1, "Setting this bit clears the WUF1 flag in the PWR_SR1 register. This bit is always read as 0."] + CR5: + SMPSEN: + Disabled: [0, "SMPS step-down converter SMPS mode disabled (LDO mode enabled)"] + Enabled: [1, "SMPS step-down converter SMPS mode enabled"] + RFEOLEN: + Disabled: [0, "Radio end-of-life detector disabled"] + Enabled: [1, "Radio end-of-life detector enabled"] + PUCRA: + "PU1[012345]": + Disabled: [0, "Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set"] + "PU[0123456789]": + Disabled: [0, "Disable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable pull-up on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PA[y] bit is also set"] + PDCRA: + "PD1[012345]": + Disabled: [0, "Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + "PD[0123456789]": + Disabled: [0, "Disable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PA[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + PUCRB: + "PU1[012345]": + Disabled: [0, "Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set"] + "PU[0123456789]": + Disabled: [0, "Disable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable pull-up on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PB[y] bit is also set"] + PDCRB: + "PD1[012345]": + Disabled: [0, "Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + "PD[0123456789]": + Disabled: [0, "Disable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PB[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + PUCRC: + "PU1[345]": + Disabled: [0, "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set"] + "PU[0123456]": + Disabled: [0, "Disable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable pull-up on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PC[y] bit is also set"] + PDCRC: + "PD1[345]": + Disabled: [0, "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + "PD[0123456]": + Disabled: [0, "Disable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PC[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + PUCRH: + PU3: + Disabled: [0, "Disable pull-up on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable pull-up on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3). The pull-up is not activated if the corresponding PH[y] bit is also set"] + PDCRH: + PD3: + Disabled: [0, "Disable the pull-down on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + Enabled: [1, "Enable the pull-down on PH[y] when both APC bits are set in PWR control register 3 (PWR_CR3)"] + EXTSCR: + C1DS: + RunningOrSleep: [0, "CPU is running or in sleep"] + DeepSleep: [1, "CPU is in Deep-Sleep"] + C1STOPF: + NoStop: [0, "System has not been in Stop 0 or 1 mode"] + Stop: [1, "System has been in Stop 0 or 1 mode"] + C1STOP2F: + NoStop: [0, "System has not been in Stop 2 mode"] + Stop: [1, "System has been in Stop 2 mode"] + C1SBF: + NoStandby: [0, "System has not been in Standby mode"] + Standby: [1, "System has been in Standby mode"] + C1CSSF: + _write: + Clear: [1, "Setting this bit clears the C1STOPF and C1SBF bits"] + SUBGHZSPICR: + NSS: + Low: [0, "Sub-GHz SPI NSS signal at level low"] + High: [1, "Sub-GHz SPI NSS signal is at level high"] diff --git a/peripherals/rcc/rcc_wl.yaml b/peripherals/rcc/rcc_wl.yaml new file mode 100644 index 000000000..c1c5a333d --- /dev/null +++ b/peripherals/rcc/rcc_wl.yaml @@ -0,0 +1,439 @@ + +"RCC": + CR: + PLLRDY: + Unlocked: [0, "PLL unlocked"] + Locked: [1, "PLL Locked"] + PLLON: + "Off": [0, "Main PLL Off"] + "On": [1, "Main PLL On"] + HSEBYPPWR: + PB0: [0, "PB0 selected"] + VDDTCXO: [1, "VDDTCXO selected"] + HSEPRE: + Div1: [0, "SYSCLK not divided (HSE32)"] + Div2: [1, "SYSCLK divided by two (HSE32/2)"] + CSSON: + Disabled: [0, "HSE32 CSS off"] + Enabled: [1, "HSE32 CSS on if the HSE32 oscillator is stable and off if not"] + HSERDY: + NotReady: [0, "HSE32 oscillator not ready"] + Ready: [1, "HSE32 oscillator ready"] + HSEON: + Disabled: [0, "HSE32 oscillator for CPU disabled"] + Enabled: [1, "HSE32 oscillator for CPU enabled"] + HSIKERDY: + NotReady: [0, "HSI16 oscillator not ready"] + Ready: [1, "HSI16 oscillator ready"] + HSIASFS: + Disabled: [0, "HSI16 not enabled by hardware when exiting Stop modes with MSI as wakeup clock"] + Enabled: [1, "HSI16 enabled by hardware when exiting Stop mode with MSI as wakeup clock"] + HSIRDY: + NotReady: [0, "HSI16 oscillator not ready"] + Ready: [1, "HSI16 oscillator ready"] + HSIKERON: + NotForced: [0, "No effect on HSI16 oscillator"] + Forced: [1, "HSI16 oscillator forced on even in Stop modes"] + HSION: + Disabled: [0, "HSI16 oscillator off"] + Enabled: [1, "HSI16 oscillator on"] + MSIRANGE: + Range100K: [0b0000, "range 0 around 100 kHz"] + Range200K: [0b0001, "range 1 around 200 kHz"] + Range400K: [0b0010, "range 2 around 400 kHz"] + Range800K: [0b0011, "range 3 around 800 kHz"] + Range1M: [0b0100, "range 4 around 1 MHz"] + Range2M: [0b0101, "range 5 around 2 MHz"] + Range4M: [0b0110, "range 6 around 4 MHz (reset value)"] + Range8M: [0b0111, "range 7 around 8 MHz"] + Range16M: [0b1000, "range 8 around 16 MHz"] + Range24M: [0b1001, "range 9 around 24 MHz"] + Range32M: [0b1010, "range 10 around 32 MHz"] + Range48M: [0b1011, "range 11 around 48 MHz"] + MSIRGSEL: + CSR: [0, "MSI frequency range defined by MSISRANGE[3:0] in the RCC_CSR register"] + CR: [1, "MSI frequency range defined by MSIRANGE[3:0] in the RCC_CR register"] + MSIPLLEN: + "Off": [0, "MSI PLL Off"] + "On": [1, "MSI PLL On"] + MSIRDY: + NotReady: [0, "MSI oscillator not ready"] + Ready: [1, "MSI oscillator ready"] + MSION: + Disabled: [0, "MSI oscillator off"] + Enabled: [1, "MSI oscillator on"] + + ICSCR: + HSITRIM: [0, 0x3F] + HSICAL: [0, 0xFF] + MSITRIM: [0, 0xFF] + MSICAL: [0, 0xFF] + + CFGR: + MCOPRE: + Div1: [0, "No division"] + Div2: [1, "Division by 2"] + Div4: [2, "Division by 4"] + Div8: [3, "Division by 8"] + Div16: [4, "Division by 16"] + MCOSEL: + NoClock: [0, "No clock"] + SYSCLK: [1, "SYSCLK clock selected"] + MSI: [2, "MSI oscillator clock selected"] + HSI16: [3, "HSI16 oscillator clock selected"] + HSE32: [4, "HSE32 oscillator clock selected"] + PLLR: [5, "Main PLLRCLK clock selected"] + LSI: [6, "LSI oscillator clock selected"] + LSE: [8, "LSE oscillator clock selected"] + PLLP: [13, "Main PLLPCLK clock selected"] + PLLQ: [14, "Main PLLQCLK clock selected"] + PPRE2F: + NotApplied: [0, "PCLK2 prescaler value not yet applied"] + Applied: [1, "PCLK2 prescaler value applied"] + PPRE1F: + NotApplied: [0, "PCLK1 prescaler value not yet applied"] + Applied: [1, "PCLK1 prescaler value applied"] + HPREF: + NotApplied: [0, "HCLK1 prescaler value not yet applied"] + Applied: [1, "HCLK1 prescaler value applied"] + STOPWUCK: + MSI: [0, "MSI oscillator selected as wakeup from stop clock and CSS backup clock"] + HSI16: [1, "HSI16 oscillator selected as wakeup from stop clock and CSS backup clock"] + PPRE2: + Div1: [0, "HCLK not divided"] # Same for [0, 8] + Div2: [4, "HCLK divided by 2"] + Div4: [5, "HCLK divided by 4"] + Div8: [6, "HCLK divided by 8"] + Div16: [7, "HCLK divided by 16"] + PPRE1: + Div1: [0, "HCLK not divided"] # Same for [0, 8] + Div2: [4, "HCLK divided by 2"] + Div4: [5, "HCLK divided by 4"] + Div8: [6, "HCLK divided by 8"] + Div16: [7, "HCLK divided by 16"] + HPRE: + Div1: [0b0000, "SYSCLK not divided"] + Div3: [0b0001, "SYSCLK divided by 3"] + Div5: [0b0010, "SYSCLK divided by 5"] + Div6: [0b0101, "SYSCLK divided by 6"] + Div10: [0b0110, "SYSCLK divided by 10"] + Div32: [0b0111, "SYSCLK divided by 32"] + Div2: [0b1000, "SYSCLK divided by 2"] + Div4: [0b1001, "SYSCLK divided by 4"] + Div8: [0b1010, "SYSCLK divided by 8"] + Div16: [0b1011, "SYSCLK divided by 16"] + Div64: [0b1100, "SYSCLK divided by 64"] + Div128: [0b1101, "SYSCLK divided by 128"] + Div256: [0b1110, "SYSCLK divided by 128"] + Div512: [0b1111, "SYSCLK divided by 512"] + SWS: + MSI: [0, "MSI oscillator used as system clock"] + HSI16: [1, "HSI16 oscillator used as system clock"] + HSE32: [2, "HSE32 oscillator used as system clock"] + PLLR: [3, "PLLRCLK used as system clock"] + SW: + MSI: [0, "MSI oscillator used as system clock"] + HSI16: [1, "HSI16 oscillator used as system clock"] + HSE32: [2, "HSE32 oscillator used as system clock"] + PLLR: [3, "PLLRCLK used as system clock"] + + PLLCFGR: + "PLL[RQ]": + Div2: [1, "PLL = VCO/(N+1)"] + Div3: [2, "PLL = VCO/(N+1)"] + Div4: [3, "PLL = VCO/(N+1)"] + Div5: [4, "PLL = VCO/(N+1)"] + Div6: [5, "PLL = VCO/(N+1)"] + Div7: [6, "PLL = VCO/(N+1)"] + Div8: [7, "PLL = VCO/(N+1)"] + "PLL[PRQ]EN": + Disabled: [0, "PLLCLK output disabled"] + Enabled: [1, "PLLCLK output enabled"] + PLLP: + Div2: [1, "PLL = VCO/(N+1)"] + Div3: [2, "PLL = VCO/(N+1)"] + Div4: [3, "PLL = VCO/(N+1)"] + Div5: [4, "PLL = VCO/(N+1)"] + Div6: [5, "PLL = VCO/(N+1)"] + Div7: [6, "PLL = VCO/(N+1)"] + Div8: [7, "PLL = VCO/(N+1)"] + Div9: [8, "PLL = VCO/(N+1)"] + Div10: [9, "PLL = VCO/(N+1)"] + Div11: [10, "PLL = VCO/(N+1)"] + Div12: [11, "PLL = VCO/(N+1)"] + Div13: [12, "PLL = VCO/(N+1)"] + Div14: [13, "PLL = VCO/(N+1)"] + Div15: [14, "PLL = VCO/(N+1)"] + Div16: [15, "PLL = VCO/(N+1)"] + Div17: [16, "PLL = VCO/(N+1)"] + Div18: [17, "PLL = VCO/(N+1)"] + Div19: [18, "PLL = VCO/(N+1)"] + Div20: [19, "PLL = VCO/(N+1)"] + Div21: [20, "PLL = VCO/(N+1)"] + Div22: [21, "PLL = VCO/(N+1)"] + Div23: [22, "PLL = VCO/(N+1)"] + Div24: [23, "PLL = VCO/(N+1)"] + Div25: [24, "PLL = VCO/(N+1)"] + Div26: [25, "PLL = VCO/(N+1)"] + Div27: [26, "PLL = VCO/(N+1)"] + Div28: [27, "PLL = VCO/(N+1)"] + Div29: [28, "PLL = VCO/(N+1)"] + Div30: [29, "PLL = VCO/(N+1)"] + Div31: [30, "PLL = VCO/(N+1)"] + Div32: [31, "PLL = VCO/(N+1)"] + PLLN: [6, 127] + PLLM: + Div1: [0, "VCO input = PLL input / PLLM"] + Div2: [1, "VCO input = PLL input / PLLM"] + Div3: [2, "VCO input = PLL input / PLLM"] + Div4: [3, "VCO input = PLL input / PLLM"] + Div5: [4, "VCO input = PLL input / PLLM"] + Div6: [5, "VCO input = PLL input / PLLM"] + Div7: [6, "VCO input = PLL input / PLLM"] + Div8: [7, "VCO input = PLL input / PLLM"] + PLLSRC: + NoClock: [0, "No clock sent to PLL"] + MSI: [1, "MSI clock selected as PLL clock entry"] + HSI16: [2, "HSI16 clock selected as PLL clock entry"] + HSE32: [3, "HSE32 clock selected as PLL clock entry"] + + CIER: + LSECSSIE: + Disabled: [0, "Interrupt disabled"] + Enabled: [1, "Interrupt enabled"] + PLLRDYIE: + Disabled: [0, "Interrupt disabled"] + Enabled: [1, "Interrupt enabled"] + HSERDYIE: + Disabled: [0, "Interrupt disabled"] + Enabled: [1, "Interrupt enabled"] + HSIRDYIE: + Disabled: [0, "Interrupt disabled"] + Enabled: [1, "Interrupt enabled"] + MSIRDYIE: + Disabled: [0, "Interrupt disabled"] + Enabled: [1, "Interrupt enabled"] + LSERDYIE: + Disabled: [0, "Interrupt disabled"] + Enabled: [1, "Interrupt enabled"] + LSIRDYIE: + Disabled: [0, "Interrupt disabled"] + Enabled: [1, "Interrupt enabled"] + + CIFR: + LSECSSF: + NotInterrupted: [0, "Not interrupted"] + Interrupted: [1, "Interrupted"] + CSSF: + NotInterrupted: [0, "Not interrupted"] + Interrupted: [1, "Interrupted"] + PLLRDYF: + NotInterrupted: [0, "Not interrupted"] + Interrupted: [1, "Interrupted"] + HSERDYF: + NotInterrupted: [0, "Not interrupted"] + Interrupted: [1, "Interrupted"] + HSIRDYF: + NotInterrupted: [0, "Not interrupted"] + Interrupted: [1, "Interrupted"] + MSIRDYF: + NotInterrupted: [0, "Not interrupted"] + Interrupted: [1, "Interrupted"] + LSERDYF: + NotInterrupted: [0, "Not interrupted"] + Interrupted: [1, "Interrupted"] + LSIRDYF: + NotInterrupted: [0, "Not interrupted"] + Interrupted: [1, "Interrupted"] + + CICR: + LSECSSC: + Clear: [1, "Clear interrupt flag"] + CSSC: + Clear: [1, "Clear interrupt flag"] + PLLRDYC: + Clear: [1, "Clear interrupt flag"] + HSERDYC: + Clear: [1, "Clear interrupt flag"] + HSIRDYC: + Clear: [1, "Clear interrupt flag"] + MSIRDYC: + Clear: [1, "Clear interrupt flag"] + LSERDYC: + Clear: [1, "Clear interrupt flag"] + LSIRDYC: + Clear: [1, "Clear interrupt flag"] + + "AHB[123]RSTR": + "*": + NoReset: [0, "No effect"] + Reset: [1, "Reset peripheral"] + + "APB[123]RSTR?": + "*": + NoReset: [0, "No effect"] + Reset: [1, "Reset peripheral"] + + "A[PH]B[123]ENR": + "*": + Disabled: [0, "Clock disabled"] + Enabled: [1, "Clock enabled"] + + "APB[123]ENR?": + "*": + Disabled: [0, "Clock disabled"] + Enabled: [1, "Clock enabled"] + + "A[PH]B[123]SMENR?": + "*": + Disabled: [0, "Clock disabled"] + Enabled: [1, "Clock enabled"] + + CCIPR: + RNGSEL: + PLLQ: [0, "PLLQ clock selected"] + LSI: [1, "LSI clock selected"] + LSE: [2, "LSE clock selected"] + MSI: [3, "MSI clock selected"] + ADCSEL: + NoClock: [0, "No clock selected"] + HSI16: [1, "HSI16 clock selected"] + PLLP: [2, "PLLP clock selected"] + SYSCLK: [3, "SYSCLK clock selected"] + "LPTIM[123]SEL": + PCLK: [0, "PCLK clock selected"] + LSI: [1, "LSI clock selected"] + HSI16: [2, "HSI16 clock selected"] + LSE: [3, "LSE clock selected"] + "I2C[123]SEL": + PCLK: [0, "PCLK clock selected"] + SYSCLK: [1, "SYSCLK clock selected"] + HSI16: [2, "HSI16 clock selected"] + LPUART1SEL: + PCLK: [0, "PCLK clock selected"] + SYSCLK: [1, "SYSCLK clock selected"] + HSI16: [2, "HSI16 clock selected"] + LSE: [3, "LSE clock selected"] + SPI2S2SEL: + PLLQ: [1, "PLLQ clock selected"] + HSI16: [2, "HSI16 clock selected"] + I2S: [3, "External input I2S_CKIN selected"] + "USART[12]SEL": + PCLK: [0, "PCLK clock selected"] + SYSCLK: [1, "SYSCLK clock selected"] + HSI16: [2, "HSI16 clock selected"] + LSE: [3, "LSE clock selected"] + + BDCR: + LSCOSEL: + LSI: [0, "LSI clock selected"] + LSE: [1, "LSE clock selected"] + LSCOEN: + Disabled: [0, "LSCO disabled"] + Enabled: [1, "LSCO enabled"] + BDRST: + NotActive: [0, "Reset not activated"] + Reset: [1, "Entire Backup domain reset"] + RTCEN: + Disabled: [0, "RTC kernel clock disabled"] + Enabled: [1, "RTC kernel clock enabled"] + LSESYSRDY: + NotReady: [0, "LSE system clock not ready"] + Ready: [1, "LSE system clock ready"] + RTCSEL: + NoClock: [0, "No clock"] + LSE: [1, "LSE oscillator clock selected"] + LSI: [2, "LSI oscillator clock selected"] + HSE32: [3, "HSE32 oscillator clock divided by 32 selected"] + LSESYSEN: + Disabled: [0, "LSE system clock disabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode"] + Enabled: [1, "LSE system clock enabled to USARTx, LPUARTx, LPTIMx, TIMx, RNG, system LSCO, MCO, MSI PLL mode"] + LSECSSD: + NoFailure: [0, "No failure detected on LSE"] + Failure: [1, "Failure detected on LSE"] + LSECSSON: + Disabled: [0, "CSS on LSE disabled"] + Enabled: [1, "CSS on LSE enabled"] + LSEDRV: + Low: [0, "Xtal mode lower driving capability"] + MedLow: [1, "Xtal mode medium-low driving capability"] + MedHigh: [2, "Xtal mode medium-high driving capability"] + High: [3, "Xtal mode higher driving capability"] + LSEBYP: + Disabled: [0, "LSE oscillator not bypassed"] + Enabled: [1, "LSE oscillator bypassed"] + LSERDY: + NotReady: [0, "LSE oscillator not ready"] + Ready: [1, "LSE oscillator ready"] + LSEON: + "Off": [0, "LSE oscillator off"] + "On": [1, "LSE oscillator on"] + + CSR: + LPWRRSTF: + NoReset: [0, "No reset occurred"] + Reset: [1, "Reset occurred"] + WWDGRSTF: + NoReset: [0, "No reset occurred"] + Reset: [1, "Reset occurred"] + IWDGRSTF: + NoReset: [0, "No reset occurred"] + Reset: [1, "Reset occurred"] + SFTRSTF: + NoReset: [0, "No reset occurred"] + Reset: [1, "Reset occurred"] + BORRSTF: + NoReset: [0, "No reset occurred"] + Reset: [1, "Reset occurred"] + PINRSTF: + NoReset: [0, "No reset occurred"] + Reset: [1, "Reset occurred"] + OBLRSTF: + NoReset: [0, "No reset occurred"] + Reset: [1, "Reset occurred"] + RFILARSTF: + NoIllegalCommand: [0, "No SUBGHZ radio illegal command occurred"] + IllegalCommand: [1, "SUBGHZ radio illegal command occurred"] + RMVF: + NoEffect: [0, "No effect"] + Clear: [1, "Reset flags reset"] + RFRST: + Removed: [0, "Sub-GHz radio software reset removed"] + Reset: [1, "Sub-GHz radio software reset active"] + RFRSTF: + NoReset: [0, "Sub-GHz radio out of reset"] + Reset: [1, "Sub-GHz radio in reset"] + MSISRANGE: + f_1MHz: [0b0100, "Range 4 around 1 MHz"] + f_2MHz: [0b0101, "Range 5 around 2 MHz"] + f_4MHz: [0b0110, "Range 6 around 4 MHz (reset value)"] + f_8MHz: [0b0111, "Range 7 around 8 MHz"] + LSIPRE: + Div1: [0, "LSI clock not divided"] + Div128: [1, "LSI clock divided by 128"] + LSIRDY: + NotReady: [0, "LSI oscillator not ready"] + Ready: [1, "LSI oscillator ready"] + LSION: + "Off": [0, "LSI oscillator off"] + "On": [1, "LSI oscillator on"] + + EXTCFGR: + SHDHPREF: + NotApplied: [0, "HCLK3 prescaler value not yet applied"] + Applied: [1, "HCLK3 prescaler value applied"] + SHDHPRE: + Div1: [0b0000, "SYSCLK not divided"] + Div3: [0b0001, "SYSCLK divided by 3"] + Div5: [0b0010, "SYSCLK divided by 5"] + Div6: [0b0101, "SYSCLK divided by 6"] + Div10: [0b0110, "SYSCLK divided by 10"] + Div32: [0b0111, "SYSCLK divided by 32"] + Div2: [0b1000, "SYSCLK divided by 2"] + Div4: [0b1001, "SYSCLK divided by 4"] + Div8: [0b1010, "SYSCLK divided by 8"] + Div16: [0b1011, "SYSCLK divided by 16"] + Div64: [0b1100, "SYSCLK divided by 64"] + Div128: [0b1101, "SYSCLK divided by 128"] + Div256: [0b1110, "SYSCLK divided by 128"] + Div512: [0b1111, "SYSCLK divided by 512"] diff --git a/peripherals/rng/rng_wl.yaml b/peripherals/rng/rng_wl.yaml new file mode 100644 index 000000000..2381f938b --- /dev/null +++ b/peripherals/rng/rng_wl.yaml @@ -0,0 +1,56 @@ +_include: + - ./rng_v1.yaml + - ./rng_v1_ced.yaml + +RNG: + CR: + CONFIGLOCK: + Enabled: [0, "Writes to the RNG_CR configuration bits [29:4] are allowed"] + Disabled: [1, "Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset"] + CONDRST: + RNG_CONFIG1: + ConfigA: [0x0F, "Recommended value for config A (NIST certifiable)"] + ConfigB: [0x18, "Recommended value for config B (not NIST certifiable)"] + RNG_CONFIG2: + ConfigA_B: [0x00, "Recommended value for config A and B"] + RNG_CONFIG3: + ConfigA: [0x0D, "Recommended value for config A (NIST certifiable)"] + ConfigB: [0x00, "Recommended value for config B (not NIST certifiable)"] + CLKDIV: + NoDiv: [0, "Internal RNG clock after divider is similar to incoming RNG clock"] + Div_2_1: [1, "Divide RNG clock by 2^1"] + Div_2_2: [2, "Divide RNG clock by 2^2"] + Div_2_3: [3, "Divide RNG clock by 2^3"] + Div_2_4: [4, "Divide RNG clock by 2^4"] + Div_2_5: [5, "Divide RNG clock by 2^5"] + Div_2_6: [6, "Divide RNG clock by 2^6"] + Div_2_7: [7, "Divide RNG clock by 2^7"] + Div_2_8: [8, "Divide RNG clock by 2^8"] + Div_2_9: [9, "Divide RNG clock by 2^9"] + Div_2_10: [10, "Divide RNG clock by 2^10"] + Div_2_11: [11, "Divide RNG clock by 2^11"] + Div_2_12: [12, "Divide RNG clock by 2^12"] + Div_2_13: [13, "Divide RNG clock by 2^13"] + Div_2_14: [14, "Divide RNG clock by 2^14"] + Div_2_15: [15, "Divide RNG clock by 2^15"] + NISTC: + Default: [0, "Hardware default values for NIST compliant RNG. In this configuration per 128-bit output two conditioning loops are performed and 256 bits of noise source are used"] + Custom: [1, "Custom values for NIST compliant RNG"] + + SR: + SEIS: + NoFault: [0, "No faulty sequence detected"] + Fault: [1, "At least one faulty sequence has been detected"] + CEIS,CECS: + Correct: [0, "The RNG clock is correct (fRNGCLK> fHCLK/32)"] + Slow: [1, "The RNG clock before internal divider has been detected too slow (fRNGCLK< fHCLK/32)"] + SECS: + NoFault: [0, "No faulty sequence has currently been detected. If the SEIS bit is set, this means that a faulty sequence was detected and the situation has been recovered"] + Fault: [1, "At least one faulty sequence has been detected - see ref manual for details"] + DRDY: + Invalid: [0, "The RNG_DR register is not yet valid, no random data is available"] + Valid: [1, "The RNG_DR register contains valid random data"] + HTCR: + HTCFG: + Magic: [0x1759_0ABC, "Magic number to be written before any write (0x1759_0ABC)"] + Recommended: [0x0000_AA74, "Recommended value for RNG certification (0x0000_AA74)"] diff --git a/peripherals/rtc/rtc_wl.yaml b/peripherals/rtc/rtc_wl.yaml new file mode 100644 index 000000000..31b29f5d5 --- /dev/null +++ b/peripherals/rtc/rtc_wl.yaml @@ -0,0 +1,275 @@ +RTC: + TR: + PM: + AM: [0, "AM or 24-hour format"] + PM: [1, "PM"] + HT: [0, 3] + HU: [0, 15] + MNT: [0, 7] + MNU: [0, 15] + ST: [0, 7] + SU: [0, 15] + DR: + YT: [0, 15] + YU: [0, 15] + WDU: [1, 7] + MT: [0, 1] + MU: [0, 15] + DT: [0, 3] + DU: [0, 15] + + SSR: + SS: [0, 65535] + + ICSR: + RECALPF: + _read: + Pending: [1, "The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0"] + BCDU: + Bit7: [0, "1s increment each time SS[7:0]=0"] + Bit8: [1, "1s increment each time SS[8:0]=0"] + Bit9: [2, "1s increment each time SS[9:0]=0"] + Bit10: [3, "1s increment each time SS[10:0]=0"] + Bit11: [4, "1s increment each time SS[11:0]=0"] + Bit12: [5, "1s increment each time SS[12:0]=0"] + Bit13: [6, "1s increment each time SS[13:0]=0"] + Bit14: [7, "1s increment each time SS[14:0]=0"] + BIN: + BCD: [0, "Free running BCD calendar mode (Binary mode disabled)"] + Binary: [1, "Free running Binary mode (BCD mode disabled)"] + BinBCD: [2, "Free running BCD calendar and Binary modes"] + BinBCD2: [3, "Free running BCD calendar and Binary modes"] + INIT: + FreeRunningMode: [0, "Free running mode"] + InitMode: [1, "Initialization mode used to program time and date register (RTC_TR and RTC_DR), and prescaler register (RTC_PRER). Counters are stopped and start counting from the new value when INIT is reset."] + INITF: + _read: + NotAllowed: [0, "Calendar registers update is not allowed"] + Allowed: [1, "Calendar registers update is allowed"] + RSF: + _read: + NotSynced: [0, "Calendar shadow registers not yet synchronized"] + Synced: [1, "Calendar shadow registers synchronized"] + _write: + Clear: [0, "This flag is cleared by software by writing 0"] + INITS: + _read: + NotInitalized: [0, "Calendar has not been initialized"] + Initalized: [1, "Calendar has been initialized"] + SHPF: + _read: + NoShiftPending: [0, "No shift operation is pending"] + ShiftPending: [1, "A shift operation is pending"] + WUTWF: + _read: + UpdateNotAllowed: [0, "Wakeup timer configuration update not allowed"] + UpdateAllowed: [1, "Wakeup timer configuration update allowed"] + + PRER: + PREDIV_A: [0, 0x7F] + PREDIV_S: [0, 0x7FFF] + + WUTR: + WUT: [0, 0xFFFF] + WUTOCLR: [0, 0xFFFF] + + CR: + OUT2EN: + Disabled: [0, "RTC output 2 disable"] + Enabled: [1, "RTC output 2 enable"] + TAMPALRM_TYPE: + PushPull: [0, "TAMPALRM is push-pull output"] + OpenDrain: [1, "TAMPALRM is open-drain output"] + TAMPALRM_PU: + NoPullUp: [0, "No pull-up is applied on TAMPALRM output"] + PullUp: [1, "A pull-up is applied on TAMPALRM output"] + TAMPOE: + Disabled: [0, "The tamper flag is not routed on TAMPALRM"] + Enabled: [1, "The tamper flag is routed on TAMPALRM, combined with the signal provided by OSEL and with the polarity provided by POL"] + TAMPTS: + Disabled: [0, "Tamper detection event does not cause a RTC timestamp to be saved"] + Enabled: [1, "Save RTC timestamp on tamper detection event"] + ITSE: + Disabled: [0, "Internal event timestamp disabled"] + Enabled: [1, "Internal event timestamp enabled"] + COE: + Disabled: [0, "Calibration output disabled"] + Enabled: [1, "Calibration output enabled"] + OSEL: + Disabled: [0, "Output disabled"] + AlarmA: [1, "Alarm A output enabled"] + AlarmB: [2, "Alarm B output enabled"] + Wakeup: [3, "Wakeup output enabled"] + POL: + High: [0, "The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"] + Low: [1, "The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])"] + COSEL: + CalFreq_512Hz: [0, "Calibration output is 512 Hz (with default prescaler setting)"] + CalFreq_1Hz: [1, "Calibration output is 1 Hz (with default prescaler setting)"] + BKP: + DSTNotChanged: [0, "Daylight Saving Time change has not been performed"] + DSTChanged: [1, "Daylight Saving Time change has been performed"] + SUB1H: + _write: + Sub1: [1, "Subtracts 1 hour to the current time. This can be used for winter time change outside initialization mode"] + ADD1H: + _write: + Add1: [1, "Adds 1 hour to the current time. This can be used for summer time change outside initialization mode"] + TSIE: + Disabled: [0, "Time-stamp Interrupt disabled"] + Enabled: [1, "Time-stamp Interrupt enabled"] + WUTIE: + Disabled: [0, "Wakeup timer interrupt disabled"] + Enabled: [1, "Wakeup timer interrupt enabled"] + ALRBIE: + Disabled: [0, "Alarm B Interrupt disabled"] + Enabled: [1, "Alarm B Interrupt enabled"] + ALRAIE: + Disabled: [0, "Alarm A interrupt disabled"] + Enabled: [1, "Alarm A interrupt enabled"] + TSE: + Disabled: [0, "Timestamp disabled"] + Enabled: [1, "Timestamp enabled"] + WUTE: + Disabled: [0, "Wakeup timer disabled"] + Enabled: [1, "Wakeup timer enabled"] + ALRBE: + Disabled: [0, "Alarm B disabled"] + Enabled: [1, "Alarm B enabled"] + ALRAE: + Disabled: [0, "Alarm A disabled"] + Enabled: [1, "Alarm A enabled"] + SSRUIE: + Disabled: [0, "SSR underflow interrupt disabled"] + Enabled: [1, "SSR underflow interrupt enabled"] + FMT: + TwentyFourHour: [0, "24 hour/day format"] + AmPm: [1, "AM/PM hour format"] + BYPSHAD: + ShadowReg: [0, "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from the shadow registers, which are updated once every two RTCCLK cycles"] + BypassShadowReg: [1, "Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken directly from the calendar counters"] + REFCKON: + Disabled: [0, "RTC_REFIN detection disabled"] + Enabled: [1, "RTC_REFIN detection enabled"] + TSEDGE: + RisingEdge: [0, "RTC_TS input rising edge generates a time-stamp event"] + FallingEdge: [1, "RTC_TS input falling edge generates a time-stamp event"] + WUCKSEL: + Div16: [0, "RTC/16 clock is selected"] + Div8: [1, "RTC/8 clock is selected"] + Div4: [2, "RTC/4 clock is selected"] + Div2: [3, "RTC/2 clock is selected"] + ClockSpare: [4, "ck_spre (usually 1 Hz) clock is selected"] + ClockSpareWithOffset: [6, "ck_spre (usually 1 Hz) clock is selected and 2^16 is added to the WUT counter value"] + + WPR: + KEY: + Deactivate1: [0xCA, "Key 1"] + Deactivate2: [0x53, "Key 2"] + Activate: [0x0, "Activate write protection (any value that is not the keys)"] + + CALR: + CALP: + NoChange: [0, "No RTCCLK pulses are added"] + IncreaseFreq: [1, "One RTCCLK pulse is effectively inserted every 2^11 pulses (frequency increased by 488.5 ppm)"] + CALW8: + EightSeconds: [1, "When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected"] + CALW16: + SixteenSeconds: [1, "When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must not be set to ‘1’ if CALW8=1"] + LPCAL: + RTCCLK: [0, "Calibration window is 220 RTCCLK, which is a high-consumption mode. This mode should be set only when less than 32s calibration window is required"] + CkApre: [1, "Calibration window is 220 ck_apre, which is the required configuration for ultra-low consumption mode"] + CALM: [0, 511] + + SHIFTR: + ADD1S: + _write: + Add1: [1, "Add one second to the clock/calendar"] + SUBFS: [0, 32767] + + TSTR: + _read: + PM: + AM: [0, "AM or 24-hour format"] + PM: [1, "PM"] + HT: [0, 3] + HU: [0, 15] + MNT: [0, 7] + MNU: [0, 15] + ST: [0, 7] + SU: [0, 15] + TSDR: + _read: + WDU: [0, 3] + MT: [0, 1] + MU: [0, 7] + DT: [0, 3] + DU: [0, 15] + TSSSR: + _read: + SS: [0, 65535] + + "ALRM?R": + "MSK*": + Mask: [0, "Alarm set if the date/day match"] + NotMask: [1, "Date/day don’t care in Alarm comparison"] + WDSEL: + DateUnits: [0, "DU[3:0] represents the date units"] + WeekDay: [1, "DU[3:0] represents the week day. DT[1:0] is don’t care."] + DT: [0, 3] + DU: [0, 15] + PM: + AM: [0, "AM or 24-hour format"] + PM: [1, "PM"] + HT: [0, 3] + HU: [0, 15] + MNT: [0, 7] + MNU: [0, 15] + ST: [0, 7] + SU: [0, 15] + + "ALRM?SSR": + SSCLR: + FreeRunning: [0, "The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running"] + ALRMBINR: [1, "The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to RTC_ALRMABINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when reaching RTC_ALRMABINR → SS[31:0]"] + MASKSS: [0, 0x3F] + SS: [0, 0x7FFF] + + SR: + SSRUF: + Underflow: [1, "This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1"] + ITSF: + TimestampEvent: [1, "This flag is set by hardware when a timestamp on the internal event occurs"] + TSOVF: + Overflow: [1, "This flag is set by hardware when a time-stamp event occurs while TSF is already set"] + TSF: + TimestampEvent: [1, "This flag is set by hardware when a time-stamp event occurs"] + WUTF: + Zero: [1, "This flag is set by hardware when the wakeup auto-reload counter reaches 0"] + ALRBF: + Match: [1, "This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)"] + ALRAF: + Match: [1, "This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)"] + + MISR: + SSRUMF: + Underflow: [1, "This flag is set by hardware when the SSR rolls under 0. SSRUF is not set when SSCLR=1"] + ITSMF: + TimestampEvent: [1, "This flag is set by hardware when a timestamp on the internal event occurs"] + TSOVMF: + Overflow: [1, "This flag is set by hardware when a time-stamp event occurs while TSF is already set"] + TSMF: + TimestampEvent: [1, "This flag is set by hardware when a time-stamp event occurs"] + WUTMF: + Zero: [1, "This flag is set by hardware when the wakeup auto-reload counter reaches 0"] + ALRBMF: + Match: [1, "This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR)"] + ALRAMF: + Match: [1, "This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR)"] + + SCR: + "*": + Clear: [1, "Clear interrupt flag by writing 1"] + + "ALR?BINR": + SS: [0, 0xFFFFFFFF] diff --git a/peripherals/spi/spi_I2S_ASTRTEN.yaml b/peripherals/spi/spi_I2S_ASTRTEN.yaml new file mode 100644 index 000000000..941ce9dab --- /dev/null +++ b/peripherals/spi/spi_I2S_ASTRTEN.yaml @@ -0,0 +1,5 @@ +"I2S*": + I2SCFGR: + ASTRTEN: + AsyncStartDisabled: [0, "Asynchronous start disabled"] + AsyncStartEnabled: [1, "Asynchronous start enabled"] diff --git a/peripherals/syscfg/syscfg_wl.yaml b/peripherals/syscfg/syscfg_wl.yaml new file mode 100644 index 000000000..c1f7ef269 --- /dev/null +++ b/peripherals/syscfg/syscfg_wl.yaml @@ -0,0 +1,161 @@ +SYSCFG: + MEMRMP: + MEM_MODE: + MainFlash: [0, "Main Flash memory mapped at 0x0000_0000"] + SystemFlash: [1, "System Flash memory mapped at 0x0000_0000"] + SRAM: [3, "Embedded SRAM mapped at 0x0000_0000"] + + CFGR1: + I2C3_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C3 pins selected through selection bits in GPIOx_AFR registers"] + I2C2_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C2 pins selected through selection bits in GPIOx_AFR registers"] + I2C1_FMP: + Standard: [0, "FM+ mode is controlled by I2C_Pxx_FMP bits only"] + FMP: [1, "FM+ mode is enabled on all I2C1 pins selected through selection bits in GPIOx_AFR registers"] + I2C_PB9_FMP: + Standard: [0, "PB9 pin operate in standard mode"] + FMP: [1, "I2C FM+ mode enabled on PB9 and the Speed control is bypassed"] + I2C_PB8_FMP: + Standard: [0, "PB8 pin operate in standard mode"] + FMP: [1, "I2C FM+ mode enabled on PB8 and the Speed control is bypassed"] + I2C_PB7_FMP: + Standard: [0, "PB7 pin operate in standard mode"] + FMP: [1, "I2C FM+ mode enabled on PB7 and the Speed control is bypassed"] + I2C_PB6_FMP: + Standard: [0, "PB6 pin operate in standard mode"] + FMP: [1, "I2C FM+ mode enabled on PB6 and the Speed control is bypassed"] + BOOSTEN: + Disabled: [0, "I/O analog switches are supplied by VDDA voltage. This is the recommended configuration when using the ADC in high VDDA voltage operation"] + Enabled: [1, "I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD). This is the recommended configuration when using the ADC in low VDDA voltage operation"] + + EXTICR1: + EXTI3: + PA3: [0, "Select PA3 as the source input for the EXTI3 external interrupt"] + PB3: [1, "Select PB3 as the source input for the EXTI3 external interrupt"] + PC3: [2, "Select PC3 as the source input for the EXTI3 external interrupt"] + PH3: [7, "Select PH3 as the source input for the EXTI3 external interrupt"] + EXTI2: + PA2: [0, "Select PA2 as the source input for the EXTI2 external interrupt"] + PB2: [1, "Select PB2 as the source input for the EXTI2 external interrupt"] + PC2: [2, "Select PC2 as the source input for the EXTI2 external interrupt"] + EXTI1: + PA1: [0, "Select PA1 as the source input for the EXTI1 external interrupt"] + PB1: [1, "Select PB1 as the source input for the EXTI1 external interrupt"] + PC1: [2, "Select PC1 as the source input for the EXTI1 external interrupt"] + EXTI0: + PA0: [0, "Select PA0 as the source input for the EXTI0 external interrupt"] + PB0: [1, "Select PB0 as the source input for the EXTI0 external interrupt"] + PC0: [2, "Select PC0 as the source input for the EXTI0 external interrupt"] + + EXTICR2: + EXTI7: + PA7: [0, "Select PA7 as the source input for the EXTI7 external interrupt"] + PB7: [1, "Select PB7 as the source input for the EXTI7 external interrupt"] + EXTI6: + PA6: [0, "Select PA6 as the source input for the EXTI6 external interrupt"] + PB6: [1, "Select PB6 as the source input for the EXTI6 external interrupt"] + PC6: [2, "Select PC6 as the source input for the EXTI6 external interrupt"] + EXTI5: + PA5: [0, "Select PA5 as the source input for the EXTI5 external interrupt"] + PB5: [1, "Select PB5 as the source input for the EXTI5 external interrupt"] + PC5: [2, "Select PC5 as the source input for the EXTI5 external interrupt"] + EXTI4: + PA4: [0, "Select PA4 as the source input for the EXTI4 external interrupt"] + PB4: [1, "Select PB4 as the source input for the EXTI4 external interrupt"] + PC4: [2, "Select PC4 as the source input for the EXTI4 external interrupt"] + + EXTICR3: + EXTI11: + PA11: [0, "Select PA11 as the source input for the EXTI11 external interrupt"] + PB11: [1, "Select PB11 as the source input for the EXTI11 external interrupt"] + EXTI10: + PA10: [0, "Select PA10 as the source input for the EXTI10 external interrupt"] + PB10: [1, "Select PB10 as the source input for the EXTI10 external interrupt"] + EXTI9: + PA9: [0, "Select PA9 as the source input for the EXTI9 external interrupt"] + PB9: [1, "Select PB9 as the source input for the EXTI9 external interrupt"] + EXTI8: + PA8: [0, "Select PA8 as the source input for the EXTI8 external interrupt"] + PB8: [1, "Select PB8 as the source input for the EXTI8 external interrupt"] + + EXTICR4: + EXTI15: + PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] + PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] + PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] + EXTI14: + PA15: [0, "Select PA15 as the source input for the EXTI15 external interrupt"] + PB15: [1, "Select PB15 as the source input for the EXTI15 external interrupt"] + PC15: [2, "Select PC15 as the source input for the EXTI15 external interrupt"] + EXTI13: + PA13: [0, "Select PA13 as the source input for the EXTI13 external interrupt"] + PB13: [1, "Select PB13 as the source input for the EXTI13 external interrupt"] + PC13: [2, "Select PC13 as the source input for the EXTI13 external interrupt"] + EXTI12: + PA12: [0, "Select PA12 as the source input for the EXTI12 external interrupt"] + PB12: [1, "Select PB12 as the source input for the EXTI12 external interrupt"] + + SCSR: + PKASRAMBSY: + Idle: [0, "No PKA SRAM erase operation is ongoing"] + Busy: [1, "PKA SRAM erase operation is ongoing"] + SRAMBSY: + Idle: [0, "No SRAM1 or SRAM2 erase operation is ongoing"] + Busy: [1, "SRAM1 or SRAM2 erase operation is ongoing"] + SRAM2ER: + _write: + Erase: [1, "Start SRAM2 erase operation"] + + CFGR2: + SPF: + _read: + Nominal: [0, "No SRAM2 parity error detected"] + Error: [1, "SRAM2 parity error detected"] + _write: + Clear: [1, "Clear SRAM2 parity error flag"] + ECCL: + _read: + Disconnected: [0, "ECC error disconnected from TIM1/16/17 break input"] + Connected: [1, "ECC error connected to TIM1/16/17 break input"] + _write: + Connect: [1, "Connect ECC error to TIM1/16/17 break input"] + PVDL: + _read: + Disconnected: [0, "PVD interrupt disconnected from TIM1/16/17 break input. PVDE and PLS[2:0] bits can be programmed by the application"] + Connected: [1, "PVD interrupt connected to TIM1/16/17 break input. PVDE and PLS[2:0] bits are read only"] + _write: + Connect: [1, "Connect PVD interretup to TIM1/16/17 break input"] + SPL: + _read: + Disconnected: [0, "SRAM2 parity error signal disconnected from TIM1/16/17 break input"] + Connected: [1, "SRAM2 parity error signal connected to TIM1/16/17 break input"] + _write: + Connect: [1, "Connect SRAM2 parity error signal to TIM1/16/17 break input"] + CLL: + _read: + Disconnected: [0, "CPU LOCKUP output disconnected from TIM1/16/17 break input"] + Connected: [1, "CPU LOCKUP output connected to TIM1/16/17 break input"] + _write: + Connect: [1, "Connect CPU LOCKUP output to TIM1/16/17 break input"] + + SWPR: + P??WP: + Disabled: [0, "SRAM2 1 KB page protection disabled"] + Enabled: [1, "SRAM2 1 KB page protection enabled"] + P?WP: + Disabled: [0, "SRAM2 1 KB page protection disabled"] + Enabled: [1, "SRAM2 1 KB page protection enabled"] + + SKR: + KEY: + Step1: [0xCA, "Step 1 to remove SRAM2ER bits write protection"] + Step2: [0x53, "Step 2 to remove SRAM2ER bits write protection"] + WriteProtect: [0x11, "Activate SRAM2ER bits write protection"] + + RFDCR: + RFTBSEL: + Digital: [0, "Digital test bus selected on RF_ADTB[3:0]"] + Analog: [1, "Analog test bus selected on RF_ADTB[3:0]"] diff --git a/peripherals/tamp/tamp_wl.yaml b/peripherals/tamp/tamp_wl.yaml new file mode 100644 index 000000000..ba775d79b --- /dev/null +++ b/peripherals/tamp/tamp_wl.yaml @@ -0,0 +1,92 @@ + +TAMP: + CR1: + ITAMP?E: + Disabled: [0, "Internal tamper x disabled"] + Enabled: [1, "Internal tamper x enabled"] + TAMP?E: + Disabled: [0, "Tamper detection on TAMP_INx is disabled"] + Enabled: [1, "Tamper detection on TAMP_IN3 is enabled"] + + CR2: + TAMP?TRG: + FilteredLowOrUnfilteredHigh: [0, "If TAMPFLT != 00 Tamper x input staying low triggers a tamper detection event. If TAMPFLT = 00 Tamper x input rising edge and high level triggers a tamper detection event"] + FilteredHighOrUnfilteredLow: [1, "If TAMPFLT != 00 Tamper x input staying high triggers a tamper detection event. If TAMPFLT = 00 Tamper x input falling edge and low level triggers a tamper detection event"] + BKERASE: + _write: + Reset: [1, "Reset backup registers"] + TAMP?MSK: + ResetBySoftware: [0, "Tamper x event generates a trigger event and TAMPxF must be cleared by software to allow next tamper event detection"] + ResetByHardware: [1, "Tamper x event generates a trigger event. TAMPxF is masked and internally cleared by hardware. The backup registers are not erased. The tamper x interrupt must not be enabled when TAMP3MSK is set"] + TAMP?NOER: + Erase: [0, "Tamper x event erases the backup registers"] + NotErase: [1, "Tamper x event does not erase the backup registers"] + + CR3: + ITAMP?NOER: + Erase: [0, "Internal tamper x event erases the backup registers"] + NotErase: [1, "Internal tamper x event does not erase the backup registers"] + + FLTCR: + TAMPPUDIS: + Enabled: [0, "Precharge TAMP_INx pins before sampling (enable internal pull-up)"] + Disabled: [1, "Disable precharge of TAMP_INx pins"] + TAMPPRCH: + Cycles1: [0, "1 RTCCLK cycle"] + Cycles2: [1, "2 RTCCLK cycles"] + Cycles4: [2, "4 RTCCLK cycles"] + Cycles8: [3, "8 RTCCLK cycles"] + TAMPFLT: + NoFilter: [0, Tamper event is activated on edge of TAMP_INx input transitions to the active level (no internal pull-up on TAMP_INx input)"] + Filter2: [1, Tamper event is activated after 2 consecutive samples at the active level"] + Filter4: [2, Tamper event is activated after 4 consecutive samples at the active level"] + Filter8: [3, Tamper event is activated after 8 consecutive samples at the active level"] + TAMPFREQ: + Hz_1: [0, "RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)"] + Hz_2: [1, "RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)"] + Hz_4: [2, "RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)"] + Hz_8: [3, "RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)"] + Hz_16: [4, "RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)"] + Hz_32: [5, "RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)"] + Hz_64: [6, "RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)"] + Hz_128: [7, "RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"] + + IER: + ITAMP?IE: + Disabled: [0, "Internal tamper x interrupt disabled"] + Enabled: [1, "Internal tamper x interrupt enabled"] + TAMP?IE: + Disabled: [0, "Tamper x interrupt disabled"] + Enabled: [1, "Tampoer x interrupt enabled"] + + SR: + ITAMP?F: + Idle: [0, "No tamper detected"] + Tamper: [1, "Internal tamper detected"] + TAMP?F: + Idle: [0, "No tamper detected"] + Tamper: [1, "Tamper detected"] + + MISR: + ITAMP?MF: + Idle: [0, "No tamper detected - Masked"] + Tamper: [1, "Internal tamper detected - Masked"] + TAMP?MF: + Idle: [0, "No tamper detected - Masked"] + Tamper: [1, "Tamper detected - Masked"] + + SCR: + CITAMP?F: + _write: + Clear: [1, "Clear tamper flag"] + CTAMP?F: + _write: + Clear: [1, "Clear tamper flag"] + + COUNTR: + COUNT: [0, 0xFFFFFFFF] + + BKP?R: + BKP: [0, 0xFFFFFFFF] + BKP1?R: + BKP: [0, 0xFFFFFFFF] diff --git a/peripherals/tim/tim12_common_wl.yaml b/peripherals/tim/tim12_common_wl.yaml new file mode 100644 index 000000000..dd79cee50 --- /dev/null +++ b/peripherals/tim/tim12_common_wl.yaml @@ -0,0 +1,199 @@ +# Common base for 16bit and 32bit TIM2 peripheral + +"TIM[12]": + CR1: + UIFREMAP: + Disabled: [0, "No remapping. UIF status bit is not copied to TIMx_CNT register bit 31"] + Enabled: [1, "Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31"] + CR2: + TI1S: + Normal: [0, "The TIMx_CH1 pin is connected to TI1 input"] + XOR: [1, "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + MMS: + Reset: [0, "The UG bit from the TIMx_EGR register is used as trigger output"] + Enable: [1, "The counter enable signal, CNT_EN, is used as trigger output"] + Update: [2, "The update event is selected as trigger output"] + ComparePulse: [3, "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + CompareOC1: [4, "OC1REF signal is used as trigger output"] + CompareOC2: [5, "OC2REF signal is used as trigger output"] + CompareOC3: [6, "OC3REF signal is used as trigger output"] + CompareOC4: [7, "OC4REF signal is used as trigger output"] + CCDS: + OnCompare: [0, "CCx DMA request sent when CCx event occurs"] + OnUpdate: [1, "CCx DMA request sent when update event occurs"] + SMCR: + ETP: + NotInverted: [0, "ETR is noninverted, active at high level or rising edge"] + Inverted: [1, "ETR is inverted, active at low level or falling edge"] + ECE: + Disabled: [0, "External clock mode 2 disabled"] + Enabled: [1, "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal"] + ETPS: + Div1: [0, "Prescaler OFF"] + Div2: [1, "ETRP frequency divided by 2"] + Div4: [2, "ETRP frequency divided by 4"] + Div8: [3, "ETRP frequency divided by 8"] + ETF: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + MSM: + NoSync: [0, "No action"] + Sync: [1, "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event"] + TS: + ITR0: [0, "Internal Trigger 0 (ITR0)"] + ITR1: [1, "Internal Trigger 1 (ITR1)"] + ITR2: [2, "Internal Trigger 2 (ITR2)"] + TI1F_ED: [4, "TI1 Edge Detector (TI1F_ED)"] + TI1FP1: [5, "Filtered Timer Input 1 (TI1FP1)"] + TI2FP2: [6, "Filtered Timer Input 2 (TI2FP2)"] + ETRF: [7, "External Trigger input (ETRF)"] + SMS_3: + Disabled: [0, "Slave mode disabled (see SMS[0:2])"] + CombinedResetTrigger: [1, "SMS[0:2] must be 0b000 (DisabledOrCombined). Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter"] + SMS: + DisabledOrCombined: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. If SMS[3]=1 then Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter"] + EncoderMode1: [1, "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level"] + EncoderMode2: [2, "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level"] + EncoderMode3: [3, "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input"] + ResetMode: [4, "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers"] + GatedMode: [5, "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled"] + TriggerMode: [6, "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled"] + ExtClockMode: [7, "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter"] + DIER: + "CC?DE": + Disabled: [0, "CCx DMA request disabled"] + Enabled: [1, "CCx DMA request enabled"] + UDE: + Disabled: [0, "Update DMA request disabled"] + Enabled: [1, "Update DMA request enabled"] + TIE: + Disabled: [0, "Trigger interrupt disabled"] + Enabled: [1, "Trigger interrupt enabled"] + "CC?IE": + Disabled: [0, "CCx interrupt disabled"] + Enabled: [1, "CCx interrupt enabled"] + + SR: + "CC?OF": + _read: + NoOvercapture: [0, "No overcapture has been detected"] + Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set"] + _write: + Clear: [0, "Clear flag"] + TIF: + _read: + NoTrigger: [0, "No trigger event occurred"] + Trigger: [1, "Trigger interrupt pending"] + _write: + Clear: [0, "Clear flag"] + "CC?IF": + _read: + NoMatch: [0, "No campture/compare has been detected"] + Match: [1, "If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register"] + _write: + Clear: [0, "Clear flag"] + EGR: + TG: + _write: + Trigger: [1, "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled"] + "CC?G": + _write: + Trigger: [1, "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register"] + + CCMR?_Input: + IC?F: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + IC?PSC: + Output: [0, "CCx channel is configured as output"] + Capture2: [1, "Capture is done once every 2 events"] + Capture4: [2, "Capture is done once every 4 events"] + Capture8: [3, "Capture is done once every 8 events"] + CC?S: + Output: [0, "CCx channel is configured as output"] + TI1: [1, "CCx channel is configured as input, ICx is mapped on TI1"] + TI2: [2, "CCx channel is configured as input, ICx is mapped on TI2"] + TRC: [3, "CCx channel is configured as input, ICx is mapped on TRC"] + + CCMR[12]_Output: + OC?PE: + Disabled: [0, "Preload register on CCRx disabled. New values written to CCRx are taken into account immediately"] + Enabled: [1, "Preload register on CCRx enabled. Preload value is loaded into active register on each update event"] + OC?CE: + Disabled: [0, "OCxRef is not affected by the ocref_clr_int signal"] + Enabled: [1, "OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal"] + OC?FE: + Disabled: [0, "Fast output disabled"] + Enabled: [1, "Fast output enabled"] + CC?S: + "Output": [0, "CCx channel is configured as output"] + TI1: [1, "CCx channel is configured as input, ICx is mapped on TI1"] + TI2: [2, "CCx channel is configured as input, ICx is mapped on TI2"] + TRC: [3, "CCx channel is configured as input, ICx is mapped on TRC"] + OC?M: + Frozen: [0, "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"] + ActiveOnMatch: [1, "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1"] + InactiveOnMatch: [2, "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved"] + Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"] + ForceInactive: [4, "OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"] + ForceActive: [5, "OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"] + PwmMode1: [6, "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] + PwmMode2: [7, "Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1"] + OC?M_3: + Normal: [0, "Normal output compare mode (modes 0-7)"] + Extended: [1, "Extended output compare mode (modes 7-15)"] + + CCER: + "CC?NP": + ActiveHigh: [0, "OCxN active high"] + ActiveLow: [1, "OCxN active low"] + "CC?P": + RisingEdge: [0, "Noninverted/rising edge"] + FallingEdge: [1, "Inverted/falling edge"] + "CC?E": + Disabled: [0, "Capture disabled"] + Enabled: [1, "Capture enabled"] + + DCR: + DBL: [0, 0b10001] + DBA: [0, 31] + + AF1: + _modify: + ResETRSEL: + name: ETRSEL + ETRSEL: + Legacy: [0, 'ETR legacy mode'] + COMP1: [1, 'COMP1 output'] + COMP2: [2, 'COMP2 output'] + TISEL: + TI?SEL: + Selected: [0, "TIM1_CHx input selected"] diff --git a/peripherals/tim/tim16_wl.yaml b/peripherals/tim/tim16_wl.yaml new file mode 100644 index 000000000..28d84a5dd --- /dev/null +++ b/peripherals/tim/tim16_wl.yaml @@ -0,0 +1,193 @@ +_include: + - tim16.yaml + +TIM1[67]: + _include: + - tim_1ch_16bit.yaml + CR1: + UIFREMAP: + Disabled: [0, "No remapping. UIF status bit is not copied to TIMx_CNT register bit 31"] + Enabled: [1, "Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31"] + + DIER: + UDE: + Disabled: [0, "Update DMA request disabled"] + Enabled: [1, "Update DMA request enabled"] + + SR: + "CC?OF": + _read: + NoOvercapture: [0, "No overcapture has been detected"] + Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set"] + _write: + Clear: [0, "Clear flag"] + BIF: + _read: + NoBreak: [0, "No break event occurred"] + Break: [1, "Break interrupt pending"] + _write: + Clear: [0, "Clear flag"] + COMIF: + _read: + NoCOM: [0, "No COM event occurred"] + COM: [1, "COM interrupt pending"] + _write: + Clear: [0, "Clear flag"] + "CC?IF": + _read: + NoMatch: [0, "No campture/compare has been detected"] + Match: [1, "If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register"] + _write: + Clear: [0, "Clear flag"] + + EGR: + BG: + _write: + Trigger: [1, "A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled"] + COMG: + _write: + Trigger: [1, "When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated"] + "CC?G": + _write: + Trigger: [1, "If CC1 is an output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CC1 is an input: The current value of the counter is captured in TIMx_CCR1 register"] + + CCMR?_Input: + IC?F: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + IC?PSC: + Output: [0, "CCx channel is configured as output"] + Capture_2: [1, "Capture is done once every 2 events"] + Capture_4: [2, "Capture is done once every 4 events"] + Capture_8: [3, "Capture is done once every 8 events"] + CC?S: + Output: [0, "CCx channel is configured as output"] + TI1: [1, "CCx channel is configured as input, ICx is mapped on TI1"] + TI2: [2, "CCx channel is configured as input, ICx is mapped on TI2"] + TRC: [3, "CCx channel is configured as input, ICx is mapped on TRC"] + + CCMR[12]_Output: + OC?PE: + Disabled: [0, "Preload register on CCRx disabled. New values written to CCRx are taken into account immediately"] + Enabled: [1, "Preload register on CCRx enabled. Preload value is loaded into active register on each update event"] + OC?FE: + Disabled: [0, "Fast output disabled"] + Enabled: [1, "Fast output enabled"] + CC?S: + "Output": [0, "CCx channel is configured as output"] + TI1: [1, "CCx channel is configured as input, ICx is mapped on TI1"] + OC?M: + Frozen: [0, "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"] + ActiveOnMatch: [1, "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"] + InactiveOnMatch: [2, "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] + Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + ForceInactive: [4, "OCyREF is forced low"] + ForceActive: [5, "OCyREF is forced high"] + PwmMode1: [6, "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active"] + PwmMode2: [7, "Inversely to PwmMode1"] + OC?M_3: + Normal: [0, "Normal output compare mode (modes 0-7)"] + + CCER: + "CC?NP": + ActiveHigh: [0, "OCxN active high"] + ActiveLow: [1, "OCxN active low"] + "CC?NE": + Disabled: [0, "Complementary output disabled"] + Enabled: [1, "Complementary output enabled"] + "CC?P": + RisingEdge: [0, "Noninverted/rising edge"] + FallingEdge: [1, "Inverted/falling edge"] + "CC?E": + Disabled: [0, "Capture disabled"] + Enabled: [1, "Capture enabled"] + + RCR: + REP: [0, 0xFF] + + BDTR: + _modify: + DT: + name: DTG + BKBID: + Input: [0, "Break input BRK in input mode"] + Bidirectional: [1, "Break input BRK in bidirectional mode"] + BKDSRM: + Armed: [0, "Break input BRK is armed"] + Disarmed: [1, "Break input BRK is disarmed"] + MOE: + Disabled: [0, "OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit"] + Enabled: [1, "OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)"] + AOE: + Disabled: [0, "MOE can be set only by software"] + Enabled: [1, "MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)"] + BKP: + ActiveLow: [0, "Break input BRK is active low"] + ActiveHigh: [1, "Break input BRK is active high"] + BKE: + Disabled: [0, "Break inputs (BRK and CCS clock failure event) disabled"] + Enabled: [1, "Break inputs (BRK and CCS clock failure event) enabled"] + OSSR: + Disabled: [0, "OC/OCN outputs are disabled when inactive"] + Enabled: [1, "OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1"] + OSSI: + Disabled: [0, "OC/OCN outputs are disabled when inactive"] + Enabled: [1, "OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime"] + LOCK: + "Off": [0, "No write protection"] + Level1: [1, "Level 1 write protection"] + Level2: [2, "Level 2 write protection"] + Level3: [3, "Level 3 write protection"] + DTG: [0, 0xFF] + + DCR: + DBL: [0, 0b10001] + DBA: [0, 31] + + DMAR: + DMAB: [0, 0xFFFF] + + OR1: + TI1_RMP: + GPIO : [0, "TI1 is connected to GPIO"] + LSI : [1, "TI1 is connected to LSI"] + LSE : [2, "TI1 is connected to LSE"] + RTC : [3, "TI1 is connected to RTC wake-up interrupt"] + + AF1: + BKCMP2P: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BKCMP1P: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BKINP: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BKCMP2E: + Disabled: [0, "COMP2 input disabled"] + Enabled: [1, "COMP2 input enabled"] + BKCMP1E: + Disabled: [0, "COMP1 input disabled"] + Enabled: [1, "COMP1 input enabled"] + BKINE: + Disabled: [0, "BKIN input disabled"] + Enabled: [1, "BKIN input enabled"] + + TISEL: + TISEL: + Selected: [0, "TIM1_CH1 input selected"] diff --git a/peripherals/tim/tim1_wl.yaml b/peripherals/tim/tim1_wl.yaml new file mode 100644 index 000000000..c0bac006f --- /dev/null +++ b/peripherals/tim/tim1_wl.yaml @@ -0,0 +1,269 @@ +TIM1: + CR2: + MMS2: + "Reset": [0b0000, "Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset"] + Enable: [0b0001, "Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)"] + Update: [0b0010, "Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer"] + ComparePulse: [0b0011, "Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2)"] + CompareOC1: [0b0100, "Compare - OC1REFC signal is used as trigger output (TRGO2)"] + CompareOC2: [0b0101, "Compare - OC2REFC signal is used as trigger output (TRGO2)"] + CompareOC3: [0b0110, "Compare - OC3REFC signal is used as trigger output (TRGO2)"] + CompareOC4: [0b0111, "Compare - OC4REFC signal is used as trigger output (TRGO2)"] + CompareOC5: [0b1000, "Compare - OC5REFC signal is used as trigger output (TRGO2)"] + CompareOC6: [0b1001, "Compare - OC6REFC signal is used as trigger output (TRGO2)"] + PulseOC4: [0b1010, "Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2"] + PulseOC6: [0b1011, "Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2"] + RisingOC4_6: [0b1100, "Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2"] + RisingOC4_FallingOC6: [0b1101, "Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2"] + RisingOC5_6: [0b1110, "Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2"] + RisingOC5_FallingOC6: [0b1111, "Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2"] + OIS?N: + Disabled: [0, "OCxN=0 after a dead-time when MOE=0"] + Enabled: [1, "OCxN=1 after a dead-time when MOE=0"] + OIS?: + Disabled: [0, "OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0"] + Enabled: [1, "OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0"] + CCUS: + Bit: [0, "When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only"] + BitOrEdge: [1, "When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI"] + CCPC: + NotPreloaded: [0, "CCxE, CCxNE and OCxM bits are not preloaded"] + Preloaded: [1, "CCxE, CCxNE and OCxM bits are preloaded"] + + DIER: + TDE: + Disabled: [0, "Trigger DMA request disabled"] + Enabled: [1, "Trigger DMA request enabled"] + COMDE: + Disabled: [0, "COM DMA request disabled"] + Enabled: [1, "COM DMA request enabled"] + BIE: + Disabled: [0, "Break interrupt disabled"] + Enabled: [1, "Break interrupt enabled"] + COMIE: + Disabled: [0, "COM interrupt disabled"] + Enabled: [1, "COM interrupt enabled"] + + SR: + SBIF: + _read: + NoTrigger: [0, "No break event occurred"] + Trigger: [1, "An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register"] + _write: + Clear: [0, "Clear flag"] + B2IF: + _read: + NoTrigger: [0, "No break event occurred"] + Trigger: [1, "An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register"] + _write: + Clear: [0, "Clear flag"] + BIF: + _read: + NoTrigger: [0, "No break event occurred"] + Trigger: [1, "An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register"] + _write: + Clear: [0, "Clear flag"] + + EGR: + _modify: + COM: + name: COMG + B2G: + _write: + Trigger: [1, "A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled"] + BG: + _write: + Trigger: [1, "A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled"] + COMG: + _write: + Trigger: [1, "When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated"] + + AF1: + BKCMP2P: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BKCMP1P: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BKINP: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BKCMP2E: + Disabled: [0, "COMP2 input disabled"] + Enabled: [1, "COMP2 input enabled"] + BKCMP1E: + Disabled: [0, "COMP1 input disabled"] + Enabled: [1, "COMP1 input enabled"] + BKINE: + Disabled: [0, "BKIN input disabled"] + Enabled: [1, "BKIN input enabled"] + + AF2: + BK2CMP2P: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BK2CMP1P: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BK2INP: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BK2CMP2E: + Disabled: [0, "COMP2 input disabled"] + Enabled: [1, "COMP2 input enabled"] + BK2CMP1E: + Disabled: [0, "COMP1 input disabled"] + Enabled: [1, "COMP1 input enabled"] + BK2INE: + Disabled: [0, "BKIN input disabled"] + Enabled: [1, "BKIN input enabled"] + + BDTR: + _modify: + DT: + name: DTG + BK2BID: + Input: [0, "Break input BRK2 in input mode"] + Bidirectional: [1, "Break input BRK2 in bidirectional mode"] + BKBID: + Input: [0, "Break input BRK in input mode"] + Bidirectional: [1, "Break input BRK in bidirectional mode"] + BK2DSRM: + Armed: [0, "Break input BRK2 is armed"] + Disarmed: [1, "Break input BRK2 is disarmed"] + BKDSRM: + Armed: [0, "Break input BRK is armed"] + Disarmed: [1, "Break input BRK is disarmed"] + BK2P: + Low: [0, "Break input BRK2 is active low"] + High: [1, "Break input BRK2 is active high"] + BK2E: + Disabled: [0, "Break function disabled"] + Enabled: [1, "Break function enabled"] + BK2F: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + BKF: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + MOE: + Disabled: [0, "In response to a break 2 event OC and OCN outputs are disabled - In response to a break event or if MOE is written to 0 OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit"] + Enabled: [1, "OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)"] + AOE: + Disabled: [0, "MOE can be set only by software"] + Enabled: [1, "MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)"] + BKP: + ActiveLow: [0, "Break input BRK is active low"] + ActiveHigh: [1, "Break input BRK is active high"] + BKE: + Disabled: [0, "Break function disabled"] + Enabled: [1, "Break function enabled"] + OSSR: + Disabled: [0, "OC/OCN outputs are disabled when inactive"] + Enabled: [1, "OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1"] + OSSI: + Disabled: [0, "OC/OCN outputs are disabled when inactive"] + Enabled: [1, "OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime"] + LOCK: + "Off": [0, "No write protection"] + Level1: [1, "Level 1 write protection"] + Level2: [2, "Level 2 write protection"] + Level3: [3, "Level 3 write protection"] + DTG: [0, 0xFF] + + CCMR3_Output: + OC?PE: + Disabled: [0, "Preload register on CCRx disabled. New values written to CCRx are taken into account immediately"] + Enabled: [1, "Preload register on CCRx enabled. Preload value is loaded into active register on each update event"] + OC?CE: + Disabled: [0, "OCxRef is not affected by the ocref_clr_int signal"] + Enabled: [1, "OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal"] + OC?FE: + Disabled: [0, "Fast output disabled"] + Enabled: [1, "Fast output enabled"] + OC?M: + Frozen: [0, "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs. Alt (OCxM[3]): Channel active until trigger is detected on TRGI signal"] + ActiveOnMatch: [1, "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register. Alt (OCxM[3]): OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] + InactiveOnMatch: [2, "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"] + Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy"] + ForceInactive: [4, "OCyREF is forced low. Alt (OCxM[3]): OC1REFC is the logical OR between OC1REF and OC2REF"] + ForceActive: [5, "OCyREF is forced high. Alt (OCxM[3]): OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] + PwmMode1: [6, "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active. Alt (OCxM[3]): OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] + PwmMode2: [7, "Inversely to PwmMode1. Alt (OCxM[3]): Assymetric PWM Mode 2: OC1REFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] + OC?M_3: + NormalModes: [0, "Choose low modes (0-7)"] + AlternateModes: [1, "Choose high modes (8-15)"] + + CCER: + "CC?NE": + Disabled: [0, "Complementary output disabled"] + Enabled: [1, "Complementary output enabled"] + + CNT: + CNT: [0, 65535] + ARR: + ARR: [0, 65535] + RCR: + REP: [0, 65535] + CCR1: + CCR1: [0, 65535] + CCR2: + CCR2: [0, 65535] + CCR3: + CCR3: [0, 65535] + CCR4: + CCR4: [0, 65535] + CCR5: + GC5C3: + Disabled: [0, "No effect of OC5REF on OC3REFC"] + Enabled: [1, "OC3REFC is the logical AND of OC3REFC and OC5REF"] + GC5C2: + Disabled: [0, "No effect of OC5REF on OC2REFC"] + Enabled: [1, "OC2REFC is the logical AND of OC2REFC and OC5REF"] + GC5C1: + Disabled: [0, "No effect of OC5REF on OC1REFC"] + Enabled: [1, "OC1REFC is the logical AND of OC1REFC and OC5REF"] + CCR5: [0, 65535] + CCR6: + CCR6: [0, 65535] + DMAR: + DMAB: [0, 0xFFFF] + OR1: + TI1_RMP: + IO: [0, 'TIM1 input capture 1 is connected to I/O'] + COMP1: [1, 'TIM1 input capture 1 is connected to COMP1 output'] + TIM1_ETR_ADC1_RMP: + Select: [0, 'TIM1_ETR is not connected to ADC AWDx (must be selected when the ETR comes from the ETR input pin)'] + ADC_AWD1: [1, 'TIM1_ETR is connected to ADC AWD1'] + ADC_AWD2: [2, 'TIM1_ETR is connected to ADC AWD2'] + ADC_AWD3: [3, 'TIM1_ETR is connected to ADC AWD3'] + + diff --git a/peripherals/tim/tim2_wl.yaml b/peripherals/tim/tim2_wl.yaml new file mode 100644 index 000000000..61f49e857 --- /dev/null +++ b/peripherals/tim/tim2_wl.yaml @@ -0,0 +1,26 @@ +TIM2: + _include: + - ../../devices/common_patches/tim/tim2_common_32bit.yaml + OR1: + TI4_RMP: + GPIO: [0, "TIM2 TI4 is connected to GPIO: Refer to Alternate Function mapping"] + COMP_1: [1, "TIM2 TI4 is connected to COMP1_OUT"] + COMP_2: [2, "TIM2 TI4 is connected to COMP2_OUT"] + COMP_12: [3, "TIM2 TI4 is connected to a logical OR between COMP1_OUT and COMP2_OUT"] + ETR_RMP: + GPIO: [0, "TIM2 ETR is connected to GPIO: Refer to Alternate Function mapping"] + TIM2_ETR: [1, "LSE internal clock is connected to TIM2_ETR input"] + CNT: + CNT: [0, 0xFFFFFFFF] + ARR: + ARR: [0, 0xFFFFFFFF] + CCR1: + CCR1: [0, 0xFFFFFFFF] + CCR2: + CCR2: [0, 0xFFFFFFFF] + CCR3: + CCR3: [0, 0xFFFFFFFF] + CCR4: + CCR4: [0, 0xFFFFFFFF] + DMAR: + DMAB: [0, 0xFFFF] diff --git a/peripherals/usart/fifoen_common.yaml b/peripherals/usart/fifoen_common.yaml new file mode 100644 index 000000000..2a9403e55 --- /dev/null +++ b/peripherals/usart/fifoen_common.yaml @@ -0,0 +1,31 @@ +CR1: + RXFFIE: + Disabled: [0, "Interrupt inhibited"] + Enabled: [1, "USART interrupt generated when RXFF = 1 in the USART_ISR register"] + TXFEIE: + Disabled: [0, "Interrupt inhibited"] + Enabled: [1, "USART interrupt generated when TXFE = 1 in the USART_ISR register"] + FIFOEN: + Disabled: [0, "FIFO mode is disabled"] + Enabled: [1, "FIFO mode is enabled"] +CR3: + TXFTCFG: + Depth_1_8: [0, "TXFIFO reaches 1/8 of its depth"] + Depth_1_4: [1, "TXFIFO reaches 1/4 of its depth"] + Depth_1_2: [2, "TXFIFO reaches 1/2 of its depth"] + Depth_3_4: [3, "TXFIFO reaches 3/4 of its depth"] + Depth_7_8: [4, "TXFIFO reaches 7/8 of its depth"] + Empty: [5, "TXFIFO becomes empty"] + RXFTIE: + Disabled: [0, "Interrupt inhibited"] + Enabled: [1, "USART interrupt generated when Receive FIFO reaches the threshold programmed in RXFTCFG"] + RXFTCFG: + Depth_1_8: [0, "RXFIFO reaches 1/8 of its depth"] + Depth_1_4: [1, "RXFIFO reaches 1/4 of its depth"] + Depth_1_2: [2, "RXFIFO reaches 1/2 of its depth"] + Depth_3_4: [3, "RXFIFO reaches 3/4 of its depth"] + Depth_7_8: [4, "RXFIFO reaches 7/8 of its depth"] + Full: [5, "RXFIFO becomes full"] + TXFTIE: + Disabled: [0, "Interrupt inhibited"] + Enabled: [1, "USART interrupt generated when Transmit FIFO reaches the threshold programmed in TXFTCFG"] diff --git a/peripherals/usart/fifoen_usart.yaml b/peripherals/usart/fifoen_usart.yaml new file mode 100644 index 000000000..844f3dbca --- /dev/null +++ b/peripherals/usart/fifoen_usart.yaml @@ -0,0 +1,10 @@ +CR3: + TCBGTIE: + Disabled: [0, "Interrupt inhibited"] + Enabled: [1, "USART interrupt generated whenever TCBGT=1 in the USART_ISR register"] +ICR: + TCBGTCF: + Clear: [1, "Clear the TCBGT flag in the ISR register"] + TXFECF: + Clear: [1, "Clear the TXFE flag in the ISR register"] + diff --git a/peripherals/usart/lpuart_wl.yaml b/peripherals/usart/lpuart_wl.yaml new file mode 100644 index 000000000..f0020fb63 --- /dev/null +++ b/peripherals/usart/lpuart_wl.yaml @@ -0,0 +1,152 @@ +# LPUART in WL family +"LPUART,LPUART*": + _include: + - _v2_AB_common.yaml + - _v2_with_7bit_data.yaml + - fifoen_common.yaml + CR1: + DEAT: [0, 0b11111] + DEDT: [0, 0b11111] + CMIE: + Disabled: [0, "Interrupt is disabled"] + Enabled: [1, "Interrupt is generated when the CMF bit is set in the ISR register"] + MME: + Disabled: [0, "Receiver in active mode permanently"] + Enabled: [1, "Receiver can switch between mute mode and active mode"] + WAKE: + Idle: [0, "Idle line"] + Address: [1, "Address mask"] + PCE: + Disabled: [0, "Parity control disabled"] + Enabled: [1, "Parity control enabled"] + PS: + Even: [0, "Even parity"] + Odd: [1, "Odd parity"] + PEIE: + Disabled: [0, "Interrupt is disabled"] + Enabled: [1, "Interrupt is generated whenever PE=1 in the ISR register"] + TXEIE: + Disabled: [0, "Interrupt is disabled"] + Enabled: [1, "Interrupt is generated whenever TXE=1 in the ISR register"] + TCIE: + Disabled: [0, "Interrupt is disabled"] + Enabled: [1, "Interrupt is generated whenever TC=1 in the ISR register"] + RXNEIE: + Disabled: [0, "Interrupt is disabled"] + Enabled: [1, "Interrupt is generated whenever ORE=1 or RXNE=1 in the ISR register"] + IDLEIE: + Disabled: [0, "Interrupt is disabled"] + Enabled: [1, "Interrupt is generated whenever IDLE=1 in the ISR register"] + TE: + Disabled: [0, "Transmitter is disabled"] + Enabled: [1, "Transmitter is enabled"] + RE: + Disabled: [0, "Receiver is disabled"] + Enabled: [1, "Receiver is enabled"] + UE: + Disabled: [0, "UART is disabled"] + Enabled: [1, "UART is enabled"] + CR2: + ADD: [0, 0xFF] + MSBFIRST: + LSB: [0, "data is transmitted/received with data bit 0 first, following the start bit"] + MSB: [1, "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit"] + DATAINV: + Positive: [0, "Logical data from the data register are send/received in positive/direct logic"] + Negative: [1, "Logical data from the data register are send/received in negative/inverse logic"] + TXINV: + Standard: [0, "TX pin signal works using the standard logic levels"] + Inverted: [1, "TX pin signal values are inverted"] + RXINV: + Standard: [0, "RX pin signal works using the standard logic levels"] + Inverted: [1, "RX pin signal values are inverted"] + SWAP: + Standard: [0, "TX/RX pins are used as defined in standard pinout"] + Swapped: [1, "The TX and RX pins functions are swapped"] + STOP: + Stop1: [0, "1 stop bit"] + Stop2: [2, "2 stop bit"] + ADDM7: + Bit4: [0, "4-bit address detection"] + Bit7: [1, "7-bit address detection"] + CR3: + DEP: + High: [0, "DE signal is active high"] + Low: [1, "DE signal is active low"] + DEM: + Disabled: [0, "DE function is disabled"] + Enabled: [1, "The DE signal is output on the RTS pin"] + DDRE: + NotDisabled: [0, "DMA is not disabled in case of reception error"] + Disabled: [1, "DMA is disabled following a reception error"] + OVRDIS: + Enabled: [0, "Overrun Error Flag, ORE, is set when received data is not read before receiving new data"] + Disabled: [1, "Overrun functionality is disabled. If new data is received while the RXNE flag is still set the ORE flag is not set and the new received data overwrites the previous content of the RDR register"] + CTSIE: + Disabled: [0, "Interrupt is inhibited"] + Enabled: [1, "An interrupt is generated whenever CTSIF=1 in the ISR register"] + CTSE: + Disabled: [0, "CTS hardware flow control disabled"] + Enabled: [1, "CTS mode enabled, data is only transmitted when the CTS input is asserted"] + RTSE: + Disabled: [0, "RTS hardware flow control disabled"] + Enabled: [1, "RTS output enabled, data is only requested when there is space in the receive buffer"] + DMAT: + Disabled: [0, "DMA mode is disabled for transmission"] + Enabled: [1, "DMA mode is enabled for transmission"] + DMAR: + Disabled: [0, "DMA mode is disabled for reception"] + Enabled: [1, "DMA mode is enabled for reception"] + HDSEL: + NotSelected: [0, "Half duplex mode is not selected"] + Selected: [1, "Half duplex mode is selected"] + EIE: + Disabled: [0, "Interrupt is inhibited"] + Enabled: [1, "An interrupt is generated when FE=1 or ORE=1 or NF=1 in the ISR register"] + RQR: + TXFRQ: + Discard: [1, "Set the TXE flags. This allows to discard the transmit data"] + RXFRQ: + Discard: [1, "clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition"] + MMRQ: + Mute: [1, "Puts the USART in mute mode and sets the RWU flag"] + SBKRQ: + Break: [1, "sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available"] + ICR: + CMCF: + Clear: [1, "Clears the CMF flag in the ISR register"] + CTSCF: + Clear: [1, "Clears the CTSIF flag in the ISR register"] + TCCF: + Clear: [1, "Clears the TC flag in the ISR register"] + IDLECF: + Clear: [1, "Clears the IDLE flag in the ISR register"] + ORECF: + Clear: [1, "Clears the ORE flag in the ISR register"] + NCF: + Clear: [1, "Clears the NF flag in the ISR register"] + FECF: + Clear: [1, "Clears the FE flag in the ISR register"] + PECF: + Clear: [1, "Clears the PE flag in the ISR register"] + RDR: + RDR: [0, 0x1FF] + TDR: + TDR: [0, 0x1FF] + BRR: + BRR: [0, 0xFFFFFF] + PRESC: + PRESCALER: + Div1: [0b0000, "/1"] + Div2: [0b0001, "/2"] + Div4: [0b0010, "/4"] + Div6: [0b0011, "/6"] + Div8: [0b0100, "/8"] + Div10: [0b0101, "/10"] + Div12: [0b0110, "/12"] + Div16: [0b0111, "/16"] + Div32: [0b1000, "/32"] + Div64: [0b1001, "/64"] + Div128: [0b1010, "/128"] + Div256: [0b1011, "/256"] + diff --git a/peripherals/usart/usart_wl.yaml b/peripherals/usart/usart_wl.yaml new file mode 100644 index 000000000..33a6b87ba --- /dev/null +++ b/peripherals/usart/usart_wl.yaml @@ -0,0 +1,30 @@ +"USART*": + _include: + - fifoen_common.yaml + - fifoen_usart.yaml + - _v2_AB_common.yaml + CR2: + DIS_NSS: + Disabled: [0, "SPI slave selection depends on NSS input pin"] + Enabled: [1, "SPI slave is always selected and NSS input pin is ignored"] + SLVEN: + Disabled: [0, "Slave mode disabled"] + Enabled: [1, "Slave mode enabled"] + ICR: + UDRCF: + Clear: [1, "Clear the UDR flag in the ISR register"] + PRESC: + PRESCALER: + Div1: [0b0000, "/1"] + Div2: [0b0001, "/2"] + Div4: [0b0010, "/4"] + Div6: [0b0011, "/6"] + Div8: [0b0100, "/8"] + Div10: [0b0101, "/10"] + Div12: [0b0110, "/12"] + Div16: [0b0111, "/16"] + Div32: [0b1000, "/32"] + Div64: [0b1001, "/64"] + Div128: [0b1010, "/128"] + Div256: [0b1011, "/256"] + diff --git a/peripherals/vrefbuf/vrefbuf_wl.yaml b/peripherals/vrefbuf/vrefbuf_wl.yaml new file mode 100644 index 000000000..cf1a6e848 --- /dev/null +++ b/peripherals/vrefbuf/vrefbuf_wl.yaml @@ -0,0 +1,18 @@ +# Vrefbuf peripheral for WL family + +VREFBUF: + CSR: + VRR: + NotReady: [0, "The voltage reference buffer output is not ready"] + Ready: [1, "The voltage reference buffer output reached the requested level"] + VRS: + V2_048: [0, "Voltage reference set to VREF_OUT1 (around 2.048 V)"] + V2_5: [1, "Voltage reference set to VREF_OUT2 (around 2.5 V)"] + HIZ: + Connected: [0, "VREF+ pin is internally connected to the voltage reference buffer output"] + HighZ: [1, "VREF+ pin is high impedance"] + ENVR: + Disabled: [0, "Internal voltage reference mode disable (external voltage reference mode)"] + Enabled: [1, "Internal voltage reference mode (reference buffer enable or hold mode) enable"] + CCR: + TRIM: [0, 0b111111]