From a0dac036c4c50edc7185136a471799498e87c270 Mon Sep 17 00:00:00 2001 From: Maxime Date: Sun, 15 Aug 2021 19:35:35 +0200 Subject: [PATCH 1/5] stm32mp1: GPIO, IPCC, ADC, Timers (100%), USART --- devices/stm32mp157.yaml | 462 ++++++++++++++++++++ peripherals/adc/adc_v3_common_mp1.yaml | 40 ++ peripherals/adc/adc_v3_mp1.yaml | 119 ++++++ peripherals/gpio/gpio_with_seccfgr.yaml | 8 + peripherals/ipcc/ipcc_mp1.yaml | 113 +++++ peripherals/tim/tim_gp_mp1.yaml | 534 ++++++++++++++++++++++++ 6 files changed, 1276 insertions(+) create mode 100644 peripherals/adc/adc_v3_common_mp1.yaml create mode 100644 peripherals/adc/adc_v3_mp1.yaml create mode 100644 peripherals/gpio/gpio_with_seccfgr.yaml create mode 100644 peripherals/ipcc/ipcc_mp1.yaml create mode 100644 peripherals/tim/tim_gp_mp1.yaml diff --git a/devices/stm32mp157.yaml b/devices/stm32mp157.yaml index f63d96317..06947f496 100644 --- a/devices/stm32mp157.yaml +++ b/devices/stm32mp157.yaml @@ -14,7 +14,469 @@ _modify: vendorSystickConfig: "false" DSIHOST1: name: DSI + description: DSI + groupName: DSI + # The SVD calls ADC1 ADC. + ADC: + name: ADC1 + description: ADC1 + groupName: ADC1 + ADC_common: + name: ADC_Common +# Stripping prefixes DSI: _strip: - "DSI_" +GPIO?: + _strip: + - "GPIO?_" +ADC*: + _strip: + - "ADC_" +IPCC: + _strip: + - "IPCC_" +TIM?: + _strip: + - TIM?_ +TIM1?: + _strip: + - TIM1?_ + - TIM?_ + +# Cleaning up the timers +TIM*: + CR1: + _modify: + OMP: + name: OPM +TIM1: + _modify: + CCMR1ALTERNATE1: + name: CCMR1_Input + CCMR2ALTERNATE17: + name: CCMR2_Input + CCMR3: + name: CCMR3_Output + +TIM2: + _add: + AF1: + description: "TIM2 alternate function option register 1" + access: read-write + resetValue: 0x00000000 + addressOffset: 0x60 + fields: + ETRSEL: + description: ETR source selection + bitOffset: 14 + bitWidth: 4 + _modify: + CCMR1ALTERNATE2: + name: CCMR1_Input + CCMR2ALTERNATE18: + name: CCMR2_Input +TIM3: + _add: + AF1: + description: "TIM3 alternate function option register 1" + access: read-write + resetValue: 0x00000000 + addressOffset: 0x60 + fields: + ETRSEL: + description: ETR source selection + bitOffset: 14 + bitWidth: 4 + _modify: + CCMR1ALTERNATE3: + name: CCMR1_Input + CCMR2ALTERNATE19: + name: CCMR2_Input +TIM4: + _add: + AF1: + description: "TIM4 alternate function option register 1" + access: read-write + resetValue: 0x00000000 + addressOffset: 0x60 + fields: + ETRSEL: + description: ETR source selection + bitOffset: 14 + bitWidth: 4 + _modify: + CCMR1ALTERNATE4: + name: CCMR1_Input + CCMR2ALTERNATE20: + name: CCMR2_Input +TIM5: + _add: + AF1: + description: "TIM5 alternate function option register 1" + access: read-write + resetValue: 0x00000000 + addressOffset: 0x60 + fields: + ETRSEL: + description: ETR source selection + bitOffset: 14 + bitWidth: 4 + _modify: + CCMR1ALTERNATE5: + name: CCMR1_Input + CCMR2ALTERNATE21: + name: CCMR2_Input +TIM8: + _modify: + CCMR1ALTERNATE8: + name: CCMR1_Input + CCMR2ALTERNATE24: + name: CCMR2_Input + CCMR3: + name: CCMR3_Output + CCMR3_Output: + _modify: + OC5M3: + name: OC5M_3 + OC6M3: + name: OC6M_3 +TIM12: + _modify: + CCMR1_output: + name: CCMR1_Output + CCMR1_input: + name: CCMR1_Input + SMCR: + _modify: + TS_3: + name: TS3 + TS_4: + name: TS4 + +TIM[1-58],TIM12: + SMCR: + _merge: + TS_4_3: TS[34] + +TIM[1-8]: + EGR: + _modify: + COM: + name: COMG + +TIM[1-58],TIM1[25]: + SMCR: + _modify: + SMS3: + name: SMS_3 + +TIM[18],TIM1[5-7]: + BDTR: + _modify: + DT: + name: DTG + +TIM1[34]: + _modify: + CCMR1: + name: CCMR1_Output + CCMR1_Output: + _modify: + OC1M3: + name: OC1M_3 + +TIM[18]: + CCMR3_Output: + _modify: + OC5M3: + name: OC5M_3 + OC6M3: + name: OC6M_3 +TIM1[3-4]: + _add: + CCMR1_Input: + description: > + The same register can be used for input capture mode (this section) or for output compare + mode (next section). The direction of a channel is defined by configuring the corresponding + CCxS bits. All the other bits in this register have different functions in input and output + modes + access: read-write + resetValue: 0x00000000 + addressOffset: 0x18 + fields: + IC1F: + description: Input capture 1 filter + bitOffset: 4 + bitWidth: 4 + IC1PSC: + description: Input capture 1 prescaler + bitOffset: 2 + bitWidth: 2 + CC1S: + description: Capture/Compare 1 selection + bitOffset: 0 + bitWidth: 2 +TIM[25]: + _modify: + CNT: + size: 32 + ARR: + size: 32 + CCR?: + size: 32 + CNT: + _delete: + - UIFCPY + _modify: + CNT: + bitWidth: 32 + ARR: + _modify: + ARR: + bitWidth: 32 + CCR?: + _modify: + CCR?: + bitWidth: 32 +TIM[2-7]: + _delete: + - CCMR3 + - CCR6 + - RCR + - BDTR +TIM[2-5]: + _delete: + - CCR5 + _add: + TISEL: + description: Timer input selection register + access: read-write + resetValue: 0x00000000 + addressOffset: 0x68 + fields: + TI1SEL: + description: TI1[0] to TI1[15] input selection + bitOffset: 0 + bitWidth: 4 + TI2SEL: + description: TI2[0] to TI2[15] input selection + bitOffset: 8 + bitWidth: 4 + TI3SEL: + description: TI3[0] to TI3[15] input selection + bitOffset: 16 + bitWidth: 4 + TI4SEL: + description: TI4[0] to TI4[15] input selection + bitOffset: 24 + bitWidth: 4 + CR2: + _delete: + - CCPC + - CCUS + - OIS* + - MMS2 + DIER: + _delete: + - COMIE + - BIE + - COMDE + SR: + _delete: + - COMIF + - BIF + - B2IF + - SBIF + - CC5IF + - CC6IF + EGR: + _delete: + - COMG + - BG + - B2G + CCER: + _delete: + - CC?NE + - CC5* + - CC6* + DMAR: + _modify: + DMAB: + bitWidth: 16 +TIM[67]: + _delete: + - SMCR + - CCMR* + - CCER + - CCR* + - DCR + - DMAR + CR1: + _delete: + - DIR + - CMS + - CKD + CR2: + _delete: + - C* + - O* + - MMS2 + - TI1S + DIER: + _delete: + - B* + - C* + - T* + SR: + _delete: + - B* + - C* + - S* + - T* + EGR: + _delete: + - B* + - C* + - T* + +TIM[1-58]: + _add: + CCMR1_Output: + description: > + The same register can be used for output compare mode (this section) or for input capture + mode (previous section). The direction of a channel is defined by configuring the + corresponding CCxS bits. All the other bits of this register have a different function for input + capture and for output compare modes. It is possible to combine both modes independently + (e.g. channel 1 in input capture mode and channel 2 in output compare mode). + access: read-write + resetValue: 0x00000000 + addressOffset: 0x18 + fields: + OC2M_3: + description: Output Compare 2 mode[3] + bitOffset: 24 + bitWidth: 1 + OC1M_3: + description: Output Compare 1 mode[3] + bitOffset: 16 + bitWidth: 1 + OC2CE: + description: Output Compare 2 clear enable + bitOffset: 15 + bitWidth: 1 + OC4M: + description: Output Compare 2 mode + bitOffset: 12 + bitWidth: 3 + OC2PE: + description: Output Compare 2 preload enable + bitOffset: 11 + bitWidth: 1 + OC2FE: + description: Output Compare 2 fast enable + bitOffset: 10 + bitWidth: 1 + CC2S: + description: Capture/Compare 2 selection + bitOffset: 8 + bitWidth: 2 + OC1CE: + description: Output Compare 1 clear enable + bitOffset: 7 + bitWidth: 1 + OC1M: + description: Output Compare 1 mode + bitOffset: 4 + bitWidth: 3 + OC1PE: + description: Output Compare 1 preload enable + bitOffset: 3 + bitWidth: 1 + OC1FE: + description: Output Compare 1 fast enable + bitOffset: 2 + bitWidth: 1 + CC1S: + description: Capture/Compare 1 selection + bitOffset: 0 + bitWidth: 2 + CCMR2_Output: + description: > + The same register can be used for output compare mode (this section) or for input capture + mode (previous section). The direction of a channel is defined by configuring the + corresponding CCxS bits. All the other bits of this register have a different function for input + capture and for output compare modes. It is possible to combine both modes independently + (e.g. channel 1 in input capture mode and channel 2 in output compare mode). + access: read-write + resetValue: 0x00000000 + addressOffset: 0x1C + fields: + OC4M_3: + description: Output Compare 2 mode[3] + bitOffset: 24 + bitWidth: 1 + OC3M_3: + description: Output Compare 1 mode[3] + bitOffset: 16 + bitWidth: 1 + OC4CE: + description: Output Compare 2 clear enable + bitOffset: 15 + bitWidth: 1 + OC4M: + description: Output Compare 2 mode + bitOffset: 12 + bitWidth: 3 + OC4PE: + description: Output Compare 2 preload enable + bitOffset: 11 + bitWidth: 1 + OC4FE: + description: Output Compare 2 fast enable + bitOffset: 10 + bitWidth: 1 + CC4S: + description: Capture/Compare 2 selection + bitOffset: 8 + bitWidth: 2 + OC3CE: + description: Output Compare 1 clear enable + bitOffset: 7 + bitWidth: 1 + OC3M: + description: TIM[1-58]:Output Compare 1 mode + bitOffset: 4 + bitWidth: 3 + OC3PE: + description: Output Compare 1 preload enable + bitOffset: 3 + bitWidth: 1 + OC3FE: + description: Output Compare 1 fast enable + bitOffset: 2 + bitWidth: 1 + CC3S: + description: Capture/Compare 1 selection + bitOffset: 0 + bitWidth: 2 + +_include: +- ../peripherals/adc/adc_v3_mp1.yaml +- ../peripherals/adc/adc_v3_common_mp1.yaml +- ../peripherals/gpio/gpio_v2.yaml +- ../peripherals/gpio/gpio_with_brr.yaml +- ../peripherals/gpio/gpio_with_seccfgr.yaml +- ../peripherals/ipcc/ipcc_mp1.yaml +- ../peripherals/usart/usart_v2C.yaml +- ../peripherals/usart/usart_wl.yaml +- ../peripherals/tim/tim_gp_mp1.yaml +- ../devices/common_patches/merge_USART_CR1_DEATx_fields.yaml +- ../devices/common_patches/merge_USART_CR1_DEDTx_fields.yaml +- ../devices/common_patches/merge_USART_CR2_ADDx_fields.yaml +- ../devices/common_patches/merge_USART_CR2_ABRMODx_fields.yaml +- ../devices/common_patches/rename_USART_CR1_M0_field.yaml +- ../devices/common_patches/rename_USART_CR3_SCARCNT_field.yaml +- ../devices/common_patches/rename_USART_CR2_DATAINV_field.yaml +- common_patches/merge_USART_BRR_fields.yaml \ No newline at end of file diff --git a/peripherals/adc/adc_v3_common_mp1.yaml b/peripherals/adc/adc_v3_common_mp1.yaml new file mode 100644 index 000000000..6fb4e53e3 --- /dev/null +++ b/peripherals/adc/adc_v3_common_mp1.yaml @@ -0,0 +1,40 @@ +# ADC_Common with MP1 specific fields + +_include: + - "adc_v3_common.yaml" + +"ADC*_*": + CCR: + MDMA: + Disabled: [0, "MDMA mode disabled"] + Bits12_10: [2, "MDMA mode enabled for 12 and 10-bit resolution"] + Bits8_6: [3, "MDMA mode enabled for 8 and 6-bit resolution"] + DMACFG: + OneShot: [0, "DMA one shot mode selected"] + Circulator: [1, "DMA circular mode selected"] + _modify: + CH17SEL: + name: TSEN + description: Temperature sensor voltage enable + CH18SEL: + name: VBATEN + description: VBAT enable + TSEN: + Disabled: [0, "Temperature sensor channel disabled"] + Enabled: [1, "Temperature sensor channel enabled"] + VBATEN: + Disabled: [0, "VBAT channel disabled"] + Enabled: [1, "VBAT channel enabled"] + PRESC: + Div1: [0, "Input ADC clock not divided"] + Div2: [1, "Input ADC clock divided by 2"] + Div4: [2, "Input ADC clock divided by 4"] + Div6: [3, "Input ADC clock divided by 6"] + Div8: [4, "Input ADC clock divided by 8"] + Div10: [5, "Input ADC clock divided by 10"] + Div12: [6, "Input ADC clock divided by 12"] + Div16: [7, "Input ADC clock divided by 16"] + Div32: [8, "Input ADC clock divided by 32"] + Div64: [9, "Input ADC clock divided by 64"] + Div128: [10, "Input ADC clock divided by 128"] + Div256: [11, "Input ADC clock divided by 256"] diff --git a/peripherals/adc/adc_v3_mp1.yaml b/peripherals/adc/adc_v3_mp1.yaml new file mode 100644 index 000000000..94b3548cf --- /dev/null +++ b/peripherals/adc/adc_v3_mp1.yaml @@ -0,0 +1,119 @@ +# ADC v3 with MP1 specific fields + +_include: + - "adc_v3.yaml" + +"ADC,ADC?": + CR: + ADVREGEN: + Disabled: [0, "ADC voltage regulator disabled"] + Enabled: [1, "ADC voltage regulator enabled"] + DEEPPWD: + PowerUp: [0, "ADC not in deep power down"] + PowerDown: [1, "ADC in deep power down"] + "LINCALRDYW?": + Reset: [0, "LINCALFACT Word Read"] + Set: [1, "LINCALFACT Word Write"] + ADCALLIN: + NoLinearity: [0, "ADC calibration without linearaity calibration"] + Linearity: [1, "ADC calibration with linearaity calibration"] + BOOST: + Disabled: [0, "Boost mode off. Used when ADC clock < 20 MHz to save power at lower clock frequency"] + Enabled: [1, "Boost mode on. Must be used when ADC clock > 20 MHz"] + CFGR: + EXTSEL: + TIM4_CC4: [5, "Timer 4 CC4 event"] + TIM8_TRGO: [7, "Timer 8 TRGO event"] + TIM8_TRGO2: [8, "Timer 8 TRGO2 event"] + TIM4_TRGO: [12, "Timer 4 TRGO event"] + HRTIM1_ADCTRG1: [16, "HRTIM1_ADCTRG1 event"] + HRTIM1_ADCTRG3: [17, "HRTIM1_ADCTRG3 event"] + LPTIM1_OUT: [18, "LPTIM1_OUT event"] + LPTIM2_OUT: [19, "LPTIM2_OUT event"] + LPTIM3_OUT: [20, "LPTIM3_OUT event"] + JQDIS: + Enabled: [0, "Injected Queue enabled"] + Disabled: [1, "Injected Queue disabled"] + DMNGT: + DR: [0, "Store output data in DR only"] + DMA_OneShot: [1, "DMA One Shot Mode selected"] + DFSDM: [2, "DFSDM mode selected"] + DMA_Circular: [3, "DMA Circular Mode selected"] + _modify: + RES: + bitWidth: 3 + RES: + SixteenBit: [0, "16-bit resolution"] + FourteenBit: [1, "14-bit resolution in legacy mode (not optimized power consumption)"] + TwelveBit: [2, "12-bit resolution in legacy mode (not optimized power consumption)"] + TenBit: [3, "10-bit resolution"] + FourteenBitV: [5, "14-bit resolution"] + TwelveBitV: [6, "12-bit resolution"] + EightBit: [7, "8-bit resolution"] + CFGR2: + LSHIFT: [0, 15] + OSVR: [0, 1023] + "RSHIFT?": + Disabled: [0, "Right-shifting disabled"] + Enabled: [1, "Data is right-shifted 1-bit"] + ROVSM: + Continued: [0, "Oversampling is temporary stopped and continued after injection sequence"] + Resumed: [1, "Oversampling is aborted and resumed from start after injection sequence"] + TROVS: + Automatic: [0, "All oversampled conversions for a channel are run following a trigger"] + Triggered: [1, "Each oversampled conversion for a channel needs a new trigger"] + OVSS: [0, 11] + JOVSE: + Disabled: [0, "Injected oversampling disabled"] + Enabled: [1, "Injected oversampling enabled"] + ROVSE: + Disabled: [0, "Regular oversampling disabled"] + Enabled: [1, "Regular oversampling enabled"] + "SMPR?": + "SMP*": + Cycles1_5: [0, "1.5 ADC clock cycles"] + Cycles2_5: [1, "2.5 ADC clock cycles"] + Cycles8_5: [2, "8.5 ADC clock cycles"] + Cycles16_5: [3, "16.5 ADC clock cycles"] + Cycles32_5: [4, "32.5 ADC clock cycles"] + Cycles64_5: [5, "64.5 ADC clock cycles"] + Cycles387_5: [6, "387.5 ADC clock cycles"] + Cycles810_5: [7, "810.5 ADC clock cycles"] + "HTR?": + "HTR?": [0, 0x03FF_FFFF] + "LTR?": + "LTR?": [0, 0x03FF_FFFF] + JSQR: + JEXTSEL: + TIM4_TRGO: [5, "Timer 4 TRGO event"] + TIM8_CC4: [7, "Timer 8 CC4 event"] + TIM8_TRGO: [9, "Timer 8 TRGO event"] + TIM8_TRGO2: [10, "Timer 8 TRGO2 event"] + HRTIM1_ADCTRG2: [16, "HRTIM1_ADCTRG2 event"] + HRTIM1_ADCTRG4: [17, "HRTIM1_ADCTRG4 event"] + LPTIM1_OUT: [18, "LPTIM1_OUT event"] + LPTIM2_OUT: [19, "LPTIM2_OUT event"] + LPTIM3_OUT: [20, "LPTIM3_OUT event"] + "OFR?": + SSATE: + Disabled: [0, "Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)"] + Enabled: [1, "Offset is subtracted and result is saturated to maintain result size"] + "OFFSET?_CH": [0, 31] + "OFFSET?": [0, 0x3FFFFFF] + PCSEL: + "PCSEL*": + NotPreselected: [0, "Input channel x is not pre-selected"] + Preselected: [1, "Pre-select input channel x"] + CALFACT: + CALFACT_?: [0, 2047] + CALFACT2: + LINCALFACT: [0, 0x3FFFFFFF] + +ADC2: + _modify: + ADC2_OR: + name: "OR" + OR: + VDDCOREEN: + Disabled: [0, "VDDCORE channel disabled"] + Enabled: [1, "VDDCORE channel enabled"] \ No newline at end of file diff --git a/peripherals/gpio/gpio_with_seccfgr.yaml b/peripherals/gpio/gpio_with_seccfgr.yaml new file mode 100644 index 000000000..7596ef826 --- /dev/null +++ b/peripherals/gpio/gpio_with_seccfgr.yaml @@ -0,0 +1,8 @@ +# GPIOZ appear to have SECCFGR registers + +"GPIOZ": + SECCFGR: + "SEC[01234567]": + _write: + NonSecure: [0, "The I/O pin is non-secure"] + Secure: [1, "The I/O pin is secure"] diff --git a/peripherals/ipcc/ipcc_mp1.yaml b/peripherals/ipcc/ipcc_mp1.yaml new file mode 100644 index 000000000..94ff32259 --- /dev/null +++ b/peripherals/ipcc/ipcc_mp1.yaml @@ -0,0 +1,113 @@ +IPCC: + C1CR: + RXOIE: + Disabled: [0, "Processor 1 RX occupied interrupt disabled"] + Enabled: [1, " Enable an unmasked processor 1 receive channel occupied to generate an RX occupied interrupt"] + TXFIE: + Disabled: [0, "Processor 1 TX free interrupt disabled"] + Enabled: [1, " Enable an unmasked processor 1 transmit channel free to generate a TX free interrupt"] + C2CR: + TXFIE: + Disabled: [0, "Processor 2 TX free interrupt disabled"] + Enabled: [1, "Enable an unmasked processor 2 transmit channel free to generate a TX free interrupt"] + RXOIE: + Disabled: [0, "Processor 2 RX occupied interrupt disabled"] + Enabled: [1, ": Enable an unmasked processor 2 receive channel occupied to generate an RX occupied interrupt"] + + C1MR: + _split: + CHxFM: + name: CH%sFM + description: Processor 1 transmit channel %s free interrupt mask + CHxOM: + name: CH%sOM + description: Processor 1 receive channel %s occupied interrupt mask + CH?FM: + Unmasked: [0, "Transmit channel n free interrupt unmasked"] + Masked: [1, "Transmit channel n free interrupt masked"] + CH?OM: + Unmasked: [0, "Receive channel n occupied interrupt unmasked"] + Masked: [1, "Receive channel n occupied interrupt masked"] + C2MR: + _split: + CHxFM: + name: CH%sFM + description: Processor 2 transmit channel %s free interrupt mask + CHxOM: + name: CH%sOM + description: Processor 2 receive channel %s occupied interrupt mask + CH?FM: + Unmasked: [0, "Transmit channel n free interrupt unmasked"] + Masked: [1, "Transmit channel n free interrupt masked"] + CH?OM: + Unmasked: [0, "Receive channel n occupied interrupt unmasked"] + Masked: [1, "Receive channel n occupied interrupt masked"] + + C1SCR: + _split: + CHxS: + name: CH%sS + description: Processor 1 transmit channel %s status set + CHxC: + name: CH%sC + description: Processor 1 receive channel %s status clear + CH?S: + NoAction: [0, "No action"] + SetStatusBit: [1, "Processor 1 transmit channel n status bit set"] + CH?C: + NoAction: [0, "No action"] + SetStatusBit: [1, "Processor 1 receive channel n status bit clear"] + C2SCR: + _split: + CHxS: + name: CH%sS + description: Processor 2 transmit channel %s status set + CHxC: + name: CH%sC + description: Processor 2 receive channel %s status clear + CH?S: + NoAction: [0, "No action"] + SetStatusBit: [1, "Processor 2 transmit channel n status bit set"] + CH?C: + NoAction: [0, "No action"] + SetStatusBit: [1, "Processor 2 receive channel n status bit clear"] + + C1TOC2SR: + _split: + CHxF: + name: CH%sF + description: Processor 1 transmit to processor 2 receive channel %i status flag before masking + CH?F: + Free: [0, "Channel free, data can be written by the sending processor 1"] + Occupied: [1, "Channel occupied, data can be read by the receiving processor 2"] + C2TOC1SR: + _split: + CHxF: + name: CH%sF + description: Processor 2 transmit to processor 1 receive channel %i status flag before masking + CH?F: + Free: [0, "Channel free, data can be written by the sending processor 2"] + Occupied: [1, "Channel occupied, data can be read by the receiving processor 1"] + HWCFGR: + _add: + SECCTRL: + description: Security options + bitOffset: 8 + bitWidth: 4 + access: read-only + OPTBITS: + description: Reserved for future use + bitOffset: 16 + bitWidth: 8 + access: read-only + CIDWIDTH: + description: CID bit field width range 0 to 12 + bitOffset: 24 + bitWidth: 4 + access: read-only + SECCTRL: + NoSecurity: [0, "No security"] + Security: [1, "Security"] + SecurityAndPrivilege: [2, "Security and privilege"] + SecurityPrivilegeResourceIsolation: [3, "Security, privilege and resource isolation."] + CIDWIDTH: [0, 12] \ No newline at end of file diff --git a/peripherals/tim/tim_gp_mp1.yaml b/peripherals/tim/tim_gp_mp1.yaml new file mode 100644 index 000000000..c6ebb940b --- /dev/null +++ b/peripherals/tim/tim_gp_mp1.yaml @@ -0,0 +1,534 @@ +TIM[1-58]: + CR1: + CMS: + EdgeAligned: [0, "The counter counts up or down depending on the direction bit"] + CenterAligned1: [1, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down."] + CenterAligned2: [2, "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up."] + CenterAligned3: [3, "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down."] + DIR: + Up: [0, "Counter used as upcounter"] + Down: [1, "Counter used as downcounter"] + SMCR: + ETP: + NotInverted: [0, "ETR is noninverted, active at high level or rising edge"] + Inverted: [1, "ETR is inverted, active at low level or falling edge"] + ECE: + Disabled: [0, "TIM[1-58]:[1-58]:ternal clock mode 2 disabled"] + Enabled: [1, "External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal."] + ETPS: + Div1: [0, "Prescaler OFF"] + Div2: [1, "ETRP frequency divided by 2"] + Div4: [2, "ETRP frequency divided by 4"] + Div8: [3, "ETRP frequency divided by 8"] + ETF: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + CCMR2_Input: + CC?S: + TI3: [1, "Channel is configured as input, ICx is mapped on TI3"] + TI4: [2, "Channel is configured as input, ICx is mapped on TI4"] + TRC: [3, "Channel is configured as input, ICx is mapped on TRC"] + +TIM[18]: + CR2: + MMS2: + "Reset": [0b0000, "Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2). If the reset is generated by the trigger input (slave mode controller configured in reset mode), the signal on TRGO2 is delayed compared to the actual reset"] + Enable: [0b0001, "Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO2). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic AND between the CEN control bit and the trigger input when configured in Gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO2, except if the Master/Slave mode is selected (see the MSM bit description in TIMx_SMCR register)"] + Update: [0b0010, "Update - the update event is selected as trigger output (TRGO2). For instance, a master timer can then be used as a prescaler for a slave timer"] + ComparePulse: [0b0011, "Compare pulse - the trigger output sends a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or compare match occurs (TRGO2)"] + CompareOC1: [0b0100, "Compare - OC1REFC signal is used as trigger output (TRGO2)"] + CompareOC2: [0b0101, "Compare - OC2REFC signal is used as trigger output (TRGO2)"] + CompareOC3: [0b0110, "CompareCCMR[12]_Output:CCMR[12]_Output: - OC3REFC signal is used as trigger output (TRGO2)"] + CompareOC4: [0b0111, "Compare - OC4REFC signal is used as trigger output (TRGO2)"] + CompareOC5: [0b1000, "Compare - OC5REFC signal is used as trigger output (TRGO2)"] + CompareOC6: [0b1001, "Compare - OC6REFC signal is used as trigger output (TRGO2)"] + PulseOC4: [0b1010, "Compare Pulse - OC4REFC rising or falling edges generate pulses on TRGO2"] + PulseOC6: [0b1011, "Compare Pulse - OC6REFC rising or falling edges generate pulses on TRGO2"] + RisingOC4_6: [0b1100, "Compare Pulse - OC4REFC or OC6REFC rising edges generate pulses on TRGO2"] + RisingOC4_FallingOC6: [0b1101, "Compare Pulse - OC4REFC rising or OC6REFC falling edges generate pulses on TRGO2"] + RisingOC5_6: [0b1110, "Compare Pulse - OC5REFC or OC6REFC rising edges generate pulses on TRGO2"] + RisingOC5_FallingOC6: [0b1111, "Compare Pulse - OC5REFC rising or OC6REFC falling edges generate pulses on TRGO2"] + SR: + B2IF: + _read: + NoTrigger: [0, "No break event occurred"] + Trigger: [1, "An active level has been detected on the break 2 input. An interrupt is generated if BIE=1 in the TIMx_DIER register"] + _write: + Clear: [0, "Clear flag"] + SBIF: + _read: + NoTrigger: [0, "No break event occurred"] + Trigger: [1, "An active level has been detected on the system break input. An interrupt is generated if BIE=1 in the TIMx_DIER register"] + _write: + Clear: [0, "Clear flag"] + EGR: + B2G: + _write: + Trigger: [1, "A break 2 event is generated. MOE bit is cleared and B2IF flag is set. Related interrupt can occur if enabled"] + BDTR: + BK2BID: + Input: [0, "Break input BRK2 in input mode"] + Bidirectional: [1, "Break input BRK2 in bidirectional mode"] + BK2DSRM: + Armed: [0, "Break input BRK2 is armed"] + Disarmed: [1, "Break input BRK2 is disarmed"] + BK2P: + Low: [0, "Break input BRK2 is active low"] + High: [1, "Break input BRK2 is active high"] + BK2E: + Disabled: [0, "Break function disabled"] + Enabled: [1, "Break function enabled"] + BK2F: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + CCR5: + GC5C3: + Disabled: [0, "No effect of OC5REF on OC3REFC"] + Enabled: [1, "OC3REFC is the logical AND of OC3REFC and OC5REF"] + GC5C2: + Disabled: [0, "No effect of OC5REF on OC2REFC"] + Enabled: [1, "OC2REFC is the logical AND of OC2REFC and OC5REF"] + GC5C1: + Disabled: [0, "No effect of OC5REF on OC1REFC"] + Enabled: [1, "OC1REFC is the logical AND of OC1REFC and OC5REF"] + AF1: + ETRSEL: + IO: [0b0000, "ETR input is connected to I/O"] + ADC1_AWD1: [0b0011, "ADC1 AWD1"] + ADC1_AWD2: [0b0100, "ADC1 AWD2"] + ADC1_AWD3: [0b0101, "ADC1 AWD3"] + ADC2_AWD1: [0b0110, "ADC2 AWD1"] + ADC2_AWD2: [0b0111, "ADC2 AWD2"] + ADC2_AWD3: [0b1000, "ADC2 AWD3"] + AF2: + BK2INP: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BK2INE: + Disabled: [0, "BKIN input disabled"] + Enabled: [1, "BKIN input enabled"] + +TIM1,TIM15: + AF1: + BKDF1BK0E: + Disabled: [0, "dfsdm1_break[0] input disabled"] + Enabled: [1, "dfsdm1_break[0] input enabled"] +TIM1: + AF2: + BK2DF1BK1E: + Disabled: [0, "dfsdm1_break[1] input disabled"] + Enabled: [1, "dfsdm1_break[1] input enabled"] +TIM2: + AF1: + ETRSEL: + IO: [0b0000, "ETR input is connected to I/O"] + LSE: [0b0011, "LSE"] + SAI1_FS_A: [0b0100, "SAI1 FS_A"] + SAI1_FS_B: [0b0101, "SAI1 FS_B"] + Eth_PTP_PPS_Out: [0b0110, "eth_ptp_pps_out"] +TIM3: + AF1: + ETRSEL: + IO: [0b0000, "ETR input is connected to I/O"] + Eth_PTP_PPS_Out: [0b0110, "eth_ptp_pps_out"] +TIM4: + AF1: + ETRSEL: + IO: [0b0000, "ETR input is connected to I/O"] + SAI1_FS_A: [0b0001, "SAI2 FS_A"] + SAI1_FS_B: [0b0010, "SAI2 FS_B"] + Eth_PTP_PPS_Out: [0b0011, "OTG_SOF"] +TIM5: + AF1: + ETRSEL: + IO: [0b0000, "ETR input is connected to I/O"] + SAI1_FS_A: [0b0001, "SAI2 FS_A"] + SAI1_FS_B: [0b0010, "SAI2 FS_B"] + Eth_PTP_PPS_Out: [0b0011, "OTG_SOF"] +TIM8,TIM16: + AF1: + BKDF1BK2E: + Disabled: [0, "dfsdm1_break[2] input disabled"] + Enabled: [1, "dfsdm1_break[2] input enabled"] + +TIM[18],TIM1[5-7]: + CR2: + OIS?N: + Disabled: [0, "OCxN=0 after a dead-time when MOE=0"] + Enabled: [1, "OCxN=1 after a dead-time when MOE=0"] + OIS?: + Disabled: [0, "OCx=0 (after a dead-time if OCx(N) is implemented) when MOE=0"] + Enabled: [1, "OCx=1 (after a dead-time if OCx(N) is implemented) when MOE=0"] + CCUS: + Bit: [0, "When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only"] + BitOrEdge: [1, "When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI"] + CCPC: + NotPreloaded: [0, "CCxE, CCxNE and OCxM bits are not preloaded"] + Preloaded: [1, "CCxE, CCxNE and OCxM bits are preloaded"] + DIER: + COMDE: + Disabled: [0, "COM DMA request disabled"] + Enabled: [1, "COM DMA request enabled"] + BIE: + Disabled: [0, "Break interrupt disabled"] + Enabled: [1, "Break interrupt enabled"] + COMIE: + Disabled: [0, "COM interrupt disabled"] + Enabled: [1, "COM interrupt enabled"] + SR: + BIF: + _read: + NoTrigger: [0, "No break event occurred"] + Trigger: [1, "An active level has been detected on the break input. An interrupt is generated if BIE=1 in the TIMx_DIER register"] + _write: + Clear: [0, "Clear flag"] + COMIF: + _read: + NoCOM: [0, "No COM event occurred"] + COM: [1, "COM interrupt pending"] + _write: + Clear: [0, "Clear flag"] + CCER: + "CC?NE": + Disabled: [0, "Complementary output disabled"] + Enabled: [1, "Complementary output enabled"] + RCR: + REP: [0, 65535] + BDTR: + BKBID: + Input: [0, "Break input BRK in input mode"] + Bidirectional: [1, "Break input BRK in bidirectional mode"] + BKDSRM: + Armed: [0, "Break input BRK is armed"] + Disarmed: [1, "Break input BRK is disarmed"] + BKF: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + MOE: + Disabled: [0, "In response to a break 2 event OC and OCN outputs are disabled - In response to a break event or if MOE is written to 0 OC and OCN outputs are disabled or forced to idle state depending on the OSSI bit"] + Enabled: [1, "OC and OCN outputs are enabled if their respective enable bits are set (CCxE, CCxNE in TIMx_CCER register)"] + AOE: + Disabled: [0, "MOE can be set only by software"] + Enabled: [1, "MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active)"] + BKP: + ActiveLow: [0, "Break input BRK is active low"] + ActiveHigh: [1, "Break input BRK is active high"] + BKE: + Disabled: [0, "Break function disabled"] + Enabled: [1, "Break function enabled"] + OSSR: + Disabled: [0, "OC/OCN outputs are disabled when inactive"] + Enabled: [1, "OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1"] + OSSI: + Disabled: [0, "OC/OCN outputs are disabled when inactive"] + Enabled: [1, "OC/OCN outputs are first forced with their inactive level then forced to their idle level after the deadtime"] + LOCK: + "Off": [0, "No write protection"] + Level1: [1, "Level 1 write protection"] + Level2: [2, "Level 2 write protection"] + Level3: [3, "Level 3 write protection"] + DTG: [0, 0xFF] + AF1: + BKINP: + NotInverted: [0, 'Input polarity not inverted'] + Inverted: [1, 'Input polarity inverted'] + BKINE: + Disabled: [0, "BKIN input disabled"] + Enabled: [1, "BKIN input enabled"] +TIM8: + AF2: + BK2DF1BK3E: + Disabled: [0, "dfsdm1_break[3] input disabled"] + Enabled: [1, "dfsdm1_break[3] input enabled"] + +TIM*: + CR1: + OPM: + NotStopped: [0, "Not stopped at update event"] + Stopped: [1, "Counter stops counting at next update event"] + UIFREMAP: + Disabled: [0, "No remapping. UIF status bit is not copied to TIMx_CNT register bit 31"] + Enabled: [1, "Remapping enabled. UIF status bit is copied to TIMx_CNT register bit 31"] + ARPE: + Disabled: [0, "TIMx_APRR register is not buffered"] + Enabled: [1, "TIMx_APRR register is buffered"] + URS: + AnyEvent: [0, "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request"] + CounterOnly: [1, "Only counter overflow/underflow generates an update interrupt or DMA request"] + UDIS: + Enabled: [0, "Update event enabled"] + Disabled: [1, "Update event disabled"] + CEN: + Disabled: [0, "Counter disabled"] + Enabled: [1, "Counter enabled"] + DIER: + UIE: + Disabled: [0, "Update interrupt disabled"] + Enabled: [1, "Update interrupt enabled"] + SR: + UIF: + Clear: [0, "No update occurred"] + UpdatePending: [1, "Update interrupt pending."] + EGR: + UG: + Update: [1, "Re-initializes the timer counter and generates an update of the registers."] + PSC: + PSC: [0, 65535] + +TIM[1-58],TIM1[2-5]: + EGR: + "CC?G": + _write: + Trigger: [1, "If CCx is an output: CCxIF flag is set, Corresponding interrupt or DMA request is sent if enabled. If CCx is an input: The current value of the counter is captured in TIMx_CCR1 register."] + CCMR?_Input: + IC?F: + NoFilter: [0, "No filter, sampling is done at fDTS"] + FCK_INT_N2: [1, "fSAMPLING=fCK_INT, N=2"] + FCK_INT_N4: [2, "fSAMPLING=fCK_INT, N=4"] + FCK_INT_N8: [3, "fSAMPLING=fCK_INT, N=8"] + FDTS_Div2_N6: [4, "fSAMPLING=fDTS/2, N=6"] + FDTS_Div2_N8: [5, "fSAMPLING=fDTS/2, N=8"] + FDTS_Div4_N6: [6, "fSAMPLING=fDTS/4, N=6"] + FDTS_Div4_N8: [7, "fSAMPLING=fDTS/4, N=8"] + FDTS_Div8_N6: [8, "fSAMPLING=fDTS/8, N=6"] + FDTS_Div8_N8: [9, "fSAMPLING=fDTS/8, N=8"] + FDTS_Div16_N5: [10, "fSAMPLING=fDTS/16, N=5"] + FDTS_Div16_N6: [11, "fSAMPLING=fDTS/16, N=6"] + FDTS_Div16_N8: [12, "fSAMPLING=fDTS/16, N=8"] + FDTS_Div32_N5: [13, "fSAMPLING=fDTS/32, N=5"] + FDTS_Div32_N6: [14, "fSAMPLING=fDTS/32, N=6"] + FDTS_Div32_N8: [15, "fSAMPLING=fDTS/32, N=8"] + IC?PSC: + NoPrescaler: [0b00, "No prescaler, capture is done each time an edge is detected on the capture input"] + Every2Events: [0b01, "Capture is done once every 2 events"] + Every4Events: [0b10, "Capture is done once every 4 events"] + Every8Events: [0b11, "Capture is done once every 8 events"] + CCMR1_Input: + CC?S: + TI1: [1, "Channel is configured as input, ICx is mapped on TI1"] + TI2: [2, "Channel is configured as input, ICx is mapped on TI2"] + TRC: [3, "Channel is configured as input, ICx is mapped on TRC"] + CCMR?_Output: + OC?PE: + Disabled: [0, "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"] + Enabled: [1, "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"] + OC?FE: + Disabled: [0, "Fast output disabled"] + Enabled: [1, "Fast output enabled"] + OC?M: + Frozen: [0, "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs / OpmMode1: Retriggerable OPM mode 1 - In up-counting mode, the channel is active until a trigger event is detected (on TRGI signal). In down-counting mode, the channel is inactive"] + ActiveOnMatch: [1, "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register / OpmMode2: Inversely to OpmMode1"] + InactiveOnMatch: [2, "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register / Reserved"] + Toggle: [3, "OCyREF toggles when TIMx_CNT=TIMx_CCRy / Reserved"] + ForceInactive: [4, "OCyREF is forced low / CombinedPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC is the logical OR between OC1REF and OC2REF"] + ForceActive: [5, "OCyREF is forced high / CombinedPwmMode2: OCyREF has the same behavior as in PWM mode 2. OCyREFC is the logical AND between OC1REF and OC2REF"] + PwmMode1: [6, "In upcounting, channel is active as long as TIMx_CNTTIMx_CCRy else active / AsymmetricPwmMode1: OCyREF has the same behavior as in PWM mode 1. OCyREFC outputs OC1REF when the counter is counting up, OC2REF when it is counting down"] + PwmMode2: [7, "Inversely to PwmMode1 / AsymmetricPwmMode2: Inversely to AsymmetricPwmMode1"] + OC?M_3: + Normal: [0, "Normal output compare mode (modes 0-7)"] + Extended: [1, "Extended output compare mode (modes 7-15)"] + CCMR[12]_Output: + CC?S: + Output: [0, "Channel is configured as output"] + +TIM[1-58],TIM1[25]: + CR2: + TI1S: + Normal: [0, "The TIMx_CH1 pin is connected to TI1 input"] + XOR: [1, "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input"] + SMCR: + MSM: + NoSync: [0, "No action"] + Sync: [1, "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event."] + TS: + ITR0: [0, "Internal Trigger 0 (ITR0)"] + ITR1: [1, "Internal Trigger 1 (ITR1)"] + ITR2: [2, "Internal Trigger 2 (ITR2)"] + TI1F_ED: [4, "TI1 Edge Detector (TI1F_ED)"] + TI1FP1: [5, "Filtered Timer Input 1 (TI1FP1)"] + TI2FP2: [6, "Filtered Timer Input 2 (TI2FP2)"] + ETRF: [7, "External Trigger input (ETRF)"] + SMS: + Disabled: [0, "Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock."] + Encoder_Mode_1: [1, "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level."] + Encoder_Mode_2: [2, "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level."] + Encoder_Mode_3: [3, "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input."] + Reset_Mode: [4, "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers."] + Gated_Mode: [5, "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled."] + Trigger_Mode: [6, "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled."] + Ext_Clock_Mode: [7, "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter."] + SMS_3: + Disabled: [0, "Slave mode disabled (see SMS[0:2])"] + CombinedResetTrigger: [1, "SMS[0:2] must be 0b000 (DisabledOrCombined). Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter"] + TS_4_3: [0, 3] + DIER: + TIE: + Disabled: [0, "Trigger interrupt disabled"] + Enabled: [1, "Trigger interrupt enabled"] + SR: + TIF: + _read: + NoTrigger: [0, "No trigger event occurred"] + Trigger: [1, "Trigger interrupt pending"] + _write: + Clear: [0, "Clear flag"] + EGR: + TG: + _write: + Trigger: [1, "The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled."] + +TIM[1-8],TIM1[25]: + CR2: + MMS: + Reset: [0, "The UG bit from the TIMx_EGR register is used as trigger output"] + Enable: [1, "The counter enable signal, CNT_EN, is used as trigger output"] + Update: [2, "The update event is selected as trigger output"] + ComparePulse: [3, "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred"] + CompareOC1: [4, "OC1REF signal is used as trigger output"] + CompareOC2: [5, "OC2REF signal is used as trigger output"] + CompareOC3: [6, "OC3REF signal is used as trigger output"] + CompareOC4: [7, "OC4REF signal is used as trigger output"] + +TIM[1346-8],TIM1[2-7]: + CNT: + _modify: + UIFCPY: + description: > + Update interrupt flag Copy + This bit is a read-only copy of the UIF bit of the TIMx_ISR register + UIFCPY: + _read: + NoUpdateOccured: [0, "No update occurred"] + UpdateOccured: [1, "Update interrupt pending"] + CNT: [0, 65535] + ARR: + ARR: [0, 65535] + +TIM[1348],TIM1[2-7]: + CCR?: + CCR?: [0, 65535] + +TIM[25]: + CNT: + CNT: [0, 4294967295] + ARR: + ARR: [0, 4294967295] + CCR?: + CCR?: [0, 4294967295] + +TIM[1-58],TIM1[5-7]: + CR2: + CCDS: + OnCompare: [0, "CCx DMA request sent when CCx event occurs"] + OnUpdate: [1, "CCx DMA request sent when update event occurs"] + DIER: + "CC?DE": + Disabled: [0, "CCx DMA request disabled"] + Enabled: [1, "CCx DMA request enabled"] + DCR: + DBL: [0, 18] + DBA: [0, 31] + DMAR: + DMAB: [0, 0xFFFF] + +TIM[1-8],TIM1[5-7]: + DIER: + UDE: + Disabled: [0, "Update DMA request disabled"] + Enabled: [1, "Update DMA request enabled"] + +TIM[1-58],TIM1[2-7]: + CR1: + CKD: + Div1: [0, "t_DTS = t_CK_INT"] + Div2: [1, "t_DTS = 2 × t_CK_INT"] + Div4: [2, "t_DTS = 4 × t_CK_INT"] + TISEL: + TI?SEL: + Selected: [0, "CHx input selected"] + DIER: + "CC?IE": + Disabled: [0, "CCx interrupt disabled"] + Enabled: [1, "CCx interrupt enabled"] + SR: + "CC?OF": + _read: + Overcapture: [1, "The counter value has been captured in TIMx_CCRx register while CCxIF flag was already set"] + _write: + Clear: [0, "Clear flag"] + "CC?IF": + _read: + Match: [1, "If CC1 is an output: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. If CC1 is an input: The counter value has been captured in TIMx_CCR1 register."] + _write: + Clear: [0, "Clear flag"] + CCER: + "CC?NP": + ActiveHigh: [0, "OCxN active high"] + ActiveLow: [1, "OCxN active low"] + "CC?P": + RisingEdge: [0, "Noninverted/rising edge"] + FallingEdge: [1, "Inverted/falling edge"] + "CC?E": + Disabled: [0, "Capture disabled"] + Enabled: [1, "Capture enabled"] + +TIM[18],TIM15: + EGR: + BG: + _write: + Trigger: [1, "A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or DMA transfer can occur if enabled"] + COMG: + _write: + Trigger: [1, "When CCPC bit is set, it allows CCxE, CCxNE and OCxM bits to be updated"] + +TIM[1-58],TIM15: + DIER: + TDE: + Disabled: [0, "Trigger DMA request disabled"] + Enabled: [1, "Trigger DMA request enabled"] + CCMR?_Output: + OC?CE: + Disabled: [0, "OCxRef is not affected by the ocref_clr_int signal"] + Enabled: [1, "OCxRef is cleared as soon as a High level is detected on ocref_clr_int signal"] \ No newline at end of file From 1e6f9fadc8d14d927631bb89efa810444a089643 Mon Sep 17 00:00:00 2001 From: Maxime Date: Sun, 15 Aug 2021 22:39:44 +0200 Subject: [PATCH 2/5] Strip all peripherals prefixes --- devices/stm32mp157.yaml | 151 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 2 deletions(-) diff --git a/devices/stm32mp157.yaml b/devices/stm32mp157.yaml index 06947f496..40b91622b 100644 --- a/devices/stm32mp157.yaml +++ b/devices/stm32mp157.yaml @@ -25,18 +25,153 @@ _modify: name: ADC_Common # Stripping prefixes +ADC*: + _strip: + - "ADC_" +AXIMC_Mx: + _strip: + - "AXIMC_" +BSEC: + _strip: + - "BSEC_" +CCU: + _strip: + - "FCCAN_CCU_" +CRC?: + _strip: + - "CRC_" +CRYP?: + _strip: + - "CRYP_" +DAC?: + _strip: + - "DAC_" +DCMI: + _strip: + - "DCMI_" +DDRCTRL: + _strip: + - "DDRCTRL_" +DDRPERFM: + _strip: + - "DDRPERFM_" +DDRPHYC: + _strip: + - "DDRPHYC_" +DFSDM?: + _strip: + - "DFSDM_" +DLYB*: + _strip: + - "DLYB_" +DMA?: + _strip: + - "DMA_" +DMAMUX?: + _strip: + - "DMAMUX_" DSI: _strip: - "DSI_" +DTS: + _strip: + - "DTS_" +ETH*: + _strip: + - "ETH_" +ETZPC: + _strip: + - "ETZPC_" +EXTI: + _strip: + - "EXTI_" +FDCAN?: + _strip: + - "FDCAN_" +FMC: + _strip: + - "FMC_" +GIC?: + _strip: + - "GIC?_" GPIO?: _strip: - "GPIO?_" -ADC*: +HASH?: _strip: - - "ADC_" + - "HASH_" +HDMI_CEC: + _strip: + - "CEC_" +HDP: + _strip: + - "HDP_" +HSEM: + _strip: + - "HSEM_" +I2C?: + _strip: + - "I2C_" IPCC: _strip: - "IPCC_" +IWDG?: + _strip: + - "IWDG_" +LPTIM?: + _strip: + - "LPTIM_" +LTDC: + _strip: + - "LTDC_" +MDIOS: + _strip: + - "MDIOS_" +MDMA: + _strip: + - "MDMA_" +OTG: + _strip: + - "OTG_" +PWR: + _strip: + - "PWR_" +QUADSPI: + _strip: + - "QUADSPI_" +RCC: + _strip: + - "RCC_" +RNG?: + _strip: + - "RNG_" +RTC: + _strip: + - "RTC_" +SAI?: + _strip: + - "SAI_" +SDMMC?: + _strip: + - "SDMMC_" +SPDIFRX: + _strip: + - "SPDIFRX_" +SPI?: + _strip: + - "SPI_" +STGENC: + _strip: + - "STGENC_" +STGEN?: + _strip: + - "STGEN?_" +SYSCFG: + _strip: + - "SYSCFG_" +TAMP: + _strip: + - "TAMP_" TIM?: _strip: - TIM?_ @@ -44,6 +179,18 @@ TIM1?: _strip: - TIM1?_ - TIM?_ +TZC: + _strip: + - "TZC_" +USBPHYC: + _strip: + - "USBPHYC_" +VREFBUF: + _strip: + - "VREFBUF_" +WWDG?: + _strip: + - "WWDG_" # Cleaning up the timers TIM*: From 61da9d7dcb99710ece5e004767e7fccb5b67ecd8 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Tue, 9 Nov 2021 19:19:24 +0100 Subject: [PATCH 3/5] Updating STM32H7 ETH_MAC MMC mask register writable --- devices/common_patches/h7_ethernet_mac.yaml | 10 ++++++++++ devices/stm32h735.yaml | 1 + devices/stm32h743.yaml | 1 + devices/stm32h743v.yaml | 1 + devices/stm32h747cm4.yaml | 1 + devices/stm32h747cm7.yaml | 1 + devices/stm32h753.yaml | 1 + devices/stm32h753v.yaml | 1 + devices/stm32h7b3.yaml | 1 + 9 files changed, 18 insertions(+) create mode 100644 devices/common_patches/h7_ethernet_mac.yaml diff --git a/devices/common_patches/h7_ethernet_mac.yaml b/devices/common_patches/h7_ethernet_mac.yaml new file mode 100644 index 000000000..28ef263ea --- /dev/null +++ b/devices/common_patches/h7_ethernet_mac.yaml @@ -0,0 +1,10 @@ +Ethernet_MAC: + MMC_TX_INTERRUPT_MASK: + _modify: + TXLPITRCIM: + access: read-write + + MMC_RX_INTERRUPT_MASK: + _modify: + RXLPITRCIM: + access: read-write diff --git a/devices/stm32h735.yaml b/devices/stm32h735.yaml index a3a875224..8ae0cb388 100644 --- a/devices/stm32h735.yaml +++ b/devices/stm32h735.yaml @@ -568,3 +568,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml + - common_patches/h7_ethernet_mac.yaml diff --git a/devices/stm32h743.yaml b/devices/stm32h743.yaml index 50fbb81ca..238be961b 100644 --- a/devices/stm32h743.yaml +++ b/devices/stm32h743.yaml @@ -78,3 +78,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml + - common_patches/h7_ethernet_mac.yaml diff --git a/devices/stm32h743v.yaml b/devices/stm32h743v.yaml index 3f3117c6f..b90189438 100644 --- a/devices/stm32h743v.yaml +++ b/devices/stm32h743v.yaml @@ -80,3 +80,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml + - common_patches/h7_ethernet_mac.yaml diff --git a/devices/stm32h747cm4.yaml b/devices/stm32h747cm4.yaml index 57558e9c9..4f6d86dd9 100644 --- a/devices/stm32h747cm4.yaml +++ b/devices/stm32h747cm4.yaml @@ -90,3 +90,4 @@ _include: - ../peripherals/sai/sai.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml + - common_patches/h7_ethernet_mac.yaml diff --git a/devices/stm32h747cm7.yaml b/devices/stm32h747cm7.yaml index 0b0ddba30..b36229dc1 100644 --- a/devices/stm32h747cm7.yaml +++ b/devices/stm32h747cm7.yaml @@ -95,3 +95,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml + - common_patches/h7_ethernet_mac.yaml diff --git a/devices/stm32h753.yaml b/devices/stm32h753.yaml index b40f7124e..d0ac044e3 100644 --- a/devices/stm32h753.yaml +++ b/devices/stm32h753.yaml @@ -87,3 +87,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml + - common_patches/h7_ethernet_mac.yaml diff --git a/devices/stm32h753v.yaml b/devices/stm32h753v.yaml index 6609ce813..00036890d 100644 --- a/devices/stm32h753v.yaml +++ b/devices/stm32h753v.yaml @@ -90,3 +90,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml + - common_patches/h7_ethernet_mac.yaml diff --git a/devices/stm32h7b3.yaml b/devices/stm32h7b3.yaml index ca541faaa..5a6aa9250 100644 --- a/devices/stm32h7b3.yaml +++ b/devices/stm32h7b3.yaml @@ -146,3 +146,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml + - common_patches/h7_ethernet_mac.yaml From 49e48352981c09c1fa4d64ec3cb11c941182f6f0 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 10 Nov 2021 09:28:18 +0100 Subject: [PATCH 4/5] Removing ethernet patches from B3 variant --- devices/stm32h7b3.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/devices/stm32h7b3.yaml b/devices/stm32h7b3.yaml index 5a6aa9250..ca541faaa 100644 --- a/devices/stm32h7b3.yaml +++ b/devices/stm32h7b3.yaml @@ -146,4 +146,3 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml - - common_patches/h7_ethernet_mac.yaml From f76fd3906a87d8e9e16403c1d7470e1d0439a375 Mon Sep 17 00:00:00 2001 From: Richard Meadows <962920+richardeoin@users.noreply.github.com> Date: Wed, 10 Nov 2021 22:56:36 +0100 Subject: [PATCH 5/5] ETH_MAC MMC register patch #658 also applies to MP1 --- ...{h7_ethernet_mac.yaml => h7_mp1_ethernet_mac.yaml} | 2 +- devices/stm32h735.yaml | 2 +- devices/stm32h743.yaml | 2 +- devices/stm32h743v.yaml | 2 +- devices/stm32h747cm4.yaml | 2 +- devices/stm32h747cm7.yaml | 2 +- devices/stm32h753.yaml | 2 +- devices/stm32h753v.yaml | 2 +- devices/stm32mp157.yaml | 11 ++++++----- 9 files changed, 14 insertions(+), 13 deletions(-) rename devices/common_patches/{h7_ethernet_mac.yaml => h7_mp1_ethernet_mac.yaml} (86%) diff --git a/devices/common_patches/h7_ethernet_mac.yaml b/devices/common_patches/h7_mp1_ethernet_mac.yaml similarity index 86% rename from devices/common_patches/h7_ethernet_mac.yaml rename to devices/common_patches/h7_mp1_ethernet_mac.yaml index 28ef263ea..83fa1a448 100644 --- a/devices/common_patches/h7_ethernet_mac.yaml +++ b/devices/common_patches/h7_mp1_ethernet_mac.yaml @@ -1,4 +1,4 @@ -Ethernet_MAC: +Ethernet_MAC,ETH_MAC_MMC: MMC_TX_INTERRUPT_MASK: _modify: TXLPITRCIM: diff --git a/devices/stm32h735.yaml b/devices/stm32h735.yaml index 8ae0cb388..f71567a02 100644 --- a/devices/stm32h735.yaml +++ b/devices/stm32h735.yaml @@ -568,4 +568,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml - - common_patches/h7_ethernet_mac.yaml + - common_patches/h7_mp1_ethernet_mac.yaml diff --git a/devices/stm32h743.yaml b/devices/stm32h743.yaml index 238be961b..055bbab57 100644 --- a/devices/stm32h743.yaml +++ b/devices/stm32h743.yaml @@ -78,4 +78,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml - - common_patches/h7_ethernet_mac.yaml + - common_patches/h7_mp1_ethernet_mac.yaml diff --git a/devices/stm32h743v.yaml b/devices/stm32h743v.yaml index b90189438..0c4a579b1 100644 --- a/devices/stm32h743v.yaml +++ b/devices/stm32h743v.yaml @@ -80,4 +80,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml - - common_patches/h7_ethernet_mac.yaml + - common_patches/h7_mp1_ethernet_mac.yaml diff --git a/devices/stm32h747cm4.yaml b/devices/stm32h747cm4.yaml index 4f6d86dd9..70a1a5c1e 100644 --- a/devices/stm32h747cm4.yaml +++ b/devices/stm32h747cm4.yaml @@ -90,4 +90,4 @@ _include: - ../peripherals/sai/sai.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml - - common_patches/h7_ethernet_mac.yaml + - common_patches/h7_mp1_ethernet_mac.yaml diff --git a/devices/stm32h747cm7.yaml b/devices/stm32h747cm7.yaml index b36229dc1..5ca611a41 100644 --- a/devices/stm32h747cm7.yaml +++ b/devices/stm32h747cm7.yaml @@ -95,4 +95,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml - - common_patches/h7_ethernet_mac.yaml + - common_patches/h7_mp1_ethernet_mac.yaml diff --git a/devices/stm32h753.yaml b/devices/stm32h753.yaml index d0ac044e3..998901fa3 100644 --- a/devices/stm32h753.yaml +++ b/devices/stm32h753.yaml @@ -87,4 +87,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml - - common_patches/h7_ethernet_mac.yaml + - common_patches/h7_mp1_ethernet_mac.yaml diff --git a/devices/stm32h753v.yaml b/devices/stm32h753v.yaml index 00036890d..3ba119a87 100644 --- a/devices/stm32h753v.yaml +++ b/devices/stm32h753v.yaml @@ -90,4 +90,4 @@ _include: - ../peripherals/rtc/rtc_h7.yaml - common_patches/h7_crc_addr_fix.yaml - common_patches/h7_wwdg.yaml - - common_patches/h7_ethernet_mac.yaml + - common_patches/h7_mp1_ethernet_mac.yaml diff --git a/devices/stm32mp157.yaml b/devices/stm32mp157.yaml index 40b91622b..4b0f0592f 100644 --- a/devices/stm32mp157.yaml +++ b/devices/stm32mp157.yaml @@ -492,10 +492,10 @@ TIM[1-58]: _add: CCMR1_Output: description: > - The same register can be used for output compare mode (this section) or for input capture - mode (previous section). The direction of a channel is defined by configuring the - corresponding CCxS bits. All the other bits of this register have a different function for input - capture and for output compare modes. It is possible to combine both modes independently + The same register can be used for output compare mode (this section) or for input capture + mode (previous section). The direction of a channel is defined by configuring the + corresponding CCxS bits. All the other bits of this register have a different function for input + capture and for output compare modes. It is possible to combine both modes independently (e.g. channel 1 in input capture mode and channel 2 in output compare mode). access: read-write resetValue: 0x00000000 @@ -626,4 +626,5 @@ _include: - ../devices/common_patches/rename_USART_CR1_M0_field.yaml - ../devices/common_patches/rename_USART_CR3_SCARCNT_field.yaml - ../devices/common_patches/rename_USART_CR2_DATAINV_field.yaml -- common_patches/merge_USART_BRR_fields.yaml \ No newline at end of file +- common_patches/merge_USART_BRR_fields.yaml +- common_patches/h7_mp1_ethernet_mac.yaml