From 586b060d92a5c4e0f00a20e064c172091ba97648 Mon Sep 17 00:00:00 2001 From: Mathias Date: Tue, 21 Dec 2021 14:45:05 +0100 Subject: [PATCH 1/2] STM32L4x5: Add GPIOx ASCR & BRR registers --- devices/common_patches/l4_gpio_ascr_brr.yaml | 20 ++++++++++++++++++++ devices/stm32l4x5.yaml | 10 ++++++++++ 2 files changed, 30 insertions(+) create mode 100644 devices/common_patches/l4_gpio_ascr_brr.yaml diff --git a/devices/common_patches/l4_gpio_ascr_brr.yaml b/devices/common_patches/l4_gpio_ascr_brr.yaml new file mode 100644 index 000000000..0d329b0c8 --- /dev/null +++ b/devices/common_patches/l4_gpio_ascr_brr.yaml @@ -0,0 +1,20 @@ +"GPIO*": + _add: + ASCR: + description: GPIO port analog switch control register + addressOffset: 0x2C + fields: + ASC: + description: These bits are written by software to configure the analog connection of the IOs. + access: read-write + bitOffset: 0 + bitWidth: 16 + BRR: + description: GPIO port bit reset register + addressOffset: 0x28 + fields: + BR: + description: These bits are write-only. A read to these bits returns the value 0x0000 + access: read-only + bitOffset: 0 + bitWidth: 16 \ No newline at end of file diff --git a/devices/stm32l4x5.yaml b/devices/stm32l4x5.yaml index 2c2e2d5fa..5021e658d 100644 --- a/devices/stm32l4x5.yaml +++ b/devices/stm32l4x5.yaml @@ -9,12 +9,21 @@ _modify: ADC_Common: CCR: _modify: + MULT: + name: DUAL + description: Dual ADC mode selection TSEN: name: CH18SEL description: CH18 selection (Vbat) VBATEN: name: CH17SEL description: CH17 selection (temperature) + _add: + PRESC: + description: ADC prescaler + bitOffset: 18 + bitWidth: 4 + access: read-write # Merge the thousands of individal bit fields into a single field for each # CAN filter register. This is not only much easier to use but also saves @@ -179,4 +188,5 @@ _include: - ./common_patches/l4_adc_smpr.yaml - ./common_patches/l4_adc_sqr1.yaml - ./common_patches/l4_spi.yaml + - ./common_patches/l4_gpio_ascr_brr.yaml - ../peripherals/spi/spi_l4.yaml From 96a4fea7ea6db9c50af9d2d4a4f36c0f8f30ca27 Mon Sep 17 00:00:00 2001 From: Mathias Date: Sat, 15 Jan 2022 17:51:16 +0100 Subject: [PATCH 2/2] Split gpio patch into BRR & ASCR files and apply BRR to 4x1, 4x2 & 4x3 aswell. Add enum variants to both files --- ...{l4_gpio_ascr_brr.yaml => l4_gpio_ascr.yaml} | 15 ++++++--------- devices/common_patches/l4_gpio_brr.yaml | 17 +++++++++++++++++ devices/stm32l4x1.yaml | 1 + devices/stm32l4x2.yaml | 1 + devices/stm32l4x3.yaml | 1 + devices/stm32l4x5.yaml | 3 ++- 6 files changed, 28 insertions(+), 10 deletions(-) rename devices/common_patches/{l4_gpio_ascr_brr.yaml => l4_gpio_ascr.yaml} (53%) create mode 100644 devices/common_patches/l4_gpio_brr.yaml diff --git a/devices/common_patches/l4_gpio_ascr_brr.yaml b/devices/common_patches/l4_gpio_ascr.yaml similarity index 53% rename from devices/common_patches/l4_gpio_ascr_brr.yaml rename to devices/common_patches/l4_gpio_ascr.yaml index 0d329b0c8..84602a171 100644 --- a/devices/common_patches/l4_gpio_ascr_brr.yaml +++ b/devices/common_patches/l4_gpio_ascr.yaml @@ -9,12 +9,9 @@ access: read-write bitOffset: 0 bitWidth: 16 - BRR: - description: GPIO port bit reset register - addressOffset: 0x28 - fields: - BR: - description: These bits are write-only. A read to these bits returns the value 0x0000 - access: read-only - bitOffset: 0 - bitWidth: 16 \ No newline at end of file + ASCR: + _split: [ASC] + ASC*: + _write: + NoAction: [0, "Disconnect analog switch to the ADC input"] + Reset: [1, " Connect analog switch to the ADC input"] \ No newline at end of file diff --git a/devices/common_patches/l4_gpio_brr.yaml b/devices/common_patches/l4_gpio_brr.yaml new file mode 100644 index 000000000..b3ea49155 --- /dev/null +++ b/devices/common_patches/l4_gpio_brr.yaml @@ -0,0 +1,17 @@ +"GPIO*": + _add: + BRR: + description: GPIO port bit reset register + addressOffset: 0x28 + fields: + BR: + description: These bits are write-only. A read to these bits returns the value 0x0000 + access: write-only + bitOffset: 0 + bitWidth: 16 + BRR: + _split: [BR] + BR*: + _write: + NoAction: [0, "No action on the corresponding ODx bit"] + Reset: [1, "Reset the corresponding ODx bit"] \ No newline at end of file diff --git a/devices/stm32l4x1.yaml b/devices/stm32l4x1.yaml index 521f42122..14e909678 100644 --- a/devices/stm32l4x1.yaml +++ b/devices/stm32l4x1.yaml @@ -130,4 +130,5 @@ _include: - ./common_patches/l4_adc_smpr.yaml - ./common_patches/l4_adc_sqr1.yaml - ./common_patches/l4_spi.yaml + - ./common_patches/l4_gpio_brr.yaml - ../peripherals/spi/spi_l4.yaml diff --git a/devices/stm32l4x2.yaml b/devices/stm32l4x2.yaml index a6279b9c8..695b61e55 100644 --- a/devices/stm32l4x2.yaml +++ b/devices/stm32l4x2.yaml @@ -9,4 +9,5 @@ MPU: _include: - ./common_patches/stm32l4x2_l412.yaml - common_patches/rtc/rtc_bkpr.yaml + - ./common_patches/l4_gpio_brr.yaml - ../peripherals/fw/fw_l0_l4.yaml diff --git a/devices/stm32l4x3.yaml b/devices/stm32l4x3.yaml index d59ac5cd1..05b4c9ddc 100644 --- a/devices/stm32l4x3.yaml +++ b/devices/stm32l4x3.yaml @@ -161,5 +161,6 @@ _include: - ./common_patches/l4_adc_smpr.yaml - ./common_patches/l4_adc_sqr1.yaml - ./common_patches/l4_spi.yaml + - ./common_patches/l4_gpio_brr.yaml - ../peripherals/spi/spi_l4.yaml - ./common_patches/l4_lcd_segment.yaml diff --git a/devices/stm32l4x5.yaml b/devices/stm32l4x5.yaml index 5021e658d..92affcf63 100644 --- a/devices/stm32l4x5.yaml +++ b/devices/stm32l4x5.yaml @@ -188,5 +188,6 @@ _include: - ./common_patches/l4_adc_smpr.yaml - ./common_patches/l4_adc_sqr1.yaml - ./common_patches/l4_spi.yaml - - ./common_patches/l4_gpio_ascr_brr.yaml + - ./common_patches/l4_gpio_ascr.yaml + - ./common_patches/l4_gpio_brr.yaml - ../peripherals/spi/spi_l4.yaml